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* [PATCH v24 00/12] *AuxCCS handling and render compression modifiers
@ 2026-03-20 17:02 Tvrtko Ursulin
  2026-03-20 17:02 ` [PATCH v24 01/12] drm/xe: Rename XE_BO_FLAG_SCANOUT to XE_BO_FLAG_FORCE_WC Tvrtko Ursulin
                   ` (15 more replies)
  0 siblings, 16 replies; 31+ messages in thread
From: Tvrtko Ursulin @ 2026-03-20 17:02 UTC (permalink / raw)
  To: intel-xe; +Cc: kernel-dev, Uma Shankar, Tvrtko Ursulin, Rodrigo Vivi

A series to add support for compressed surface scanout under xe with
Alderlake-P.

Currently the auxiliary buffer data isn't mapped into the page tables at all so
cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe")
had to disable the support.

On top of that there are missing flushes, invalidations and similar.

Tested with KDE Wayland, on Lenovo Carbon X1 ADL-P:

  [PLANE:32:plane 1A]: type=PRI
          uapi: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=visible, src=2880.000000x1800.000000+0.000000+0.000000, dst=2880x1800+0+0, rotation=0 (0x00000001)
          hw: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=yes, src=2880.000000x1800.000000+0.000000+0.000000, dst=2880x1800+0+0, rotation=0 (0x00000001)

Display working fine - no artefacts, no DMAR/PIPE faults.

All IGTs pass for me locally.

v2:
 * More patches added to fix kms_flip_tiling.

v3:
 * Rebased after some cleanup patches from v2 were merged.
 * Added people to Cc as suggested by Rodrigo.
 * Adjusted last patch title. (Rodrigo)
 * Apply GGTT flushing only to iomapped system memory buffers.

v4:
 * Added patch for potentially misplaced Wa_14016712196.
 * Fixed (hopefully) MAX_JOB_SIZE_DW on Meteorlake.

v5:
 * Split out ring emission changes to smaller patches.
 * Fixed MAX_JOB_SIZE_DW even more.
 * Don't emit MI_FLUSH_DW_CCS on !BCS. This should fix Meteorlake.

 v6:
 * Added AuxCCS invalidation to indirect context workarounds.
 * Also added the indirect context handling and some other workarounds. They are
   unrelated but the series depends on it.
 * Dropped DPT pin alignment reduction since BMG appears not to be liking it for
   some reason.

v7:
 * Rebased on top of recent xe_fb_pin.c refactoring and also the indirect
   context workarounds series.

v8:
 * Rebased for bo->size removal.
 * Corrected PIPE_CONTROL_FLUSH_L3 to bit 30. (Jose)

v9:
 * Fixed fb remapping changes.
 * Dropped two not required patches from the series.
 * Fixed criteria for GGTT flushing.
 * Limit clflush to the compression metadata area.
 * Rebased for indirect context workarounds landing upstream.

v10:
 * Rebase for XE_GT_WA().

v11:
 * Do not use stolen for DPT on IGFX + AuxCCS.

v12:
 * Rebased for some ringbuf and LRC code changes.

v13:
 * Rebased for various upstream changes.
 * Dropped clflush and stolen avoidance patches after merging IGT MOCS 61 usage.

 v14:
 * MMIO 0x4248 and MI_FLUSH_DW_CCS are MTL+. (Matt)
 * Consolidate engine feature checks. (Ville)
 * Brought back the patch to put DPT tables in system memory for 100% CI pass
   rate. It looks like MOCS 61 is not enough to avoid sporadic pipecrc
   mismatches.

v15:
 * Limited to enabling on Alderlake-P only. (Dropped all Meteorlake patches.)
 * Dropped unrelated GGTT alignment fix. (Sent standalone.)
 * Use display parent interface for probing AuxCCS driver support.

v16:
 * Use write-combine for DPT in stolen memory. (Ville)
 * Dropped clflush patches under assumption pre-production ADL machine were the
   reason for sporadic pipecrc failures.

v17:
 * Mechanical rebase for upstream conflicts.

v18:
 * Added a patch to rename XE_BO_FLAG_SCANOUT to XE_BO_FLAG_FORCE_WC. (Rodrigo)
 * Instead of exporting a helper function for emitting the aux invalidation
   into the ring, add it to the ring ops vfunc table. (Matthew)

v19:
 * Tweaked comments and removed some stray hunks from v17.

v20:
 * Include <linux/types.h> for u32.

v21:
 * Forward declare struct xe_gt to fix standalone headers test.

v22:
 * Split up "drm/xe/display: Add support for AuxCCS" into four patches for
   easier review.

v23:
 * Fixed rebase error made in v22 when splitting up the patches.

v24:
 * Fixed flag confusion in "drm/xe: Rename XE_BO_FLAG_SCANOUT to XE_BO_FLAG_FORCE_WC".
 * Applied r-b's.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>

Tvrtko Ursulin (12):
  drm/xe: Rename XE_BO_FLAG_SCANOUT to XE_BO_FLAG_FORCE_WC
  drm/xe: Use write-combine mapping when populating DPT
  drm/xe/xelpg: Limit AuxCCS ring buffer programming to Alderlake
  drm/xe/xelp: Quiesce memory traffic before invalidating AuxCCS
  drm/xe/xelp: Wait for AuxCCS invalidation to complete
  drm/xe: Move aux table invalidation to ring ops
  drm/xe/xelp: Add AuxCCS invalidation to the indirect context
    workarounds
  drm/xe/display: Move remapped plane loop out of __xe_pin_fb_vma_dpt
  drm/xe/display: Change write_dpt_remapped_tiled function signature
  drm/xe/display: Respect remapped plane alignment
  drm/xe/display: Add support for AuxCCS
  drm/xe/xelp: Expose AuxCCS frame buffer modifiers on Alderlake-P

 drivers/gpu/drm/xe/display/intel_fbdev_fb.c   |  12 +-
 drivers/gpu/drm/xe/display/xe_display.c       |   8 ++
 drivers/gpu/drm/xe/display/xe_display_bo.c    |   6 +-
 drivers/gpu/drm/xe/display/xe_dsb_buffer.c    |   4 +-
 drivers/gpu/drm/xe/display/xe_fb_pin.c        | 116 +++++++++++++-----
 drivers/gpu/drm/xe/display/xe_initial_plane.c |   2 +-
 .../gpu/drm/xe/instructions/xe_mi_commands.h  |   6 +
 drivers/gpu/drm/xe/xe_bo.c                    |  15 +--
 drivers/gpu/drm/xe/xe_bo.h                    |   2 +-
 drivers/gpu/drm/xe/xe_lrc.c                   |  23 ++++
 drivers/gpu/drm/xe/xe_ring_ops.c              | 106 ++++++++++++----
 drivers/gpu/drm/xe/xe_ring_ops_types.h        |   8 +-
 12 files changed, 237 insertions(+), 71 deletions(-)

-- 
2.52.0


^ permalink raw reply	[flat|nested] 31+ messages in thread
* [PATCH v25 00/12] AuxCCS handling and render compression modifiers
@ 2026-03-24  8:40 Tvrtko Ursulin
  2026-03-24 18:53 ` ✗ Xe.CI.FULL: failure for " Patchwork
  0 siblings, 1 reply; 31+ messages in thread
From: Tvrtko Ursulin @ 2026-03-24  8:40 UTC (permalink / raw)
  To: intel-xe; +Cc: kernel-dev, Uma Shankar, Tvrtko Ursulin, Rodrigo Vivi

A series to add support for compressed surface scanout under xe with
Alderlake-P.

Currently the auxiliary buffer data isn't mapped into the page tables at all so
cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe")
had to disable the support.

On top of that there are missing flushes, invalidations and similar.

Tested with KDE Wayland, on Lenovo Carbon X1 ADL-P:

  [PLANE:32:plane 1A]: type=PRI
          uapi: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=visible, src=2880.000000x1800.000000+0.000000+0.000000, dst=2880x1800+0+0, rotation=0 (0x00000001)
          hw: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=yes, src=2880.000000x1800.000000+0.000000+0.000000, dst=2880x1800+0+0, rotation=0 (0x00000001)

Display working fine - no artefacts, no DMAR/PIPE faults.

All IGTs pass for me locally.

v2:
 * More patches added to fix kms_flip_tiling.

v3:
 * Rebased after some cleanup patches from v2 were merged.
 * Added people to Cc as suggested by Rodrigo.
 * Adjusted last patch title. (Rodrigo)
 * Apply GGTT flushing only to iomapped system memory buffers.

v4:
 * Added patch for potentially misplaced Wa_14016712196.
 * Fixed (hopefully) MAX_JOB_SIZE_DW on Meteorlake.

v5:
 * Split out ring emission changes to smaller patches.
 * Fixed MAX_JOB_SIZE_DW even more.
 * Don't emit MI_FLUSH_DW_CCS on !BCS. This should fix Meteorlake.

 v6:
 * Added AuxCCS invalidation to indirect context workarounds.
 * Also added the indirect context handling and some other workarounds. They are
   unrelated but the series depends on it.
 * Dropped DPT pin alignment reduction since BMG appears not to be liking it for
   some reason.

v7:
 * Rebased on top of recent xe_fb_pin.c refactoring and also the indirect
   context workarounds series.

v8:
 * Rebased for bo->size removal.
 * Corrected PIPE_CONTROL_FLUSH_L3 to bit 30. (Jose)

v9:
 * Fixed fb remapping changes.
 * Dropped two not required patches from the series.
 * Fixed criteria for GGTT flushing.
 * Limit clflush to the compression metadata area.
 * Rebased for indirect context workarounds landing upstream.

v10:
 * Rebase for XE_GT_WA().

v11:
 * Do not use stolen for DPT on IGFX + AuxCCS.

v12:
 * Rebased for some ringbuf and LRC code changes.

v13:
 * Rebased for various upstream changes.
 * Dropped clflush and stolen avoidance patches after merging IGT MOCS 61 usage.

 v14:
 * MMIO 0x4248 and MI_FLUSH_DW_CCS are MTL+. (Matt)
 * Consolidate engine feature checks. (Ville)
 * Brought back the patch to put DPT tables in system memory for 100% CI pass
   rate. It looks like MOCS 61 is not enough to avoid sporadic pipecrc
   mismatches.

v15:
 * Limited to enabling on Alderlake-P only. (Dropped all Meteorlake patches.)
 * Dropped unrelated GGTT alignment fix. (Sent standalone.)
 * Use display parent interface for probing AuxCCS driver support.

v16:
 * Use write-combine for DPT in stolen memory. (Ville)
 * Dropped clflush patches under assumption pre-production ADL machine were the
   reason for sporadic pipecrc failures.

v17:
 * Mechanical rebase for upstream conflicts.

v18:
 * Added a patch to rename XE_BO_FLAG_SCANOUT to XE_BO_FLAG_FORCE_WC. (Rodrigo)
 * Instead of exporting a helper function for emitting the aux invalidation
   into the ring, add it to the ring ops vfunc table. (Matthew)

v19:
 * Tweaked comments and removed some stray hunks from v17.

v20:
 * Include <linux/types.h> for u32.

v21:
 * Forward declare struct xe_gt to fix standalone headers test.

v22:
 * Split up "drm/xe/display: Add support for AuxCCS" into four patches for
   easier review.

v23:
 * Fixed rebase error made in v22 when splitting up the patches.

v24:
 * Fixed flag confusion in "drm/xe: Rename XE_BO_FLAG_SCANOUT to XE_BO_FLAG_FORCE_WC".
 * Applied r-b's.

v25:
 * Rebased for upstream conflict and tidied some checkpatch warnings added in
   the patch split.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>

Tvrtko Ursulin (12):
  drm/xe: Rename XE_BO_FLAG_SCANOUT to XE_BO_FLAG_FORCE_WC
  drm/xe: Use write-combine mapping when populating DPT
  drm/xe/xelpg: Limit AuxCCS ring buffer programming to Alderlake
  drm/xe/xelp: Quiesce memory traffic before invalidating AuxCCS
  drm/xe/xelp: Wait for AuxCCS invalidation to complete
  drm/xe: Move aux table invalidation to ring ops
  drm/xe/xelp: Add AuxCCS invalidation to the indirect context
    workarounds
  drm/xe/display: Move remapped plane loop out of __xe_pin_fb_vma_dpt
  drm/xe/display: Change write_dpt_remapped_tiled function signature
  drm/xe/display: Respect remapped plane alignment
  drm/xe/display: Add support for AuxCCS
  drm/xe/xelp: Expose AuxCCS frame buffer modifiers on Alderlake-P

 drivers/gpu/drm/xe/display/intel_fbdev_fb.c   |  12 +-
 drivers/gpu/drm/xe/display/xe_display.c       |   8 ++
 drivers/gpu/drm/xe/display/xe_display_bo.c    |   6 +-
 drivers/gpu/drm/xe/display/xe_dsb_buffer.c    |   4 +-
 drivers/gpu/drm/xe/display/xe_fb_pin.c        | 116 +++++++++++++-----
 drivers/gpu/drm/xe/display/xe_initial_plane.c |   2 +-
 .../gpu/drm/xe/instructions/xe_mi_commands.h  |   6 +
 drivers/gpu/drm/xe/xe_bo.c                    |  17 +--
 drivers/gpu/drm/xe/xe_bo.h                    |   2 +-
 drivers/gpu/drm/xe/xe_lrc.c                   |  23 ++++
 drivers/gpu/drm/xe/xe_ring_ops.c              | 106 ++++++++++++----
 drivers/gpu/drm/xe/xe_ring_ops_types.h        |   8 +-
 12 files changed, 238 insertions(+), 72 deletions(-)

-- 
2.52.0


^ permalink raw reply	[flat|nested] 31+ messages in thread
* [PATCH v23 00/12] AuxCCS handling and render compression modifiers
@ 2026-03-19 10:06 Tvrtko Ursulin
  2026-03-20 11:38 ` ✗ Xe.CI.FULL: failure for " Patchwork
  0 siblings, 1 reply; 31+ messages in thread
From: Tvrtko Ursulin @ 2026-03-19 10:06 UTC (permalink / raw)
  To: intel-xe; +Cc: kernel-dev, Uma Shankar, Tvrtko Ursulin, Rodrigo Vivi

A series to add support for compressed surface scanout under xe with
Alderlake-P.

Currently the auxiliary buffer data isn't mapped into the page tables at all so
cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe")
had to disable the support.

On top of that there are missing flushes, invalidations and similar.

Tested with KDE Wayland, on Lenovo Carbon X1 ADL-P:

  [PLANE:32:plane 1A]: type=PRI
          uapi: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=visible, src=2880.000000x1800.000000+0.000000+0.000000, dst=2880x1800+0+0, rotation=0 (0x00000001)
          hw: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=yes, src=2880.000000x1800.000000+0.000000+0.000000, dst=2880x1800+0+0, rotation=0 (0x00000001)

Display working fine - no artefacts, no DMAR/PIPE faults.

All IGTs pass for me locally.

v2:
 * More patches added to fix kms_flip_tiling.

v3:
 * Rebased after some cleanup patches from v2 were merged.
 * Added people to Cc as suggested by Rodrigo.
 * Adjusted last patch title. (Rodrigo)
 * Apply GGTT flushing only to iomapped system memory buffers.

v4:
 * Added patch for potentially misplaced Wa_14016712196.
 * Fixed (hopefully) MAX_JOB_SIZE_DW on Meteorlake.

v5:
 * Split out ring emission changes to smaller patches.
 * Fixed MAX_JOB_SIZE_DW even more.
 * Don't emit MI_FLUSH_DW_CCS on !BCS. This should fix Meteorlake.

 v6:
 * Added AuxCCS invalidation to indirect context workarounds.
 * Also added the indirect context handling and some other workarounds. They are
   unrelated but the series depends on it.
 * Dropped DPT pin alignment reduction since BMG appears not to be liking it for
   some reason.

v7:
 * Rebased on top of recent xe_fb_pin.c refactoring and also the indirect
   context workarounds series.

v8:
 * Rebased for bo->size removal.
 * Corrected PIPE_CONTROL_FLUSH_L3 to bit 30. (Jose)

v9:
 * Fixed fb remapping changes.
 * Dropped two not required patches from the series.
 * Fixed criteria for GGTT flushing.
 * Limit clflush to the compression metadata area.
 * Rebased for indirect context workarounds landing upstream.

v10:
 * Rebase for XE_GT_WA().

v11:
 * Do not use stolen for DPT on IGFX + AuxCCS.

v12:
 * Rebased for some ringbuf and LRC code changes.

v13:
 * Rebased for various upstream changes.
 * Dropped clflush and stolen avoidance patches after merging IGT MOCS 61 usage.

 v14:
 * MMIO 0x4248 and MI_FLUSH_DW_CCS are MTL+. (Matt)
 * Consolidate engine feature checks. (Ville)
 * Brought back the patch to put DPT tables in system memory for 100% CI pass
   rate. It looks like MOCS 61 is not enough to avoid sporadic pipecrc
   mismatches.

v15:
 * Limited to enabling on Alderlake-P only. (Dropped all Meteorlake patches.)
 * Dropped unrelated GGTT alignment fix. (Sent standalone.)
 * Use display parent interface for probing AuxCCS driver support.

v16:
 * Use write-combine for DPT in stolen memory. (Ville)
 * Dropped clflush patches under assumption pre-production ADL machine were the
   reason for sporadic pipecrc failures.

v17:
 * Mechanical rebase for upstream conflicts.

v18:
 * Added a patch to rename XE_BO_FLAG_SCANOUT to XE_BO_FLAG_FORCE_WC. (Rodrigo)
 * Instead of exporting a helper function for emitting the aux invalidation
   into the ring, add it to the ring ops vfunc table. (Matthew)

v19:
 * Tweaked comments and removed some stray hunks from v17.

v20:
 * Include <linux/types.h> for u32.

v21:
 * Forward declare struct xe_gt to fix standalone headers test.

v22:
 * Split up "drm/xe/display: Add support for AuxCCS" into four patches for
   easier review.

v23:
 * Fixed rebase error made in v22 when splitting up the patches.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>

Tvrtko Ursulin (12):
  drm/xe: Rename XE_BO_FLAG_SCANOUT to XE_BO_FLAG_FORCE_WC
  drm/xe: Use write-combine mapping when populating DPT
  drm/xe/xelpg: Limit AuxCCS ring buffer programming to Alderlake
  drm/xe/xelp: Quiesce memory traffic before invalidating AuxCCS
  drm/xe/xelp: Wait for AuxCCS invalidation to complete
  drm/xe: Move aux table invalidation to ring ops
  drm/xe/xelp: Add AuxCCS invalidation to the indirect context
    workarounds
  drm/xe/display: Move remapped plane loop out of __xe_pin_fb_vma_dpt
  drm/xe/display: Change write_dpt_remapped_tiled function signature
  drm/xe/display: Respect remapped plane alignment
  drm/xe/display: Add support for AuxCCS
  drm/xe/xelp: Expose AuxCCS frame buffer modifiers on Alderlake-P

 drivers/gpu/drm/xe/display/intel_fbdev_fb.c   |  12 +-
 drivers/gpu/drm/xe/display/xe_display.c       |   8 ++
 drivers/gpu/drm/xe/display/xe_display_bo.c    |   6 +-
 drivers/gpu/drm/xe/display/xe_dsb_buffer.c    |   4 +-
 drivers/gpu/drm/xe/display/xe_fb_pin.c        | 116 +++++++++++++-----
 drivers/gpu/drm/xe/display/xe_initial_plane.c |   2 +-
 .../gpu/drm/xe/instructions/xe_mi_commands.h  |   6 +
 drivers/gpu/drm/xe/xe_bo.c                    |  15 +--
 drivers/gpu/drm/xe/xe_bo.h                    |   2 +-
 drivers/gpu/drm/xe/xe_lrc.c                   |  23 ++++
 drivers/gpu/drm/xe/xe_ring_ops.c              | 106 ++++++++++++----
 drivers/gpu/drm/xe/xe_ring_ops_types.h        |   8 +-
 12 files changed, 237 insertions(+), 71 deletions(-)

-- 
2.52.0


^ permalink raw reply	[flat|nested] 31+ messages in thread
* [PATCH v16 0/8] AuxCCS handling and render compression modifiers
@ 2025-12-16 15:37 Tvrtko Ursulin
  2025-12-17 21:57 ` ✗ Xe.CI.Full: failure for " Patchwork
  0 siblings, 1 reply; 31+ messages in thread
From: Tvrtko Ursulin @ 2025-12-16 15:37 UTC (permalink / raw)
  To: intel-xe; +Cc: kernel-dev, Tvrtko Ursulin, Rodrigo Vivi

A series to add support for compressed surface scanout under xe with
Alderlake-P.

Currently the auxiliary buffer data isn't mapped into the page tables at all so
cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe")
had to disable the support.

On top of that there are missing flushes, invalidations and similar.

Tested with KDE Wayland, on Lenovo Carbon X1 ADL-P:

  [PLANE:32:plane 1A]: type=PRI
          uapi: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=visible, src=2880.000000x1800.000000+0.000000+0.000000, dst=2880x1800+0+0, rotation=0 (0x00000001)
          hw: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=yes, src=2880.000000x1800.000000+0.000000+0.000000, dst=2880x1800+0+0, rotation=0 (0x00000001)

Display working fine - no artefacts, no DMAR/PIPE faults.

All IGTs pass for me locally.

v2:
 * More patches added to fix kms_flip_tiling.

v3:
 * Rebased after some cleanup patches from v2 were merged.
 * Added people to Cc as suggested by Rodrigo.
 * Adjusted last patch title. (Rodrigo)
 * Apply GGTT flushing only to iomapped system memory buffers.

v4:
 * Added patch for potentially misplaced Wa_14016712196.
 * Fixed (hopefully) MAX_JOB_SIZE_DW on Meteorlake.

v5:
 * Split out ring emission changes to smaller patches.
 * Fixed MAX_JOB_SIZE_DW even more.
 * Don't emit MI_FLUSH_DW_CCS on !BCS. This should fix Meteorlake.

 v6:
 * Added AuxCCS invalidation to indirect context workarounds.
 * Also added the indirect context handling and some other workarounds. They are
   unrelated but the series depends on it.
 * Dropped DPT pin alignment reduction since BMG appears not to be liking it for
   some reason.

v7:
 * Rebased on top of recent xe_fb_pin.c refactoring and also the indirect
   context workarounds series.

v8:
 * Rebased for bo->size removal.
 * Corrected PIPE_CONTROL_FLUSH_L3 to bit 30. (Jose)

v9:
 * Fixed fb remapping changes.
 * Dropped two not required patches from the series.
 * Fixed criteria for GGTT flushing.
 * Limit clflush to the compression metadata area.
 * Rebased for indirect context workarounds landing upstream.

v10:
 * Rebase for XE_GT_WA().

v11:
 * Do not use stolen for DPT on IGFX + AuxCCS.

v12:
 * Rebased for some ringbuf and LRC code changes.

v13:
 * Rebased for various upstream changes.
 * Dropped clflush and stolen avoidance patches after merging IGT MOCS 61 usage.

 v14:
 * MMIO 0x4248 and MI_FLUSH_DW_CCS are MTL+. (Matt)
 * Consolidate engine feature checks. (Ville)
 * Brought back the patch to put DPT tables in system memory for 100% CI pass
   rate. It looks like MOCS 61 is not enough to avoid sporadic pipecrc
   mismatches.

v15:
 * Limited to enabling on Alderlake-P only. (Dropped all Meteorlake patches.)
 * Dropped unrelated GGTT alignment fix. (Sent standalone.)
 * Use display parent interface for probing AuxCCS driver support.

v16:
 * Use write-combine for DPT in stolen memory. (Ville)
 * Dropped clflush patches under assumption pre-production ADL machine were the
   reason for sporadic pipecrc failures.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>

Tvrtko Ursulin (8):
  drm/xe: Use write-combine mapping when populating DPT
  drm/xe/xelpg: Limit AuxCCS ring buffer programming to Alderlake
  drm/xe/xelp: Quiesce memory traffic before invalidating AuxCCS
  drm/xe/xelp: Wait for AuxCCS invalidation to complete
  drm/xe: Export xe_emit_aux_table_inv
  drm/xe/xelp: Add AuxCCS invalidation to the indirect context
    workarounds
  drm/xe/display: Add support for AuxCCS
  drm/xe/xelp: Expose AuxCCS frame buffer modifiers on Alderlake-P

 drivers/gpu/drm/xe/display/xe_display.c       |   8 ++
 drivers/gpu/drm/xe/display/xe_fb_pin.c        | 114 +++++++++++++-----
 .../gpu/drm/xe/instructions/xe_mi_commands.h  |   6 +
 drivers/gpu/drm/xe/xe_hw_engine.h             |  24 ++++
 drivers/gpu/drm/xe/xe_lrc.c                   |  27 +++++
 drivers/gpu/drm/xe/xe_ring_ops.c              |  84 ++++++++-----
 drivers/gpu/drm/xe/xe_ring_ops.h              |   3 +
 drivers/gpu/drm/xe/xe_ring_ops_types.h        |   2 +-
 8 files changed, 206 insertions(+), 62 deletions(-)

-- 
2.51.1


^ permalink raw reply	[flat|nested] 31+ messages in thread
* [PATCH v15 00/10] AuxCCS handling and render compression modifiers
@ 2025-12-08 19:17 Tvrtko Ursulin
  2025-12-09  3:28 ` ✗ Xe.CI.Full: failure for " Patchwork
  0 siblings, 1 reply; 31+ messages in thread
From: Tvrtko Ursulin @ 2025-12-08 19:17 UTC (permalink / raw)
  To: intel-xe; +Cc: kernel-dev, Tvrtko Ursulin, Rodrigo Vivi

From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>

A series to add support for compressed surface scanout under xe with
Alderlake-P.

Currently the auxiliary buffer data isn't mapped into the page tables at all so
cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe")
had to disable the support.

On top of that there are missing flushes, invalidations and similar.

Tested with KDE Wayland, on Lenovo Carbon X1 ADL-P:

  [PLANE:32:plane 1A]: type=PRI
          uapi: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=visible, src=2880.000000x1800.000000+0.000000+0.000000, dst=2880x1800+0+0, rotation=0 (0x00000001)
          hw: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=yes, src=2880.000000x1800.000000+0.000000+0.000000, dst=2880x1800+0+0, rotation=0 (0x00000001)

Display working fine - no artefacts, no DMAR/PIPE faults.

All IGTs pass for me locally.

v2:
 * More patches added to fix kms_flip_tiling.

v3:
 * Rebased after some cleanup patches from v2 were merged.
 * Added people to Cc as suggested by Rodrigo.
 * Adjusted last patch title. (Rodrigo)
 * Apply GGTT flushing only to iomapped system memory buffers.

v4:
 * Added patch for potentially misplaced Wa_14016712196.
 * Fixed (hopefully) MAX_JOB_SIZE_DW on Meteorlake.

v5:
 * Split out ring emission changes to smaller patches.
 * Fixed MAX_JOB_SIZE_DW even more.
 * Don't emit MI_FLUSH_DW_CCS on !BCS. This should fix Meteorlake.

 v6:
 * Added AuxCCS invalidation to indirect context workarounds.
 * Also added the indirect context handling and some other workarounds. They are
   unrelated but the series depends on it.
 * Dropped DPT pin alignment reduction since BMG appears not to be liking it for
   some reason.

v7:
 * Rebased on top of recent xe_fb_pin.c refactoring and also the indirect
   context workarounds series.

v8:
 * Rebased for bo->size removal.
 * Corrected PIPE_CONTROL_FLUSH_L3 to bit 30. (Jose)

v9:
 * Fixed fb remapping changes.
 * Dropped two not required patches from the series.
 * Fixed criteria for GGTT flushing.
 * Limit clflush to the compression metadata area.
 * Rebased for indirect context workarounds landing upstream.

v10:
 * Rebase for XE_GT_WA().

v11:
 * Do not use stolen for DPT on IGFX + AuxCCS.

v12:
 * Rebased for some ringbuf and LRC code changes.

v13:
 * Rebased for various upstream changes.
 * Dropped clflush and stolen avoidance patches after merging IGT MOCS 61 usage.

 v14:
 * MMIO 0x4248 and MI_FLUSH_DW_CCS are MTL+. (Matt)
 * Consolidate engine feature checks. (Ville)
 * Brought back the patch to put DPT tables in system memory for 100% CI pass
   rate. It looks like MOCS 61 is not enough to avoid sporadic pipecrc
   mismatches.

v15:
 * Limited to enabling on Alderlake-P only. (Dropped all Meteorlake patches.)
 * Dropped unrelated GGTT alignment fix. (Sent standalone.)
 * Use display parent interface for probing AuxCCS driver support.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>

Tvrtko Ursulin (10):
  drm/xe/xelpg: Limit AuxCCS ring buffer programming to Alderlake
  drm/xe/xelp: Quiesce memory traffic before invalidating AuxCCS
  drm/xe/xelp: Wait for AuxCCS invalidation to complete
  drm/xe: Export xe_emit_aux_table_inv
  drm/xe/xelp: Add AuxCCS invalidation to the indirect context
    workarounds
  drm/xe: Handle DPT in system memory
  drm/xe: Do not use stolen memory for DPT on IGFX and AuxCCS
  drm/xe/display: Add support for AuxCCS
  drm/i915/display: Detect AuxCCS support via display parent interface
  drm/xe/xelp: Expose AuxCCS frame buffer modifiers on Alderlake-P

 .../drm/i915/display/intel_display_device.h   |   1 -
 drivers/gpu/drm/i915/display/intel_fb.c       |   3 +-
 drivers/gpu/drm/i915/display/intel_parent.c   |   5 +
 drivers/gpu/drm/i915/display/intel_parent.h   |   2 +
 .../drm/i915/display/skl_universal_plane.c    |   9 +-
 drivers/gpu/drm/i915/i915_driver.c            |  10 ++
 drivers/gpu/drm/xe/display/xe_display.c       |   8 ++
 drivers/gpu/drm/xe/display/xe_fb_pin.c        | 131 +++++++++++++-----
 .../gpu/drm/xe/instructions/xe_mi_commands.h  |   6 +
 drivers/gpu/drm/xe/xe_hw_engine.h             |  24 ++++
 drivers/gpu/drm/xe/xe_lrc.c                   |  27 ++++
 drivers/gpu/drm/xe/xe_ring_ops.c              |  84 +++++++----
 drivers/gpu/drm/xe/xe_ring_ops.h              |   3 +
 drivers/gpu/drm/xe/xe_ring_ops_types.h        |   2 +-
 include/drm/intel/display_parent_interface.h  |   3 +
 15 files changed, 247 insertions(+), 71 deletions(-)

-- 
2.52.0


^ permalink raw reply	[flat|nested] 31+ messages in thread
* [PATCH v14 00/13] AuxCCS handling and render compression modifiers
@ 2025-10-24 10:47 Tvrtko Ursulin
  2025-10-24 23:57 ` ✗ Xe.CI.Full: failure for " Patchwork
  0 siblings, 1 reply; 31+ messages in thread
From: Tvrtko Ursulin @ 2025-10-24 10:47 UTC (permalink / raw)
  To: intel-xe; +Cc: kernel-dev, Tvrtko Ursulin

A series to fix and add xe support for AuxCSS framebuffers via DPT.

Currently the auxiliary buffer data isn't mapped into the page tables at all so
cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe")
had to disable the support.

On top of that there are missing flushes, invalidations and similar.

Tested with KDE Wayland, on Lenovo Carbon X1 ADL-P:

  [PLANE:32:plane 1A]: type=PRI
          uapi: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=visible, src=2880.000000x1800.000000+0.000000+0.000000, dst=2880x1800+0+0, rotation=0 (0x00000001)
          hw: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=yes, src=2880.000000x1800.000000+0.000000+0.000000, dst=2880x1800+0+0, rotation=0 (0x00000001)

Display working fine - no artefacts, no DMAR/PIPE faults.

All IGTs pass for me locally.

v2:
 * More patches added to fix kms_flip_tiling.

v3:
 * Rebased after some cleanup patches from v2 were merged.
 * Added people to Cc as suggested by Rodrigo.
 * Adjusted last patch title. (Rodrigo)
 * Apply GGTT flushing only to iomapped system memory buffers.

v4:
 * Added patch for potentially misplaced Wa_14016712196.
 * Fixed (hopefully) MAX_JOB_SIZE_DW on Meteorlake.

v5:
 * Split out ring emission changes to smaller patches.
 * Fixed MAX_JOB_SIZE_DW even more.
 * Don't emit MI_FLUSH_DW_CCS on !BCS. This should fix Meteorlake.

 v6:
 * Added AuxCCS invalidation to indirect context workarounds.
 * Also added the indirect context handling and some other workarounds. They are
   unrelated but the series depends on it.
 * Dropped DPT pin alignment reduction since BMG appears not to be liking it for
   some reason.

v7:
 * Rebased on top of recent xe_fb_pin.c refactoring and also the indirect
   context workarounds series.

v8:
 * Rebased for bo->size removal.
 * Corrected PIPE_CONTROL_FLUSH_L3 to bit 30. (Jose)

v9:
 * Fixed fb remapping changes.
 * Dropped two not required patches from the series.
 * Fixed criteria for GGTT flushing.
 * Limit clflush to the compression metadata area.
 * Rebased for indirect context workarounds landing upstream.

v10:
 * Rebase for XE_GT_WA().

v11:
 * Do not use stolen for DPT on IGFX + AuxCCS.

v12:
 * Rebased for some ringbuf and LRC code changes.

v13:
 * Rebased for various upstream changes.
 * Dropped clflush and stolen avoidance patches after merging IGT MOCS 61 usage.

 v14:
 * MMIO 0x4248 and MI_FLUSH_DW_CCS are MTL+. (Matt)
 * Consolidate engine feature checks. (Ville)
 * Brought back the patch to put DPT tables in system memory for 100% CI pass
   rate. It looks like MOCS 61 is not enough to avoid sporadic pipecrc
   mismatches.

Tvrtko Ursulin (13):
  drm/xe: Fix ggtt fb alignment
  drm/xe/xelpg: Flush CCS when flushing caches
  drm/xe/xelp: Quiesce memory traffic before invalidating AuxCCS
  drm/xe/xelp: Support auxccs invalidation on blitter
  drm/xe/xelp: Use MI_FLUSH_DW_CCS on auxccs platforms
  drm/xe/xelp: Wait for AuxCCS invalidation to complete
  drm/xe: Export xe_emit_aux_table_inv
  drm/xe/xelp: Add AuxCCS invalidation to the indirect context
    workarounds
  drm/xe: Flush GGTT writes after populating DPT
  drm/xe: Handle DPT in system memory
  drm/xe: Do not use stolen memory for DPT on IGFX and AuxCCS
  drm/xe/display: Add support for AuxCCS
  drm/i915/display: Expose AuxCCS frame buffer modifiers for Xe

 .../drm/i915/display/skl_universal_plane.c    |   6 -
 drivers/gpu/drm/xe/display/xe_fb_pin.c        | 177 ++++++++++++++---
 .../gpu/drm/xe/instructions/xe_gpu_commands.h |   1 +
 .../gpu/drm/xe/instructions/xe_mi_commands.h  |   6 +
 drivers/gpu/drm/xe/regs/xe_gt_regs.h          |   1 +
 drivers/gpu/drm/xe/xe_hw_engine.h             |  27 +++
 drivers/gpu/drm/xe/xe_lrc.c                   |  27 +++
 drivers/gpu/drm/xe/xe_ring_ops.c              | 183 +++++++++---------
 drivers/gpu/drm/xe/xe_ring_ops.h              |   3 +
 drivers/gpu/drm/xe/xe_ring_ops_types.h        |   2 +-
 10 files changed, 299 insertions(+), 134 deletions(-)

-- 
2.48.0


^ permalink raw reply	[flat|nested] 31+ messages in thread
* [PATCH v13 00/12] AuxCCS handling and render compression modifiers
@ 2025-10-20  7:58 Tvrtko Ursulin
  2025-10-20 14:52 ` ✗ Xe.CI.Full: failure for " Patchwork
  0 siblings, 1 reply; 31+ messages in thread
From: Tvrtko Ursulin @ 2025-10-20  7:58 UTC (permalink / raw)
  To: intel-xe; +Cc: kernel-dev, Tvrtko Ursulin

A series to fix and add xe support for AuxCSS framebuffers via DPT.

Currently the auxiliary buffer data isn't mapped into the page tables at all so
cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe")
had to disable the support.

On top of that there are missing flushes, invalidations and similar.

Tested with KDE Wayland, on Lenovo Carbon X1 ADL-P:

  [PLANE:32:plane 1A]: type=PRI
          uapi: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=visible, src=2880.000000x1800.000000+0.000000+0.000000, dst=2880x1800+0+0, rotation=0 (0x00000001)
          hw: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=yes, src=2880.000000x1800.000000+0.000000+0.000000, dst=2880x1800+0+0, rotation=0 (0x00000001)

Display working fine - no artefacts, no DMAR/PIPE faults.

All IGTs pass for me locally.

v2:
 * More patches added to fix kms_flip_tiling.

v3:
 * Rebased after some cleanup patches from v2 were merged.
 * Added people to Cc as suggested by Rodrigo.
 * Adjusted last patch title. (Rodrigo)
 * Apply GGTT flushing only to iomapped system memory buffers.

v4:
 * Added patch for potentially misplaced Wa_14016712196.
 * Fixed (hopefully) MAX_JOB_SIZE_DW on Meteorlake.

v5:
 * Split out ring emission changes to smaller patches.
 * Fixed MAX_JOB_SIZE_DW even more.
 * Don't emit MI_FLUSH_DW_CCS on !BCS. This should fix Meteorlake.

 v6:
 * Added AuxCCS invalidation to indirect context workarounds.
 * Also added the indirect context handling and some other workarounds. They are
   unrelated but the series depends on it.
 * Dropped DPT pin alignment reduction since BMG appears not to be liking it for
   some reason.

v7:
 * Rebased on top of recent xe_fb_pin.c refactoring and also the indirect
   context workarounds series.

v8:
 * Rebased for bo->size removal.
 * Corrected PIPE_CONTROL_FLUSH_L3 to bit 30. (Jose)

v9:
 * Fixed fb remapping changes.
 * Dropped two not required patches from the series.
 * Fixed criteria for GGTT flushing.
 * Limit clflush to the compression metadata area.
 * Rebased for indirect context workarounds landing upstream.

v10:
 * Rebase for XE_GT_WA().

v11:
 * Do not use stolen for DPT on IGFX + AuxCCS.

v12:
 * Rebased for some ringbuf and LRC code changes.

v13:
 * Rebased for various upstream changes.
 * Dropped clflush and stolen avoidance patches after merging IGT MOCS 61 usage.

Tvrtko Ursulin (12):
  drm/xe: Fix ggtt fb alignment
  drm/xe/xelpg: Flush CCS when flushing caches
  drm/xe/xelp: Quiesce memory traffic before invalidating AuxCCS
  drm/xe/xelp: Support auxccs invalidation on blitter
  drm/xe/xelp: Use MI_FLUSH_DW_CCS on auxccs platforms
  drm/xe/xelp: Wait for AuxCCS invalidation to complete
  drm/xe: Export xe_emit_aux_table_inv
  drm/xe/xelp: Add AuxCCS invalidation to the indirect context
    workarounds
  drm/xe: Flush GGTT writes after populating DPT
  drm/xe: Handle DPT in system memory
  drm/xe/display: Add support for AuxCCS
  drm/i915/display: Expose AuxCCS frame buffer modifiers for Xe

 .../drm/i915/display/skl_universal_plane.c    |   6 -
 drivers/gpu/drm/xe/display/xe_fb_pin.c        | 159 +++++++++++++---
 .../gpu/drm/xe/instructions/xe_gpu_commands.h |   1 +
 .../gpu/drm/xe/instructions/xe_mi_commands.h  |   6 +
 drivers/gpu/drm/xe/regs/xe_gt_regs.h          |   1 +
 drivers/gpu/drm/xe/xe_lrc.c                   |  38 ++++
 drivers/gpu/drm/xe/xe_ring_ops.c              | 178 +++++++++---------
 drivers/gpu/drm/xe/xe_ring_ops.h              |   3 +
 drivers/gpu/drm/xe/xe_ring_ops_types.h        |   2 +-
 9 files changed, 272 insertions(+), 122 deletions(-)

-- 
2.48.0


^ permalink raw reply	[flat|nested] 31+ messages in thread
* [PATCH 0/2] AuxCCS handling and render compression modifiers
@ 2025-01-31 14:20 Tvrtko Ursulin
  2025-01-31 20:26 ` ✗ Xe.CI.Full: failure for " Patchwork
  0 siblings, 1 reply; 31+ messages in thread
From: Tvrtko Ursulin @ 2025-01-31 14:20 UTC (permalink / raw)
  To: intel-xe
  Cc: kernel-dev, Tvrtko Ursulin, José Roberto de Souza,
	Juha-Pekka Heikkila, Michael J. Ruhl

A two patch series to fix and add xe support for AuxCSS framebuffers via DPT.

Currently the auxiliary buffer data isn't mapped into the page tables at all so
cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe")
had to disable the support.

First patch fixes that and second effectively reverts cf48bddd31de.

Tested with KDE Wayland, on Lenovo Carbon X1 ADL-P:

  [PLANE:32:plane 1A]: type=PRI
          uapi: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=visible, src=2880.000000x1800.000000+0.000000+0.000000, dst=2880x1800+0+0, rotation=0 (0x00000001)
          hw: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=yes, src=2880.000000x1800.000000+0.000000+0.000000, dst=2880x1800+0+0, rotation=0 (0x00000001)

Display working fine - no artefacts, no DMAR/PIPE faults.

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Cc: Michael J. Ruhl <michael.j.ruhl@intel.com>

Tvrtko Ursulin (2):
  drm/xe/display: Add support for AuxCCS
  drm/xe/display: Expose AuxCCS frame buffer modifiers

 .../drm/i915/display/skl_universal_plane.c    |   6 -
 drivers/gpu/drm/xe/display/xe_fb_pin.c        | 107 +++++++++++++-----
 2 files changed, 80 insertions(+), 33 deletions(-)

-- 
2.48.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

end of thread, other threads:[~2026-03-24 18:53 UTC | newest]

Thread overview: 31+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-03-20 17:02 [PATCH v24 00/12] *AuxCCS handling and render compression modifiers Tvrtko Ursulin
2026-03-20 17:02 ` [PATCH v24 01/12] drm/xe: Rename XE_BO_FLAG_SCANOUT to XE_BO_FLAG_FORCE_WC Tvrtko Ursulin
2026-03-20 17:02 ` [PATCH v24 02/12] drm/xe: Use write-combine mapping when populating DPT Tvrtko Ursulin
2026-03-20 17:02 ` [PATCH v24 03/12] drm/xe/xelpg: Limit AuxCCS ring buffer programming to Alderlake Tvrtko Ursulin
2026-03-20 17:02 ` [PATCH v24 04/12] drm/xe/xelp: Quiesce memory traffic before invalidating AuxCCS Tvrtko Ursulin
2026-03-20 17:02 ` [PATCH v24 05/12] drm/xe/xelp: Wait for AuxCCS invalidation to complete Tvrtko Ursulin
2026-03-20 17:02 ` [PATCH v24 06/12] drm/xe: Move aux table invalidation to ring ops Tvrtko Ursulin
2026-03-20 17:02 ` [PATCH v24 07/12] drm/xe/xelp: Add AuxCCS invalidation to the indirect context workarounds Tvrtko Ursulin
2026-03-20 17:02 ` [PATCH v24 08/12] drm/xe/display: Move remapped plane loop out of __xe_pin_fb_vma_dpt Tvrtko Ursulin
2026-03-20 17:02 ` [PATCH v24 09/12] drm/xe/display: Change write_dpt_remapped_tiled function signature Tvrtko Ursulin
2026-03-20 17:02 ` [PATCH v24 10/12] drm/xe/display: Respect remapped plane alignment Tvrtko Ursulin
2026-03-20 17:02 ` [PATCH v24 11/12] drm/xe/display: Add support for AuxCCS Tvrtko Ursulin
2026-03-20 17:02 ` [PATCH v24 12/12] drm/xe/xelp: Expose AuxCCS frame buffer modifiers on Alderlake-P Tvrtko Ursulin
2026-03-20 17:07 ` ✗ CI.checkpatch: warning for *AuxCCS handling and render compression modifiers Patchwork
2026-03-20 17:09 ` ✓ CI.KUnit: success " Patchwork
2026-03-20 17:43 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-21 17:52 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-03-23  9:42   ` Tvrtko Ursulin
2026-03-23 22:11     ` Rodrigo Vivi
2026-03-24  8:25       ` Tvrtko Ursulin
  -- strict thread matches above, loose matches on Subject: below --
2026-03-24  8:40 [PATCH v25 00/12] AuxCCS " Tvrtko Ursulin
2026-03-24 18:53 ` ✗ Xe.CI.FULL: failure for " Patchwork
2026-03-19 10:06 [PATCH v23 00/12] " Tvrtko Ursulin
2026-03-20 11:38 ` ✗ Xe.CI.FULL: failure for " Patchwork
2025-12-16 15:37 [PATCH v16 0/8] " Tvrtko Ursulin
2025-12-17 21:57 ` ✗ Xe.CI.Full: failure for " Patchwork
2025-12-08 19:17 [PATCH v15 00/10] " Tvrtko Ursulin
2025-12-09  3:28 ` ✗ Xe.CI.Full: failure for " Patchwork
2025-10-24 10:47 [PATCH v14 00/13] " Tvrtko Ursulin
2025-10-24 23:57 ` ✗ Xe.CI.Full: failure for " Patchwork
2025-11-07 20:55   ` Tvrtko Ursulin
2025-10-20  7:58 [PATCH v13 00/12] " Tvrtko Ursulin
2025-10-20 14:52 ` ✗ Xe.CI.Full: failure for " Patchwork
2025-10-20 15:03   ` Tvrtko Ursulin
2025-01-31 14:20 [PATCH 0/2] " Tvrtko Ursulin
2025-01-31 20:26 ` ✗ Xe.CI.Full: failure for " Patchwork
2025-02-04 11:12   ` Tvrtko Ursulin
2025-02-04 23:36     ` Rodrigo Vivi

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