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* [PATCH] drm/xe: Add device CXL capabilities identification
@ 2024-05-26  8:24 Farah Kassabri
  2024-05-26  8:29 ` ✓ CI.Patch_applied: success for " Patchwork
                   ` (8 more replies)
  0 siblings, 9 replies; 12+ messages in thread
From: Farah Kassabri @ 2024-05-26  8:24 UTC (permalink / raw)
  To: intel-xe; +Cc: farah.kassabri

As future Intel GPUs will use CXL interface with the host
servers, this patch will add check if the xe device has CXL
capabilities or not, by reading the PCIe standard DVSEC register
and identify the CXL vendor id.

Signed-off-by: Farah Kassabri <fkassabri@habana.ai>
---
 drivers/gpu/drm/xe/Makefile          |  3 ++-
 drivers/gpu/drm/xe/xe_cxl.c          | 33 ++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_cxl.h          | 14 ++++++++++++
 drivers/gpu/drm/xe/xe_device.c       |  5 +++++
 drivers/gpu/drm/xe/xe_device_types.h | 10 +++++++++
 5 files changed, 64 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/xe/xe_cxl.c
 create mode 100644 drivers/gpu/drm/xe/xe_cxl.h

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index c9f067b8f54d..faf40ff3c62e 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -146,7 +146,8 @@ xe-y += xe_bb.o \
 	xe_vram_freq.o \
 	xe_wait_user_fence.o \
 	xe_wa.o \
-	xe_wopcm.o
+	xe_wopcm.o \
+	xe_cxl.o \
 
 xe-$(CONFIG_HMM_MIRROR) += xe_hmm.o
 
diff --git a/drivers/gpu/drm/xe/xe_cxl.c b/drivers/gpu/drm/xe/xe_cxl.c
new file mode 100644
index 000000000000..da47a79ee2c2
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_cxl.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#include "xe_cxl.h"
+
+int xe_init_cxl_capabilities(struct xe_device *xe, struct pci_dev *pdev)
+{
+	int cxl_dvsec, rc;
+	u16 ctrl;
+
+	cxl_dvsec = pci_find_dvsec_capability(pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE);
+	if (cxl_dvsec) {
+		xe->info.has_cxl_cap = true;
+		xe->cxl.dvsec = cxl_dvsec;
+
+		rc = pci_read_config_word(pdev, cxl_dvsec + CXL_DVSEC_CTRL_OFFSET, &ctrl);
+		if (rc < 0) {
+			drm_err(&xe->drm, "Failed to read dvsec ctrl register\n");
+			return rc;
+		}
+
+		if (ctrl & CXL_DVSEC_MEM_ENABLE)
+			xe->cxl.type = (ctrl & BIT(0)) ? 2 : 3;
+		else
+			xe->cxl.type = 1;
+
+		drm_dbg(&xe->drm, "The device has CXL capability, type %u\n", xe->cxl.type);
+	}
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/xe/xe_cxl.h b/drivers/gpu/drm/xe/xe_cxl.h
new file mode 100644
index 000000000000..971c6e9adc2f
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_cxl.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef _XE_CXL_H_
+#define _XE_CXL_H_
+
+#include "xe_device.h"
+#include "../drivers/cxl/cxlpci.h"
+
+int xe_init_cxl_capabilities(struct xe_device *xe, struct pci_dev *pdev);
+
+#endif /* _XE_CXL_H_ */
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 5acf2c92789f..ca2e47a47b11 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -50,6 +50,7 @@
 #include "xe_ttm_sys_mgr.h"
 #include "xe_vm.h"
 #include "xe_wait_user_fence.h"
+#include "xe_cxl.h"
 
 static int xe_file_open(struct drm_device *dev, struct drm_file *file)
 {
@@ -312,6 +313,10 @@ struct xe_device *xe_device_create(struct pci_dev *pdev,
 	if (WARN_ON(err))
 		goto err;
 
+	err = xe_init_cxl_capabilities(xe, pdev);
+	if (err)
+		goto err;
+
 	return xe;
 
 err:
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index bc97990fd032..aad56b829ca4 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -285,6 +285,8 @@ struct xe_device {
 		u8 has_atomic_enable_pte_bit:1;
 		/** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */
 		u8 has_device_atomics_on_smem:1;
+		/** @info.has_cxl_cap: device has CXL capabilities */
+		u8 has_cxl_cap:1;
 
 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
 		struct {
@@ -321,6 +323,14 @@ struct xe_device {
 		struct ttm_resource_manager sys_mgr;
 	} mem;
 
+	/** @cxl: cxl info for device */
+	struct {
+		/** @cxl.dvsec: offset to device DVSEC */
+		int dvsec;
+		/** @cxl.type: cxl device type */
+		int type;
+	} cxl;
+
 	/** @sriov: device level virtualization data */
 	struct {
 		/** @sriov.__mode: SR-IOV mode (Don't access directly!) */
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread
end of thread, other threads:[~2024-05-27 14:12 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-05-26  8:24 [PATCH] drm/xe: Add device CXL capabilities identification Farah Kassabri
2024-05-26  8:29 ` ✓ CI.Patch_applied: success for " Patchwork
2024-05-26  8:29 ` ✗ CI.checkpatch: warning " Patchwork
2024-05-26  8:30 ` ✓ CI.KUnit: success " Patchwork
2024-05-26  8:42 ` ✓ CI.Build: " Patchwork
2024-05-26  8:44 ` ✓ CI.Hooks: " Patchwork
2024-05-26  8:45 ` ✓ CI.checksparse: " Patchwork
2024-05-26  9:24 ` ✓ CI.BAT: " Patchwork
2024-05-26 10:32 ` [PATCH] " Michal Wajdeczko
2024-05-26 13:10   ` Farah Kassabri
2024-05-26 16:13     ` Michal Wajdeczko
2024-05-27 14:12 ` ✗ CI.FULL: failure for " Patchwork

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