[PATCH 00/15] drm/i915: refactor display funcs, add display irq hooks

[PATCH 00/15] drm/i915: refactor display funcs, add display irq hooks

[Jani Nikula]

I was going to add display irq hooks first, but decided the organization
of the existing hooks under display->funcs is a bit weird. Spread them
out by function first. And then add hooks for display irq calls.

The end goal is to reduce the number of functions exposed from display
to i915 and xe core.

Jani Nikula (15):
  drm/i915/display: move audio funcs under audio sub-struct
  drm/i915/display: move color funcs under color sub-struct
  drm/i915/display: move fdi funcs under fdi sub-struct
  drm/i915/display: move watermark funcs under wm sub-struct
  drm/i915/display: move hotplug irq funcs under hotplug sub-struct
  drm/i915/display: move dpll funcs under dpll sub-struct
  drm/i915/display: move cdclk funcs under cdclk sub-struct
  drm/i915/display: move display funcs under modeset sub-struct
  drm/i915/irq: deduplicate dg1_de_irq_postinstall() and
    gen11_de_irq_postinstall()
  drm/i915/irq: move VLV/CHV LPE irq handler call after irq acks
  drm/i915/irq: constify pipe stats parameters
  drm/i915/irq: add display irq funcs, start with
    intel_display_irq_reset()
  drm/i915/irq: add intel_display_irq_postinstall() to irq funcs
  drm/i915/irq: add intel_display_irq_ack() to irq funcs
  drm/i915/irq: add intel_display_irq_handler() to irq funcs

 drivers/gpu/drm/i915/display/i9xx_wm.c        |  22 +-
 drivers/gpu/drm/i915/display/intel_audio.c    |  22 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  84 +++----
 drivers/gpu/drm/i915/display/intel_color.c    |  58 ++---
 drivers/gpu/drm/i915/display/intel_display.c  |  30 +--
 .../gpu/drm/i915/display/intel_display_core.h |  60 ++---
 .../gpu/drm/i915/display/intel_display_irq.c  | 218 +++++++++++++++---
 .../gpu/drm/i915/display/intel_display_irq.h  |  37 ++-
 drivers/gpu/drm/i915/display/intel_dpll.c     |  28 +--
 drivers/gpu/drm/i915/display/intel_fdi.c      |   8 +-
 .../gpu/drm/i915/display/intel_hotplug_irq.c  |  30 +--
 .../drm/i915/display/intel_initial_plane.c    |   4 +-
 .../drm/i915/display/intel_modeset_setup.c    |   2 +-
 drivers/gpu/drm/i915/display/intel_wm.c       |  32 +--
 drivers/gpu/drm/i915/display/skl_watermark.c  |   2 +-
 drivers/gpu/drm/i915/i915_irq.c               | 182 +++++----------
 drivers/gpu/drm/xe/display/xe_display.c       |   6 +-
 17 files changed, 454 insertions(+), 371 deletions(-)

-- 
2.47.3

[PATCH 01/15] drm/i915/display: move audio funcs under audio sub-struct

[Jani Nikula]

Move audio related functions under audio sub-struct of struct
intel_display.

The funcs sub-struct of struct intel_display seems unnecessary. Instead
of display->funcs.FEATURE, prefer display->FEATURE.funcs.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_audio.c    | 22 ++++++++-----------
 .../gpu/drm/i915/display/intel_display_core.h |  6 ++---
 .../gpu/drm/i915/display/intel_display_irq.c  |  4 ++++
 3 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 081627e0d917..2a6476ccc85b 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -754,10 +754,8 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
 		    crtc->base.base.id, crtc->base.name,
 		    drm_eld_size(crtc_state->eld));
 
-	if (display->funcs.audio)
-		display->funcs.audio->audio_codec_enable(encoder,
-							      crtc_state,
-							      conn_state);
+	if (display->audio.funcs)
+		display->audio.funcs->audio_codec_enable(encoder, crtc_state, conn_state);
 
 	mutex_lock(&display->audio.mutex);
 
@@ -813,10 +811,8 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
 		    encoder->base.base.id, encoder->base.name,
 		    crtc->base.base.id, crtc->base.name);
 
-	if (display->funcs.audio)
-		display->funcs.audio->audio_codec_disable(encoder,
-							       old_crtc_state,
-							       old_conn_state);
+	if (display->audio.funcs)
+		display->audio.funcs->audio_codec_disable(encoder, old_crtc_state, old_conn_state);
 
 	mutex_lock(&display->audio.mutex);
 
@@ -864,8 +860,8 @@ void intel_audio_codec_get_config(struct intel_encoder *encoder,
 	if (!crtc_state->has_audio)
 		return;
 
-	if (display->funcs.audio)
-		display->funcs.audio->audio_codec_get_config(encoder, crtc_state);
+	if (display->audio.funcs)
+		display->audio.funcs->audio_codec_get_config(encoder, crtc_state);
 }
 
 static const struct intel_audio_funcs g4x_audio_funcs = {
@@ -893,12 +889,12 @@ static const struct intel_audio_funcs hsw_audio_funcs = {
 void intel_audio_hooks_init(struct intel_display *display)
 {
 	if (display->platform.g4x)
-		display->funcs.audio = &g4x_audio_funcs;
+		display->audio.funcs = &g4x_audio_funcs;
 	else if (display->platform.valleyview || display->platform.cherryview ||
 		 HAS_PCH_CPT(display) || HAS_PCH_IBX(display))
-		display->funcs.audio = &ibx_audio_funcs;
+		display->audio.funcs = &ibx_audio_funcs;
 	else if (display->platform.haswell || DISPLAY_VER(display) >= 8)
-		display->funcs.audio = &hsw_audio_funcs;
+		display->audio.funcs = &hsw_audio_funcs;
 }
 
 struct aud_ts_cdclk_m_n {
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index c5a07090cba6..c61990ca9e29 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -100,6 +100,9 @@ struct intel_audio_state {
 };
 
 struct intel_audio {
+	/* internal display audio functions */
+	const struct intel_audio_funcs *funcs;
+
 	/* hda/i915 audio component */
 	struct i915_audio_component *component;
 	bool component_registered;
@@ -319,9 +322,6 @@ struct intel_display {
 
 		/* Display internal color functions */
 		const struct intel_color_funcs *color;
-
-		/* Display internal audio functions */
-		const struct intel_audio_funcs *audio;
 	} funcs;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 70c1bba7c0a8..b5bfdebc66ca 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -2458,6 +2458,10 @@ void dg1_de_irq_postinstall(struct intel_display *display)
 	intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
 }
 
+struct intel_display_irq_funcs {
+	void (*reset)(struct intel_display *display);
+};
+
 void intel_display_irq_init(struct intel_display *display)
 {
 	spin_lock_init(&display->irq.lock);
-- 
2.47.3

[PATCH 02/15] drm/i915/display: move color funcs under color sub-struct

[Jani Nikula]

Move color related functions under color sub-struct of struct
intel_display.

The funcs sub-struct of struct intel_display seems unnecessary. Instead
of display->funcs.FEATURE, prefer display->FEATURE.funcs.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c    | 58 +++++++++----------
 .../gpu/drm/i915/display/intel_display_core.h |  6 +-
 2 files changed, 32 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index e7950655434b..0531c60e5e5d 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1933,7 +1933,7 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->dsb_color)
 		return;
 
-	display->funcs.color->load_luts(crtc_state);
+	display->color.funcs->load_luts(crtc_state);
 }
 
 void intel_color_commit_noarm(struct intel_dsb *dsb,
@@ -1941,8 +1941,8 @@ void intel_color_commit_noarm(struct intel_dsb *dsb,
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 
-	if (display->funcs.color->color_commit_noarm)
-		display->funcs.color->color_commit_noarm(dsb, crtc_state);
+	if (display->color.funcs->color_commit_noarm)
+		display->color.funcs->color_commit_noarm(dsb, crtc_state);
 }
 
 void intel_color_commit_arm(struct intel_dsb *dsb,
@@ -1950,15 +1950,15 @@ void intel_color_commit_arm(struct intel_dsb *dsb,
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 
-	display->funcs.color->color_commit_arm(dsb, crtc_state);
+	display->color.funcs->color_commit_arm(dsb, crtc_state);
 }
 
 void intel_color_post_update(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 
-	if (display->funcs.color->color_post_update)
-		display->funcs.color->color_post_update(crtc_state);
+	if (display->color.funcs->color_post_update)
+		display->color.funcs->color_post_update(crtc_state);
 }
 
 void intel_color_modeset(const struct intel_crtc_state *crtc_state)
@@ -2022,7 +2022,7 @@ void intel_color_prepare_commit(struct intel_atomic_state *state,
 	if (!intel_color_uses_dsb(crtc_state))
 		return;
 
-	display->funcs.color->load_luts(crtc_state);
+	display->color.funcs->load_luts(crtc_state);
 
 	if (crtc_state->use_dsb && intel_color_uses_chained_dsb(crtc_state)) {
 		intel_vrr_send_push(crtc_state->dsb_color, crtc_state);
@@ -2113,19 +2113,19 @@ int intel_color_check(struct intel_atomic_state *state,
 	if (!intel_crtc_needs_color_update(new_crtc_state))
 		return 0;
 
-	return display->funcs.color->color_check(state, crtc);
+	return display->color.funcs->color_check(state, crtc);
 }
 
 void intel_color_get_config(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 
-	display->funcs.color->get_config(crtc_state);
+	display->color.funcs->get_config(crtc_state);
 
-	display->funcs.color->read_luts(crtc_state);
+	display->color.funcs->read_luts(crtc_state);
 
-	if (display->funcs.color->read_csc)
-		display->funcs.color->read_csc(crtc_state);
+	if (display->color.funcs->read_csc)
+		display->color.funcs->read_csc(crtc_state);
 }
 
 bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state,
@@ -2142,7 +2142,7 @@ bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state,
 	if (!is_pre_csc_lut && crtc_state->c8_planes)
 		return true;
 
-	return display->funcs.color->lut_equal(crtc_state, blob1, blob2,
+	return display->color.funcs->lut_equal(crtc_state, blob1, blob2,
 					       is_pre_csc_lut);
 }
 
@@ -4253,8 +4253,8 @@ intel_color_load_plane_csc_matrix(struct intel_dsb *dsb,
 {
 	struct intel_display *display = to_intel_display(plane_state);
 
-	if (display->funcs.color->load_plane_csc_matrix)
-		display->funcs.color->load_plane_csc_matrix(dsb, plane_state);
+	if (display->color.funcs->load_plane_csc_matrix)
+		display->color.funcs->load_plane_csc_matrix(dsb, plane_state);
 }
 
 static void
@@ -4263,8 +4263,8 @@ intel_color_load_plane_luts(struct intel_dsb *dsb,
 {
 	struct intel_display *display = to_intel_display(plane_state);
 
-	if (display->funcs.color->load_plane_luts)
-		display->funcs.color->load_plane_luts(dsb, plane_state);
+	if (display->color.funcs->load_plane_luts)
+		display->color.funcs->load_plane_luts(dsb, plane_state);
 }
 
 bool
@@ -4346,29 +4346,29 @@ void intel_color_init_hooks(struct intel_display *display)
 {
 	if (HAS_GMCH(display)) {
 		if (display->platform.cherryview)
-			display->funcs.color = &chv_color_funcs;
+			display->color.funcs = &chv_color_funcs;
 		else if (display->platform.valleyview)
-			display->funcs.color = &vlv_color_funcs;
+			display->color.funcs = &vlv_color_funcs;
 		else if (DISPLAY_VER(display) >= 4)
-			display->funcs.color = &i965_color_funcs;
+			display->color.funcs = &i965_color_funcs;
 		else
-			display->funcs.color = &i9xx_color_funcs;
+			display->color.funcs = &i9xx_color_funcs;
 	} else {
 		if (DISPLAY_VER(display) >= 12)
-			display->funcs.color = &tgl_color_funcs;
+			display->color.funcs = &tgl_color_funcs;
 		else if (DISPLAY_VER(display) == 11)
-			display->funcs.color = &icl_color_funcs;
+			display->color.funcs = &icl_color_funcs;
 		else if (DISPLAY_VER(display) == 10)
-			display->funcs.color = &glk_color_funcs;
+			display->color.funcs = &glk_color_funcs;
 		else if (DISPLAY_VER(display) == 9)
-			display->funcs.color = &skl_color_funcs;
+			display->color.funcs = &skl_color_funcs;
 		else if (DISPLAY_VER(display) == 8)
-			display->funcs.color = &bdw_color_funcs;
+			display->color.funcs = &bdw_color_funcs;
 		else if (display->platform.haswell)
-			display->funcs.color = &hsw_color_funcs;
+			display->color.funcs = &hsw_color_funcs;
 		else if (DISPLAY_VER(display) == 7)
-			display->funcs.color = &ivb_color_funcs;
+			display->color.funcs = &ivb_color_funcs;
 		else
-			display->funcs.color = &ilk_color_funcs;
+			display->color.funcs = &ilk_color_funcs;
 	}
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index c61990ca9e29..db07e332af5a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -319,9 +319,6 @@ struct intel_display {
 
 		/* fdi display functions */
 		const struct intel_fdi_funcs *fdi;
-
-		/* Display internal color functions */
-		const struct intel_color_funcs *color;
 	} funcs;
 
 	struct {
@@ -365,6 +362,9 @@ struct intel_display {
 	} cdclk;
 
 	struct {
+		/* internal color functions */
+		const struct intel_color_funcs *funcs;
+
 		struct drm_property_blob *glk_linear_degamma_lut;
 	} color;
 
-- 
2.47.3

[PATCH 03/15] drm/i915/display: move fdi funcs under fdi sub-struct

[Jani Nikula]

Move fdi related functions under fdi sub-struct of struct intel_display.

The funcs sub-struct of struct intel_display seems unnecessary. Instead
of display->funcs.FEATURE, prefer display->FEATURE.funcs.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_core.h | 6 +++---
 drivers/gpu/drm/i915/display/intel_fdi.c          | 8 ++++----
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index db07e332af5a..0fdda5339e81 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -316,9 +316,6 @@ struct intel_display {
 
 		/* pm display functions */
 		const struct intel_wm_funcs *wm;
-
-		/* fdi display functions */
-		const struct intel_fdi_funcs *fdi;
 	} funcs;
 
 	struct {
@@ -418,6 +415,9 @@ struct intel_display {
 	} fbdev;
 
 	struct {
+		/* internal fdi functions */
+		const struct intel_fdi_funcs *funcs;
+
 		unsigned int pll_freq;
 		u32 rx_config;
 	} fdi;
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 917f020650af..f5094655a63b 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -123,7 +123,7 @@ void intel_fdi_link_train(struct intel_crtc *crtc,
 {
 	struct intel_display *display = to_intel_display(crtc);
 
-	display->funcs.fdi->fdi_link_train(crtc, crtc_state);
+	display->fdi.funcs->fdi_link_train(crtc, crtc_state);
 }
 
 /**
@@ -1109,11 +1109,11 @@ void
 intel_fdi_init_hook(struct intel_display *display)
 {
 	if (display->platform.ironlake) {
-		display->funcs.fdi = &ilk_funcs;
+		display->fdi.funcs = &ilk_funcs;
 	} else if (display->platform.sandybridge) {
-		display->funcs.fdi = &gen6_funcs;
+		display->fdi.funcs = &gen6_funcs;
 	} else if (display->platform.ivybridge) {
 		/* FIXME: detect B0+ stepping and use auto training */
-		display->funcs.fdi = &ivb_funcs;
+		display->fdi.funcs = &ivb_funcs;
 	}
 }
-- 
2.47.3

[PATCH 04/15] drm/i915/display: move watermark funcs under wm sub-struct

[Jani Nikula]

Move watermark related functions under wm sub-struct of struct
intel_display.

The funcs sub-struct of struct intel_display seems unnecessary. Instead
of display->funcs.FEATURE, prefer display->FEATURE.funcs.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/i9xx_wm.c        | 22 ++++++-------
 drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
 .../gpu/drm/i915/display/intel_display_core.h |  6 ++--
 drivers/gpu/drm/i915/display/intel_wm.c       | 32 +++++++++----------
 drivers/gpu/drm/i915/display/skl_watermark.c  |  2 +-
 5 files changed, 32 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 02ac6f9a3d0e..ca4fff10ce8f 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -3584,7 +3584,7 @@ void ilk_wm_sanitize(struct intel_display *display)
 	int i;
 
 	/* Only supported on platforms that use atomic watermark design */
-	if (!display->funcs.wm->optimize_watermarks)
+	if (!display->wm.funcs->optimize_watermarks)
 		return;
 
 	if (drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 9))
@@ -4152,34 +4152,34 @@ void i9xx_wm_init(struct intel_display *display)
 	/* For FIFO watermark updates */
 	if (HAS_PCH_SPLIT(display)) {
 		ilk_setup_wm_latency(display);
-		display->funcs.wm = &ilk_wm_funcs;
+		display->wm.funcs = &ilk_wm_funcs;
 	} else if (display->platform.valleyview || display->platform.cherryview) {
 		vlv_setup_wm_latency(display);
-		display->funcs.wm = &vlv_wm_funcs;
+		display->wm.funcs = &vlv_wm_funcs;
 	} else if (display->platform.g4x) {
 		g4x_setup_wm_latency(display);
-		display->funcs.wm = &g4x_wm_funcs;
+		display->wm.funcs = &g4x_wm_funcs;
 	} else if (display->platform.pineview) {
 		if (!pnv_get_cxsr_latency(display)) {
 			drm_info(display->drm, "Unknown FSB/MEM, disabling CxSR\n");
 			/* Disable CxSR and never update its watermark again */
 			intel_set_memory_cxsr(display, false);
-			display->funcs.wm = &nop_funcs;
+			display->wm.funcs = &nop_funcs;
 		} else {
-			display->funcs.wm = &pnv_wm_funcs;
+			display->wm.funcs = &pnv_wm_funcs;
 		}
 	} else if (DISPLAY_VER(display) == 4) {
-		display->funcs.wm = &i965_wm_funcs;
+		display->wm.funcs = &i965_wm_funcs;
 	} else if (DISPLAY_VER(display) == 3) {
-		display->funcs.wm = &i9xx_wm_funcs;
+		display->wm.funcs = &i9xx_wm_funcs;
 	} else if (DISPLAY_VER(display) == 2) {
 		if (INTEL_NUM_PIPES(display) == 1)
-			display->funcs.wm = &i845_wm_funcs;
+			display->wm.funcs = &i845_wm_funcs;
 		else
-			display->funcs.wm = &i9xx_wm_funcs;
+			display->wm.funcs = &i9xx_wm_funcs;
 	} else {
 		drm_err(display->drm,
 			"unexpected fall-through in %s\n", __func__);
-		display->funcs.wm = &nop_funcs;
+		display->wm.funcs = &nop_funcs;
 	}
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 674a4ece6d0f..7839e663f7bc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2162,7 +2162,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
 	if (DISPLAY_VER(display) != 2)
 		intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
 
-	if (!display->funcs.wm->initial_watermarks)
+	if (!display->wm.funcs->initial_watermarks)
 		intel_update_watermarks(display);
 
 	/* clock the pipe down to 640x480@60 to potentially save power */
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 0fdda5339e81..01394724abc9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -247,6 +247,9 @@ struct intel_vbt_data {
 };
 
 struct intel_wm {
+	/* internal watermark functions */
+	const struct intel_wm_funcs *funcs;
+
 	/*
 	 * Raw watermark latency values:
 	 * in 0.1us units for WM0,
@@ -313,9 +316,6 @@ struct intel_display {
 
 		/* irq display functions */
 		const struct intel_hotplug_funcs *hotplug;
-
-		/* pm display functions */
-		const struct intel_wm_funcs *wm;
 	} funcs;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_wm.c b/drivers/gpu/drm/i915/display/intel_wm.c
index f887a664fe22..b4aded774ce6 100644
--- a/drivers/gpu/drm/i915/display/intel_wm.c
+++ b/drivers/gpu/drm/i915/display/intel_wm.c
@@ -48,8 +48,8 @@
  */
 void intel_update_watermarks(struct intel_display *display)
 {
-	if (display->funcs.wm->update_wm)
-		display->funcs.wm->update_wm(display);
+	if (display->wm.funcs->update_wm)
+		display->wm.funcs->update_wm(display);
 }
 
 int intel_wm_compute(struct intel_atomic_state *state,
@@ -57,10 +57,10 @@ int intel_wm_compute(struct intel_atomic_state *state,
 {
 	struct intel_display *display = to_intel_display(state);
 
-	if (!display->funcs.wm->compute_watermarks)
+	if (!display->wm.funcs->compute_watermarks)
 		return 0;
 
-	return display->funcs.wm->compute_watermarks(state, crtc);
+	return display->wm.funcs->compute_watermarks(state, crtc);
 }
 
 bool intel_initial_watermarks(struct intel_atomic_state *state,
@@ -68,8 +68,8 @@ bool intel_initial_watermarks(struct intel_atomic_state *state,
 {
 	struct intel_display *display = to_intel_display(state);
 
-	if (display->funcs.wm->initial_watermarks) {
-		display->funcs.wm->initial_watermarks(state, crtc);
+	if (display->wm.funcs->initial_watermarks) {
+		display->wm.funcs->initial_watermarks(state, crtc);
 		return true;
 	}
 
@@ -81,8 +81,8 @@ void intel_atomic_update_watermarks(struct intel_atomic_state *state,
 {
 	struct intel_display *display = to_intel_display(state);
 
-	if (display->funcs.wm->atomic_update_watermarks)
-		display->funcs.wm->atomic_update_watermarks(state, crtc);
+	if (display->wm.funcs->atomic_update_watermarks)
+		display->wm.funcs->atomic_update_watermarks(state, crtc);
 }
 
 void intel_optimize_watermarks(struct intel_atomic_state *state,
@@ -90,30 +90,30 @@ void intel_optimize_watermarks(struct intel_atomic_state *state,
 {
 	struct intel_display *display = to_intel_display(state);
 
-	if (display->funcs.wm->optimize_watermarks)
-		display->funcs.wm->optimize_watermarks(state, crtc);
+	if (display->wm.funcs->optimize_watermarks)
+		display->wm.funcs->optimize_watermarks(state, crtc);
 }
 
 int intel_compute_global_watermarks(struct intel_atomic_state *state)
 {
 	struct intel_display *display = to_intel_display(state);
 
-	if (display->funcs.wm->compute_global_watermarks)
-		return display->funcs.wm->compute_global_watermarks(state);
+	if (display->wm.funcs->compute_global_watermarks)
+		return display->wm.funcs->compute_global_watermarks(state);
 
 	return 0;
 }
 
 void intel_wm_get_hw_state(struct intel_display *display)
 {
-	if (display->funcs.wm->get_hw_state)
-		return display->funcs.wm->get_hw_state(display);
+	if (display->wm.funcs->get_hw_state)
+		return display->wm.funcs->get_hw_state(display);
 }
 
 void intel_wm_sanitize(struct intel_display *display)
 {
-	if (display->funcs.wm->sanitize)
-		return display->funcs.wm->sanitize(display);
+	if (display->wm.funcs->sanitize)
+		return display->wm.funcs->sanitize(display);
 }
 
 bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 4bffa27ce02c..96d2dcbe7bbc 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3995,7 +3995,7 @@ void skl_wm_init(struct intel_display *display)
 
 	skl_setup_wm_latency(display);
 
-	display->funcs.wm = &skl_wm_funcs;
+	display->wm.funcs = &skl_wm_funcs;
 }
 
 static int skl_watermark_ipc_status_show(struct seq_file *m, void *data)
-- 
2.47.3

[PATCH 05/15] drm/i915/display: move hotplug irq funcs under hotplug sub-struct

[Jani Nikula]

Move hotplug irq related functions under hotplug sub-struct of struct
intel_display.

The funcs sub-struct of struct intel_display seems unnecessary. Instead
of display->funcs.FEATURE, prefer display->FEATURE.funcs.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/display/intel_display_core.h |  8 ++---
 .../gpu/drm/i915/display/intel_hotplug_irq.c  | 30 +++++++++----------
 2 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 01394724abc9..0c2e17edbd5f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -47,7 +47,7 @@ struct intel_dpll_global_funcs;
 struct intel_dpll_mgr;
 struct intel_fbdev;
 struct intel_fdi_funcs;
-struct intel_hotplug_funcs;
+struct intel_hotplug_irq_funcs;
 struct intel_initial_plane_config;
 struct intel_opregion;
 struct intel_overlay;
@@ -155,6 +155,9 @@ struct intel_frontbuffer_tracking {
 };
 
 struct intel_hotplug {
+	/* internal hotplug irq functions */
+	const struct intel_hotplug_irq_funcs *funcs;
+
 	struct delayed_work hotplug_work;
 
 	const u32 *hpd, *pch_hpd;
@@ -313,9 +316,6 @@ struct intel_display {
 
 		/* Display pll funcs */
 		const struct intel_dpll_global_funcs *dpll;
-
-		/* irq display functions */
-		const struct intel_hotplug_funcs *hotplug;
 	} funcs;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index 8865cb2ac569..539fd555edce 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -1420,7 +1420,7 @@ static void i915_hpd_irq_setup(struct intel_display *display)
 					     hotplug_en);
 }
 
-struct intel_hotplug_funcs {
+struct intel_hotplug_irq_funcs {
 	/* Enable HPD sense and interrupts for all present encoders */
 	void (*hpd_irq_setup)(struct intel_display *display);
 	/* Enable HPD sense for a single encoder */
@@ -1428,7 +1428,7 @@ struct intel_hotplug_funcs {
 };
 
 #define HPD_FUNCS(platform)					 \
-static const struct intel_hotplug_funcs platform##_hpd_funcs = { \
+static const struct intel_hotplug_irq_funcs platform##_hpd_funcs = { \
 	.hpd_irq_setup = platform##_hpd_irq_setup,		 \
 	.hpd_enable_detection = platform##_hpd_enable_detection, \
 }
@@ -1447,8 +1447,8 @@ void intel_hpd_enable_detection(struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(encoder);
 
-	if (display->funcs.hotplug)
-		display->funcs.hotplug->hpd_enable_detection(encoder);
+	if (display->hotplug.funcs)
+		display->hotplug.funcs->hpd_enable_detection(encoder);
 }
 
 void intel_hpd_irq_setup(struct intel_display *display)
@@ -1457,8 +1457,8 @@ void intel_hpd_irq_setup(struct intel_display *display)
 	    !display->irq.vlv_display_irqs_enabled)
 		return;
 
-	if (display->funcs.hotplug)
-		display->funcs.hotplug->hpd_irq_setup(display);
+	if (display->hotplug.funcs)
+		display->hotplug.funcs->hpd_irq_setup(display);
 }
 
 void intel_hotplug_irq_init(struct intel_display *display)
@@ -1469,23 +1469,23 @@ void intel_hotplug_irq_init(struct intel_display *display)
 
 	if (HAS_GMCH(display)) {
 		if (HAS_HOTPLUG(display))
-			display->funcs.hotplug = &i915_hpd_funcs;
+			display->hotplug.funcs = &i915_hpd_funcs;
 	} else {
 		if (HAS_PCH_DG2(display))
-			display->funcs.hotplug = &icp_hpd_funcs;
+			display->hotplug.funcs = &icp_hpd_funcs;
 		else if (HAS_PCH_DG1(display))
-			display->funcs.hotplug = &dg1_hpd_funcs;
+			display->hotplug.funcs = &dg1_hpd_funcs;
 		else if (DISPLAY_VER(display) >= 14)
-			display->funcs.hotplug = &xelpdp_hpd_funcs;
+			display->hotplug.funcs = &xelpdp_hpd_funcs;
 		else if (DISPLAY_VER(display) >= 11)
-			display->funcs.hotplug = &gen11_hpd_funcs;
+			display->hotplug.funcs = &gen11_hpd_funcs;
 		else if (display->platform.geminilake || display->platform.broxton)
-			display->funcs.hotplug = &bxt_hpd_funcs;
+			display->hotplug.funcs = &bxt_hpd_funcs;
 		else if (INTEL_PCH_TYPE(display) >= PCH_ICP)
-			display->funcs.hotplug = &icp_hpd_funcs;
+			display->hotplug.funcs = &icp_hpd_funcs;
 		else if (INTEL_PCH_TYPE(display) >= PCH_SPT)
-			display->funcs.hotplug = &spt_hpd_funcs;
+			display->hotplug.funcs = &spt_hpd_funcs;
 		else
-			display->funcs.hotplug = &ilk_hpd_funcs;
+			display->hotplug.funcs = &ilk_hpd_funcs;
 	}
 }
-- 
2.47.3

[PATCH 06/15] drm/i915/display: move dpll funcs under dpll sub-struct

[Jani Nikula]

Move dpll related functions under dpll sub-struct of struct
intel_display.

The funcs sub-struct of struct intel_display seems unnecessary. Instead
of display->funcs.FEATURE, prefer display->FEATURE.funcs.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/display/intel_display_core.h |  6 ++--
 drivers/gpu/drm/i915/display/intel_dpll.c     | 28 +++++++++----------
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 0c2e17edbd5f..5a1aee340728 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -127,6 +127,9 @@ struct intel_audio {
  * dpll, because on some platforms plls share registers.
  */
 struct intel_dpll_global {
+	/* internal dpll functions */
+	const struct intel_dpll_global_funcs *funcs;
+
 	struct mutex lock;
 
 	int num_dpll;
@@ -313,9 +316,6 @@ struct intel_display {
 
 		/* Display CDCLK functions */
 		const struct intel_cdclk_funcs *cdclk;
-
-		/* Display pll funcs */
-		const struct intel_dpll_global_funcs *dpll;
 	} funcs;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index a1aa88598013..f40807a5566b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1735,7 +1735,7 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
 	if (!crtc_state->hw.enable)
 		return 0;
 
-	ret = display->funcs.dpll->crtc_compute_clock(state, crtc);
+	ret = display->dpll.funcs->crtc_compute_clock(state, crtc);
 	if (ret) {
 		drm_dbg_kms(display->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n",
 			    crtc->base.base.id, crtc->base.name);
@@ -1759,10 +1759,10 @@ int intel_dpll_crtc_get_dpll(struct intel_atomic_state *state,
 	if (!crtc_state->hw.enable || crtc_state->intel_dpll)
 		return 0;
 
-	if (!display->funcs.dpll->crtc_get_dpll)
+	if (!display->dpll.funcs->crtc_get_dpll)
 		return 0;
 
-	ret = display->funcs.dpll->crtc_get_dpll(state, crtc);
+	ret = display->dpll.funcs->crtc_get_dpll(state, crtc);
 	if (ret) {
 		drm_dbg_kms(display->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",
 			    crtc->base.base.id, crtc->base.name);
@@ -1776,27 +1776,27 @@ void
 intel_dpll_init_clock_hook(struct intel_display *display)
 {
 	if (HAS_LT_PHY(display))
-		display->funcs.dpll = &xe3plpd_dpll_funcs;
+		display->dpll.funcs = &xe3plpd_dpll_funcs;
 	else if (DISPLAY_VER(display) >= 14)
-		display->funcs.dpll = &mtl_dpll_funcs;
+		display->dpll.funcs = &mtl_dpll_funcs;
 	else if (display->platform.dg2)
-		display->funcs.dpll = &dg2_dpll_funcs;
+		display->dpll.funcs = &dg2_dpll_funcs;
 	else if (DISPLAY_VER(display) >= 9 || HAS_DDI(display))
-		display->funcs.dpll = &hsw_dpll_funcs;
+		display->dpll.funcs = &hsw_dpll_funcs;
 	else if (HAS_PCH_SPLIT(display))
-		display->funcs.dpll = &ilk_dpll_funcs;
+		display->dpll.funcs = &ilk_dpll_funcs;
 	else if (display->platform.cherryview)
-		display->funcs.dpll = &chv_dpll_funcs;
+		display->dpll.funcs = &chv_dpll_funcs;
 	else if (display->platform.valleyview)
-		display->funcs.dpll = &vlv_dpll_funcs;
+		display->dpll.funcs = &vlv_dpll_funcs;
 	else if (display->platform.g4x)
-		display->funcs.dpll = &g4x_dpll_funcs;
+		display->dpll.funcs = &g4x_dpll_funcs;
 	else if (display->platform.pineview)
-		display->funcs.dpll = &pnv_dpll_funcs;
+		display->dpll.funcs = &pnv_dpll_funcs;
 	else if (DISPLAY_VER(display) != 2)
-		display->funcs.dpll = &i9xx_dpll_funcs;
+		display->dpll.funcs = &i9xx_dpll_funcs;
 	else
-		display->funcs.dpll = &i8xx_dpll_funcs;
+		display->dpll.funcs = &i8xx_dpll_funcs;
 }
 
 static bool i9xx_has_pps(struct intel_display *display)
-- 
2.47.3

[PATCH 07/15] drm/i915/display: move cdclk funcs under cdclk sub-struct

[Jani Nikula]

Move cdclk related functions under cdclk sub-struct of struct
intel_display.

The funcs sub-struct of struct intel_display seems unnecessary. Instead
of display->funcs.FEATURE, prefer display->FEATURE.funcs.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c    | 84 +++++++++----------
 .../gpu/drm/i915/display/intel_display_core.h |  6 +-
 2 files changed, 45 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 57d714c81fc4..a1bf01021d65 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -170,27 +170,27 @@ struct intel_cdclk_funcs {
 void intel_cdclk_get_cdclk(struct intel_display *display,
 			   struct intel_cdclk_config *cdclk_config)
 {
-	display->funcs.cdclk->get_cdclk(display, cdclk_config);
+	display->cdclk.funcs->get_cdclk(display, cdclk_config);
 }
 
 static void intel_cdclk_set_cdclk(struct intel_display *display,
 				  const struct intel_cdclk_config *cdclk_config,
 				  enum pipe pipe)
 {
-	display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe);
+	display->cdclk.funcs->set_cdclk(display, cdclk_config, pipe);
 }
 
 static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state)
 {
 	struct intel_display *display = to_intel_display(state);
 
-	return display->funcs.cdclk->modeset_calc_cdclk(state);
+	return display->cdclk.funcs->modeset_calc_cdclk(state);
 }
 
 static u8 intel_cdclk_calc_voltage_level(struct intel_display *display,
 					 int cdclk)
 {
-	return display->funcs.cdclk->calc_voltage_level(cdclk);
+	return display->cdclk.funcs->calc_voltage_level(cdclk);
 }
 
 static void fixed_133mhz_get_cdclk(struct intel_display *display,
@@ -2619,7 +2619,7 @@ static void intel_set_cdclk(struct intel_display *display,
 	if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config))
 		return;
 
-	if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk))
+	if (drm_WARN_ON_ONCE(display->drm, !display->cdclk.funcs->set_cdclk))
 		return;
 
 	intel_cdclk_dump_config(display, cdclk_config, context);
@@ -4042,100 +4042,100 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
 void intel_init_cdclk_hooks(struct intel_display *display)
 {
 	if (DISPLAY_VER(display) >= 35) {
-		display->funcs.cdclk = &xe3lpd_cdclk_funcs;
+		display->cdclk.funcs = &xe3lpd_cdclk_funcs;
 		display->cdclk.table = xe3p_lpd_cdclk_table;
 	} else if (DISPLAY_VER(display) >= 30) {
-		display->funcs.cdclk = &xe3lpd_cdclk_funcs;
+		display->cdclk.funcs = &xe3lpd_cdclk_funcs;
 		display->cdclk.table = xe3lpd_cdclk_table;
 	} else if (DISPLAY_VER(display) >= 20) {
-		display->funcs.cdclk = &rplu_cdclk_funcs;
+		display->cdclk.funcs = &rplu_cdclk_funcs;
 		display->cdclk.table = xe2lpd_cdclk_table;
 	} else if (DISPLAY_VERx100(display) >= 1401) {
-		display->funcs.cdclk = &rplu_cdclk_funcs;
+		display->cdclk.funcs = &rplu_cdclk_funcs;
 		display->cdclk.table = xe2hpd_cdclk_table;
 	} else if (DISPLAY_VER(display) >= 14) {
-		display->funcs.cdclk = &rplu_cdclk_funcs;
+		display->cdclk.funcs = &rplu_cdclk_funcs;
 		display->cdclk.table = mtl_cdclk_table;
 	} else if (display->platform.dg2) {
-		display->funcs.cdclk = &tgl_cdclk_funcs;
+		display->cdclk.funcs = &tgl_cdclk_funcs;
 		display->cdclk.table = dg2_cdclk_table;
 	} else if (display->platform.alderlake_p) {
 		/* Wa_22011320316:adl-p[a0] */
 		if (intel_display_wa(display, INTEL_DISPLAY_WA_22011320316)) {
 			display->cdclk.table = adlp_a_step_cdclk_table;
-			display->funcs.cdclk = &tgl_cdclk_funcs;
+			display->cdclk.funcs = &tgl_cdclk_funcs;
 		} else if (display->platform.alderlake_p_raptorlake_u) {
 			display->cdclk.table = rplu_cdclk_table;
-			display->funcs.cdclk = &rplu_cdclk_funcs;
+			display->cdclk.funcs = &rplu_cdclk_funcs;
 		} else {
 			display->cdclk.table = adlp_cdclk_table;
-			display->funcs.cdclk = &tgl_cdclk_funcs;
+			display->cdclk.funcs = &tgl_cdclk_funcs;
 		}
 	} else if (display->platform.rocketlake) {
-		display->funcs.cdclk = &tgl_cdclk_funcs;
+		display->cdclk.funcs = &tgl_cdclk_funcs;
 		display->cdclk.table = rkl_cdclk_table;
 	} else if (DISPLAY_VER(display) >= 12) {
-		display->funcs.cdclk = &tgl_cdclk_funcs;
+		display->cdclk.funcs = &tgl_cdclk_funcs;
 		display->cdclk.table = icl_cdclk_table;
 	} else if (display->platform.jasperlake || display->platform.elkhartlake) {
-		display->funcs.cdclk = &ehl_cdclk_funcs;
+		display->cdclk.funcs = &ehl_cdclk_funcs;
 		display->cdclk.table = icl_cdclk_table;
 	} else if (DISPLAY_VER(display) >= 11) {
-		display->funcs.cdclk = &icl_cdclk_funcs;
+		display->cdclk.funcs = &icl_cdclk_funcs;
 		display->cdclk.table = icl_cdclk_table;
 	} else if (display->platform.geminilake || display->platform.broxton) {
-		display->funcs.cdclk = &bxt_cdclk_funcs;
+		display->cdclk.funcs = &bxt_cdclk_funcs;
 		if (display->platform.geminilake)
 			display->cdclk.table = glk_cdclk_table;
 		else
 			display->cdclk.table = bxt_cdclk_table;
 	} else if (DISPLAY_VER(display) == 9) {
-		display->funcs.cdclk = &skl_cdclk_funcs;
+		display->cdclk.funcs = &skl_cdclk_funcs;
 	} else if (display->platform.broadwell) {
-		display->funcs.cdclk = &bdw_cdclk_funcs;
+		display->cdclk.funcs = &bdw_cdclk_funcs;
 	} else if (display->platform.haswell) {
-		display->funcs.cdclk = &hsw_cdclk_funcs;
+		display->cdclk.funcs = &hsw_cdclk_funcs;
 	} else if (display->platform.cherryview) {
-		display->funcs.cdclk = &chv_cdclk_funcs;
+		display->cdclk.funcs = &chv_cdclk_funcs;
 	} else if (display->platform.valleyview) {
-		display->funcs.cdclk = &vlv_cdclk_funcs;
+		display->cdclk.funcs = &vlv_cdclk_funcs;
 	} else if (display->platform.sandybridge || display->platform.ivybridge) {
-		display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
+		display->cdclk.funcs = &fixed_400mhz_cdclk_funcs;
 	} else if (display->platform.ironlake) {
-		display->funcs.cdclk = &ilk_cdclk_funcs;
+		display->cdclk.funcs = &ilk_cdclk_funcs;
 	} else if (display->platform.gm45) {
-		display->funcs.cdclk = &gm45_cdclk_funcs;
+		display->cdclk.funcs = &gm45_cdclk_funcs;
 	} else if (display->platform.g45) {
-		display->funcs.cdclk = &g33_cdclk_funcs;
+		display->cdclk.funcs = &g33_cdclk_funcs;
 	} else if (display->platform.i965gm) {
-		display->funcs.cdclk = &i965gm_cdclk_funcs;
+		display->cdclk.funcs = &i965gm_cdclk_funcs;
 	} else if (display->platform.i965g) {
-		display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
+		display->cdclk.funcs = &fixed_400mhz_cdclk_funcs;
 	} else if (display->platform.pineview) {
-		display->funcs.cdclk = &pnv_cdclk_funcs;
+		display->cdclk.funcs = &pnv_cdclk_funcs;
 	} else if (display->platform.g33) {
-		display->funcs.cdclk = &g33_cdclk_funcs;
+		display->cdclk.funcs = &g33_cdclk_funcs;
 	} else if (display->platform.i945gm) {
-		display->funcs.cdclk = &i945gm_cdclk_funcs;
+		display->cdclk.funcs = &i945gm_cdclk_funcs;
 	} else if (display->platform.i945g) {
-		display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
+		display->cdclk.funcs = &fixed_400mhz_cdclk_funcs;
 	} else if (display->platform.i915gm) {
-		display->funcs.cdclk = &i915gm_cdclk_funcs;
+		display->cdclk.funcs = &i915gm_cdclk_funcs;
 	} else if (display->platform.i915g) {
-		display->funcs.cdclk = &i915g_cdclk_funcs;
+		display->cdclk.funcs = &i915g_cdclk_funcs;
 	} else if (display->platform.i865g) {
-		display->funcs.cdclk = &i865g_cdclk_funcs;
+		display->cdclk.funcs = &i865g_cdclk_funcs;
 	} else if (display->platform.i85x) {
-		display->funcs.cdclk = &i85x_cdclk_funcs;
+		display->cdclk.funcs = &i85x_cdclk_funcs;
 	} else if (display->platform.i845g) {
-		display->funcs.cdclk = &i845g_cdclk_funcs;
+		display->cdclk.funcs = &i845g_cdclk_funcs;
 	} else if (display->platform.i830) {
-		display->funcs.cdclk = &i830_cdclk_funcs;
+		display->cdclk.funcs = &i830_cdclk_funcs;
 	}
 
-	if (drm_WARN(display->drm, !display->funcs.cdclk,
+	if (drm_WARN(display->drm, !display->cdclk.funcs,
 		     "Unknown platform. Assuming i830\n"))
-		display->funcs.cdclk = &i830_cdclk_funcs;
+		display->cdclk.funcs = &i830_cdclk_funcs;
 }
 
 int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 5a1aee340728..a319fb97dafa 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -313,9 +313,6 @@ struct intel_display {
 	struct {
 		/* Top level crtc-ish functions */
 		const struct intel_display_funcs *display;
-
-		/* Display CDCLK functions */
-		const struct intel_cdclk_funcs *cdclk;
 	} funcs;
 
 	struct {
@@ -345,6 +342,9 @@ struct intel_display {
 	} bw;
 
 	struct {
+		/* Internal CDCLK functions */
+		const struct intel_cdclk_funcs *funcs;
+
 		/* The current hardware cdclk configuration */
 		struct intel_cdclk_config hw;
 
-- 
2.47.3

[PATCH 08/15] drm/i915/display: move display funcs under modeset sub-struct

[Jani Nikula]

Move generic crtc-ish modeset related functions under a new modeset
sub-struct of struct intel_display. Rename struct intel_display_funcs to
intel_modeset_funcs to make it a little bit more specific. Remove the
funcs sub-struct.

The funcs sub-struct of struct intel_display seems unnecessary. Instead
of display->funcs.FEATURE, prefer display->FEATURE.funcs.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 28 +++++++++----------
 .../gpu/drm/i915/display/intel_display_core.h | 13 ++++-----
 .../drm/i915/display/intel_initial_plane.c    |  4 +--
 .../drm/i915/display/intel_modeset_setup.c    |  2 +-
 4 files changed, 23 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7839e663f7bc..b023cc46c863 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4051,7 +4051,7 @@ bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
-	if (!display->funcs.display->get_pipe_config(crtc, crtc_state))
+	if (!display->modeset.funcs->get_pipe_config(crtc, crtc_state))
 		return false;
 
 	crtc_state->hw.active = true;
@@ -6739,7 +6739,7 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
 
 	intel_psr_notify_pipe_change(state, crtc, true);
 
-	display->funcs.display->crtc_enable(state, crtc);
+	display->modeset.funcs->crtc_enable(state, crtc);
 
 	/* vblanks work again, re-enable pipe CRC. */
 	intel_crtc_enable_pipe_crc(crtc);
@@ -6870,7 +6870,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
 
 	intel_psr_notify_pipe_change(state, crtc, false);
 
-	display->funcs.display->crtc_disable(state, crtc);
+	display->modeset.funcs->crtc_disable(state, crtc);
 
 	for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
 					 intel_crtc_joined_pipe_mask(old_crtc_state)) {
@@ -7522,7 +7522,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	}
 
 	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
-	display->funcs.display->commit_modeset_enables(state);
+	display->modeset.funcs->commit_modeset_enables(state);
 
 	/* FIXME probably need to sequence this properly */
 	intel_program_dpkgc_latency(state);
@@ -8195,7 +8195,7 @@ intel_mode_valid_max_plane_size(struct intel_display *display,
 	return MODE_OK;
 }
 
-static const struct intel_display_funcs skl_display_funcs = {
+static const struct intel_modeset_funcs skl_display_funcs = {
 	.get_pipe_config = hsw_get_pipe_config,
 	.crtc_enable = hsw_crtc_enable,
 	.crtc_disable = hsw_crtc_disable,
@@ -8204,7 +8204,7 @@ static const struct intel_display_funcs skl_display_funcs = {
 	.fixup_initial_plane_config = skl_fixup_initial_plane_config,
 };
 
-static const struct intel_display_funcs ddi_display_funcs = {
+static const struct intel_modeset_funcs ddi_display_funcs = {
 	.get_pipe_config = hsw_get_pipe_config,
 	.crtc_enable = hsw_crtc_enable,
 	.crtc_disable = hsw_crtc_disable,
@@ -8213,7 +8213,7 @@ static const struct intel_display_funcs ddi_display_funcs = {
 	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
 };
 
-static const struct intel_display_funcs pch_split_display_funcs = {
+static const struct intel_modeset_funcs pch_split_display_funcs = {
 	.get_pipe_config = ilk_get_pipe_config,
 	.crtc_enable = ilk_crtc_enable,
 	.crtc_disable = ilk_crtc_disable,
@@ -8222,7 +8222,7 @@ static const struct intel_display_funcs pch_split_display_funcs = {
 	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
 };
 
-static const struct intel_display_funcs vlv_display_funcs = {
+static const struct intel_modeset_funcs vlv_display_funcs = {
 	.get_pipe_config = i9xx_get_pipe_config,
 	.crtc_enable = valleyview_crtc_enable,
 	.crtc_disable = i9xx_crtc_disable,
@@ -8231,7 +8231,7 @@ static const struct intel_display_funcs vlv_display_funcs = {
 	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
 };
 
-static const struct intel_display_funcs i9xx_display_funcs = {
+static const struct intel_modeset_funcs i9xx_display_funcs = {
 	.get_pipe_config = i9xx_get_pipe_config,
 	.crtc_enable = i9xx_crtc_enable,
 	.crtc_disable = i9xx_crtc_disable,
@@ -8247,16 +8247,16 @@ static const struct intel_display_funcs i9xx_display_funcs = {
 void intel_init_display_hooks(struct intel_display *display)
 {
 	if (DISPLAY_VER(display) >= 9) {
-		display->funcs.display = &skl_display_funcs;
+		display->modeset.funcs = &skl_display_funcs;
 	} else if (HAS_DDI(display)) {
-		display->funcs.display = &ddi_display_funcs;
+		display->modeset.funcs = &ddi_display_funcs;
 	} else if (HAS_PCH_SPLIT(display)) {
-		display->funcs.display = &pch_split_display_funcs;
+		display->modeset.funcs = &pch_split_display_funcs;
 	} else if (display->platform.cherryview ||
 		   display->platform.valleyview) {
-		display->funcs.display = &vlv_display_funcs;
+		display->modeset.funcs = &vlv_display_funcs;
 	} else {
-		display->funcs.display = &i9xx_display_funcs;
+		display->modeset.funcs = &i9xx_display_funcs;
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index a319fb97dafa..796517e7bc6c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -59,7 +59,7 @@ struct task_struct;
 /* Amount of PSF GV points, BSpec precisely defines this */
 #define I915_NUM_PSF_GV_POINTS 3
 
-struct intel_display_funcs {
+struct intel_modeset_funcs {
 	/*
 	 * Returns the active state of the crtc, and if the crtc is active,
 	 * fills out the pipe-config with the hw state.
@@ -309,12 +309,6 @@ struct intel_display {
 	/* list of all intel_crtcs sorted by pipe */
 	struct list_head pipe_list;
 
-	/* Display functions */
-	struct {
-		/* Top level crtc-ish functions */
-		const struct intel_display_funcs *display;
-	} funcs;
-
 	struct {
 		bool any_task_allowed;
 		struct task_struct *allowed_task;
@@ -518,6 +512,11 @@ struct intel_display {
 		u32 pipestat_irq_mask[I915_MAX_PIPES];
 	} irq;
 
+	struct {
+		/* Top level crtc-ish functions */
+		const struct intel_modeset_funcs *funcs;
+	} modeset;
+
 	struct {
 		/* protected by wm.wm_mutex */
 		u16 linetime[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/display/intel_initial_plane.c b/drivers/gpu/drm/i915/display/intel_initial_plane.c
index 0e5cd45f01cc..034fe199c2a1 100644
--- a/drivers/gpu/drm/i915/display/intel_initial_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_initial_plane.c
@@ -224,7 +224,7 @@ void intel_initial_plane_config(struct intel_display *display)
 		 * can even allow for smooth boot transitions if the BIOS
 		 * fb is large enough for the active pipe configuration.
 		 */
-		display->funcs.display->get_initial_plane_config(crtc, plane_config);
+		display->modeset.funcs->get_initial_plane_config(crtc, plane_config);
 
 		/*
 		 * If the fb is shared between multiple heads, we'll
@@ -232,7 +232,7 @@ void intel_initial_plane_config(struct intel_display *display)
 		 */
 		intel_find_initial_plane_obj(crtc, &all_plane_configs);
 
-		if (display->funcs.display->fixup_initial_plane_config(crtc, plane_config))
+		if (display->modeset.funcs->fixup_initial_plane_config(crtc, plane_config))
 			intel_initial_plane_vblank_wait(crtc);
 
 		plane_config_fini(display, plane_config);
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 40a65a0d7ec7..4c646b1bd0ee 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -83,7 +83,7 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
 		drm_WARN_ON(display->drm, IS_ERR(temp_crtc_state) || ret);
 	}
 
-	display->funcs.display->crtc_disable(to_intel_atomic_state(state), crtc);
+	display->modeset.funcs->crtc_disable(to_intel_atomic_state(state), crtc);
 
 	drm_atomic_state_put(state);
 
-- 
2.47.3

[PATCH 09/15] drm/i915/irq: deduplicate dg1_de_irq_postinstall() and gen11_de_irq_postinstall()

[Jani Nikula]

dg1_de_irq_postinstall() and gen11_de_irq_postinstall() are exactly the
same. Remove dg1_de_irq_postinstall() and call
gen11_de_irq_postinstall() instead.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_irq.c | 9 ---------
 drivers/gpu/drm/i915/display/intel_display_irq.h | 1 -
 drivers/gpu/drm/i915/i915_irq.c                  | 2 +-
 3 files changed, 1 insertion(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index b5bfdebc66ca..bf4b5e7b6011 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -2449,15 +2449,6 @@ void gen11_de_irq_postinstall(struct intel_display *display)
 	intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
 }
 
-void dg1_de_irq_postinstall(struct intel_display *display)
-{
-	if (!HAS_DISPLAY(display))
-		return;
-
-	gen8_de_irq_postinstall(display);
-	intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
-}
-
 struct intel_display_irq_funcs {
 	void (*reset)(struct intel_display *display);
 };
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index b25d180254d7..e2b1674fae06 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -71,7 +71,6 @@ void vlv_display_irq_postinstall(struct intel_display *display);
 void ilk_de_irq_postinstall(struct intel_display *display);
 void gen8_de_irq_postinstall(struct intel_display *display);
 void gen11_de_irq_postinstall(struct intel_display *display);
-void dg1_de_irq_postinstall(struct intel_display *display);
 
 u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
 void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d4d8dd0a4174..ef9eadf38a53 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -778,7 +778,7 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
 
-	dg1_de_irq_postinstall(display);
+	gen11_de_irq_postinstall(display);
 
 	dg1_master_intr_enable(intel_uncore_regs(uncore));
 	intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
-- 
2.47.3

[PATCH 10/15] drm/i915/irq: move VLV/CHV LPE irq handler call after irq acks

[Jani Nikula]

The location of the intel_lpe_audio_irq_handler() call seems too
early. Group the handler calls together slightly later.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ef9eadf38a53..1c87f56d668d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -282,10 +282,6 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 		 * signalled in IIR */
 		i9xx_pipestat_irq_ack(display, iir, pipe_stats);
 
-		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
-			   I915_LPE_PIPE_B_INTERRUPT))
-			intel_lpe_audio_irq_handler(display);
-
 		/*
 		 * VLV_IIR is single buffered, and reflects the level
 		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
@@ -301,6 +297,10 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 		if (pm_iir)
 			gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir);
 
+		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
+			   I915_LPE_PIPE_B_INTERRUPT))
+			intel_lpe_audio_irq_handler(display);
+
 		if (hotplug_status)
 			i9xx_hpd_irq_handler(display, hotplug_status);
 
@@ -372,11 +372,6 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 		 * signalled in IIR */
 		i9xx_pipestat_irq_ack(display, iir, pipe_stats);
 
-		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
-			   I915_LPE_PIPE_B_INTERRUPT |
-			   I915_LPE_PIPE_C_INTERRUPT))
-			intel_lpe_audio_irq_handler(display);
-
 		/*
 		 * VLV_IIR is single buffered, and reflects the level
 		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
@@ -387,6 +382,11 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
 		intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
 
+		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
+			   I915_LPE_PIPE_B_INTERRUPT |
+			   I915_LPE_PIPE_C_INTERRUPT))
+			intel_lpe_audio_irq_handler(display);
+
 		if (hotplug_status)
 			i9xx_hpd_irq_handler(display, hotplug_status);
 
-- 
2.47.3

[PATCH 11/15] drm/i915/irq: constify pipe stats parameters

[Jani Nikula]

The pipe stat irq handling doesn't need to modify the pipe stats
arrays. Make them const.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_irq.c | 6 +++---
 drivers/gpu/drm/i915/display/intel_display_irq.h | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index bf4b5e7b6011..d30b063714b0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -597,7 +597,7 @@ void i9xx_pipestat_irq_ack(struct intel_display *display,
 }
 
 void i915_pipestat_irq_handler(struct intel_display *display,
-			       u32 iir, u32 pipe_stats[I915_MAX_PIPES])
+			       u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
 {
 	bool blc_event = false;
 	enum pipe pipe;
@@ -621,7 +621,7 @@ void i915_pipestat_irq_handler(struct intel_display *display,
 }
 
 void i965_pipestat_irq_handler(struct intel_display *display,
-			       u32 iir, u32 pipe_stats[I915_MAX_PIPES])
+			       u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
 {
 	bool blc_event = false;
 	enum pipe pipe;
@@ -648,7 +648,7 @@ void i965_pipestat_irq_handler(struct intel_display *display,
 }
 
 void valleyview_pipestat_irq_handler(struct intel_display *display,
-				     u32 pipe_stats[I915_MAX_PIPES])
+				     const u32 pipe_stats[I915_MAX_PIPES])
 {
 	enum pipe pipe;
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index e2b1674fae06..d25b9ea4272b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -78,9 +78,9 @@ void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 st
 
 void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
 
-void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
-void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
-void valleyview_pipestat_irq_handler(struct intel_display *display, u32 pipe_stats[I915_MAX_PIPES]);
+void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
+void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
+void valleyview_pipestat_irq_handler(struct intel_display *display, const u32 pipe_stats[I915_MAX_PIPES]);
 
 void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt);
 void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);
-- 
2.47.3

[PATCH 12/15] drm/i915/irq: add display irq funcs, start with intel_display_irq_reset()

[Jani Nikula]

Introduce display irq hooks with struct intel_display_irq_funcs, and add
the ->reset hook as the first thing. Call the reset hooks from i915 and
xe core via intel_display_irq_reset().

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/display/intel_display_core.h |  3 ++
 .../gpu/drm/i915/display/intel_display_irq.c  | 52 +++++++++++++++++--
 .../gpu/drm/i915/display/intel_display_irq.h  |  6 +--
 drivers/gpu/drm/i915/i915_irq.c               | 16 +++---
 drivers/gpu/drm/xe/display/xe_display.c       |  2 +-
 5 files changed, 60 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 796517e7bc6c..7bc2ff11b658 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -475,6 +475,9 @@ struct intel_display {
 	} ips;
 
 	struct {
+		/* internal display irq functions */
+		const struct intel_display_irq_funcs *funcs;
+
 		/* protects the irq masks */
 		spinlock_t lock;
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index d30b063714b0..7505652257d8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1947,7 +1947,7 @@ static void _vlv_display_irq_reset(struct intel_display *display)
 	display->irq.vlv_imr_mask = ~0u;
 }
 
-void vlv_display_irq_reset(struct intel_display *display)
+static void vlv_display_irq_reset(struct intel_display *display)
 {
 	spin_lock_irq(&display->irq.lock);
 	if (display->irq.vlv_display_irqs_enabled)
@@ -1955,7 +1955,7 @@ void vlv_display_irq_reset(struct intel_display *display)
 	spin_unlock_irq(&display->irq.lock);
 }
 
-void i9xx_display_irq_reset(struct intel_display *display)
+static void i9xx_display_irq_reset(struct intel_display *display)
 {
 	if (HAS_HOTPLUG(display)) {
 		i915_hotplug_interrupt_update(display, 0xffffffff, 0);
@@ -2076,7 +2076,7 @@ static void ibx_display_irq_reset(struct intel_display *display)
 		intel_de_write(display, SERR_INT, 0xffffffff);
 }
 
-void ilk_display_irq_reset(struct intel_display *display)
+static void ilk_display_irq_reset(struct intel_display *display)
 {
 	irq_reset(display, DE_IRQ_REGS);
 	display->irq.ilk_de_imr_mask = ~0u;
@@ -2092,7 +2092,7 @@ void ilk_display_irq_reset(struct intel_display *display)
 	ibx_display_irq_reset(display);
 }
 
-void gen8_display_irq_reset(struct intel_display *display)
+static void gen8_display_irq_reset(struct intel_display *display)
 {
 	enum pipe pipe;
 
@@ -2114,7 +2114,7 @@ void gen8_display_irq_reset(struct intel_display *display)
 		ibx_display_irq_reset(display);
 }
 
-void gen11_display_irq_reset(struct intel_display *display)
+static void gen11_display_irq_reset(struct intel_display *display)
 {
 	enum pipe pipe;
 	u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
@@ -2453,6 +2453,35 @@ struct intel_display_irq_funcs {
 	void (*reset)(struct intel_display *display);
 };
 
+struct intel_display_irq_funcs gen11_display_irq_funcs = {
+	.reset = gen11_display_irq_reset,
+};
+
+struct intel_display_irq_funcs gen8_display_irq_funcs = {
+	.reset = gen8_display_irq_reset,
+};
+
+struct intel_display_irq_funcs vlv_display_irq_funcs = {
+	.reset = vlv_display_irq_reset,
+};
+
+struct intel_display_irq_funcs ilk_display_irq_funcs = {
+	.reset = ilk_display_irq_reset,
+};
+
+struct intel_display_irq_funcs i965_display_irq_funcs = {
+	.reset = i9xx_display_irq_reset,
+};
+
+struct intel_display_irq_funcs i915_display_irq_funcs = {
+	.reset = i9xx_display_irq_reset,
+};
+
+void intel_display_irq_reset(struct intel_display *display)
+{
+	display->irq.funcs->reset(display);
+}
+
 void intel_display_irq_init(struct intel_display *display)
 {
 	spin_lock_init(&display->irq.lock);
@@ -2463,6 +2492,19 @@ void intel_display_irq_init(struct intel_display *display)
 
 	INIT_WORK(&display->irq.vblank_notify_work,
 		  intel_display_vblank_notify_work);
+
+	if (DISPLAY_VER(display) >= 11)
+		display->irq.funcs = &gen11_display_irq_funcs;
+	else if (display->platform.cherryview || display->platform.valleyview)
+		display->irq.funcs = &vlv_display_irq_funcs;
+	else if (DISPLAY_VER(display) >= 8)
+		display->irq.funcs = &gen8_display_irq_funcs;
+	else if (DISPLAY_VER(display) >= 5)
+		display->irq.funcs = &ilk_display_irq_funcs;
+	else if (DISPLAY_VER(display) == 4)
+		display->irq.funcs = &i965_display_irq_funcs;
+	else
+		display->irq.funcs = &i915_display_irq_funcs;
 }
 
 struct intel_display_irq_snapshot {
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index d25b9ea4272b..21b2145656cd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -58,11 +58,7 @@ void gen11_display_irq_handler(struct intel_display *display);
 u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
 void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
 
-void i9xx_display_irq_reset(struct intel_display *display);
-void ilk_display_irq_reset(struct intel_display *display);
-void vlv_display_irq_reset(struct intel_display *display);
-void gen8_display_irq_reset(struct intel_display *display);
-void gen11_display_irq_reset(struct intel_display *display);
+void intel_display_irq_reset(struct intel_display *display);
 
 u32 i9xx_display_irq_enable_mask(struct intel_display *display);
 void i915_display_irq_postinstall(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1c87f56d668d..7e0ec9294d70 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -640,7 +640,7 @@ static void ilk_irq_reset(struct drm_i915_private *dev_priv)
 	struct intel_display *display = dev_priv->display;
 
 	/* The master interrupt enable is in DEIER, reset display irq first */
-	ilk_display_irq_reset(display);
+	intel_display_irq_reset(display);
 	gen5_gt_irq_reset(to_gt(dev_priv));
 }
 
@@ -653,7 +653,7 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
 
 	gen5_gt_irq_reset(to_gt(dev_priv));
 
-	vlv_display_irq_reset(display);
+	intel_display_irq_reset(display);
 }
 
 static void gen8_irq_reset(struct drm_i915_private *dev_priv)
@@ -664,7 +664,7 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
 	gen8_master_intr_disable(intel_uncore_regs(uncore));
 
 	gen8_gt_irq_reset(to_gt(dev_priv));
-	gen8_display_irq_reset(display);
+	intel_display_irq_reset(display);
 	gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
 }
 
@@ -677,7 +677,7 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv)
 	gen11_master_intr_disable(intel_uncore_regs(&dev_priv->uncore));
 
 	gen11_gt_irq_reset(gt);
-	gen11_display_irq_reset(display);
+	intel_display_irq_reset(display);
 
 	gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
 	gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
@@ -695,7 +695,7 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv)
 	for_each_gt(gt, dev_priv, i)
 		gen11_gt_irq_reset(gt);
 
-	gen11_display_irq_reset(display);
+	intel_display_irq_reset(display);
 
 	gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
 	gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
@@ -715,7 +715,7 @@ static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
 
 	gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
 
-	vlv_display_irq_reset(display);
+	intel_display_irq_reset(display);
 }
 
 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -864,7 +864,7 @@ static void i915_irq_reset(struct drm_i915_private *dev_priv)
 	struct intel_display *display = dev_priv->display;
 	struct intel_uncore *uncore = &dev_priv->uncore;
 
-	i9xx_display_irq_reset(display);
+	intel_display_irq_reset(display);
 
 	gen2_error_reset(uncore, GEN2_ERROR_REGS);
 	gen2_irq_reset(uncore, GEN2_IRQ_REGS);
@@ -951,7 +951,7 @@ static void i965_irq_reset(struct drm_i915_private *dev_priv)
 	struct intel_display *display = dev_priv->display;
 	struct intel_uncore *uncore = &dev_priv->uncore;
 
-	i9xx_display_irq_reset(display);
+	intel_display_irq_reset(display);
 
 	gen2_error_reset(uncore, GEN2_ERROR_REGS);
 	gen2_irq_reset(uncore, GEN2_IRQ_REGS);
diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index 0747044f7c2a..d6a4546fbe94 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -235,7 +235,7 @@ void xe_display_irq_reset(struct xe_device *xe)
 	if (!xe->info.probe_display)
 		return;
 
-	gen11_display_irq_reset(display);
+	intel_display_irq_reset(display);
 }
 
 void xe_display_irq_postinstall(struct xe_device *xe)
-- 
2.47.3

[PATCH 13/15] drm/i915/irq: add intel_display_irq_postinstall() to irq funcs

[Jani Nikula]

Call the platform specific display irq postinstall hooks via
intel_display_irq_postinstall().

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/display/intel_display_irq.c  | 24 ++++++++++++++-----
 .../gpu/drm/i915/display/intel_display_irq.h  |  7 +-----
 drivers/gpu/drm/i915/i915_irq.c               | 16 ++++++-------
 drivers/gpu/drm/xe/display/xe_display.c       |  2 +-
 4 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 7505652257d8..6ba094a0df66 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1981,7 +1981,7 @@ u32 i9xx_display_irq_enable_mask(struct intel_display *display)
 	return enable_mask;
 }
 
-void i915_display_irq_postinstall(struct intel_display *display)
+static void i915_display_irq_postinstall(struct intel_display *display)
 {
 	/*
 	 * Interrupt setup is already guaranteed to be single-threaded, this is
@@ -1995,7 +1995,7 @@ void i915_display_irq_postinstall(struct intel_display *display)
 	i915_enable_asle_pipestat(display);
 }
 
-void i965_display_irq_postinstall(struct intel_display *display)
+static void i965_display_irq_postinstall(struct intel_display *display)
 {
 	/*
 	 * Interrupt setup is already guaranteed to be single-threaded, this is
@@ -2057,7 +2057,7 @@ static void _vlv_display_irq_postinstall(struct intel_display *display)
 	irq_init(display, VLV_IRQ_REGS, display->irq.vlv_imr_mask, enable_mask);
 }
 
-void vlv_display_irq_postinstall(struct intel_display *display)
+static void vlv_display_irq_postinstall(struct intel_display *display)
 {
 	spin_lock_irq(&display->irq.lock);
 	if (display->irq.vlv_display_irqs_enabled)
@@ -2268,7 +2268,7 @@ void valleyview_disable_display_irqs(struct intel_display *display)
 	spin_unlock_irq(&display->irq.lock);
 }
 
-void ilk_de_irq_postinstall(struct intel_display *display)
+static void ilk_de_irq_postinstall(struct intel_display *display)
 {
 	u32 display_mask, extra_mask;
 
@@ -2312,7 +2312,7 @@ void ilk_de_irq_postinstall(struct intel_display *display)
 static void mtp_irq_postinstall(struct intel_display *display);
 static void icp_irq_postinstall(struct intel_display *display);
 
-void gen8_de_irq_postinstall(struct intel_display *display)
+static void gen8_de_irq_postinstall(struct intel_display *display)
 {
 	u32 de_pipe_masked = gen8_de_pipe_fault_mask(display) |
 		GEN8_PIPE_CDCLK_CRC_DONE;
@@ -2439,7 +2439,7 @@ static void icp_irq_postinstall(struct intel_display *display)
 	irq_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);
 }
 
-void gen11_de_irq_postinstall(struct intel_display *display)
+static void gen11_de_irq_postinstall(struct intel_display *display)
 {
 	if (!HAS_DISPLAY(display))
 		return;
@@ -2451,30 +2451,37 @@ void gen11_de_irq_postinstall(struct intel_display *display)
 
 struct intel_display_irq_funcs {
 	void (*reset)(struct intel_display *display);
+	void (*postinstall)(struct intel_display *display);
 };
 
 struct intel_display_irq_funcs gen11_display_irq_funcs = {
 	.reset = gen11_display_irq_reset,
+	.postinstall = gen11_de_irq_postinstall,
 };
 
 struct intel_display_irq_funcs gen8_display_irq_funcs = {
 	.reset = gen8_display_irq_reset,
+	.postinstall = gen8_de_irq_postinstall,
 };
 
 struct intel_display_irq_funcs vlv_display_irq_funcs = {
 	.reset = vlv_display_irq_reset,
+	.postinstall = vlv_display_irq_postinstall,
 };
 
 struct intel_display_irq_funcs ilk_display_irq_funcs = {
 	.reset = ilk_display_irq_reset,
+	.postinstall = ilk_de_irq_postinstall,
 };
 
 struct intel_display_irq_funcs i965_display_irq_funcs = {
 	.reset = i9xx_display_irq_reset,
+	.postinstall = i965_display_irq_postinstall,
 };
 
 struct intel_display_irq_funcs i915_display_irq_funcs = {
 	.reset = i9xx_display_irq_reset,
+	.postinstall = i915_display_irq_postinstall,
 };
 
 void intel_display_irq_reset(struct intel_display *display)
@@ -2482,6 +2489,11 @@ void intel_display_irq_reset(struct intel_display *display)
 	display->irq.funcs->reset(display);
 }
 
+void intel_display_irq_postinstall(struct intel_display *display)
+{
+	display->irq.funcs->postinstall(display);
+}
+
 void intel_display_irq_init(struct intel_display *display)
 {
 	spin_lock_init(&display->irq.lock);
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index 21b2145656cd..fd9873ce9755 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -59,14 +59,9 @@ u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
 void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
 
 void intel_display_irq_reset(struct intel_display *display);
+void intel_display_irq_postinstall(struct intel_display *display);
 
 u32 i9xx_display_irq_enable_mask(struct intel_display *display);
-void i915_display_irq_postinstall(struct intel_display *display);
-void i965_display_irq_postinstall(struct intel_display *display);
-void vlv_display_irq_postinstall(struct intel_display *display);
-void ilk_de_irq_postinstall(struct intel_display *display);
-void gen8_de_irq_postinstall(struct intel_display *display);
-void gen11_de_irq_postinstall(struct intel_display *display);
 
 u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
 void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7e0ec9294d70..7ffa0e8c5608 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -724,7 +724,7 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen5_gt_irq_postinstall(to_gt(dev_priv));
 
-	ilk_de_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 }
 
 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -733,7 +733,7 @@ static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen5_gt_irq_postinstall(to_gt(dev_priv));
 
-	vlv_display_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 
 	intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
 	intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
@@ -744,7 +744,7 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
 	struct intel_display *display = dev_priv->display;
 
 	gen8_gt_irq_postinstall(to_gt(dev_priv));
-	gen8_de_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 
 	gen8_master_intr_enable(intel_uncore_regs(&dev_priv->uncore));
 }
@@ -757,7 +757,7 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
 	u32 gu_misc_masked = GEN11_GU_MISC_GSE;
 
 	gen11_gt_irq_postinstall(gt);
-	gen11_de_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 
 	gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
 
@@ -778,7 +778,7 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
 
-	gen11_de_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 
 	dg1_master_intr_enable(intel_uncore_regs(uncore));
 	intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
@@ -790,7 +790,7 @@ static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen8_gt_irq_postinstall(to_gt(dev_priv));
 
-	vlv_display_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 
 	intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
 	intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
@@ -888,7 +888,7 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->gen2_imr_mask, enable_mask);
 
-	i915_display_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 }
 
 static irqreturn_t i915_irq_handler(int irq, void *arg)
@@ -997,7 +997,7 @@ static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->gen2_imr_mask, enable_mask);
 
-	i965_display_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 }
 
 static irqreturn_t i965_irq_handler(int irq, void *arg)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index d6a4546fbe94..736a5e6938d6 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -245,7 +245,7 @@ void xe_display_irq_postinstall(struct xe_device *xe)
 	if (!xe->info.probe_display)
 		return;
 
-	gen11_de_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 }
 
 static bool suspend_to_idle(void)
-- 
2.47.3

[PATCH 14/15] drm/i915/irq: add intel_display_irq_ack() to irq funcs

[Jani Nikula]

Some platforms have a separate step for acking display irqs. Call the
platform specific display irq ack hooks, if any, via
intel_display_irq_ack().

Introduce struct intel_display_irq_state to group together all the data
the ack hooks need. In the follow-up, this state will be passed on to a
shared handler function.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/display/intel_display_irq.c  |  42 ++++-
 .../gpu/drm/i915/display/intel_display_irq.h  |  12 +-
 drivers/gpu/drm/i915/i915_irq.c               | 144 +++++++-----------
 3 files changed, 102 insertions(+), 96 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 6ba094a0df66..662081e274bf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -529,8 +529,8 @@ static void i9xx_pipestat_irq_reset(struct intel_display *display)
 	}
 }
 
-void i9xx_pipestat_irq_ack(struct intel_display *display,
-			   u32 iir, u32 pipe_stats[I915_MAX_PIPES])
+static void i9xx_pipestat_irq_ack(struct intel_display *display,
+				  u32 iir, u32 pipe_stats[I915_MAX_PIPES])
 {
 	enum pipe pipe;
 
@@ -1898,8 +1898,8 @@ static void vlv_page_table_error_irq_handler(struct intel_display *display, u32
 	}
 }
 
-void vlv_display_error_irq_ack(struct intel_display *display,
-			       u32 *eir, u32 *dpinvgtt)
+static void vlv_display_error_irq_ack(struct intel_display *display,
+				      u32 *eir, u32 *dpinvgtt)
 {
 	u32 emr;
 
@@ -2010,6 +2010,16 @@ static void i965_display_irq_postinstall(struct intel_display *display)
 	i915_enable_asle_pipestat(display);
 }
 
+static void i9xx_display_irq_ack(struct intel_display *display,
+				 struct intel_display_irq_state *state)
+{
+	if (state->iir & I915_DISPLAY_PORT_INTERRUPT)
+		state->hotplug_status = i9xx_hpd_irq_ack(display);
+
+	/* Call regardless, as some status bits might not be signalled in IIR */
+	i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
+}
+
 static u32 vlv_error_mask(void)
 {
 	/* TODO enable other errors too? */
@@ -2065,6 +2075,19 @@ static void vlv_display_irq_postinstall(struct intel_display *display)
 	spin_unlock_irq(&display->irq.lock);
 }
 
+static void vlv_display_irq_ack(struct intel_display *display,
+				struct intel_display_irq_state *state)
+{
+	if (state->iir & I915_DISPLAY_PORT_INTERRUPT)
+		state->hotplug_status = i9xx_hpd_irq_ack(display);
+
+	if (state->iir & I915_MASTER_ERROR_INTERRUPT)
+		vlv_display_error_irq_ack(display, &state->eir, &state->dpinvgtt);
+
+	/* Call regardless, as some status bits might not be signalled in IIR */
+	i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
+}
+
 static void ibx_display_irq_reset(struct intel_display *display)
 {
 	if (HAS_PCH_NOP(display))
@@ -2452,6 +2475,7 @@ static void gen11_de_irq_postinstall(struct intel_display *display)
 struct intel_display_irq_funcs {
 	void (*reset)(struct intel_display *display);
 	void (*postinstall)(struct intel_display *display);
+	void (*ack)(struct intel_display *display, struct intel_display_irq_state *state);
 };
 
 struct intel_display_irq_funcs gen11_display_irq_funcs = {
@@ -2467,6 +2491,7 @@ struct intel_display_irq_funcs gen8_display_irq_funcs = {
 struct intel_display_irq_funcs vlv_display_irq_funcs = {
 	.reset = vlv_display_irq_reset,
 	.postinstall = vlv_display_irq_postinstall,
+	.ack = vlv_display_irq_ack,
 };
 
 struct intel_display_irq_funcs ilk_display_irq_funcs = {
@@ -2477,11 +2502,13 @@ struct intel_display_irq_funcs ilk_display_irq_funcs = {
 struct intel_display_irq_funcs i965_display_irq_funcs = {
 	.reset = i9xx_display_irq_reset,
 	.postinstall = i965_display_irq_postinstall,
+	.ack = i9xx_display_irq_ack,
 };
 
 struct intel_display_irq_funcs i915_display_irq_funcs = {
 	.reset = i9xx_display_irq_reset,
 	.postinstall = i915_display_irq_postinstall,
+	.ack = i9xx_display_irq_ack,
 };
 
 void intel_display_irq_reset(struct intel_display *display)
@@ -2494,6 +2521,13 @@ void intel_display_irq_postinstall(struct intel_display *display)
 	display->irq.funcs->postinstall(display);
 }
 
+void intel_display_irq_ack(struct intel_display *display,
+			   struct intel_display_irq_state *state)
+{
+	if (display->irq.funcs->ack)
+		display->irq.funcs->ack(display, state);
+}
+
 void intel_display_irq_init(struct intel_display *display)
 {
 	spin_lock_init(&display->irq.lock);
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index fd9873ce9755..3773a31e48f2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -58,8 +58,17 @@ void gen11_display_irq_handler(struct intel_display *display);
 u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
 void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
 
+struct intel_display_irq_state {
+	u32 iir;
+	u32 eir;
+	u32 hotplug_status;
+	u32 dpinvgtt;
+	u32 pipe_stats[I915_MAX_PIPES];
+};
+
 void intel_display_irq_reset(struct intel_display *display);
 void intel_display_irq_postinstall(struct intel_display *display);
+void intel_display_irq_ack(struct intel_display *display, struct intel_display_irq_state *state);
 
 u32 i9xx_display_irq_enable_mask(struct intel_display *display);
 
@@ -67,13 +76,10 @@ u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
 void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
 void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
 
-void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
-
 void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
 void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
 void valleyview_pipestat_irq_handler(struct intel_display *display, const u32 pipe_stats[I915_MAX_PIPES]);
 
-void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt);
 void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);
 
 void intel_display_irq_init(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7ffa0e8c5608..bb65ce9d09b2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -236,17 +236,15 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 
 	do {
-		u32 iir, gt_iir, pm_iir;
-		u32 eir = 0, dpinvgtt = 0;
-		u32 pipe_stats[I915_MAX_PIPES] = {};
-		u32 hotplug_status = 0;
+		struct intel_display_irq_state state = {};
+		u32 gt_iir, pm_iir;
 		u32 ier = 0;
 
 		gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR);
 		pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR);
-		iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
+		state.iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
 
-		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
+		if (gt_iir == 0 && pm_iir == 0 && state.iir == 0)
 			break;
 
 		ret = IRQ_HANDLED;
@@ -272,22 +270,14 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 		if (pm_iir)
 			intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir);
 
-		if (iir & I915_DISPLAY_PORT_INTERRUPT)
-			hotplug_status = i9xx_hpd_irq_ack(display);
-
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
-			vlv_display_error_irq_ack(display, &eir, &dpinvgtt);
-
-		/* Call regardless, as some status bits might not be
-		 * signalled in IIR */
-		i9xx_pipestat_irq_ack(display, iir, pipe_stats);
+		intel_display_irq_ack(display, &state);
 
 		/*
 		 * VLV_IIR is single buffered, and reflects the level
 		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
 		 */
-		if (iir)
-			intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
+		if (state.iir)
+			intel_uncore_write(&dev_priv->uncore, VLV_IIR, state.iir);
 
 		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
 		intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
@@ -297,17 +287,17 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 		if (pm_iir)
 			gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir);
 
-		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
-			   I915_LPE_PIPE_B_INTERRUPT))
+		if (state.iir & (I915_LPE_PIPE_A_INTERRUPT |
+				 I915_LPE_PIPE_B_INTERRUPT))
 			intel_lpe_audio_irq_handler(display);
 
-		if (hotplug_status)
-			i9xx_hpd_irq_handler(display, hotplug_status);
+		if (state.hotplug_status)
+			i9xx_hpd_irq_handler(display, state.hotplug_status);
 
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
-			vlv_display_error_irq_handler(display, eir, dpinvgtt);
+		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
+			vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
 
-		valleyview_pipestat_irq_handler(display, pipe_stats);
+		valleyview_pipestat_irq_handler(display, state.pipe_stats);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, ret);
@@ -330,16 +320,14 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 
 	do {
-		u32 master_ctl, iir;
-		u32 eir = 0, dpinvgtt = 0;
-		u32 pipe_stats[I915_MAX_PIPES] = {};
-		u32 hotplug_status = 0;
+		struct intel_display_irq_state state = {};
+		u32 master_ctl;
 		u32 ier = 0;
 
 		master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
-		iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
+		state.iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
 
-		if (master_ctl == 0 && iir == 0)
+		if (master_ctl == 0 && state.iir == 0)
 			break;
 
 		ret = IRQ_HANDLED;
@@ -362,38 +350,30 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 
 		gen8_gt_irq_handler(to_gt(dev_priv), master_ctl);
 
-		if (iir & I915_DISPLAY_PORT_INTERRUPT)
-			hotplug_status = i9xx_hpd_irq_ack(display);
-
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
-			vlv_display_error_irq_ack(display, &eir, &dpinvgtt);
-
-		/* Call regardless, as some status bits might not be
-		 * signalled in IIR */
-		i9xx_pipestat_irq_ack(display, iir, pipe_stats);
+		intel_display_irq_ack(display, &state);
 
 		/*
 		 * VLV_IIR is single buffered, and reflects the level
 		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
 		 */
-		if (iir)
-			intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
+		if (state.iir)
+			intel_uncore_write(&dev_priv->uncore, VLV_IIR, state.iir);
 
 		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
 		intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
 
-		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
-			   I915_LPE_PIPE_B_INTERRUPT |
-			   I915_LPE_PIPE_C_INTERRUPT))
+		if (state.iir & (I915_LPE_PIPE_A_INTERRUPT |
+				 I915_LPE_PIPE_B_INTERRUPT |
+				 I915_LPE_PIPE_C_INTERRUPT))
 			intel_lpe_audio_irq_handler(display);
 
-		if (hotplug_status)
-			i9xx_hpd_irq_handler(display, hotplug_status);
+		if (state.hotplug_status)
+			i9xx_hpd_irq_handler(display, state.hotplug_status);
 
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
-			vlv_display_error_irq_handler(display, eir, dpinvgtt);
+		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
+			vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
 
-		valleyview_pipestat_irq_handler(display, pipe_stats);
+		valleyview_pipestat_irq_handler(display, state.pipe_stats);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, ret);
@@ -904,39 +884,32 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 
 	do {
-		u32 pipe_stats[I915_MAX_PIPES] = {};
+		struct intel_display_irq_state state = {};
 		u32 eir = 0, eir_stuck = 0;
-		u32 hotplug_status = 0;
-		u32 iir;
 
-		iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
-		if (iir == 0)
+		state.iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
+		if (state.iir == 0)
 			break;
 
 		ret = IRQ_HANDLED;
 
-		if (iir & I915_DISPLAY_PORT_INTERRUPT)
-			hotplug_status = i9xx_hpd_irq_ack(display);
-
-		/* Call regardless, as some status bits might not be
-		 * signalled in IIR */
-		i9xx_pipestat_irq_ack(display, iir, pipe_stats);
+		intel_display_irq_ack(display, &state);
 
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
+		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
 
-		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
+		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, state.iir);
 
-		if (iir & I915_USER_INTERRUPT)
-			intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir);
+		if (state.iir & I915_USER_INTERRUPT)
+			intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], state.iir);
 
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
+		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
 
-		if (hotplug_status)
-			i9xx_hpd_irq_handler(display, hotplug_status);
+		if (state.hotplug_status)
+			i9xx_hpd_irq_handler(display, state.hotplug_status);
 
-		i915_pipestat_irq_handler(display, iir, pipe_stats);
+		i915_pipestat_irq_handler(display, state.iir, state.pipe_stats);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, ret);
@@ -1013,44 +986,37 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 
 	do {
-		u32 pipe_stats[I915_MAX_PIPES] = {};
+		struct intel_display_irq_state state = {};
 		u32 eir = 0, eir_stuck = 0;
-		u32 hotplug_status = 0;
-		u32 iir;
 
-		iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
-		if (iir == 0)
+		state.iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
+		if (state.iir == 0)
 			break;
 
 		ret = IRQ_HANDLED;
 
-		if (iir & I915_DISPLAY_PORT_INTERRUPT)
-			hotplug_status = i9xx_hpd_irq_ack(display);
-
-		/* Call regardless, as some status bits might not be
-		 * signalled in IIR */
-		i9xx_pipestat_irq_ack(display, iir, pipe_stats);
+		intel_display_irq_ack(display, &state);
 
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
+		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
 
-		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
+		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, state.iir);
 
-		if (iir & I915_USER_INTERRUPT)
+		if (state.iir & I915_USER_INTERRUPT)
 			intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0],
-					    iir);
+					    state.iir);
 
-		if (iir & I915_BSD_USER_INTERRUPT)
+		if (state.iir & I915_BSD_USER_INTERRUPT)
 			intel_engine_cs_irq(to_gt(dev_priv)->engine[VCS0],
-					    iir >> 25);
+					    state.iir >> 25);
 
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
+		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
 
-		if (hotplug_status)
-			i9xx_hpd_irq_handler(display, hotplug_status);
+		if (state.hotplug_status)
+			i9xx_hpd_irq_handler(display, state.hotplug_status);
 
-		i965_pipestat_irq_handler(display, iir, pipe_stats);
+		i965_pipestat_irq_handler(display, state.iir, state.pipe_stats);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, IRQ_HANDLED);
-- 
2.47.3

[PATCH 15/15] drm/i915/irq: add intel_display_irq_handler() to irq funcs

[Jani Nikula]

Call the platform specific display irq handler hooks via
intel_display_irq_handler(). Add master_ctl to struct
intel_display_irq_state, and pass the state pointer to the handler where
necessary.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/display/intel_display_irq.c  | 95 ++++++++++++++++---
 .../gpu/drm/i915/display/intel_display_irq.h  | 11 +--
 drivers/gpu/drm/i915/i915_irq.c               | 48 +++-------
 drivers/gpu/drm/xe/display/xe_display.c       |  2 +-
 4 files changed, 98 insertions(+), 58 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 662081e274bf..5aec1bedbd61 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -23,6 +23,7 @@
 #include "intel_fifo_underrun.h"
 #include "intel_gmbus.h"
 #include "intel_hotplug_irq.h"
+#include "intel_lpe_audio.h"
 #include "intel_parent.h"
 #include "intel_pipe_crc_regs.h"
 #include "intel_plane.h"
@@ -596,8 +597,8 @@ static void i9xx_pipestat_irq_ack(struct intel_display *display,
 	spin_unlock(&display->irq.lock);
 }
 
-void i915_pipestat_irq_handler(struct intel_display *display,
-			       u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
+static void i915_pipestat_irq_handler(struct intel_display *display,
+				      u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
 {
 	bool blc_event = false;
 	enum pipe pipe;
@@ -620,8 +621,8 @@ void i915_pipestat_irq_handler(struct intel_display *display,
 		intel_opregion_asle_intr(display);
 }
 
-void i965_pipestat_irq_handler(struct intel_display *display,
-			       u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
+static void i965_pipestat_irq_handler(struct intel_display *display,
+				      u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
 {
 	bool blc_event = false;
 	enum pipe pipe;
@@ -647,8 +648,8 @@ void i965_pipestat_irq_handler(struct intel_display *display,
 		intel_gmbus_irq_handler(display);
 }
 
-void valleyview_pipestat_irq_handler(struct intel_display *display,
-				     const u32 pipe_stats[I915_MAX_PIPES])
+static void valleyview_pipestat_irq_handler(struct intel_display *display,
+					    const u32 pipe_stats[I915_MAX_PIPES])
 {
 	enum pipe pipe;
 
@@ -1020,7 +1021,8 @@ void ilk_display_irq_master_enable(struct intel_display *display, u32 de_ier, u3
 		intel_de_write_fw(display, SDEIER, sde_ier);
 }
 
-bool ilk_display_irq_handler(struct intel_display *display)
+static bool ilk_display_irq_handler(struct intel_display *display,
+				    const struct intel_display_irq_state *state)
 {
 	u32 de_iir;
 	bool handled = false;
@@ -1404,7 +1406,7 @@ static void gen8_read_and_ack_pch_irqs(struct intel_display *display, u32 *pch_i
 		intel_de_write(display, PICAINTERRUPT_IER, pica_ier);
 }
 
-void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
+static void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
 {
 	u32 iir;
 	enum pipe pipe;
@@ -1565,6 +1567,14 @@ void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
 	}
 }
 
+static bool gen8_display_irq_handler(struct intel_display *display,
+				     const struct intel_display_irq_state *state)
+{
+	gen8_de_irq_handler(display, state->master_ctl);
+
+	return true;
+}
+
 u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl)
 {
 	u32 iir;
@@ -1589,7 +1599,8 @@ void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir)
 		intel_opregion_asle_intr(display);
 }
 
-void gen11_display_irq_handler(struct intel_display *display)
+static bool gen11_display_irq_handler(struct intel_display *display,
+				      const struct intel_display_irq_state *state)
 {
 	u32 disp_ctl;
 
@@ -1605,6 +1616,8 @@ void gen11_display_irq_handler(struct intel_display *display)
 	intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
 
 	intel_display_rpm_assert_unblock(display);
+
+	return true;
 }
 
 static void i915gm_irq_cstate_wa_enable(struct intel_display *display)
@@ -1920,8 +1933,8 @@ static void vlv_display_error_irq_ack(struct intel_display *display,
 	intel_de_write(display, VLV_EMR, emr);
 }
 
-void vlv_display_error_irq_handler(struct intel_display *display,
-				   u32 eir, u32 dpinvgtt)
+static void vlv_display_error_irq_handler(struct intel_display *display,
+					  u32 eir, u32 dpinvgtt)
 {
 	drm_dbg(display->drm, "Master Error, EIR 0x%08x\n", eir);
 
@@ -2020,6 +2033,28 @@ static void i9xx_display_irq_ack(struct intel_display *display,
 	i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
 }
 
+static bool i965_display_irq_handler(struct intel_display *display,
+				     const struct intel_display_irq_state *state)
+{
+	if (state->hotplug_status)
+		i9xx_hpd_irq_handler(display, state->hotplug_status);
+
+	i965_pipestat_irq_handler(display, state->iir, state->pipe_stats);
+
+	return true;
+}
+
+static bool i915_display_irq_handler(struct intel_display *display,
+				     const struct intel_display_irq_state *state)
+{
+	if (state->hotplug_status)
+		i9xx_hpd_irq_handler(display, state->hotplug_status);
+
+	i915_pipestat_irq_handler(display, state->iir, state->pipe_stats);
+
+	return true;
+}
+
 static u32 vlv_error_mask(void)
 {
 	/* TODO enable other errors too? */
@@ -2088,6 +2123,28 @@ static void vlv_display_irq_ack(struct intel_display *display,
 	i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
 }
 
+static bool vlv_display_irq_handler(struct intel_display *display,
+				    const struct intel_display_irq_state *state)
+{
+	u32 lpe_mask = I915_LPE_PIPE_A_INTERRUPT | I915_LPE_PIPE_B_INTERRUPT;
+
+	if (display->platform.cherryview)
+		lpe_mask |= I915_LPE_PIPE_C_INTERRUPT;
+
+	if (state->iir & lpe_mask)
+		intel_lpe_audio_irq_handler(display);
+
+	if (state->hotplug_status)
+		i9xx_hpd_irq_handler(display, state->hotplug_status);
+
+	if (state->iir & I915_MASTER_ERROR_INTERRUPT)
+		vlv_display_error_irq_handler(display, state->eir, state->dpinvgtt);
+
+	valleyview_pipestat_irq_handler(display, state->pipe_stats);
+
+	return true;
+}
+
 static void ibx_display_irq_reset(struct intel_display *display)
 {
 	if (HAS_PCH_NOP(display))
@@ -2476,39 +2533,46 @@ struct intel_display_irq_funcs {
 	void (*reset)(struct intel_display *display);
 	void (*postinstall)(struct intel_display *display);
 	void (*ack)(struct intel_display *display, struct intel_display_irq_state *state);
+	bool (*handler)(struct intel_display *display, const struct intel_display_irq_state *state);
 };
 
 struct intel_display_irq_funcs gen11_display_irq_funcs = {
 	.reset = gen11_display_irq_reset,
 	.postinstall = gen11_de_irq_postinstall,
+	.handler = gen11_display_irq_handler,
 };
 
 struct intel_display_irq_funcs gen8_display_irq_funcs = {
 	.reset = gen8_display_irq_reset,
 	.postinstall = gen8_de_irq_postinstall,
+	.handler = gen8_display_irq_handler,
 };
 
 struct intel_display_irq_funcs vlv_display_irq_funcs = {
 	.reset = vlv_display_irq_reset,
 	.postinstall = vlv_display_irq_postinstall,
 	.ack = vlv_display_irq_ack,
+	.handler = vlv_display_irq_handler,
 };
 
 struct intel_display_irq_funcs ilk_display_irq_funcs = {
 	.reset = ilk_display_irq_reset,
 	.postinstall = ilk_de_irq_postinstall,
+	.handler = ilk_display_irq_handler,
 };
 
 struct intel_display_irq_funcs i965_display_irq_funcs = {
 	.reset = i9xx_display_irq_reset,
 	.postinstall = i965_display_irq_postinstall,
 	.ack = i9xx_display_irq_ack,
+	.handler = i965_display_irq_handler,
 };
 
 struct intel_display_irq_funcs i915_display_irq_funcs = {
 	.reset = i9xx_display_irq_reset,
 	.postinstall = i915_display_irq_postinstall,
 	.ack = i9xx_display_irq_ack,
+	.handler = i915_display_irq_handler,
 };
 
 void intel_display_irq_reset(struct intel_display *display)
@@ -2528,6 +2592,15 @@ void intel_display_irq_ack(struct intel_display *display,
 		display->irq.funcs->ack(display, state);
 }
 
+bool intel_display_irq_handler(struct intel_display *display,
+			       const struct intel_display_irq_state *state)
+{
+	if (!display->irq.funcs->handler)
+		return true;
+
+	return display->irq.funcs->handler(display, state);
+}
+
 void intel_display_irq_init(struct intel_display *display)
 {
 	spin_lock_init(&display->irq.lock);
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index 3773a31e48f2..a1227cee885a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -51,14 +51,12 @@ void bdw_disable_vblank(struct drm_crtc *crtc);
 
 void ilk_display_irq_master_disable(struct intel_display *display, u32 *de_ier, u32 *sde_ier);
 void ilk_display_irq_master_enable(struct intel_display *display, u32 de_ier, u32 sde_ier);
-bool ilk_display_irq_handler(struct intel_display *display);
-void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl);
-void gen11_display_irq_handler(struct intel_display *display);
 
 u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
 void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
 
 struct intel_display_irq_state {
+	u32 master_ctl;
 	u32 iir;
 	u32 eir;
 	u32 hotplug_status;
@@ -69,6 +67,7 @@ struct intel_display_irq_state {
 void intel_display_irq_reset(struct intel_display *display);
 void intel_display_irq_postinstall(struct intel_display *display);
 void intel_display_irq_ack(struct intel_display *display, struct intel_display_irq_state *state);
+bool intel_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);
 
 u32 i9xx_display_irq_enable_mask(struct intel_display *display);
 
@@ -76,12 +75,6 @@ u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
 void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
 void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
 
-void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
-void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
-void valleyview_pipestat_irq_handler(struct intel_display *display, const u32 pipe_stats[I915_MAX_PIPES]);
-
-void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);
-
 void intel_display_irq_init(struct intel_display *display);
 
 void i915gm_irq_cstate_wa(struct intel_display *display, bool enable);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index bb65ce9d09b2..30ce462e92ab 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -38,8 +38,6 @@
 
 #include "display/intel_display_irq.h"
 #include "display/intel_hotplug.h"
-#include "display/intel_hotplug_irq.h"
-#include "display/intel_lpe_audio.h"
 
 #include "gt/intel_breadcrumbs.h"
 #include "gt/intel_gt.h"
@@ -287,17 +285,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 		if (pm_iir)
 			gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir);
 
-		if (state.iir & (I915_LPE_PIPE_A_INTERRUPT |
-				 I915_LPE_PIPE_B_INTERRUPT))
-			intel_lpe_audio_irq_handler(display);
-
-		if (state.hotplug_status)
-			i9xx_hpd_irq_handler(display, state.hotplug_status);
-
-		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
-			vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
-
-		valleyview_pipestat_irq_handler(display, state.pipe_stats);
+		intel_display_irq_handler(display, &state);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, ret);
@@ -362,18 +350,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
 		intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
 
-		if (state.iir & (I915_LPE_PIPE_A_INTERRUPT |
-				 I915_LPE_PIPE_B_INTERRUPT |
-				 I915_LPE_PIPE_C_INTERRUPT))
-			intel_lpe_audio_irq_handler(display);
-
-		if (state.hotplug_status)
-			i9xx_hpd_irq_handler(display, state.hotplug_status);
-
-		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
-			vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
-
-		valleyview_pipestat_irq_handler(display, state.pipe_stats);
+		intel_display_irq_handler(display, &state);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, ret);
@@ -420,7 +397,7 @@ static irqreturn_t ilk_irq_handler(int irq, void *arg)
 		ret = IRQ_HANDLED;
 	}
 
-	if (ilk_display_irq_handler(display))
+	if (intel_display_irq_handler(display, NULL))
 		ret = IRQ_HANDLED;
 
 	if (GRAPHICS_VER(i915) >= 6) {
@@ -482,8 +459,11 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 
 	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
 	if (master_ctl & ~GEN8_GT_IRQS) {
+		const struct intel_display_irq_state state = {
+			.master_ctl = master_ctl,
+		};
 		disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
-		gen8_de_irq_handler(display, master_ctl);
+		intel_display_irq_handler(display, &state);
 		enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 	}
 
@@ -535,7 +515,7 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
 
 	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
 	if (master_ctl & GEN11_DISPLAY_IRQ)
-		gen11_display_irq_handler(display);
+		intel_display_irq_handler(display, NULL);
 
 	gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);
 
@@ -602,7 +582,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
 	gen11_gt_irq_handler(gt, master_ctl);
 
 	if (master_ctl & GEN11_DISPLAY_IRQ)
-		gen11_display_irq_handler(display);
+		intel_display_irq_handler(display, NULL);
 
 	gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);
 
@@ -906,10 +886,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
 		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
 
-		if (state.hotplug_status)
-			i9xx_hpd_irq_handler(display, state.hotplug_status);
-
-		i915_pipestat_irq_handler(display, state.iir, state.pipe_stats);
+		intel_display_irq_handler(display, &state);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, ret);
@@ -1013,10 +990,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
 		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
 
-		if (state.hotplug_status)
-			i9xx_hpd_irq_handler(display, state.hotplug_status);
-
-		i965_pipestat_irq_handler(display, state.iir, state.pipe_stats);
+		intel_display_irq_handler(display, &state);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, IRQ_HANDLED);
diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index 736a5e6938d6..4f283fb79554 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -214,7 +214,7 @@ void xe_display_irq_handler(struct xe_device *xe, u32 master_ctl)
 		return;
 
 	if (master_ctl & DISPLAY_IRQ)
-		gen11_display_irq_handler(display);
+		intel_display_irq_handler(display, NULL);
 }
 
 void xe_display_irq_enable(struct xe_device *xe, u32 gu_misc_iir)
-- 
2.47.3

Re: [PATCH 10/15] drm/i915/irq: move VLV/CHV LPE irq handler call after irq acks

[Ville Syrjälä]

On Wed, Apr 29, 2026 at 01:24:50PM +0300, Jani Nikula wrote:
> The location of the intel_lpe_audio_irq_handler() call seems too
> early. Group the handler calls together slightly later.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index ef9eadf38a53..1c87f56d668d 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -282,10 +282,6 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
>  		 * signalled in IIR */
>  		i9xx_pipestat_irq_ack(display, iir, pipe_stats);
>  
> -		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
> -			   I915_LPE_PIPE_B_INTERRUPT))
> -			intel_lpe_audio_irq_handler(display);

This thing acks the irq too, so I believe it needs to stay here.

> -
>  		/*
>  		 * VLV_IIR is single buffered, and reflects the level
>  		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
> @@ -301,6 +297,10 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
>  		if (pm_iir)
>  			gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir);
>  
> +		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
> +			   I915_LPE_PIPE_B_INTERRUPT))
> +			intel_lpe_audio_irq_handler(display);
> +
>  		if (hotplug_status)
>  			i9xx_hpd_irq_handler(display, hotplug_status);
>  
> @@ -372,11 +372,6 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
>  		 * signalled in IIR */
>  		i9xx_pipestat_irq_ack(display, iir, pipe_stats);
>  
> -		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
> -			   I915_LPE_PIPE_B_INTERRUPT |
> -			   I915_LPE_PIPE_C_INTERRUPT))
> -			intel_lpe_audio_irq_handler(display);
> -
>  		/*
>  		 * VLV_IIR is single buffered, and reflects the level
>  		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
> @@ -387,6 +382,11 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
>  		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
>  		intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
>  
> +		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
> +			   I915_LPE_PIPE_B_INTERRUPT |
> +			   I915_LPE_PIPE_C_INTERRUPT))
> +			intel_lpe_audio_irq_handler(display);
> +
>  		if (hotplug_status)
>  			i9xx_hpd_irq_handler(display, hotplug_status);
>  
> -- 
> 2.47.3

-- 
Ville Syrjälä
Intel

Re: [PATCH 15/15] drm/i915/irq: add intel_display_irq_handler() to irq funcs

[Ville Syrjälä]

On Wed, Apr 29, 2026 at 01:24:55PM +0300, Jani Nikula wrote:
> Call the platform specific display irq handler hooks via
> intel_display_irq_handler(). Add master_ctl to struct
> intel_display_irq_state, and pass the state pointer to the handler where
> necessary.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_irq.c  | 95 ++++++++++++++++---
>  .../gpu/drm/i915/display/intel_display_irq.h  | 11 +--
>  drivers/gpu/drm/i915/i915_irq.c               | 48 +++-------
>  drivers/gpu/drm/xe/display/xe_display.c       |  2 +-
>  4 files changed, 98 insertions(+), 58 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 662081e274bf..5aec1bedbd61 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -23,6 +23,7 @@
>  #include "intel_fifo_underrun.h"
>  #include "intel_gmbus.h"
>  #include "intel_hotplug_irq.h"
> +#include "intel_lpe_audio.h"
>  #include "intel_parent.h"
>  #include "intel_pipe_crc_regs.h"
>  #include "intel_plane.h"
> @@ -596,8 +597,8 @@ static void i9xx_pipestat_irq_ack(struct intel_display *display,
>  	spin_unlock(&display->irq.lock);
>  }
>  
> -void i915_pipestat_irq_handler(struct intel_display *display,
> -			       u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
> +static void i915_pipestat_irq_handler(struct intel_display *display,
> +				      u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
>  {
>  	bool blc_event = false;
>  	enum pipe pipe;
> @@ -620,8 +621,8 @@ void i915_pipestat_irq_handler(struct intel_display *display,
>  		intel_opregion_asle_intr(display);
>  }
>  
> -void i965_pipestat_irq_handler(struct intel_display *display,
> -			       u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
> +static void i965_pipestat_irq_handler(struct intel_display *display,
> +				      u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
>  {
>  	bool blc_event = false;
>  	enum pipe pipe;
> @@ -647,8 +648,8 @@ void i965_pipestat_irq_handler(struct intel_display *display,
>  		intel_gmbus_irq_handler(display);
>  }
>  
> -void valleyview_pipestat_irq_handler(struct intel_display *display,
> -				     const u32 pipe_stats[I915_MAX_PIPES])
> +static void valleyview_pipestat_irq_handler(struct intel_display *display,
> +					    const u32 pipe_stats[I915_MAX_PIPES])
>  {
>  	enum pipe pipe;
>  
> @@ -1020,7 +1021,8 @@ void ilk_display_irq_master_enable(struct intel_display *display, u32 de_ier, u3
>  		intel_de_write_fw(display, SDEIER, sde_ier);
>  }
>  
> -bool ilk_display_irq_handler(struct intel_display *display)
> +static bool ilk_display_irq_handler(struct intel_display *display,
> +				    const struct intel_display_irq_state *state)
>  {
>  	u32 de_iir;
>  	bool handled = false;
> @@ -1404,7 +1406,7 @@ static void gen8_read_and_ack_pch_irqs(struct intel_display *display, u32 *pch_i
>  		intel_de_write(display, PICAINTERRUPT_IER, pica_ier);
>  }
>  
> -void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
> +static void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
>  {
>  	u32 iir;
>  	enum pipe pipe;
> @@ -1565,6 +1567,14 @@ void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
>  	}
>  }
>  
> +static bool gen8_display_irq_handler(struct intel_display *display,
> +				     const struct intel_display_irq_state *state)
> +{
> +	gen8_de_irq_handler(display, state->master_ctl);
> +
> +	return true;
> +}
> +
>  u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl)
>  {
>  	u32 iir;
> @@ -1589,7 +1599,8 @@ void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir)
>  		intel_opregion_asle_intr(display);
>  }
>  
> -void gen11_display_irq_handler(struct intel_display *display)
> +static bool gen11_display_irq_handler(struct intel_display *display,
> +				      const struct intel_display_irq_state *state)
>  {
>  	u32 disp_ctl;
>  
> @@ -1605,6 +1616,8 @@ void gen11_display_irq_handler(struct intel_display *display)
>  	intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
>  
>  	intel_display_rpm_assert_unblock(display);
> +
> +	return true;
>  }
>  
>  static void i915gm_irq_cstate_wa_enable(struct intel_display *display)
> @@ -1920,8 +1933,8 @@ static void vlv_display_error_irq_ack(struct intel_display *display,
>  	intel_de_write(display, VLV_EMR, emr);
>  }
>  
> -void vlv_display_error_irq_handler(struct intel_display *display,
> -				   u32 eir, u32 dpinvgtt)
> +static void vlv_display_error_irq_handler(struct intel_display *display,
> +					  u32 eir, u32 dpinvgtt)
>  {
>  	drm_dbg(display->drm, "Master Error, EIR 0x%08x\n", eir);
>  
> @@ -2020,6 +2033,28 @@ static void i9xx_display_irq_ack(struct intel_display *display,
>  	i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
>  }
>  
> +static bool i965_display_irq_handler(struct intel_display *display,
> +				     const struct intel_display_irq_state *state)
> +{
> +	if (state->hotplug_status)
> +		i9xx_hpd_irq_handler(display, state->hotplug_status);
> +
> +	i965_pipestat_irq_handler(display, state->iir, state->pipe_stats);
> +
> +	return true;
> +}
> +
> +static bool i915_display_irq_handler(struct intel_display *display,
> +				     const struct intel_display_irq_state *state)
> +{
> +	if (state->hotplug_status)
> +		i9xx_hpd_irq_handler(display, state->hotplug_status);
> +
> +	i915_pipestat_irq_handler(display, state->iir, state->pipe_stats);
> +
> +	return true;
> +}
> +
>  static u32 vlv_error_mask(void)
>  {
>  	/* TODO enable other errors too? */
> @@ -2088,6 +2123,28 @@ static void vlv_display_irq_ack(struct intel_display *display,
>  	i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
>  }
>  
> +static bool vlv_display_irq_handler(struct intel_display *display,
> +				    const struct intel_display_irq_state *state)
> +{
> +	u32 lpe_mask = I915_LPE_PIPE_A_INTERRUPT | I915_LPE_PIPE_B_INTERRUPT;
> +
> +	if (display->platform.cherryview)
> +		lpe_mask |= I915_LPE_PIPE_C_INTERRUPT;

I would prefer a function rather than the extra variable. The other
option is to just use the CHV mask always. There is nothing on the
extra bit on VLV so we never unmask it.

> +
> +	if (state->iir & lpe_mask)
> +		intel_lpe_audio_irq_handler(display);
> +
> +	if (state->hotplug_status)
> +		i9xx_hpd_irq_handler(display, state->hotplug_status);
> +
> +	if (state->iir & I915_MASTER_ERROR_INTERRUPT)
> +		vlv_display_error_irq_handler(display, state->eir, state->dpinvgtt);
> +
> +	valleyview_pipestat_irq_handler(display, state->pipe_stats);
> +
> +	return true;
> +}
> +
>  static void ibx_display_irq_reset(struct intel_display *display)
>  {
>  	if (HAS_PCH_NOP(display))
> @@ -2476,39 +2533,46 @@ struct intel_display_irq_funcs {
>  	void (*reset)(struct intel_display *display);
>  	void (*postinstall)(struct intel_display *display);
>  	void (*ack)(struct intel_display *display, struct intel_display_irq_state *state);
> +	bool (*handler)(struct intel_display *display, const struct intel_display_irq_state *state);
>  };
>  
>  struct intel_display_irq_funcs gen11_display_irq_funcs = {
>  	.reset = gen11_display_irq_reset,
>  	.postinstall = gen11_de_irq_postinstall,
> +	.handler = gen11_display_irq_handler,
>  };
>  
>  struct intel_display_irq_funcs gen8_display_irq_funcs = {
>  	.reset = gen8_display_irq_reset,
>  	.postinstall = gen8_de_irq_postinstall,
> +	.handler = gen8_display_irq_handler,
>  };
>  
>  struct intel_display_irq_funcs vlv_display_irq_funcs = {
>  	.reset = vlv_display_irq_reset,
>  	.postinstall = vlv_display_irq_postinstall,
>  	.ack = vlv_display_irq_ack,
> +	.handler = vlv_display_irq_handler,
>  };
>  
>  struct intel_display_irq_funcs ilk_display_irq_funcs = {
>  	.reset = ilk_display_irq_reset,
>  	.postinstall = ilk_de_irq_postinstall,
> +	.handler = ilk_display_irq_handler,
>  };
>  
>  struct intel_display_irq_funcs i965_display_irq_funcs = {
>  	.reset = i9xx_display_irq_reset,
>  	.postinstall = i965_display_irq_postinstall,
>  	.ack = i9xx_display_irq_ack,
> +	.handler = i965_display_irq_handler,
>  };
>  
>  struct intel_display_irq_funcs i915_display_irq_funcs = {
>  	.reset = i9xx_display_irq_reset,
>  	.postinstall = i915_display_irq_postinstall,
>  	.ack = i9xx_display_irq_ack,
> +	.handler = i915_display_irq_handler,
>  };
>  
>  void intel_display_irq_reset(struct intel_display *display)
> @@ -2528,6 +2592,15 @@ void intel_display_irq_ack(struct intel_display *display,
>  		display->irq.funcs->ack(display, state);
>  }
>  
> +bool intel_display_irq_handler(struct intel_display *display,
> +			       const struct intel_display_irq_state *state)
> +{
> +	if (!display->irq.funcs->handler)
> +		return true;
> +
> +	return display->irq.funcs->handler(display, state);
> +}
> +
>  void intel_display_irq_init(struct intel_display *display)
>  {
>  	spin_lock_init(&display->irq.lock);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
> index 3773a31e48f2..a1227cee885a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
> @@ -51,14 +51,12 @@ void bdw_disable_vblank(struct drm_crtc *crtc);
>  
>  void ilk_display_irq_master_disable(struct intel_display *display, u32 *de_ier, u32 *sde_ier);
>  void ilk_display_irq_master_enable(struct intel_display *display, u32 de_ier, u32 sde_ier);
> -bool ilk_display_irq_handler(struct intel_display *display);
> -void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl);
> -void gen11_display_irq_handler(struct intel_display *display);
>  
>  u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
>  void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
>  
>  struct intel_display_irq_state {
> +	u32 master_ctl;

Ideally I'd like a separate structs for different platforms,
but until I resurrect my old ack vs. handle split for all
platforms I guess we don't need anything else here for
ilk+. So good enough for now I suppose.

>  	u32 iir;
>  	u32 eir;
>  	u32 hotplug_status;
> @@ -69,6 +67,7 @@ struct intel_display_irq_state {
>  void intel_display_irq_reset(struct intel_display *display);
>  void intel_display_irq_postinstall(struct intel_display *display);
>  void intel_display_irq_ack(struct intel_display *display, struct intel_display_irq_state *state);
> +bool intel_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);
>  
>  u32 i9xx_display_irq_enable_mask(struct intel_display *display);
>  
> @@ -76,12 +75,6 @@ u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
>  void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
>  void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
>  
> -void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
> -void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
> -void valleyview_pipestat_irq_handler(struct intel_display *display, const u32 pipe_stats[I915_MAX_PIPES]);
> -
> -void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);
> -
>  void intel_display_irq_init(struct intel_display *display);
>  
>  void i915gm_irq_cstate_wa(struct intel_display *display, bool enable);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index bb65ce9d09b2..30ce462e92ab 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -38,8 +38,6 @@
>  
>  #include "display/intel_display_irq.h"
>  #include "display/intel_hotplug.h"
> -#include "display/intel_hotplug_irq.h"
> -#include "display/intel_lpe_audio.h"
>  
>  #include "gt/intel_breadcrumbs.h"
>  #include "gt/intel_gt.h"
> @@ -287,17 +285,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
>  		if (pm_iir)
>  			gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir);
>  
> -		if (state.iir & (I915_LPE_PIPE_A_INTERRUPT |
> -				 I915_LPE_PIPE_B_INTERRUPT))
> -			intel_lpe_audio_irq_handler(display);
> -
> -		if (state.hotplug_status)
> -			i9xx_hpd_irq_handler(display, state.hotplug_status);
> -
> -		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
> -			vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
> -
> -		valleyview_pipestat_irq_handler(display, state.pipe_stats);
> +		intel_display_irq_handler(display, &state);
>  	} while (0);
>  
>  	pmu_irq_stats(dev_priv, ret);
> @@ -362,18 +350,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
>  		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
>  		intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
>  
> -		if (state.iir & (I915_LPE_PIPE_A_INTERRUPT |
> -				 I915_LPE_PIPE_B_INTERRUPT |
> -				 I915_LPE_PIPE_C_INTERRUPT))
> -			intel_lpe_audio_irq_handler(display);
> -
> -		if (state.hotplug_status)
> -			i9xx_hpd_irq_handler(display, state.hotplug_status);
> -
> -		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
> -			vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
> -
> -		valleyview_pipestat_irq_handler(display, state.pipe_stats);
> +		intel_display_irq_handler(display, &state);
>  	} while (0);
>  
>  	pmu_irq_stats(dev_priv, ret);
> @@ -420,7 +397,7 @@ static irqreturn_t ilk_irq_handler(int irq, void *arg)
>  		ret = IRQ_HANDLED;
>  	}
>  
> -	if (ilk_display_irq_handler(display))
> +	if (intel_display_irq_handler(display, NULL))
>  		ret = IRQ_HANDLED;
>  
>  	if (GRAPHICS_VER(i915) >= 6) {
> @@ -482,8 +459,11 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
>  
>  	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
>  	if (master_ctl & ~GEN8_GT_IRQS) {
> +		const struct intel_display_irq_state state = {
> +			.master_ctl = master_ctl,
> +		};
>  		disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> -		gen8_de_irq_handler(display, master_ctl);
> +		intel_display_irq_handler(display, &state);
>  		enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>  	}
>  
> @@ -535,7 +515,7 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
>  
>  	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
>  	if (master_ctl & GEN11_DISPLAY_IRQ)
> -		gen11_display_irq_handler(display);
> +		intel_display_irq_handler(display, NULL);
>  
>  	gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);
>  
> @@ -602,7 +582,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
>  	gen11_gt_irq_handler(gt, master_ctl);
>  
>  	if (master_ctl & GEN11_DISPLAY_IRQ)
> -		gen11_display_irq_handler(display);
> +		intel_display_irq_handler(display, NULL);
>  
>  	gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);
>  
> @@ -906,10 +886,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
>  		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
>  			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
>  
> -		if (state.hotplug_status)
> -			i9xx_hpd_irq_handler(display, state.hotplug_status);
> -
> -		i915_pipestat_irq_handler(display, state.iir, state.pipe_stats);
> +		intel_display_irq_handler(display, &state);
>  	} while (0);
>  
>  	pmu_irq_stats(dev_priv, ret);
> @@ -1013,10 +990,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
>  		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
>  			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
>  
> -		if (state.hotplug_status)
> -			i9xx_hpd_irq_handler(display, state.hotplug_status);
> -
> -		i965_pipestat_irq_handler(display, state.iir, state.pipe_stats);
> +		intel_display_irq_handler(display, &state);
>  	} while (0);
>  
>  	pmu_irq_stats(dev_priv, IRQ_HANDLED);
> diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
> index 736a5e6938d6..4f283fb79554 100644
> --- a/drivers/gpu/drm/xe/display/xe_display.c
> +++ b/drivers/gpu/drm/xe/display/xe_display.c
> @@ -214,7 +214,7 @@ void xe_display_irq_handler(struct xe_device *xe, u32 master_ctl)
>  		return;
>  
>  	if (master_ctl & DISPLAY_IRQ)
> -		gen11_display_irq_handler(display);
> +		intel_display_irq_handler(display, NULL);
>  }
>  
>  void xe_display_irq_enable(struct xe_device *xe, u32 gu_misc_iir)
> -- 
> 2.47.3

-- 
Ville Syrjälä
Intel

✗ CI.checkpatch: warning for drm/i915: refactor display funcs, add display irq hooks

[Patchwork]

== Series Details ==

Series: drm/i915: refactor display funcs, add display irq hooks
URL   : https://patchwork.freedesktop.org/series/165710/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
c8c12e558adaef7a4d125d83b6e1f8824bc13b82
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 5b39454654c4f162a593d6c08c4ddf71320c7db3
Author: Jani Nikula <jani.nikula@intel.com>
Date:   Wed Apr 29 13:24:55 2026 +0300

    drm/i915/irq: add intel_display_irq_handler() to irq funcs
    
    Call the platform specific display irq handler hooks via
    intel_display_irq_handler(). Add master_ctl to struct
    intel_display_irq_state, and pass the state pointer to the handler where
    necessary.
    
    Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+ /mt/dim checkpatch 1db870ffb55b6414a78d7609ba7e08adf880dfc5 drm-intel
efdfe68ac66e drm/i915/display: move audio funcs under audio sub-struct
ed135fbba09a drm/i915/display: move color funcs under color sub-struct
59fc26e721b5 drm/i915/display: move fdi funcs under fdi sub-struct
4e9c8d59ea24 drm/i915/display: move watermark funcs under wm sub-struct
c1d30880ab53 drm/i915/display: move hotplug irq funcs under hotplug sub-struct
66e356137d8a drm/i915/display: move dpll funcs under dpll sub-struct
6a860fecd6e6 drm/i915/display: move cdclk funcs under cdclk sub-struct
81f753125b39 drm/i915/display: move display funcs under modeset sub-struct
c6eb9b9e70e1 drm/i915/irq: deduplicate dg1_de_irq_postinstall() and gen11_de_irq_postinstall()
5a2ba49577e7 drm/i915/irq: move VLV/CHV LPE irq handler call after irq acks
8b06b08a5762 drm/i915/irq: constify pipe stats parameters
-:53: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#53: FILE: drivers/gpu/drm/i915/display/intel_display_irq.h:81:
+void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);

-:54: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#54: FILE: drivers/gpu/drm/i915/display/intel_display_irq.h:82:
+void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);

-:55: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#55: FILE: drivers/gpu/drm/i915/display/intel_display_irq.h:83:
+void valleyview_pipestat_irq_handler(struct intel_display *display, const u32 pipe_stats[I915_MAX_PIPES]);

total: 0 errors, 3 warnings, 0 checks, 36 lines checked
2085541ee845 drm/i915/irq: add display irq funcs, start with intel_display_irq_reset()
a60a5e32ae71 drm/i915/irq: add intel_display_irq_postinstall() to irq funcs
df48e7e2e60d drm/i915/irq: add intel_display_irq_ack() to irq funcs
5b39454654c4 drm/i915/irq: add intel_display_irq_handler() to irq funcs
-:267: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#267: FILE: drivers/gpu/drm/i915/display/intel_display_irq.h:70:
+bool intel_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);

total: 0 errors, 1 warnings, 0 checks, 357 lines checked

✓ CI.KUnit: success for drm/i915: refactor display funcs, add display irq hooks

[Patchwork]

== Series Details ==

Series: drm/i915: refactor display funcs, add display irq hooks
URL   : https://patchwork.freedesktop.org/series/165710/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[12:14:16] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:14:21] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:14:52] Starting KUnit Kernel (1/1)...
[12:14:52] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:14:52] ================== guc_buf (11 subtests) ===================
[12:14:52] [PASSED] test_smallest
[12:14:52] [PASSED] test_largest
[12:14:52] [PASSED] test_granular
[12:14:52] [PASSED] test_unique
[12:14:52] [PASSED] test_overlap
[12:14:52] [PASSED] test_reusable
[12:14:52] [PASSED] test_too_big
[12:14:52] [PASSED] test_flush
[12:14:52] [PASSED] test_lookup
[12:14:52] [PASSED] test_data
[12:14:52] [PASSED] test_class
[12:14:52] ===================== [PASSED] guc_buf =====================
[12:14:52] =================== guc_dbm (7 subtests) ===================
[12:14:52] [PASSED] test_empty
[12:14:52] [PASSED] test_default
[12:14:52] ======================== test_size  ========================
[12:14:52] [PASSED] 4
[12:14:52] [PASSED] 8
[12:14:52] [PASSED] 32
[12:14:52] [PASSED] 256
[12:14:52] ==================== [PASSED] test_size ====================
[12:14:52] ======================= test_reuse  ========================
[12:14:52] [PASSED] 4
[12:14:52] [PASSED] 8
[12:14:52] [PASSED] 32
[12:14:52] [PASSED] 256
[12:14:52] =================== [PASSED] test_reuse ====================
[12:14:52] =================== test_range_overlap  ====================
[12:14:52] [PASSED] 4
[12:14:52] [PASSED] 8
[12:14:52] [PASSED] 32
[12:14:52] [PASSED] 256
[12:14:52] =============== [PASSED] test_range_overlap ================
[12:14:52] =================== test_range_compact  ====================
[12:14:52] [PASSED] 4
[12:14:52] [PASSED] 8
[12:14:52] [PASSED] 32
[12:14:52] [PASSED] 256
[12:14:52] =============== [PASSED] test_range_compact ================
[12:14:52] ==================== test_range_spare  =====================
[12:14:52] [PASSED] 4
[12:14:52] [PASSED] 8
[12:14:52] [PASSED] 32
[12:14:52] [PASSED] 256
[12:14:52] ================ [PASSED] test_range_spare =================
[12:14:52] ===================== [PASSED] guc_dbm =====================
[12:14:52] =================== guc_idm (6 subtests) ===================
[12:14:52] [PASSED] bad_init
[12:14:52] [PASSED] no_init
[12:14:52] [PASSED] init_fini
[12:14:52] [PASSED] check_used
[12:14:52] [PASSED] check_quota
[12:14:52] [PASSED] check_all
[12:14:52] ===================== [PASSED] guc_idm =====================
[12:14:52] ================== no_relay (3 subtests) ===================
[12:14:52] [PASSED] xe_drops_guc2pf_if_not_ready
[12:14:52] [PASSED] xe_drops_guc2vf_if_not_ready
[12:14:52] [PASSED] xe_rejects_send_if_not_ready
[12:14:52] ==================== [PASSED] no_relay =====================
[12:14:52] ================== pf_relay (14 subtests) ==================
[12:14:52] [PASSED] pf_rejects_guc2pf_too_short
[12:14:52] [PASSED] pf_rejects_guc2pf_too_long
[12:14:52] [PASSED] pf_rejects_guc2pf_no_payload
[12:14:52] [PASSED] pf_fails_no_payload
[12:14:52] [PASSED] pf_fails_bad_origin
[12:14:52] [PASSED] pf_fails_bad_type
[12:14:52] [PASSED] pf_txn_reports_error
[12:14:52] [PASSED] pf_txn_sends_pf2guc
[12:14:52] [PASSED] pf_sends_pf2guc
[12:14:52] [SKIPPED] pf_loopback_nop
[12:14:52] [SKIPPED] pf_loopback_echo
[12:14:52] [SKIPPED] pf_loopback_fail
[12:14:52] [SKIPPED] pf_loopback_busy
[12:14:52] [SKIPPED] pf_loopback_retry
[12:14:52] ==================== [PASSED] pf_relay =====================
[12:14:52] ================== vf_relay (3 subtests) ===================
[12:14:52] [PASSED] vf_rejects_guc2vf_too_short
[12:14:52] [PASSED] vf_rejects_guc2vf_too_long
[12:14:52] [PASSED] vf_rejects_guc2vf_no_payload
[12:14:52] ==================== [PASSED] vf_relay =====================
[12:14:52] ================ pf_gt_config (9 subtests) =================
[12:14:52] [PASSED] fair_contexts_1vf
[12:14:52] [PASSED] fair_doorbells_1vf
[12:14:52] [PASSED] fair_ggtt_1vf
[12:14:52] ====================== fair_vram_1vf  ======================
[12:14:52] [PASSED] 3.50 GiB
[12:14:52] [PASSED] 11.5 GiB
[12:14:52] [PASSED] 15.5 GiB
[12:14:52] [PASSED] 31.5 GiB
[12:14:52] [PASSED] 63.5 GiB
[12:14:52] [PASSED] 1.91 GiB
[12:14:52] ================== [PASSED] fair_vram_1vf ==================
[12:14:52] ================ fair_vram_1vf_admin_only  =================
[12:14:52] [PASSED] 3.50 GiB
[12:14:52] [PASSED] 11.5 GiB
[12:14:52] [PASSED] 15.5 GiB
[12:14:52] [PASSED] 31.5 GiB
[12:14:52] [PASSED] 63.5 GiB
[12:14:52] [PASSED] 1.91 GiB
[12:14:52] ============ [PASSED] fair_vram_1vf_admin_only =============
[12:14:52] ====================== fair_contexts  ======================
[12:14:52] [PASSED] 1 VF
[12:14:52] [PASSED] 2 VFs
[12:14:52] [PASSED] 3 VFs
[12:14:52] [PASSED] 4 VFs
[12:14:52] [PASSED] 5 VFs
[12:14:52] [PASSED] 6 VFs
[12:14:52] [PASSED] 7 VFs
[12:14:52] [PASSED] 8 VFs
[12:14:52] [PASSED] 9 VFs
[12:14:52] [PASSED] 10 VFs
[12:14:52] [PASSED] 11 VFs
[12:14:52] [PASSED] 12 VFs
[12:14:52] [PASSED] 13 VFs
[12:14:52] [PASSED] 14 VFs
[12:14:52] [PASSED] 15 VFs
[12:14:52] [PASSED] 16 VFs
[12:14:52] [PASSED] 17 VFs
[12:14:52] [PASSED] 18 VFs
[12:14:52] [PASSED] 19 VFs
[12:14:52] [PASSED] 20 VFs
[12:14:52] [PASSED] 21 VFs
[12:14:52] [PASSED] 22 VFs
[12:14:52] [PASSED] 23 VFs
[12:14:52] [PASSED] 24 VFs
[12:14:52] [PASSED] 25 VFs
[12:14:52] [PASSED] 26 VFs
[12:14:52] [PASSED] 27 VFs
[12:14:52] [PASSED] 28 VFs
[12:14:52] [PASSED] 29 VFs
[12:14:52] [PASSED] 30 VFs
[12:14:52] [PASSED] 31 VFs
[12:14:52] [PASSED] 32 VFs
[12:14:52] [PASSED] 33 VFs
[12:14:52] [PASSED] 34 VFs
[12:14:52] [PASSED] 35 VFs
[12:14:52] [PASSED] 36 VFs
[12:14:52] [PASSED] 37 VFs
[12:14:52] [PASSED] 38 VFs
[12:14:52] [PASSED] 39 VFs
[12:14:52] [PASSED] 40 VFs
[12:14:52] [PASSED] 41 VFs
[12:14:52] [PASSED] 42 VFs
[12:14:52] [PASSED] 43 VFs
[12:14:52] [PASSED] 44 VFs
[12:14:52] [PASSED] 45 VFs
[12:14:52] [PASSED] 46 VFs
[12:14:52] [PASSED] 47 VFs
[12:14:52] [PASSED] 48 VFs
[12:14:52] [PASSED] 49 VFs
[12:14:52] [PASSED] 50 VFs
[12:14:52] [PASSED] 51 VFs
[12:14:52] [PASSED] 52 VFs
[12:14:52] [PASSED] 53 VFs
[12:14:52] [PASSED] 54 VFs
[12:14:52] [PASSED] 55 VFs
[12:14:52] [PASSED] 56 VFs
[12:14:52] [PASSED] 57 VFs
[12:14:52] [PASSED] 58 VFs
[12:14:52] [PASSED] 59 VFs
[12:14:52] [PASSED] 60 VFs
[12:14:52] [PASSED] 61 VFs
[12:14:52] [PASSED] 62 VFs
[12:14:52] [PASSED] 63 VFs
[12:14:52] ================== [PASSED] fair_contexts ==================
[12:14:52] ===================== fair_doorbells  ======================
[12:14:52] [PASSED] 1 VF
[12:14:52] [PASSED] 2 VFs
[12:14:52] [PASSED] 3 VFs
[12:14:52] [PASSED] 4 VFs
[12:14:52] [PASSED] 5 VFs
[12:14:52] [PASSED] 6 VFs
[12:14:52] [PASSED] 7 VFs
[12:14:52] [PASSED] 8 VFs
[12:14:52] [PASSED] 9 VFs
[12:14:52] [PASSED] 10 VFs
[12:14:52] [PASSED] 11 VFs
[12:14:52] [PASSED] 12 VFs
[12:14:52] [PASSED] 13 VFs
[12:14:52] [PASSED] 14 VFs
[12:14:52] [PASSED] 15 VFs
[12:14:52] [PASSED] 16 VFs
[12:14:52] [PASSED] 17 VFs
[12:14:52] [PASSED] 18 VFs
[12:14:52] [PASSED] 19 VFs
[12:14:52] [PASSED] 20 VFs
[12:14:52] [PASSED] 21 VFs
[12:14:52] [PASSED] 22 VFs
[12:14:52] [PASSED] 23 VFs
[12:14:52] [PASSED] 24 VFs
[12:14:52] [PASSED] 25 VFs
[12:14:52] [PASSED] 26 VFs
[12:14:52] [PASSED] 27 VFs
[12:14:52] [PASSED] 28 VFs
[12:14:52] [PASSED] 29 VFs
[12:14:52] [PASSED] 30 VFs
[12:14:52] [PASSED] 31 VFs
[12:14:52] [PASSED] 32 VFs
[12:14:52] [PASSED] 33 VFs
[12:14:52] [PASSED] 34 VFs
[12:14:52] [PASSED] 35 VFs
[12:14:52] [PASSED] 36 VFs
[12:14:52] [PASSED] 37 VFs
[12:14:52] [PASSED] 38 VFs
[12:14:52] [PASSED] 39 VFs
[12:14:52] [PASSED] 40 VFs
[12:14:52] [PASSED] 41 VFs
[12:14:52] [PASSED] 42 VFs
[12:14:52] [PASSED] 43 VFs
[12:14:52] [PASSED] 44 VFs
[12:14:52] [PASSED] 45 VFs
[12:14:52] [PASSED] 46 VFs
[12:14:52] [PASSED] 47 VFs
[12:14:52] [PASSED] 48 VFs
[12:14:52] [PASSED] 49 VFs
[12:14:52] [PASSED] 50 VFs
[12:14:52] [PASSED] 51 VFs
[12:14:52] [PASSED] 52 VFs
[12:14:52] [PASSED] 53 VFs
[12:14:52] [PASSED] 54 VFs
[12:14:52] [PASSED] 55 VFs
[12:14:52] [PASSED] 56 VFs
[12:14:52] [PASSED] 57 VFs
[12:14:52] [PASSED] 58 VFs
[12:14:52] [PASSED] 59 VFs
[12:14:52] [PASSED] 60 VFs
[12:14:52] [PASSED] 61 VFs
[12:14:52] [PASSED] 62 VFs
[12:14:52] [PASSED] 63 VFs
[12:14:52] ================= [PASSED] fair_doorbells ==================
[12:14:52] ======================== fair_ggtt  ========================
[12:14:52] [PASSED] 1 VF
[12:14:52] [PASSED] 2 VFs
[12:14:52] [PASSED] 3 VFs
[12:14:52] [PASSED] 4 VFs
[12:14:52] [PASSED] 5 VFs
[12:14:52] [PASSED] 6 VFs
[12:14:52] [PASSED] 7 VFs
[12:14:52] [PASSED] 8 VFs
[12:14:52] [PASSED] 9 VFs
[12:14:52] [PASSED] 10 VFs
[12:14:52] [PASSED] 11 VFs
[12:14:52] [PASSED] 12 VFs
[12:14:52] [PASSED] 13 VFs
[12:14:52] [PASSED] 14 VFs
[12:14:52] [PASSED] 15 VFs
[12:14:52] [PASSED] 16 VFs
[12:14:52] [PASSED] 17 VFs
[12:14:52] [PASSED] 18 VFs
[12:14:52] [PASSED] 19 VFs
[12:14:52] [PASSED] 20 VFs
[12:14:52] [PASSED] 21 VFs
[12:14:52] [PASSED] 22 VFs
[12:14:52] [PASSED] 23 VFs
[12:14:52] [PASSED] 24 VFs
[12:14:52] [PASSED] 25 VFs
[12:14:52] [PASSED] 26 VFs
[12:14:52] [PASSED] 27 VFs
[12:14:52] [PASSED] 28 VFs
[12:14:52] [PASSED] 29 VFs
[12:14:52] [PASSED] 30 VFs
[12:14:52] [PASSED] 31 VFs
[12:14:52] [PASSED] 32 VFs
[12:14:52] [PASSED] 33 VFs
[12:14:52] [PASSED] 34 VFs
[12:14:52] [PASSED] 35 VFs
[12:14:52] [PASSED] 36 VFs
[12:14:52] [PASSED] 37 VFs
[12:14:52] [PASSED] 38 VFs
[12:14:52] [PASSED] 39 VFs
[12:14:52] [PASSED] 40 VFs
[12:14:52] [PASSED] 41 VFs
[12:14:52] [PASSED] 42 VFs
[12:14:52] [PASSED] 43 VFs
[12:14:52] [PASSED] 44 VFs
[12:14:52] [PASSED] 45 VFs
[12:14:52] [PASSED] 46 VFs
[12:14:52] [PASSED] 47 VFs
[12:14:52] [PASSED] 48 VFs
[12:14:52] [PASSED] 49 VFs
[12:14:52] [PASSED] 50 VFs
[12:14:52] [PASSED] 51 VFs
[12:14:52] [PASSED] 52 VFs
[12:14:52] [PASSED] 53 VFs
[12:14:52] [PASSED] 54 VFs
[12:14:52] [PASSED] 55 VFs
[12:14:52] [PASSED] 56 VFs
[12:14:52] [PASSED] 57 VFs
[12:14:52] [PASSED] 58 VFs
[12:14:52] [PASSED] 59 VFs
[12:14:52] [PASSED] 60 VFs
[12:14:52] [PASSED] 61 VFs
[12:14:52] [PASSED] 62 VFs
[12:14:52] [PASSED] 63 VFs
[12:14:52] ==================== [PASSED] fair_ggtt ====================
[12:14:52] ======================== fair_vram  ========================
[12:14:52] [PASSED] 1 VF
[12:14:52] [PASSED] 2 VFs
[12:14:52] [PASSED] 3 VFs
[12:14:52] [PASSED] 4 VFs
[12:14:52] [PASSED] 5 VFs
[12:14:52] [PASSED] 6 VFs
[12:14:52] [PASSED] 7 VFs
[12:14:52] [PASSED] 8 VFs
[12:14:52] [PASSED] 9 VFs
[12:14:52] [PASSED] 10 VFs
[12:14:52] [PASSED] 11 VFs
[12:14:52] [PASSED] 12 VFs
[12:14:52] [PASSED] 13 VFs
[12:14:52] [PASSED] 14 VFs
[12:14:52] [PASSED] 15 VFs
[12:14:52] [PASSED] 16 VFs
[12:14:52] [PASSED] 17 VFs
[12:14:52] [PASSED] 18 VFs
[12:14:52] [PASSED] 19 VFs
[12:14:52] [PASSED] 20 VFs
[12:14:52] [PASSED] 21 VFs
[12:14:52] [PASSED] 22 VFs
[12:14:52] [PASSED] 23 VFs
[12:14:52] [PASSED] 24 VFs
[12:14:52] [PASSED] 25 VFs
[12:14:52] [PASSED] 26 VFs
[12:14:52] [PASSED] 27 VFs
[12:14:52] [PASSED] 28 VFs
[12:14:52] [PASSED] 29 VFs
[12:14:52] [PASSED] 30 VFs
[12:14:52] [PASSED] 31 VFs
[12:14:52] [PASSED] 32 VFs
[12:14:52] [PASSED] 33 VFs
[12:14:52] [PASSED] 34 VFs
[12:14:52] [PASSED] 35 VFs
[12:14:52] [PASSED] 36 VFs
[12:14:52] [PASSED] 37 VFs
[12:14:52] [PASSED] 38 VFs
[12:14:52] [PASSED] 39 VFs
[12:14:52] [PASSED] 40 VFs
[12:14:52] [PASSED] 41 VFs
[12:14:52] [PASSED] 42 VFs
[12:14:52] [PASSED] 43 VFs
[12:14:52] [PASSED] 44 VFs
[12:14:52] [PASSED] 45 VFs
[12:14:52] [PASSED] 46 VFs
[12:14:52] [PASSED] 47 VFs
[12:14:52] [PASSED] 48 VFs
[12:14:52] [PASSED] 49 VFs
[12:14:52] [PASSED] 50 VFs
[12:14:52] [PASSED] 51 VFs
[12:14:52] [PASSED] 52 VFs
[12:14:52] [PASSED] 53 VFs
[12:14:52] [PASSED] 54 VFs
[12:14:52] [PASSED] 55 VFs
[12:14:52] [PASSED] 56 VFs
[12:14:52] [PASSED] 57 VFs
[12:14:52] [PASSED] 58 VFs
[12:14:52] [PASSED] 59 VFs
[12:14:52] [PASSED] 60 VFs
[12:14:52] [PASSED] 61 VFs
[12:14:52] [PASSED] 62 VFs
[12:14:52] [PASSED] 63 VFs
[12:14:52] ==================== [PASSED] fair_vram ====================
[12:14:52] ================== [PASSED] pf_gt_config ===================
[12:14:52] ===================== lmtt (1 subtest) =====================
[12:14:52] ======================== test_ops  =========================
[12:14:52] [PASSED] 2-level
[12:14:52] [PASSED] multi-level
[12:14:52] ==================== [PASSED] test_ops =====================
[12:14:52] ====================== [PASSED] lmtt =======================
[12:14:52] ================= pf_service (11 subtests) =================
[12:14:52] [PASSED] pf_negotiate_any
[12:14:52] [PASSED] pf_negotiate_base_match
[12:14:52] [PASSED] pf_negotiate_base_newer
[12:14:52] [PASSED] pf_negotiate_base_next
[12:14:52] [SKIPPED] pf_negotiate_base_older
[12:14:52] [PASSED] pf_negotiate_base_prev
[12:14:52] [PASSED] pf_negotiate_latest_match
[12:14:52] [PASSED] pf_negotiate_latest_newer
[12:14:52] [PASSED] pf_negotiate_latest_next
[12:14:52] [SKIPPED] pf_negotiate_latest_older
[12:14:52] [SKIPPED] pf_negotiate_latest_prev
[12:14:52] =================== [PASSED] pf_service ====================
[12:14:52] ================= xe_guc_g2g (2 subtests) ==================
[12:14:52] ============== xe_live_guc_g2g_kunit_default  ==============
[12:14:52] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[12:14:52] ============== xe_live_guc_g2g_kunit_allmem  ===============
[12:14:52] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[12:14:52] =================== [SKIPPED] xe_guc_g2g ===================
[12:14:52] =================== xe_mocs (2 subtests) ===================
[12:14:52] ================ xe_live_mocs_kernel_kunit  ================
[12:14:52] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[12:14:52] ================ xe_live_mocs_reset_kunit  =================
[12:14:52] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[12:14:52] ==================== [SKIPPED] xe_mocs =====================
[12:14:52] ================= xe_migrate (2 subtests) ==================
[12:14:52] ================= xe_migrate_sanity_kunit  =================
[12:14:52] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[12:14:52] ================== xe_validate_ccs_kunit  ==================
[12:14:52] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[12:14:52] =================== [SKIPPED] xe_migrate ===================
[12:14:52] ================== xe_dma_buf (1 subtest) ==================
[12:14:52] ==================== xe_dma_buf_kunit  =====================
[12:14:52] ================ [SKIPPED] xe_dma_buf_kunit ================
[12:14:52] =================== [SKIPPED] xe_dma_buf ===================
[12:14:52] ================= xe_bo_shrink (1 subtest) =================
[12:14:52] =================== xe_bo_shrink_kunit  ====================
[12:14:52] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[12:14:52] ================== [SKIPPED] xe_bo_shrink ==================
[12:14:52] ==================== xe_bo (2 subtests) ====================
[12:14:52] ================== xe_ccs_migrate_kunit  ===================
[12:14:52] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[12:14:52] ==================== xe_bo_evict_kunit  ====================
[12:14:52] =============== [SKIPPED] xe_bo_evict_kunit ================
[12:14:52] ===================== [SKIPPED] xe_bo ======================
[12:14:52] ==================== args (13 subtests) ====================
[12:14:52] [PASSED] count_args_test
[12:14:52] [PASSED] call_args_example
[12:14:52] [PASSED] call_args_test
[12:14:52] [PASSED] drop_first_arg_example
[12:14:52] [PASSED] drop_first_arg_test
[12:14:52] [PASSED] first_arg_example
[12:14:52] [PASSED] first_arg_test
[12:14:52] [PASSED] last_arg_example
[12:14:52] [PASSED] last_arg_test
[12:14:52] [PASSED] pick_arg_example
[12:14:52] [PASSED] if_args_example
[12:14:52] [PASSED] if_args_test
[12:14:52] [PASSED] sep_comma_example
[12:14:52] ====================== [PASSED] args =======================
[12:14:52] =================== xe_pci (3 subtests) ====================
[12:14:52] ==================== check_graphics_ip  ====================
[12:14:52] [PASSED] 12.00 Xe_LP
[12:14:52] [PASSED] 12.10 Xe_LP+
[12:14:52] [PASSED] 12.55 Xe_HPG
[12:14:52] [PASSED] 12.60 Xe_HPC
[12:14:52] [PASSED] 12.70 Xe_LPG
[12:14:52] [PASSED] 12.71 Xe_LPG
[12:14:52] [PASSED] 12.74 Xe_LPG+
[12:14:52] [PASSED] 20.01 Xe2_HPG
[12:14:52] [PASSED] 20.02 Xe2_HPG
[12:14:52] [PASSED] 20.04 Xe2_LPG
[12:14:52] [PASSED] 30.00 Xe3_LPG
[12:14:52] [PASSED] 30.01 Xe3_LPG
[12:14:52] [PASSED] 30.03 Xe3_LPG
[12:14:52] [PASSED] 30.04 Xe3_LPG
[12:14:52] [PASSED] 30.05 Xe3_LPG
[12:14:52] [PASSED] 35.10 Xe3p_LPG
[12:14:52] [PASSED] 35.11 Xe3p_XPC
[12:14:52] ================ [PASSED] check_graphics_ip ================
[12:14:52] ===================== check_media_ip  ======================
[12:14:52] [PASSED] 12.00 Xe_M
[12:14:52] [PASSED] 12.55 Xe_HPM
[12:14:52] [PASSED] 13.00 Xe_LPM+
[12:14:52] [PASSED] 13.01 Xe2_HPM
[12:14:52] [PASSED] 20.00 Xe2_LPM
[12:14:52] [PASSED] 30.00 Xe3_LPM
[12:14:52] [PASSED] 30.02 Xe3_LPM
[12:14:52] [PASSED] 35.00 Xe3p_LPM
[12:14:52] [PASSED] 35.03 Xe3p_HPM
[12:14:52] ================= [PASSED] check_media_ip ==================
[12:14:52] =================== check_platform_desc  ===================
[12:14:52] [PASSED] 0x9A60 (TIGERLAKE)
[12:14:52] [PASSED] 0x9A68 (TIGERLAKE)
[12:14:52] [PASSED] 0x9A70 (TIGERLAKE)
[12:14:52] [PASSED] 0x9A40 (TIGERLAKE)
[12:14:52] [PASSED] 0x9A49 (TIGERLAKE)
[12:14:52] [PASSED] 0x9A59 (TIGERLAKE)
[12:14:52] [PASSED] 0x9A78 (TIGERLAKE)
[12:14:52] [PASSED] 0x9AC0 (TIGERLAKE)
[12:14:52] [PASSED] 0x9AC9 (TIGERLAKE)
[12:14:52] [PASSED] 0x9AD9 (TIGERLAKE)
[12:14:52] [PASSED] 0x9AF8 (TIGERLAKE)
[12:14:52] [PASSED] 0x4C80 (ROCKETLAKE)
[12:14:52] [PASSED] 0x4C8A (ROCKETLAKE)
[12:14:52] [PASSED] 0x4C8B (ROCKETLAKE)
[12:14:52] [PASSED] 0x4C8C (ROCKETLAKE)
[12:14:52] [PASSED] 0x4C90 (ROCKETLAKE)
[12:14:52] [PASSED] 0x4C9A (ROCKETLAKE)
[12:14:52] [PASSED] 0x4680 (ALDERLAKE_S)
[12:14:52] [PASSED] 0x4682 (ALDERLAKE_S)
[12:14:52] [PASSED] 0x4688 (ALDERLAKE_S)
[12:14:52] [PASSED] 0x468A (ALDERLAKE_S)
[12:14:52] [PASSED] 0x468B (ALDERLAKE_S)
[12:14:52] [PASSED] 0x4690 (ALDERLAKE_S)
[12:14:52] [PASSED] 0x4692 (ALDERLAKE_S)
[12:14:52] [PASSED] 0x4693 (ALDERLAKE_S)
[12:14:52] [PASSED] 0x46A0 (ALDERLAKE_P)
[12:14:52] [PASSED] 0x46A1 (ALDERLAKE_P)
[12:14:52] [PASSED] 0x46A2 (ALDERLAKE_P)
[12:14:52] [PASSED] 0x46A3 (ALDERLAKE_P)
[12:14:52] [PASSED] 0x46A6 (ALDERLAKE_P)
[12:14:52] [PASSED] 0x46A8 (ALDERLAKE_P)
[12:14:52] [PASSED] 0x46AA (ALDERLAKE_P)
[12:14:52] [PASSED] 0x462A (ALDERLAKE_P)
[12:14:52] [PASSED] 0x4626 (ALDERLAKE_P)
[12:14:52] [PASSED] 0x4628 (ALDERLAKE_P)
[12:14:52] [PASSED] 0x46B0 (ALDERLAKE_P)
[12:14:52] [PASSED] 0x46B1 (ALDERLAKE_P)
[12:14:52] [PASSED] 0x46B2 (ALDERLAKE_P)
[12:14:52] [PASSED] 0x46B3 (ALDERLAKE_P)
[12:14:52] [PASSED] 0x46C0 (ALDERLAKE_P)
[12:14:52] [PASSED] 0x46C1 (ALDERLAKE_P)
[12:14:52] [PASSED] 0x46C2 (ALDERLAKE_P)
[12:14:52] [PASSED] 0x46C3 (ALDERLAKE_P)
[12:14:52] [PASSED] 0x46D0 (ALDERLAKE_N)
[12:14:52] [PASSED] 0x46D1 (ALDERLAKE_N)
[12:14:52] [PASSED] 0x46D2 (ALDERLAKE_N)
[12:14:52] [PASSED] 0x46D3 (ALDERLAKE_N)
[12:14:52] [PASSED] 0x46D4 (ALDERLAKE_N)
[12:14:52] [PASSED] 0xA721 (ALDERLAKE_P)
[12:14:52] [PASSED] 0xA7A1 (ALDERLAKE_P)
[12:14:52] [PASSED] 0xA7A9 (ALDERLAKE_P)
[12:14:52] [PASSED] 0xA7AC (ALDERLAKE_P)
[12:14:52] [PASSED] 0xA7AD (ALDERLAKE_P)
[12:14:52] [PASSED] 0xA720 (ALDERLAKE_P)
[12:14:52] [PASSED] 0xA7A0 (ALDERLAKE_P)
[12:14:52] [PASSED] 0xA7A8 (ALDERLAKE_P)
[12:14:52] [PASSED] 0xA7AA (ALDERLAKE_P)
[12:14:52] [PASSED] 0xA7AB (ALDERLAKE_P)
[12:14:52] [PASSED] 0xA780 (ALDERLAKE_S)
[12:14:52] [PASSED] 0xA781 (ALDERLAKE_S)
[12:14:52] [PASSED] 0xA782 (ALDERLAKE_S)
[12:14:52] [PASSED] 0xA783 (ALDERLAKE_S)
[12:14:52] [PASSED] 0xA788 (ALDERLAKE_S)
[12:14:52] [PASSED] 0xA789 (ALDERLAKE_S)
[12:14:52] [PASSED] 0xA78A (ALDERLAKE_S)
[12:14:52] [PASSED] 0xA78B (ALDERLAKE_S)
[12:14:52] [PASSED] 0x4905 (DG1)
[12:14:52] [PASSED] 0x4906 (DG1)
[12:14:52] [PASSED] 0x4907 (DG1)
[12:14:52] [PASSED] 0x4908 (DG1)
[12:14:52] [PASSED] 0x4909 (DG1)
[12:14:52] [PASSED] 0x56C0 (DG2)
[12:14:52] [PASSED] 0x56C2 (DG2)
[12:14:52] [PASSED] 0x56C1 (DG2)
[12:14:52] [PASSED] 0x7D51 (METEORLAKE)
[12:14:52] [PASSED] 0x7DD1 (METEORLAKE)
[12:14:52] [PASSED] 0x7D41 (METEORLAKE)
[12:14:52] [PASSED] 0x7D67 (METEORLAKE)
[12:14:52] [PASSED] 0xB640 (METEORLAKE)
[12:14:52] [PASSED] 0x56A0 (DG2)
[12:14:52] [PASSED] 0x56A1 (DG2)
[12:14:52] [PASSED] 0x56A2 (DG2)
[12:14:52] [PASSED] 0x56BE (DG2)
[12:14:52] [PASSED] 0x56BF (DG2)
[12:14:52] [PASSED] 0x5690 (DG2)
[12:14:52] [PASSED] 0x5691 (DG2)
[12:14:52] [PASSED] 0x5692 (DG2)
[12:14:52] [PASSED] 0x56A5 (DG2)
[12:14:52] [PASSED] 0x56A6 (DG2)
[12:14:52] [PASSED] 0x56B0 (DG2)
[12:14:52] [PASSED] 0x56B1 (DG2)
[12:14:52] [PASSED] 0x56BA (DG2)
[12:14:52] [PASSED] 0x56BB (DG2)
[12:14:52] [PASSED] 0x56BC (DG2)
[12:14:52] [PASSED] 0x56BD (DG2)
[12:14:52] [PASSED] 0x5693 (DG2)
[12:14:52] [PASSED] 0x5694 (DG2)
[12:14:52] [PASSED] 0x5695 (DG2)
[12:14:52] [PASSED] 0x56A3 (DG2)
[12:14:52] [PASSED] 0x56A4 (DG2)
[12:14:52] [PASSED] 0x56B2 (DG2)
[12:14:52] [PASSED] 0x56B3 (DG2)
[12:14:52] [PASSED] 0x5696 (DG2)
[12:14:52] [PASSED] 0x5697 (DG2)
[12:14:52] [PASSED] 0xB69 (PVC)
[12:14:52] [PASSED] 0xB6E (PVC)
[12:14:52] [PASSED] 0xBD4 (PVC)
[12:14:52] [PASSED] 0xBD5 (PVC)
[12:14:52] [PASSED] 0xBD6 (PVC)
[12:14:52] [PASSED] 0xBD7 (PVC)
[12:14:52] [PASSED] 0xBD8 (PVC)
[12:14:52] [PASSED] 0xBD9 (PVC)
[12:14:52] [PASSED] 0xBDA (PVC)
[12:14:52] [PASSED] 0xBDB (PVC)
[12:14:52] [PASSED] 0xBE0 (PVC)
[12:14:52] [PASSED] 0xBE1 (PVC)
[12:14:52] [PASSED] 0xBE5 (PVC)
[12:14:52] [PASSED] 0x7D40 (METEORLAKE)
[12:14:52] [PASSED] 0x7D45 (METEORLAKE)
[12:14:52] [PASSED] 0x7D55 (METEORLAKE)
[12:14:52] [PASSED] 0x7D60 (METEORLAKE)
[12:14:52] [PASSED] 0x7DD5 (METEORLAKE)
[12:14:52] [PASSED] 0x6420 (LUNARLAKE)
[12:14:52] [PASSED] 0x64A0 (LUNARLAKE)
[12:14:52] [PASSED] 0x64B0 (LUNARLAKE)
[12:14:52] [PASSED] 0xE202 (BATTLEMAGE)
[12:14:52] [PASSED] 0xE209 (BATTLEMAGE)
[12:14:52] [PASSED] 0xE20B (BATTLEMAGE)
[12:14:52] [PASSED] 0xE20C (BATTLEMAGE)
[12:14:52] [PASSED] 0xE20D (BATTLEMAGE)
[12:14:52] [PASSED] 0xE210 (BATTLEMAGE)
[12:14:52] [PASSED] 0xE211 (BATTLEMAGE)
[12:14:52] [PASSED] 0xE212 (BATTLEMAGE)
[12:14:52] [PASSED] 0xE216 (BATTLEMAGE)
[12:14:52] [PASSED] 0xE220 (BATTLEMAGE)
[12:14:52] [PASSED] 0xE221 (BATTLEMAGE)
[12:14:52] [PASSED] 0xE222 (BATTLEMAGE)
[12:14:52] [PASSED] 0xE223 (BATTLEMAGE)
[12:14:52] [PASSED] 0xB080 (PANTHERLAKE)
[12:14:52] [PASSED] 0xB081 (PANTHERLAKE)
[12:14:52] [PASSED] 0xB082 (PANTHERLAKE)
[12:14:52] [PASSED] 0xB083 (PANTHERLAKE)
[12:14:52] [PASSED] 0xB084 (PANTHERLAKE)
[12:14:52] [PASSED] 0xB085 (PANTHERLAKE)
[12:14:52] [PASSED] 0xB086 (PANTHERLAKE)
[12:14:52] [PASSED] 0xB087 (PANTHERLAKE)
[12:14:52] [PASSED] 0xB08F (PANTHERLAKE)
[12:14:52] [PASSED] 0xB090 (PANTHERLAKE)
[12:14:52] [PASSED] 0xB0A0 (PANTHERLAKE)
[12:14:52] [PASSED] 0xB0B0 (PANTHERLAKE)
[12:14:52] [PASSED] 0xFD80 (PANTHERLAKE)
[12:14:52] [PASSED] 0xFD81 (PANTHERLAKE)
[12:14:52] [PASSED] 0xD740 (NOVALAKE_S)
[12:14:52] [PASSED] 0xD741 (NOVALAKE_S)
[12:14:52] [PASSED] 0xD742 (NOVALAKE_S)
[12:14:52] [PASSED] 0xD743 (NOVALAKE_S)
[12:14:52] [PASSED] 0xD744 (NOVALAKE_S)
[12:14:52] [PASSED] 0xD745 (NOVALAKE_S)
[12:14:52] [PASSED] 0x674C (CRESCENTISLAND)
[12:14:52] [PASSED] 0xD750 (NOVALAKE_P)
[12:14:52] [PASSED] 0xD751 (NOVALAKE_P)
[12:14:52] [PASSED] 0xD752 (NOVALAKE_P)
[12:14:52] [PASSED] 0xD753 (NOVALAKE_P)
[12:14:52] [PASSED] 0xD754 (NOVALAKE_P)
[12:14:52] [PASSED] 0xD755 (NOVALAKE_P)
[12:14:52] [PASSED] 0xD756 (NOVALAKE_P)
[12:14:52] [PASSED] 0xD757 (NOVALAKE_P)
[12:14:52] [PASSED] 0xD75F (NOVALAKE_P)
[12:14:52] =============== [PASSED] check_platform_desc ===============
[12:14:52] ===================== [PASSED] xe_pci ======================
[12:14:52] =================== xe_rtp (2 subtests) ====================
[12:14:52] =============== xe_rtp_process_to_sr_tests  ================
[12:14:52] [PASSED] coalesce-same-reg
[12:14:52] [PASSED] no-match-no-add
[12:14:52] [PASSED] match-or
[12:14:52] [PASSED] match-or-xfail
[12:14:52] [PASSED] no-match-no-add-multiple-rules
[12:14:52] [PASSED] two-regs-two-entries
[12:14:52] [PASSED] clr-one-set-other
[12:14:52] [PASSED] set-field
[12:14:52] [PASSED] conflict-duplicate
[12:14:52] [PASSED] conflict-not-disjoint
[12:14:52] [PASSED] conflict-reg-type
[12:14:52] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[12:14:52] ================== xe_rtp_process_tests  ===================
[12:14:52] [PASSED] active1
[12:14:52] [PASSED] active2
[12:14:52] [PASSED] active-inactive
[12:14:52] [PASSED] inactive-active
[12:14:52] [PASSED] inactive-1st_or_active-inactive
[12:14:52] [PASSED] inactive-2nd_or_active-inactive
[12:14:52] [PASSED] inactive-last_or_active-inactive
[12:14:52] [PASSED] inactive-no_or_active-inactive
[12:14:52] ============== [PASSED] xe_rtp_process_tests ===============
[12:14:52] ===================== [PASSED] xe_rtp ======================
[12:14:52] ==================== xe_wa (1 subtest) =====================
[12:14:52] ======================== xe_wa_gt  =========================
[12:14:52] [PASSED] TIGERLAKE B0
[12:14:52] [PASSED] DG1 A0
[12:14:52] [PASSED] DG1 B0
[12:14:52] [PASSED] ALDERLAKE_S A0
[12:14:52] [PASSED] ALDERLAKE_S B0
[12:14:52] [PASSED] ALDERLAKE_S C0
[12:14:52] [PASSED] ALDERLAKE_S D0
[12:14:52] [PASSED] ALDERLAKE_P A0
[12:14:52] [PASSED] ALDERLAKE_P B0
[12:14:52] [PASSED] ALDERLAKE_P C0
[12:14:52] [PASSED] ALDERLAKE_S RPLS D0
[12:14:52] [PASSED] ALDERLAKE_P RPLU E0
[12:14:52] [PASSED] DG2 G10 C0
[12:14:52] [PASSED] DG2 G11 B1
[12:14:52] [PASSED] DG2 G12 A1
[12:14:52] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:14:52] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:14:52] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[12:14:52] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[12:14:52] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[12:14:52] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[12:14:52] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[12:14:52] ==================== [PASSED] xe_wa_gt =====================
[12:14:52] ====================== [PASSED] xe_wa ======================
[12:14:52] ============================================================
[12:14:52] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[12:14:53] Elapsed time: 36.077s total, 4.289s configuring, 31.172s building, 0.603s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[12:14:53] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:14:54] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:15:19] Starting KUnit Kernel (1/1)...
[12:15:19] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:15:19] ============ drm_test_pick_cmdline (2 subtests) ============
[12:15:19] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[12:15:19] =============== drm_test_pick_cmdline_named  ===============
[12:15:19] [PASSED] NTSC
[12:15:19] [PASSED] NTSC-J
[12:15:19] [PASSED] PAL
[12:15:19] [PASSED] PAL-M
[12:15:19] =========== [PASSED] drm_test_pick_cmdline_named ===========
[12:15:19] ============== [PASSED] drm_test_pick_cmdline ==============
[12:15:19] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[12:15:19] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[12:15:19] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[12:15:19] =========== drm_validate_clone_mode (2 subtests) ===========
[12:15:19] ============== drm_test_check_in_clone_mode  ===============
[12:15:19] [PASSED] in_clone_mode
[12:15:19] [PASSED] not_in_clone_mode
[12:15:19] ========== [PASSED] drm_test_check_in_clone_mode ===========
[12:15:19] =============== drm_test_check_valid_clones  ===============
[12:15:19] [PASSED] not_in_clone_mode
[12:15:19] [PASSED] valid_clone
[12:15:19] [PASSED] invalid_clone
[12:15:19] =========== [PASSED] drm_test_check_valid_clones ===========
[12:15:19] ============= [PASSED] drm_validate_clone_mode =============
[12:15:19] ============= drm_validate_modeset (1 subtest) =============
[12:15:19] [PASSED] drm_test_check_connector_changed_modeset
[12:15:19] ============== [PASSED] drm_validate_modeset ===============
[12:15:19] ====== drm_test_bridge_get_current_state (2 subtests) ======
[12:15:19] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[12:15:19] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[12:15:19] ======== [PASSED] drm_test_bridge_get_current_state ========
[12:15:19] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[12:15:19] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[12:15:19] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[12:15:19] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[12:15:19] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[12:15:19] ============== drm_bridge_alloc (2 subtests) ===============
[12:15:19] [PASSED] drm_test_drm_bridge_alloc_basic
[12:15:19] [PASSED] drm_test_drm_bridge_alloc_get_put
[12:15:19] ================ [PASSED] drm_bridge_alloc =================
[12:15:19] ============= drm_cmdline_parser (40 subtests) =============
[12:15:19] [PASSED] drm_test_cmdline_force_d_only
[12:15:19] [PASSED] drm_test_cmdline_force_D_only_dvi
[12:15:19] [PASSED] drm_test_cmdline_force_D_only_hdmi
[12:15:19] [PASSED] drm_test_cmdline_force_D_only_not_digital
[12:15:19] [PASSED] drm_test_cmdline_force_e_only
[12:15:19] [PASSED] drm_test_cmdline_res
[12:15:19] [PASSED] drm_test_cmdline_res_vesa
[12:15:19] [PASSED] drm_test_cmdline_res_vesa_rblank
[12:15:19] [PASSED] drm_test_cmdline_res_rblank
[12:15:19] [PASSED] drm_test_cmdline_res_bpp
[12:15:19] [PASSED] drm_test_cmdline_res_refresh
[12:15:19] [PASSED] drm_test_cmdline_res_bpp_refresh
[12:15:19] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[12:15:19] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[12:15:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[12:15:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[12:15:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[12:15:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[12:15:19] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[12:15:19] [PASSED] drm_test_cmdline_res_margins_force_on
[12:15:19] [PASSED] drm_test_cmdline_res_vesa_margins
[12:15:19] [PASSED] drm_test_cmdline_name
[12:15:19] [PASSED] drm_test_cmdline_name_bpp
[12:15:19] [PASSED] drm_test_cmdline_name_option
[12:15:19] [PASSED] drm_test_cmdline_name_bpp_option
[12:15:19] [PASSED] drm_test_cmdline_rotate_0
[12:15:19] [PASSED] drm_test_cmdline_rotate_90
[12:15:19] [PASSED] drm_test_cmdline_rotate_180
[12:15:19] [PASSED] drm_test_cmdline_rotate_270
[12:15:19] [PASSED] drm_test_cmdline_hmirror
[12:15:19] [PASSED] drm_test_cmdline_vmirror
[12:15:19] [PASSED] drm_test_cmdline_margin_options
[12:15:19] [PASSED] drm_test_cmdline_multiple_options
[12:15:19] [PASSED] drm_test_cmdline_bpp_extra_and_option
[12:15:19] [PASSED] drm_test_cmdline_extra_and_option
[12:15:19] [PASSED] drm_test_cmdline_freestanding_options
[12:15:19] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[12:15:19] [PASSED] drm_test_cmdline_panel_orientation
[12:15:19] ================ drm_test_cmdline_invalid  =================
[12:15:19] [PASSED] margin_only
[12:15:19] [PASSED] interlace_only
[12:15:19] [PASSED] res_missing_x
[12:15:19] [PASSED] res_missing_y
[12:15:19] [PASSED] res_bad_y
[12:15:19] [PASSED] res_missing_y_bpp
[12:15:19] [PASSED] res_bad_bpp
[12:15:19] [PASSED] res_bad_refresh
[12:15:19] [PASSED] res_bpp_refresh_force_on_off
[12:15:19] [PASSED] res_invalid_mode
[12:15:19] [PASSED] res_bpp_wrong_place_mode
[12:15:19] [PASSED] name_bpp_refresh
[12:15:19] [PASSED] name_refresh
[12:15:19] [PASSED] name_refresh_wrong_mode
[12:15:19] [PASSED] name_refresh_invalid_mode
[12:15:19] [PASSED] rotate_multiple
[12:15:19] [PASSED] rotate_invalid_val
[12:15:19] [PASSED] rotate_truncated
[12:15:19] [PASSED] invalid_option
[12:15:19] [PASSED] invalid_tv_option
[12:15:19] [PASSED] truncated_tv_option
[12:15:19] ============ [PASSED] drm_test_cmdline_invalid =============
[12:15:19] =============== drm_test_cmdline_tv_options  ===============
[12:15:19] [PASSED] NTSC
[12:15:19] [PASSED] NTSC_443
[12:15:19] [PASSED] NTSC_J
[12:15:19] [PASSED] PAL
[12:15:19] [PASSED] PAL_M
[12:15:19] [PASSED] PAL_N
[12:15:19] [PASSED] SECAM
[12:15:19] [PASSED] MONO_525
[12:15:19] [PASSED] MONO_625
[12:15:19] =========== [PASSED] drm_test_cmdline_tv_options ===========
[12:15:19] =============== [PASSED] drm_cmdline_parser ================
[12:15:19] ========== drmm_connector_hdmi_init (20 subtests) ==========
[12:15:19] [PASSED] drm_test_connector_hdmi_init_valid
[12:15:19] [PASSED] drm_test_connector_hdmi_init_bpc_8
[12:15:19] [PASSED] drm_test_connector_hdmi_init_bpc_10
[12:15:19] [PASSED] drm_test_connector_hdmi_init_bpc_12
[12:15:19] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[12:15:19] [PASSED] drm_test_connector_hdmi_init_bpc_null
[12:15:19] [PASSED] drm_test_connector_hdmi_init_formats_empty
[12:15:19] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[12:15:19] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[12:15:19] [PASSED] supported_formats=0x9 yuv420_allowed=1
[12:15:19] [PASSED] supported_formats=0x9 yuv420_allowed=0
[12:15:19] [PASSED] supported_formats=0x5 yuv420_allowed=1
[12:15:19] [PASSED] supported_formats=0x5 yuv420_allowed=0
[12:15:19] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[12:15:19] [PASSED] drm_test_connector_hdmi_init_null_ddc
[12:15:19] [PASSED] drm_test_connector_hdmi_init_null_product
[12:15:19] [PASSED] drm_test_connector_hdmi_init_null_vendor
[12:15:19] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[12:15:19] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[12:15:19] [PASSED] drm_test_connector_hdmi_init_product_valid
[12:15:19] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[12:15:19] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[12:15:19] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[12:15:19] ========= drm_test_connector_hdmi_init_type_valid  =========
[12:15:19] [PASSED] HDMI-A
[12:15:19] [PASSED] HDMI-B
[12:15:19] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[12:15:19] ======== drm_test_connector_hdmi_init_type_invalid  ========
[12:15:19] [PASSED] Unknown
[12:15:19] [PASSED] VGA
[12:15:19] [PASSED] DVI-I
[12:15:19] [PASSED] DVI-D
[12:15:19] [PASSED] DVI-A
[12:15:19] [PASSED] Composite
[12:15:19] [PASSED] SVIDEO
[12:15:19] [PASSED] LVDS
[12:15:19] [PASSED] Component
[12:15:19] [PASSED] DIN
[12:15:19] [PASSED] DP
[12:15:19] [PASSED] TV
[12:15:19] [PASSED] eDP
[12:15:19] [PASSED] Virtual
[12:15:19] [PASSED] DSI
[12:15:19] [PASSED] DPI
[12:15:19] [PASSED] Writeback
[12:15:19] [PASSED] SPI
[12:15:19] [PASSED] USB
[12:15:19] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[12:15:19] ============ [PASSED] drmm_connector_hdmi_init =============
[12:15:19] ============= drmm_connector_init (3 subtests) =============
[12:15:19] [PASSED] drm_test_drmm_connector_init
[12:15:19] [PASSED] drm_test_drmm_connector_init_null_ddc
[12:15:19] ========= drm_test_drmm_connector_init_type_valid  =========
[12:15:19] [PASSED] Unknown
[12:15:19] [PASSED] VGA
[12:15:19] [PASSED] DVI-I
[12:15:19] [PASSED] DVI-D
[12:15:19] [PASSED] DVI-A
[12:15:19] [PASSED] Composite
[12:15:19] [PASSED] SVIDEO
[12:15:19] [PASSED] LVDS
[12:15:19] [PASSED] Component
[12:15:19] [PASSED] DIN
[12:15:19] [PASSED] DP
[12:15:19] [PASSED] HDMI-A
[12:15:19] [PASSED] HDMI-B
[12:15:19] [PASSED] TV
[12:15:19] [PASSED] eDP
[12:15:19] [PASSED] Virtual
[12:15:19] [PASSED] DSI
[12:15:19] [PASSED] DPI
[12:15:19] [PASSED] Writeback
[12:15:19] [PASSED] SPI
[12:15:19] [PASSED] USB
[12:15:19] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[12:15:19] =============== [PASSED] drmm_connector_init ===============
[12:15:19] ========= drm_connector_dynamic_init (6 subtests) ==========
[12:15:19] [PASSED] drm_test_drm_connector_dynamic_init
[12:15:19] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[12:15:19] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[12:15:19] [PASSED] drm_test_drm_connector_dynamic_init_properties
[12:15:19] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[12:15:19] [PASSED] Unknown
[12:15:19] [PASSED] VGA
[12:15:19] [PASSED] DVI-I
[12:15:19] [PASSED] DVI-D
[12:15:19] [PASSED] DVI-A
[12:15:19] [PASSED] Composite
[12:15:19] [PASSED] SVIDEO
[12:15:19] [PASSED] LVDS
[12:15:19] [PASSED] Component
[12:15:19] [PASSED] DIN
[12:15:19] [PASSED] DP
[12:15:19] [PASSED] HDMI-A
[12:15:19] [PASSED] HDMI-B
[12:15:19] [PASSED] TV
[12:15:19] [PASSED] eDP
[12:15:19] [PASSED] Virtual
[12:15:19] [PASSED] DSI
[12:15:19] [PASSED] DPI
[12:15:19] [PASSED] Writeback
[12:15:19] [PASSED] SPI
[12:15:19] [PASSED] USB
[12:15:19] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[12:15:19] ======== drm_test_drm_connector_dynamic_init_name  =========
[12:15:19] [PASSED] Unknown
[12:15:19] [PASSED] VGA
[12:15:19] [PASSED] DVI-I
[12:15:19] [PASSED] DVI-D
[12:15:19] [PASSED] DVI-A
[12:15:19] [PASSED] Composite
[12:15:19] [PASSED] SVIDEO
[12:15:19] [PASSED] LVDS
[12:15:19] [PASSED] Component
[12:15:19] [PASSED] DIN
[12:15:19] [PASSED] DP
[12:15:19] [PASSED] HDMI-A
[12:15:19] [PASSED] HDMI-B
[12:15:19] [PASSED] TV
[12:15:19] [PASSED] eDP
[12:15:19] [PASSED] Virtual
[12:15:19] [PASSED] DSI
[12:15:19] [PASSED] DPI
[12:15:19] [PASSED] Writeback
[12:15:19] [PASSED] SPI
[12:15:19] [PASSED] USB
[12:15:19] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[12:15:19] =========== [PASSED] drm_connector_dynamic_init ============
[12:15:19] ==== drm_connector_dynamic_register_early (4 subtests) =====
[12:15:19] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[12:15:19] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[12:15:19] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[12:15:19] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[12:15:19] ====== [PASSED] drm_connector_dynamic_register_early =======
[12:15:19] ======= drm_connector_dynamic_register (7 subtests) ========
[12:15:19] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[12:15:19] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[12:15:19] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[12:15:19] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[12:15:19] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[12:15:19] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[12:15:19] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[12:15:19] ========= [PASSED] drm_connector_dynamic_register ==========
[12:15:19] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[12:15:19] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[12:15:19] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[12:15:19] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[12:15:19] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[12:15:19] ========== drm_test_get_tv_mode_from_name_valid  ===========
[12:15:19] [PASSED] NTSC
[12:15:19] [PASSED] NTSC-443
[12:15:19] [PASSED] NTSC-J
[12:15:19] [PASSED] PAL
[12:15:19] [PASSED] PAL-M
[12:15:19] [PASSED] PAL-N
[12:15:19] [PASSED] SECAM
[12:15:19] [PASSED] Mono
[12:15:19] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[12:15:19] [PASSED] drm_test_get_tv_mode_from_name_truncated
[12:15:19] ============ [PASSED] drm_get_tv_mode_from_name ============
[12:15:19] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[12:15:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[12:15:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[12:15:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[12:15:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[12:15:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[12:15:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[12:15:19] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[12:15:19] [PASSED] VIC 96
[12:15:19] [PASSED] VIC 97
[12:15:19] [PASSED] VIC 101
[12:15:19] [PASSED] VIC 102
[12:15:19] [PASSED] VIC 106
[12:15:19] [PASSED] VIC 107
[12:15:19] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[12:15:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[12:15:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[12:15:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[12:15:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[12:15:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[12:15:19] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[12:15:19] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[12:15:19] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[12:15:19] [PASSED] Automatic
[12:15:19] [PASSED] Full
[12:15:19] [PASSED] Limited 16:235
[12:15:19] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[12:15:19] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[12:15:19] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[12:15:19] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[12:15:19] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[12:15:19] [PASSED] RGB
[12:15:19] [PASSED] YUV 4:2:0
[12:15:19] [PASSED] YUV 4:2:2
[12:15:19] [PASSED] YUV 4:4:4
[12:15:19] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[12:15:19] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[12:15:19] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[12:15:19] ============= drm_damage_helper (21 subtests) ==============
[12:15:19] [PASSED] drm_test_damage_iter_no_damage
[12:15:19] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[12:15:19] [PASSED] drm_test_damage_iter_no_damage_src_moved
[12:15:19] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[12:15:19] [PASSED] drm_test_damage_iter_no_damage_not_visible
[12:15:19] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[12:15:19] [PASSED] drm_test_damage_iter_no_damage_no_fb
[12:15:19] [PASSED] drm_test_damage_iter_simple_damage
[12:15:19] [PASSED] drm_test_damage_iter_single_damage
[12:15:19] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[12:15:19] [PASSED] drm_test_damage_iter_single_damage_outside_src
[12:15:19] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[12:15:19] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[12:15:19] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[12:15:19] [PASSED] drm_test_damage_iter_single_damage_src_moved
[12:15:19] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[12:15:19] [PASSED] drm_test_damage_iter_damage
[12:15:19] [PASSED] drm_test_damage_iter_damage_one_intersect
[12:15:19] [PASSED] drm_test_damage_iter_damage_one_outside
[12:15:19] [PASSED] drm_test_damage_iter_damage_src_moved
[12:15:19] [PASSED] drm_test_damage_iter_damage_not_visible
[12:15:19] ================ [PASSED] drm_damage_helper ================
[12:15:19] ============== drm_dp_mst_helper (3 subtests) ==============
[12:15:19] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[12:15:19] [PASSED] Clock 154000 BPP 30 DSC disabled
[12:15:19] [PASSED] Clock 234000 BPP 30 DSC disabled
[12:15:19] [PASSED] Clock 297000 BPP 24 DSC disabled
[12:15:19] [PASSED] Clock 332880 BPP 24 DSC enabled
[12:15:19] [PASSED] Clock 324540 BPP 24 DSC enabled
[12:15:19] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[12:15:19] ============== drm_test_dp_mst_calc_pbn_div  ===============
[12:15:19] [PASSED] Link rate 2000000 lane count 4
[12:15:19] [PASSED] Link rate 2000000 lane count 2
[12:15:19] [PASSED] Link rate 2000000 lane count 1
[12:15:19] [PASSED] Link rate 1350000 lane count 4
[12:15:19] [PASSED] Link rate 1350000 lane count 2
[12:15:19] [PASSED] Link rate 1350000 lane count 1
[12:15:19] [PASSED] Link rate 1000000 lane count 4
[12:15:19] [PASSED] Link rate 1000000 lane count 2
[12:15:19] [PASSED] Link rate 1000000 lane count 1
[12:15:19] [PASSED] Link rate 810000 lane count 4
[12:15:19] [PASSED] Link rate 810000 lane count 2
[12:15:19] [PASSED] Link rate 810000 lane count 1
[12:15:19] [PASSED] Link rate 540000 lane count 4
[12:15:19] [PASSED] Link rate 540000 lane count 2
[12:15:19] [PASSED] Link rate 540000 lane count 1
[12:15:19] [PASSED] Link rate 270000 lane count 4
[12:15:19] [PASSED] Link rate 270000 lane count 2
[12:15:19] [PASSED] Link rate 270000 lane count 1
[12:15:19] [PASSED] Link rate 162000 lane count 4
[12:15:19] [PASSED] Link rate 162000 lane count 2
[12:15:19] [PASSED] Link rate 162000 lane count 1
[12:15:19] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[12:15:19] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[12:15:19] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[12:15:19] [PASSED] DP_POWER_UP_PHY with port number
[12:15:19] [PASSED] DP_POWER_DOWN_PHY with port number
[12:15:19] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[12:15:19] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[12:15:19] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[12:15:19] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[12:15:19] [PASSED] DP_QUERY_PAYLOAD with port number
[12:15:19] [PASSED] DP_QUERY_PAYLOAD with VCPI
[12:15:19] [PASSED] DP_REMOTE_DPCD_READ with port number
[12:15:19] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[12:15:19] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[12:15:19] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[12:15:19] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[12:15:19] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[12:15:19] [PASSED] DP_REMOTE_I2C_READ with port number
[12:15:19] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[12:15:19] [PASSED] DP_REMOTE_I2C_READ with transactions array
[12:15:19] [PASSED] DP_REMOTE_I2C_WRITE with port number
[12:15:19] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[12:15:19] [PASSED] DP_REMOTE_I2C_WRITE with data array
[12:15:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[12:15:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[12:15:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[12:15:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[12:15:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[12:15:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[12:15:19] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[12:15:19] ================ [PASSED] drm_dp_mst_helper ================
[12:15:19] ================== drm_exec (7 subtests) ===================
[12:15:19] [PASSED] sanitycheck
[12:15:19] [PASSED] test_lock
[12:15:19] [PASSED] test_lock_unlock
[12:15:19] [PASSED] test_duplicates
[12:15:19] [PASSED] test_prepare
[12:15:19] [PASSED] test_prepare_array
[12:15:19] [PASSED] test_multiple_loops
[12:15:19] ==================== [PASSED] drm_exec =====================
[12:15:19] =========== drm_format_helper_test (17 subtests) ===========
[12:15:19] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[12:15:19] [PASSED] single_pixel_source_buffer
[12:15:19] [PASSED] single_pixel_clip_rectangle
[12:15:19] [PASSED] well_known_colors
[12:15:19] [PASSED] destination_pitch
[12:15:19] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[12:15:19] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[12:15:19] [PASSED] single_pixel_source_buffer
[12:15:19] [PASSED] single_pixel_clip_rectangle
[12:15:19] [PASSED] well_known_colors
[12:15:19] [PASSED] destination_pitch
[12:15:19] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[12:15:19] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[12:15:19] [PASSED] single_pixel_source_buffer
[12:15:19] [PASSED] single_pixel_clip_rectangle
[12:15:19] [PASSED] well_known_colors
[12:15:19] [PASSED] destination_pitch
[12:15:19] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[12:15:19] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[12:15:19] [PASSED] single_pixel_source_buffer
[12:15:19] [PASSED] single_pixel_clip_rectangle
[12:15:19] [PASSED] well_known_colors
[12:15:19] [PASSED] destination_pitch
[12:15:19] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[12:15:19] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[12:15:19] [PASSED] single_pixel_source_buffer
[12:15:19] [PASSED] single_pixel_clip_rectangle
[12:15:19] [PASSED] well_known_colors
[12:15:19] [PASSED] destination_pitch
[12:15:19] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[12:15:19] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[12:15:19] [PASSED] single_pixel_source_buffer
[12:15:19] [PASSED] single_pixel_clip_rectangle
[12:15:19] [PASSED] well_known_colors
[12:15:19] [PASSED] destination_pitch
[12:15:19] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[12:15:19] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[12:15:19] [PASSED] single_pixel_source_buffer
[12:15:19] [PASSED] single_pixel_clip_rectangle
[12:15:19] [PASSED] well_known_colors
[12:15:19] [PASSED] destination_pitch
[12:15:19] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[12:15:19] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[12:15:19] [PASSED] single_pixel_source_buffer
[12:15:19] [PASSED] single_pixel_clip_rectangle
[12:15:19] [PASSED] well_known_colors
[12:15:19] [PASSED] destination_pitch
[12:15:19] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[12:15:19] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[12:15:19] [PASSED] single_pixel_source_buffer
[12:15:19] [PASSED] single_pixel_clip_rectangle
[12:15:19] [PASSED] well_known_colors
[12:15:19] [PASSED] destination_pitch
[12:15:19] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[12:15:19] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[12:15:19] [PASSED] single_pixel_source_buffer
[12:15:19] [PASSED] single_pixel_clip_rectangle
[12:15:19] [PASSED] well_known_colors
[12:15:19] [PASSED] destination_pitch
[12:15:19] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[12:15:19] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[12:15:19] [PASSED] single_pixel_source_buffer
[12:15:19] [PASSED] single_pixel_clip_rectangle
[12:15:19] [PASSED] well_known_colors
[12:15:19] [PASSED] destination_pitch
[12:15:19] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[12:15:19] ============== drm_test_fb_xrgb8888_to_mono  ===============
[12:15:19] [PASSED] single_pixel_source_buffer
[12:15:19] [PASSED] single_pixel_clip_rectangle
[12:15:19] [PASSED] well_known_colors
[12:15:19] [PASSED] destination_pitch
[12:15:19] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[12:15:19] ==================== drm_test_fb_swab  =====================
[12:15:19] [PASSED] single_pixel_source_buffer
[12:15:19] [PASSED] single_pixel_clip_rectangle
[12:15:19] [PASSED] well_known_colors
[12:15:19] [PASSED] destination_pitch
[12:15:19] ================ [PASSED] drm_test_fb_swab =================
[12:15:19] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[12:15:19] [PASSED] single_pixel_source_buffer
[12:15:19] [PASSED] single_pixel_clip_rectangle
[12:15:19] [PASSED] well_known_colors
[12:15:19] [PASSED] destination_pitch
[12:15:19] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[12:15:19] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[12:15:19] [PASSED] single_pixel_source_buffer
[12:15:19] [PASSED] single_pixel_clip_rectangle
[12:15:19] [PASSED] well_known_colors
[12:15:19] [PASSED] destination_pitch
[12:15:19] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[12:15:19] ================= drm_test_fb_clip_offset  =================
[12:15:19] [PASSED] pass through
[12:15:19] [PASSED] horizontal offset
[12:15:19] [PASSED] vertical offset
[12:15:19] [PASSED] horizontal and vertical offset
[12:15:19] [PASSED] horizontal offset (custom pitch)
[12:15:19] [PASSED] vertical offset (custom pitch)
[12:15:19] [PASSED] horizontal and vertical offset (custom pitch)
[12:15:19] ============= [PASSED] drm_test_fb_clip_offset =============
[12:15:19] =================== drm_test_fb_memcpy  ====================
[12:15:19] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[12:15:19] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[12:15:19] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[12:15:19] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[12:15:19] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[12:15:19] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[12:15:19] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[12:15:19] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[12:15:19] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[12:15:19] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[12:15:19] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[12:15:19] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[12:15:19] =============== [PASSED] drm_test_fb_memcpy ================
[12:15:19] ============= [PASSED] drm_format_helper_test ==============
[12:15:19] ================= drm_format (18 subtests) =================
[12:15:19] [PASSED] drm_test_format_block_width_invalid
[12:15:19] [PASSED] drm_test_format_block_width_one_plane
[12:15:19] [PASSED] drm_test_format_block_width_two_plane
[12:15:19] [PASSED] drm_test_format_block_width_three_plane
[12:15:19] [PASSED] drm_test_format_block_width_tiled
[12:15:19] [PASSED] drm_test_format_block_height_invalid
[12:15:19] [PASSED] drm_test_format_block_height_one_plane
[12:15:19] [PASSED] drm_test_format_block_height_two_plane
[12:15:19] [PASSED] drm_test_format_block_height_three_plane
[12:15:19] [PASSED] drm_test_format_block_height_tiled
[12:15:19] [PASSED] drm_test_format_min_pitch_invalid
[12:15:19] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[12:15:19] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[12:15:19] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[12:15:19] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[12:15:19] [PASSED] drm_test_format_min_pitch_two_plane
[12:15:19] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[12:15:19] [PASSED] drm_test_format_min_pitch_tiled
[12:15:19] =================== [PASSED] drm_format ====================
[12:15:19] ============== drm_framebuffer (10 subtests) ===============
[12:15:19] ========== drm_test_framebuffer_check_src_coords  ==========
[12:15:19] [PASSED] Success: source fits into fb
[12:15:19] [PASSED] Fail: overflowing fb with x-axis coordinate
[12:15:19] [PASSED] Fail: overflowing fb with y-axis coordinate
[12:15:19] [PASSED] Fail: overflowing fb with source width
[12:15:19] [PASSED] Fail: overflowing fb with source height
[12:15:19] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[12:15:19] [PASSED] drm_test_framebuffer_cleanup
[12:15:19] =============== drm_test_framebuffer_create  ===============
[12:15:19] [PASSED] ABGR8888 normal sizes
[12:15:19] [PASSED] ABGR8888 max sizes
[12:15:19] [PASSED] ABGR8888 pitch greater than min required
[12:15:19] [PASSED] ABGR8888 pitch less than min required
[12:15:19] [PASSED] ABGR8888 Invalid width
[12:15:19] [PASSED] ABGR8888 Invalid buffer handle
[12:15:19] [PASSED] No pixel format
[12:15:19] [PASSED] ABGR8888 Width 0
[12:15:19] [PASSED] ABGR8888 Height 0
[12:15:19] [PASSED] ABGR8888 Out of bound height * pitch combination
[12:15:19] [PASSED] ABGR8888 Large buffer offset
[12:15:19] [PASSED] ABGR8888 Buffer offset for inexistent plane
[12:15:19] [PASSED] ABGR8888 Invalid flag
[12:15:19] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[12:15:19] [PASSED] ABGR8888 Valid buffer modifier
[12:15:19] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[12:15:19] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[12:15:19] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[12:15:19] [PASSED] NV12 Normal sizes
[12:15:19] [PASSED] NV12 Max sizes
[12:15:19] [PASSED] NV12 Invalid pitch
[12:15:19] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[12:15:19] [PASSED] NV12 different  modifier per-plane
[12:15:19] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[12:15:19] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[12:15:19] [PASSED] NV12 Modifier for inexistent plane
[12:15:19] [PASSED] NV12 Handle for inexistent plane
[12:15:19] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[12:15:19] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[12:15:19] [PASSED] YVU420 Normal sizes
[12:15:19] [PASSED] YVU420 Max sizes
[12:15:19] [PASSED] YVU420 Invalid pitch
[12:15:19] [PASSED] YVU420 Different pitches
[12:15:19] [PASSED] YVU420 Different buffer offsets/pitches
[12:15:19] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[12:15:19] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[12:15:19] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[12:15:19] [PASSED] YVU420 Valid modifier
[12:15:19] [PASSED] YVU420 Different modifiers per plane
[12:15:19] [PASSED] YVU420 Modifier for inexistent plane
[12:15:19] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[12:15:19] [PASSED] X0L2 Normal sizes
[12:15:19] [PASSED] X0L2 Max sizes
[12:15:19] [PASSED] X0L2 Invalid pitch
[12:15:19] [PASSED] X0L2 Pitch greater than minimum required
[12:15:19] [PASSED] X0L2 Handle for inexistent plane
[12:15:19] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[12:15:19] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[12:15:19] [PASSED] X0L2 Valid modifier
[12:15:19] [PASSED] X0L2 Modifier for inexistent plane
[12:15:19] =========== [PASSED] drm_test_framebuffer_create ===========
[12:15:19] [PASSED] drm_test_framebuffer_free
[12:15:19] [PASSED] drm_test_framebuffer_init
[12:15:19] [PASSED] drm_test_framebuffer_init_bad_format
[12:15:19] [PASSED] drm_test_framebuffer_init_dev_mismatch
[12:15:19] [PASSED] drm_test_framebuffer_lookup
[12:15:19] [PASSED] drm_test_framebuffer_lookup_inexistent
[12:15:19] [PASSED] drm_test_framebuffer_modifiers_not_supported
[12:15:19] ================= [PASSED] drm_framebuffer =================
[12:15:19] ================ drm_gem_shmem (8 subtests) ================
[12:15:19] [PASSED] drm_gem_shmem_test_obj_create
[12:15:19] [PASSED] drm_gem_shmem_test_obj_create_private
[12:15:19] [PASSED] drm_gem_shmem_test_pin_pages
[12:15:19] [PASSED] drm_gem_shmem_test_vmap
[12:15:19] [PASSED] drm_gem_shmem_test_get_sg_table
[12:15:19] [PASSED] drm_gem_shmem_test_get_pages_sgt
[12:15:19] [PASSED] drm_gem_shmem_test_madvise
[12:15:19] [PASSED] drm_gem_shmem_test_purge
[12:15:19] ================== [PASSED] drm_gem_shmem ==================
[12:15:19] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[12:15:19] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[12:15:19] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[12:15:19] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[12:15:19] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[12:15:19] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[12:15:19] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[12:15:19] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[12:15:19] [PASSED] Automatic
[12:15:19] [PASSED] Full
[12:15:19] [PASSED] Limited 16:235
[12:15:19] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[12:15:19] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[12:15:19] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[12:15:19] [PASSED] drm_test_check_disable_connector
[12:15:19] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[12:15:19] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[12:15:19] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[12:15:19] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[12:15:19] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[12:15:19] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[12:15:19] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[12:15:19] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[12:15:19] [PASSED] drm_test_check_output_bpc_dvi
[12:15:19] [PASSED] drm_test_check_output_bpc_format_vic_1
[12:15:19] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[12:15:19] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[12:15:19] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[12:15:19] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[12:15:19] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[12:15:19] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[12:15:19] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[12:15:19] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[12:15:19] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[12:15:19] [PASSED] drm_test_check_broadcast_rgb_value
[12:15:19] [PASSED] drm_test_check_bpc_8_value
[12:15:19] [PASSED] drm_test_check_bpc_10_value
[12:15:19] [PASSED] drm_test_check_bpc_12_value
[12:15:19] [PASSED] drm_test_check_format_value
[12:15:19] [PASSED] drm_test_check_tmds_char_value
[12:15:19] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[12:15:19] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[12:15:19] [PASSED] drm_test_check_mode_valid
[12:15:19] [PASSED] drm_test_check_mode_valid_reject
[12:15:19] [PASSED] drm_test_check_mode_valid_reject_rate
[12:15:19] [PASSED] drm_test_check_mode_valid_reject_max_clock
[12:15:19] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[12:15:19] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[12:15:19] [PASSED] drm_test_check_infoframes
[12:15:19] [PASSED] drm_test_check_reject_avi_infoframe
[12:15:19] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[12:15:19] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[12:15:19] [PASSED] drm_test_check_reject_audio_infoframe
[12:15:19] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[12:15:19] ================= drm_managed (2 subtests) =================
[12:15:19] [PASSED] drm_test_managed_release_action
[12:15:19] [PASSED] drm_test_managed_run_action
[12:15:19] =================== [PASSED] drm_managed ===================
[12:15:19] =================== drm_mm (6 subtests) ====================
[12:15:19] [PASSED] drm_test_mm_init
[12:15:19] [PASSED] drm_test_mm_debug
[12:15:19] [PASSED] drm_test_mm_align32
[12:15:19] [PASSED] drm_test_mm_align64
[12:15:19] [PASSED] drm_test_mm_lowest
[12:15:19] [PASSED] drm_test_mm_highest
[12:15:19] ===================== [PASSED] drm_mm ======================
[12:15:19] ============= drm_modes_analog_tv (5 subtests) =============
[12:15:19] [PASSED] drm_test_modes_analog_tv_mono_576i
[12:15:19] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[12:15:19] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[12:15:19] [PASSED] drm_test_modes_analog_tv_pal_576i
[12:15:19] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[12:15:19] =============== [PASSED] drm_modes_analog_tv ===============
[12:15:19] ============== drm_plane_helper (2 subtests) ===============
[12:15:19] =============== drm_test_check_plane_state  ================
[12:15:19] [PASSED] clipping_simple
[12:15:19] [PASSED] clipping_rotate_reflect
[12:15:19] [PASSED] positioning_simple
[12:15:19] [PASSED] upscaling
[12:15:19] [PASSED] downscaling
[12:15:19] [PASSED] rounding1
[12:15:19] [PASSED] rounding2
[12:15:19] [PASSED] rounding3
[12:15:19] [PASSED] rounding4
[12:15:19] =========== [PASSED] drm_test_check_plane_state ============
[12:15:19] =========== drm_test_check_invalid_plane_state  ============
[12:15:19] [PASSED] positioning_invalid
[12:15:19] [PASSED] upscaling_invalid
[12:15:19] [PASSED] downscaling_invalid
[12:15:19] ======= [PASSED] drm_test_check_invalid_plane_state ========
[12:15:19] ================ [PASSED] drm_plane_helper =================
[12:15:19] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[12:15:19] ====== drm_test_connector_helper_tv_get_modes_check  =======
[12:15:19] [PASSED] None
[12:15:19] [PASSED] PAL
[12:15:19] [PASSED] NTSC
[12:15:19] [PASSED] Both, NTSC Default
[12:15:19] [PASSED] Both, PAL Default
[12:15:19] [PASSED] Both, NTSC Default, with PAL on command-line
[12:15:19] [PASSED] Both, PAL Default, with NTSC on command-line
[12:15:19] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[12:15:19] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[12:15:19] ================== drm_rect (9 subtests) ===================
[12:15:19] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[12:15:19] [PASSED] drm_test_rect_clip_scaled_not_clipped
[12:15:19] [PASSED] drm_test_rect_clip_scaled_clipped
[12:15:19] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[12:15:19] ================= drm_test_rect_intersect  =================
[12:15:19] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[12:15:19] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[12:15:19] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[12:15:19] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[12:15:19] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[12:15:19] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[12:15:19] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[12:15:19] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[12:15:19] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[12:15:19] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[12:15:19] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[12:15:19] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[12:15:19] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[12:15:19] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[12:15:19] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[12:15:19] ============= [PASSED] drm_test_rect_intersect =============
[12:15:19] ================ drm_test_rect_calc_hscale  ================
[12:15:19] [PASSED] normal use
[12:15:19] [PASSED] out of max range
[12:15:19] [PASSED] out of min range
[12:15:19] [PASSED] zero dst
[12:15:19] [PASSED] negative src
[12:15:19] [PASSED] negative dst
[12:15:19] ============ [PASSED] drm_test_rect_calc_hscale ============
[12:15:19] ================ drm_test_rect_calc_vscale  ================
[12:15:19] [PASSED] normal use
[12:15:19] [PASSED] out of max range
[12:15:19] [PASSED] out of min range
[12:15:19] [PASSED] zero dst
[12:15:19] [PASSED] negative src
[12:15:19] [PASSED] negative dst
[12:15:19] ============ [PASSED] drm_test_rect_calc_vscale ============
[12:15:19] ================== drm_test_rect_rotate  ===================
[12:15:19] [PASSED] reflect-x
[12:15:19] [PASSED] reflect-y
[12:15:19] [PASSED] rotate-0
[12:15:19] [PASSED] rotate-90
[12:15:19] [PASSED] rotate-180
[12:15:19] [PASSED] rotate-270
[12:15:19] ============== [PASSED] drm_test_rect_rotate ===============
[12:15:19] ================ drm_test_rect_rotate_inv  =================
[12:15:19] [PASSED] reflect-x
[12:15:19] [PASSED] reflect-y
[12:15:19] [PASSED] rotate-0
[12:15:19] [PASSED] rotate-90
[12:15:19] [PASSED] rotate-180
[12:15:19] [PASSED] rotate-270
[12:15:19] ============ [PASSED] drm_test_rect_rotate_inv =============
[12:15:19] ==================== [PASSED] drm_rect =====================
[12:15:19] ============ drm_sysfb_modeset_test (1 subtest) ============
[12:15:19] ============ drm_test_sysfb_build_fourcc_list  =============
[12:15:19] [PASSED] no native formats
[12:15:19] [PASSED] XRGB8888 as native format
[12:15:19] [PASSED] remove duplicates
[12:15:19] [PASSED] convert alpha formats
[12:15:19] [PASSED] random formats
[12:15:19] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[12:15:19] ============= [PASSED] drm_sysfb_modeset_test ==============
[12:15:19] ================== drm_fixp (2 subtests) ===================
[12:15:19] [PASSED] drm_test_int2fixp
[12:15:19] [PASSED] drm_test_sm2fixp
[12:15:19] ==================== [PASSED] drm_fixp =====================
[12:15:19] ============================================================
[12:15:19] Testing complete. Ran 621 tests: passed: 621
[12:15:19] Elapsed time: 26.155s total, 1.775s configuring, 24.216s building, 0.112s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[12:15:19] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:15:21] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:15:30] Starting KUnit Kernel (1/1)...
[12:15:30] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:15:30] ================= ttm_device (5 subtests) ==================
[12:15:30] [PASSED] ttm_device_init_basic
[12:15:30] [PASSED] ttm_device_init_multiple
[12:15:30] [PASSED] ttm_device_fini_basic
[12:15:30] [PASSED] ttm_device_init_no_vma_man
[12:15:30] ================== ttm_device_init_pools  ==================
[12:15:30] [PASSED] No DMA allocations, no DMA32 required
[12:15:30] [PASSED] DMA allocations, DMA32 required
[12:15:30] [PASSED] No DMA allocations, DMA32 required
[12:15:30] [PASSED] DMA allocations, no DMA32 required
[12:15:30] ============== [PASSED] ttm_device_init_pools ==============
[12:15:30] =================== [PASSED] ttm_device ====================
[12:15:30] ================== ttm_pool (8 subtests) ===================
[12:15:30] ================== ttm_pool_alloc_basic  ===================
[12:15:30] [PASSED] One page
[12:15:30] [PASSED] More than one page
[12:15:30] [PASSED] Above the allocation limit
[12:15:30] [PASSED] One page, with coherent DMA mappings enabled
[12:15:30] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:15:30] ============== [PASSED] ttm_pool_alloc_basic ===============
[12:15:30] ============== ttm_pool_alloc_basic_dma_addr  ==============
[12:15:30] [PASSED] One page
[12:15:30] [PASSED] More than one page
[12:15:30] [PASSED] Above the allocation limit
[12:15:30] [PASSED] One page, with coherent DMA mappings enabled
[12:15:30] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:15:30] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[12:15:30] [PASSED] ttm_pool_alloc_order_caching_match
[12:15:30] [PASSED] ttm_pool_alloc_caching_mismatch
[12:15:30] [PASSED] ttm_pool_alloc_order_mismatch
[12:15:30] [PASSED] ttm_pool_free_dma_alloc
[12:15:30] [PASSED] ttm_pool_free_no_dma_alloc
[12:15:30] [PASSED] ttm_pool_fini_basic
[12:15:30] ==================== [PASSED] ttm_pool =====================
[12:15:30] ================ ttm_resource (8 subtests) =================
[12:15:30] ================= ttm_resource_init_basic  =================
[12:15:30] [PASSED] Init resource in TTM_PL_SYSTEM
[12:15:30] [PASSED] Init resource in TTM_PL_VRAM
[12:15:30] [PASSED] Init resource in a private placement
[12:15:30] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[12:15:30] ============= [PASSED] ttm_resource_init_basic =============
[12:15:30] [PASSED] ttm_resource_init_pinned
[12:15:30] [PASSED] ttm_resource_fini_basic
[12:15:30] [PASSED] ttm_resource_manager_init_basic
[12:15:30] [PASSED] ttm_resource_manager_usage_basic
[12:15:30] [PASSED] ttm_resource_manager_set_used_basic
[12:15:30] [PASSED] ttm_sys_man_alloc_basic
[12:15:30] [PASSED] ttm_sys_man_free_basic
[12:15:30] ================== [PASSED] ttm_resource ===================
[12:15:30] =================== ttm_tt (15 subtests) ===================
[12:15:30] ==================== ttm_tt_init_basic  ====================
[12:15:30] [PASSED] Page-aligned size
[12:15:30] [PASSED] Extra pages requested
[12:15:30] ================ [PASSED] ttm_tt_init_basic ================
[12:15:30] [PASSED] ttm_tt_init_misaligned
[12:15:30] [PASSED] ttm_tt_fini_basic
[12:15:30] [PASSED] ttm_tt_fini_sg
[12:15:30] [PASSED] ttm_tt_fini_shmem
[12:15:30] [PASSED] ttm_tt_create_basic
[12:15:30] [PASSED] ttm_tt_create_invalid_bo_type
[12:15:30] [PASSED] ttm_tt_create_ttm_exists
[12:15:30] [PASSED] ttm_tt_create_failed
[12:15:30] [PASSED] ttm_tt_destroy_basic
[12:15:30] [PASSED] ttm_tt_populate_null_ttm
[12:15:30] [PASSED] ttm_tt_populate_populated_ttm
[12:15:30] [PASSED] ttm_tt_unpopulate_basic
[12:15:30] [PASSED] ttm_tt_unpopulate_empty_ttm
[12:15:30] [PASSED] ttm_tt_swapin_basic
[12:15:30] ===================== [PASSED] ttm_tt ======================
[12:15:30] =================== ttm_bo (14 subtests) ===================
[12:15:30] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[12:15:30] [PASSED] Cannot be interrupted and sleeps
[12:15:30] [PASSED] Cannot be interrupted, locks straight away
[12:15:30] [PASSED] Can be interrupted, sleeps
[12:15:30] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[12:15:30] [PASSED] ttm_bo_reserve_locked_no_sleep
[12:15:30] [PASSED] ttm_bo_reserve_no_wait_ticket
[12:15:30] [PASSED] ttm_bo_reserve_double_resv
[12:15:30] [PASSED] ttm_bo_reserve_interrupted
[12:15:30] [PASSED] ttm_bo_reserve_deadlock
[12:15:30] [PASSED] ttm_bo_unreserve_basic
[12:15:30] [PASSED] ttm_bo_unreserve_pinned
[12:15:30] [PASSED] ttm_bo_unreserve_bulk
[12:15:30] [PASSED] ttm_bo_fini_basic
[12:15:30] [PASSED] ttm_bo_fini_shared_resv
[12:15:30] [PASSED] ttm_bo_pin_basic
[12:15:30] [PASSED] ttm_bo_pin_unpin_resource
[12:15:30] [PASSED] ttm_bo_multiple_pin_one_unpin
[12:15:30] ===================== [PASSED] ttm_bo ======================
[12:15:30] ============== ttm_bo_validate (22 subtests) ===============
[12:15:30] ============== ttm_bo_init_reserved_sys_man  ===============
[12:15:30] [PASSED] Buffer object for userspace
[12:15:30] [PASSED] Kernel buffer object
[12:15:30] [PASSED] Shared buffer object
[12:15:30] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[12:15:30] ============== ttm_bo_init_reserved_mock_man  ==============
[12:15:30] [PASSED] Buffer object for userspace
[12:15:30] [PASSED] Kernel buffer object
[12:15:30] [PASSED] Shared buffer object
[12:15:30] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[12:15:30] [PASSED] ttm_bo_init_reserved_resv
[12:15:30] ================== ttm_bo_validate_basic  ==================
[12:15:30] [PASSED] Buffer object for userspace
[12:15:30] [PASSED] Kernel buffer object
[12:15:30] [PASSED] Shared buffer object
[12:15:30] ============== [PASSED] ttm_bo_validate_basic ==============
[12:15:30] [PASSED] ttm_bo_validate_invalid_placement
[12:15:30] ============= ttm_bo_validate_same_placement  ==============
[12:15:30] [PASSED] System manager
[12:15:30] [PASSED] VRAM manager
[12:15:30] ========= [PASSED] ttm_bo_validate_same_placement ==========
[12:15:30] [PASSED] ttm_bo_validate_failed_alloc
[12:15:30] [PASSED] ttm_bo_validate_pinned
[12:15:30] [PASSED] ttm_bo_validate_busy_placement
[12:15:30] ================ ttm_bo_validate_multihop  =================
[12:15:30] [PASSED] Buffer object for userspace
[12:15:30] [PASSED] Kernel buffer object
[12:15:30] [PASSED] Shared buffer object
[12:15:30] ============ [PASSED] ttm_bo_validate_multihop =============
[12:15:30] ========== ttm_bo_validate_no_placement_signaled  ==========
[12:15:30] [PASSED] Buffer object in system domain, no page vector
[12:15:30] [PASSED] Buffer object in system domain with an existing page vector
[12:15:30] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[12:15:30] ======== ttm_bo_validate_no_placement_not_signaled  ========
[12:15:30] [PASSED] Buffer object for userspace
[12:15:30] [PASSED] Kernel buffer object
[12:15:30] [PASSED] Shared buffer object
[12:15:30] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[12:15:30] [PASSED] ttm_bo_validate_move_fence_signaled
[12:15:30] ========= ttm_bo_validate_move_fence_not_signaled  =========
[12:15:30] [PASSED] Waits for GPU
[12:15:30] [PASSED] Tries to lock straight away
[12:15:30] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[12:15:30] [PASSED] ttm_bo_validate_swapout
[12:15:30] [PASSED] ttm_bo_validate_happy_evict
[12:15:30] [PASSED] ttm_bo_validate_all_pinned_evict
[12:15:30] [PASSED] ttm_bo_validate_allowed_only_evict
[12:15:30] [PASSED] ttm_bo_validate_deleted_evict
[12:15:30] [PASSED] ttm_bo_validate_busy_domain_evict
[12:15:30] [PASSED] ttm_bo_validate_evict_gutting
[12:15:30] [PASSED] ttm_bo_validate_recrusive_evict
[12:15:30] ================= [PASSED] ttm_bo_validate =================
[12:15:30] ============================================================
[12:15:30] Testing complete. Ran 102 tests: passed: 102
[12:15:30] Elapsed time: 11.482s total, 1.700s configuring, 9.567s building, 0.185s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915: refactor display funcs, add display irq hooks

[Patchwork]

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== Series Details ==

Series: drm/i915: refactor display funcs, add display irq hooks
URL   : https://patchwork.freedesktop.org/series/165710/
State : success

== Summary ==

CI Bug Log - changes from xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5_BAT -> xe-pw-165710v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5 -> xe-pw-165710v1

  IGT_8879: 02b0e01dd9a5a3ab1efe976bb8c4f13cfcdbab1a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5: 1db870ffb55b6414a78d7609ba7e08adf880dfc5
  xe-pw-165710v1: 165710v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/index.html

[-- Attachment #2: Type: text/html, Size: 1517 bytes --]

✗ Xe.CI.FULL: failure for drm/i915: refactor display funcs, add display irq hooks

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 47908 bytes --]

== Series Details ==

Series: drm/i915: refactor display funcs, add display irq hooks
URL   : https://patchwork.freedesktop.org/series/165710/
State : failure

== Summary ==

CI Bug Log - changes from xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5_FULL -> xe-pw-165710v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-165710v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-165710v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-165710v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_exec_reset@multi-queue-gt-reset:
    - shard-bmg:          NOTRUN -> [SKIP][1] +2 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-4/igt@xe_exec_reset@multi-queue-gt-reset.html

  
Known issues
------------

  Here are the changes found in xe-pw-165710v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@x-tiled-16bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][2] ([Intel XE#2327]) +2 other tests skip
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-addfb:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#2328] / [Intel XE#7367]) +1 other test skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-3/igt@kms_big_fb@y-tiled-addfb.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#607] / [Intel XE#7361])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-4/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#1124]) +8 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][6] ([Intel XE#1124]) +1 other test skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_bw@connected-linear-tiling-4-displays-target-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#7679]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@kms_bw@connected-linear-tiling-4-displays-target-2160x1440p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-target-3840x2160p:
    - shard-lnl:          NOTRUN -> [SKIP][8] ([Intel XE#7676])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_bw@connected-linear-tiling-4-displays-target-3840x2160p.html

  * igt@kms_bw@linear-tiling-2-displays-target-1920x1080p:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#367]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-4/igt@kms_bw@linear-tiling-2-displays-target-1920x1080p.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [PASS][10] -> [INCOMPLETE][11] ([Intel XE#7084]) +1 other test incomplete
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][12] ([Intel XE#2669] / [Intel XE#3433] / [Intel XE#7389]) +3 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-a-edp-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-b-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#2652]) +8 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-4/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-b-dp-2.html

  * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#2887]) +13 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][15] ([Intel XE#2887]) +3 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_chamelium_color@ctm-negative:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#2325] / [Intel XE#7358]) +2 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@kms_chamelium_color@ctm-negative.html

  * igt@kms_chamelium_edid@hdmi-edid-change-during-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][17] ([Intel XE#373]) +1 other test skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2252]) +5 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-4/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_color_pipeline@plane-lut3d-green-only@pipe-b-plane-0:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#6969]) +10 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-4/igt@kms_color_pipeline@plane-lut3d-green-only@pipe-b-plane-0.html

  * igt@kms_color_pipeline@plane-lut3d-green-only@pipe-d-plane-2:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#6969] / [Intel XE#7006]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-4/igt@kms_color_pipeline@plane-lut3d-green-only@pipe-d-plane-2.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-lnl:          NOTRUN -> [SKIP][21] ([Intel XE#307] / [Intel XE#6974])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@dp-mst-type-1-suspend-resume:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#6974])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-3/igt@kms_content_protection@dp-mst-type-1-suspend-resume.html

  * igt@kms_content_protection@lic-type-1:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#7642])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@kms_content_protection@lic-type-1.html

  * igt@kms_content_protection@suspend-resume@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][24] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-3/igt@kms_content_protection@suspend-resume@pipe-a-dp-2.html

  * igt@kms_content_protection@type1:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#7642])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_content_protection@type1.html

  * igt@kms_content_protection@uevent-hdcp14:
    - shard-bmg:          NOTRUN -> [FAIL][26] ([Intel XE#6707] / [Intel XE#7439]) +1 other test fail
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@kms_content_protection@uevent-hdcp14.html

  * igt@kms_cursor_crc@cursor-onscreen-max-size:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#2320]) +7 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@kms_cursor_crc@cursor-onscreen-max-size.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2321] / [Intel XE#7355])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-3/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#2321] / [Intel XE#7355]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#309] / [Intel XE#7343]) +2 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          NOTRUN -> [FAIL][31] ([Intel XE#7571])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#323] / [Intel XE#6035])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#2286] / [Intel XE#6035])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#2244]) +1 other test skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-3/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_fbcon_fbt@fbc:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#4156] / [Intel XE#7425])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@kms_fbcon_fbt@fbc.html

  * igt@kms_fbcon_fbt@psr:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#6126] / [Intel XE#776])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-4/igt@kms_fbcon_fbt@psr.html

  * igt@kms_feature_discovery@chamelium:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#2372] / [Intel XE#7359])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-4/igt@kms_feature_discovery@chamelium.html

  * igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#1421]) +1 other test skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          NOTRUN -> [FAIL][39] ([Intel XE#301]) +1 other test fail
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@plain-flip-fb-recreate:
    - shard-bmg:          [PASS][40] -> [FAIL][41] ([Intel XE#5408] / [Intel XE#6266])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-6/igt@kms_flip@plain-flip-fb-recreate.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-4/igt@kms_flip@plain-flip-fb-recreate.html

  * igt@kms_flip@plain-flip-fb-recreate@a-hdmi-a3:
    - shard-bmg:          [PASS][42] -> [FAIL][43] ([Intel XE#6266])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-6/igt@kms_flip@plain-flip-fb-recreate@a-hdmi-a3.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-4/igt@kms_flip@plain-flip-fb-recreate@a-hdmi-a3.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#7178] / [Intel XE#7349])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#7178] / [Intel XE#7351]) +6 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yuv-linear-to-32bpp-yuv-linear-reflect-x:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#7179])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_flip_scaled_crc@flip-32bpp-yuv-linear-to-32bpp-yuv-linear-reflect-x.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][47] ([Intel XE#7178] / [Intel XE#7351])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#4141]) +18 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#7061] / [Intel XE#7356]) +4 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#6312] / [Intel XE#651]) +2 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#2311]) +24 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#2352] / [Intel XE#7399])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#2313]) +27 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#656]) +9 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#7086] / [Intel XE#7390])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#6911] / [Intel XE#7466])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping:
    - shard-lnl:          NOTRUN -> [SKIP][57] ([Intel XE#7283])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier-source-clamping:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#7283]) +4 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-3/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier-source-clamping.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-c:
    - shard-lnl:          NOTRUN -> [SKIP][59] ([Intel XE#2763] / [Intel XE#6886]) +3 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-c.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-bmg:          NOTRUN -> [SKIP][60] ([Intel XE#7794])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-bmg:          NOTRUN -> [SKIP][61] ([Intel XE#3309] / [Intel XE#7368])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-4/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383] / [Intel XE#836]) +1 other test skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-3/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@package-g7:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#6814] / [Intel XE#7428])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@kms_pm_rpm@package-g7.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-lnl:          NOTRUN -> [SKIP][64] ([Intel XE#2893] / [Intel XE#7304])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf:
    - shard-lnl:          NOTRUN -> [SKIP][65] ([Intel XE#2893] / [Intel XE#4608] / [Intel XE#7304])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][66] ([Intel XE#4608])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][67] ([Intel XE#4608] / [Intel XE#7304])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-b-edp-1.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][68] ([Intel XE#1489]) +7 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr@fbc-psr2-cursor-plane-move:
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#1406] / [Intel XE#7345])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_psr@fbc-psr2-cursor-plane-move.html

  * igt@kms_psr@fbc-psr2-cursor-plane-move@edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][70] ([Intel XE#1406] / [Intel XE#4609])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_psr@fbc-psr2-cursor-plane-move@edp-1.html

  * igt@kms_psr@pr-primary-blt:
    - shard-lnl:          NOTRUN -> [SKIP][71] ([Intel XE#1406])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_psr@pr-primary-blt.html

  * igt@kms_psr@pr-primary-render:
    - shard-bmg:          NOTRUN -> [SKIP][72] ([Intel XE#2234] / [Intel XE#2850]) +10 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-4/igt@kms_psr@pr-primary-render.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-bmg:          NOTRUN -> [SKIP][73] ([Intel XE#7795]) +1 other test skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-4/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
    - shard-lnl:          NOTRUN -> [SKIP][74] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#2330] / [Intel XE#5813])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
    - shard-bmg:          NOTRUN -> [SKIP][76] ([Intel XE#3904] / [Intel XE#7342])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-3/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html

  * igt@kms_setmode@invalid-clone-exclusive-crtc:
    - shard-bmg:          NOTRUN -> [SKIP][77] ([Intel XE#1435])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@kms_setmode@invalid-clone-exclusive-crtc.html

  * igt@kms_sharpness_filter@invalid-filter-with-plane:
    - shard-bmg:          NOTRUN -> [SKIP][78] ([Intel XE#6503]) +2 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-4/igt@kms_sharpness_filter@invalid-filter-with-plane.html

  * igt@kms_vrr@flipline:
    - shard-bmg:          NOTRUN -> [SKIP][79] ([Intel XE#1499]) +2 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-4/igt@kms_vrr@flipline.html

  * igt@xe_eudebug_online@set-breakpoint-faultable:
    - shard-bmg:          NOTRUN -> [SKIP][80] ([Intel XE#7636]) +14 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-4/igt@xe_eudebug_online@set-breakpoint-faultable.html

  * igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-vram:
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#7636]) +2 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-vram.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][82] ([Intel XE#6321])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_evict@evict-mixed-threads-small-multi-vm:
    - shard-lnl:          NOTRUN -> [SKIP][83] ([Intel XE#6540] / [Intel XE#688]) +1 other test skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@xe_evict@evict-mixed-threads-small-multi-vm.html

  * igt@xe_evict@evict-threads-small-multi-queue:
    - shard-bmg:          NOTRUN -> [SKIP][84] ([Intel XE#7140]) +2 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-4/igt@xe_evict@evict-threads-small-multi-queue.html

  * igt@xe_exec_balancer@twice-cm-virtual-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][85] ([Intel XE#7482]) +4 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@xe_exec_balancer@twice-cm-virtual-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap:
    - shard-lnl:          NOTRUN -> [SKIP][86] ([Intel XE#1392]) +1 other test skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][87] ([Intel XE#2322] / [Intel XE#7372]) +7 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][88] ([Intel XE#7136]) +15 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-3/igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr.html

  * igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][89] ([Intel XE#7136]) +3 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-race.html

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-fault-basic-smem:
    - shard-lnl:          NOTRUN -> [SKIP][90] ([Intel XE#6874]) +7 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@xe_exec_multi_queue@max-queues-preempt-mode-fault-basic-smem.html

  * igt@xe_exec_multi_queue@one-queue-priority-smem:
    - shard-bmg:          NOTRUN -> [SKIP][91] ([Intel XE#6874]) +29 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@xe_exec_multi_queue@one-queue-priority-smem.html

  * igt@xe_exec_system_allocator@many-stride-new-prefetch:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][92] ([Intel XE#7098])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@xe_exec_system_allocator@many-stride-new-prefetch.html

  * igt@xe_exec_threads@threads-multi-queue-cm-fd-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][93] ([Intel XE#7138]) +7 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-3/igt@xe_exec_threads@threads-multi-queue-cm-fd-userptr-rebind.html

  * igt@xe_exec_threads@threads-multi-queue-rebind-err:
    - shard-lnl:          NOTRUN -> [SKIP][94] ([Intel XE#7138]) +1 other test skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@xe_exec_threads@threads-multi-queue-rebind-err.html

  * igt@xe_multigpu_svm@mgpu-concurrent-access-basic:
    - shard-bmg:          NOTRUN -> [SKIP][95] ([Intel XE#6964]) +3 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-3/igt@xe_multigpu_svm@mgpu-concurrent-access-basic.html

  * igt@xe_page_reclaim@binds-null-vma:
    - shard-bmg:          NOTRUN -> [SKIP][96] ([Intel XE#7793]) +1 other test skip
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@xe_page_reclaim@binds-null-vma.html

  * igt@xe_pat@pat-index-xelp:
    - shard-bmg:          NOTRUN -> [SKIP][97] ([Intel XE#2245] / [Intel XE#7590])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@xe_pat@pat-index-xelp.html

  * igt@xe_peer2peer@write:
    - shard-bmg:          NOTRUN -> [SKIP][98] ([Intel XE#2427] / [Intel XE#6953] / [Intel XE#7326] / [Intel XE#7353])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@xe_peer2peer@write.html

  * igt@xe_pm@s2idle-d3cold-basic-exec:
    - shard-bmg:          NOTRUN -> [SKIP][99] ([Intel XE#2284] / [Intel XE#7370]) +3 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@xe_pm@s2idle-d3cold-basic-exec.html

  * igt@xe_pm_residency@cpg-basic:
    - shard-lnl:          NOTRUN -> [SKIP][100] ([Intel XE#584] / [Intel XE#7369]) +1 other test skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@xe_pm_residency@cpg-basic.html

  * igt@xe_pxp@pxp-termination-key-update-post-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][101] ([Intel XE#4733] / [Intel XE#7417]) +2 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@xe_pxp@pxp-termination-key-update-post-suspend.html

  * igt@xe_query@multigpu-query-mem-usage:
    - shard-bmg:          NOTRUN -> [SKIP][102] ([Intel XE#944]) +1 other test skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@xe_query@multigpu-query-mem-usage.html

  * igt@xe_sriov_auto_provisioning@fair-allocation:
    - shard-lnl:          NOTRUN -> [SKIP][103] ([Intel XE#4130] / [Intel XE#7366])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-2/igt@xe_sriov_auto_provisioning@fair-allocation.html

  
#### Possible fixes ####

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [FAIL][104] ([Intel XE#301]) -> [PASS][105] +1 other test pass
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  
#### Warnings ####

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][106] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][107] ([Intel XE#3544])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-1/igt@kms_hdr@brightness-with-hdr.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-9/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][108] ([Intel XE#2426] / [Intel XE#5848]) -> [FAIL][109] ([Intel XE#1729] / [Intel XE#7424])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern.html

  * igt@xe_module_load@load:
    - shard-bmg:          ([PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [ABORT][122], [PASS][123], [ABORT][124], [ABORT][125], [PASS][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132], [PASS][133]) -> ([PASS][134], [PASS][135], [PASS][136], [PASS][137], [PASS][138], [PASS][139], [PASS][140], [PASS][141], [PASS][142], [PASS][143], [PASS][144], [PASS][145], [PASS][146], [PASS][147], [PASS][148], [SKIP][149], [PASS][150], [PASS][151], [PASS][152], [PASS][153], [PASS][154], [PASS][155], [PASS][156]) ([Intel XE#2457] / [Intel XE#7405])
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-3/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-8/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-7/igt@xe_module_load@load.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-7/igt@xe_module_load@load.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-8/igt@xe_module_load@load.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-7/igt@xe_module_load@load.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-4/igt@xe_module_load@load.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-9/igt@xe_module_load@load.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-9/igt@xe_module_load@load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-9/igt@xe_module_load@load.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-3/igt@xe_module_load@load.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-2/igt@xe_module_load@load.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-5/igt@xe_module_load@load.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-4/igt@xe_module_load@load.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-5/igt@xe_module_load@load.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-5/igt@xe_module_load@load.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-10/igt@xe_module_load@load.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-10/igt@xe_module_load@load.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-1/igt@xe_module_load@load.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-1/igt@xe_module_load@load.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-3/igt@xe_module_load@load.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-2/igt@xe_module_load@load.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-6/igt@xe_module_load@load.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5/shard-bmg-6/igt@xe_module_load@load.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-7/igt@xe_module_load@load.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-7/igt@xe_module_load@load.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-4/igt@xe_module_load@load.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-3/igt@xe_module_load@load.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-9/igt@xe_module_load@load.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-7/igt@xe_module_load@load.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-7/igt@xe_module_load@load.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-4/igt@xe_module_load@load.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-4/igt@xe_module_load@load.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-9/igt@xe_module_load@load.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-10/igt@xe_module_load@load.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-9/igt@xe_module_load@load.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@xe_module_load@load.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@xe_module_load@load.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-3/igt@xe_module_load@load.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-6/igt@xe_module_load@load.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-2/igt@xe_module_load@load.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-8/igt@xe_module_load@load.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-8/igt@xe_module_load@load.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-1/igt@xe_module_load@load.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-10/igt@xe_module_load@load.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-2/igt@xe_module_load@load.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/shard-bmg-2/igt@xe_module_load@load.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2245]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2245
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328
  [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
  [Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
  [Intel XE#2372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2372
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2427]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2427
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3433]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3433
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4156]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4156
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#5408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5408
  [Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#6035]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6035
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#6126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6126
  [Intel XE#6266]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6266
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707
  [Intel XE#6814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6814
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
  [Intel XE#6953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6953
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6969]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6969
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7006]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7006
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7086]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7086
  [Intel XE#7098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7098
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7140]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7140
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7326]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7326
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7345
  [Intel XE#7349]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7349
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7353]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7353
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7359]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7359
  [Intel XE#7361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7361
  [Intel XE#7366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7366
  [Intel XE#7367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7367
  [Intel XE#7368]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7368
  [Intel XE#7369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7369
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
  [Intel XE#7389]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7389
  [Intel XE#7390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7390
  [Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
  [Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7425]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7425
  [Intel XE#7428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7428
  [Intel XE#7439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7439
  [Intel XE#7466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7466
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7571
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#7676]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7676
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7794
  [Intel XE#7795]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7795
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5 -> xe-pw-165710v1

  IGT_8879: 02b0e01dd9a5a3ab1efe976bb8c4f13cfcdbab1a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4949-1db870ffb55b6414a78d7609ba7e08adf880dfc5: 1db870ffb55b6414a78d7609ba7e08adf880dfc5
  xe-pw-165710v1: 165710v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165710v1/index.html

[-- Attachment #2: Type: text/html, Size: 53019 bytes --]

Re: [PATCH 10/15] drm/i915/irq: move VLV/CHV LPE irq handler call after irq acks

[Jani Nikula]

On Wed, 29 Apr 2026, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Apr 29, 2026 at 01:24:50PM +0300, Jani Nikula wrote:
>> The location of the intel_lpe_audio_irq_handler() call seems too
>> early. Group the handler calls together slightly later.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_irq.c | 18 +++++++++---------
>>  1 file changed, 9 insertions(+), 9 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index ef9eadf38a53..1c87f56d668d 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -282,10 +282,6 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
>>  		 * signalled in IIR */
>>  		i9xx_pipestat_irq_ack(display, iir, pipe_stats);
>>  
>> -		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
>> -			   I915_LPE_PIPE_B_INTERRUPT))
>> -			intel_lpe_audio_irq_handler(display);
>
> This thing acks the irq too, so I believe it needs to stay here.

That was lost on me with the rabbit hole the lpe irq handler is.

I think I can put this in the intel_display_irq_ack() part, although the
name becomes misleading as it also handles some parts. Oh well.

BR,
Jani.


>
>> -
>>  		/*
>>  		 * VLV_IIR is single buffered, and reflects the level
>>  		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
>> @@ -301,6 +297,10 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
>>  		if (pm_iir)
>>  			gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir);
>>  
>> +		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
>> +			   I915_LPE_PIPE_B_INTERRUPT))
>> +			intel_lpe_audio_irq_handler(display);
>> +
>>  		if (hotplug_status)
>>  			i9xx_hpd_irq_handler(display, hotplug_status);
>>  
>> @@ -372,11 +372,6 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
>>  		 * signalled in IIR */
>>  		i9xx_pipestat_irq_ack(display, iir, pipe_stats);
>>  
>> -		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
>> -			   I915_LPE_PIPE_B_INTERRUPT |
>> -			   I915_LPE_PIPE_C_INTERRUPT))
>> -			intel_lpe_audio_irq_handler(display);
>> -
>>  		/*
>>  		 * VLV_IIR is single buffered, and reflects the level
>>  		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
>> @@ -387,6 +382,11 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
>>  		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
>>  		intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
>>  
>> +		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
>> +			   I915_LPE_PIPE_B_INTERRUPT |
>> +			   I915_LPE_PIPE_C_INTERRUPT))
>> +			intel_lpe_audio_irq_handler(display);
>> +
>>  		if (hotplug_status)
>>  			i9xx_hpd_irq_handler(display, hotplug_status);
>>  
>> -- 
>> 2.47.3

-- 
Jani Nikula, Intel

Re: [PATCH 15/15] drm/i915/irq: add intel_display_irq_handler() to irq funcs

[Jani Nikula]

On Wed, 29 Apr 2026, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Apr 29, 2026 at 01:24:55PM +0300, Jani Nikula wrote:
>> @@ -2088,6 +2123,28 @@ static void vlv_display_irq_ack(struct intel_display *display,
>>  	i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
>>  }
>>  
>> +static bool vlv_display_irq_handler(struct intel_display *display,
>> +				    const struct intel_display_irq_state *state)
>> +{
>> +	u32 lpe_mask = I915_LPE_PIPE_A_INTERRUPT | I915_LPE_PIPE_B_INTERRUPT;
>> +
>> +	if (display->platform.cherryview)
>> +		lpe_mask |= I915_LPE_PIPE_C_INTERRUPT;
>
> I would prefer a function rather than the extra variable. The other
> option is to just use the CHV mask always. There is nothing on the
> extra bit on VLV so we never unmask it.

Hmm. reset and postinstall also have slight variations for VLV vs. CHV,
but only very slight. I think they're overall close enough that
splitting out a funcs struct and separate funcs for CHV is more
distracting and duplication than helpful.

Or would something like this be satisfactory? Just a couple of small
wrapper functions around intel_lpe_audio_irq_handler() here that the
compiler would just inline:

	if (display->platform.cherryview)
		chv_lpe_audio_irq_handler(display, state->iir);		
	else
		vlv_lpe_audio_irq_handler(display, state->iir);		

Of course this would need to move to the ack part per your other review
comment.


>> @@ -51,14 +51,12 @@ void bdw_disable_vblank(struct drm_crtc *crtc);
>>  
>>  void ilk_display_irq_master_disable(struct intel_display *display, u32 *de_ier, u32 *sde_ier);
>>  void ilk_display_irq_master_enable(struct intel_display *display, u32 de_ier, u32 sde_ier);
>> -bool ilk_display_irq_handler(struct intel_display *display);
>> -void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl);
>> -void gen11_display_irq_handler(struct intel_display *display);
>>  
>>  u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
>>  void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
>>  
>>  struct intel_display_irq_state {
>> +	u32 master_ctl;
>
> Ideally I'd like a separate structs for different platforms,
> but until I resurrect my old ack vs. handle split for all
> platforms I guess we don't need anything else here for
> ilk+. So good enough for now I suppose.

You mean per-platform substructs/unions within struct
intel_display_irq_state? I can do that.

BR,
Jani.



-- 
Jani Nikula, Intel

Re: [PATCH 15/15] drm/i915/irq: add intel_display_irq_handler() to irq funcs

[Ville Syrjälä]

On Thu, Apr 30, 2026 at 10:59:11AM +0300, Jani Nikula wrote:
> On Wed, 29 Apr 2026, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Wed, Apr 29, 2026 at 01:24:55PM +0300, Jani Nikula wrote:
> >> @@ -2088,6 +2123,28 @@ static void vlv_display_irq_ack(struct intel_display *display,
> >>  	i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
> >>  }
> >>  
> >> +static bool vlv_display_irq_handler(struct intel_display *display,
> >> +				    const struct intel_display_irq_state *state)
> >> +{
> >> +	u32 lpe_mask = I915_LPE_PIPE_A_INTERRUPT | I915_LPE_PIPE_B_INTERRUPT;
> >> +
> >> +	if (display->platform.cherryview)
> >> +		lpe_mask |= I915_LPE_PIPE_C_INTERRUPT;
> >
> > I would prefer a function rather than the extra variable. The other
> > option is to just use the CHV mask always. There is nothing on the
> > extra bit on VLV so we never unmask it.
> 
> Hmm. reset and postinstall also have slight variations for VLV vs. CHV,
> but only very slight. I think they're overall close enough that
> splitting out a funcs struct and separate funcs for CHV is more
> distracting and duplication than helpful.

I think with DPINVGTT we could just switch to using full 16bit masks
and get rid of the vlv/chv difference. I should check if the unused
bits are all tied to 0...

> 
> Or would something like this be satisfactory? Just a couple of small
> wrapper functions around intel_lpe_audio_irq_handler() here that the
> compiler would just inline:
> 
> 	if (display->platform.cherryview)
> 		chv_lpe_audio_irq_handler(display, state->iir);		
> 	else
> 		vlv_lpe_audio_irq_handler(display, state->iir);		
> 
> Of course this would need to move to the ack part per your other review
> comment.

I was just thinking of having something like 
vlv_lpe_irq_mask()
{
	if (chv)
		return ...;
	else
		return ...;
}

> 
> 
> >> @@ -51,14 +51,12 @@ void bdw_disable_vblank(struct drm_crtc *crtc);
> >>  
> >>  void ilk_display_irq_master_disable(struct intel_display *display, u32 *de_ier, u32 *sde_ier);
> >>  void ilk_display_irq_master_enable(struct intel_display *display, u32 de_ier, u32 sde_ier);
> >> -bool ilk_display_irq_handler(struct intel_display *display);
> >> -void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl);
> >> -void gen11_display_irq_handler(struct intel_display *display);
> >>  
> >>  u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
> >>  void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
> >>  
> >>  struct intel_display_irq_state {
> >> +	u32 master_ctl;
> >
> > Ideally I'd like a separate structs for different platforms,
> > but until I resurrect my old ack vs. handle split for all
> > platforms I guess we don't need anything else here for
> > ilk+. So good enough for now I suppose.
> 
> You mean per-platform substructs/unions within struct
> intel_display_irq_state? I can do that.

Yeah something like that. Not super important right since
we just have the master_ctl for non-gmch platforms.

-- 
Ville Syrjälä
Intel