* [PATCH 0/5] drm/i915/dp: Sanitize link capability change handling
@ 2026-05-18 11:24 Imre Deak
2026-05-18 11:24 ` [PATCH 1/5] drm/i915/dp: Add helpers to reset link params Imre Deak
` (7 more replies)
0 siblings, 8 replies; 21+ messages in thread
From: Imre Deak @ 2026-05-18 11:24 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Ville Syrjälä, Jani Nikula
Sanitize link capability change handling via long HPD pulse /
RX_CAP_CHANGED HPD IRQ events and the connector detect paths by making
all of them consistently reset the link training/recovery and MST link
probe state after a link capability change.
This also prepares for the refactoring of the DP link capability logic
in patch [1], simplifying the handling of link capability changes in
that patchset based on the above.
[1] https://lore.kernel.org/all/20260428125233.1664668-1-imre.deak@intel.com
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Imre Deak (5):
drm/i915/dp: Add helpers to reset link params
drm/i915/dp: Reset link params after a DPRX capability change
drm/i915/dp: Add helper to set common link params
drm/i915/dp: Cache max common lane count
drm/i915/dp: Detect changes in common link parameters
drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 103 +++++++++++++++---
drivers/gpu/drm/i915/display/intel_dp.h | 3 +-
.../drm/i915/display/intel_dp_link_training.c | 4 +-
6 files changed, 94 insertions(+), 21 deletions(-)
--
2.49.1
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 1/5] drm/i915/dp: Add helpers to reset link params
2026-05-18 11:24 [PATCH 0/5] drm/i915/dp: Sanitize link capability change handling Imre Deak
@ 2026-05-18 11:24 ` Imre Deak
2026-05-21 21:36 ` Ville Syrjälä
2026-05-18 11:24 ` [PATCH 2/5] drm/i915/dp: Reset link params after a DPRX capability change Imre Deak
` (6 subsequent siblings)
7 siblings, 1 reply; 21+ messages in thread
From: Imre Deak @ 2026-05-18 11:24 UTC (permalink / raw)
To: intel-gfx, intel-xe
Add helpers to defer and handle link params resets instead of
open-coding the same. Rename intel_dp_reset_link_params() to
intel_dp_reset_link_params_force() to align its name with the new
deferred reset helpers.
When deferring a reset, return whether a new reset was queued, used by a
follow-up change.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 41 +++++++++++++++----
drivers/gpu/drm/i915/display/intel_dp.h | 3 +-
.../drm/i915/display/intel_dp_link_training.c | 4 +-
5 files changed, 38 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 5ff1cdf4581a5..c20a97e21419b 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -1265,7 +1265,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
- intel_dp->reset_link_params = true;
+ intel_dp_reset_link_params_defer(intel_dp);
intel_dp_invalidate_source_oui(intel_dp);
if (display->platform.valleyview || display->platform.cherryview)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 86520848892e0..77819aaeccb76 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4664,7 +4664,7 @@ static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
- intel_dp->reset_link_params = true;
+ intel_dp_reset_link_params_defer(intel_dp);
intel_dp_invalidate_source_oui(intel_dp);
intel_pps_encoder_reset(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 1920d2f026665..13163dd085e91 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3710,7 +3710,11 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp,
intel_dp->lane_count = lane_count;
}
-void intel_dp_reset_link_params(struct intel_dp *intel_dp)
+/*
+ * Reset link params now, preserving any deferred connector
+ * detect-time reset request.
+ */
+void intel_dp_reset_link_params_force(struct intel_dp *intel_dp)
{
intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);
intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
@@ -3720,6 +3724,28 @@ void intel_dp_reset_link_params(struct intel_dp *intel_dp)
intel_dp->link.seq_train_failures = 0;
}
+/*
+ * Reset link params during the next connector detect.
+ * Return %true if a new reset was queued.
+ */
+bool intel_dp_reset_link_params_defer(struct intel_dp *intel_dp)
+{
+ bool reset_was_pending = intel_dp->reset_link_params;
+
+ intel_dp->reset_link_params = true;
+
+ return !reset_was_pending;
+}
+
+static void intel_dp_handle_deferred_link_params_reset(struct intel_dp *intel_dp)
+{
+ if (!intel_dp->reset_link_params)
+ return;
+
+ intel_dp->reset_link_params = false;
+ intel_dp_reset_link_params_force(intel_dp);
+}
+
/* Enable backlight PWM and backlight PP control. */
void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
@@ -4066,7 +4092,7 @@ void intel_dp_sync_state(struct intel_encoder *encoder,
intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);
if (crtc_state) {
- intel_dp_reset_link_params(intel_dp);
+ intel_dp_reset_link_params_force(intel_dp);
intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count);
intel_dp->link.active = true;
}
@@ -6487,10 +6513,7 @@ intel_dp_detect(struct drm_connector *_connector,
intel_dp_detect_sdp_caps(intel_dp);
- if (intel_dp->reset_link_params) {
- intel_dp_reset_link_params(intel_dp);
- intel_dp->reset_link_params = false;
- }
+ intel_dp_handle_deferred_link_params_reset(intel_dp);
intel_dp_mst_configure(intel_dp);
@@ -6944,7 +6967,7 @@ intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
intel_dp_read_dprx_caps(intel_dp, dpcd);
- intel_dp->reset_link_params = true;
+ intel_dp_reset_link_params_defer(intel_dp);
intel_dp_invalidate_source_oui(intel_dp);
return IRQ_NONE;
@@ -7252,7 +7275,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
encoder->base.name))
return false;
- intel_dp->reset_link_params = true;
+ intel_dp_reset_link_params_defer(intel_dp);
/* Preserve the current hw state. */
intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
@@ -7317,7 +7340,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
intel_dp_set_source_rates(intel_dp);
intel_dp_set_common_rates(intel_dp);
- intel_dp_reset_link_params(intel_dp);
+ intel_dp_reset_link_params_force(intel_dp);
/* init MST on ports that can support it */
intel_dp_mst_encoder_init(dig_port, connector->base.base.id);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index f41480d247142..7c24d3dbb6983 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -114,7 +114,8 @@ int intel_dp_rate_index(const int *rates, int len, int rate);
int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count);
void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count);
void intel_dp_update_sink_caps(struct intel_dp *intel_dp);
-void intel_dp_reset_link_params(struct intel_dp *intel_dp);
+void intel_dp_reset_link_params_force(struct intel_dp *intel_dp);
+bool intel_dp_reset_link_params_defer(struct intel_dp *intel_dp);
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
u8 *link_bw, u8 *rate_select);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index a26094223f780..b7075060e7bd3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1935,7 +1935,7 @@ static ssize_t i915_dp_force_link_rate_write(struct file *file,
if (err)
return err;
- intel_dp_reset_link_params(intel_dp);
+ intel_dp_reset_link_params_force(intel_dp);
intel_dp->link.force_rate = rate;
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
@@ -2037,7 +2037,7 @@ static ssize_t i915_dp_force_lane_count_write(struct file *file,
if (err)
return err;
- intel_dp_reset_link_params(intel_dp);
+ intel_dp_reset_link_params_force(intel_dp);
intel_dp->link.force_lane_count = lane_count;
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
--
2.49.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 2/5] drm/i915/dp: Reset link params after a DPRX capability change
2026-05-18 11:24 [PATCH 0/5] drm/i915/dp: Sanitize link capability change handling Imre Deak
2026-05-18 11:24 ` [PATCH 1/5] drm/i915/dp: Add helpers to reset link params Imre Deak
@ 2026-05-18 11:24 ` Imre Deak
2026-05-18 11:24 ` [PATCH 3/5] drm/i915/dp: Add helper to set common link params Imre Deak
` (5 subsequent siblings)
7 siblings, 0 replies; 21+ messages in thread
From: Imre Deak @ 2026-05-18 11:24 UTC (permalink / raw)
To: intel-gfx, intel-xe
There is no reason to distinguish between DPRX capability changes
signaled via a long HPD and via an RX_CAP_CHANGED HPD IRQ.
Both cases result in reading out the DPRX capabilities and updating the
corresponding sink and common capabilities cached in intel_dp, however
only the long HPD resets the link training/recovery state and MST link
probe parameters correspondingly. The link training/recovery state may
contain reduced maximum link rate/lane count values left over from a
previous link training failure.
Based on the above after an RX_CAP_CHANGED increased the link rate, lane
count parameters the maximum link rate/lane count in the link
training/recovery state may remain below these, leaving the newly added
valid configurations unavailable for subsequent modesets in an
inconsistent way.
Handle RX_CAP_CHANGED IRQs the same way as long HPDs and reset the link
recovery state and MST link probe parameters in that case as well.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 13163dd085e91..9c530ef12b7cc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6026,8 +6026,10 @@ static bool intel_dp_handle_link_service_irq(struct intel_dp *intel_dp, u8 irq_m
drm_WARN_ON(display->drm, irq_mask & ~(INTEL_DP_LINK_SERVICE_IRQ_MASK_SST |
INTEL_DP_LINK_SERVICE_IRQ_MASK_MST));
- if (irq_mask & RX_CAP_CHANGED)
+ if (irq_mask & RX_CAP_CHANGED) {
+ intel_dp_reset_link_params_defer(intel_dp);
reprobe_needed = true;
+ }
if (irq_mask & LINK_STATUS_CHANGED)
intel_dp_check_link_state(intel_dp);
--
2.49.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 3/5] drm/i915/dp: Add helper to set common link params
2026-05-18 11:24 [PATCH 0/5] drm/i915/dp: Sanitize link capability change handling Imre Deak
2026-05-18 11:24 ` [PATCH 1/5] drm/i915/dp: Add helpers to reset link params Imre Deak
2026-05-18 11:24 ` [PATCH 2/5] drm/i915/dp: Reset link params after a DPRX capability change Imre Deak
@ 2026-05-18 11:24 ` Imre Deak
2026-05-22 7:20 ` Hogander, Jouni
2026-05-18 11:24 ` [PATCH 4/5] drm/i915/dp: Cache max common lane count Imre Deak
` (4 subsequent siblings)
7 siblings, 1 reply; 21+ messages in thread
From: Imre Deak @ 2026-05-18 11:24 UTC (permalink / raw)
To: intel-gfx, intel-xe
Add intel_dp_set_common_link_params() to prepare for updating the
maximum common lane count together with the common rates.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9c530ef12b7cc..06bf1fb23faff 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -805,7 +805,11 @@ static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
intel_dp->common_rates[0] = 162000;
intel_dp->num_common_rates = 1;
}
+}
+static void intel_dp_set_common_link_params(struct intel_dp *intel_dp)
+{
+ intel_dp_set_common_rates(intel_dp);
intel_dp_link_config_init(intel_dp);
}
@@ -4903,7 +4907,7 @@ void intel_dp_update_sink_caps(struct intel_dp *intel_dp)
{
intel_dp_set_sink_rates(intel_dp);
intel_dp_set_max_sink_lane_count(intel_dp);
- intel_dp_set_common_rates(intel_dp);
+ intel_dp_set_common_link_params(intel_dp);
}
static bool
@@ -7341,7 +7345,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
}
intel_dp_set_source_rates(intel_dp);
- intel_dp_set_common_rates(intel_dp);
+ intel_dp_set_common_link_params(intel_dp);
intel_dp_reset_link_params_force(intel_dp);
/* init MST on ports that can support it */
--
2.49.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 4/5] drm/i915/dp: Cache max common lane count
2026-05-18 11:24 [PATCH 0/5] drm/i915/dp: Sanitize link capability change handling Imre Deak
` (2 preceding siblings ...)
2026-05-18 11:24 ` [PATCH 3/5] drm/i915/dp: Add helper to set common link params Imre Deak
@ 2026-05-18 11:24 ` Imre Deak
2026-05-22 7:21 ` Hogander, Jouni
2026-05-18 11:24 ` [PATCH 5/5] drm/i915/dp: Detect changes in common link parameters Imre Deak
` (3 subsequent siblings)
7 siblings, 1 reply; 21+ messages in thread
From: Imre Deak @ 2026-05-18 11:24 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cache the maximum common lane count together with the common link
rates.
This is safe because the cached value is updated:
- during driver probe, before the connector is registered and can be
used for mode validation or modesetting
- during resume, before output HW state readout can query it
- during connector detection, right after updating the sink/link
capabilities
Caching the value allows detecting max common lane count changes in
a follow-up change and keeps the tracking of max common lane count
aligned with that of common rates.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++++++--
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f44be5c689aef..c3811242310c8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1820,6 +1820,7 @@ struct intel_dp {
/* intersection of source and sink rates */
int num_common_rates;
int common_rates[DP_MAX_SUPPORTED_RATES];
+ int max_common_lane_count;
struct {
/* TODO: move the rest of link specific fields to here */
bool active;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 06bf1fb23faff..6c4dadfc35806 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -363,7 +363,7 @@ int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
}
/* Theoretical max between source and sink */
-int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
+static void intel_dp_set_max_common_lane_count(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
int source_max = intel_dp_max_source_lane_count(dig_port);
@@ -374,7 +374,12 @@ int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
if (lttpr_max)
sink_max = min(sink_max, lttpr_max);
- return min3(source_max, sink_max, lane_max);
+ intel_dp->max_common_lane_count = min3(source_max, sink_max, lane_max);
+}
+
+int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
+{
+ return intel_dp->max_common_lane_count;
}
static int forced_lane_count(struct intel_dp *intel_dp)
@@ -810,6 +815,7 @@ static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
static void intel_dp_set_common_link_params(struct intel_dp *intel_dp)
{
intel_dp_set_common_rates(intel_dp);
+ intel_dp_set_max_common_lane_count(intel_dp);
intel_dp_link_config_init(intel_dp);
}
--
2.49.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 5/5] drm/i915/dp: Detect changes in common link parameters
2026-05-18 11:24 [PATCH 0/5] drm/i915/dp: Sanitize link capability change handling Imre Deak
` (3 preceding siblings ...)
2026-05-18 11:24 ` [PATCH 4/5] drm/i915/dp: Cache max common lane count Imre Deak
@ 2026-05-18 11:24 ` Imre Deak
2026-05-21 21:43 ` Ville Syrjälä
2026-05-18 12:01 ` ✓ CI.KUnit: success for drm/i915/dp: Sanitize link capability change handling Patchwork
` (2 subsequent siblings)
7 siblings, 1 reply; 21+ messages in thread
From: Imre Deak @ 2026-05-18 11:24 UTC (permalink / raw)
To: intel-gfx, intel-xe
Detect DPRX capability changes without a long HPD or RX_CAP_CHANGED
signal and queue a corresponding link params reset.
Besides detecting the above unexpected capability changes, this also
avoids races between queuing and handling a deferred link params reset.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 50 +++++++++++++++++++++----
1 file changed, 43 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6c4dadfc35806..dd968c2d9fa64 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -362,19 +362,25 @@ int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
return max_lanes;
}
-/* Theoretical max between source and sink */
-static void intel_dp_set_max_common_lane_count(struct intel_dp *intel_dp)
+/*
+ * Theoretical max between source and sink.
+ * Return %true if the max common lane count changed.
+ */
+static bool intel_dp_set_max_common_lane_count(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
int source_max = intel_dp_max_source_lane_count(dig_port);
int sink_max = intel_dp->max_sink_lane_count;
int lane_max = intel_tc_port_max_lane_count(dig_port);
int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
+ int old_max_common_lane_count = intel_dp->max_common_lane_count;
if (lttpr_max)
sink_max = min(sink_max, lttpr_max);
intel_dp->max_common_lane_count = min3(source_max, sink_max, lane_max);
+
+ return intel_dp->max_common_lane_count != old_max_common_lane_count;
}
int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
@@ -792,13 +798,20 @@ int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lan
return -1;
}
-static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
+/* Return %true if the common rates changed. */
+static bool intel_dp_set_common_rates(struct intel_dp *intel_dp)
{
struct intel_display *display = to_intel_display(intel_dp);
+ int num_old_common_rates = intel_dp->num_common_rates;
+ int old_common_rates[DP_MAX_SUPPORTED_RATES];
drm_WARN_ON(display->drm,
!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
+ static_assert(sizeof(old_common_rates) == sizeof(intel_dp->common_rates));
+ memcpy(old_common_rates, intel_dp->common_rates,
+ num_old_common_rates * sizeof(old_common_rates[0]));
+
intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
intel_dp->num_source_rates,
intel_dp->sink_rates,
@@ -810,13 +823,26 @@ static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
intel_dp->common_rates[0] = 162000;
intel_dp->num_common_rates = 1;
}
+
+ return num_old_common_rates != intel_dp->num_common_rates ||
+ memcmp(old_common_rates, intel_dp->common_rates,
+ num_old_common_rates * sizeof(old_common_rates[0]));
}
-static void intel_dp_set_common_link_params(struct intel_dp *intel_dp)
+/* Return %true if any common link param changed. */
+static bool intel_dp_set_common_link_params(struct intel_dp *intel_dp)
{
- intel_dp_set_common_rates(intel_dp);
- intel_dp_set_max_common_lane_count(intel_dp);
+ bool params_changed = false;
+
+ if (intel_dp_set_common_rates(intel_dp))
+ params_changed = true;
+
+ if (intel_dp_set_max_common_lane_count(intel_dp))
+ params_changed = true;
+
intel_dp_link_config_init(intel_dp);
+
+ return params_changed;
}
bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
@@ -4911,9 +4937,19 @@ intel_dp_has_sink_count(struct intel_dp *intel_dp)
void intel_dp_update_sink_caps(struct intel_dp *intel_dp)
{
+ struct intel_display *display = to_intel_display(intel_dp);
+
intel_dp_set_sink_rates(intel_dp);
intel_dp_set_max_sink_lane_count(intel_dp);
- intel_dp_set_common_link_params(intel_dp);
+ /*
+ * Handle unexpected sink cap changes, or a race between setting
+ * the deferred link params flag in the HPD IRQ handler and
+ * clearing the flag during connector detect.
+ */
+ if (intel_dp_set_common_link_params(intel_dp) &&
+ intel_dp_reset_link_params_defer(intel_dp))
+ drm_dbg_kms(display->drm,
+ "DPRX capabilities changed before long HPD or RX_CAP_CHANGED signal\n");
}
static bool
--
2.49.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* ✓ CI.KUnit: success for drm/i915/dp: Sanitize link capability change handling
2026-05-18 11:24 [PATCH 0/5] drm/i915/dp: Sanitize link capability change handling Imre Deak
` (4 preceding siblings ...)
2026-05-18 11:24 ` [PATCH 5/5] drm/i915/dp: Detect changes in common link parameters Imre Deak
@ 2026-05-18 12:01 ` Patchwork
2026-05-18 12:41 ` ✓ Xe.CI.BAT: " Patchwork
2026-05-18 16:04 ` ✗ Xe.CI.FULL: failure " Patchwork
7 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2026-05-18 12:01 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-xe
== Series Details ==
Series: drm/i915/dp: Sanitize link capability change handling
URL : https://patchwork.freedesktop.org/series/166769/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[12:00:13] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:00:18] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:00:49] Starting KUnit Kernel (1/1)...
[12:00:49] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:00:49] ================== guc_buf (11 subtests) ===================
[12:00:49] [PASSED] test_smallest
[12:00:49] [PASSED] test_largest
[12:00:49] [PASSED] test_granular
[12:00:49] [PASSED] test_unique
[12:00:49] [PASSED] test_overlap
[12:00:49] [PASSED] test_reusable
[12:00:49] [PASSED] test_too_big
[12:00:49] [PASSED] test_flush
[12:00:49] [PASSED] test_lookup
[12:00:49] [PASSED] test_data
[12:00:49] [PASSED] test_class
[12:00:49] ===================== [PASSED] guc_buf =====================
[12:00:49] =================== guc_dbm (7 subtests) ===================
[12:00:49] [PASSED] test_empty
[12:00:49] [PASSED] test_default
[12:00:49] ======================== test_size ========================
[12:00:49] [PASSED] 4
[12:00:49] [PASSED] 8
[12:00:49] [PASSED] 32
[12:00:49] [PASSED] 256
[12:00:49] ==================== [PASSED] test_size ====================
[12:00:49] ======================= test_reuse ========================
[12:00:49] [PASSED] 4
[12:00:49] [PASSED] 8
[12:00:49] [PASSED] 32
[12:00:49] [PASSED] 256
[12:00:49] =================== [PASSED] test_reuse ====================
[12:00:49] =================== test_range_overlap ====================
[12:00:49] [PASSED] 4
[12:00:49] [PASSED] 8
[12:00:49] [PASSED] 32
[12:00:49] [PASSED] 256
[12:00:49] =============== [PASSED] test_range_overlap ================
[12:00:49] =================== test_range_compact ====================
[12:00:49] [PASSED] 4
[12:00:49] [PASSED] 8
[12:00:49] [PASSED] 32
[12:00:49] [PASSED] 256
[12:00:49] =============== [PASSED] test_range_compact ================
[12:00:49] ==================== test_range_spare =====================
[12:00:49] [PASSED] 4
[12:00:49] [PASSED] 8
[12:00:49] [PASSED] 32
[12:00:49] [PASSED] 256
[12:00:49] ================ [PASSED] test_range_spare =================
[12:00:49] ===================== [PASSED] guc_dbm =====================
[12:00:49] =================== guc_idm (6 subtests) ===================
[12:00:49] [PASSED] bad_init
[12:00:49] [PASSED] no_init
[12:00:49] [PASSED] init_fini
[12:00:49] [PASSED] check_used
[12:00:49] [PASSED] check_quota
[12:00:49] [PASSED] check_all
[12:00:49] ===================== [PASSED] guc_idm =====================
[12:00:49] ================== no_relay (3 subtests) ===================
[12:00:49] [PASSED] xe_drops_guc2pf_if_not_ready
[12:00:49] [PASSED] xe_drops_guc2vf_if_not_ready
[12:00:49] [PASSED] xe_rejects_send_if_not_ready
[12:00:49] ==================== [PASSED] no_relay =====================
[12:00:49] ================== pf_relay (14 subtests) ==================
[12:00:49] [PASSED] pf_rejects_guc2pf_too_short
[12:00:49] [PASSED] pf_rejects_guc2pf_too_long
[12:00:49] [PASSED] pf_rejects_guc2pf_no_payload
[12:00:49] [PASSED] pf_fails_no_payload
[12:00:49] [PASSED] pf_fails_bad_origin
[12:00:49] [PASSED] pf_fails_bad_type
[12:00:49] [PASSED] pf_txn_reports_error
[12:00:49] [PASSED] pf_txn_sends_pf2guc
[12:00:49] [PASSED] pf_sends_pf2guc
[12:00:49] [SKIPPED] pf_loopback_nop
[12:00:49] [SKIPPED] pf_loopback_echo
[12:00:49] [SKIPPED] pf_loopback_fail
[12:00:49] [SKIPPED] pf_loopback_busy
[12:00:49] [SKIPPED] pf_loopback_retry
[12:00:49] ==================== [PASSED] pf_relay =====================
[12:00:49] ================== vf_relay (3 subtests) ===================
[12:00:49] [PASSED] vf_rejects_guc2vf_too_short
[12:00:49] [PASSED] vf_rejects_guc2vf_too_long
[12:00:49] [PASSED] vf_rejects_guc2vf_no_payload
[12:00:49] ==================== [PASSED] vf_relay =====================
[12:00:49] ================ pf_gt_config (9 subtests) =================
[12:00:49] [PASSED] fair_contexts_1vf
[12:00:49] [PASSED] fair_doorbells_1vf
[12:00:49] [PASSED] fair_ggtt_1vf
[12:00:49] ====================== fair_vram_1vf ======================
[12:00:49] [PASSED] 3.50 GiB
[12:00:49] [PASSED] 11.5 GiB
[12:00:49] [PASSED] 15.5 GiB
[12:00:49] [PASSED] 31.5 GiB
[12:00:49] [PASSED] 63.5 GiB
[12:00:49] [PASSED] 1.91 GiB
[12:00:49] ================== [PASSED] fair_vram_1vf ==================
[12:00:49] ================ fair_vram_1vf_admin_only =================
[12:00:49] [PASSED] 3.50 GiB
[12:00:49] [PASSED] 11.5 GiB
[12:00:49] [PASSED] 15.5 GiB
[12:00:49] [PASSED] 31.5 GiB
[12:00:49] [PASSED] 63.5 GiB
[12:00:49] [PASSED] 1.91 GiB
[12:00:49] ============ [PASSED] fair_vram_1vf_admin_only =============
[12:00:49] ====================== fair_contexts ======================
[12:00:49] [PASSED] 1 VF
[12:00:49] [PASSED] 2 VFs
[12:00:49] [PASSED] 3 VFs
[12:00:49] [PASSED] 4 VFs
[12:00:49] [PASSED] 5 VFs
[12:00:49] [PASSED] 6 VFs
[12:00:49] [PASSED] 7 VFs
[12:00:49] [PASSED] 8 VFs
[12:00:49] [PASSED] 9 VFs
[12:00:49] [PASSED] 10 VFs
[12:00:49] [PASSED] 11 VFs
[12:00:49] [PASSED] 12 VFs
[12:00:49] [PASSED] 13 VFs
[12:00:49] [PASSED] 14 VFs
[12:00:49] [PASSED] 15 VFs
[12:00:49] [PASSED] 16 VFs
[12:00:49] [PASSED] 17 VFs
[12:00:49] [PASSED] 18 VFs
[12:00:49] [PASSED] 19 VFs
[12:00:49] [PASSED] 20 VFs
[12:00:49] [PASSED] 21 VFs
[12:00:49] [PASSED] 22 VFs
[12:00:49] [PASSED] 23 VFs
[12:00:49] [PASSED] 24 VFs
[12:00:49] [PASSED] 25 VFs
[12:00:49] [PASSED] 26 VFs
[12:00:49] [PASSED] 27 VFs
[12:00:49] [PASSED] 28 VFs
[12:00:49] [PASSED] 29 VFs
[12:00:49] [PASSED] 30 VFs
[12:00:49] [PASSED] 31 VFs
[12:00:49] [PASSED] 32 VFs
[12:00:49] [PASSED] 33 VFs
[12:00:49] [PASSED] 34 VFs
[12:00:49] [PASSED] 35 VFs
[12:00:49] [PASSED] 36 VFs
[12:00:49] [PASSED] 37 VFs
[12:00:49] [PASSED] 38 VFs
[12:00:49] [PASSED] 39 VFs
[12:00:49] [PASSED] 40 VFs
[12:00:49] [PASSED] 41 VFs
[12:00:49] [PASSED] 42 VFs
[12:00:49] [PASSED] 43 VFs
[12:00:49] [PASSED] 44 VFs
[12:00:49] [PASSED] 45 VFs
[12:00:49] [PASSED] 46 VFs
[12:00:49] [PASSED] 47 VFs
[12:00:49] [PASSED] 48 VFs
[12:00:49] [PASSED] 49 VFs
[12:00:49] [PASSED] 50 VFs
[12:00:49] [PASSED] 51 VFs
[12:00:49] [PASSED] 52 VFs
[12:00:49] [PASSED] 53 VFs
[12:00:49] [PASSED] 54 VFs
[12:00:49] [PASSED] 55 VFs
[12:00:49] [PASSED] 56 VFs
[12:00:49] [PASSED] 57 VFs
[12:00:49] [PASSED] 58 VFs
[12:00:49] [PASSED] 59 VFs
[12:00:49] [PASSED] 60 VFs
[12:00:49] [PASSED] 61 VFs
[12:00:49] [PASSED] 62 VFs
[12:00:49] [PASSED] 63 VFs
[12:00:49] ================== [PASSED] fair_contexts ==================
[12:00:49] ===================== fair_doorbells ======================
[12:00:49] [PASSED] 1 VF
[12:00:49] [PASSED] 2 VFs
[12:00:49] [PASSED] 3 VFs
[12:00:49] [PASSED] 4 VFs
[12:00:49] [PASSED] 5 VFs
[12:00:49] [PASSED] 6 VFs
[12:00:49] [PASSED] 7 VFs
[12:00:49] [PASSED] 8 VFs
[12:00:49] [PASSED] 9 VFs
[12:00:49] [PASSED] 10 VFs
[12:00:49] [PASSED] 11 VFs
[12:00:49] [PASSED] 12 VFs
[12:00:49] [PASSED] 13 VFs
[12:00:49] [PASSED] 14 VFs
[12:00:49] [PASSED] 15 VFs
[12:00:49] [PASSED] 16 VFs
[12:00:49] [PASSED] 17 VFs
[12:00:49] [PASSED] 18 VFs
[12:00:49] [PASSED] 19 VFs
[12:00:49] [PASSED] 20 VFs
[12:00:49] [PASSED] 21 VFs
[12:00:49] [PASSED] 22 VFs
[12:00:49] [PASSED] 23 VFs
[12:00:49] [PASSED] 24 VFs
[12:00:49] [PASSED] 25 VFs
[12:00:49] [PASSED] 26 VFs
[12:00:49] [PASSED] 27 VFs
[12:00:49] [PASSED] 28 VFs
[12:00:49] [PASSED] 29 VFs
[12:00:49] [PASSED] 30 VFs
[12:00:49] [PASSED] 31 VFs
[12:00:49] [PASSED] 32 VFs
[12:00:49] [PASSED] 33 VFs
[12:00:49] [PASSED] 34 VFs
[12:00:49] [PASSED] 35 VFs
[12:00:49] [PASSED] 36 VFs
[12:00:49] [PASSED] 37 VFs
[12:00:49] [PASSED] 38 VFs
[12:00:49] [PASSED] 39 VFs
[12:00:49] [PASSED] 40 VFs
[12:00:49] [PASSED] 41 VFs
[12:00:49] [PASSED] 42 VFs
[12:00:49] [PASSED] 43 VFs
[12:00:49] [PASSED] 44 VFs
[12:00:49] [PASSED] 45 VFs
[12:00:49] [PASSED] 46 VFs
[12:00:49] [PASSED] 47 VFs
[12:00:49] [PASSED] 48 VFs
[12:00:49] [PASSED] 49 VFs
[12:00:49] [PASSED] 50 VFs
[12:00:49] [PASSED] 51 VFs
[12:00:49] [PASSED] 52 VFs
[12:00:49] [PASSED] 53 VFs
[12:00:49] [PASSED] 54 VFs
[12:00:49] [PASSED] 55 VFs
[12:00:49] [PASSED] 56 VFs
[12:00:49] [PASSED] 57 VFs
[12:00:49] [PASSED] 58 VFs
[12:00:49] [PASSED] 59 VFs
[12:00:49] [PASSED] 60 VFs
[12:00:49] [PASSED] 61 VFs
[12:00:49] [PASSED] 62 VFs
[12:00:49] [PASSED] 63 VFs
[12:00:49] ================= [PASSED] fair_doorbells ==================
[12:00:49] ======================== fair_ggtt ========================
[12:00:49] [PASSED] 1 VF
[12:00:49] [PASSED] 2 VFs
[12:00:49] [PASSED] 3 VFs
[12:00:49] [PASSED] 4 VFs
[12:00:49] [PASSED] 5 VFs
[12:00:49] [PASSED] 6 VFs
[12:00:49] [PASSED] 7 VFs
[12:00:49] [PASSED] 8 VFs
[12:00:49] [PASSED] 9 VFs
[12:00:49] [PASSED] 10 VFs
[12:00:49] [PASSED] 11 VFs
[12:00:49] [PASSED] 12 VFs
[12:00:49] [PASSED] 13 VFs
[12:00:49] [PASSED] 14 VFs
[12:00:49] [PASSED] 15 VFs
[12:00:49] [PASSED] 16 VFs
[12:00:49] [PASSED] 17 VFs
[12:00:49] [PASSED] 18 VFs
[12:00:49] [PASSED] 19 VFs
[12:00:49] [PASSED] 20 VFs
[12:00:49] [PASSED] 21 VFs
[12:00:49] [PASSED] 22 VFs
[12:00:49] [PASSED] 23 VFs
[12:00:49] [PASSED] 24 VFs
[12:00:49] [PASSED] 25 VFs
[12:00:49] [PASSED] 26 VFs
[12:00:49] [PASSED] 27 VFs
[12:00:49] [PASSED] 28 VFs
[12:00:49] [PASSED] 29 VFs
[12:00:49] [PASSED] 30 VFs
[12:00:49] [PASSED] 31 VFs
[12:00:49] [PASSED] 32 VFs
[12:00:49] [PASSED] 33 VFs
[12:00:49] [PASSED] 34 VFs
[12:00:49] [PASSED] 35 VFs
[12:00:49] [PASSED] 36 VFs
[12:00:49] [PASSED] 37 VFs
[12:00:49] [PASSED] 38 VFs
[12:00:49] [PASSED] 39 VFs
[12:00:49] [PASSED] 40 VFs
[12:00:49] [PASSED] 41 VFs
[12:00:49] [PASSED] 42 VFs
[12:00:49] [PASSED] 43 VFs
[12:00:49] [PASSED] 44 VFs
[12:00:49] [PASSED] 45 VFs
[12:00:49] [PASSED] 46 VFs
[12:00:49] [PASSED] 47 VFs
[12:00:49] [PASSED] 48 VFs
[12:00:49] [PASSED] 49 VFs
[12:00:49] [PASSED] 50 VFs
[12:00:49] [PASSED] 51 VFs
[12:00:49] [PASSED] 52 VFs
[12:00:49] [PASSED] 53 VFs
[12:00:49] [PASSED] 54 VFs
[12:00:49] [PASSED] 55 VFs
[12:00:49] [PASSED] 56 VFs
[12:00:49] [PASSED] 57 VFs
[12:00:49] [PASSED] 58 VFs
[12:00:49] [PASSED] 59 VFs
[12:00:49] [PASSED] 60 VFs
[12:00:50] [PASSED] 61 VFs
[12:00:50] [PASSED] 62 VFs
[12:00:50] [PASSED] 63 VFs
[12:00:50] ==================== [PASSED] fair_ggtt ====================
[12:00:50] ======================== fair_vram ========================
[12:00:50] [PASSED] 1 VF
[12:00:50] [PASSED] 2 VFs
[12:00:50] [PASSED] 3 VFs
[12:00:50] [PASSED] 4 VFs
[12:00:50] [PASSED] 5 VFs
[12:00:50] [PASSED] 6 VFs
[12:00:50] [PASSED] 7 VFs
[12:00:50] [PASSED] 8 VFs
[12:00:50] [PASSED] 9 VFs
[12:00:50] [PASSED] 10 VFs
[12:00:50] [PASSED] 11 VFs
[12:00:50] [PASSED] 12 VFs
[12:00:50] [PASSED] 13 VFs
[12:00:50] [PASSED] 14 VFs
[12:00:50] [PASSED] 15 VFs
[12:00:50] [PASSED] 16 VFs
[12:00:50] [PASSED] 17 VFs
[12:00:50] [PASSED] 18 VFs
[12:00:50] [PASSED] 19 VFs
[12:00:50] [PASSED] 20 VFs
[12:00:50] [PASSED] 21 VFs
[12:00:50] [PASSED] 22 VFs
[12:00:50] [PASSED] 23 VFs
[12:00:50] [PASSED] 24 VFs
[12:00:50] [PASSED] 25 VFs
[12:00:50] [PASSED] 26 VFs
[12:00:50] [PASSED] 27 VFs
[12:00:50] [PASSED] 28 VFs
[12:00:50] [PASSED] 29 VFs
[12:00:50] [PASSED] 30 VFs
[12:00:50] [PASSED] 31 VFs
[12:00:50] [PASSED] 32 VFs
[12:00:50] [PASSED] 33 VFs
[12:00:50] [PASSED] 34 VFs
[12:00:50] [PASSED] 35 VFs
[12:00:50] [PASSED] 36 VFs
[12:00:50] [PASSED] 37 VFs
[12:00:50] [PASSED] 38 VFs
[12:00:50] [PASSED] 39 VFs
[12:00:50] [PASSED] 40 VFs
[12:00:50] [PASSED] 41 VFs
[12:00:50] [PASSED] 42 VFs
[12:00:50] [PASSED] 43 VFs
[12:00:50] [PASSED] 44 VFs
[12:00:50] [PASSED] 45 VFs
[12:00:50] [PASSED] 46 VFs
[12:00:50] [PASSED] 47 VFs
[12:00:50] [PASSED] 48 VFs
[12:00:50] [PASSED] 49 VFs
[12:00:50] [PASSED] 50 VFs
[12:00:50] [PASSED] 51 VFs
[12:00:50] [PASSED] 52 VFs
[12:00:50] [PASSED] 53 VFs
[12:00:50] [PASSED] 54 VFs
[12:00:50] [PASSED] 55 VFs
[12:00:50] [PASSED] 56 VFs
[12:00:50] [PASSED] 57 VFs
[12:00:50] [PASSED] 58 VFs
[12:00:50] [PASSED] 59 VFs
[12:00:50] [PASSED] 60 VFs
[12:00:50] [PASSED] 61 VFs
[12:00:50] [PASSED] 62 VFs
[12:00:50] [PASSED] 63 VFs
[12:00:50] ==================== [PASSED] fair_vram ====================
[12:00:50] ================== [PASSED] pf_gt_config ===================
[12:00:50] ===================== lmtt (1 subtest) =====================
[12:00:50] ======================== test_ops =========================
[12:00:50] [PASSED] 2-level
[12:00:50] [PASSED] multi-level
[12:00:50] ==================== [PASSED] test_ops =====================
[12:00:50] ====================== [PASSED] lmtt =======================
[12:00:50] ================= pf_service (11 subtests) =================
[12:00:50] [PASSED] pf_negotiate_any
[12:00:50] [PASSED] pf_negotiate_base_match
[12:00:50] [PASSED] pf_negotiate_base_newer
[12:00:50] [PASSED] pf_negotiate_base_next
[12:00:50] [SKIPPED] pf_negotiate_base_older
[12:00:50] [PASSED] pf_negotiate_base_prev
[12:00:50] [PASSED] pf_negotiate_latest_match
[12:00:50] [PASSED] pf_negotiate_latest_newer
[12:00:50] [PASSED] pf_negotiate_latest_next
[12:00:50] [SKIPPED] pf_negotiate_latest_older
[12:00:50] [SKIPPED] pf_negotiate_latest_prev
[12:00:50] =================== [PASSED] pf_service ====================
[12:00:50] ================= xe_guc_g2g (2 subtests) ==================
[12:00:50] ============== xe_live_guc_g2g_kunit_default ==============
[12:00:50] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[12:00:50] ============== xe_live_guc_g2g_kunit_allmem ===============
[12:00:50] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[12:00:50] =================== [SKIPPED] xe_guc_g2g ===================
[12:00:50] =================== xe_mocs (2 subtests) ===================
[12:00:50] ================ xe_live_mocs_kernel_kunit ================
[12:00:50] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[12:00:50] ================ xe_live_mocs_reset_kunit =================
[12:00:50] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[12:00:50] ==================== [SKIPPED] xe_mocs =====================
[12:00:50] ================= xe_migrate (2 subtests) ==================
[12:00:50] ================= xe_migrate_sanity_kunit =================
[12:00:50] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[12:00:50] ================== xe_validate_ccs_kunit ==================
[12:00:50] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[12:00:50] =================== [SKIPPED] xe_migrate ===================
[12:00:50] ================== xe_dma_buf (1 subtest) ==================
[12:00:50] ==================== xe_dma_buf_kunit =====================
[12:00:50] ================ [SKIPPED] xe_dma_buf_kunit ================
[12:00:50] =================== [SKIPPED] xe_dma_buf ===================
[12:00:50] ================= xe_bo_shrink (1 subtest) =================
[12:00:50] =================== xe_bo_shrink_kunit ====================
[12:00:50] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[12:00:50] ================== [SKIPPED] xe_bo_shrink ==================
[12:00:50] ==================== xe_bo (2 subtests) ====================
[12:00:50] ================== xe_ccs_migrate_kunit ===================
[12:00:50] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[12:00:50] ==================== xe_bo_evict_kunit ====================
[12:00:50] =============== [SKIPPED] xe_bo_evict_kunit ================
[12:00:50] ===================== [SKIPPED] xe_bo ======================
[12:00:50] ==================== args (13 subtests) ====================
[12:00:50] [PASSED] count_args_test
[12:00:50] [PASSED] call_args_example
[12:00:50] [PASSED] call_args_test
[12:00:50] [PASSED] drop_first_arg_example
[12:00:50] [PASSED] drop_first_arg_test
[12:00:50] [PASSED] first_arg_example
[12:00:50] [PASSED] first_arg_test
[12:00:50] [PASSED] last_arg_example
[12:00:50] [PASSED] last_arg_test
[12:00:50] [PASSED] pick_arg_example
[12:00:50] [PASSED] if_args_example
[12:00:50] [PASSED] if_args_test
[12:00:50] [PASSED] sep_comma_example
[12:00:50] ====================== [PASSED] args =======================
[12:00:50] =================== xe_pci (3 subtests) ====================
[12:00:50] ==================== check_graphics_ip ====================
[12:00:50] [PASSED] 12.00 Xe_LP
[12:00:50] [PASSED] 12.10 Xe_LP+
[12:00:50] [PASSED] 12.55 Xe_HPG
[12:00:50] [PASSED] 12.60 Xe_HPC
[12:00:50] [PASSED] 12.70 Xe_LPG
[12:00:50] [PASSED] 12.71 Xe_LPG
[12:00:50] [PASSED] 12.74 Xe_LPG+
[12:00:50] [PASSED] 20.01 Xe2_HPG
[12:00:50] [PASSED] 20.02 Xe2_HPG
[12:00:50] [PASSED] 20.04 Xe2_LPG
[12:00:50] [PASSED] 30.00 Xe3_LPG
[12:00:50] [PASSED] 30.01 Xe3_LPG
[12:00:50] [PASSED] 30.03 Xe3_LPG
[12:00:50] [PASSED] 30.04 Xe3_LPG
[12:00:50] [PASSED] 30.05 Xe3_LPG
[12:00:50] [PASSED] 35.10 Xe3p_LPG
[12:00:50] [PASSED] 35.11 Xe3p_XPC
[12:00:50] ================ [PASSED] check_graphics_ip ================
[12:00:50] ===================== check_media_ip ======================
[12:00:50] [PASSED] 12.00 Xe_M
[12:00:50] [PASSED] 12.55 Xe_HPM
[12:00:50] [PASSED] 13.00 Xe_LPM+
[12:00:50] [PASSED] 13.01 Xe2_HPM
[12:00:50] [PASSED] 20.00 Xe2_LPM
[12:00:50] [PASSED] 30.00 Xe3_LPM
[12:00:50] [PASSED] 30.02 Xe3_LPM
[12:00:50] [PASSED] 35.00 Xe3p_LPM
[12:00:50] [PASSED] 35.03 Xe3p_HPM
[12:00:50] ================= [PASSED] check_media_ip ==================
[12:00:50] =================== check_platform_desc ===================
[12:00:50] [PASSED] 0x9A60 (TIGERLAKE)
[12:00:50] [PASSED] 0x9A68 (TIGERLAKE)
[12:00:50] [PASSED] 0x9A70 (TIGERLAKE)
[12:00:50] [PASSED] 0x9A40 (TIGERLAKE)
[12:00:50] [PASSED] 0x9A49 (TIGERLAKE)
[12:00:50] [PASSED] 0x9A59 (TIGERLAKE)
[12:00:50] [PASSED] 0x9A78 (TIGERLAKE)
[12:00:50] [PASSED] 0x9AC0 (TIGERLAKE)
[12:00:50] [PASSED] 0x9AC9 (TIGERLAKE)
[12:00:50] [PASSED] 0x9AD9 (TIGERLAKE)
[12:00:50] [PASSED] 0x9AF8 (TIGERLAKE)
[12:00:50] [PASSED] 0x4C80 (ROCKETLAKE)
[12:00:50] [PASSED] 0x4C8A (ROCKETLAKE)
[12:00:50] [PASSED] 0x4C8B (ROCKETLAKE)
[12:00:50] [PASSED] 0x4C8C (ROCKETLAKE)
[12:00:50] [PASSED] 0x4C90 (ROCKETLAKE)
[12:00:50] [PASSED] 0x4C9A (ROCKETLAKE)
[12:00:50] [PASSED] 0x4680 (ALDERLAKE_S)
[12:00:50] [PASSED] 0x4682 (ALDERLAKE_S)
[12:00:50] [PASSED] 0x4688 (ALDERLAKE_S)
[12:00:50] [PASSED] 0x468A (ALDERLAKE_S)
[12:00:50] [PASSED] 0x468B (ALDERLAKE_S)
[12:00:50] [PASSED] 0x4690 (ALDERLAKE_S)
[12:00:50] [PASSED] 0x4692 (ALDERLAKE_S)
[12:00:50] [PASSED] 0x4693 (ALDERLAKE_S)
[12:00:50] [PASSED] 0x46A0 (ALDERLAKE_P)
[12:00:50] [PASSED] 0x46A1 (ALDERLAKE_P)
[12:00:50] [PASSED] 0x46A2 (ALDERLAKE_P)
[12:00:50] [PASSED] 0x46A3 (ALDERLAKE_P)
[12:00:50] [PASSED] 0x46A6 (ALDERLAKE_P)
[12:00:50] [PASSED] 0x46A8 (ALDERLAKE_P)
[12:00:50] [PASSED] 0x46AA (ALDERLAKE_P)
[12:00:50] [PASSED] 0x462A (ALDERLAKE_P)
[12:00:50] [PASSED] 0x4626 (ALDERLAKE_P)
[12:00:50] [PASSED] 0x4628 (ALDERLAKE_P)
[12:00:50] [PASSED] 0x46B0 (ALDERLAKE_P)
[12:00:50] [PASSED] 0x46B1 (ALDERLAKE_P)
[12:00:50] [PASSED] 0x46B2 (ALDERLAKE_P)
[12:00:50] [PASSED] 0x46B3 (ALDERLAKE_P)
[12:00:50] [PASSED] 0x46C0 (ALDERLAKE_P)
[12:00:50] [PASSED] 0x46C1 (ALDERLAKE_P)
[12:00:50] [PASSED] 0x46C2 (ALDERLAKE_P)
[12:00:50] [PASSED] 0x46C3 (ALDERLAKE_P)
[12:00:50] [PASSED] 0x46D0 (ALDERLAKE_N)
[12:00:50] [PASSED] 0x46D1 (ALDERLAKE_N)
[12:00:50] [PASSED] 0x46D2 (ALDERLAKE_N)
[12:00:50] [PASSED] 0x46D3 (ALDERLAKE_N)
[12:00:50] [PASSED] 0x46D4 (ALDERLAKE_N)
[12:00:50] [PASSED] 0xA721 (ALDERLAKE_P)
[12:00:50] [PASSED] 0xA7A1 (ALDERLAKE_P)
[12:00:50] [PASSED] 0xA7A9 (ALDERLAKE_P)
[12:00:50] [PASSED] 0xA7AC (ALDERLAKE_P)
[12:00:50] [PASSED] 0xA7AD (ALDERLAKE_P)
[12:00:50] [PASSED] 0xA720 (ALDERLAKE_P)
[12:00:50] [PASSED] 0xA7A0 (ALDERLAKE_P)
[12:00:50] [PASSED] 0xA7A8 (ALDERLAKE_P)
[12:00:50] [PASSED] 0xA7AA (ALDERLAKE_P)
[12:00:50] [PASSED] 0xA7AB (ALDERLAKE_P)
[12:00:50] [PASSED] 0xA780 (ALDERLAKE_S)
[12:00:50] [PASSED] 0xA781 (ALDERLAKE_S)
[12:00:50] [PASSED] 0xA782 (ALDERLAKE_S)
[12:00:50] [PASSED] 0xA783 (ALDERLAKE_S)
[12:00:50] [PASSED] 0xA788 (ALDERLAKE_S)
[12:00:50] [PASSED] 0xA789 (ALDERLAKE_S)
[12:00:50] [PASSED] 0xA78A (ALDERLAKE_S)
[12:00:50] [PASSED] 0xA78B (ALDERLAKE_S)
[12:00:50] [PASSED] 0x4905 (DG1)
[12:00:50] [PASSED] 0x4906 (DG1)
[12:00:50] [PASSED] 0x4907 (DG1)
[12:00:50] [PASSED] 0x4908 (DG1)
[12:00:50] [PASSED] 0x4909 (DG1)
[12:00:50] [PASSED] 0x56C0 (DG2)
[12:00:50] [PASSED] 0x56C2 (DG2)
[12:00:50] [PASSED] 0x56C1 (DG2)
[12:00:50] [PASSED] 0x7D51 (METEORLAKE)
[12:00:50] [PASSED] 0x7DD1 (METEORLAKE)
[12:00:50] [PASSED] 0x7D41 (METEORLAKE)
[12:00:50] [PASSED] 0x7D67 (METEORLAKE)
[12:00:50] [PASSED] 0xB640 (METEORLAKE)
[12:00:50] [PASSED] 0x56A0 (DG2)
[12:00:50] [PASSED] 0x56A1 (DG2)
[12:00:50] [PASSED] 0x56A2 (DG2)
[12:00:50] [PASSED] 0x56BE (DG2)
[12:00:50] [PASSED] 0x56BF (DG2)
[12:00:50] [PASSED] 0x5690 (DG2)
[12:00:50] [PASSED] 0x5691 (DG2)
[12:00:50] [PASSED] 0x5692 (DG2)
[12:00:50] [PASSED] 0x56A5 (DG2)
[12:00:50] [PASSED] 0x56A6 (DG2)
[12:00:50] [PASSED] 0x56B0 (DG2)
[12:00:50] [PASSED] 0x56B1 (DG2)
[12:00:50] [PASSED] 0x56BA (DG2)
[12:00:50] [PASSED] 0x56BB (DG2)
[12:00:50] [PASSED] 0x56BC (DG2)
[12:00:50] [PASSED] 0x56BD (DG2)
[12:00:50] [PASSED] 0x5693 (DG2)
[12:00:50] [PASSED] 0x5694 (DG2)
[12:00:50] [PASSED] 0x5695 (DG2)
[12:00:50] [PASSED] 0x56A3 (DG2)
[12:00:50] [PASSED] 0x56A4 (DG2)
[12:00:50] [PASSED] 0x56B2 (DG2)
[12:00:50] [PASSED] 0x56B3 (DG2)
[12:00:50] [PASSED] 0x5696 (DG2)
[12:00:50] [PASSED] 0x5697 (DG2)
[12:00:50] [PASSED] 0xB69 (PVC)
[12:00:50] [PASSED] 0xB6E (PVC)
[12:00:50] [PASSED] 0xBD4 (PVC)
[12:00:50] [PASSED] 0xBD5 (PVC)
[12:00:50] [PASSED] 0xBD6 (PVC)
[12:00:50] [PASSED] 0xBD7 (PVC)
[12:00:50] [PASSED] 0xBD8 (PVC)
[12:00:50] [PASSED] 0xBD9 (PVC)
[12:00:50] [PASSED] 0xBDA (PVC)
[12:00:50] [PASSED] 0xBDB (PVC)
[12:00:50] [PASSED] 0xBE0 (PVC)
[12:00:50] [PASSED] 0xBE1 (PVC)
[12:00:50] [PASSED] 0xBE5 (PVC)
[12:00:50] [PASSED] 0x7D40 (METEORLAKE)
[12:00:50] [PASSED] 0x7D45 (METEORLAKE)
[12:00:50] [PASSED] 0x7D55 (METEORLAKE)
[12:00:50] [PASSED] 0x7D60 (METEORLAKE)
[12:00:50] [PASSED] 0x7DD5 (METEORLAKE)
[12:00:50] [PASSED] 0x6420 (LUNARLAKE)
[12:00:50] [PASSED] 0x64A0 (LUNARLAKE)
[12:00:50] [PASSED] 0x64B0 (LUNARLAKE)
[12:00:50] [PASSED] 0xE202 (BATTLEMAGE)
[12:00:50] [PASSED] 0xE209 (BATTLEMAGE)
[12:00:50] [PASSED] 0xE20B (BATTLEMAGE)
[12:00:50] [PASSED] 0xE20C (BATTLEMAGE)
[12:00:50] [PASSED] 0xE20D (BATTLEMAGE)
[12:00:50] [PASSED] 0xE210 (BATTLEMAGE)
[12:00:50] [PASSED] 0xE211 (BATTLEMAGE)
[12:00:50] [PASSED] 0xE212 (BATTLEMAGE)
[12:00:50] [PASSED] 0xE216 (BATTLEMAGE)
[12:00:50] [PASSED] 0xE220 (BATTLEMAGE)
[12:00:50] [PASSED] 0xE221 (BATTLEMAGE)
[12:00:50] [PASSED] 0xE222 (BATTLEMAGE)
[12:00:50] [PASSED] 0xE223 (BATTLEMAGE)
[12:00:50] [PASSED] 0xB080 (PANTHERLAKE)
[12:00:50] [PASSED] 0xB081 (PANTHERLAKE)
[12:00:50] [PASSED] 0xB082 (PANTHERLAKE)
[12:00:50] [PASSED] 0xB083 (PANTHERLAKE)
[12:00:50] [PASSED] 0xB084 (PANTHERLAKE)
[12:00:50] [PASSED] 0xB085 (PANTHERLAKE)
[12:00:50] [PASSED] 0xB086 (PANTHERLAKE)
[12:00:50] [PASSED] 0xB087 (PANTHERLAKE)
[12:00:50] [PASSED] 0xB08F (PANTHERLAKE)
[12:00:50] [PASSED] 0xB090 (PANTHERLAKE)
[12:00:50] [PASSED] 0xB0A0 (PANTHERLAKE)
[12:00:50] [PASSED] 0xB0B0 (PANTHERLAKE)
[12:00:50] [PASSED] 0xFD80 (PANTHERLAKE)
[12:00:50] [PASSED] 0xFD81 (PANTHERLAKE)
[12:00:50] [PASSED] 0xD740 (NOVALAKE_S)
[12:00:50] [PASSED] 0xD741 (NOVALAKE_S)
[12:00:50] [PASSED] 0xD742 (NOVALAKE_S)
[12:00:50] [PASSED] 0xD743 (NOVALAKE_S)
[12:00:50] [PASSED] 0xD744 (NOVALAKE_S)
[12:00:50] [PASSED] 0xD745 (NOVALAKE_S)
[12:00:50] [PASSED] 0x674C (CRESCENTISLAND)
[12:00:50] [PASSED] 0x674D (CRESCENTISLAND)
[12:00:50] [PASSED] 0x674E (CRESCENTISLAND)
[12:00:50] [PASSED] 0x674F (CRESCENTISLAND)
[12:00:50] [PASSED] 0x6750 (CRESCENTISLAND)
[12:00:50] [PASSED] 0xD750 (NOVALAKE_P)
[12:00:50] [PASSED] 0xD751 (NOVALAKE_P)
[12:00:50] [PASSED] 0xD752 (NOVALAKE_P)
[12:00:50] [PASSED] 0xD753 (NOVALAKE_P)
[12:00:50] [PASSED] 0xD754 (NOVALAKE_P)
[12:00:50] [PASSED] 0xD755 (NOVALAKE_P)
[12:00:50] [PASSED] 0xD756 (NOVALAKE_P)
[12:00:50] [PASSED] 0xD757 (NOVALAKE_P)
[12:00:50] [PASSED] 0xD75F (NOVALAKE_P)
[12:00:50] =============== [PASSED] check_platform_desc ===============
[12:00:50] ===================== [PASSED] xe_pci ======================
[12:00:50] =================== xe_rtp (2 subtests) ====================
[12:00:50] =============== xe_rtp_process_to_sr_tests ================
[12:00:50] [PASSED] coalesce-same-reg
[12:00:50] [PASSED] no-match-no-add
[12:00:50] [PASSED] match-or
[12:00:50] [PASSED] match-or-xfail
[12:00:50] [PASSED] no-match-no-add-multiple-rules
[12:00:50] [PASSED] two-regs-two-entries
[12:00:50] [PASSED] clr-one-set-other
[12:00:50] [PASSED] set-field
[12:00:50] [PASSED] conflict-duplicate
[12:00:50] [PASSED] conflict-not-disjoint
[12:00:50] [PASSED] conflict-reg-type
[12:00:50] [PASSED] bad-mcr-reg-forced-to-regular
[12:00:50] [PASSED] bad-regular-reg-forced-to-mcr
[12:00:50] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[12:00:50] ================== xe_rtp_process_tests ===================
[12:00:50] [PASSED] active1
[12:00:50] [PASSED] active2
[12:00:50] [PASSED] active-inactive
[12:00:50] [PASSED] inactive-active
[12:00:50] [PASSED] inactive-1st_or_active-inactive
[12:00:50] [PASSED] inactive-2nd_or_active-inactive
[12:00:50] [PASSED] inactive-last_or_active-inactive
[12:00:50] [PASSED] inactive-no_or_active-inactive
[12:00:50] ============== [PASSED] xe_rtp_process_tests ===============
[12:00:50] ===================== [PASSED] xe_rtp ======================
[12:00:50] ==================== xe_wa (1 subtest) =====================
[12:00:50] ======================== xe_wa_gt =========================
[12:00:50] [PASSED] TIGERLAKE B0
[12:00:50] [PASSED] DG1 A0
[12:00:50] [PASSED] DG1 B0
[12:00:50] [PASSED] ALDERLAKE_S A0
[12:00:50] [PASSED] ALDERLAKE_S B0
[12:00:50] [PASSED] ALDERLAKE_S C0
[12:00:50] [PASSED] ALDERLAKE_S D0
[12:00:50] [PASSED] ALDERLAKE_P A0
[12:00:50] [PASSED] ALDERLAKE_P B0
[12:00:50] [PASSED] ALDERLAKE_P C0
[12:00:50] [PASSED] ALDERLAKE_S RPLS D0
[12:00:50] [PASSED] ALDERLAKE_P RPLU E0
[12:00:50] [PASSED] DG2 G10 C0
[12:00:50] [PASSED] DG2 G11 B1
[12:00:50] [PASSED] DG2 G12 A1
[12:00:50] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:00:50] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:00:50] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[12:00:50] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[12:00:50] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[12:00:50] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[12:00:50] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[12:00:50] ==================== [PASSED] xe_wa_gt =====================
[12:00:50] ====================== [PASSED] xe_wa ======================
[12:00:50] ============================================================
[12:00:50] Testing complete. Ran 603 tests: passed: 585, skipped: 18
[12:00:50] Elapsed time: 36.219s total, 4.284s configuring, 31.266s building, 0.618s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[12:00:50] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:00:51] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:01:16] Starting KUnit Kernel (1/1)...
[12:01:16] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:01:16] ============ drm_test_pick_cmdline (2 subtests) ============
[12:01:16] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[12:01:16] =============== drm_test_pick_cmdline_named ===============
[12:01:16] [PASSED] NTSC
[12:01:16] [PASSED] NTSC-J
[12:01:16] [PASSED] PAL
[12:01:16] [PASSED] PAL-M
[12:01:16] =========== [PASSED] drm_test_pick_cmdline_named ===========
[12:01:16] ============== [PASSED] drm_test_pick_cmdline ==============
[12:01:16] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[12:01:16] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[12:01:16] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[12:01:16] =========== drm_validate_clone_mode (2 subtests) ===========
[12:01:16] ============== drm_test_check_in_clone_mode ===============
[12:01:16] [PASSED] in_clone_mode
[12:01:16] [PASSED] not_in_clone_mode
[12:01:16] ========== [PASSED] drm_test_check_in_clone_mode ===========
[12:01:16] =============== drm_test_check_valid_clones ===============
[12:01:16] [PASSED] not_in_clone_mode
[12:01:16] [PASSED] valid_clone
[12:01:16] [PASSED] invalid_clone
[12:01:16] =========== [PASSED] drm_test_check_valid_clones ===========
[12:01:16] ============= [PASSED] drm_validate_clone_mode =============
[12:01:16] ============= drm_validate_modeset (1 subtest) =============
[12:01:16] [PASSED] drm_test_check_connector_changed_modeset
[12:01:16] ============== [PASSED] drm_validate_modeset ===============
[12:01:16] ====== drm_test_bridge_get_current_state (2 subtests) ======
[12:01:16] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[12:01:16] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[12:01:16] ======== [PASSED] drm_test_bridge_get_current_state ========
[12:01:16] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[12:01:16] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[12:01:16] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[12:01:16] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[12:01:16] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[12:01:16] ============== drm_bridge_alloc (2 subtests) ===============
[12:01:16] [PASSED] drm_test_drm_bridge_alloc_basic
[12:01:16] [PASSED] drm_test_drm_bridge_alloc_get_put
[12:01:16] ================ [PASSED] drm_bridge_alloc =================
[12:01:16] ============= drm_cmdline_parser (40 subtests) =============
[12:01:16] [PASSED] drm_test_cmdline_force_d_only
[12:01:16] [PASSED] drm_test_cmdline_force_D_only_dvi
[12:01:16] [PASSED] drm_test_cmdline_force_D_only_hdmi
[12:01:16] [PASSED] drm_test_cmdline_force_D_only_not_digital
[12:01:16] [PASSED] drm_test_cmdline_force_e_only
[12:01:16] [PASSED] drm_test_cmdline_res
[12:01:16] [PASSED] drm_test_cmdline_res_vesa
[12:01:16] [PASSED] drm_test_cmdline_res_vesa_rblank
[12:01:16] [PASSED] drm_test_cmdline_res_rblank
[12:01:16] [PASSED] drm_test_cmdline_res_bpp
[12:01:16] [PASSED] drm_test_cmdline_res_refresh
[12:01:16] [PASSED] drm_test_cmdline_res_bpp_refresh
[12:01:16] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[12:01:16] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[12:01:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[12:01:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[12:01:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[12:01:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[12:01:16] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[12:01:16] [PASSED] drm_test_cmdline_res_margins_force_on
[12:01:16] [PASSED] drm_test_cmdline_res_vesa_margins
[12:01:16] [PASSED] drm_test_cmdline_name
[12:01:16] [PASSED] drm_test_cmdline_name_bpp
[12:01:16] [PASSED] drm_test_cmdline_name_option
[12:01:16] [PASSED] drm_test_cmdline_name_bpp_option
[12:01:16] [PASSED] drm_test_cmdline_rotate_0
[12:01:16] [PASSED] drm_test_cmdline_rotate_90
[12:01:16] [PASSED] drm_test_cmdline_rotate_180
[12:01:16] [PASSED] drm_test_cmdline_rotate_270
[12:01:16] [PASSED] drm_test_cmdline_hmirror
[12:01:16] [PASSED] drm_test_cmdline_vmirror
[12:01:16] [PASSED] drm_test_cmdline_margin_options
[12:01:16] [PASSED] drm_test_cmdline_multiple_options
[12:01:16] [PASSED] drm_test_cmdline_bpp_extra_and_option
[12:01:16] [PASSED] drm_test_cmdline_extra_and_option
[12:01:16] [PASSED] drm_test_cmdline_freestanding_options
[12:01:16] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[12:01:16] [PASSED] drm_test_cmdline_panel_orientation
[12:01:16] ================ drm_test_cmdline_invalid =================
[12:01:16] [PASSED] margin_only
[12:01:16] [PASSED] interlace_only
[12:01:16] [PASSED] res_missing_x
[12:01:16] [PASSED] res_missing_y
[12:01:16] [PASSED] res_bad_y
[12:01:16] [PASSED] res_missing_y_bpp
[12:01:16] [PASSED] res_bad_bpp
[12:01:16] [PASSED] res_bad_refresh
[12:01:16] [PASSED] res_bpp_refresh_force_on_off
[12:01:16] [PASSED] res_invalid_mode
[12:01:16] [PASSED] res_bpp_wrong_place_mode
[12:01:16] [PASSED] name_bpp_refresh
[12:01:16] [PASSED] name_refresh
[12:01:16] [PASSED] name_refresh_wrong_mode
[12:01:16] [PASSED] name_refresh_invalid_mode
[12:01:16] [PASSED] rotate_multiple
[12:01:16] [PASSED] rotate_invalid_val
[12:01:16] [PASSED] rotate_truncated
[12:01:16] [PASSED] invalid_option
[12:01:16] [PASSED] invalid_tv_option
[12:01:16] [PASSED] truncated_tv_option
[12:01:16] ============ [PASSED] drm_test_cmdline_invalid =============
[12:01:16] =============== drm_test_cmdline_tv_options ===============
[12:01:16] [PASSED] NTSC
[12:01:16] [PASSED] NTSC_443
[12:01:16] [PASSED] NTSC_J
[12:01:16] [PASSED] PAL
[12:01:16] [PASSED] PAL_M
[12:01:16] [PASSED] PAL_N
[12:01:16] [PASSED] SECAM
[12:01:16] [PASSED] MONO_525
[12:01:16] [PASSED] MONO_625
[12:01:16] =========== [PASSED] drm_test_cmdline_tv_options ===========
[12:01:16] =============== [PASSED] drm_cmdline_parser ================
[12:01:16] ========== drmm_connector_hdmi_init (20 subtests) ==========
[12:01:16] [PASSED] drm_test_connector_hdmi_init_valid
[12:01:16] [PASSED] drm_test_connector_hdmi_init_bpc_8
[12:01:16] [PASSED] drm_test_connector_hdmi_init_bpc_10
[12:01:16] [PASSED] drm_test_connector_hdmi_init_bpc_12
[12:01:16] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[12:01:16] [PASSED] drm_test_connector_hdmi_init_bpc_null
[12:01:16] [PASSED] drm_test_connector_hdmi_init_formats_empty
[12:01:16] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[12:01:16] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[12:01:16] [PASSED] supported_formats=0x9 yuv420_allowed=1
[12:01:16] [PASSED] supported_formats=0x9 yuv420_allowed=0
[12:01:16] [PASSED] supported_formats=0x5 yuv420_allowed=1
[12:01:16] [PASSED] supported_formats=0x5 yuv420_allowed=0
[12:01:16] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[12:01:16] [PASSED] drm_test_connector_hdmi_init_null_ddc
[12:01:16] [PASSED] drm_test_connector_hdmi_init_null_product
[12:01:16] [PASSED] drm_test_connector_hdmi_init_null_vendor
[12:01:16] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[12:01:16] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[12:01:16] [PASSED] drm_test_connector_hdmi_init_product_valid
[12:01:16] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[12:01:16] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[12:01:16] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[12:01:16] ========= drm_test_connector_hdmi_init_type_valid =========
[12:01:16] [PASSED] HDMI-A
[12:01:16] [PASSED] HDMI-B
[12:01:16] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[12:01:16] ======== drm_test_connector_hdmi_init_type_invalid ========
[12:01:16] [PASSED] Unknown
[12:01:16] [PASSED] VGA
[12:01:16] [PASSED] DVI-I
[12:01:16] [PASSED] DVI-D
[12:01:16] [PASSED] DVI-A
[12:01:16] [PASSED] Composite
[12:01:16] [PASSED] SVIDEO
[12:01:16] [PASSED] LVDS
[12:01:16] [PASSED] Component
[12:01:16] [PASSED] DIN
[12:01:16] [PASSED] DP
[12:01:16] [PASSED] TV
[12:01:16] [PASSED] eDP
[12:01:16] [PASSED] Virtual
[12:01:16] [PASSED] DSI
[12:01:16] [PASSED] DPI
[12:01:16] [PASSED] Writeback
[12:01:16] [PASSED] SPI
[12:01:16] [PASSED] USB
[12:01:16] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[12:01:16] ============ [PASSED] drmm_connector_hdmi_init =============
[12:01:16] ============= drmm_connector_init (3 subtests) =============
[12:01:16] [PASSED] drm_test_drmm_connector_init
[12:01:16] [PASSED] drm_test_drmm_connector_init_null_ddc
[12:01:16] ========= drm_test_drmm_connector_init_type_valid =========
[12:01:16] [PASSED] Unknown
[12:01:16] [PASSED] VGA
[12:01:16] [PASSED] DVI-I
[12:01:16] [PASSED] DVI-D
[12:01:16] [PASSED] DVI-A
[12:01:16] [PASSED] Composite
[12:01:16] [PASSED] SVIDEO
[12:01:16] [PASSED] LVDS
[12:01:16] [PASSED] Component
[12:01:16] [PASSED] DIN
[12:01:16] [PASSED] DP
[12:01:16] [PASSED] HDMI-A
[12:01:16] [PASSED] HDMI-B
[12:01:16] [PASSED] TV
[12:01:16] [PASSED] eDP
[12:01:16] [PASSED] Virtual
[12:01:16] [PASSED] DSI
[12:01:16] [PASSED] DPI
[12:01:16] [PASSED] Writeback
[12:01:16] [PASSED] SPI
[12:01:16] [PASSED] USB
[12:01:16] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[12:01:16] =============== [PASSED] drmm_connector_init ===============
[12:01:16] ========= drm_connector_dynamic_init (6 subtests) ==========
[12:01:16] [PASSED] drm_test_drm_connector_dynamic_init
[12:01:16] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[12:01:16] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[12:01:16] [PASSED] drm_test_drm_connector_dynamic_init_properties
[12:01:16] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[12:01:16] [PASSED] Unknown
[12:01:16] [PASSED] VGA
[12:01:16] [PASSED] DVI-I
[12:01:16] [PASSED] DVI-D
[12:01:16] [PASSED] DVI-A
[12:01:16] [PASSED] Composite
[12:01:16] [PASSED] SVIDEO
[12:01:16] [PASSED] LVDS
[12:01:16] [PASSED] Component
[12:01:16] [PASSED] DIN
[12:01:16] [PASSED] DP
[12:01:16] [PASSED] HDMI-A
[12:01:16] [PASSED] HDMI-B
[12:01:16] [PASSED] TV
[12:01:16] [PASSED] eDP
[12:01:16] [PASSED] Virtual
[12:01:16] [PASSED] DSI
[12:01:16] [PASSED] DPI
[12:01:16] [PASSED] Writeback
[12:01:16] [PASSED] SPI
[12:01:16] [PASSED] USB
[12:01:16] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[12:01:16] ======== drm_test_drm_connector_dynamic_init_name =========
[12:01:16] [PASSED] Unknown
[12:01:16] [PASSED] VGA
[12:01:16] [PASSED] DVI-I
[12:01:16] [PASSED] DVI-D
[12:01:16] [PASSED] DVI-A
[12:01:16] [PASSED] Composite
[12:01:16] [PASSED] SVIDEO
[12:01:16] [PASSED] LVDS
[12:01:16] [PASSED] Component
[12:01:16] [PASSED] DIN
[12:01:16] [PASSED] DP
[12:01:16] [PASSED] HDMI-A
[12:01:16] [PASSED] HDMI-B
[12:01:16] [PASSED] TV
[12:01:16] [PASSED] eDP
[12:01:16] [PASSED] Virtual
[12:01:16] [PASSED] DSI
[12:01:16] [PASSED] DPI
[12:01:16] [PASSED] Writeback
[12:01:16] [PASSED] SPI
[12:01:16] [PASSED] USB
[12:01:16] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[12:01:16] =========== [PASSED] drm_connector_dynamic_init ============
[12:01:16] ==== drm_connector_dynamic_register_early (4 subtests) =====
[12:01:16] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[12:01:16] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[12:01:16] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[12:01:16] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[12:01:16] ====== [PASSED] drm_connector_dynamic_register_early =======
[12:01:16] ======= drm_connector_dynamic_register (7 subtests) ========
[12:01:16] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[12:01:16] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[12:01:16] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[12:01:16] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[12:01:16] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[12:01:16] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[12:01:16] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[12:01:16] ========= [PASSED] drm_connector_dynamic_register ==========
[12:01:16] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[12:01:16] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[12:01:16] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[12:01:16] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[12:01:16] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[12:01:16] ========== drm_test_get_tv_mode_from_name_valid ===========
[12:01:16] [PASSED] NTSC
[12:01:16] [PASSED] NTSC-443
[12:01:16] [PASSED] NTSC-J
[12:01:16] [PASSED] PAL
[12:01:16] [PASSED] PAL-M
[12:01:16] [PASSED] PAL-N
[12:01:16] [PASSED] SECAM
[12:01:16] [PASSED] Mono
[12:01:16] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[12:01:16] [PASSED] drm_test_get_tv_mode_from_name_truncated
[12:01:16] ============ [PASSED] drm_get_tv_mode_from_name ============
[12:01:16] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[12:01:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[12:01:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[12:01:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[12:01:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[12:01:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[12:01:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[12:01:16] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[12:01:16] [PASSED] VIC 96
[12:01:16] [PASSED] VIC 97
[12:01:16] [PASSED] VIC 101
[12:01:16] [PASSED] VIC 102
[12:01:16] [PASSED] VIC 106
[12:01:16] [PASSED] VIC 107
[12:01:16] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[12:01:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[12:01:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[12:01:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[12:01:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[12:01:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[12:01:16] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[12:01:16] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[12:01:16] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[12:01:16] [PASSED] Automatic
[12:01:16] [PASSED] Full
[12:01:16] [PASSED] Limited 16:235
[12:01:16] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[12:01:16] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[12:01:16] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[12:01:16] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[12:01:16] === drm_test_drm_hdmi_connector_get_output_format_name ====
[12:01:16] [PASSED] RGB
[12:01:16] [PASSED] YUV 4:2:0
[12:01:16] [PASSED] YUV 4:2:2
[12:01:16] [PASSED] YUV 4:4:4
[12:01:16] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[12:01:16] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[12:01:16] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[12:01:16] ============= drm_damage_helper (21 subtests) ==============
[12:01:16] [PASSED] drm_test_damage_iter_no_damage
[12:01:16] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[12:01:16] [PASSED] drm_test_damage_iter_no_damage_src_moved
[12:01:16] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[12:01:16] [PASSED] drm_test_damage_iter_no_damage_not_visible
[12:01:16] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[12:01:16] [PASSED] drm_test_damage_iter_no_damage_no_fb
[12:01:16] [PASSED] drm_test_damage_iter_simple_damage
[12:01:16] [PASSED] drm_test_damage_iter_single_damage
[12:01:16] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[12:01:16] [PASSED] drm_test_damage_iter_single_damage_outside_src
[12:01:16] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[12:01:16] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[12:01:16] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[12:01:16] [PASSED] drm_test_damage_iter_single_damage_src_moved
[12:01:16] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[12:01:16] [PASSED] drm_test_damage_iter_damage
[12:01:16] [PASSED] drm_test_damage_iter_damage_one_intersect
[12:01:16] [PASSED] drm_test_damage_iter_damage_one_outside
[12:01:16] [PASSED] drm_test_damage_iter_damage_src_moved
[12:01:16] [PASSED] drm_test_damage_iter_damage_not_visible
[12:01:16] ================ [PASSED] drm_damage_helper ================
[12:01:16] ============== drm_dp_mst_helper (3 subtests) ==============
[12:01:16] ============== drm_test_dp_mst_calc_pbn_mode ==============
[12:01:16] [PASSED] Clock 154000 BPP 30 DSC disabled
[12:01:16] [PASSED] Clock 234000 BPP 30 DSC disabled
[12:01:16] [PASSED] Clock 297000 BPP 24 DSC disabled
[12:01:16] [PASSED] Clock 332880 BPP 24 DSC enabled
[12:01:16] [PASSED] Clock 324540 BPP 24 DSC enabled
[12:01:16] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[12:01:16] ============== drm_test_dp_mst_calc_pbn_div ===============
[12:01:16] [PASSED] Link rate 2000000 lane count 4
[12:01:16] [PASSED] Link rate 2000000 lane count 2
[12:01:16] [PASSED] Link rate 2000000 lane count 1
[12:01:16] [PASSED] Link rate 1350000 lane count 4
[12:01:16] [PASSED] Link rate 1350000 lane count 2
[12:01:16] [PASSED] Link rate 1350000 lane count 1
[12:01:16] [PASSED] Link rate 1000000 lane count 4
[12:01:16] [PASSED] Link rate 1000000 lane count 2
[12:01:16] [PASSED] Link rate 1000000 lane count 1
[12:01:16] [PASSED] Link rate 810000 lane count 4
[12:01:16] [PASSED] Link rate 810000 lane count 2
[12:01:16] [PASSED] Link rate 810000 lane count 1
[12:01:16] [PASSED] Link rate 540000 lane count 4
[12:01:16] [PASSED] Link rate 540000 lane count 2
[12:01:16] [PASSED] Link rate 540000 lane count 1
[12:01:16] [PASSED] Link rate 270000 lane count 4
[12:01:16] [PASSED] Link rate 270000 lane count 2
[12:01:16] [PASSED] Link rate 270000 lane count 1
[12:01:16] [PASSED] Link rate 162000 lane count 4
[12:01:16] [PASSED] Link rate 162000 lane count 2
[12:01:16] [PASSED] Link rate 162000 lane count 1
[12:01:16] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[12:01:16] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[12:01:16] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[12:01:16] [PASSED] DP_POWER_UP_PHY with port number
[12:01:16] [PASSED] DP_POWER_DOWN_PHY with port number
[12:01:16] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[12:01:16] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[12:01:16] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[12:01:16] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[12:01:16] [PASSED] DP_QUERY_PAYLOAD with port number
[12:01:16] [PASSED] DP_QUERY_PAYLOAD with VCPI
[12:01:16] [PASSED] DP_REMOTE_DPCD_READ with port number
[12:01:16] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[12:01:16] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[12:01:16] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[12:01:16] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[12:01:16] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[12:01:16] [PASSED] DP_REMOTE_I2C_READ with port number
[12:01:16] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[12:01:16] [PASSED] DP_REMOTE_I2C_READ with transactions array
[12:01:16] [PASSED] DP_REMOTE_I2C_WRITE with port number
[12:01:16] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[12:01:16] [PASSED] DP_REMOTE_I2C_WRITE with data array
[12:01:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[12:01:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[12:01:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[12:01:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[12:01:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[12:01:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[12:01:16] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[12:01:16] ================ [PASSED] drm_dp_mst_helper ================
[12:01:16] ================== drm_exec (7 subtests) ===================
[12:01:16] [PASSED] sanitycheck
[12:01:16] [PASSED] test_lock
[12:01:16] [PASSED] test_lock_unlock
[12:01:16] [PASSED] test_duplicates
[12:01:16] [PASSED] test_prepare
[12:01:16] [PASSED] test_prepare_array
[12:01:16] [PASSED] test_multiple_loops
[12:01:16] ==================== [PASSED] drm_exec =====================
[12:01:16] =========== drm_format_helper_test (17 subtests) ===========
[12:01:16] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[12:01:16] [PASSED] single_pixel_source_buffer
[12:01:16] [PASSED] single_pixel_clip_rectangle
[12:01:16] [PASSED] well_known_colors
[12:01:16] [PASSED] destination_pitch
[12:01:16] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[12:01:16] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[12:01:16] [PASSED] single_pixel_source_buffer
[12:01:16] [PASSED] single_pixel_clip_rectangle
[12:01:16] [PASSED] well_known_colors
[12:01:16] [PASSED] destination_pitch
[12:01:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[12:01:16] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[12:01:16] [PASSED] single_pixel_source_buffer
[12:01:16] [PASSED] single_pixel_clip_rectangle
[12:01:16] [PASSED] well_known_colors
[12:01:16] [PASSED] destination_pitch
[12:01:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[12:01:16] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[12:01:16] [PASSED] single_pixel_source_buffer
[12:01:16] [PASSED] single_pixel_clip_rectangle
[12:01:16] [PASSED] well_known_colors
[12:01:16] [PASSED] destination_pitch
[12:01:16] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[12:01:16] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[12:01:16] [PASSED] single_pixel_source_buffer
[12:01:16] [PASSED] single_pixel_clip_rectangle
[12:01:16] [PASSED] well_known_colors
[12:01:16] [PASSED] destination_pitch
[12:01:16] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[12:01:16] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[12:01:16] [PASSED] single_pixel_source_buffer
[12:01:16] [PASSED] single_pixel_clip_rectangle
[12:01:16] [PASSED] well_known_colors
[12:01:16] [PASSED] destination_pitch
[12:01:16] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[12:01:16] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[12:01:16] [PASSED] single_pixel_source_buffer
[12:01:16] [PASSED] single_pixel_clip_rectangle
[12:01:16] [PASSED] well_known_colors
[12:01:16] [PASSED] destination_pitch
[12:01:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[12:01:16] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[12:01:16] [PASSED] single_pixel_source_buffer
[12:01:16] [PASSED] single_pixel_clip_rectangle
[12:01:16] [PASSED] well_known_colors
[12:01:16] [PASSED] destination_pitch
[12:01:16] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[12:01:16] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[12:01:16] [PASSED] single_pixel_source_buffer
[12:01:16] [PASSED] single_pixel_clip_rectangle
[12:01:16] [PASSED] well_known_colors
[12:01:16] [PASSED] destination_pitch
[12:01:16] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[12:01:16] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[12:01:16] [PASSED] single_pixel_source_buffer
[12:01:16] [PASSED] single_pixel_clip_rectangle
[12:01:16] [PASSED] well_known_colors
[12:01:16] [PASSED] destination_pitch
[12:01:16] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[12:01:16] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[12:01:16] [PASSED] single_pixel_source_buffer
[12:01:16] [PASSED] single_pixel_clip_rectangle
[12:01:16] [PASSED] well_known_colors
[12:01:16] [PASSED] destination_pitch
[12:01:16] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[12:01:16] ============== drm_test_fb_xrgb8888_to_mono ===============
[12:01:16] [PASSED] single_pixel_source_buffer
[12:01:16] [PASSED] single_pixel_clip_rectangle
[12:01:16] [PASSED] well_known_colors
[12:01:16] [PASSED] destination_pitch
[12:01:16] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[12:01:16] ==================== drm_test_fb_swab =====================
[12:01:16] [PASSED] single_pixel_source_buffer
[12:01:16] [PASSED] single_pixel_clip_rectangle
[12:01:16] [PASSED] well_known_colors
[12:01:16] [PASSED] destination_pitch
[12:01:16] ================ [PASSED] drm_test_fb_swab =================
[12:01:16] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[12:01:16] [PASSED] single_pixel_source_buffer
[12:01:16] [PASSED] single_pixel_clip_rectangle
[12:01:16] [PASSED] well_known_colors
[12:01:16] [PASSED] destination_pitch
[12:01:16] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[12:01:16] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[12:01:16] [PASSED] single_pixel_source_buffer
[12:01:16] [PASSED] single_pixel_clip_rectangle
[12:01:16] [PASSED] well_known_colors
[12:01:16] [PASSED] destination_pitch
[12:01:16] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[12:01:16] ================= drm_test_fb_clip_offset =================
[12:01:16] [PASSED] pass through
[12:01:16] [PASSED] horizontal offset
[12:01:16] [PASSED] vertical offset
[12:01:16] [PASSED] horizontal and vertical offset
[12:01:16] [PASSED] horizontal offset (custom pitch)
[12:01:16] [PASSED] vertical offset (custom pitch)
[12:01:16] [PASSED] horizontal and vertical offset (custom pitch)
[12:01:16] ============= [PASSED] drm_test_fb_clip_offset =============
[12:01:16] =================== drm_test_fb_memcpy ====================
[12:01:16] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[12:01:16] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[12:01:16] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[12:01:16] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[12:01:16] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[12:01:16] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[12:01:16] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[12:01:16] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[12:01:16] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[12:01:16] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[12:01:16] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[12:01:16] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[12:01:16] =============== [PASSED] drm_test_fb_memcpy ================
[12:01:16] ============= [PASSED] drm_format_helper_test ==============
[12:01:16] ================= drm_format (18 subtests) =================
[12:01:16] [PASSED] drm_test_format_block_width_invalid
[12:01:16] [PASSED] drm_test_format_block_width_one_plane
[12:01:16] [PASSED] drm_test_format_block_width_two_plane
[12:01:16] [PASSED] drm_test_format_block_width_three_plane
[12:01:16] [PASSED] drm_test_format_block_width_tiled
[12:01:16] [PASSED] drm_test_format_block_height_invalid
[12:01:16] [PASSED] drm_test_format_block_height_one_plane
[12:01:16] [PASSED] drm_test_format_block_height_two_plane
[12:01:16] [PASSED] drm_test_format_block_height_three_plane
[12:01:16] [PASSED] drm_test_format_block_height_tiled
[12:01:16] [PASSED] drm_test_format_min_pitch_invalid
[12:01:16] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[12:01:16] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[12:01:16] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[12:01:16] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[12:01:16] [PASSED] drm_test_format_min_pitch_two_plane
[12:01:16] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[12:01:16] [PASSED] drm_test_format_min_pitch_tiled
[12:01:16] =================== [PASSED] drm_format ====================
[12:01:16] ============== drm_framebuffer (10 subtests) ===============
[12:01:16] ========== drm_test_framebuffer_check_src_coords ==========
[12:01:16] [PASSED] Success: source fits into fb
[12:01:16] [PASSED] Fail: overflowing fb with x-axis coordinate
[12:01:16] [PASSED] Fail: overflowing fb with y-axis coordinate
[12:01:16] [PASSED] Fail: overflowing fb with source width
[12:01:16] [PASSED] Fail: overflowing fb with source height
[12:01:16] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[12:01:16] [PASSED] drm_test_framebuffer_cleanup
[12:01:16] =============== drm_test_framebuffer_create ===============
[12:01:16] [PASSED] ABGR8888 normal sizes
[12:01:16] [PASSED] ABGR8888 max sizes
[12:01:16] [PASSED] ABGR8888 pitch greater than min required
[12:01:16] [PASSED] ABGR8888 pitch less than min required
[12:01:16] [PASSED] ABGR8888 Invalid width
[12:01:16] [PASSED] ABGR8888 Invalid buffer handle
[12:01:16] [PASSED] No pixel format
[12:01:16] [PASSED] ABGR8888 Width 0
[12:01:16] [PASSED] ABGR8888 Height 0
[12:01:16] [PASSED] ABGR8888 Out of bound height * pitch combination
[12:01:16] [PASSED] ABGR8888 Large buffer offset
[12:01:16] [PASSED] ABGR8888 Buffer offset for inexistent plane
[12:01:16] [PASSED] ABGR8888 Invalid flag
[12:01:16] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[12:01:16] [PASSED] ABGR8888 Valid buffer modifier
[12:01:16] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[12:01:16] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[12:01:16] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[12:01:16] [PASSED] NV12 Normal sizes
[12:01:16] [PASSED] NV12 Max sizes
[12:01:16] [PASSED] NV12 Invalid pitch
[12:01:16] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[12:01:16] [PASSED] NV12 different modifier per-plane
[12:01:16] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[12:01:16] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[12:01:16] [PASSED] NV12 Modifier for inexistent plane
[12:01:16] [PASSED] NV12 Handle for inexistent plane
[12:01:16] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[12:01:16] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[12:01:16] [PASSED] YVU420 Normal sizes
[12:01:16] [PASSED] YVU420 Max sizes
[12:01:16] [PASSED] YVU420 Invalid pitch
[12:01:16] [PASSED] YVU420 Different pitches
[12:01:16] [PASSED] YVU420 Different buffer offsets/pitches
[12:01:16] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[12:01:16] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[12:01:16] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[12:01:16] [PASSED] YVU420 Valid modifier
[12:01:16] [PASSED] YVU420 Different modifiers per plane
[12:01:16] [PASSED] YVU420 Modifier for inexistent plane
[12:01:16] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[12:01:16] [PASSED] X0L2 Normal sizes
[12:01:16] [PASSED] X0L2 Max sizes
[12:01:16] [PASSED] X0L2 Invalid pitch
[12:01:16] [PASSED] X0L2 Pitch greater than minimum required
[12:01:16] [PASSED] X0L2 Handle for inexistent plane
[12:01:16] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[12:01:16] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[12:01:16] [PASSED] X0L2 Valid modifier
[12:01:16] [PASSED] X0L2 Modifier for inexistent plane
[12:01:16] =========== [PASSED] drm_test_framebuffer_create ===========
[12:01:16] [PASSED] drm_test_framebuffer_free
[12:01:16] [PASSED] drm_test_framebuffer_init
[12:01:16] [PASSED] drm_test_framebuffer_init_bad_format
[12:01:16] [PASSED] drm_test_framebuffer_init_dev_mismatch
[12:01:16] [PASSED] drm_test_framebuffer_lookup
[12:01:16] [PASSED] drm_test_framebuffer_lookup_inexistent
[12:01:16] [PASSED] drm_test_framebuffer_modifiers_not_supported
[12:01:16] ================= [PASSED] drm_framebuffer =================
[12:01:16] ================ drm_gem_shmem (8 subtests) ================
[12:01:16] [PASSED] drm_gem_shmem_test_obj_create
[12:01:16] [PASSED] drm_gem_shmem_test_obj_create_private
[12:01:16] [PASSED] drm_gem_shmem_test_pin_pages
[12:01:16] [PASSED] drm_gem_shmem_test_vmap
[12:01:16] [PASSED] drm_gem_shmem_test_get_sg_table
[12:01:16] [PASSED] drm_gem_shmem_test_get_pages_sgt
[12:01:16] [PASSED] drm_gem_shmem_test_madvise
[12:01:16] [PASSED] drm_gem_shmem_test_purge
[12:01:16] ================== [PASSED] drm_gem_shmem ==================
[12:01:16] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[12:01:16] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[12:01:16] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[12:01:16] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[12:01:16] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[12:01:16] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[12:01:16] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[12:01:16] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[12:01:16] [PASSED] Automatic
[12:01:16] [PASSED] Full
[12:01:16] [PASSED] Limited 16:235
[12:01:16] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[12:01:16] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[12:01:16] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[12:01:16] [PASSED] drm_test_check_disable_connector
[12:01:16] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[12:01:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[12:01:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[12:01:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[12:01:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[12:01:16] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[12:01:16] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[12:01:16] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[12:01:16] [PASSED] drm_test_check_output_bpc_dvi
[12:01:16] [PASSED] drm_test_check_output_bpc_format_vic_1
[12:01:16] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[12:01:16] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[12:01:16] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[12:01:16] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[12:01:16] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[12:01:16] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[12:01:16] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[12:01:16] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[12:01:16] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[12:01:16] [PASSED] drm_test_check_broadcast_rgb_value
[12:01:16] [PASSED] drm_test_check_bpc_8_value
[12:01:16] [PASSED] drm_test_check_bpc_10_value
[12:01:16] [PASSED] drm_test_check_bpc_12_value
[12:01:16] [PASSED] drm_test_check_format_value
[12:01:16] [PASSED] drm_test_check_tmds_char_value
[12:01:16] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[12:01:16] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[12:01:16] [PASSED] drm_test_check_mode_valid
[12:01:16] [PASSED] drm_test_check_mode_valid_reject
[12:01:16] [PASSED] drm_test_check_mode_valid_reject_rate
[12:01:16] [PASSED] drm_test_check_mode_valid_reject_max_clock
[12:01:16] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[12:01:16] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[12:01:16] [PASSED] drm_test_check_infoframes
[12:01:16] [PASSED] drm_test_check_reject_avi_infoframe
[12:01:16] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[12:01:16] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[12:01:16] [PASSED] drm_test_check_reject_audio_infoframe
[12:01:16] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[12:01:16] ================= drm_managed (2 subtests) =================
[12:01:16] [PASSED] drm_test_managed_release_action
[12:01:16] [PASSED] drm_test_managed_run_action
[12:01:16] =================== [PASSED] drm_managed ===================
[12:01:16] =================== drm_mm (6 subtests) ====================
[12:01:16] [PASSED] drm_test_mm_init
[12:01:16] [PASSED] drm_test_mm_debug
[12:01:16] [PASSED] drm_test_mm_align32
[12:01:16] [PASSED] drm_test_mm_align64
[12:01:16] [PASSED] drm_test_mm_lowest
[12:01:16] [PASSED] drm_test_mm_highest
[12:01:16] ===================== [PASSED] drm_mm ======================
[12:01:16] ============= drm_modes_analog_tv (5 subtests) =============
[12:01:16] [PASSED] drm_test_modes_analog_tv_mono_576i
[12:01:16] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[12:01:16] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[12:01:16] [PASSED] drm_test_modes_analog_tv_pal_576i
[12:01:16] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[12:01:16] =============== [PASSED] drm_modes_analog_tv ===============
[12:01:16] ============== drm_plane_helper (2 subtests) ===============
[12:01:16] =============== drm_test_check_plane_state ================
[12:01:16] [PASSED] clipping_simple
[12:01:16] [PASSED] clipping_rotate_reflect
[12:01:16] [PASSED] positioning_simple
[12:01:16] [PASSED] upscaling
[12:01:16] [PASSED] downscaling
[12:01:16] [PASSED] rounding1
[12:01:16] [PASSED] rounding2
[12:01:16] [PASSED] rounding3
[12:01:16] [PASSED] rounding4
[12:01:16] =========== [PASSED] drm_test_check_plane_state ============
[12:01:16] =========== drm_test_check_invalid_plane_state ============
[12:01:16] [PASSED] positioning_invalid
[12:01:16] [PASSED] upscaling_invalid
[12:01:16] [PASSED] downscaling_invalid
[12:01:16] ======= [PASSED] drm_test_check_invalid_plane_state ========
[12:01:16] ================ [PASSED] drm_plane_helper =================
[12:01:16] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[12:01:16] ====== drm_test_connector_helper_tv_get_modes_check =======
[12:01:16] [PASSED] None
[12:01:16] [PASSED] PAL
[12:01:16] [PASSED] NTSC
[12:01:16] [PASSED] Both, NTSC Default
[12:01:16] [PASSED] Both, PAL Default
[12:01:16] [PASSED] Both, NTSC Default, with PAL on command-line
[12:01:16] [PASSED] Both, PAL Default, with NTSC on command-line
[12:01:16] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[12:01:16] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[12:01:16] ================== drm_rect (9 subtests) ===================
[12:01:16] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[12:01:16] [PASSED] drm_test_rect_clip_scaled_not_clipped
[12:01:16] [PASSED] drm_test_rect_clip_scaled_clipped
[12:01:16] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[12:01:16] ================= drm_test_rect_intersect =================
[12:01:16] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[12:01:16] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[12:01:16] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[12:01:16] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[12:01:16] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[12:01:16] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[12:01:16] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[12:01:16] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[12:01:16] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[12:01:16] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[12:01:16] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[12:01:16] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[12:01:16] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[12:01:16] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[12:01:16] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[12:01:16] ============= [PASSED] drm_test_rect_intersect =============
[12:01:16] ================ drm_test_rect_calc_hscale ================
[12:01:16] [PASSED] normal use
[12:01:16] [PASSED] out of max range
[12:01:16] [PASSED] out of min range
[12:01:16] [PASSED] zero dst
[12:01:16] [PASSED] negative src
[12:01:16] [PASSED] negative dst
[12:01:16] ============ [PASSED] drm_test_rect_calc_hscale ============
[12:01:16] ================ drm_test_rect_calc_vscale ================
[12:01:16] [PASSED] normal use
[12:01:16] [PASSED] out of max range
[12:01:16] [PASSED] out of min range
[12:01:16] [PASSED] zero dst
[12:01:16] [PASSED] negative src
[12:01:16] [PASSED] negative dst
[12:01:16] ============ [PASSED] drm_test_rect_calc_vscale ============
[12:01:16] ================== drm_test_rect_rotate ===================
[12:01:16] [PASSED] reflect-x
[12:01:16] [PASSED] reflect-y
[12:01:16] [PASSED] rotate-0
[12:01:16] [PASSED] rotate-90
[12:01:16] [PASSED] rotate-180
[12:01:16] [PASSED] rotate-270
[12:01:16] ============== [PASSED] drm_test_rect_rotate ===============
[12:01:16] ================ drm_test_rect_rotate_inv =================
[12:01:16] [PASSED] reflect-x
[12:01:16] [PASSED] reflect-y
[12:01:16] [PASSED] rotate-0
[12:01:16] [PASSED] rotate-90
[12:01:16] [PASSED] rotate-180
[12:01:16] [PASSED] rotate-270
[12:01:16] ============ [PASSED] drm_test_rect_rotate_inv =============
[12:01:16] ==================== [PASSED] drm_rect =====================
[12:01:16] ============ drm_sysfb_modeset_test (1 subtest) ============
[12:01:16] ============ drm_test_sysfb_build_fourcc_list =============
[12:01:16] [PASSED] no native formats
[12:01:16] [PASSED] XRGB8888 as native format
[12:01:16] [PASSED] remove duplicates
[12:01:16] [PASSED] convert alpha formats
[12:01:16] [PASSED] random formats
[12:01:16] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[12:01:16] ============= [PASSED] drm_sysfb_modeset_test ==============
[12:01:16] ================== drm_fixp (2 subtests) ===================
[12:01:16] [PASSED] drm_test_int2fixp
[12:01:16] [PASSED] drm_test_sm2fixp
[12:01:16] ==================== [PASSED] drm_fixp =====================
[12:01:16] ============================================================
[12:01:16] Testing complete. Ran 621 tests: passed: 621
[12:01:16] Elapsed time: 26.231s total, 1.701s configuring, 24.364s building, 0.134s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[12:01:16] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:01:18] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:01:27] Starting KUnit Kernel (1/1)...
[12:01:27] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:01:28] ================= ttm_device (5 subtests) ==================
[12:01:28] [PASSED] ttm_device_init_basic
[12:01:28] [PASSED] ttm_device_init_multiple
[12:01:28] [PASSED] ttm_device_fini_basic
[12:01:28] [PASSED] ttm_device_init_no_vma_man
[12:01:28] ================== ttm_device_init_pools ==================
[12:01:28] [PASSED] No DMA allocations, no DMA32 required
[12:01:28] [PASSED] DMA allocations, DMA32 required
[12:01:28] [PASSED] No DMA allocations, DMA32 required
[12:01:28] [PASSED] DMA allocations, no DMA32 required
[12:01:28] ============== [PASSED] ttm_device_init_pools ==============
[12:01:28] =================== [PASSED] ttm_device ====================
[12:01:28] ================== ttm_pool (8 subtests) ===================
[12:01:28] ================== ttm_pool_alloc_basic ===================
[12:01:28] [PASSED] One page
[12:01:28] [PASSED] More than one page
[12:01:28] [PASSED] Above the allocation limit
[12:01:28] [PASSED] One page, with coherent DMA mappings enabled
[12:01:28] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:01:28] ============== [PASSED] ttm_pool_alloc_basic ===============
[12:01:28] ============== ttm_pool_alloc_basic_dma_addr ==============
[12:01:28] [PASSED] One page
[12:01:28] [PASSED] More than one page
[12:01:28] [PASSED] Above the allocation limit
[12:01:28] [PASSED] One page, with coherent DMA mappings enabled
[12:01:28] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:01:28] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[12:01:28] [PASSED] ttm_pool_alloc_order_caching_match
[12:01:28] [PASSED] ttm_pool_alloc_caching_mismatch
[12:01:28] [PASSED] ttm_pool_alloc_order_mismatch
[12:01:28] [PASSED] ttm_pool_free_dma_alloc
[12:01:28] [PASSED] ttm_pool_free_no_dma_alloc
[12:01:28] [PASSED] ttm_pool_fini_basic
[12:01:28] ==================== [PASSED] ttm_pool =====================
[12:01:28] ================ ttm_resource (8 subtests) =================
[12:01:28] ================= ttm_resource_init_basic =================
[12:01:28] [PASSED] Init resource in TTM_PL_SYSTEM
[12:01:28] [PASSED] Init resource in TTM_PL_VRAM
[12:01:28] [PASSED] Init resource in a private placement
[12:01:28] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[12:01:28] ============= [PASSED] ttm_resource_init_basic =============
[12:01:28] [PASSED] ttm_resource_init_pinned
[12:01:28] [PASSED] ttm_resource_fini_basic
[12:01:28] [PASSED] ttm_resource_manager_init_basic
[12:01:28] [PASSED] ttm_resource_manager_usage_basic
[12:01:28] [PASSED] ttm_resource_manager_set_used_basic
[12:01:28] [PASSED] ttm_sys_man_alloc_basic
[12:01:28] [PASSED] ttm_sys_man_free_basic
[12:01:28] ================== [PASSED] ttm_resource ===================
[12:01:28] =================== ttm_tt (15 subtests) ===================
[12:01:28] ==================== ttm_tt_init_basic ====================
[12:01:28] [PASSED] Page-aligned size
[12:01:28] [PASSED] Extra pages requested
[12:01:28] ================ [PASSED] ttm_tt_init_basic ================
[12:01:28] [PASSED] ttm_tt_init_misaligned
[12:01:28] [PASSED] ttm_tt_fini_basic
[12:01:28] [PASSED] ttm_tt_fini_sg
[12:01:28] [PASSED] ttm_tt_fini_shmem
[12:01:28] [PASSED] ttm_tt_create_basic
[12:01:28] [PASSED] ttm_tt_create_invalid_bo_type
[12:01:28] [PASSED] ttm_tt_create_ttm_exists
[12:01:28] [PASSED] ttm_tt_create_failed
[12:01:28] [PASSED] ttm_tt_destroy_basic
[12:01:28] [PASSED] ttm_tt_populate_null_ttm
[12:01:28] [PASSED] ttm_tt_populate_populated_ttm
[12:01:28] [PASSED] ttm_tt_unpopulate_basic
[12:01:28] [PASSED] ttm_tt_unpopulate_empty_ttm
[12:01:28] [PASSED] ttm_tt_swapin_basic
[12:01:28] ===================== [PASSED] ttm_tt ======================
[12:01:28] =================== ttm_bo (14 subtests) ===================
[12:01:28] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[12:01:28] [PASSED] Cannot be interrupted and sleeps
[12:01:28] [PASSED] Cannot be interrupted, locks straight away
[12:01:28] [PASSED] Can be interrupted, sleeps
[12:01:28] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[12:01:28] [PASSED] ttm_bo_reserve_locked_no_sleep
[12:01:28] [PASSED] ttm_bo_reserve_no_wait_ticket
[12:01:28] [PASSED] ttm_bo_reserve_double_resv
[12:01:28] [PASSED] ttm_bo_reserve_interrupted
[12:01:28] [PASSED] ttm_bo_reserve_deadlock
[12:01:28] [PASSED] ttm_bo_unreserve_basic
[12:01:28] [PASSED] ttm_bo_unreserve_pinned
[12:01:28] [PASSED] ttm_bo_unreserve_bulk
[12:01:28] [PASSED] ttm_bo_fini_basic
[12:01:28] [PASSED] ttm_bo_fini_shared_resv
[12:01:28] [PASSED] ttm_bo_pin_basic
[12:01:28] [PASSED] ttm_bo_pin_unpin_resource
[12:01:28] [PASSED] ttm_bo_multiple_pin_one_unpin
[12:01:28] ===================== [PASSED] ttm_bo ======================
[12:01:28] ============== ttm_bo_validate (22 subtests) ===============
[12:01:28] ============== ttm_bo_init_reserved_sys_man ===============
[12:01:28] [PASSED] Buffer object for userspace
[12:01:28] [PASSED] Kernel buffer object
[12:01:28] [PASSED] Shared buffer object
[12:01:28] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[12:01:28] ============== ttm_bo_init_reserved_mock_man ==============
[12:01:28] [PASSED] Buffer object for userspace
[12:01:28] [PASSED] Kernel buffer object
[12:01:28] [PASSED] Shared buffer object
[12:01:28] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[12:01:28] [PASSED] ttm_bo_init_reserved_resv
[12:01:28] ================== ttm_bo_validate_basic ==================
[12:01:28] [PASSED] Buffer object for userspace
[12:01:28] [PASSED] Kernel buffer object
[12:01:28] [PASSED] Shared buffer object
[12:01:28] ============== [PASSED] ttm_bo_validate_basic ==============
[12:01:28] [PASSED] ttm_bo_validate_invalid_placement
[12:01:28] ============= ttm_bo_validate_same_placement ==============
[12:01:28] [PASSED] System manager
[12:01:28] [PASSED] VRAM manager
[12:01:28] ========= [PASSED] ttm_bo_validate_same_placement ==========
[12:01:28] [PASSED] ttm_bo_validate_failed_alloc
[12:01:28] [PASSED] ttm_bo_validate_pinned
[12:01:28] [PASSED] ttm_bo_validate_busy_placement
[12:01:28] ================ ttm_bo_validate_multihop =================
[12:01:28] [PASSED] Buffer object for userspace
[12:01:28] [PASSED] Kernel buffer object
[12:01:28] [PASSED] Shared buffer object
[12:01:28] ============ [PASSED] ttm_bo_validate_multihop =============
[12:01:28] ========== ttm_bo_validate_no_placement_signaled ==========
[12:01:28] [PASSED] Buffer object in system domain, no page vector
[12:01:28] [PASSED] Buffer object in system domain with an existing page vector
[12:01:28] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[12:01:28] ======== ttm_bo_validate_no_placement_not_signaled ========
[12:01:28] [PASSED] Buffer object for userspace
[12:01:28] [PASSED] Kernel buffer object
[12:01:28] [PASSED] Shared buffer object
[12:01:28] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[12:01:28] [PASSED] ttm_bo_validate_move_fence_signaled
[12:01:28] ========= ttm_bo_validate_move_fence_not_signaled =========
[12:01:28] [PASSED] Waits for GPU
[12:01:28] [PASSED] Tries to lock straight away
[12:01:28] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[12:01:28] [PASSED] ttm_bo_validate_swapout
[12:01:28] [PASSED] ttm_bo_validate_happy_evict
[12:01:28] [PASSED] ttm_bo_validate_all_pinned_evict
[12:01:28] [PASSED] ttm_bo_validate_allowed_only_evict
[12:01:28] [PASSED] ttm_bo_validate_deleted_evict
[12:01:28] [PASSED] ttm_bo_validate_busy_domain_evict
[12:01:28] [PASSED] ttm_bo_validate_evict_gutting
[12:01:28] [PASSED] ttm_bo_validate_recrusive_evict
[12:01:28] ================= [PASSED] ttm_bo_validate =================
[12:01:28] ============================================================
[12:01:28] Testing complete. Ran 102 tests: passed: 102
[12:01:28] Elapsed time: 11.552s total, 1.731s configuring, 9.556s building, 0.225s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 21+ messages in thread
* ✓ Xe.CI.BAT: success for drm/i915/dp: Sanitize link capability change handling
2026-05-18 11:24 [PATCH 0/5] drm/i915/dp: Sanitize link capability change handling Imre Deak
` (5 preceding siblings ...)
2026-05-18 12:01 ` ✓ CI.KUnit: success for drm/i915/dp: Sanitize link capability change handling Patchwork
@ 2026-05-18 12:41 ` Patchwork
2026-05-18 16:04 ` ✗ Xe.CI.FULL: failure " Patchwork
7 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2026-05-18 12:41 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 967 bytes --]
== Series Details ==
Series: drm/i915/dp: Sanitize link capability change handling
URL : https://patchwork.freedesktop.org/series/166769/
State : success
== Summary ==
CI Bug Log - changes from xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2_BAT -> xe-pw-166769v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2 -> xe-pw-166769v1
IGT_8917: 65d691069f26fc2a42c79e2364241320b85d48bc @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2: 4a64e92e2b244c93c99832a0850204ed2ddca5b2
xe-pw-166769v1: 166769v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/index.html
[-- Attachment #2: Type: text/html, Size: 1515 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* ✗ Xe.CI.FULL: failure for drm/i915/dp: Sanitize link capability change handling
2026-05-18 11:24 [PATCH 0/5] drm/i915/dp: Sanitize link capability change handling Imre Deak
` (6 preceding siblings ...)
2026-05-18 12:41 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-05-18 16:04 ` Patchwork
7 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2026-05-18 16:04 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 17828 bytes --]
== Series Details ==
Series: drm/i915/dp: Sanitize link capability change handling
URL : https://patchwork.freedesktop.org/series/166769/
State : failure
== Summary ==
CI Bug Log - changes from xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2_FULL -> xe-pw-166769v1_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-166769v1_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-166769v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-166769v1_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@xe_exec_system_allocator@process-many-large-malloc-busy-nomemset:
- shard-lnl: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-lnl-2/igt@xe_exec_system_allocator@process-many-large-malloc-busy-nomemset.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-lnl-1/igt@xe_exec_system_allocator@process-many-large-malloc-busy-nomemset.html
Known issues
------------
Here are the changes found in xe-pw-166769v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-lnl: [PASS][3] -> [FAIL][4] ([Intel XE#301]) +1 other test fail
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-lnl: [PASS][5] -> [FAIL][6] ([Intel XE#301] / [Intel XE#3149])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_hdr@invalid-hdr:
- shard-bmg: [PASS][7] -> [SKIP][8] ([Intel XE#1503])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-7/igt@kms_hdr@invalid-hdr.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-4/igt@kms_hdr@invalid-hdr.html
* igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb2101010:
- shard-bmg: [PASS][9] -> [SKIP][10] ([Intel XE#7922]) +1 other test skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-7/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb2101010.html
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-4/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb2101010.html
* igt@kms_hdr@static-toggle-dpms@pipe-a-hdmi-a-3-xrgb2101010:
- shard-bmg: [PASS][11] -> [SKIP][12] ([Intel XE#7915]) +3 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-10/igt@kms_hdr@static-toggle-dpms@pipe-a-hdmi-a-3-xrgb2101010.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-7/igt@kms_hdr@static-toggle-dpms@pipe-a-hdmi-a-3-xrgb2101010.html
* igt@xe_evict@evict-beng-mixed-many-threads-small:
- shard-bmg: [PASS][13] -> [INCOMPLETE][14] ([Intel XE#6321])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-7/igt@xe_evict@evict-beng-mixed-many-threads-small.html
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-9/igt@xe_evict@evict-beng-mixed-many-threads-small.html
* igt@xe_wedged@wedged-mode-toggle:
- shard-bmg: [PASS][15] -> [ABORT][16] ([Intel XE#7914])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-2/igt@xe_wedged@wedged-mode-toggle.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-5/igt@xe_wedged@wedged-mode-toggle.html
#### Possible fixes ####
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-lnl: [FAIL][17] ([Intel XE#301]) -> [PASS][18] +1 other test pass
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@xe_pat@pt-caching-random-offsets:
- shard-bmg: [SKIP][19] ([Intel XE#6703]) -> [PASS][20] +46 other tests pass
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-2/igt@xe_pat@pt-caching-random-offsets.html
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-5/igt@xe_pat@pt-caching-random-offsets.html
* igt@xe_render_copy@render-full-compressed@render-tile64-256x256:
- shard-bmg: [FAIL][21] -> [PASS][22] +5 other tests pass
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-2/igt@xe_render_copy@render-full-compressed@render-tile64-256x256.html
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-5/igt@xe_render_copy@render-full-compressed@render-tile64-256x256.html
#### Warnings ####
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-bmg: [SKIP][23] ([Intel XE#6703]) -> [SKIP][24] ([Intel XE#2370])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-2/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-5/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-90:
- shard-bmg: [SKIP][25] ([Intel XE#6703]) -> [SKIP][26] ([Intel XE#2327])
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-2/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-5/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
* igt@kms_chamelium_color@ctm-green-to-red:
- shard-bmg: [SKIP][27] ([Intel XE#6703]) -> [SKIP][28] ([Intel XE#2325] / [Intel XE#7358])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-2/igt@kms_chamelium_color@ctm-green-to-red.html
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-5/igt@kms_chamelium_color@ctm-green-to-red.html
* igt@kms_cursor_crc@cursor-offscreen-512x512:
- shard-bmg: [SKIP][29] ([Intel XE#6703]) -> [SKIP][30] ([Intel XE#2321] / [Intel XE#7355])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-2/igt@kms_cursor_crc@cursor-offscreen-512x512.html
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-5/igt@kms_cursor_crc@cursor-offscreen-512x512.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-lnl: [FAIL][31] ([Intel XE#301]) -> [FAIL][32] ([Intel XE#301] / [Intel XE#3149])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank.html
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-blt:
- shard-bmg: [SKIP][33] ([Intel XE#6703]) -> [SKIP][34] ([Intel XE#2311]) +4 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-blt.html
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][35] ([Intel XE#6703]) -> [SKIP][36] ([Intel XE#4141])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc.html
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][37] ([Intel XE#6703]) -> [SKIP][38] ([Intel XE#2313]) +3 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-2/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-cur-indfb-draw-mmap-wc.html
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-5/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_plane_lowres@tiling-yf:
- shard-bmg: [SKIP][39] ([Intel XE#6703]) -> [SKIP][40] ([Intel XE#2393])
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-2/igt@kms_plane_lowres@tiling-yf.html
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-5/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_pm_rpm@dpms-mode-unset-lpsp:
- shard-bmg: [SKIP][41] ([Intel XE#6703]) -> [SKIP][42] ([Intel XE#1439] / [Intel XE#7402] / [Intel XE#836])
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-2/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-5/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf:
- shard-bmg: [SKIP][43] ([Intel XE#6703]) -> [SKIP][44] ([Intel XE#1489])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-2/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-5/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-bmg: [SKIP][45] ([Intel XE#6703]) -> [SKIP][46] ([Intel XE#3904] / [Intel XE#7342])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-2/igt@kms_rotation_crc@bad-pixel-format.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-5/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-bmg: [FAIL][47] ([Intel XE#1729] / [Intel XE#7424]) -> [SKIP][48] ([Intel XE#2426] / [Intel XE#5848])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern.html
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-bmg: [SKIP][49] ([Intel XE#2509] / [Intel XE#7437]) -> [SKIP][50] ([Intel XE#2426] / [Intel XE#5848])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr:
- shard-bmg: [SKIP][51] ([Intel XE#6703]) -> [SKIP][52] ([Intel XE#2322] / [Intel XE#7372])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-2/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr.html
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-5/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr.html
* igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate:
- shard-bmg: [SKIP][53] ([Intel XE#6703]) -> [SKIP][54] ([Intel XE#7136])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-2/igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate.html
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-5/igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate.html
* igt@xe_exec_multi_queue@many-queues-userptr:
- shard-bmg: [SKIP][55] ([Intel XE#6703]) -> [SKIP][56] ([Intel XE#6874]) +1 other test skip
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-2/igt@xe_exec_multi_queue@many-queues-userptr.html
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-5/igt@xe_exec_multi_queue@many-queues-userptr.html
* igt@xe_exec_sip_eudebug@breakpoint-writesip-nodebug:
- shard-bmg: [SKIP][57] ([Intel XE#6703]) -> [SKIP][58] ([Intel XE#7636])
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-2/igt@xe_exec_sip_eudebug@breakpoint-writesip-nodebug.html
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-5/igt@xe_exec_sip_eudebug@breakpoint-writesip-nodebug.html
* igt@xe_exec_threads@threads-multi-queue-mixed-fd-userptr-rebind:
- shard-bmg: [SKIP][59] ([Intel XE#6703]) -> [SKIP][60] ([Intel XE#7138])
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-mixed-fd-userptr-rebind.html
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/shard-bmg-5/igt@xe_exec_threads@threads-multi-queue-mixed-fd-userptr-rebind.html
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2370
[Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
[Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
[Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
[Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
[Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
[Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
[Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
[Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
[Intel XE#7402]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7402
[Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
[Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
[Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
[Intel XE#7914]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7914
[Intel XE#7915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7915
[Intel XE#7922]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7922
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
Build changes
-------------
* Linux: xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2 -> xe-pw-166769v1
IGT_8917: 65d691069f26fc2a42c79e2364241320b85d48bc @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-5079-4a64e92e2b244c93c99832a0850204ed2ddca5b2: 4a64e92e2b244c93c99832a0850204ed2ddca5b2
xe-pw-166769v1: 166769v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166769v1/index.html
[-- Attachment #2: Type: text/html, Size: 20589 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/5] drm/i915/dp: Add helpers to reset link params
2026-05-18 11:24 ` [PATCH 1/5] drm/i915/dp: Add helpers to reset link params Imre Deak
@ 2026-05-21 21:36 ` Ville Syrjälä
2026-05-22 7:36 ` Hogander, Jouni
2026-05-22 7:47 ` Imre Deak
0 siblings, 2 replies; 21+ messages in thread
From: Ville Syrjälä @ 2026-05-21 21:36 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx, intel-xe
On Mon, May 18, 2026 at 02:24:22PM +0300, Imre Deak wrote:
> Add helpers to defer and handle link params resets instead of
> open-coding the same. Rename intel_dp_reset_link_params() to
> intel_dp_reset_link_params_force() to align its name with the new
> deferred reset helpers.
>
> When deferring a reset, return whether a new reset was queued, used by a
> follow-up change.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 41 +++++++++++++++----
> drivers/gpu/drm/i915/display/intel_dp.h | 3 +-
> .../drm/i915/display/intel_dp_link_training.c | 4 +-
> 5 files changed, 38 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
> index 5ff1cdf4581a5..c20a97e21419b 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -1265,7 +1265,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
>
> intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
>
> - intel_dp->reset_link_params = true;
> + intel_dp_reset_link_params_defer(intel_dp);
> intel_dp_invalidate_source_oui(intel_dp);
>
> if (display->platform.valleyview || display->platform.cherryview)
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 86520848892e0..77819aaeccb76 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4664,7 +4664,7 @@ static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
> struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
> struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
>
> - intel_dp->reset_link_params = true;
> + intel_dp_reset_link_params_defer(intel_dp);
> intel_dp_invalidate_source_oui(intel_dp);
>
> intel_pps_encoder_reset(intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 1920d2f026665..13163dd085e91 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3710,7 +3710,11 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp,
> intel_dp->lane_count = lane_count;
> }
>
> -void intel_dp_reset_link_params(struct intel_dp *intel_dp)
> +/*
> + * Reset link params now, preserving any deferred connector
> + * detect-time reset request.
> + */
> +void intel_dp_reset_link_params_force(struct intel_dp *intel_dp)
> {
> intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);
> intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
> @@ -3720,6 +3724,28 @@ void intel_dp_reset_link_params(struct intel_dp *intel_dp)
> intel_dp->link.seq_train_failures = 0;
> }
>
> +/*
> + * Reset link params during the next connector detect.
> + * Return %true if a new reset was queued.
> + */
> +bool intel_dp_reset_link_params_defer(struct intel_dp *intel_dp)
I find the intel_dp_reset_link_params_defer() vs.
intel_dp_reset_link_params_force() naming rather confusing.
Can't immediately think of a really good name for
intel_dp_reset_link_params_defer() so maybe it's better to not
have a function for it at all (ie. just drop this patch)? Then
you at least see that it's just setting the flag. AFAICS you
only have a single place (in the last patch) that uses this
return value for anything, so could just do the check+set
dance there on the spot.
> +{
> + bool reset_was_pending = intel_dp->reset_link_params;
> +
> + intel_dp->reset_link_params = true;
> +
> + return !reset_was_pending;
> +}
> +
> +static void intel_dp_handle_deferred_link_params_reset(struct intel_dp *intel_dp)
> +{
> + if (!intel_dp->reset_link_params)
> + return;
> +
> + intel_dp->reset_link_params = false;
> + intel_dp_reset_link_params_force(intel_dp);
> +}
> +
> /* Enable backlight PWM and backlight PP control. */
> void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state)
> @@ -4066,7 +4092,7 @@ void intel_dp_sync_state(struct intel_encoder *encoder,
> intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);
>
> if (crtc_state) {
> - intel_dp_reset_link_params(intel_dp);
> + intel_dp_reset_link_params_force(intel_dp);
> intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count);
> intel_dp->link.active = true;
> }
> @@ -6487,10 +6513,7 @@ intel_dp_detect(struct drm_connector *_connector,
>
> intel_dp_detect_sdp_caps(intel_dp);
>
> - if (intel_dp->reset_link_params) {
> - intel_dp_reset_link_params(intel_dp);
> - intel_dp->reset_link_params = false;
> - }
> + intel_dp_handle_deferred_link_params_reset(intel_dp);
>
> intel_dp_mst_configure(intel_dp);
>
> @@ -6944,7 +6967,7 @@ intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
>
> intel_dp_read_dprx_caps(intel_dp, dpcd);
>
> - intel_dp->reset_link_params = true;
> + intel_dp_reset_link_params_defer(intel_dp);
> intel_dp_invalidate_source_oui(intel_dp);
>
> return IRQ_NONE;
> @@ -7252,7 +7275,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
> encoder->base.name))
> return false;
>
> - intel_dp->reset_link_params = true;
> + intel_dp_reset_link_params_defer(intel_dp);
>
> /* Preserve the current hw state. */
> intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
> @@ -7317,7 +7340,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
>
> intel_dp_set_source_rates(intel_dp);
> intel_dp_set_common_rates(intel_dp);
> - intel_dp_reset_link_params(intel_dp);
> + intel_dp_reset_link_params_force(intel_dp);
>
> /* init MST on ports that can support it */
> intel_dp_mst_encoder_init(dig_port, connector->base.base.id);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index f41480d247142..7c24d3dbb6983 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -114,7 +114,8 @@ int intel_dp_rate_index(const int *rates, int len, int rate);
> int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count);
> void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count);
> void intel_dp_update_sink_caps(struct intel_dp *intel_dp);
> -void intel_dp_reset_link_params(struct intel_dp *intel_dp);
> +void intel_dp_reset_link_params_force(struct intel_dp *intel_dp);
> +bool intel_dp_reset_link_params_defer(struct intel_dp *intel_dp);
>
> void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
> u8 *link_bw, u8 *rate_select);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index a26094223f780..b7075060e7bd3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -1935,7 +1935,7 @@ static ssize_t i915_dp_force_link_rate_write(struct file *file,
> if (err)
> return err;
>
> - intel_dp_reset_link_params(intel_dp);
> + intel_dp_reset_link_params_force(intel_dp);
> intel_dp->link.force_rate = rate;
>
> drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
> @@ -2037,7 +2037,7 @@ static ssize_t i915_dp_force_lane_count_write(struct file *file,
> if (err)
> return err;
>
> - intel_dp_reset_link_params(intel_dp);
> + intel_dp_reset_link_params_force(intel_dp);
> intel_dp->link.force_lane_count = lane_count;
>
> drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
> --
> 2.49.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 5/5] drm/i915/dp: Detect changes in common link parameters
2026-05-18 11:24 ` [PATCH 5/5] drm/i915/dp: Detect changes in common link parameters Imre Deak
@ 2026-05-21 21:43 ` Ville Syrjälä
2026-05-22 7:54 ` Imre Deak
0 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjälä @ 2026-05-21 21:43 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx, intel-xe
On Mon, May 18, 2026 at 02:24:26PM +0300, Imre Deak wrote:
> Detect DPRX capability changes without a long HPD or RX_CAP_CHANGED
> signal and queue a corresponding link params reset.
>
> Besides detecting the above unexpected capability changes, this also
> avoids races between queuing and handling a deferred link params reset.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 50 +++++++++++++++++++++----
> 1 file changed, 43 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 6c4dadfc35806..dd968c2d9fa64 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -362,19 +362,25 @@ int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
> return max_lanes;
> }
>
> -/* Theoretical max between source and sink */
> -static void intel_dp_set_max_common_lane_count(struct intel_dp *intel_dp)
> +/*
> + * Theoretical max between source and sink.
> + * Return %true if the max common lane count changed.
> + */
> +static bool intel_dp_set_max_common_lane_count(struct intel_dp *intel_dp)
> {
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> int source_max = intel_dp_max_source_lane_count(dig_port);
> int sink_max = intel_dp->max_sink_lane_count;
> int lane_max = intel_tc_port_max_lane_count(dig_port);
> int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
> + int old_max_common_lane_count = intel_dp->max_common_lane_count;
>
> if (lttpr_max)
> sink_max = min(sink_max, lttpr_max);
>
> intel_dp->max_common_lane_count = min3(source_max, sink_max, lane_max);
> +
> + return intel_dp->max_common_lane_count != old_max_common_lane_count;
> }
>
> int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
> @@ -792,13 +798,20 @@ int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lan
> return -1;
> }
>
> -static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
> +/* Return %true if the common rates changed. */
> +static bool intel_dp_set_common_rates(struct intel_dp *intel_dp)
> {
> struct intel_display *display = to_intel_display(intel_dp);
> + int num_old_common_rates = intel_dp->num_common_rates;
> + int old_common_rates[DP_MAX_SUPPORTED_RATES];
>
> drm_WARN_ON(display->drm,
> !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
>
> + static_assert(sizeof(old_common_rates) == sizeof(intel_dp->common_rates));
Could also assert the element size/type match. Maybe (as a followup
later) introduce a proper type for this rates[]+num construct and then
we could just copy the darn thing with a normal assignment and not have
to worry about this kind of stuff at all...
> + memcpy(old_common_rates, intel_dp->common_rates,
> + num_old_common_rates * sizeof(old_common_rates[0]));
> +
> intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
> intel_dp->num_source_rates,
> intel_dp->sink_rates,
> @@ -810,13 +823,26 @@ static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
> intel_dp->common_rates[0] = 162000;
> intel_dp->num_common_rates = 1;
> }
> +
> + return num_old_common_rates != intel_dp->num_common_rates ||
> + memcmp(old_common_rates, intel_dp->common_rates,
> + num_old_common_rates * sizeof(old_common_rates[0]));
> }
>
> -static void intel_dp_set_common_link_params(struct intel_dp *intel_dp)
> +/* Return %true if any common link param changed. */
> +static bool intel_dp_set_common_link_params(struct intel_dp *intel_dp)
> {
> - intel_dp_set_common_rates(intel_dp);
> - intel_dp_set_max_common_lane_count(intel_dp);
> + bool params_changed = false;
> +
> + if (intel_dp_set_common_rates(intel_dp))
> + params_changed = true;
> +
> + if (intel_dp_set_max_common_lane_count(intel_dp))
> + params_changed = true;
> +
> intel_dp_link_config_init(intel_dp);
> +
> + return params_changed;
> }
>
> bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
> @@ -4911,9 +4937,19 @@ intel_dp_has_sink_count(struct intel_dp *intel_dp)
>
> void intel_dp_update_sink_caps(struct intel_dp *intel_dp)
> {
> + struct intel_display *display = to_intel_display(intel_dp);
> +
> intel_dp_set_sink_rates(intel_dp);
> intel_dp_set_max_sink_lane_count(intel_dp);
> - intel_dp_set_common_link_params(intel_dp);
> + /*
> + * Handle unexpected sink cap changes, or a race between setting
> + * the deferred link params flag in the HPD IRQ handler and
> + * clearing the flag during connector detect.
> + */
> + if (intel_dp_set_common_link_params(intel_dp) &&
> + intel_dp_reset_link_params_defer(intel_dp))
> + drm_dbg_kms(display->drm,
> + "DPRX capabilities changed before long HPD or RX_CAP_CHANGED signal\n");
> }
>
> static bool
> --
> 2.49.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 3/5] drm/i915/dp: Add helper to set common link params
2026-05-18 11:24 ` [PATCH 3/5] drm/i915/dp: Add helper to set common link params Imre Deak
@ 2026-05-22 7:20 ` Hogander, Jouni
0 siblings, 0 replies; 21+ messages in thread
From: Hogander, Jouni @ 2026-05-22 7:20 UTC (permalink / raw)
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
Deak, Imre
On Mon, 2026-05-18 at 14:24 +0300, Imre Deak wrote:
> Add intel_dp_set_common_link_params() to prepare for updating the
> maximum common lane count together with the common rates.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9c530ef12b7cc..06bf1fb23faff 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -805,7 +805,11 @@ static void intel_dp_set_common_rates(struct
> intel_dp *intel_dp)
> intel_dp->common_rates[0] = 162000;
> intel_dp->num_common_rates = 1;
> }
> +}
>
> +static void intel_dp_set_common_link_params(struct intel_dp
> *intel_dp)
> +{
> + intel_dp_set_common_rates(intel_dp);
> intel_dp_link_config_init(intel_dp);
> }
>
> @@ -4903,7 +4907,7 @@ void intel_dp_update_sink_caps(struct intel_dp
> *intel_dp)
> {
> intel_dp_set_sink_rates(intel_dp);
> intel_dp_set_max_sink_lane_count(intel_dp);
> - intel_dp_set_common_rates(intel_dp);
> + intel_dp_set_common_link_params(intel_dp);
> }
>
> static bool
> @@ -7341,7 +7345,7 @@ intel_dp_init_connector(struct
> intel_digital_port *dig_port,
> }
>
> intel_dp_set_source_rates(intel_dp);
> - intel_dp_set_common_rates(intel_dp);
> + intel_dp_set_common_link_params(intel_dp);
> intel_dp_reset_link_params_force(intel_dp);
>
> /* init MST on ports that can support it */
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 4/5] drm/i915/dp: Cache max common lane count
2026-05-18 11:24 ` [PATCH 4/5] drm/i915/dp: Cache max common lane count Imre Deak
@ 2026-05-22 7:21 ` Hogander, Jouni
0 siblings, 0 replies; 21+ messages in thread
From: Hogander, Jouni @ 2026-05-22 7:21 UTC (permalink / raw)
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
Deak, Imre
On Mon, 2026-05-18 at 14:24 +0300, Imre Deak wrote:
> Cache the maximum common lane count together with the common link
> rates.
>
> This is safe because the cached value is updated:
> - during driver probe, before the connector is registered and can be
> used for mode validation or modesetting
> - during resume, before output HW state readout can query it
> - during connector detection, right after updating the sink/link
> capabilities
>
> Caching the value allows detecting max common lane count changes in
> a follow-up change and keeps the tracking of max common lane count
> aligned with that of common rates.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++++++--
> 2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index f44be5c689aef..c3811242310c8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1820,6 +1820,7 @@ struct intel_dp {
> /* intersection of source and sink rates */
> int num_common_rates;
> int common_rates[DP_MAX_SUPPORTED_RATES];
> + int max_common_lane_count;
> struct {
> /* TODO: move the rest of link specific fields to
> here */
> bool active;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 06bf1fb23faff..6c4dadfc35806 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -363,7 +363,7 @@ int intel_dp_max_source_lane_count(struct
> intel_digital_port *dig_port)
> }
>
> /* Theoretical max between source and sink */
> -int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
> +static void intel_dp_set_max_common_lane_count(struct intel_dp
> *intel_dp)
> {
> struct intel_digital_port *dig_port =
> dp_to_dig_port(intel_dp);
> int source_max = intel_dp_max_source_lane_count(dig_port);
> @@ -374,7 +374,12 @@ int intel_dp_max_common_lane_count(struct
> intel_dp *intel_dp)
> if (lttpr_max)
> sink_max = min(sink_max, lttpr_max);
>
> - return min3(source_max, sink_max, lane_max);
> + intel_dp->max_common_lane_count = min3(source_max, sink_max,
> lane_max);
> +}
> +
> +int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
> +{
> + return intel_dp->max_common_lane_count;
> }
>
> static int forced_lane_count(struct intel_dp *intel_dp)
> @@ -810,6 +815,7 @@ static void intel_dp_set_common_rates(struct
> intel_dp *intel_dp)
> static void intel_dp_set_common_link_params(struct intel_dp
> *intel_dp)
> {
> intel_dp_set_common_rates(intel_dp);
> + intel_dp_set_max_common_lane_count(intel_dp);
> intel_dp_link_config_init(intel_dp);
> }
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/5] drm/i915/dp: Add helpers to reset link params
2026-05-21 21:36 ` Ville Syrjälä
@ 2026-05-22 7:36 ` Hogander, Jouni
2026-05-22 7:47 ` Imre Deak
1 sibling, 0 replies; 21+ messages in thread
From: Hogander, Jouni @ 2026-05-22 7:36 UTC (permalink / raw)
To: ville.syrjala@linux.intel.com, Deak, Imre
Cc: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
On Fri, 2026-05-22 at 00:36 +0300, Ville Syrjälä wrote:
> On Mon, May 18, 2026 at 02:24:22PM +0300, Imre Deak wrote:
> > Add helpers to defer and handle link params resets instead of
> > open-coding the same. Rename intel_dp_reset_link_params() to
> > intel_dp_reset_link_params_force() to align its name with the new
> > deferred reset helpers.
> >
> > When deferring a reset, return whether a new reset was queued, used
> > by a
> > follow-up change.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_dp.c | 41
> > +++++++++++++++----
> > drivers/gpu/drm/i915/display/intel_dp.h | 3 +-
> > .../drm/i915/display/intel_dp_link_training.c | 4 +-
> > 5 files changed, 38 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
> > b/drivers/gpu/drm/i915/display/g4x_dp.c
> > index 5ff1cdf4581a5..c20a97e21419b 100644
> > --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> > @@ -1265,7 +1265,7 @@ static void intel_dp_encoder_reset(struct
> > drm_encoder *encoder)
> >
> > intel_dp->DP = intel_de_read(display, intel_dp-
> > >output_reg);
> >
> > - intel_dp->reset_link_params = true;
> > + intel_dp_reset_link_params_defer(intel_dp);
> > intel_dp_invalidate_source_oui(intel_dp);
> >
> > if (display->platform.valleyview || display-
> > >platform.cherryview)
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 86520848892e0..77819aaeccb76 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4664,7 +4664,7 @@ static void intel_ddi_encoder_reset(struct
> > drm_encoder *encoder)
> > struct intel_dp *intel_dp =
> > enc_to_intel_dp(to_intel_encoder(encoder));
> > struct intel_digital_port *dig_port =
> > enc_to_dig_port(to_intel_encoder(encoder));
> >
> > - intel_dp->reset_link_params = true;
> > + intel_dp_reset_link_params_defer(intel_dp);
> > intel_dp_invalidate_source_oui(intel_dp);
> >
> > intel_pps_encoder_reset(intel_dp);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 1920d2f026665..13163dd085e91 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -3710,7 +3710,11 @@ void intel_dp_set_link_params(struct
> > intel_dp *intel_dp,
> > intel_dp->lane_count = lane_count;
> > }
> >
> > -void intel_dp_reset_link_params(struct intel_dp *intel_dp)
> > +/*
> > + * Reset link params now, preserving any deferred connector
> > + * detect-time reset request.
> > + */
> > +void intel_dp_reset_link_params_force(struct intel_dp *intel_dp)
> > {
> > intel_dp->link.max_lane_count =
> > intel_dp_max_common_lane_count(intel_dp);
> > intel_dp->link.max_rate =
> > intel_dp_max_common_rate(intel_dp);
> > @@ -3720,6 +3724,28 @@ void intel_dp_reset_link_params(struct
> > intel_dp *intel_dp)
> > intel_dp->link.seq_train_failures = 0;
> > }
> >
> > +/*
> > + * Reset link params during the next connector detect.
> > + * Return %true if a new reset was queued.
> > + */
> > +bool intel_dp_reset_link_params_defer(struct intel_dp *intel_dp)
>
> I find the intel_dp_reset_link_params_defer() vs.
> intel_dp_reset_link_params_force() naming rather confusing.
>
> Can't immediately think of a really good name for
> intel_dp_reset_link_params_defer() so maybe it's better to not
> have a function for it at all (ie. just drop this patch)? Then
> you at least see that it's just setting the flag. AFAICS you
> only have a single place (in the last patch) that uses this
> return value for anything, so could just do the check+set
> dance there on the spot.
I found naming here also a bit confusing. Maybe:
intel_dp_link_params_reset
intel_dp_link_params_reset_request
intel_dp_handle_link_params_reset_request
BR,
Jouni Högander
>
> > +{
> > + bool reset_was_pending = intel_dp->reset_link_params;
> > +
> > + intel_dp->reset_link_params = true;
> > +
> > + return !reset_was_pending;
> > +}
> > +
> > +static void intel_dp_handle_deferred_link_params_reset(struct
> > intel_dp *intel_dp)
> > +{
> > + if (!intel_dp->reset_link_params)
> > + return;
> > +
> > + intel_dp->reset_link_params = false;
> > + intel_dp_reset_link_params_force(intel_dp);
> > +}
> > +
> > /* Enable backlight PWM and backlight PP control. */
> > void intel_edp_backlight_on(const struct intel_crtc_state
> > *crtc_state,
> > const struct drm_connector_state
> > *conn_state)
> > @@ -4066,7 +4092,7 @@ void intel_dp_sync_state(struct intel_encoder
> > *encoder,
> > intel_dp_tunnel_resume(intel_dp, crtc_state,
> > dpcd_updated);
> >
> > if (crtc_state) {
> > - intel_dp_reset_link_params(intel_dp);
> > + intel_dp_reset_link_params_force(intel_dp);
> > intel_dp_set_link_params(intel_dp, crtc_state-
> > >port_clock, crtc_state->lane_count);
> > intel_dp->link.active = true;
> > }
> > @@ -6487,10 +6513,7 @@ intel_dp_detect(struct drm_connector
> > *_connector,
> >
> > intel_dp_detect_sdp_caps(intel_dp);
> >
> > - if (intel_dp->reset_link_params) {
> > - intel_dp_reset_link_params(intel_dp);
> > - intel_dp->reset_link_params = false;
> > - }
> > + intel_dp_handle_deferred_link_params_reset(intel_dp);
> >
> > intel_dp_mst_configure(intel_dp);
> >
> > @@ -6944,7 +6967,7 @@ intel_dp_hpd_pulse(struct intel_digital_port
> > *dig_port, bool long_hpd)
> >
> > intel_dp_read_dprx_caps(intel_dp, dpcd);
> >
> > - intel_dp->reset_link_params = true;
> > + intel_dp_reset_link_params_defer(intel_dp);
> > intel_dp_invalidate_source_oui(intel_dp);
> >
> > return IRQ_NONE;
> > @@ -7252,7 +7275,7 @@ intel_dp_init_connector(struct
> > intel_digital_port *dig_port,
> > encoder->base.name))
> > return false;
> >
> > - intel_dp->reset_link_params = true;
> > + intel_dp_reset_link_params_defer(intel_dp);
> >
> > /* Preserve the current hw state. */
> > intel_dp->DP = intel_de_read(display, intel_dp-
> > >output_reg);
> > @@ -7317,7 +7340,7 @@ intel_dp_init_connector(struct
> > intel_digital_port *dig_port,
> >
> > intel_dp_set_source_rates(intel_dp);
> > intel_dp_set_common_rates(intel_dp);
> > - intel_dp_reset_link_params(intel_dp);
> > + intel_dp_reset_link_params_force(intel_dp);
> >
> > /* init MST on ports that can support it */
> > intel_dp_mst_encoder_init(dig_port, connector-
> > >base.base.id);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> > b/drivers/gpu/drm/i915/display/intel_dp.h
> > index f41480d247142..7c24d3dbb6983 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -114,7 +114,8 @@ int intel_dp_rate_index(const int *rates, int
> > len, int rate);
> > int intel_dp_link_config_index(struct intel_dp *intel_dp, int
> > link_rate, int lane_count);
> > void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx,
> > int *link_rate, int *lane_count);
> > void intel_dp_update_sink_caps(struct intel_dp *intel_dp);
> > -void intel_dp_reset_link_params(struct intel_dp *intel_dp);
> > +void intel_dp_reset_link_params_force(struct intel_dp *intel_dp);
> > +bool intel_dp_reset_link_params_defer(struct intel_dp *intel_dp);
> >
> > void intel_dp_compute_rate(struct intel_dp *intel_dp, int
> > port_clock,
> > u8 *link_bw, u8 *rate_select);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > index a26094223f780..b7075060e7bd3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > @@ -1935,7 +1935,7 @@ static ssize_t
> > i915_dp_force_link_rate_write(struct file *file,
> > if (err)
> > return err;
> >
> > - intel_dp_reset_link_params(intel_dp);
> > + intel_dp_reset_link_params_force(intel_dp);
> > intel_dp->link.force_rate = rate;
> >
> > drm_modeset_unlock(&display->drm-
> > >mode_config.connection_mutex);
> > @@ -2037,7 +2037,7 @@ static ssize_t
> > i915_dp_force_lane_count_write(struct file *file,
> > if (err)
> > return err;
> >
> > - intel_dp_reset_link_params(intel_dp);
> > + intel_dp_reset_link_params_force(intel_dp);
> > intel_dp->link.force_lane_count = lane_count;
> >
> > drm_modeset_unlock(&display->drm-
> > >mode_config.connection_mutex);
> > --
> > 2.49.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/5] drm/i915/dp: Add helpers to reset link params
2026-05-21 21:36 ` Ville Syrjälä
2026-05-22 7:36 ` Hogander, Jouni
@ 2026-05-22 7:47 ` Imre Deak
2026-05-22 10:29 ` Jani Nikula
1 sibling, 1 reply; 21+ messages in thread
From: Imre Deak @ 2026-05-22 7:47 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Jouni Hogander, intel-gfx, intel-xe
On Fri, May 22, 2026 at 12:36:27AM +0300, Ville Syrjälä wrote:
> On Mon, May 18, 2026 at 02:24:22PM +0300, Imre Deak wrote:
> > Add helpers to defer and handle link params resets instead of
> > open-coding the same. Rename intel_dp_reset_link_params() to
> > intel_dp_reset_link_params_force() to align its name with the new
> > deferred reset helpers.
> >
> > When deferring a reset, return whether a new reset was queued, used by a
> > follow-up change.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_dp.c | 41 +++++++++++++++----
> > drivers/gpu/drm/i915/display/intel_dp.h | 3 +-
> > .../drm/i915/display/intel_dp_link_training.c | 4 +-
> > 5 files changed, 38 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
> > index 5ff1cdf4581a5..c20a97e21419b 100644
> > --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> > @@ -1265,7 +1265,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
> >
> > intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
> >
> > - intel_dp->reset_link_params = true;
> > + intel_dp_reset_link_params_defer(intel_dp);
> > intel_dp_invalidate_source_oui(intel_dp);
> >
> > if (display->platform.valleyview || display->platform.cherryview)
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 86520848892e0..77819aaeccb76 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4664,7 +4664,7 @@ static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
> > struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
> > struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
> >
> > - intel_dp->reset_link_params = true;
> > + intel_dp_reset_link_params_defer(intel_dp);
> > intel_dp_invalidate_source_oui(intel_dp);
> >
> > intel_pps_encoder_reset(intel_dp);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 1920d2f026665..13163dd085e91 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -3710,7 +3710,11 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp,
> > intel_dp->lane_count = lane_count;
> > }
> >
> > -void intel_dp_reset_link_params(struct intel_dp *intel_dp)
> > +/*
> > + * Reset link params now, preserving any deferred connector
> > + * detect-time reset request.
> > + */
> > +void intel_dp_reset_link_params_force(struct intel_dp *intel_dp)
> > {
> > intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);
> > intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
> > @@ -3720,6 +3724,28 @@ void intel_dp_reset_link_params(struct intel_dp *intel_dp)
> > intel_dp->link.seq_train_failures = 0;
> > }
> >
> > +/*
> > + * Reset link params during the next connector detect.
> > + * Return %true if a new reset was queued.
> > + */
> > +bool intel_dp_reset_link_params_defer(struct intel_dp *intel_dp)
>
> I find the intel_dp_reset_link_params_defer() vs.
> intel_dp_reset_link_params_force() naming rather confusing.
>
> Can't immediately think of a really good name for
> intel_dp_reset_link_params_defer() so maybe it's better to not
> have a function for it at all (ie. just drop this patch)?
The idea was to have an interface to reset the link params directly or
in a deferred way, instead of a direct access of the flag.
The names are not great yes. I could use what Jouni suggested instead,
or if the above argument is not good enough I can also drop this patch.
> Then you at least see that it's just setting the flag. AFAICS you only
> have a single place (in the last patch) that uses this return value
> for anything, so could just do the check+set dance there on the spot.
>
> > +{
> > + bool reset_was_pending = intel_dp->reset_link_params;
> > +
> > + intel_dp->reset_link_params = true;
> > +
> > + return !reset_was_pending;
> > +}
> > +
> > +static void intel_dp_handle_deferred_link_params_reset(struct intel_dp *intel_dp)
> > +{
> > + if (!intel_dp->reset_link_params)
> > + return;
> > +
> > + intel_dp->reset_link_params = false;
> > + intel_dp_reset_link_params_force(intel_dp);
> > +}
> > +
> > /* Enable backlight PWM and backlight PP control. */
> > void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
> > const struct drm_connector_state *conn_state)
> > @@ -4066,7 +4092,7 @@ void intel_dp_sync_state(struct intel_encoder *encoder,
> > intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);
> >
> > if (crtc_state) {
> > - intel_dp_reset_link_params(intel_dp);
> > + intel_dp_reset_link_params_force(intel_dp);
> > intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count);
> > intel_dp->link.active = true;
> > }
> > @@ -6487,10 +6513,7 @@ intel_dp_detect(struct drm_connector *_connector,
> >
> > intel_dp_detect_sdp_caps(intel_dp);
> >
> > - if (intel_dp->reset_link_params) {
> > - intel_dp_reset_link_params(intel_dp);
> > - intel_dp->reset_link_params = false;
> > - }
> > + intel_dp_handle_deferred_link_params_reset(intel_dp);
> >
> > intel_dp_mst_configure(intel_dp);
> >
> > @@ -6944,7 +6967,7 @@ intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
> >
> > intel_dp_read_dprx_caps(intel_dp, dpcd);
> >
> > - intel_dp->reset_link_params = true;
> > + intel_dp_reset_link_params_defer(intel_dp);
> > intel_dp_invalidate_source_oui(intel_dp);
> >
> > return IRQ_NONE;
> > @@ -7252,7 +7275,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
> > encoder->base.name))
> > return false;
> >
> > - intel_dp->reset_link_params = true;
> > + intel_dp_reset_link_params_defer(intel_dp);
> >
> > /* Preserve the current hw state. */
> > intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
> > @@ -7317,7 +7340,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
> >
> > intel_dp_set_source_rates(intel_dp);
> > intel_dp_set_common_rates(intel_dp);
> > - intel_dp_reset_link_params(intel_dp);
> > + intel_dp_reset_link_params_force(intel_dp);
> >
> > /* init MST on ports that can support it */
> > intel_dp_mst_encoder_init(dig_port, connector->base.base.id);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> > index f41480d247142..7c24d3dbb6983 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -114,7 +114,8 @@ int intel_dp_rate_index(const int *rates, int len, int rate);
> > int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count);
> > void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count);
> > void intel_dp_update_sink_caps(struct intel_dp *intel_dp);
> > -void intel_dp_reset_link_params(struct intel_dp *intel_dp);
> > +void intel_dp_reset_link_params_force(struct intel_dp *intel_dp);
> > +bool intel_dp_reset_link_params_defer(struct intel_dp *intel_dp);
> >
> > void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
> > u8 *link_bw, u8 *rate_select);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > index a26094223f780..b7075060e7bd3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > @@ -1935,7 +1935,7 @@ static ssize_t i915_dp_force_link_rate_write(struct file *file,
> > if (err)
> > return err;
> >
> > - intel_dp_reset_link_params(intel_dp);
> > + intel_dp_reset_link_params_force(intel_dp);
> > intel_dp->link.force_rate = rate;
> >
> > drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
> > @@ -2037,7 +2037,7 @@ static ssize_t i915_dp_force_lane_count_write(struct file *file,
> > if (err)
> > return err;
> >
> > - intel_dp_reset_link_params(intel_dp);
> > + intel_dp_reset_link_params_force(intel_dp);
> > intel_dp->link.force_lane_count = lane_count;
> >
> > drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
> > --
> > 2.49.1
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 5/5] drm/i915/dp: Detect changes in common link parameters
2026-05-21 21:43 ` Ville Syrjälä
@ 2026-05-22 7:54 ` Imre Deak
0 siblings, 0 replies; 21+ messages in thread
From: Imre Deak @ 2026-05-22 7:54 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe
On Fri, May 22, 2026 at 12:43:41AM +0300, Ville Syrjälä wrote:
> On Mon, May 18, 2026 at 02:24:26PM +0300, Imre Deak wrote:
> > Detect DPRX capability changes without a long HPD or RX_CAP_CHANGED
> > signal and queue a corresponding link params reset.
> >
> > Besides detecting the above unexpected capability changes, this also
> > avoids races between queuing and handling a deferred link params reset.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 50 +++++++++++++++++++++----
> > 1 file changed, 43 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 6c4dadfc35806..dd968c2d9fa64 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -362,19 +362,25 @@ int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
> > return max_lanes;
> > }
> >
> > -/* Theoretical max between source and sink */
> > -static void intel_dp_set_max_common_lane_count(struct intel_dp *intel_dp)
> > +/*
> > + * Theoretical max between source and sink.
> > + * Return %true if the max common lane count changed.
> > + */
> > +static bool intel_dp_set_max_common_lane_count(struct intel_dp *intel_dp)
> > {
> > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > int source_max = intel_dp_max_source_lane_count(dig_port);
> > int sink_max = intel_dp->max_sink_lane_count;
> > int lane_max = intel_tc_port_max_lane_count(dig_port);
> > int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
> > + int old_max_common_lane_count = intel_dp->max_common_lane_count;
> >
> > if (lttpr_max)
> > sink_max = min(sink_max, lttpr_max);
> >
> > intel_dp->max_common_lane_count = min3(source_max, sink_max, lane_max);
> > +
> > + return intel_dp->max_common_lane_count != old_max_common_lane_count;
> > }
> >
> > int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
> > @@ -792,13 +798,20 @@ int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lan
> > return -1;
> > }
> >
> > -static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
> > +/* Return %true if the common rates changed. */
> > +static bool intel_dp_set_common_rates(struct intel_dp *intel_dp)
> > {
> > struct intel_display *display = to_intel_display(intel_dp);
> > + int num_old_common_rates = intel_dp->num_common_rates;
> > + int old_common_rates[DP_MAX_SUPPORTED_RATES];
> >
> > drm_WARN_ON(display->drm,
> > !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
> >
> > + static_assert(sizeof(old_common_rates) == sizeof(intel_dp->common_rates));
>
> Could also assert the element size/type match. Maybe (as a followup
> later) introduce a proper type for this rates[]+num construct and then
> we could just copy the darn thing with a normal assignment and not have
> to worry about this kind of stuff at all...
Yes, makes sense. I'd have to pass common rates to
intel_dp_link_config_init() later (in the link capability refactor
patchset), so could do what you suggest at that point.
The struct could be used then for source and sink rates as well.
>
> > + memcpy(old_common_rates, intel_dp->common_rates,
> > + num_old_common_rates * sizeof(old_common_rates[0]));
> > +
> > intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
> > intel_dp->num_source_rates,
> > intel_dp->sink_rates,
> > @@ -810,13 +823,26 @@ static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
> > intel_dp->common_rates[0] = 162000;
> > intel_dp->num_common_rates = 1;
> > }
> > +
> > + return num_old_common_rates != intel_dp->num_common_rates ||
> > + memcmp(old_common_rates, intel_dp->common_rates,
> > + num_old_common_rates * sizeof(old_common_rates[0]));
> > }
> >
> > -static void intel_dp_set_common_link_params(struct intel_dp *intel_dp)
> > +/* Return %true if any common link param changed. */
> > +static bool intel_dp_set_common_link_params(struct intel_dp *intel_dp)
> > {
> > - intel_dp_set_common_rates(intel_dp);
> > - intel_dp_set_max_common_lane_count(intel_dp);
> > + bool params_changed = false;
> > +
> > + if (intel_dp_set_common_rates(intel_dp))
> > + params_changed = true;
> > +
> > + if (intel_dp_set_max_common_lane_count(intel_dp))
> > + params_changed = true;
> > +
> > intel_dp_link_config_init(intel_dp);
> > +
> > + return params_changed;
> > }
> >
> > bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
> > @@ -4911,9 +4937,19 @@ intel_dp_has_sink_count(struct intel_dp *intel_dp)
> >
> > void intel_dp_update_sink_caps(struct intel_dp *intel_dp)
> > {
> > + struct intel_display *display = to_intel_display(intel_dp);
> > +
> > intel_dp_set_sink_rates(intel_dp);
> > intel_dp_set_max_sink_lane_count(intel_dp);
> > - intel_dp_set_common_link_params(intel_dp);
> > + /*
> > + * Handle unexpected sink cap changes, or a race between setting
> > + * the deferred link params flag in the HPD IRQ handler and
> > + * clearing the flag during connector detect.
> > + */
> > + if (intel_dp_set_common_link_params(intel_dp) &&
> > + intel_dp_reset_link_params_defer(intel_dp))
> > + drm_dbg_kms(display->drm,
> > + "DPRX capabilities changed before long HPD or RX_CAP_CHANGED signal\n");
> > }
> >
> > static bool
> > --
> > 2.49.1
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/5] drm/i915/dp: Add helpers to reset link params
2026-05-22 7:47 ` Imre Deak
@ 2026-05-22 10:29 ` Jani Nikula
2026-05-22 12:39 ` Ville Syrjälä
0 siblings, 1 reply; 21+ messages in thread
From: Jani Nikula @ 2026-05-22 10:29 UTC (permalink / raw)
To: imre.deak, Ville Syrjälä; +Cc: Jouni Hogander, intel-gfx, intel-xe
On Fri, 22 May 2026, Imre Deak <imre.deak@intel.com> wrote:
> On Fri, May 22, 2026 at 12:36:27AM +0300, Ville Syrjälä wrote:
>> On Mon, May 18, 2026 at 02:24:22PM +0300, Imre Deak wrote:
>> > Add helpers to defer and handle link params resets instead of
>> > open-coding the same. Rename intel_dp_reset_link_params() to
>> > intel_dp_reset_link_params_force() to align its name with the new
>> > deferred reset helpers.
>> >
>> > When deferring a reset, return whether a new reset was queued, used by a
>> > follow-up change.
>> >
>> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
>> > drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
>> > drivers/gpu/drm/i915/display/intel_dp.c | 41 +++++++++++++++----
>> > drivers/gpu/drm/i915/display/intel_dp.h | 3 +-
>> > .../drm/i915/display/intel_dp_link_training.c | 4 +-
>> > 5 files changed, 38 insertions(+), 14 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
>> > index 5ff1cdf4581a5..c20a97e21419b 100644
>> > --- a/drivers/gpu/drm/i915/display/g4x_dp.c
>> > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
>> > @@ -1265,7 +1265,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
>> >
>> > intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
>> >
>> > - intel_dp->reset_link_params = true;
>> > + intel_dp_reset_link_params_defer(intel_dp);
>> > intel_dp_invalidate_source_oui(intel_dp);
>> >
>> > if (display->platform.valleyview || display->platform.cherryview)
>> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>> > index 86520848892e0..77819aaeccb76 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> > @@ -4664,7 +4664,7 @@ static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
>> > struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
>> > struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
>> >
>> > - intel_dp->reset_link_params = true;
>> > + intel_dp_reset_link_params_defer(intel_dp);
>> > intel_dp_invalidate_source_oui(intel_dp);
>> >
>> > intel_pps_encoder_reset(intel_dp);
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> > index 1920d2f026665..13163dd085e91 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> > @@ -3710,7 +3710,11 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp,
>> > intel_dp->lane_count = lane_count;
>> > }
>> >
>> > -void intel_dp_reset_link_params(struct intel_dp *intel_dp)
>> > +/*
>> > + * Reset link params now, preserving any deferred connector
>> > + * detect-time reset request.
>> > + */
>> > +void intel_dp_reset_link_params_force(struct intel_dp *intel_dp)
>> > {
>> > intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);
>> > intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
>> > @@ -3720,6 +3724,28 @@ void intel_dp_reset_link_params(struct intel_dp *intel_dp)
>> > intel_dp->link.seq_train_failures = 0;
>> > }
>> >
>> > +/*
>> > + * Reset link params during the next connector detect.
>> > + * Return %true if a new reset was queued.
>> > + */
>> > +bool intel_dp_reset_link_params_defer(struct intel_dp *intel_dp)
>>
>> I find the intel_dp_reset_link_params_defer() vs.
>> intel_dp_reset_link_params_force() naming rather confusing.
>>
>> Can't immediately think of a really good name for
>> intel_dp_reset_link_params_defer() so maybe it's better to not
>> have a function for it at all (ie. just drop this patch)?
>
> The idea was to have an interface to reset the link params directly or
> in a deferred way, instead of a direct access of the flag.
>
> The names are not great yes. I could use what Jouni suggested instead,
> or if the above argument is not good enough I can also drop this patch.
I suggest intel_dp_reset_link_params() keeps its name, or gets renamed
to intel_dp_link_params_reset(). It just does the thing, no "force".
Then the other two use something like:
- submit/process
- queue/process
- stage/handle
or some combination i.e. something like:
intel_dp_link_params_reset()
intel_dp_link_params_reset_submit()
intel_dp_link_params_reset_process()
BR,
Jani.
>
>> Then you at least see that it's just setting the flag. AFAICS you only
>> have a single place (in the last patch) that uses this return value
>> for anything, so could just do the check+set dance there on the spot.
>
>>
>> > +{
>> > + bool reset_was_pending = intel_dp->reset_link_params;
>> > +
>> > + intel_dp->reset_link_params = true;
>> > +
>> > + return !reset_was_pending;
>> > +}
>> > +
>> > +static void intel_dp_handle_deferred_link_params_reset(struct intel_dp *intel_dp)
>> > +{
>> > + if (!intel_dp->reset_link_params)
>> > + return;
>> > +
>> > + intel_dp->reset_link_params = false;
>> > + intel_dp_reset_link_params_force(intel_dp);
>> > +}
>> > +
>> > /* Enable backlight PWM and backlight PP control. */
>> > void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
>> > const struct drm_connector_state *conn_state)
>> > @@ -4066,7 +4092,7 @@ void intel_dp_sync_state(struct intel_encoder *encoder,
>> > intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);
>> >
>> > if (crtc_state) {
>> > - intel_dp_reset_link_params(intel_dp);
>> > + intel_dp_reset_link_params_force(intel_dp);
>> > intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count);
>> > intel_dp->link.active = true;
>> > }
>> > @@ -6487,10 +6513,7 @@ intel_dp_detect(struct drm_connector *_connector,
>> >
>> > intel_dp_detect_sdp_caps(intel_dp);
>> >
>> > - if (intel_dp->reset_link_params) {
>> > - intel_dp_reset_link_params(intel_dp);
>> > - intel_dp->reset_link_params = false;
>> > - }
>> > + intel_dp_handle_deferred_link_params_reset(intel_dp);
>> >
>> > intel_dp_mst_configure(intel_dp);
>> >
>> > @@ -6944,7 +6967,7 @@ intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
>> >
>> > intel_dp_read_dprx_caps(intel_dp, dpcd);
>> >
>> > - intel_dp->reset_link_params = true;
>> > + intel_dp_reset_link_params_defer(intel_dp);
>> > intel_dp_invalidate_source_oui(intel_dp);
>> >
>> > return IRQ_NONE;
>> > @@ -7252,7 +7275,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
>> > encoder->base.name))
>> > return false;
>> >
>> > - intel_dp->reset_link_params = true;
>> > + intel_dp_reset_link_params_defer(intel_dp);
>> >
>> > /* Preserve the current hw state. */
>> > intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
>> > @@ -7317,7 +7340,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
>> >
>> > intel_dp_set_source_rates(intel_dp);
>> > intel_dp_set_common_rates(intel_dp);
>> > - intel_dp_reset_link_params(intel_dp);
>> > + intel_dp_reset_link_params_force(intel_dp);
>> >
>> > /* init MST on ports that can support it */
>> > intel_dp_mst_encoder_init(dig_port, connector->base.base.id);
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
>> > index f41480d247142..7c24d3dbb6983 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>> > @@ -114,7 +114,8 @@ int intel_dp_rate_index(const int *rates, int len, int rate);
>> > int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count);
>> > void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count);
>> > void intel_dp_update_sink_caps(struct intel_dp *intel_dp);
>> > -void intel_dp_reset_link_params(struct intel_dp *intel_dp);
>> > +void intel_dp_reset_link_params_force(struct intel_dp *intel_dp);
>> > +bool intel_dp_reset_link_params_defer(struct intel_dp *intel_dp);
>> >
>> > void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
>> > u8 *link_bw, u8 *rate_select);
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> > index a26094223f780..b7075060e7bd3 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> > @@ -1935,7 +1935,7 @@ static ssize_t i915_dp_force_link_rate_write(struct file *file,
>> > if (err)
>> > return err;
>> >
>> > - intel_dp_reset_link_params(intel_dp);
>> > + intel_dp_reset_link_params_force(intel_dp);
>> > intel_dp->link.force_rate = rate;
>> >
>> > drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
>> > @@ -2037,7 +2037,7 @@ static ssize_t i915_dp_force_lane_count_write(struct file *file,
>> > if (err)
>> > return err;
>> >
>> > - intel_dp_reset_link_params(intel_dp);
>> > + intel_dp_reset_link_params_force(intel_dp);
>> > intel_dp->link.force_lane_count = lane_count;
>> >
>> > drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
>> > --
>> > 2.49.1
>>
>> --
>> Ville Syrjälä
>> Intel
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/5] drm/i915/dp: Add helpers to reset link params
2026-05-22 10:29 ` Jani Nikula
@ 2026-05-22 12:39 ` Ville Syrjälä
2026-05-22 12:46 ` Jani Nikula
0 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjälä @ 2026-05-22 12:39 UTC (permalink / raw)
To: Jani Nikula; +Cc: imre.deak, Jouni Hogander, intel-gfx, intel-xe
On Fri, May 22, 2026 at 01:29:39PM +0300, Jani Nikula wrote:
> On Fri, 22 May 2026, Imre Deak <imre.deak@intel.com> wrote:
> > On Fri, May 22, 2026 at 12:36:27AM +0300, Ville Syrjälä wrote:
> >> On Mon, May 18, 2026 at 02:24:22PM +0300, Imre Deak wrote:
> >> > Add helpers to defer and handle link params resets instead of
> >> > open-coding the same. Rename intel_dp_reset_link_params() to
> >> > intel_dp_reset_link_params_force() to align its name with the new
> >> > deferred reset helpers.
> >> >
> >> > When deferring a reset, return whether a new reset was queued, used by a
> >> > follow-up change.
> >> >
> >> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> >> > ---
> >> > drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
> >> > drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> >> > drivers/gpu/drm/i915/display/intel_dp.c | 41 +++++++++++++++----
> >> > drivers/gpu/drm/i915/display/intel_dp.h | 3 +-
> >> > .../drm/i915/display/intel_dp_link_training.c | 4 +-
> >> > 5 files changed, 38 insertions(+), 14 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
> >> > index 5ff1cdf4581a5..c20a97e21419b 100644
> >> > --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> >> > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> >> > @@ -1265,7 +1265,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
> >> >
> >> > intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
> >> >
> >> > - intel_dp->reset_link_params = true;
> >> > + intel_dp_reset_link_params_defer(intel_dp);
> >> > intel_dp_invalidate_source_oui(intel_dp);
> >> >
> >> > if (display->platform.valleyview || display->platform.cherryview)
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> > index 86520848892e0..77819aaeccb76 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> > @@ -4664,7 +4664,7 @@ static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
> >> > struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
> >> > struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
> >> >
> >> > - intel_dp->reset_link_params = true;
> >> > + intel_dp_reset_link_params_defer(intel_dp);
> >> > intel_dp_invalidate_source_oui(intel_dp);
> >> >
> >> > intel_pps_encoder_reset(intel_dp);
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> >> > index 1920d2f026665..13163dd085e91 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >> > @@ -3710,7 +3710,11 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp,
> >> > intel_dp->lane_count = lane_count;
> >> > }
> >> >
> >> > -void intel_dp_reset_link_params(struct intel_dp *intel_dp)
> >> > +/*
> >> > + * Reset link params now, preserving any deferred connector
> >> > + * detect-time reset request.
> >> > + */
> >> > +void intel_dp_reset_link_params_force(struct intel_dp *intel_dp)
> >> > {
> >> > intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);
> >> > intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
> >> > @@ -3720,6 +3724,28 @@ void intel_dp_reset_link_params(struct intel_dp *intel_dp)
> >> > intel_dp->link.seq_train_failures = 0;
> >> > }
> >> >
> >> > +/*
> >> > + * Reset link params during the next connector detect.
> >> > + * Return %true if a new reset was queued.
> >> > + */
> >> > +bool intel_dp_reset_link_params_defer(struct intel_dp *intel_dp)
> >>
> >> I find the intel_dp_reset_link_params_defer() vs.
> >> intel_dp_reset_link_params_force() naming rather confusing.
> >>
> >> Can't immediately think of a really good name for
> >> intel_dp_reset_link_params_defer() so maybe it's better to not
> >> have a function for it at all (ie. just drop this patch)?
> >
> > The idea was to have an interface to reset the link params directly or
> > in a deferred way, instead of a direct access of the flag.
> >
> > The names are not great yes. I could use what Jouni suggested instead,
> > or if the above argument is not good enough I can also drop this patch.
>
> I suggest intel_dp_reset_link_params() keeps its name, or gets renamed
> to intel_dp_link_params_reset(). It just does the thing, no "force".
>
> Then the other two use something like:
>
> - submit/process
> - queue/process
> - stage/handle
>
> or some combination i.e. something like:
>
> intel_dp_link_params_reset()
> intel_dp_link_params_reset_submit()
> intel_dp_link_params_reset_process()
All of it kinda leaves it a bit unclear how these things
are related, and then one probably has to read through
them to figure out what they're actually doing.
Hence why I think just setting/checking the flag on the
spot might be the clearest approach. You can immediately
find where it's set vs. checked.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/5] drm/i915/dp: Add helpers to reset link params
2026-05-22 12:39 ` Ville Syrjälä
@ 2026-05-22 12:46 ` Jani Nikula
2026-05-22 12:50 ` Ville Syrjälä
0 siblings, 1 reply; 21+ messages in thread
From: Jani Nikula @ 2026-05-22 12:46 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: imre.deak, Jouni Hogander, intel-gfx, intel-xe
On Fri, 22 May 2026, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Fri, May 22, 2026 at 01:29:39PM +0300, Jani Nikula wrote:
>> On Fri, 22 May 2026, Imre Deak <imre.deak@intel.com> wrote:
>> > On Fri, May 22, 2026 at 12:36:27AM +0300, Ville Syrjälä wrote:
>> >> On Mon, May 18, 2026 at 02:24:22PM +0300, Imre Deak wrote:
>> >> > Add helpers to defer and handle link params resets instead of
>> >> > open-coding the same. Rename intel_dp_reset_link_params() to
>> >> > intel_dp_reset_link_params_force() to align its name with the new
>> >> > deferred reset helpers.
>> >> >
>> >> > When deferring a reset, return whether a new reset was queued, used by a
>> >> > follow-up change.
>> >> >
>> >> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>> >> > ---
>> >> > drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
>> >> > drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
>> >> > drivers/gpu/drm/i915/display/intel_dp.c | 41 +++++++++++++++----
>> >> > drivers/gpu/drm/i915/display/intel_dp.h | 3 +-
>> >> > .../drm/i915/display/intel_dp_link_training.c | 4 +-
>> >> > 5 files changed, 38 insertions(+), 14 deletions(-)
>> >> >
>> >> > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
>> >> > index 5ff1cdf4581a5..c20a97e21419b 100644
>> >> > --- a/drivers/gpu/drm/i915/display/g4x_dp.c
>> >> > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
>> >> > @@ -1265,7 +1265,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
>> >> >
>> >> > intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
>> >> >
>> >> > - intel_dp->reset_link_params = true;
>> >> > + intel_dp_reset_link_params_defer(intel_dp);
>> >> > intel_dp_invalidate_source_oui(intel_dp);
>> >> >
>> >> > if (display->platform.valleyview || display->platform.cherryview)
>> >> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>> >> > index 86520848892e0..77819aaeccb76 100644
>> >> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> >> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> >> > @@ -4664,7 +4664,7 @@ static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
>> >> > struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
>> >> > struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
>> >> >
>> >> > - intel_dp->reset_link_params = true;
>> >> > + intel_dp_reset_link_params_defer(intel_dp);
>> >> > intel_dp_invalidate_source_oui(intel_dp);
>> >> >
>> >> > intel_pps_encoder_reset(intel_dp);
>> >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> >> > index 1920d2f026665..13163dd085e91 100644
>> >> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> >> > @@ -3710,7 +3710,11 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp,
>> >> > intel_dp->lane_count = lane_count;
>> >> > }
>> >> >
>> >> > -void intel_dp_reset_link_params(struct intel_dp *intel_dp)
>> >> > +/*
>> >> > + * Reset link params now, preserving any deferred connector
>> >> > + * detect-time reset request.
>> >> > + */
>> >> > +void intel_dp_reset_link_params_force(struct intel_dp *intel_dp)
>> >> > {
>> >> > intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);
>> >> > intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
>> >> > @@ -3720,6 +3724,28 @@ void intel_dp_reset_link_params(struct intel_dp *intel_dp)
>> >> > intel_dp->link.seq_train_failures = 0;
>> >> > }
>> >> >
>> >> > +/*
>> >> > + * Reset link params during the next connector detect.
>> >> > + * Return %true if a new reset was queued.
>> >> > + */
>> >> > +bool intel_dp_reset_link_params_defer(struct intel_dp *intel_dp)
>> >>
>> >> I find the intel_dp_reset_link_params_defer() vs.
>> >> intel_dp_reset_link_params_force() naming rather confusing.
>> >>
>> >> Can't immediately think of a really good name for
>> >> intel_dp_reset_link_params_defer() so maybe it's better to not
>> >> have a function for it at all (ie. just drop this patch)?
>> >
>> > The idea was to have an interface to reset the link params directly or
>> > in a deferred way, instead of a direct access of the flag.
>> >
>> > The names are not great yes. I could use what Jouni suggested instead,
>> > or if the above argument is not good enough I can also drop this patch.
>>
>> I suggest intel_dp_reset_link_params() keeps its name, or gets renamed
>> to intel_dp_link_params_reset(). It just does the thing, no "force".
>>
>> Then the other two use something like:
>>
>> - submit/process
>> - queue/process
>> - stage/handle
>>
>> or some combination i.e. something like:
>>
>> intel_dp_link_params_reset()
>> intel_dp_link_params_reset_submit()
>> intel_dp_link_params_reset_process()
>
> All of it kinda leaves it a bit unclear how these things
> are related, and then one probably has to read through
> them to figure out what they're actually doing.
>
> Hence why I think just setting/checking the flag on the
> spot might be the clearest approach. You can immediately
> find where it's set vs. checked.
Trouble is if you want to hide that flag in an opaque type in the
future.
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/5] drm/i915/dp: Add helpers to reset link params
2026-05-22 12:46 ` Jani Nikula
@ 2026-05-22 12:50 ` Ville Syrjälä
2026-05-22 15:32 ` Imre Deak
0 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjälä @ 2026-05-22 12:50 UTC (permalink / raw)
To: Jani Nikula; +Cc: imre.deak, Jouni Hogander, intel-gfx, intel-xe
On Fri, May 22, 2026 at 03:46:50PM +0300, Jani Nikula wrote:
> On Fri, 22 May 2026, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Fri, May 22, 2026 at 01:29:39PM +0300, Jani Nikula wrote:
> >> On Fri, 22 May 2026, Imre Deak <imre.deak@intel.com> wrote:
> >> > On Fri, May 22, 2026 at 12:36:27AM +0300, Ville Syrjälä wrote:
> >> >> On Mon, May 18, 2026 at 02:24:22PM +0300, Imre Deak wrote:
> >> >> > Add helpers to defer and handle link params resets instead of
> >> >> > open-coding the same. Rename intel_dp_reset_link_params() to
> >> >> > intel_dp_reset_link_params_force() to align its name with the new
> >> >> > deferred reset helpers.
> >> >> >
> >> >> > When deferring a reset, return whether a new reset was queued, used by a
> >> >> > follow-up change.
> >> >> >
> >> >> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> >> >> > ---
> >> >> > drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
> >> >> > drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> >> >> > drivers/gpu/drm/i915/display/intel_dp.c | 41 +++++++++++++++----
> >> >> > drivers/gpu/drm/i915/display/intel_dp.h | 3 +-
> >> >> > .../drm/i915/display/intel_dp_link_training.c | 4 +-
> >> >> > 5 files changed, 38 insertions(+), 14 deletions(-)
> >> >> >
> >> >> > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
> >> >> > index 5ff1cdf4581a5..c20a97e21419b 100644
> >> >> > --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> >> >> > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> >> >> > @@ -1265,7 +1265,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
> >> >> >
> >> >> > intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
> >> >> >
> >> >> > - intel_dp->reset_link_params = true;
> >> >> > + intel_dp_reset_link_params_defer(intel_dp);
> >> >> > intel_dp_invalidate_source_oui(intel_dp);
> >> >> >
> >> >> > if (display->platform.valleyview || display->platform.cherryview)
> >> >> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> >> > index 86520848892e0..77819aaeccb76 100644
> >> >> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> >> >> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> >> > @@ -4664,7 +4664,7 @@ static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
> >> >> > struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
> >> >> > struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
> >> >> >
> >> >> > - intel_dp->reset_link_params = true;
> >> >> > + intel_dp_reset_link_params_defer(intel_dp);
> >> >> > intel_dp_invalidate_source_oui(intel_dp);
> >> >> >
> >> >> > intel_pps_encoder_reset(intel_dp);
> >> >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> >> >> > index 1920d2f026665..13163dd085e91 100644
> >> >> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >> >> > @@ -3710,7 +3710,11 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp,
> >> >> > intel_dp->lane_count = lane_count;
> >> >> > }
> >> >> >
> >> >> > -void intel_dp_reset_link_params(struct intel_dp *intel_dp)
> >> >> > +/*
> >> >> > + * Reset link params now, preserving any deferred connector
> >> >> > + * detect-time reset request.
> >> >> > + */
> >> >> > +void intel_dp_reset_link_params_force(struct intel_dp *intel_dp)
> >> >> > {
> >> >> > intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);
> >> >> > intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
> >> >> > @@ -3720,6 +3724,28 @@ void intel_dp_reset_link_params(struct intel_dp *intel_dp)
> >> >> > intel_dp->link.seq_train_failures = 0;
> >> >> > }
> >> >> >
> >> >> > +/*
> >> >> > + * Reset link params during the next connector detect.
> >> >> > + * Return %true if a new reset was queued.
> >> >> > + */
> >> >> > +bool intel_dp_reset_link_params_defer(struct intel_dp *intel_dp)
> >> >>
> >> >> I find the intel_dp_reset_link_params_defer() vs.
> >> >> intel_dp_reset_link_params_force() naming rather confusing.
> >> >>
> >> >> Can't immediately think of a really good name for
> >> >> intel_dp_reset_link_params_defer() so maybe it's better to not
> >> >> have a function for it at all (ie. just drop this patch)?
> >> >
> >> > The idea was to have an interface to reset the link params directly or
> >> > in a deferred way, instead of a direct access of the flag.
> >> >
> >> > The names are not great yes. I could use what Jouni suggested instead,
> >> > or if the above argument is not good enough I can also drop this patch.
> >>
> >> I suggest intel_dp_reset_link_params() keeps its name, or gets renamed
> >> to intel_dp_link_params_reset(). It just does the thing, no "force".
> >>
> >> Then the other two use something like:
> >>
> >> - submit/process
> >> - queue/process
> >> - stage/handle
> >>
> >> or some combination i.e. something like:
> >>
> >> intel_dp_link_params_reset()
> >> intel_dp_link_params_reset_submit()
> >> intel_dp_link_params_reset_process()
> >
> > All of it kinda leaves it a bit unclear how these things
> > are related, and then one probably has to read through
> > them to figure out what they're actually doing.
> >
> > Hence why I think just setting/checking the flag on the
> > spot might be the clearest approach. You can immediately
> > find where it's set vs. checked.
>
> Trouble is if you want to hide that flag in an opaque type in the
> future.
Do we want that?
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/5] drm/i915/dp: Add helpers to reset link params
2026-05-22 12:50 ` Ville Syrjälä
@ 2026-05-22 15:32 ` Imre Deak
0 siblings, 0 replies; 21+ messages in thread
From: Imre Deak @ 2026-05-22 15:32 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Jani Nikula, Jouni Hogander, intel-gfx, intel-xe
On Fri, May 22, 2026 at 03:50:38PM +0300, Ville Syrjälä wrote:
> On Fri, May 22, 2026 at 03:46:50PM +0300, Jani Nikula wrote:
> > On Fri, 22 May 2026, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > > On Fri, May 22, 2026 at 01:29:39PM +0300, Jani Nikula wrote:
> > >> On Fri, 22 May 2026, Imre Deak <imre.deak@intel.com> wrote:
> > >> > On Fri, May 22, 2026 at 12:36:27AM +0300, Ville Syrjälä wrote:
> > >> >> On Mon, May 18, 2026 at 02:24:22PM +0300, Imre Deak wrote:
> > >> >> > Add helpers to defer and handle link params resets instead of
> > >> >> > open-coding the same. Rename intel_dp_reset_link_params() to
> > >> >> > intel_dp_reset_link_params_force() to align its name with the new
> > >> >> > deferred reset helpers.
> > >> >> >
> > >> >> > When deferring a reset, return whether a new reset was queued, used by a
> > >> >> > follow-up change.
> > >> >> >
> > >> >> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > >> >> > ---
> > >> >> > drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
> > >> >> > drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> > >> >> > drivers/gpu/drm/i915/display/intel_dp.c | 41 +++++++++++++++----
> > >> >> > drivers/gpu/drm/i915/display/intel_dp.h | 3 +-
> > >> >> > .../drm/i915/display/intel_dp_link_training.c | 4 +-
> > >> >> > 5 files changed, 38 insertions(+), 14 deletions(-)
> > >> >> >
> > >> >> > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
> > >> >> > index 5ff1cdf4581a5..c20a97e21419b 100644
> > >> >> > --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> > >> >> > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> > >> >> > @@ -1265,7 +1265,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
> > >> >> >
> > >> >> > intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
> > >> >> >
> > >> >> > - intel_dp->reset_link_params = true;
> > >> >> > + intel_dp_reset_link_params_defer(intel_dp);
> > >> >> > intel_dp_invalidate_source_oui(intel_dp);
> > >> >> >
> > >> >> > if (display->platform.valleyview || display->platform.cherryview)
> > >> >> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > >> >> > index 86520848892e0..77819aaeccb76 100644
> > >> >> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > >> >> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > >> >> > @@ -4664,7 +4664,7 @@ static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
> > >> >> > struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
> > >> >> > struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
> > >> >> >
> > >> >> > - intel_dp->reset_link_params = true;
> > >> >> > + intel_dp_reset_link_params_defer(intel_dp);
> > >> >> > intel_dp_invalidate_source_oui(intel_dp);
> > >> >> >
> > >> >> > intel_pps_encoder_reset(intel_dp);
> > >> >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > >> >> > index 1920d2f026665..13163dd085e91 100644
> > >> >> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > >> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > >> >> > @@ -3710,7 +3710,11 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp,
> > >> >> > intel_dp->lane_count = lane_count;
> > >> >> > }
> > >> >> >
> > >> >> > -void intel_dp_reset_link_params(struct intel_dp *intel_dp)
> > >> >> > +/*
> > >> >> > + * Reset link params now, preserving any deferred connector
> > >> >> > + * detect-time reset request.
> > >> >> > + */
> > >> >> > +void intel_dp_reset_link_params_force(struct intel_dp *intel_dp)
> > >> >> > {
> > >> >> > intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);
> > >> >> > intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
> > >> >> > @@ -3720,6 +3724,28 @@ void intel_dp_reset_link_params(struct intel_dp *intel_dp)
> > >> >> > intel_dp->link.seq_train_failures = 0;
> > >> >> > }
> > >> >> >
> > >> >> > +/*
> > >> >> > + * Reset link params during the next connector detect.
> > >> >> > + * Return %true if a new reset was queued.
> > >> >> > + */
> > >> >> > +bool intel_dp_reset_link_params_defer(struct intel_dp *intel_dp)
> > >> >>
> > >> >> I find the intel_dp_reset_link_params_defer() vs.
> > >> >> intel_dp_reset_link_params_force() naming rather confusing.
> > >> >>
> > >> >> Can't immediately think of a really good name for
> > >> >> intel_dp_reset_link_params_defer() so maybe it's better to not
> > >> >> have a function for it at all (ie. just drop this patch)?
> > >> >
> > >> > The idea was to have an interface to reset the link params directly or
> > >> > in a deferred way, instead of a direct access of the flag.
> > >> >
> > >> > The names are not great yes. I could use what Jouni suggested instead,
> > >> > or if the above argument is not good enough I can also drop this patch.
> > >>
> > >> I suggest intel_dp_reset_link_params() keeps its name, or gets renamed
> > >> to intel_dp_link_params_reset(). It just does the thing, no "force".
> > >>
> > >> Then the other two use something like:
> > >>
> > >> - submit/process
> > >> - queue/process
> > >> - stage/handle
> > >>
> > >> or some combination i.e. something like:
> > >>
> > >> intel_dp_link_params_reset()
> > >> intel_dp_link_params_reset_submit()
> > >> intel_dp_link_params_reset_process()
> > >
> > > All of it kinda leaves it a bit unclear how these things
> > > are related, and then one probably has to read through
> > > them to figure out what they're actually doing.
> > >
> > > Hence why I think just setting/checking the flag on the
> > > spot might be the clearest approach. You can immediately
> > > find where it's set vs. checked.
> >
> > Trouble is if you want to hide that flag in an opaque type in the
> > future.
>
> Do we want that?
There's a few property of the (active) link like intel_dp::link_rate,
lane_count, link.active, reset_link_params, which all could be tracked
in a separate link specific state. It could also make sense then to move
all the handlers of that state into a separate module, but not sure
about the details for that. For now I think it's better to drop this
patch and reconsider a suitable interface later. Will resend v2 with
that.
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2026-05-22 15:32 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-05-18 11:24 [PATCH 0/5] drm/i915/dp: Sanitize link capability change handling Imre Deak
2026-05-18 11:24 ` [PATCH 1/5] drm/i915/dp: Add helpers to reset link params Imre Deak
2026-05-21 21:36 ` Ville Syrjälä
2026-05-22 7:36 ` Hogander, Jouni
2026-05-22 7:47 ` Imre Deak
2026-05-22 10:29 ` Jani Nikula
2026-05-22 12:39 ` Ville Syrjälä
2026-05-22 12:46 ` Jani Nikula
2026-05-22 12:50 ` Ville Syrjälä
2026-05-22 15:32 ` Imre Deak
2026-05-18 11:24 ` [PATCH 2/5] drm/i915/dp: Reset link params after a DPRX capability change Imre Deak
2026-05-18 11:24 ` [PATCH 3/5] drm/i915/dp: Add helper to set common link params Imre Deak
2026-05-22 7:20 ` Hogander, Jouni
2026-05-18 11:24 ` [PATCH 4/5] drm/i915/dp: Cache max common lane count Imre Deak
2026-05-22 7:21 ` Hogander, Jouni
2026-05-18 11:24 ` [PATCH 5/5] drm/i915/dp: Detect changes in common link parameters Imre Deak
2026-05-21 21:43 ` Ville Syrjälä
2026-05-22 7:54 ` Imre Deak
2026-05-18 12:01 ` ✓ CI.KUnit: success for drm/i915/dp: Sanitize link capability change handling Patchwork
2026-05-18 12:41 ` ✓ Xe.CI.BAT: " Patchwork
2026-05-18 16:04 ` ✗ Xe.CI.FULL: failure " Patchwork
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox