Re: [PATCH] drm/i915/display: Use PIPEDMC_FRMTMSTMP on display ver >= 30

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Tue, May 19, 2026 at 02:33:38AM +0000, Kandpal, Suraj wrote:
> > Subject: Re: [PATCH] drm/i915/display: Use PIPEDMC_FRMTMSTMP on
> > display ver >= 30
> > 
> > On Fri, May 15, 2026 at 09:40:56PM +0530, Suraj Kandpal wrote:
> > > Starting with display version 30, the per-pipe frame timestamp is read
> > > from the PIPEDMC register block (PIPEDMC_FRMTMSTMP) instead of the
> > > legacy PIPE_FRMTMSTMP MMIO. Extend PIPE_FRMTMSTMP() to take the
> > > display and select the appropriate register based on DISPLAY_VER(),
> > > and update all callers intel_vblank accordingly.
> > >
> > > Bspec: 79482
> > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > ---
> > > v1 -> v2:
> > > - Define registers in correct location (Jani)
> > > - Use the intel_display_wa() helper to select the correct register
> > > (Gustavo)
> > > - Fix early vblank timeout issue when DMC is not loaded
> > >
> > >  .../gpu/drm/i915/display/intel_display_wa.c    |  2 ++
> > >  .../gpu/drm/i915/display/intel_display_wa.h    |  1 +
> > >  drivers/gpu/drm/i915/display/intel_dmc_regs.h  |  6 ++++++
> > >  drivers/gpu/drm/i915/display/intel_vblank.c    | 18 ++++++++++++++----
> > >  4 files changed, 23 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c
> > > b/drivers/gpu/drm/i915/display/intel_display_wa.c
> > > index 7d3d63a59882..44c2a503c911 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_wa.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
> > > @@ -110,6 +110,8 @@ bool __intel_display_wa(struct intel_display
> > *display, enum intel_display_wa wa,
> > >  		return DISPLAY_VERx100(display) == 3000 ||
> > >  			DISPLAY_VERx100(display) == 2000 ||
> > >  			DISPLAY_VERx100(display) == 1401;
> > > +	case INTEL_DISPLAY_WA_14022946399:
> > > +		return DISPLAY_VER(display) >= 30;
> > 
> > According to bspec PIPEDMC_FRMTMSTMP shouldn't even exist on PTL.
> > Did you actually check that the register works?
> 
> Yes you are correct seems like this does not exist on PTL, weird that the Xe.CI does not throw any error In relation to this.
> 
> > 
> > And I believe the hw register corruption issue being addressed by w/a
> > 14022946399 (also applies to LNL) should anyway be fixed on the platforms
> > that have PIPEDMC_FRMTMSTMP so this w/a stuff here makes no sense.
> 
> Hmm the confusing thing here is this same WA has two ways to go about it. From NVL onwards we need to ready the PIPEDMC_FRMTMSPTMP
> But before that it was that we read the FRMTMSTMP register once per frame.
> So for display ver >= 35 we maybe should still switch to PIPEDMC_FRMTMSTMP

IIRC I read somewhere that the PIPEDMC register is going to be
removed in the near future, so not sure there's much point in 
using it at all.

-- 
Ville Syrjälä
Intel