* [PATCH] drm/xe/ggtt: use full-range drm_mm with reserved nodes on PF
@ 2026-05-27 14:45 Rodrigo Vivi
2026-05-27 17:42 ` ✓ CI.KUnit: success for " Patchwork
` (4 more replies)
0 siblings, 5 replies; 13+ messages in thread
From: Rodrigo Vivi @ 2026-05-27 14:45 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: Rodrigo Vivi, Ville Syrjälä, Michal Wajdeczko,
Maarten Lankhorst
The PF GGTT allocator was initialised over a relative [0, usable_size)
range, with ggtt->start added on every address conversion to get the
actual hardware address. Two consequences of that model were considered
"horrible hacks":
- ggtt->start (the WOPCM offset) had to be carried around and added
to every drm_mm result.
- The GUC_GGTT_TOP ceiling silently truncated the GGTT range instead
of being made explicit, leaving PTEs in [GUC_GGTT_TOP, total_size)
untouched during the initial clear.
Fix this for the PF case by initialising drm_mm over the full hardware
GGTT range [0, total_size) and permanently reserving the two forbidden
zones:
- [0, wopcm) — inaccessible below WOPCM
- [GUC_GGTT_TOP, total_size) — inaccessible above GUC_GGTT_TOP
A new mm_offset field (zero for PF) carries the base offset used in
address conversions, unifying the existing VF relative model (where
mm_offset == vf_base) with the new PF absolute model. The public
xe_ggtt_start() / xe_ggtt_size() API continues to return the usable
[wopcm, GUC_GGTT_TOP) boundaries, so callers such as the SR-IOV PF
config code are unaffected.
xe_ggtt_shift_nodes() now updates both ggtt->start and ggtt->mm_offset
so the VF recovery path remains a single O(1) WRITE_ONCE pair.
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Assisted-by: GitHub-Copilot:claude-sonnet-4.6
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/xe/xe_ggtt.c | 123 ++++++++++++++++++++++++++++-------
1 file changed, 101 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index a351c578b170..00a6cd2b8a51 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -137,6 +137,17 @@ struct xe_ggtt {
const struct xe_ggtt_pt_ops *pt_ops;
/** @mm: The memory manager used to manage individual GGTT allocations */
struct drm_mm mm;
+ /**
+ * @mm_offset: base offset added to drm_mm node addresses to obtain hardware
+ * GGTT addresses. For PF this is 0 (drm_mm uses absolute hardware addresses).
+ * For VF this equals @start (drm_mm uses relative addresses from VF base).
+ * Updated atomically by xe_ggtt_shift_nodes() during VF recovery.
+ */
+ u64 mm_offset;
+ /** @reserved_bottom: permanently reserved [0, WOPCM) drm_mm node for PF */
+ struct drm_mm_node reserved_bottom;
+ /** @reserved_top: permanently reserved [GUC_GGTT_TOP, total) drm_mm node for PF */
+ struct drm_mm_node reserved_top;
/** @access_count: counts GGTT writes */
unsigned int access_count;
/** @wq: Dedicated unordered work queue to process node removals */
@@ -318,6 +329,10 @@ static void ggtt_fini_early(struct drm_device *drm, void *arg)
{
struct xe_ggtt *ggtt = arg;
+ if (drm_mm_node_allocated(&ggtt->reserved_top))
+ drm_mm_remove_node(&ggtt->reserved_top);
+ if (drm_mm_node_allocated(&ggtt->reserved_bottom))
+ drm_mm_remove_node(&ggtt->reserved_bottom);
destroy_workqueue(ggtt->wq);
drm_mm_takedown(&ggtt->mm);
}
@@ -354,16 +369,66 @@ static const struct xe_ggtt_pt_ops xelpg_pt_wa_ops = {
.ggtt_get_pte = xe_ggtt_get_pte,
};
-static void __xe_ggtt_init_early(struct xe_ggtt *ggtt, u64 start, u64 size)
+/*
+ * __xe_ggtt_init_early - Generic drm_mm initialisation for both PF and VF.
+ *
+ * @start and @size define the usable GGTT range exposed through the public API.
+ * @mm_offset is added to every drm_mm node address to obtain the hardware
+ * address (0 for PF where the drm_mm spans real addresses; @start for VF).
+ * @mm_size is the total span passed to drm_mm_init() (equals @size for VF;
+ * equals the full hardware GGTT size for PF).
+ */
+static void __xe_ggtt_init_early(struct xe_ggtt *ggtt, u64 start, u64 size,
+ u64 mm_offset, u64 mm_size)
{
ggtt->start = start;
ggtt->size = size;
- drm_mm_init(&ggtt->mm, 0, size);
+ ggtt->mm_offset = mm_offset;
+ drm_mm_init(&ggtt->mm, 0, mm_size);
+}
+
+/*
+ * __xe_ggtt_reserve_pf_nodes - Permanently reserve the forbidden GGTT zones.
+ *
+ * Must be called after __xe_ggtt_init_early() for the PF case. Reserves
+ * [0, @wopcm) and [@guc_top, @total_size) so the allocator never hands them
+ * out. On failure the drm_mm is torn down and the error is returned.
+ */
+static int __xe_ggtt_reserve_pf_nodes(struct xe_ggtt *ggtt, u64 wopcm,
+ u64 guc_top, u64 total_size)
+{
+ int err;
+
+ /* Reserve [0, wopcm) — GuC cannot access below WOPCM */
+ if (wopcm > 0) {
+ ggtt->reserved_bottom.start = 0;
+ ggtt->reserved_bottom.size = wopcm;
+ err = drm_mm_reserve_node(&ggtt->mm, &ggtt->reserved_bottom);
+ if (WARN_ON(err))
+ goto err_takedown;
+ }
+
+ /* Reserve [guc_top, total_size) — GuC cannot access above GUC_GGTT_TOP */
+ if (guc_top < total_size) {
+ ggtt->reserved_top.start = guc_top;
+ ggtt->reserved_top.size = total_size - guc_top;
+ err = drm_mm_reserve_node(&ggtt->mm, &ggtt->reserved_top);
+ if (WARN_ON(err))
+ goto err_remove_bottom;
+ }
+
+ return 0;
+
+err_remove_bottom:
+ drm_mm_remove_node(&ggtt->reserved_bottom);
+err_takedown:
+ drm_mm_takedown(&ggtt->mm);
+ return err;
}
int xe_ggtt_init_kunit(struct xe_ggtt *ggtt, u32 start, u32 size)
{
- __xe_ggtt_init_early(ggtt, start, size);
+ __xe_ggtt_init_early(ggtt, start, size, start, size);
return 0;
}
EXPORT_SYMBOL_IF_KUNIT(xe_ggtt_init_kunit);
@@ -405,8 +470,13 @@ int xe_ggtt_init_early(struct xe_ggtt *ggtt)
xe_tile_err(ggtt->tile, "Hardware reported no preallocated GSM\n");
return -ENOMEM;
}
+ /*
+ * For PF, ggtt_size holds the full hardware GGTT size. The
+ * WOPCM and GUC_GGTT_TOP limits are enforced via permanently
+ * reserved drm_mm nodes rather than by capping the range.
+ */
ggtt_start = wopcm;
- ggtt_size = (gsm_size / 8) * (u64)XE_PAGE_SIZE - ggtt_start;
+ ggtt_size = (gsm_size / 8) * (u64)XE_PAGE_SIZE;
} else {
ggtt_start = xe_tile_sriov_vf_ggtt_base(ggtt->tile);
ggtt_size = xe_tile_sriov_vf_ggtt(ggtt->tile);
@@ -423,9 +493,6 @@ int xe_ggtt_init_early(struct xe_ggtt *ggtt)
if (IS_DGFX(xe) && xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K)
ggtt->flags |= XE_GGTT_FLAGS_64K;
- if (ggtt_size + ggtt_start > GUC_GGTT_TOP)
- ggtt_size = GUC_GGTT_TOP - ggtt_start;
-
if (GRAPHICS_VERx100(xe) >= 1270)
ggtt->pt_ops =
(ggtt->tile->media_gt && XE_GT_WA(ggtt->tile->media_gt, 22019338487)) ||
@@ -438,7 +505,19 @@ int xe_ggtt_init_early(struct xe_ggtt *ggtt)
if (!ggtt->wq)
return -ENOMEM;
- __xe_ggtt_init_early(ggtt, ggtt_start, ggtt_size);
+ if (!IS_SRIOV_VF(xe)) {
+ __xe_ggtt_init_early(ggtt, ggtt_start, GUC_GGTT_TOP - ggtt_start,
+ 0, ggtt_size);
+ err = __xe_ggtt_reserve_pf_nodes(ggtt, ggtt_start, GUC_GGTT_TOP,
+ ggtt_size);
+ if (err) {
+ destroy_workqueue(ggtt->wq);
+ return err;
+ }
+ } else {
+ __xe_ggtt_init_early(ggtt, ggtt_start, ggtt_size,
+ ggtt_start, ggtt_size);
+ }
err = drmm_add_action_or_reset(&xe->drm, ggtt_fini_early, ggtt);
if (err)
@@ -459,7 +538,7 @@ static void xe_ggtt_initial_clear(struct xe_ggtt *ggtt)
/* Display may have allocated inside ggtt, so be careful with clearing here */
mutex_lock(&ggtt->lock);
drm_mm_for_each_hole(hole, &ggtt->mm, start, end)
- xe_ggtt_clear(ggtt, ggtt->start + start, end - start);
+ xe_ggtt_clear(ggtt, ggtt->mm_offset + start, end - start);
xe_ggtt_invalidate(ggtt);
mutex_unlock(&ggtt->lock);
@@ -613,6 +692,7 @@ void xe_ggtt_shift_nodes(struct xe_ggtt *ggtt, u64 new_start)
/* pairs with READ_ONCE in xe_ggtt_node_addr() */
WRITE_ONCE(ggtt->start, new_start);
+ WRITE_ONCE(ggtt->mm_offset, new_start);
}
static int xe_ggtt_insert_node_locked(struct xe_ggtt_node *node,
@@ -815,20 +895,19 @@ static int __xe_ggtt_insert_bo_at(struct xe_ggtt *ggtt, struct xe_bo *bo,
mutex_lock(&ggtt->lock);
/*
- * When inheriting the initial framebuffer, the framebuffer is
- * physically located at VRAM address 0, and usually at GGTT address 0 too.
- *
- * The display code will ask for a GGTT allocation between end of BO and
- * remainder of GGTT, unaware that the start is reserved by WOPCM.
+ * Convert caller-supplied hardware GGTT addresses to drm_mm-relative
+ * coordinates. For PF mm_offset is 0 so this is a no-op; callers pass
+ * real addresses and the reserved_bottom/top nodes prevent allocations
+ * in the forbidden regions. For VF, mm_offset equals the VF base so
+ * we convert to relative drm_mm space.
*/
- if (start >= ggtt->start)
- start -= ggtt->start;
+ if (start >= ggtt->mm_offset)
+ start -= ggtt->mm_offset;
else
start = 0;
- /* Should never happen, but since we handle start, fail graciously for end */
- if (end >= ggtt->start)
- end -= ggtt->start;
+ if (end >= ggtt->mm_offset)
+ end -= ggtt->mm_offset;
else
end = 0;
@@ -923,7 +1002,7 @@ u64 xe_ggtt_largest_hole(struct xe_ggtt *ggtt, u64 alignment, u64 *spare)
mutex_lock(&ggtt->lock);
drm_mm_for_each_hole(entry, mm, hole_start, hole_end) {
- hole_start = max(hole_start, ggtt->start);
+ hole_start = max(hole_start, ggtt->mm_offset);
hole_start = ALIGN(hole_start, alignment);
hole_end = ALIGN_DOWN(hole_end, alignment);
if (hole_start >= hole_end)
@@ -1098,7 +1177,7 @@ u64 xe_ggtt_print_holes(struct xe_ggtt *ggtt, u64 alignment, struct drm_printer
mutex_lock(&ggtt->lock);
drm_mm_for_each_hole(entry, mm, hole_start, hole_end) {
- hole_start = max(hole_start, ggtt->start);
+ hole_start = max(hole_start, ggtt->mm_offset);
hole_start = ALIGN(hole_start, alignment);
hole_end = ALIGN_DOWN(hole_end, alignment);
if (hole_start >= hole_end)
@@ -1152,7 +1231,7 @@ u64 xe_ggtt_read_pte(struct xe_ggtt *ggtt, u64 offset)
u64 xe_ggtt_node_addr(const struct xe_ggtt_node *node)
{
/* pairs with WRITE_ONCE in xe_ggtt_shift_nodes() */
- return node->base.start + READ_ONCE(node->ggtt->start);
+ return node->base.start + READ_ONCE(node->ggtt->mm_offset);
}
/**
--
2.54.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* ✓ CI.KUnit: success for drm/xe/ggtt: use full-range drm_mm with reserved nodes on PF
2026-05-27 14:45 [PATCH] drm/xe/ggtt: use full-range drm_mm with reserved nodes on PF Rodrigo Vivi
@ 2026-05-27 17:42 ` Patchwork
2026-05-27 18:55 ` ✓ Xe.CI.BAT: " Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2026-05-27 17:42 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-xe
== Series Details ==
Series: drm/xe/ggtt: use full-range drm_mm with reserved nodes on PF
URL : https://patchwork.freedesktop.org/series/167391/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[17:40:47] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:40:52] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:41:23] Starting KUnit Kernel (1/1)...
[17:41:23] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:41:23] ================== guc_buf (11 subtests) ===================
[17:41:23] [PASSED] test_smallest
[17:41:23] [PASSED] test_largest
[17:41:23] [PASSED] test_granular
[17:41:23] [PASSED] test_unique
[17:41:23] [PASSED] test_overlap
[17:41:23] [PASSED] test_reusable
[17:41:23] [PASSED] test_too_big
[17:41:23] [PASSED] test_flush
[17:41:23] [PASSED] test_lookup
[17:41:23] [PASSED] test_data
[17:41:23] [PASSED] test_class
[17:41:23] ===================== [PASSED] guc_buf =====================
[17:41:23] =================== guc_dbm (7 subtests) ===================
[17:41:23] [PASSED] test_empty
[17:41:23] [PASSED] test_default
[17:41:23] ======================== test_size ========================
[17:41:23] [PASSED] 4
[17:41:23] [PASSED] 8
[17:41:23] [PASSED] 32
[17:41:23] [PASSED] 256
[17:41:23] ==================== [PASSED] test_size ====================
[17:41:23] ======================= test_reuse ========================
[17:41:23] [PASSED] 4
[17:41:23] [PASSED] 8
[17:41:23] [PASSED] 32
[17:41:23] [PASSED] 256
[17:41:23] =================== [PASSED] test_reuse ====================
[17:41:23] =================== test_range_overlap ====================
[17:41:23] [PASSED] 4
[17:41:23] [PASSED] 8
[17:41:23] [PASSED] 32
[17:41:23] [PASSED] 256
[17:41:23] =============== [PASSED] test_range_overlap ================
[17:41:23] =================== test_range_compact ====================
[17:41:23] [PASSED] 4
[17:41:23] [PASSED] 8
[17:41:23] [PASSED] 32
[17:41:23] [PASSED] 256
[17:41:23] =============== [PASSED] test_range_compact ================
[17:41:23] ==================== test_range_spare =====================
[17:41:23] [PASSED] 4
[17:41:23] [PASSED] 8
[17:41:23] [PASSED] 32
[17:41:23] [PASSED] 256
[17:41:23] ================ [PASSED] test_range_spare =================
[17:41:23] ===================== [PASSED] guc_dbm =====================
[17:41:23] =================== guc_idm (6 subtests) ===================
[17:41:23] [PASSED] bad_init
[17:41:23] [PASSED] no_init
[17:41:23] [PASSED] init_fini
[17:41:23] [PASSED] check_used
[17:41:23] [PASSED] check_quota
[17:41:23] [PASSED] check_all
[17:41:23] ===================== [PASSED] guc_idm =====================
[17:41:23] ================== no_relay (3 subtests) ===================
[17:41:23] [PASSED] xe_drops_guc2pf_if_not_ready
[17:41:23] [PASSED] xe_drops_guc2vf_if_not_ready
[17:41:23] [PASSED] xe_rejects_send_if_not_ready
[17:41:23] ==================== [PASSED] no_relay =====================
[17:41:23] ================== pf_relay (14 subtests) ==================
[17:41:23] [PASSED] pf_rejects_guc2pf_too_short
[17:41:23] [PASSED] pf_rejects_guc2pf_too_long
[17:41:23] [PASSED] pf_rejects_guc2pf_no_payload
[17:41:23] [PASSED] pf_fails_no_payload
[17:41:23] [PASSED] pf_fails_bad_origin
[17:41:23] [PASSED] pf_fails_bad_type
[17:41:23] [PASSED] pf_txn_reports_error
[17:41:23] [PASSED] pf_txn_sends_pf2guc
[17:41:23] [PASSED] pf_sends_pf2guc
[17:41:23] [SKIPPED] pf_loopback_nop
[17:41:23] [SKIPPED] pf_loopback_echo
[17:41:23] [SKIPPED] pf_loopback_fail
[17:41:23] [SKIPPED] pf_loopback_busy
[17:41:23] [SKIPPED] pf_loopback_retry
[17:41:23] ==================== [PASSED] pf_relay =====================
[17:41:23] ================== vf_relay (3 subtests) ===================
[17:41:23] [PASSED] vf_rejects_guc2vf_too_short
[17:41:23] [PASSED] vf_rejects_guc2vf_too_long
[17:41:23] [PASSED] vf_rejects_guc2vf_no_payload
[17:41:23] ==================== [PASSED] vf_relay =====================
[17:41:23] ================ pf_gt_config (9 subtests) =================
[17:41:23] [PASSED] fair_contexts_1vf
[17:41:23] [PASSED] fair_doorbells_1vf
[17:41:23] [PASSED] fair_ggtt_1vf
[17:41:23] ====================== fair_vram_1vf ======================
[17:41:23] [PASSED] 3.50 GiB
[17:41:23] [PASSED] 11.5 GiB
[17:41:23] [PASSED] 15.5 GiB
[17:41:23] [PASSED] 31.5 GiB
[17:41:23] [PASSED] 63.5 GiB
[17:41:23] [PASSED] 1.91 GiB
[17:41:23] ================== [PASSED] fair_vram_1vf ==================
[17:41:23] ================ fair_vram_1vf_admin_only =================
[17:41:23] [PASSED] 3.50 GiB
[17:41:23] [PASSED] 11.5 GiB
[17:41:23] [PASSED] 15.5 GiB
[17:41:23] [PASSED] 31.5 GiB
[17:41:23] [PASSED] 63.5 GiB
[17:41:23] [PASSED] 1.91 GiB
[17:41:23] ============ [PASSED] fair_vram_1vf_admin_only =============
[17:41:23] ====================== fair_contexts ======================
[17:41:23] [PASSED] 1 VF
[17:41:23] [PASSED] 2 VFs
[17:41:23] [PASSED] 3 VFs
[17:41:23] [PASSED] 4 VFs
[17:41:23] [PASSED] 5 VFs
[17:41:23] [PASSED] 6 VFs
[17:41:23] [PASSED] 7 VFs
[17:41:23] [PASSED] 8 VFs
[17:41:23] [PASSED] 9 VFs
[17:41:23] [PASSED] 10 VFs
[17:41:23] [PASSED] 11 VFs
[17:41:23] [PASSED] 12 VFs
[17:41:23] [PASSED] 13 VFs
[17:41:23] [PASSED] 14 VFs
[17:41:23] [PASSED] 15 VFs
[17:41:23] [PASSED] 16 VFs
[17:41:23] [PASSED] 17 VFs
[17:41:23] [PASSED] 18 VFs
[17:41:23] [PASSED] 19 VFs
[17:41:23] [PASSED] 20 VFs
[17:41:23] [PASSED] 21 VFs
[17:41:23] [PASSED] 22 VFs
[17:41:23] [PASSED] 23 VFs
[17:41:23] [PASSED] 24 VFs
[17:41:23] [PASSED] 25 VFs
[17:41:23] [PASSED] 26 VFs
[17:41:23] [PASSED] 27 VFs
[17:41:23] [PASSED] 28 VFs
[17:41:23] [PASSED] 29 VFs
[17:41:23] [PASSED] 30 VFs
[17:41:23] [PASSED] 31 VFs
[17:41:23] [PASSED] 32 VFs
[17:41:23] [PASSED] 33 VFs
[17:41:23] [PASSED] 34 VFs
[17:41:23] [PASSED] 35 VFs
[17:41:23] [PASSED] 36 VFs
[17:41:23] [PASSED] 37 VFs
[17:41:23] [PASSED] 38 VFs
[17:41:23] [PASSED] 39 VFs
[17:41:23] [PASSED] 40 VFs
[17:41:23] [PASSED] 41 VFs
[17:41:23] [PASSED] 42 VFs
[17:41:23] [PASSED] 43 VFs
[17:41:23] [PASSED] 44 VFs
[17:41:23] [PASSED] 45 VFs
[17:41:23] [PASSED] 46 VFs
[17:41:23] [PASSED] 47 VFs
[17:41:23] [PASSED] 48 VFs
[17:41:23] [PASSED] 49 VFs
[17:41:23] [PASSED] 50 VFs
[17:41:23] [PASSED] 51 VFs
[17:41:23] [PASSED] 52 VFs
[17:41:23] [PASSED] 53 VFs
[17:41:23] [PASSED] 54 VFs
[17:41:23] [PASSED] 55 VFs
[17:41:23] [PASSED] 56 VFs
[17:41:23] [PASSED] 57 VFs
[17:41:23] [PASSED] 58 VFs
[17:41:23] [PASSED] 59 VFs
[17:41:23] [PASSED] 60 VFs
[17:41:23] [PASSED] 61 VFs
[17:41:23] [PASSED] 62 VFs
[17:41:23] [PASSED] 63 VFs
[17:41:23] ================== [PASSED] fair_contexts ==================
[17:41:23] ===================== fair_doorbells ======================
[17:41:23] [PASSED] 1 VF
[17:41:23] [PASSED] 2 VFs
[17:41:23] [PASSED] 3 VFs
[17:41:23] [PASSED] 4 VFs
[17:41:23] [PASSED] 5 VFs
[17:41:23] [PASSED] 6 VFs
[17:41:23] [PASSED] 7 VFs
[17:41:23] [PASSED] 8 VFs
[17:41:23] [PASSED] 9 VFs
[17:41:23] [PASSED] 10 VFs
[17:41:23] [PASSED] 11 VFs
[17:41:23] [PASSED] 12 VFs
[17:41:23] [PASSED] 13 VFs
[17:41:23] [PASSED] 14 VFs
[17:41:23] [PASSED] 15 VFs
[17:41:23] [PASSED] 16 VFs
[17:41:23] [PASSED] 17 VFs
[17:41:23] [PASSED] 18 VFs
[17:41:23] [PASSED] 19 VFs
[17:41:23] [PASSED] 20 VFs
[17:41:23] [PASSED] 21 VFs
[17:41:23] [PASSED] 22 VFs
[17:41:23] [PASSED] 23 VFs
[17:41:23] [PASSED] 24 VFs
[17:41:23] [PASSED] 25 VFs
[17:41:23] [PASSED] 26 VFs
[17:41:23] [PASSED] 27 VFs
[17:41:23] [PASSED] 28 VFs
[17:41:23] [PASSED] 29 VFs
[17:41:23] [PASSED] 30 VFs
[17:41:23] [PASSED] 31 VFs
[17:41:23] [PASSED] 32 VFs
[17:41:23] [PASSED] 33 VFs
[17:41:23] [PASSED] 34 VFs
[17:41:23] [PASSED] 35 VFs
[17:41:23] [PASSED] 36 VFs
[17:41:23] [PASSED] 37 VFs
[17:41:23] [PASSED] 38 VFs
[17:41:23] [PASSED] 39 VFs
[17:41:23] [PASSED] 40 VFs
[17:41:23] [PASSED] 41 VFs
[17:41:23] [PASSED] 42 VFs
[17:41:23] [PASSED] 43 VFs
[17:41:23] [PASSED] 44 VFs
[17:41:23] [PASSED] 45 VFs
[17:41:23] [PASSED] 46 VFs
[17:41:23] [PASSED] 47 VFs
[17:41:23] [PASSED] 48 VFs
[17:41:23] [PASSED] 49 VFs
[17:41:24] [PASSED] 50 VFs
[17:41:24] [PASSED] 51 VFs
[17:41:24] [PASSED] 52 VFs
[17:41:24] [PASSED] 53 VFs
[17:41:24] [PASSED] 54 VFs
[17:41:24] [PASSED] 55 VFs
[17:41:24] [PASSED] 56 VFs
[17:41:24] [PASSED] 57 VFs
[17:41:24] [PASSED] 58 VFs
[17:41:24] [PASSED] 59 VFs
[17:41:24] [PASSED] 60 VFs
[17:41:24] [PASSED] 61 VFs
[17:41:24] [PASSED] 62 VFs
[17:41:24] [PASSED] 63 VFs
[17:41:24] ================= [PASSED] fair_doorbells ==================
[17:41:24] ======================== fair_ggtt ========================
[17:41:24] [PASSED] 1 VF
[17:41:24] [PASSED] 2 VFs
[17:41:24] [PASSED] 3 VFs
[17:41:24] [PASSED] 4 VFs
[17:41:24] [PASSED] 5 VFs
[17:41:24] [PASSED] 6 VFs
[17:41:24] [PASSED] 7 VFs
[17:41:24] [PASSED] 8 VFs
[17:41:24] [PASSED] 9 VFs
[17:41:24] [PASSED] 10 VFs
[17:41:24] [PASSED] 11 VFs
[17:41:24] [PASSED] 12 VFs
[17:41:24] [PASSED] 13 VFs
[17:41:24] [PASSED] 14 VFs
[17:41:24] [PASSED] 15 VFs
[17:41:24] [PASSED] 16 VFs
[17:41:24] [PASSED] 17 VFs
[17:41:24] [PASSED] 18 VFs
[17:41:24] [PASSED] 19 VFs
[17:41:24] [PASSED] 20 VFs
[17:41:24] [PASSED] 21 VFs
[17:41:24] [PASSED] 22 VFs
[17:41:24] [PASSED] 23 VFs
[17:41:24] [PASSED] 24 VFs
[17:41:24] [PASSED] 25 VFs
[17:41:24] [PASSED] 26 VFs
[17:41:24] [PASSED] 27 VFs
[17:41:24] [PASSED] 28 VFs
[17:41:24] [PASSED] 29 VFs
[17:41:24] [PASSED] 30 VFs
[17:41:24] [PASSED] 31 VFs
[17:41:24] [PASSED] 32 VFs
[17:41:24] [PASSED] 33 VFs
[17:41:24] [PASSED] 34 VFs
[17:41:24] [PASSED] 35 VFs
[17:41:24] [PASSED] 36 VFs
[17:41:24] [PASSED] 37 VFs
[17:41:24] [PASSED] 38 VFs
[17:41:24] [PASSED] 39 VFs
[17:41:24] [PASSED] 40 VFs
[17:41:24] [PASSED] 41 VFs
[17:41:24] [PASSED] 42 VFs
[17:41:24] [PASSED] 43 VFs
[17:41:24] [PASSED] 44 VFs
[17:41:24] [PASSED] 45 VFs
[17:41:24] [PASSED] 46 VFs
[17:41:24] [PASSED] 47 VFs
[17:41:24] [PASSED] 48 VFs
[17:41:24] [PASSED] 49 VFs
[17:41:24] [PASSED] 50 VFs
[17:41:24] [PASSED] 51 VFs
[17:41:24] [PASSED] 52 VFs
[17:41:24] [PASSED] 53 VFs
[17:41:24] [PASSED] 54 VFs
[17:41:24] [PASSED] 55 VFs
[17:41:24] [PASSED] 56 VFs
[17:41:24] [PASSED] 57 VFs
[17:41:24] [PASSED] 58 VFs
[17:41:24] [PASSED] 59 VFs
[17:41:24] [PASSED] 60 VFs
[17:41:24] [PASSED] 61 VFs
[17:41:24] [PASSED] 62 VFs
[17:41:24] [PASSED] 63 VFs
[17:41:24] ==================== [PASSED] fair_ggtt ====================
[17:41:24] ======================== fair_vram ========================
[17:41:24] [PASSED] 1 VF
[17:41:24] [PASSED] 2 VFs
[17:41:24] [PASSED] 3 VFs
[17:41:24] [PASSED] 4 VFs
[17:41:24] [PASSED] 5 VFs
[17:41:24] [PASSED] 6 VFs
[17:41:24] [PASSED] 7 VFs
[17:41:24] [PASSED] 8 VFs
[17:41:24] [PASSED] 9 VFs
[17:41:24] [PASSED] 10 VFs
[17:41:24] [PASSED] 11 VFs
[17:41:24] [PASSED] 12 VFs
[17:41:24] [PASSED] 13 VFs
[17:41:24] [PASSED] 14 VFs
[17:41:24] [PASSED] 15 VFs
[17:41:24] [PASSED] 16 VFs
[17:41:24] [PASSED] 17 VFs
[17:41:24] [PASSED] 18 VFs
[17:41:24] [PASSED] 19 VFs
[17:41:24] [PASSED] 20 VFs
[17:41:24] [PASSED] 21 VFs
[17:41:24] [PASSED] 22 VFs
[17:41:24] [PASSED] 23 VFs
[17:41:24] [PASSED] 24 VFs
[17:41:24] [PASSED] 25 VFs
[17:41:24] [PASSED] 26 VFs
[17:41:24] [PASSED] 27 VFs
[17:41:24] [PASSED] 28 VFs
[17:41:24] [PASSED] 29 VFs
[17:41:24] [PASSED] 30 VFs
[17:41:24] [PASSED] 31 VFs
[17:41:24] [PASSED] 32 VFs
[17:41:24] [PASSED] 33 VFs
[17:41:24] [PASSED] 34 VFs
[17:41:24] [PASSED] 35 VFs
[17:41:24] [PASSED] 36 VFs
[17:41:24] [PASSED] 37 VFs
[17:41:24] [PASSED] 38 VFs
[17:41:24] [PASSED] 39 VFs
[17:41:24] [PASSED] 40 VFs
[17:41:24] [PASSED] 41 VFs
[17:41:24] [PASSED] 42 VFs
[17:41:24] [PASSED] 43 VFs
[17:41:24] [PASSED] 44 VFs
[17:41:24] [PASSED] 45 VFs
[17:41:24] [PASSED] 46 VFs
[17:41:24] [PASSED] 47 VFs
[17:41:24] [PASSED] 48 VFs
[17:41:24] [PASSED] 49 VFs
[17:41:24] [PASSED] 50 VFs
[17:41:24] [PASSED] 51 VFs
[17:41:24] [PASSED] 52 VFs
[17:41:24] [PASSED] 53 VFs
[17:41:24] [PASSED] 54 VFs
[17:41:24] [PASSED] 55 VFs
[17:41:24] [PASSED] 56 VFs
[17:41:24] [PASSED] 57 VFs
[17:41:24] [PASSED] 58 VFs
[17:41:24] [PASSED] 59 VFs
[17:41:24] [PASSED] 60 VFs
[17:41:24] [PASSED] 61 VFs
[17:41:24] [PASSED] 62 VFs
[17:41:24] [PASSED] 63 VFs
[17:41:24] ==================== [PASSED] fair_vram ====================
[17:41:24] ================== [PASSED] pf_gt_config ===================
[17:41:24] ===================== lmtt (1 subtest) =====================
[17:41:24] ======================== test_ops =========================
[17:41:24] [PASSED] 2-level
[17:41:24] [PASSED] multi-level
[17:41:24] ==================== [PASSED] test_ops =====================
[17:41:24] ====================== [PASSED] lmtt =======================
[17:41:24] ================= pf_service (11 subtests) =================
[17:41:24] [PASSED] pf_negotiate_any
[17:41:24] [PASSED] pf_negotiate_base_match
[17:41:24] [PASSED] pf_negotiate_base_newer
[17:41:24] [PASSED] pf_negotiate_base_next
[17:41:24] [SKIPPED] pf_negotiate_base_older
[17:41:24] [PASSED] pf_negotiate_base_prev
[17:41:24] [PASSED] pf_negotiate_latest_match
[17:41:24] [PASSED] pf_negotiate_latest_newer
[17:41:24] [PASSED] pf_negotiate_latest_next
[17:41:24] [SKIPPED] pf_negotiate_latest_older
[17:41:24] [SKIPPED] pf_negotiate_latest_prev
[17:41:24] =================== [PASSED] pf_service ====================
[17:41:24] ================= xe_guc_g2g (2 subtests) ==================
[17:41:24] ============== xe_live_guc_g2g_kunit_default ==============
[17:41:24] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[17:41:24] ============== xe_live_guc_g2g_kunit_allmem ===============
[17:41:24] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[17:41:24] =================== [SKIPPED] xe_guc_g2g ===================
[17:41:24] =================== xe_mocs (2 subtests) ===================
[17:41:24] ================ xe_live_mocs_kernel_kunit ================
[17:41:24] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[17:41:24] ================ xe_live_mocs_reset_kunit =================
[17:41:24] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[17:41:24] ==================== [SKIPPED] xe_mocs =====================
[17:41:24] ================= xe_migrate (2 subtests) ==================
[17:41:24] ================= xe_migrate_sanity_kunit =================
[17:41:24] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[17:41:24] ================== xe_validate_ccs_kunit ==================
[17:41:24] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[17:41:24] =================== [SKIPPED] xe_migrate ===================
[17:41:24] ================== xe_dma_buf (1 subtest) ==================
[17:41:24] ==================== xe_dma_buf_kunit =====================
[17:41:24] ================ [SKIPPED] xe_dma_buf_kunit ================
[17:41:24] =================== [SKIPPED] xe_dma_buf ===================
[17:41:24] ================= xe_bo_shrink (1 subtest) =================
[17:41:24] =================== xe_bo_shrink_kunit ====================
[17:41:24] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[17:41:24] ================== [SKIPPED] xe_bo_shrink ==================
[17:41:24] ==================== xe_bo (2 subtests) ====================
[17:41:24] ================== xe_ccs_migrate_kunit ===================
[17:41:24] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[17:41:24] ==================== xe_bo_evict_kunit ====================
[17:41:24] =============== [SKIPPED] xe_bo_evict_kunit ================
[17:41:24] ===================== [SKIPPED] xe_bo ======================
[17:41:24] ==================== args (13 subtests) ====================
[17:41:24] [PASSED] count_args_test
[17:41:24] [PASSED] call_args_example
[17:41:24] [PASSED] call_args_test
[17:41:24] [PASSED] drop_first_arg_example
[17:41:24] [PASSED] drop_first_arg_test
[17:41:24] [PASSED] first_arg_example
[17:41:24] [PASSED] first_arg_test
[17:41:24] [PASSED] last_arg_example
[17:41:24] [PASSED] last_arg_test
[17:41:24] [PASSED] pick_arg_example
[17:41:24] [PASSED] if_args_example
[17:41:24] [PASSED] if_args_test
[17:41:24] [PASSED] sep_comma_example
[17:41:24] ====================== [PASSED] args =======================
[17:41:24] =================== xe_pci (3 subtests) ====================
[17:41:24] ==================== check_graphics_ip ====================
[17:41:24] [PASSED] 12.00 Xe_LP
[17:41:24] [PASSED] 12.10 Xe_LP+
[17:41:24] [PASSED] 12.55 Xe_HPG
[17:41:24] [PASSED] 12.60 Xe_HPC
[17:41:24] [PASSED] 12.70 Xe_LPG
[17:41:24] [PASSED] 12.71 Xe_LPG
[17:41:24] [PASSED] 12.74 Xe_LPG+
[17:41:24] [PASSED] 20.01 Xe2_HPG
[17:41:24] [PASSED] 20.02 Xe2_HPG
[17:41:24] [PASSED] 20.04 Xe2_LPG
[17:41:24] [PASSED] 30.00 Xe3_LPG
[17:41:24] [PASSED] 30.01 Xe3_LPG
[17:41:24] [PASSED] 30.03 Xe3_LPG
[17:41:24] [PASSED] 30.04 Xe3_LPG
[17:41:24] [PASSED] 30.05 Xe3_LPG
[17:41:24] [PASSED] 35.10 Xe3p_LPG
[17:41:24] [PASSED] 35.11 Xe3p_XPC
[17:41:24] ================ [PASSED] check_graphics_ip ================
[17:41:24] ===================== check_media_ip ======================
[17:41:24] [PASSED] 12.00 Xe_M
[17:41:24] [PASSED] 12.55 Xe_HPM
[17:41:24] [PASSED] 13.00 Xe_LPM+
[17:41:24] [PASSED] 13.01 Xe2_HPM
[17:41:24] [PASSED] 20.00 Xe2_LPM
[17:41:24] [PASSED] 30.00 Xe3_LPM
[17:41:24] [PASSED] 30.02 Xe3_LPM
[17:41:24] [PASSED] 35.00 Xe3p_LPM
[17:41:24] [PASSED] 35.03 Xe3p_HPM
[17:41:24] ================= [PASSED] check_media_ip ==================
[17:41:24] =================== check_platform_desc ===================
[17:41:24] [PASSED] 0x9A60 (TIGERLAKE)
[17:41:24] [PASSED] 0x9A68 (TIGERLAKE)
[17:41:24] [PASSED] 0x9A70 (TIGERLAKE)
[17:41:24] [PASSED] 0x9A40 (TIGERLAKE)
[17:41:24] [PASSED] 0x9A49 (TIGERLAKE)
[17:41:24] [PASSED] 0x9A59 (TIGERLAKE)
[17:41:24] [PASSED] 0x9A78 (TIGERLAKE)
[17:41:24] [PASSED] 0x9AC0 (TIGERLAKE)
[17:41:24] [PASSED] 0x9AC9 (TIGERLAKE)
[17:41:24] [PASSED] 0x9AD9 (TIGERLAKE)
[17:41:24] [PASSED] 0x9AF8 (TIGERLAKE)
[17:41:24] [PASSED] 0x4C80 (ROCKETLAKE)
[17:41:24] [PASSED] 0x4C8A (ROCKETLAKE)
[17:41:24] [PASSED] 0x4C8B (ROCKETLAKE)
[17:41:24] [PASSED] 0x4C8C (ROCKETLAKE)
[17:41:24] [PASSED] 0x4C90 (ROCKETLAKE)
[17:41:24] [PASSED] 0x4C9A (ROCKETLAKE)
[17:41:24] [PASSED] 0x4680 (ALDERLAKE_S)
[17:41:24] [PASSED] 0x4682 (ALDERLAKE_S)
[17:41:24] [PASSED] 0x4688 (ALDERLAKE_S)
[17:41:24] [PASSED] 0x468A (ALDERLAKE_S)
[17:41:24] [PASSED] 0x468B (ALDERLAKE_S)
[17:41:24] [PASSED] 0x4690 (ALDERLAKE_S)
[17:41:24] [PASSED] 0x4692 (ALDERLAKE_S)
[17:41:24] [PASSED] 0x4693 (ALDERLAKE_S)
[17:41:24] [PASSED] 0x46A0 (ALDERLAKE_P)
[17:41:24] [PASSED] 0x46A1 (ALDERLAKE_P)
[17:41:24] [PASSED] 0x46A2 (ALDERLAKE_P)
[17:41:24] [PASSED] 0x46A3 (ALDERLAKE_P)
[17:41:24] [PASSED] 0x46A6 (ALDERLAKE_P)
[17:41:24] [PASSED] 0x46A8 (ALDERLAKE_P)
[17:41:24] [PASSED] 0x46AA (ALDERLAKE_P)
[17:41:24] [PASSED] 0x462A (ALDERLAKE_P)
[17:41:24] [PASSED] 0x4626 (ALDERLAKE_P)
[17:41:24] [PASSED] 0x4628 (ALDERLAKE_P)
[17:41:24] [PASSED] 0x46B0 (ALDERLAKE_P)
[17:41:24] [PASSED] 0x46B1 (ALDERLAKE_P)
[17:41:24] [PASSED] 0x46B2 (ALDERLAKE_P)
[17:41:24] [PASSED] 0x46B3 (ALDERLAKE_P)
[17:41:24] [PASSED] 0x46C0 (ALDERLAKE_P)
[17:41:24] [PASSED] 0x46C1 (ALDERLAKE_P)
[17:41:24] [PASSED] 0x46C2 (ALDERLAKE_P)
[17:41:24] [PASSED] 0x46C3 (ALDERLAKE_P)
[17:41:24] [PASSED] 0x46D0 (ALDERLAKE_N)
[17:41:24] [PASSED] 0x46D1 (ALDERLAKE_N)
[17:41:24] [PASSED] 0x46D2 (ALDERLAKE_N)
[17:41:24] [PASSED] 0x46D3 (ALDERLAKE_N)
[17:41:24] [PASSED] 0x46D4 (ALDERLAKE_N)
[17:41:24] [PASSED] 0xA721 (ALDERLAKE_P)
[17:41:24] [PASSED] 0xA7A1 (ALDERLAKE_P)
[17:41:24] [PASSED] 0xA7A9 (ALDERLAKE_P)
[17:41:24] [PASSED] 0xA7AC (ALDERLAKE_P)
[17:41:24] [PASSED] 0xA7AD (ALDERLAKE_P)
[17:41:24] [PASSED] 0xA720 (ALDERLAKE_P)
[17:41:24] [PASSED] 0xA7A0 (ALDERLAKE_P)
[17:41:24] [PASSED] 0xA7A8 (ALDERLAKE_P)
[17:41:24] [PASSED] 0xA7AA (ALDERLAKE_P)
[17:41:24] [PASSED] 0xA7AB (ALDERLAKE_P)
[17:41:24] [PASSED] 0xA780 (ALDERLAKE_S)
[17:41:24] [PASSED] 0xA781 (ALDERLAKE_S)
[17:41:24] [PASSED] 0xA782 (ALDERLAKE_S)
[17:41:24] [PASSED] 0xA783 (ALDERLAKE_S)
[17:41:24] [PASSED] 0xA788 (ALDERLAKE_S)
[17:41:24] [PASSED] 0xA789 (ALDERLAKE_S)
[17:41:24] [PASSED] 0xA78A (ALDERLAKE_S)
[17:41:24] [PASSED] 0xA78B (ALDERLAKE_S)
[17:41:24] [PASSED] 0x4905 (DG1)
[17:41:24] [PASSED] 0x4906 (DG1)
[17:41:24] [PASSED] 0x4907 (DG1)
[17:41:24] [PASSED] 0x4908 (DG1)
[17:41:24] [PASSED] 0x4909 (DG1)
[17:41:24] [PASSED] 0x56C0 (DG2)
[17:41:24] [PASSED] 0x56C2 (DG2)
[17:41:24] [PASSED] 0x56C1 (DG2)
[17:41:24] [PASSED] 0x7D51 (METEORLAKE)
[17:41:24] [PASSED] 0x7DD1 (METEORLAKE)
[17:41:24] [PASSED] 0x7D41 (METEORLAKE)
[17:41:24] [PASSED] 0x7D67 (METEORLAKE)
[17:41:24] [PASSED] 0xB640 (METEORLAKE)
[17:41:24] [PASSED] 0x56A0 (DG2)
[17:41:24] [PASSED] 0x56A1 (DG2)
[17:41:24] [PASSED] 0x56A2 (DG2)
[17:41:24] [PASSED] 0x56BE (DG2)
[17:41:24] [PASSED] 0x56BF (DG2)
[17:41:24] [PASSED] 0x5690 (DG2)
[17:41:24] [PASSED] 0x5691 (DG2)
[17:41:24] [PASSED] 0x5692 (DG2)
[17:41:24] [PASSED] 0x56A5 (DG2)
[17:41:24] [PASSED] 0x56A6 (DG2)
[17:41:24] [PASSED] 0x56B0 (DG2)
[17:41:24] [PASSED] 0x56B1 (DG2)
[17:41:24] [PASSED] 0x56BA (DG2)
[17:41:24] [PASSED] 0x56BB (DG2)
[17:41:24] [PASSED] 0x56BC (DG2)
[17:41:24] [PASSED] 0x56BD (DG2)
[17:41:24] [PASSED] 0x5693 (DG2)
[17:41:24] [PASSED] 0x5694 (DG2)
[17:41:24] [PASSED] 0x5695 (DG2)
[17:41:24] [PASSED] 0x56A3 (DG2)
[17:41:24] [PASSED] 0x56A4 (DG2)
[17:41:24] [PASSED] 0x56B2 (DG2)
[17:41:24] [PASSED] 0x56B3 (DG2)
[17:41:24] [PASSED] 0x5696 (DG2)
[17:41:24] [PASSED] 0x5697 (DG2)
[17:41:24] [PASSED] 0xB69 (PVC)
[17:41:24] [PASSED] 0xB6E (PVC)
[17:41:24] [PASSED] 0xBD4 (PVC)
[17:41:24] [PASSED] 0xBD5 (PVC)
[17:41:24] [PASSED] 0xBD6 (PVC)
[17:41:24] [PASSED] 0xBD7 (PVC)
[17:41:24] [PASSED] 0xBD8 (PVC)
[17:41:24] [PASSED] 0xBD9 (PVC)
[17:41:24] [PASSED] 0xBDA (PVC)
[17:41:24] [PASSED] 0xBDB (PVC)
[17:41:24] [PASSED] 0xBE0 (PVC)
[17:41:24] [PASSED] 0xBE1 (PVC)
[17:41:24] [PASSED] 0xBE5 (PVC)
[17:41:24] [PASSED] 0x7D40 (METEORLAKE)
[17:41:24] [PASSED] 0x7D45 (METEORLAKE)
[17:41:24] [PASSED] 0x7D55 (METEORLAKE)
[17:41:24] [PASSED] 0x7D60 (METEORLAKE)
[17:41:24] [PASSED] 0x7DD5 (METEORLAKE)
[17:41:24] [PASSED] 0x6420 (LUNARLAKE)
[17:41:24] [PASSED] 0x64A0 (LUNARLAKE)
[17:41:24] [PASSED] 0x64B0 (LUNARLAKE)
[17:41:24] [PASSED] 0xE202 (BATTLEMAGE)
[17:41:24] [PASSED] 0xE209 (BATTLEMAGE)
[17:41:24] [PASSED] 0xE20B (BATTLEMAGE)
[17:41:24] [PASSED] 0xE20C (BATTLEMAGE)
[17:41:24] [PASSED] 0xE20D (BATTLEMAGE)
[17:41:24] [PASSED] 0xE210 (BATTLEMAGE)
[17:41:24] [PASSED] 0xE211 (BATTLEMAGE)
[17:41:24] [PASSED] 0xE212 (BATTLEMAGE)
[17:41:24] [PASSED] 0xE216 (BATTLEMAGE)
[17:41:24] [PASSED] 0xE220 (BATTLEMAGE)
[17:41:24] [PASSED] 0xE221 (BATTLEMAGE)
[17:41:24] [PASSED] 0xE222 (BATTLEMAGE)
[17:41:24] [PASSED] 0xE223 (BATTLEMAGE)
[17:41:24] [PASSED] 0xB080 (PANTHERLAKE)
[17:41:24] [PASSED] 0xB081 (PANTHERLAKE)
[17:41:24] [PASSED] 0xB082 (PANTHERLAKE)
[17:41:24] [PASSED] 0xB083 (PANTHERLAKE)
[17:41:24] [PASSED] 0xB084 (PANTHERLAKE)
[17:41:24] [PASSED] 0xB085 (PANTHERLAKE)
[17:41:24] [PASSED] 0xB086 (PANTHERLAKE)
[17:41:24] [PASSED] 0xB087 (PANTHERLAKE)
[17:41:24] [PASSED] 0xB08F (PANTHERLAKE)
[17:41:24] [PASSED] 0xB090 (PANTHERLAKE)
[17:41:24] [PASSED] 0xB0A0 (PANTHERLAKE)
[17:41:24] [PASSED] 0xB0B0 (PANTHERLAKE)
[17:41:24] [PASSED] 0xFD80 (PANTHERLAKE)
[17:41:24] [PASSED] 0xFD81 (PANTHERLAKE)
[17:41:24] [PASSED] 0xD740 (NOVALAKE_S)
[17:41:24] [PASSED] 0xD741 (NOVALAKE_S)
[17:41:24] [PASSED] 0xD742 (NOVALAKE_S)
[17:41:24] [PASSED] 0xD743 (NOVALAKE_S)
[17:41:24] [PASSED] 0xD744 (NOVALAKE_S)
[17:41:24] [PASSED] 0xD745 (NOVALAKE_S)
[17:41:24] [PASSED] 0x674C (CRESCENTISLAND)
[17:41:24] [PASSED] 0x674D (CRESCENTISLAND)
[17:41:24] [PASSED] 0x674E (CRESCENTISLAND)
[17:41:24] [PASSED] 0x674F (CRESCENTISLAND)
[17:41:24] [PASSED] 0x6750 (CRESCENTISLAND)
[17:41:24] [PASSED] 0xD750 (NOVALAKE_P)
[17:41:24] [PASSED] 0xD751 (NOVALAKE_P)
[17:41:24] [PASSED] 0xD752 (NOVALAKE_P)
[17:41:24] [PASSED] 0xD753 (NOVALAKE_P)
[17:41:24] [PASSED] 0xD754 (NOVALAKE_P)
[17:41:24] [PASSED] 0xD755 (NOVALAKE_P)
[17:41:24] [PASSED] 0xD756 (NOVALAKE_P)
[17:41:24] [PASSED] 0xD757 (NOVALAKE_P)
[17:41:24] [PASSED] 0xD75F (NOVALAKE_P)
[17:41:24] =============== [PASSED] check_platform_desc ===============
[17:41:24] ===================== [PASSED] xe_pci ======================
[17:41:24] =================== xe_rtp (3 subtests) ====================
[17:41:24] =================== xe_rtp_rules_tests ====================
[17:41:24] [PASSED] no
[17:41:24] [PASSED] yes
[17:41:24] [PASSED] no-and-no
[17:41:24] [PASSED] no-and-yes
[17:41:24] [PASSED] yes-and-no
[17:41:24] [PASSED] yes-and-yes
[17:41:24] [PASSED] no-or-no
[17:41:24] [PASSED] no-or-yes
[17:41:24] [PASSED] yes-or-no
[17:41:24] [PASSED] yes-or-yes
[17:41:24] [PASSED] no-yes-or-yes-no
[17:41:24] [PASSED] no-yes-or-yes-yes
[17:41:24] [PASSED] yes-yes-or-no-yes
[17:41:24] [PASSED] yes-yes-or-yes-yes
[17:41:24] [PASSED] no-no-or-yes-or-no
[17:41:24] [PASSED] or
[17:41:24] [PASSED] or-yes
[17:41:24] [PASSED] or-no
[17:41:24] [PASSED] yes-or
[17:41:24] [PASSED] no-or
[17:41:24] [PASSED] no-or-or-yes
[17:41:24] [PASSED] yes-or-or-no
[17:41:24] [PASSED] no-or-or-no
[17:41:24] [PASSED] missing-context-engine-class
[17:41:24] [PASSED] missing-context-engine-class-or-yes
[17:41:24] [PASSED] missing-context-engine-class-or-or-yes
[17:41:24] =============== [PASSED] xe_rtp_rules_tests ================
[17:41:24] =============== xe_rtp_process_to_sr_tests ================
[17:41:24] [PASSED] coalesce-same-reg
[17:41:24] [PASSED] no-match-no-add
[17:41:24] [PASSED] two-regs-two-entries
[17:41:24] [PASSED] clr-one-set-other
[17:41:24] [PASSED] set-field
[17:41:24] [PASSED] conflict-duplicate
[17:41:24] [PASSED] conflict-not-disjoint
[17:41:24] [PASSED] conflict-reg-type
[17:41:24] [PASSED] bad-mcr-reg-forced-to-regular
[17:41:24] [PASSED] bad-regular-reg-forced-to-mcr
[17:41:24] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[17:41:24] ================== xe_rtp_process_tests ===================
[17:41:24] [PASSED] active1
[17:41:24] [PASSED] active2
[17:41:24] [PASSED] active-inactive
[17:41:24] [PASSED] inactive-active
[17:41:24] [PASSED] inactive-active-inactive
[17:41:24] [PASSED] inactive-inactive-inactive
[17:41:24] ============== [PASSED] xe_rtp_process_tests ===============
[17:41:24] ===================== [PASSED] xe_rtp ======================
[17:41:24] ==================== xe_wa (1 subtest) =====================
[17:41:24] ======================== xe_wa_gt =========================
[17:41:24] [PASSED] TIGERLAKE B0
[17:41:24] [PASSED] DG1 A0
[17:41:24] [PASSED] DG1 B0
[17:41:24] [PASSED] ALDERLAKE_S A0
[17:41:24] [PASSED] ALDERLAKE_S B0
[17:41:24] [PASSED] ALDERLAKE_S C0
[17:41:24] [PASSED] ALDERLAKE_S D0
[17:41:24] [PASSED] ALDERLAKE_P A0
[17:41:24] [PASSED] ALDERLAKE_P B0
[17:41:24] [PASSED] ALDERLAKE_P C0
[17:41:24] [PASSED] ALDERLAKE_S RPLS D0
[17:41:24] [PASSED] ALDERLAKE_P RPLU E0
[17:41:24] [PASSED] DG2 G10 C0
[17:41:24] [PASSED] DG2 G11 B1
[17:41:24] [PASSED] DG2 G12 A1
[17:41:24] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:41:24] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:41:24] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[17:41:24] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[17:41:24] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[17:41:24] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[17:41:24] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[17:41:24] ==================== [PASSED] xe_wa_gt =====================
[17:41:24] ====================== [PASSED] xe_wa ======================
[17:41:24] ============================================================
[17:41:24] Testing complete. Ran 624 tests: passed: 606, skipped: 18
[17:41:24] Elapsed time: 36.350s total, 4.300s configuring, 31.385s building, 0.628s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[17:41:24] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:41:26] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:41:50] Starting KUnit Kernel (1/1)...
[17:41:50] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:41:50] ============ drm_test_pick_cmdline (2 subtests) ============
[17:41:50] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[17:41:50] =============== drm_test_pick_cmdline_named ===============
[17:41:50] [PASSED] NTSC
[17:41:50] [PASSED] NTSC-J
[17:41:50] [PASSED] PAL
[17:41:50] [PASSED] PAL-M
[17:41:50] =========== [PASSED] drm_test_pick_cmdline_named ===========
[17:41:50] ============== [PASSED] drm_test_pick_cmdline ==============
[17:41:50] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[17:41:50] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[17:41:50] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[17:41:50] =========== drm_validate_clone_mode (2 subtests) ===========
[17:41:50] ============== drm_test_check_in_clone_mode ===============
[17:41:50] [PASSED] in_clone_mode
[17:41:50] [PASSED] not_in_clone_mode
[17:41:50] ========== [PASSED] drm_test_check_in_clone_mode ===========
[17:41:50] =============== drm_test_check_valid_clones ===============
[17:41:50] [PASSED] not_in_clone_mode
[17:41:50] [PASSED] valid_clone
[17:41:50] [PASSED] invalid_clone
[17:41:50] =========== [PASSED] drm_test_check_valid_clones ===========
[17:41:50] ============= [PASSED] drm_validate_clone_mode =============
[17:41:50] ============= drm_validate_modeset (1 subtest) =============
[17:41:50] [PASSED] drm_test_check_connector_changed_modeset
[17:41:50] ============== [PASSED] drm_validate_modeset ===============
[17:41:50] ====== drm_test_bridge_get_current_state (2 subtests) ======
[17:41:50] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[17:41:50] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[17:41:50] ======== [PASSED] drm_test_bridge_get_current_state ========
[17:41:50] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[17:41:50] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[17:41:50] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[17:41:50] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[17:41:50] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[17:41:50] ============== drm_bridge_alloc (2 subtests) ===============
[17:41:50] [PASSED] drm_test_drm_bridge_alloc_basic
[17:41:50] [PASSED] drm_test_drm_bridge_alloc_get_put
[17:41:50] ================ [PASSED] drm_bridge_alloc =================
[17:41:50] ============= drm_cmdline_parser (40 subtests) =============
[17:41:50] [PASSED] drm_test_cmdline_force_d_only
[17:41:50] [PASSED] drm_test_cmdline_force_D_only_dvi
[17:41:50] [PASSED] drm_test_cmdline_force_D_only_hdmi
[17:41:50] [PASSED] drm_test_cmdline_force_D_only_not_digital
[17:41:50] [PASSED] drm_test_cmdline_force_e_only
[17:41:50] [PASSED] drm_test_cmdline_res
[17:41:50] [PASSED] drm_test_cmdline_res_vesa
[17:41:50] [PASSED] drm_test_cmdline_res_vesa_rblank
[17:41:50] [PASSED] drm_test_cmdline_res_rblank
[17:41:50] [PASSED] drm_test_cmdline_res_bpp
[17:41:50] [PASSED] drm_test_cmdline_res_refresh
[17:41:50] [PASSED] drm_test_cmdline_res_bpp_refresh
[17:41:50] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[17:41:50] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[17:41:50] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[17:41:50] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[17:41:50] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[17:41:50] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[17:41:50] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[17:41:50] [PASSED] drm_test_cmdline_res_margins_force_on
[17:41:50] [PASSED] drm_test_cmdline_res_vesa_margins
[17:41:50] [PASSED] drm_test_cmdline_name
[17:41:50] [PASSED] drm_test_cmdline_name_bpp
[17:41:50] [PASSED] drm_test_cmdline_name_option
[17:41:50] [PASSED] drm_test_cmdline_name_bpp_option
[17:41:50] [PASSED] drm_test_cmdline_rotate_0
[17:41:50] [PASSED] drm_test_cmdline_rotate_90
[17:41:50] [PASSED] drm_test_cmdline_rotate_180
[17:41:50] [PASSED] drm_test_cmdline_rotate_270
[17:41:50] [PASSED] drm_test_cmdline_hmirror
[17:41:50] [PASSED] drm_test_cmdline_vmirror
[17:41:50] [PASSED] drm_test_cmdline_margin_options
[17:41:50] [PASSED] drm_test_cmdline_multiple_options
[17:41:50] [PASSED] drm_test_cmdline_bpp_extra_and_option
[17:41:50] [PASSED] drm_test_cmdline_extra_and_option
[17:41:50] [PASSED] drm_test_cmdline_freestanding_options
[17:41:50] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[17:41:50] [PASSED] drm_test_cmdline_panel_orientation
[17:41:50] ================ drm_test_cmdline_invalid =================
[17:41:50] [PASSED] margin_only
[17:41:50] [PASSED] interlace_only
[17:41:50] [PASSED] res_missing_x
[17:41:50] [PASSED] res_missing_y
[17:41:50] [PASSED] res_bad_y
[17:41:50] [PASSED] res_missing_y_bpp
[17:41:50] [PASSED] res_bad_bpp
[17:41:50] [PASSED] res_bad_refresh
[17:41:50] [PASSED] res_bpp_refresh_force_on_off
[17:41:50] [PASSED] res_invalid_mode
[17:41:50] [PASSED] res_bpp_wrong_place_mode
[17:41:50] [PASSED] name_bpp_refresh
[17:41:50] [PASSED] name_refresh
[17:41:50] [PASSED] name_refresh_wrong_mode
[17:41:50] [PASSED] name_refresh_invalid_mode
[17:41:50] [PASSED] rotate_multiple
[17:41:50] [PASSED] rotate_invalid_val
[17:41:50] [PASSED] rotate_truncated
[17:41:50] [PASSED] invalid_option
[17:41:50] [PASSED] invalid_tv_option
[17:41:50] [PASSED] truncated_tv_option
[17:41:50] ============ [PASSED] drm_test_cmdline_invalid =============
[17:41:50] =============== drm_test_cmdline_tv_options ===============
[17:41:50] [PASSED] NTSC
[17:41:50] [PASSED] NTSC_443
[17:41:50] [PASSED] NTSC_J
[17:41:50] [PASSED] PAL
[17:41:50] [PASSED] PAL_M
[17:41:50] [PASSED] PAL_N
[17:41:50] [PASSED] SECAM
[17:41:50] [PASSED] MONO_525
[17:41:50] [PASSED] MONO_625
[17:41:50] =========== [PASSED] drm_test_cmdline_tv_options ===========
[17:41:50] =============== [PASSED] drm_cmdline_parser ================
[17:41:50] ========== drmm_connector_hdmi_init (20 subtests) ==========
[17:41:50] [PASSED] drm_test_connector_hdmi_init_valid
[17:41:50] [PASSED] drm_test_connector_hdmi_init_bpc_8
[17:41:50] [PASSED] drm_test_connector_hdmi_init_bpc_10
[17:41:50] [PASSED] drm_test_connector_hdmi_init_bpc_12
[17:41:50] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[17:41:50] [PASSED] drm_test_connector_hdmi_init_bpc_null
[17:41:50] [PASSED] drm_test_connector_hdmi_init_formats_empty
[17:41:50] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[17:41:50] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[17:41:50] [PASSED] supported_formats=0x9 yuv420_allowed=1
[17:41:50] [PASSED] supported_formats=0x9 yuv420_allowed=0
[17:41:50] [PASSED] supported_formats=0x5 yuv420_allowed=1
[17:41:50] [PASSED] supported_formats=0x5 yuv420_allowed=0
[17:41:50] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[17:41:50] [PASSED] drm_test_connector_hdmi_init_null_ddc
[17:41:50] [PASSED] drm_test_connector_hdmi_init_null_product
[17:41:50] [PASSED] drm_test_connector_hdmi_init_null_vendor
[17:41:50] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[17:41:50] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[17:41:50] [PASSED] drm_test_connector_hdmi_init_product_valid
[17:41:50] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[17:41:50] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[17:41:50] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[17:41:50] ========= drm_test_connector_hdmi_init_type_valid =========
[17:41:50] [PASSED] HDMI-A
[17:41:50] [PASSED] HDMI-B
[17:41:50] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[17:41:50] ======== drm_test_connector_hdmi_init_type_invalid ========
[17:41:50] [PASSED] Unknown
[17:41:50] [PASSED] VGA
[17:41:50] [PASSED] DVI-I
[17:41:50] [PASSED] DVI-D
[17:41:50] [PASSED] DVI-A
[17:41:50] [PASSED] Composite
[17:41:50] [PASSED] SVIDEO
[17:41:50] [PASSED] LVDS
[17:41:50] [PASSED] Component
[17:41:50] [PASSED] DIN
[17:41:50] [PASSED] DP
[17:41:50] [PASSED] TV
[17:41:50] [PASSED] eDP
[17:41:50] [PASSED] Virtual
[17:41:50] [PASSED] DSI
[17:41:50] [PASSED] DPI
[17:41:50] [PASSED] Writeback
[17:41:50] [PASSED] SPI
[17:41:50] [PASSED] USB
[17:41:50] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[17:41:50] ============ [PASSED] drmm_connector_hdmi_init =============
[17:41:50] ============= drmm_connector_init (3 subtests) =============
[17:41:50] [PASSED] drm_test_drmm_connector_init
[17:41:50] [PASSED] drm_test_drmm_connector_init_null_ddc
[17:41:50] ========= drm_test_drmm_connector_init_type_valid =========
[17:41:50] [PASSED] Unknown
[17:41:50] [PASSED] VGA
[17:41:50] [PASSED] DVI-I
[17:41:50] [PASSED] DVI-D
[17:41:50] [PASSED] DVI-A
[17:41:50] [PASSED] Composite
[17:41:50] [PASSED] SVIDEO
[17:41:50] [PASSED] LVDS
[17:41:50] [PASSED] Component
[17:41:50] [PASSED] DIN
[17:41:50] [PASSED] DP
[17:41:50] [PASSED] HDMI-A
[17:41:50] [PASSED] HDMI-B
[17:41:50] [PASSED] TV
[17:41:50] [PASSED] eDP
[17:41:50] [PASSED] Virtual
[17:41:50] [PASSED] DSI
[17:41:50] [PASSED] DPI
[17:41:50] [PASSED] Writeback
[17:41:50] [PASSED] SPI
[17:41:50] [PASSED] USB
[17:41:50] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[17:41:50] =============== [PASSED] drmm_connector_init ===============
[17:41:50] ========= drm_connector_dynamic_init (6 subtests) ==========
[17:41:50] [PASSED] drm_test_drm_connector_dynamic_init
[17:41:50] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[17:41:50] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[17:41:50] [PASSED] drm_test_drm_connector_dynamic_init_properties
[17:41:50] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[17:41:50] [PASSED] Unknown
[17:41:50] [PASSED] VGA
[17:41:50] [PASSED] DVI-I
[17:41:50] [PASSED] DVI-D
[17:41:50] [PASSED] DVI-A
[17:41:50] [PASSED] Composite
[17:41:50] [PASSED] SVIDEO
[17:41:50] [PASSED] LVDS
[17:41:50] [PASSED] Component
[17:41:50] [PASSED] DIN
[17:41:50] [PASSED] DP
[17:41:50] [PASSED] HDMI-A
[17:41:50] [PASSED] HDMI-B
[17:41:50] [PASSED] TV
[17:41:50] [PASSED] eDP
[17:41:50] [PASSED] Virtual
[17:41:50] [PASSED] DSI
[17:41:50] [PASSED] DPI
[17:41:50] [PASSED] Writeback
[17:41:50] [PASSED] SPI
[17:41:50] [PASSED] USB
[17:41:50] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[17:41:50] ======== drm_test_drm_connector_dynamic_init_name =========
[17:41:50] [PASSED] Unknown
[17:41:50] [PASSED] VGA
[17:41:50] [PASSED] DVI-I
[17:41:50] [PASSED] DVI-D
[17:41:50] [PASSED] DVI-A
[17:41:50] [PASSED] Composite
[17:41:50] [PASSED] SVIDEO
[17:41:50] [PASSED] LVDS
[17:41:50] [PASSED] Component
[17:41:50] [PASSED] DIN
[17:41:50] [PASSED] DP
[17:41:50] [PASSED] HDMI-A
[17:41:50] [PASSED] HDMI-B
[17:41:50] [PASSED] TV
[17:41:50] [PASSED] eDP
[17:41:50] [PASSED] Virtual
[17:41:50] [PASSED] DSI
[17:41:50] [PASSED] DPI
[17:41:50] [PASSED] Writeback
[17:41:50] [PASSED] SPI
[17:41:50] [PASSED] USB
[17:41:50] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[17:41:50] =========== [PASSED] drm_connector_dynamic_init ============
[17:41:50] ==== drm_connector_dynamic_register_early (4 subtests) =====
[17:41:50] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[17:41:50] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[17:41:50] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[17:41:50] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[17:41:50] ====== [PASSED] drm_connector_dynamic_register_early =======
[17:41:50] ======= drm_connector_dynamic_register (7 subtests) ========
[17:41:50] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[17:41:50] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[17:41:50] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[17:41:50] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[17:41:50] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[17:41:50] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[17:41:50] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[17:41:50] ========= [PASSED] drm_connector_dynamic_register ==========
[17:41:50] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[17:41:50] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[17:41:50] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[17:41:50] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[17:41:50] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[17:41:50] ========== drm_test_get_tv_mode_from_name_valid ===========
[17:41:50] [PASSED] NTSC
[17:41:50] [PASSED] NTSC-443
[17:41:50] [PASSED] NTSC-J
[17:41:50] [PASSED] PAL
[17:41:50] [PASSED] PAL-M
[17:41:50] [PASSED] PAL-N
[17:41:50] [PASSED] SECAM
[17:41:50] [PASSED] Mono
[17:41:50] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[17:41:50] [PASSED] drm_test_get_tv_mode_from_name_truncated
[17:41:50] ============ [PASSED] drm_get_tv_mode_from_name ============
[17:41:50] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[17:41:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[17:41:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[17:41:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[17:41:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[17:41:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[17:41:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[17:41:50] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[17:41:50] [PASSED] VIC 96
[17:41:50] [PASSED] VIC 97
[17:41:50] [PASSED] VIC 101
[17:41:50] [PASSED] VIC 102
[17:41:50] [PASSED] VIC 106
[17:41:50] [PASSED] VIC 107
[17:41:50] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[17:41:50] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[17:41:50] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[17:41:50] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[17:41:50] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[17:41:50] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[17:41:50] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[17:41:50] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[17:41:50] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[17:41:50] [PASSED] Automatic
[17:41:50] [PASSED] Full
[17:41:50] [PASSED] Limited 16:235
[17:41:50] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[17:41:50] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[17:41:50] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[17:41:50] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[17:41:50] === drm_test_drm_hdmi_connector_get_output_format_name ====
[17:41:50] [PASSED] RGB
[17:41:50] [PASSED] YUV 4:2:0
[17:41:50] [PASSED] YUV 4:2:2
[17:41:50] [PASSED] YUV 4:4:4
[17:41:50] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[17:41:50] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[17:41:50] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[17:41:50] ============= drm_damage_helper (21 subtests) ==============
[17:41:50] [PASSED] drm_test_damage_iter_no_damage
[17:41:50] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[17:41:50] [PASSED] drm_test_damage_iter_no_damage_src_moved
[17:41:50] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[17:41:50] [PASSED] drm_test_damage_iter_no_damage_not_visible
[17:41:50] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[17:41:50] [PASSED] drm_test_damage_iter_no_damage_no_fb
[17:41:50] [PASSED] drm_test_damage_iter_simple_damage
[17:41:50] [PASSED] drm_test_damage_iter_single_damage
[17:41:50] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[17:41:50] [PASSED] drm_test_damage_iter_single_damage_outside_src
[17:41:50] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[17:41:50] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[17:41:50] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[17:41:50] [PASSED] drm_test_damage_iter_single_damage_src_moved
[17:41:50] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[17:41:50] [PASSED] drm_test_damage_iter_damage
[17:41:50] [PASSED] drm_test_damage_iter_damage_one_intersect
[17:41:50] [PASSED] drm_test_damage_iter_damage_one_outside
[17:41:50] [PASSED] drm_test_damage_iter_damage_src_moved
[17:41:50] [PASSED] drm_test_damage_iter_damage_not_visible
[17:41:50] ================ [PASSED] drm_damage_helper ================
[17:41:50] ============== drm_dp_mst_helper (3 subtests) ==============
[17:41:50] ============== drm_test_dp_mst_calc_pbn_mode ==============
[17:41:50] [PASSED] Clock 154000 BPP 30 DSC disabled
[17:41:50] [PASSED] Clock 234000 BPP 30 DSC disabled
[17:41:50] [PASSED] Clock 297000 BPP 24 DSC disabled
[17:41:50] [PASSED] Clock 332880 BPP 24 DSC enabled
[17:41:50] [PASSED] Clock 324540 BPP 24 DSC enabled
[17:41:50] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[17:41:50] ============== drm_test_dp_mst_calc_pbn_div ===============
[17:41:50] [PASSED] Link rate 2000000 lane count 4
[17:41:50] [PASSED] Link rate 2000000 lane count 2
[17:41:50] [PASSED] Link rate 2000000 lane count 1
[17:41:50] [PASSED] Link rate 1350000 lane count 4
[17:41:50] [PASSED] Link rate 1350000 lane count 2
[17:41:50] [PASSED] Link rate 1350000 lane count 1
[17:41:50] [PASSED] Link rate 1000000 lane count 4
[17:41:50] [PASSED] Link rate 1000000 lane count 2
[17:41:50] [PASSED] Link rate 1000000 lane count 1
[17:41:50] [PASSED] Link rate 810000 lane count 4
[17:41:50] [PASSED] Link rate 810000 lane count 2
[17:41:50] [PASSED] Link rate 810000 lane count 1
[17:41:50] [PASSED] Link rate 540000 lane count 4
[17:41:50] [PASSED] Link rate 540000 lane count 2
[17:41:50] [PASSED] Link rate 540000 lane count 1
[17:41:50] [PASSED] Link rate 270000 lane count 4
[17:41:50] [PASSED] Link rate 270000 lane count 2
[17:41:50] [PASSED] Link rate 270000 lane count 1
[17:41:50] [PASSED] Link rate 162000 lane count 4
[17:41:50] [PASSED] Link rate 162000 lane count 2
[17:41:50] [PASSED] Link rate 162000 lane count 1
[17:41:50] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[17:41:50] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[17:41:50] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[17:41:50] [PASSED] DP_POWER_UP_PHY with port number
[17:41:50] [PASSED] DP_POWER_DOWN_PHY with port number
[17:41:50] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[17:41:50] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[17:41:50] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[17:41:50] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[17:41:50] [PASSED] DP_QUERY_PAYLOAD with port number
[17:41:50] [PASSED] DP_QUERY_PAYLOAD with VCPI
[17:41:50] [PASSED] DP_REMOTE_DPCD_READ with port number
[17:41:50] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[17:41:50] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[17:41:50] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[17:41:50] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[17:41:50] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[17:41:50] [PASSED] DP_REMOTE_I2C_READ with port number
[17:41:50] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[17:41:50] [PASSED] DP_REMOTE_I2C_READ with transactions array
[17:41:50] [PASSED] DP_REMOTE_I2C_WRITE with port number
[17:41:50] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[17:41:50] [PASSED] DP_REMOTE_I2C_WRITE with data array
[17:41:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[17:41:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[17:41:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[17:41:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[17:41:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[17:41:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[17:41:50] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[17:41:50] ================ [PASSED] drm_dp_mst_helper ================
[17:41:50] ================== drm_exec (7 subtests) ===================
[17:41:50] [PASSED] sanitycheck
[17:41:50] [PASSED] test_lock
[17:41:50] [PASSED] test_lock_unlock
[17:41:50] [PASSED] test_duplicates
[17:41:50] [PASSED] test_prepare
[17:41:50] [PASSED] test_prepare_array
[17:41:50] [PASSED] test_multiple_loops
[17:41:50] ==================== [PASSED] drm_exec =====================
[17:41:50] =========== drm_format_helper_test (17 subtests) ===========
[17:41:50] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[17:41:50] [PASSED] single_pixel_source_buffer
[17:41:50] [PASSED] single_pixel_clip_rectangle
[17:41:50] [PASSED] well_known_colors
[17:41:50] [PASSED] destination_pitch
[17:41:50] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[17:41:50] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[17:41:50] [PASSED] single_pixel_source_buffer
[17:41:50] [PASSED] single_pixel_clip_rectangle
[17:41:50] [PASSED] well_known_colors
[17:41:50] [PASSED] destination_pitch
[17:41:50] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[17:41:50] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[17:41:50] [PASSED] single_pixel_source_buffer
[17:41:50] [PASSED] single_pixel_clip_rectangle
[17:41:50] [PASSED] well_known_colors
[17:41:50] [PASSED] destination_pitch
[17:41:50] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[17:41:50] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[17:41:50] [PASSED] single_pixel_source_buffer
[17:41:50] [PASSED] single_pixel_clip_rectangle
[17:41:50] [PASSED] well_known_colors
[17:41:50] [PASSED] destination_pitch
[17:41:50] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[17:41:50] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[17:41:50] [PASSED] single_pixel_source_buffer
[17:41:50] [PASSED] single_pixel_clip_rectangle
[17:41:50] [PASSED] well_known_colors
[17:41:50] [PASSED] destination_pitch
[17:41:50] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[17:41:50] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[17:41:50] [PASSED] single_pixel_source_buffer
[17:41:50] [PASSED] single_pixel_clip_rectangle
[17:41:50] [PASSED] well_known_colors
[17:41:50] [PASSED] destination_pitch
[17:41:50] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[17:41:50] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[17:41:50] [PASSED] single_pixel_source_buffer
[17:41:50] [PASSED] single_pixel_clip_rectangle
[17:41:50] [PASSED] well_known_colors
[17:41:50] [PASSED] destination_pitch
[17:41:50] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[17:41:50] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[17:41:50] [PASSED] single_pixel_source_buffer
[17:41:50] [PASSED] single_pixel_clip_rectangle
[17:41:50] [PASSED] well_known_colors
[17:41:50] [PASSED] destination_pitch
[17:41:50] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[17:41:50] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[17:41:50] [PASSED] single_pixel_source_buffer
[17:41:50] [PASSED] single_pixel_clip_rectangle
[17:41:50] [PASSED] well_known_colors
[17:41:50] [PASSED] destination_pitch
[17:41:50] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[17:41:50] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[17:41:50] [PASSED] single_pixel_source_buffer
[17:41:50] [PASSED] single_pixel_clip_rectangle
[17:41:50] [PASSED] well_known_colors
[17:41:50] [PASSED] destination_pitch
[17:41:50] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[17:41:50] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[17:41:50] [PASSED] single_pixel_source_buffer
[17:41:50] [PASSED] single_pixel_clip_rectangle
[17:41:50] [PASSED] well_known_colors
[17:41:50] [PASSED] destination_pitch
[17:41:50] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[17:41:50] ============== drm_test_fb_xrgb8888_to_mono ===============
[17:41:50] [PASSED] single_pixel_source_buffer
[17:41:50] [PASSED] single_pixel_clip_rectangle
[17:41:50] [PASSED] well_known_colors
[17:41:50] [PASSED] destination_pitch
[17:41:50] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[17:41:50] ==================== drm_test_fb_swab =====================
[17:41:50] [PASSED] single_pixel_source_buffer
[17:41:50] [PASSED] single_pixel_clip_rectangle
[17:41:50] [PASSED] well_known_colors
[17:41:50] [PASSED] destination_pitch
[17:41:50] ================ [PASSED] drm_test_fb_swab =================
[17:41:50] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[17:41:50] [PASSED] single_pixel_source_buffer
[17:41:50] [PASSED] single_pixel_clip_rectangle
[17:41:50] [PASSED] well_known_colors
[17:41:50] [PASSED] destination_pitch
[17:41:50] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[17:41:50] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[17:41:50] [PASSED] single_pixel_source_buffer
[17:41:50] [PASSED] single_pixel_clip_rectangle
[17:41:50] [PASSED] well_known_colors
[17:41:50] [PASSED] destination_pitch
[17:41:50] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[17:41:50] ================= drm_test_fb_clip_offset =================
[17:41:50] [PASSED] pass through
[17:41:50] [PASSED] horizontal offset
[17:41:50] [PASSED] vertical offset
[17:41:50] [PASSED] horizontal and vertical offset
[17:41:50] [PASSED] horizontal offset (custom pitch)
[17:41:50] [PASSED] vertical offset (custom pitch)
[17:41:50] [PASSED] horizontal and vertical offset (custom pitch)
[17:41:50] ============= [PASSED] drm_test_fb_clip_offset =============
[17:41:50] =================== drm_test_fb_memcpy ====================
[17:41:50] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[17:41:50] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[17:41:50] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[17:41:50] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[17:41:50] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[17:41:50] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[17:41:50] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[17:41:50] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[17:41:50] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[17:41:50] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[17:41:50] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[17:41:50] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[17:41:50] =============== [PASSED] drm_test_fb_memcpy ================
[17:41:50] ============= [PASSED] drm_format_helper_test ==============
[17:41:50] ================= drm_format (18 subtests) =================
[17:41:50] [PASSED] drm_test_format_block_width_invalid
[17:41:50] [PASSED] drm_test_format_block_width_one_plane
[17:41:50] [PASSED] drm_test_format_block_width_two_plane
[17:41:50] [PASSED] drm_test_format_block_width_three_plane
[17:41:50] [PASSED] drm_test_format_block_width_tiled
[17:41:50] [PASSED] drm_test_format_block_height_invalid
[17:41:50] [PASSED] drm_test_format_block_height_one_plane
[17:41:50] [PASSED] drm_test_format_block_height_two_plane
[17:41:50] [PASSED] drm_test_format_block_height_three_plane
[17:41:50] [PASSED] drm_test_format_block_height_tiled
[17:41:50] [PASSED] drm_test_format_min_pitch_invalid
[17:41:50] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[17:41:50] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[17:41:50] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[17:41:50] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[17:41:50] [PASSED] drm_test_format_min_pitch_two_plane
[17:41:50] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[17:41:50] [PASSED] drm_test_format_min_pitch_tiled
[17:41:50] =================== [PASSED] drm_format ====================
[17:41:50] ============== drm_framebuffer (10 subtests) ===============
[17:41:50] ========== drm_test_framebuffer_check_src_coords ==========
[17:41:50] [PASSED] Success: source fits into fb
[17:41:50] [PASSED] Fail: overflowing fb with x-axis coordinate
[17:41:50] [PASSED] Fail: overflowing fb with y-axis coordinate
[17:41:50] [PASSED] Fail: overflowing fb with source width
[17:41:50] [PASSED] Fail: overflowing fb with source height
[17:41:50] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[17:41:50] [PASSED] drm_test_framebuffer_cleanup
[17:41:50] =============== drm_test_framebuffer_create ===============
[17:41:50] [PASSED] ABGR8888 normal sizes
[17:41:50] [PASSED] ABGR8888 max sizes
[17:41:50] [PASSED] ABGR8888 pitch greater than min required
[17:41:50] [PASSED] ABGR8888 pitch less than min required
[17:41:50] [PASSED] ABGR8888 Invalid width
[17:41:50] [PASSED] ABGR8888 Invalid buffer handle
[17:41:50] [PASSED] No pixel format
[17:41:50] [PASSED] ABGR8888 Width 0
[17:41:50] [PASSED] ABGR8888 Height 0
[17:41:50] [PASSED] ABGR8888 Out of bound height * pitch combination
[17:41:50] [PASSED] ABGR8888 Large buffer offset
[17:41:50] [PASSED] ABGR8888 Buffer offset for inexistent plane
[17:41:50] [PASSED] ABGR8888 Invalid flag
[17:41:50] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[17:41:50] [PASSED] ABGR8888 Valid buffer modifier
[17:41:50] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[17:41:50] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[17:41:50] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[17:41:50] [PASSED] NV12 Normal sizes
[17:41:50] [PASSED] NV12 Max sizes
[17:41:50] [PASSED] NV12 Invalid pitch
[17:41:50] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[17:41:50] [PASSED] NV12 different modifier per-plane
[17:41:50] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[17:41:50] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[17:41:50] [PASSED] NV12 Modifier for inexistent plane
[17:41:50] [PASSED] NV12 Handle for inexistent plane
[17:41:50] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[17:41:50] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[17:41:50] [PASSED] YVU420 Normal sizes
[17:41:50] [PASSED] YVU420 Max sizes
[17:41:50] [PASSED] YVU420 Invalid pitch
[17:41:50] [PASSED] YVU420 Different pitches
[17:41:50] [PASSED] YVU420 Different buffer offsets/pitches
[17:41:50] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[17:41:50] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[17:41:50] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[17:41:50] [PASSED] YVU420 Valid modifier
[17:41:50] [PASSED] YVU420 Different modifiers per plane
[17:41:50] [PASSED] YVU420 Modifier for inexistent plane
[17:41:50] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[17:41:50] [PASSED] X0L2 Normal sizes
[17:41:50] [PASSED] X0L2 Max sizes
[17:41:50] [PASSED] X0L2 Invalid pitch
[17:41:50] [PASSED] X0L2 Pitch greater than minimum required
[17:41:50] [PASSED] X0L2 Handle for inexistent plane
[17:41:50] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[17:41:50] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[17:41:50] [PASSED] X0L2 Valid modifier
[17:41:50] [PASSED] X0L2 Modifier for inexistent plane
[17:41:50] =========== [PASSED] drm_test_framebuffer_create ===========
[17:41:50] [PASSED] drm_test_framebuffer_free
[17:41:50] [PASSED] drm_test_framebuffer_init
[17:41:50] [PASSED] drm_test_framebuffer_init_bad_format
[17:41:50] [PASSED] drm_test_framebuffer_init_dev_mismatch
[17:41:50] [PASSED] drm_test_framebuffer_lookup
[17:41:50] [PASSED] drm_test_framebuffer_lookup_inexistent
[17:41:50] [PASSED] drm_test_framebuffer_modifiers_not_supported
[17:41:50] ================= [PASSED] drm_framebuffer =================
[17:41:50] ================ drm_gem_shmem (8 subtests) ================
[17:41:50] [PASSED] drm_gem_shmem_test_obj_create
[17:41:50] [PASSED] drm_gem_shmem_test_obj_create_private
[17:41:50] [PASSED] drm_gem_shmem_test_pin_pages
[17:41:50] [PASSED] drm_gem_shmem_test_vmap
[17:41:50] [PASSED] drm_gem_shmem_test_get_sg_table
[17:41:50] [PASSED] drm_gem_shmem_test_get_pages_sgt
[17:41:50] [PASSED] drm_gem_shmem_test_madvise
[17:41:50] [PASSED] drm_gem_shmem_test_purge
[17:41:50] ================== [PASSED] drm_gem_shmem ==================
[17:41:50] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[17:41:50] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[17:41:50] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[17:41:50] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[17:41:50] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[17:41:50] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[17:41:50] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[17:41:50] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[17:41:50] [PASSED] Automatic
[17:41:50] [PASSED] Full
[17:41:50] [PASSED] Limited 16:235
[17:41:50] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[17:41:50] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[17:41:50] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[17:41:50] [PASSED] drm_test_check_disable_connector
[17:41:50] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[17:41:50] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[17:41:50] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[17:41:50] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[17:41:50] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[17:41:50] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[17:41:50] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[17:41:50] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[17:41:50] [PASSED] drm_test_check_output_bpc_dvi
[17:41:50] [PASSED] drm_test_check_output_bpc_format_vic_1
[17:41:50] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[17:41:50] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[17:41:50] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[17:41:50] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[17:41:50] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[17:41:50] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[17:41:50] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[17:41:50] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[17:41:50] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[17:41:50] [PASSED] drm_test_check_broadcast_rgb_value
[17:41:50] [PASSED] drm_test_check_bpc_8_value
[17:41:50] [PASSED] drm_test_check_bpc_10_value
[17:41:50] [PASSED] drm_test_check_bpc_12_value
[17:41:50] [PASSED] drm_test_check_format_value
[17:41:50] [PASSED] drm_test_check_tmds_char_value
[17:41:50] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[17:41:50] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[17:41:50] [PASSED] drm_test_check_mode_valid
[17:41:50] [PASSED] drm_test_check_mode_valid_reject
[17:41:50] [PASSED] drm_test_check_mode_valid_reject_rate
[17:41:50] [PASSED] drm_test_check_mode_valid_reject_max_clock
[17:41:50] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[17:41:50] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[17:41:50] [PASSED] drm_test_check_infoframes
[17:41:50] [PASSED] drm_test_check_reject_avi_infoframe
[17:41:50] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[17:41:50] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[17:41:50] [PASSED] drm_test_check_reject_audio_infoframe
[17:41:50] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[17:41:50] ================= drm_managed (2 subtests) =================
[17:41:50] [PASSED] drm_test_managed_release_action
[17:41:50] [PASSED] drm_test_managed_run_action
[17:41:50] =================== [PASSED] drm_managed ===================
[17:41:50] =================== drm_mm (6 subtests) ====================
[17:41:50] [PASSED] drm_test_mm_init
[17:41:50] [PASSED] drm_test_mm_debug
[17:41:50] [PASSED] drm_test_mm_align32
[17:41:50] [PASSED] drm_test_mm_align64
[17:41:50] [PASSED] drm_test_mm_lowest
[17:41:50] [PASSED] drm_test_mm_highest
[17:41:50] ===================== [PASSED] drm_mm ======================
[17:41:50] ============= drm_modes_analog_tv (5 subtests) =============
[17:41:50] [PASSED] drm_test_modes_analog_tv_mono_576i
[17:41:50] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[17:41:50] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[17:41:50] [PASSED] drm_test_modes_analog_tv_pal_576i
[17:41:50] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[17:41:50] =============== [PASSED] drm_modes_analog_tv ===============
[17:41:50] ============== drm_plane_helper (2 subtests) ===============
[17:41:50] =============== drm_test_check_plane_state ================
[17:41:50] [PASSED] clipping_simple
[17:41:50] [PASSED] clipping_rotate_reflect
[17:41:50] [PASSED] positioning_simple
[17:41:50] [PASSED] upscaling
[17:41:50] [PASSED] downscaling
[17:41:50] [PASSED] rounding1
[17:41:50] [PASSED] rounding2
[17:41:50] [PASSED] rounding3
[17:41:50] [PASSED] rounding4
[17:41:50] =========== [PASSED] drm_test_check_plane_state ============
[17:41:50] =========== drm_test_check_invalid_plane_state ============
[17:41:50] [PASSED] positioning_invalid
[17:41:50] [PASSED] upscaling_invalid
[17:41:50] [PASSED] downscaling_invalid
[17:41:50] ======= [PASSED] drm_test_check_invalid_plane_state ========
[17:41:50] ================ [PASSED] drm_plane_helper =================
[17:41:50] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[17:41:50] ====== drm_test_connector_helper_tv_get_modes_check =======
[17:41:50] [PASSED] None
[17:41:50] [PASSED] PAL
[17:41:50] [PASSED] NTSC
[17:41:50] [PASSED] Both, NTSC Default
[17:41:50] [PASSED] Both, PAL Default
[17:41:50] [PASSED] Both, NTSC Default, with PAL on command-line
[17:41:50] [PASSED] Both, PAL Default, with NTSC on command-line
[17:41:50] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[17:41:50] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[17:41:50] ================== drm_rect (9 subtests) ===================
[17:41:50] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[17:41:50] [PASSED] drm_test_rect_clip_scaled_not_clipped
[17:41:50] [PASSED] drm_test_rect_clip_scaled_clipped
[17:41:50] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[17:41:50] ================= drm_test_rect_intersect =================
[17:41:50] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[17:41:50] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[17:41:50] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[17:41:50] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[17:41:50] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[17:41:50] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[17:41:50] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[17:41:50] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[17:41:50] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[17:41:50] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[17:41:50] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[17:41:50] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[17:41:50] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[17:41:50] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[17:41:50] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[17:41:50] ============= [PASSED] drm_test_rect_intersect =============
[17:41:50] ================ drm_test_rect_calc_hscale ================
[17:41:50] [PASSED] normal use
[17:41:50] [PASSED] out of max range
[17:41:50] [PASSED] out of min range
[17:41:50] [PASSED] zero dst
[17:41:50] [PASSED] negative src
[17:41:50] [PASSED] negative dst
[17:41:50] ============ [PASSED] drm_test_rect_calc_hscale ============
[17:41:50] ================ drm_test_rect_calc_vscale ================
[17:41:50] [PASSED] normal use
[17:41:50] [PASSED] out of max range
[17:41:50] [PASSED] out of min range
[17:41:50] [PASSED] zero dst
[17:41:50] [PASSED] negative src
[17:41:50] [PASSED] negative dst
[17:41:50] ============ [PASSED] drm_test_rect_calc_vscale ============
[17:41:50] ================== drm_test_rect_rotate ===================
[17:41:50] [PASSED] reflect-x
[17:41:50] [PASSED] reflect-y
[17:41:50] [PASSED] rotate-0
[17:41:50] [PASSED] rotate-90
[17:41:50] [PASSED] rotate-180
[17:41:50] [PASSED] rotate-270
[17:41:50] ============== [PASSED] drm_test_rect_rotate ===============
[17:41:50] ================ drm_test_rect_rotate_inv =================
[17:41:50] [PASSED] reflect-x
[17:41:50] [PASSED] reflect-y
[17:41:50] [PASSED] rotate-0
[17:41:50] [PASSED] rotate-90
[17:41:50] [PASSED] rotate-180
[17:41:50] [PASSED] rotate-270
[17:41:50] ============ [PASSED] drm_test_rect_rotate_inv =============
[17:41:50] ==================== [PASSED] drm_rect =====================
[17:41:50] ============ drm_sysfb_modeset_test (1 subtest) ============
[17:41:50] ============ drm_test_sysfb_build_fourcc_list =============
[17:41:50] [PASSED] no native formats
[17:41:50] [PASSED] XRGB8888 as native format
[17:41:50] [PASSED] remove duplicates
[17:41:50] [PASSED] convert alpha formats
[17:41:50] [PASSED] random formats
[17:41:50] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[17:41:50] ============= [PASSED] drm_sysfb_modeset_test ==============
[17:41:50] ================== drm_fixp (2 subtests) ===================
[17:41:50] [PASSED] drm_test_int2fixp
[17:41:50] [PASSED] drm_test_sm2fixp
[17:41:50] ==================== [PASSED] drm_fixp =====================
[17:41:50] ============================================================
[17:41:50] Testing complete. Ran 621 tests: passed: 621
[17:41:50] Elapsed time: 26.109s total, 1.750s configuring, 24.190s building, 0.118s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[17:41:50] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:41:52] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:42:01] Starting KUnit Kernel (1/1)...
[17:42:01] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:42:02] ================= ttm_device (5 subtests) ==================
[17:42:02] [PASSED] ttm_device_init_basic
[17:42:02] [PASSED] ttm_device_init_multiple
[17:42:02] [PASSED] ttm_device_fini_basic
[17:42:02] [PASSED] ttm_device_init_no_vma_man
[17:42:02] ================== ttm_device_init_pools ==================
[17:42:02] [PASSED] No DMA allocations, no DMA32 required
[17:42:02] [PASSED] DMA allocations, DMA32 required
[17:42:02] [PASSED] No DMA allocations, DMA32 required
[17:42:02] [PASSED] DMA allocations, no DMA32 required
[17:42:02] ============== [PASSED] ttm_device_init_pools ==============
[17:42:02] =================== [PASSED] ttm_device ====================
[17:42:02] ================== ttm_pool (8 subtests) ===================
[17:42:02] ================== ttm_pool_alloc_basic ===================
[17:42:02] [PASSED] One page
[17:42:02] [PASSED] More than one page
[17:42:02] [PASSED] Above the allocation limit
[17:42:02] [PASSED] One page, with coherent DMA mappings enabled
[17:42:02] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:42:02] ============== [PASSED] ttm_pool_alloc_basic ===============
[17:42:02] ============== ttm_pool_alloc_basic_dma_addr ==============
[17:42:02] [PASSED] One page
[17:42:02] [PASSED] More than one page
[17:42:02] [PASSED] Above the allocation limit
[17:42:02] [PASSED] One page, with coherent DMA mappings enabled
[17:42:02] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:42:02] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[17:42:02] [PASSED] ttm_pool_alloc_order_caching_match
[17:42:02] [PASSED] ttm_pool_alloc_caching_mismatch
[17:42:02] [PASSED] ttm_pool_alloc_order_mismatch
[17:42:02] [PASSED] ttm_pool_free_dma_alloc
[17:42:02] [PASSED] ttm_pool_free_no_dma_alloc
[17:42:02] [PASSED] ttm_pool_fini_basic
[17:42:02] ==================== [PASSED] ttm_pool =====================
[17:42:02] ================ ttm_resource (8 subtests) =================
[17:42:02] ================= ttm_resource_init_basic =================
[17:42:02] [PASSED] Init resource in TTM_PL_SYSTEM
[17:42:02] [PASSED] Init resource in TTM_PL_VRAM
[17:42:02] [PASSED] Init resource in a private placement
[17:42:02] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[17:42:02] ============= [PASSED] ttm_resource_init_basic =============
[17:42:02] [PASSED] ttm_resource_init_pinned
[17:42:02] [PASSED] ttm_resource_fini_basic
[17:42:02] [PASSED] ttm_resource_manager_init_basic
[17:42:02] [PASSED] ttm_resource_manager_usage_basic
[17:42:02] [PASSED] ttm_resource_manager_set_used_basic
[17:42:02] [PASSED] ttm_sys_man_alloc_basic
[17:42:02] [PASSED] ttm_sys_man_free_basic
[17:42:02] ================== [PASSED] ttm_resource ===================
[17:42:02] =================== ttm_tt (15 subtests) ===================
[17:42:02] ==================== ttm_tt_init_basic ====================
[17:42:02] [PASSED] Page-aligned size
[17:42:02] [PASSED] Extra pages requested
[17:42:02] ================ [PASSED] ttm_tt_init_basic ================
[17:42:02] [PASSED] ttm_tt_init_misaligned
[17:42:02] [PASSED] ttm_tt_fini_basic
[17:42:02] [PASSED] ttm_tt_fini_sg
[17:42:02] [PASSED] ttm_tt_fini_shmem
[17:42:02] [PASSED] ttm_tt_create_basic
[17:42:02] [PASSED] ttm_tt_create_invalid_bo_type
[17:42:02] [PASSED] ttm_tt_create_ttm_exists
[17:42:02] [PASSED] ttm_tt_create_failed
[17:42:02] [PASSED] ttm_tt_destroy_basic
[17:42:02] [PASSED] ttm_tt_populate_null_ttm
[17:42:02] [PASSED] ttm_tt_populate_populated_ttm
[17:42:02] [PASSED] ttm_tt_unpopulate_basic
[17:42:02] [PASSED] ttm_tt_unpopulate_empty_ttm
[17:42:02] [PASSED] ttm_tt_swapin_basic
[17:42:02] ===================== [PASSED] ttm_tt ======================
[17:42:02] =================== ttm_bo (14 subtests) ===================
[17:42:02] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[17:42:02] [PASSED] Cannot be interrupted and sleeps
[17:42:02] [PASSED] Cannot be interrupted, locks straight away
[17:42:02] [PASSED] Can be interrupted, sleeps
[17:42:02] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[17:42:02] [PASSED] ttm_bo_reserve_locked_no_sleep
[17:42:02] [PASSED] ttm_bo_reserve_no_wait_ticket
[17:42:02] [PASSED] ttm_bo_reserve_double_resv
[17:42:02] [PASSED] ttm_bo_reserve_interrupted
[17:42:02] [PASSED] ttm_bo_reserve_deadlock
[17:42:02] [PASSED] ttm_bo_unreserve_basic
[17:42:02] [PASSED] ttm_bo_unreserve_pinned
[17:42:02] [PASSED] ttm_bo_unreserve_bulk
[17:42:02] [PASSED] ttm_bo_fini_basic
[17:42:02] [PASSED] ttm_bo_fini_shared_resv
[17:42:02] [PASSED] ttm_bo_pin_basic
[17:42:02] [PASSED] ttm_bo_pin_unpin_resource
[17:42:02] [PASSED] ttm_bo_multiple_pin_one_unpin
[17:42:02] ===================== [PASSED] ttm_bo ======================
[17:42:02] ============== ttm_bo_validate (22 subtests) ===============
[17:42:02] ============== ttm_bo_init_reserved_sys_man ===============
[17:42:02] [PASSED] Buffer object for userspace
[17:42:02] [PASSED] Kernel buffer object
[17:42:02] [PASSED] Shared buffer object
[17:42:02] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[17:42:02] ============== ttm_bo_init_reserved_mock_man ==============
[17:42:02] [PASSED] Buffer object for userspace
[17:42:02] [PASSED] Kernel buffer object
[17:42:02] [PASSED] Shared buffer object
[17:42:02] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[17:42:02] [PASSED] ttm_bo_init_reserved_resv
[17:42:02] ================== ttm_bo_validate_basic ==================
[17:42:02] [PASSED] Buffer object for userspace
[17:42:02] [PASSED] Kernel buffer object
[17:42:02] [PASSED] Shared buffer object
[17:42:02] ============== [PASSED] ttm_bo_validate_basic ==============
[17:42:02] [PASSED] ttm_bo_validate_invalid_placement
[17:42:02] ============= ttm_bo_validate_same_placement ==============
[17:42:02] [PASSED] System manager
[17:42:02] [PASSED] VRAM manager
[17:42:02] ========= [PASSED] ttm_bo_validate_same_placement ==========
[17:42:02] [PASSED] ttm_bo_validate_failed_alloc
[17:42:02] [PASSED] ttm_bo_validate_pinned
[17:42:02] [PASSED] ttm_bo_validate_busy_placement
[17:42:02] ================ ttm_bo_validate_multihop =================
[17:42:02] [PASSED] Buffer object for userspace
[17:42:02] [PASSED] Kernel buffer object
[17:42:02] [PASSED] Shared buffer object
[17:42:02] ============ [PASSED] ttm_bo_validate_multihop =============
[17:42:02] ========== ttm_bo_validate_no_placement_signaled ==========
[17:42:02] [PASSED] Buffer object in system domain, no page vector
[17:42:02] [PASSED] Buffer object in system domain with an existing page vector
[17:42:02] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[17:42:02] ======== ttm_bo_validate_no_placement_not_signaled ========
[17:42:02] [PASSED] Buffer object for userspace
[17:42:02] [PASSED] Kernel buffer object
[17:42:02] [PASSED] Shared buffer object
[17:42:02] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[17:42:02] [PASSED] ttm_bo_validate_move_fence_signaled
[17:42:02] ========= ttm_bo_validate_move_fence_not_signaled =========
[17:42:02] [PASSED] Waits for GPU
[17:42:02] [PASSED] Tries to lock straight away
[17:42:02] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[17:42:02] [PASSED] ttm_bo_validate_swapout
[17:42:02] [PASSED] ttm_bo_validate_happy_evict
[17:42:02] [PASSED] ttm_bo_validate_all_pinned_evict
[17:42:02] [PASSED] ttm_bo_validate_allowed_only_evict
[17:42:02] [PASSED] ttm_bo_validate_deleted_evict
[17:42:02] [PASSED] ttm_bo_validate_busy_domain_evict
[17:42:02] [PASSED] ttm_bo_validate_evict_gutting
[17:42:02] [PASSED] ttm_bo_validate_recrusive_evict
[17:42:02] ================= [PASSED] ttm_bo_validate =================
[17:42:02] ============================================================
[17:42:02] Testing complete. Ran 102 tests: passed: 102
[17:42:02] Elapsed time: 11.590s total, 1.768s configuring, 9.557s building, 0.234s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Xe.CI.BAT: success for drm/xe/ggtt: use full-range drm_mm with reserved nodes on PF
2026-05-27 14:45 [PATCH] drm/xe/ggtt: use full-range drm_mm with reserved nodes on PF Rodrigo Vivi
2026-05-27 17:42 ` ✓ CI.KUnit: success for " Patchwork
@ 2026-05-27 18:55 ` Patchwork
2026-05-28 1:47 ` ✗ Xe.CI.FULL: failure " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2026-05-27 18:55 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 883 bytes --]
== Series Details ==
Series: drm/xe/ggtt: use full-range drm_mm with reserved nodes on PF
URL : https://patchwork.freedesktop.org/series/167391/
State : success
== Summary ==
CI Bug Log - changes from xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb_BAT -> xe-pw-167391v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb -> xe-pw-167391v1
IGT_8939: 8939
xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb: 11a8456527f00d86dc8b23035c324da194fbbadb
xe-pw-167391v1: 167391v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/index.html
[-- Attachment #2: Type: text/html, Size: 1431 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✗ Xe.CI.FULL: failure for drm/xe/ggtt: use full-range drm_mm with reserved nodes on PF
2026-05-27 14:45 [PATCH] drm/xe/ggtt: use full-range drm_mm with reserved nodes on PF Rodrigo Vivi
2026-05-27 17:42 ` ✓ CI.KUnit: success for " Patchwork
2026-05-27 18:55 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-05-28 1:47 ` Patchwork
2026-05-28 22:11 ` [PATCH] " Michal Wajdeczko
2026-06-03 12:57 ` [PATCH] drm/xe/ggtt: clear reserved area at GUC_GGTT_TOP Maarten Lankhorst
4 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2026-05-28 1:47 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 90792 bytes --]
== Series Details ==
Series: drm/xe/ggtt: use full-range drm_mm with reserved nodes on PF
URL : https://patchwork.freedesktop.org/series/167391/
State : failure
== Summary ==
CI Bug Log - changes from xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb_FULL -> xe-pw-167391v1_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-167391v1_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-167391v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-167391v1_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_atomic_transition@plane-all-transition:
- shard-bmg: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_atomic_transition@plane-all-transition.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_atomic_transition@plane-all-transition.html
Known issues
------------
Here are the changes found in xe-pw-167391v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@fbdev@unaligned-write:
- shard-bmg: [PASS][3] -> [FAIL][4] ([Intel XE#7950])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@fbdev@unaligned-write.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@fbdev@unaligned-write.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- shard-bmg: NOTRUN -> [SKIP][5] ([Intel XE#2233])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_atomic_transition@plane-all-transition@pipe-b-hdmi-a-3:
- shard-bmg: [PASS][6] -> [DMESG-FAIL][7] ([Intel XE#5545] / [Intel XE#7774])
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_atomic_transition@plane-all-transition@pipe-b-hdmi-a-3.html
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_atomic_transition@plane-all-transition@pipe-b-hdmi-a-3.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-lnl: NOTRUN -> [SKIP][8] ([Intel XE#1407]) +4 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-7/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-lnl: NOTRUN -> [SKIP][9] ([Intel XE#3658] / [Intel XE#7360]) +1 other test skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-90:
- shard-bmg: NOTRUN -> [SKIP][10] ([Intel XE#2327]) +2 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-lnl: NOTRUN -> [SKIP][11] ([Intel XE#1428] / [Intel XE#7387])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-8/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
- shard-lnl: NOTRUN -> [SKIP][12] ([Intel XE#1124]) +13 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-addfb:
- shard-bmg: NOTRUN -> [SKIP][13] ([Intel XE#2328] / [Intel XE#7367])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-9/igt@kms_big_fb@yf-tiled-addfb.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-bmg: NOTRUN -> [SKIP][14] ([Intel XE#607] / [Intel XE#7361])
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-1/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-bmg: NOTRUN -> [SKIP][15] ([Intel XE#1124]) +12 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-10/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_bw@connected-linear-tiling-2-displays-target-3840x2160p:
- shard-bmg: NOTRUN -> [SKIP][16] ([Intel XE#7679]) +1 other test skip
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-8/igt@kms_bw@connected-linear-tiling-2-displays-target-3840x2160p.html
* igt@kms_bw@connected-linear-tiling-3-displays-target-2160x1440p:
- shard-lnl: NOTRUN -> [SKIP][17] ([Intel XE#7679]) +2 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-7/igt@kms_bw@connected-linear-tiling-3-displays-target-2160x1440p.html
* igt@kms_bw@connected-linear-tiling-4-displays-target-1920x1080p:
- shard-lnl: NOTRUN -> [SKIP][18] ([Intel XE#7676]) +1 other test skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@kms_bw@connected-linear-tiling-4-displays-target-1920x1080p.html
* igt@kms_bw@linear-tiling-1-displays-target-1920x1080p:
- shard-bmg: NOTRUN -> [SKIP][19] ([Intel XE#367]) +4 other tests skip
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-3/igt@kms_bw@linear-tiling-1-displays-target-1920x1080p.html
* igt@kms_bw@linear-tiling-3-displays-target-2560x1440p:
- shard-lnl: NOTRUN -> [SKIP][20] ([Intel XE#367])
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-6/igt@kms_bw@linear-tiling-3-displays-target-2560x1440p.html
* igt@kms_ccs@bad-aux-stride-yf-tiled-ccs:
- shard-bmg: NOTRUN -> [SKIP][21] ([Intel XE#2887]) +20 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-6/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-d-hdmi-a-3:
- shard-bmg: NOTRUN -> [SKIP][22] ([Intel XE#2652]) +35 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-1/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-d-hdmi-a-3.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc:
- shard-lnl: NOTRUN -> [SKIP][23] ([Intel XE#3432]) +2 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-1/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html
- shard-bmg: NOTRUN -> [SKIP][24] ([Intel XE#3432])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-10/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs:
- shard-lnl: NOTRUN -> [SKIP][25] ([Intel XE#2887]) +15 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs.html
* igt@kms_chamelium_color@ctm-0-25:
- shard-bmg: NOTRUN -> [SKIP][26] ([Intel XE#2325] / [Intel XE#7358]) +2 other tests skip
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-9/igt@kms_chamelium_color@ctm-0-25.html
* igt@kms_chamelium_color@ctm-0-75:
- shard-lnl: NOTRUN -> [SKIP][27] ([Intel XE#306] / [Intel XE#7358])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-6/igt@kms_chamelium_color@ctm-0-75.html
* igt@kms_chamelium_edid@dp-edid-change-during-hibernate:
- shard-bmg: NOTRUN -> [SKIP][28] ([Intel XE#2252]) +11 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-9/igt@kms_chamelium_edid@dp-edid-change-during-hibernate.html
* igt@kms_chamelium_frames@hdmi-crc-single:
- shard-lnl: NOTRUN -> [SKIP][29] ([Intel XE#373]) +10 other tests skip
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-7/igt@kms_chamelium_frames@hdmi-crc-single.html
* igt@kms_content_protection@dp-mst-lic-type-0-hdcp14:
- shard-bmg: NOTRUN -> [SKIP][30] ([Intel XE#6974])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-10/igt@kms_content_protection@dp-mst-lic-type-0-hdcp14.html
* igt@kms_content_protection@dp-mst-type-0-suspend-resume:
- shard-lnl: NOTRUN -> [SKIP][31] ([Intel XE#6974]) +2 other tests skip
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-6/igt@kms_content_protection@dp-mst-type-0-suspend-resume.html
* igt@kms_content_protection@legacy:
- shard-bmg: NOTRUN -> [FAIL][32] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +3 other tests fail
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@lic-type-1:
- shard-bmg: NOTRUN -> [SKIP][33] ([Intel XE#7642]) +1 other test skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-1/igt@kms_content_protection@lic-type-1.html
* igt@kms_content_protection@mei-interface:
- shard-lnl: NOTRUN -> [SKIP][34] ([Intel XE#1468] / [Intel XE#7396])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@type1:
- shard-lnl: NOTRUN -> [SKIP][35] ([Intel XE#7642]) +1 other test skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-7/igt@kms_content_protection@type1.html
* igt@kms_cursor_crc@cursor-offscreen-128x42:
- shard-bmg: NOTRUN -> [SKIP][36] ([Intel XE#2320]) +9 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-10/igt@kms_cursor_crc@cursor-offscreen-128x42.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-lnl: NOTRUN -> [SKIP][37] ([Intel XE#2321] / [Intel XE#7355]) +1 other test skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-1/igt@kms_cursor_crc@cursor-random-512x170.html
- shard-bmg: NOTRUN -> [SKIP][38] ([Intel XE#2321] / [Intel XE#7355]) +3 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-10/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-max-size:
- shard-lnl: NOTRUN -> [SKIP][39] ([Intel XE#1424]) +6 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-6/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-lnl: NOTRUN -> [SKIP][40] ([Intel XE#309] / [Intel XE#7343]) +1 other test skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_dp_link_training@non-uhbr-mst:
- shard-bmg: NOTRUN -> [SKIP][41] ([Intel XE#4354] / [Intel XE#5882])
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-1/igt@kms_dp_link_training@non-uhbr-mst.html
* igt@kms_dp_link_training@uhbr-mst:
- shard-bmg: NOTRUN -> [SKIP][42] ([Intel XE#4354] / [Intel XE#7386])
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-9/igt@kms_dp_link_training@uhbr-mst.html
* igt@kms_dp_linktrain_fallback@dp-fallback:
- shard-lnl: NOTRUN -> [SKIP][43] ([Intel XE#4294] / [Intel XE#7477])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@kms_dp_linktrain_fallback@dp-fallback.html
* igt@kms_dsc@dsc-fractional-bpp-with-bpc:
- shard-bmg: NOTRUN -> [SKIP][44] ([Intel XE#2244]) +1 other test skip
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-3/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
* igt@kms_dsc@dsc-with-bpc:
- shard-lnl: NOTRUN -> [SKIP][45] ([Intel XE#2244])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-6/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
- shard-lnl: NOTRUN -> [SKIP][46] ([Intel XE#4422] / [Intel XE#7442])
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
- shard-bmg: NOTRUN -> [SKIP][47] ([Intel XE#4422] / [Intel XE#7442]) +1 other test skip
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-6/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-bmg: NOTRUN -> [SKIP][48] ([Intel XE#4156] / [Intel XE#7425])
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-9/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_fbcon_fbt@psr:
- shard-bmg: NOTRUN -> [SKIP][49] ([Intel XE#6126] / [Intel XE#776])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-6/igt@kms_fbcon_fbt@psr.html
* igt@kms_feature_discovery@chamelium:
- shard-lnl: NOTRUN -> [SKIP][50] ([Intel XE#701] / [Intel XE#7359])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-8/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@display-3x:
- shard-bmg: NOTRUN -> [SKIP][51] ([Intel XE#2373] / [Intel XE#7448])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-3/igt@kms_feature_discovery@display-3x.html
* igt@kms_feature_discovery@dp-mst:
- shard-bmg: NOTRUN -> [SKIP][52] ([Intel XE#2375])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-9/igt@kms_feature_discovery@dp-mst.html
* igt@kms_feature_discovery@psr1:
- shard-bmg: NOTRUN -> [SKIP][53] ([Intel XE#2374] / [Intel XE#6127])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-3/igt@kms_feature_discovery@psr1.html
* igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible:
- shard-lnl: NOTRUN -> [SKIP][54] ([Intel XE#1421]) +7 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-expired-vblank@bc-dp2-hdmi-a3:
- shard-bmg: [PASS][55] -> [FAIL][56] ([Intel XE#3321])
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_flip@2x-flip-vs-expired-vblank@bc-dp2-hdmi-a3.html
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-4/igt@kms_flip@2x-flip-vs-expired-vblank@bc-dp2-hdmi-a3.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
- shard-lnl: NOTRUN -> [SKIP][57] ([Intel XE#7178] / [Intel XE#7349])
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yuv-linear-to-32bpp-yuv-linear-reflect-x:
- shard-bmg: NOTRUN -> [SKIP][58] ([Intel XE#7179])
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-3/igt@kms_flip_scaled_crc@flip-32bpp-yuv-linear-to-32bpp-yuv-linear-reflect-x.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
- shard-bmg: NOTRUN -> [SKIP][59] ([Intel XE#7178] / [Intel XE#7349]) +1 other test skip
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling:
- shard-lnl: NOTRUN -> [SKIP][60] ([Intel XE#1397] / [Intel XE#1745] / [Intel XE#7385])
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-7/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode:
- shard-lnl: NOTRUN -> [SKIP][61] ([Intel XE#1397] / [Intel XE#7385])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-7/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
- shard-lnl: NOTRUN -> [SKIP][62] ([Intel XE#7178] / [Intel XE#7351]) +3 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
- shard-bmg: NOTRUN -> [SKIP][63] ([Intel XE#7178] / [Intel XE#7351]) +5 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-10/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@drrshdr-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-lnl: NOTRUN -> [SKIP][64] ([Intel XE#7905]) +46 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-6/igt@kms_frontbuffer_tracking@drrshdr-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][65] ([Intel XE#4141]) +24 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-render:
- shard-bmg: NOTRUN -> [SKIP][66] ([Intel XE#7061] / [Intel XE#7356]) +9 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-blt:
- shard-lnl: NOTRUN -> [SKIP][67] ([Intel XE#6312]) +19 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-7/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-blt:
- shard-lnl: NOTRUN -> [SKIP][68] ([Intel XE#7061] / [Intel XE#7356]) +4 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-modesetfrombusy:
- shard-lnl: NOTRUN -> [SKIP][69] ([Intel XE#6312] / [Intel XE#651]) +9 other tests skip
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-6/igt@kms_frontbuffer_tracking@fbcdrrs-modesetfrombusy.html
* igt@kms_frontbuffer_tracking@fbcdrrshdr-rgb565-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][70] ([Intel XE#2311]) +86 other tests skip
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrshdr-rgb565-draw-blt.html
* igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-mmap-wc:
- shard-lnl: NOTRUN -> [SKIP][71] ([Intel XE#7061]) +4 other tests skip
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbchdr-argb161616f-draw-render:
- shard-bmg: NOTRUN -> [SKIP][72] ([Intel XE#7061]) +6 other tests skip
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbchdr-argb161616f-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-y:
- shard-bmg: NOTRUN -> [SKIP][73] ([Intel XE#7399])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-y.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt:
- shard-lnl: NOTRUN -> [SKIP][74] ([Intel XE#656] / [Intel XE#7905]) +49 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psrhdr-1p-pri-indfb-multidraw:
- shard-bmg: NOTRUN -> [SKIP][75] ([Intel XE#2313]) +87 other tests skip
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-10/igt@kms_frontbuffer_tracking@psrhdr-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-indfb-plflip-blt:
- shard-lnl: NOTRUN -> [SKIP][76] ([Intel XE#7865]) +29 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-7/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_hdr@brightness-with-hdr:
- shard-lnl: NOTRUN -> [SKIP][77] ([Intel XE#3544] / [Intel XE#7915])
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-8/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_hdr@brightness-with-hdr@pipe-a-edp-1-xrgb2101010:
- shard-lnl: NOTRUN -> [SKIP][78] ([Intel XE#7915]) +3 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-8/igt@kms_hdr@brightness-with-hdr@pipe-a-edp-1-xrgb2101010.html
* igt@kms_hdr@static-toggle:
- shard-lnl: NOTRUN -> [SKIP][79] ([Intel XE#1503] / [Intel XE#7915])
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-7/igt@kms_hdr@static-toggle.html
* igt@kms_joiner@basic-big-joiner:
- shard-lnl: NOTRUN -> [SKIP][80] ([Intel XE#6901]) +1 other test skip
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-1/igt@kms_joiner@basic-big-joiner.html
- shard-bmg: NOTRUN -> [SKIP][81] ([Intel XE#6901])
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-10/igt@kms_joiner@basic-big-joiner.html
* igt@kms_joiner@basic-ultra-joiner:
- shard-bmg: NOTRUN -> [SKIP][82] ([Intel XE#6911] / [Intel XE#7378])
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-3/igt@kms_joiner@basic-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-force-big-joiner:
- shard-lnl: NOTRUN -> [SKIP][83] ([Intel XE#7086] / [Intel XE#7390])
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@kms_joiner@invalid-modeset-force-big-joiner.html
* igt@kms_plane@pixel-format-4-tiled-modifier@pipe-b-plane-5:
- shard-bmg: NOTRUN -> [SKIP][84] ([Intel XE#7130]) +3 other tests skip
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-3/igt@kms_plane@pixel-format-4-tiled-modifier@pipe-b-plane-5.html
* igt@kms_plane@pixel-format-x-tiled-modifier@pipe-b-plane-5:
- shard-lnl: NOTRUN -> [SKIP][85] ([Intel XE#7130]) +1 other test skip
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-3/igt@kms_plane@pixel-format-x-tiled-modifier@pipe-b-plane-5.html
* igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping:
- shard-bmg: NOTRUN -> [SKIP][86] ([Intel XE#7283]) +5 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping.html
* igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping:
- shard-lnl: NOTRUN -> [SKIP][87] ([Intel XE#7283]) +1 other test skip
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping.html
* igt@kms_plane@planar-pixel-format-settings@nv12-tile4-src-y:
- shard-bmg: NOTRUN -> [SKIP][88] ([Intel XE#8076])
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-1/igt@kms_plane@planar-pixel-format-settings@nv12-tile4-src-y.html
* igt@kms_plane_multiple@2x-tiling-y:
- shard-lnl: NOTRUN -> [SKIP][89] ([Intel XE#4596] / [Intel XE#5854]) +2 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@kms_plane_multiple@2x-tiling-y.html
* igt@kms_plane_multiple@2x-tiling-yf:
- shard-bmg: NOTRUN -> [SKIP][90] ([Intel XE#5021] / [Intel XE#7377]) +1 other test skip
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-9/igt@kms_plane_multiple@2x-tiling-yf.html
* igt@kms_plane_multiple@tiling-y:
- shard-lnl: NOTRUN -> [SKIP][91] ([Intel XE#5020] / [Intel XE#7348])
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-6/igt@kms_plane_multiple@tiling-y.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-a:
- shard-bmg: NOTRUN -> [SKIP][92] ([Intel XE#2763] / [Intel XE#6886]) +9 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-a.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b:
- shard-lnl: NOTRUN -> [SKIP][93] ([Intel XE#2763] / [Intel XE#6886]) +15 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b.html
* igt@kms_pm_backlight@bad-brightness:
- shard-bmg: NOTRUN -> [SKIP][94] ([Intel XE#7376] / [Intel XE#7760] / [Intel XE#870])
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-10/igt@kms_pm_backlight@bad-brightness.html
* igt@kms_pm_backlight@brightness-with-dpms:
- shard-bmg: NOTRUN -> [SKIP][95] ([Intel XE#2938] / [Intel XE#7376] / [Intel XE#7760])
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-6/igt@kms_pm_backlight@brightness-with-dpms.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-bmg: NOTRUN -> [SKIP][96] ([Intel XE#7794])
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-1/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-bmg: NOTRUN -> [SKIP][97] ([Intel XE#2499])
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-9/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area:
- shard-lnl: NOTRUN -> [SKIP][98] ([Intel XE#2893] / [Intel XE#7304]) +3 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-1/igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf:
- shard-lnl: NOTRUN -> [SKIP][99] ([Intel XE#2893] / [Intel XE#4608] / [Intel XE#7304]) +2 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf@pipe-a-edp-1:
- shard-lnl: NOTRUN -> [SKIP][100] ([Intel XE#4608]) +2 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-7/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf@pipe-a-edp-1.html
* igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area@pipe-b-edp-1:
- shard-lnl: NOTRUN -> [SKIP][101] ([Intel XE#4608] / [Intel XE#7304]) +2 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area@pipe-b-edp-1.html
* igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
- shard-bmg: NOTRUN -> [SKIP][102] ([Intel XE#1489]) +10 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-1/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html
* igt@kms_psr2_su@page_flip-p010:
- shard-bmg: NOTRUN -> [SKIP][103] ([Intel XE#2387] / [Intel XE#7429])
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-8/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@fbc-pr-cursor-plane-move:
- shard-lnl: NOTRUN -> [SKIP][104] ([Intel XE#1406]) +1 other test skip
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-7/igt@kms_psr@fbc-pr-cursor-plane-move.html
* igt@kms_psr@fbc-psr2-primary-render:
- shard-lnl: NOTRUN -> [SKIP][105] ([Intel XE#1406] / [Intel XE#7345]) +2 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-1/igt@kms_psr@fbc-psr2-primary-render.html
* igt@kms_psr@fbc-psr2-primary-render@edp-1:
- shard-lnl: NOTRUN -> [SKIP][106] ([Intel XE#1406] / [Intel XE#4609]) +2 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-1/igt@kms_psr@fbc-psr2-primary-render@edp-1.html
* igt@kms_psr@psr-basic:
- shard-bmg: NOTRUN -> [SKIP][107] ([Intel XE#2234] / [Intel XE#2850]) +19 other tests skip
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-3/igt@kms_psr@psr-basic.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
- shard-bmg: NOTRUN -> [SKIP][108] ([Intel XE#2330] / [Intel XE#5813])
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-3/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-bmg: NOTRUN -> [SKIP][109] ([Intel XE#3904] / [Intel XE#7342]) +3 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-1/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@kms_scaling_modes@scaling-mode-full-aspect:
- shard-bmg: NOTRUN -> [SKIP][110] ([Intel XE#2413])
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-8/igt@kms_scaling_modes@scaling-mode-full-aspect.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-lnl: NOTRUN -> [SKIP][111] ([Intel XE#1435]) +1 other test skip
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
* igt@kms_sharpness_filter@filter-basic:
- shard-bmg: NOTRUN -> [SKIP][112] ([Intel XE#6503]) +2 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_sharpness_filter@filter-basic.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-bmg: NOTRUN -> [SKIP][113] ([Intel XE#2426] / [Intel XE#5848])
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_tv_load_detect@load-detect:
- shard-bmg: NOTRUN -> [SKIP][114] ([Intel XE#2450] / [Intel XE#5857])
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_tv_load_detect@load-detect.html
* igt@kms_vrr@flip-suspend:
- shard-bmg: NOTRUN -> [SKIP][115] ([Intel XE#1499]) +1 other test skip
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-9/igt@kms_vrr@flip-suspend.html
* igt@kms_vrr@negative-basic:
- shard-lnl: NOTRUN -> [SKIP][116] ([Intel XE#1499]) +1 other test skip
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-6/igt@kms_vrr@negative-basic.html
* igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
- shard-lnl: NOTRUN -> [FAIL][117] ([Intel XE#2142]) +1 other test fail
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-3/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
* igt@xe_ccs@vm-bind-decompress:
- shard-lnl: NOTRUN -> [SKIP][118] ([Intel XE#7644])
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-7/igt@xe_ccs@vm-bind-decompress.html
* igt@xe_compute@ccs-mode-basic:
- shard-bmg: NOTRUN -> [SKIP][119] ([Intel XE#6599])
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-9/igt@xe_compute@ccs-mode-basic.html
* igt@xe_configfs@survivability-mode:
- shard-lnl: NOTRUN -> [SKIP][120] ([Intel XE#6010] / [Intel XE#7317] / [Intel XE#7455])
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@xe_configfs@survivability-mode.html
* igt@xe_copy_basic@mem-page-copy-17:
- shard-lnl: [PASS][121] -> [ABORT][122] ([Intel XE#8007])
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-lnl-3/igt@xe_copy_basic@mem-page-copy-17.html
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-5/igt@xe_copy_basic@mem-page-copy-17.html
* igt@xe_create@invalid-pad:
- shard-bmg: [PASS][123] -> [SKIP][124] ([Intel XE#6557] / [Intel XE#6703]) +1 other test skip
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@xe_create@invalid-pad.html
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@xe_create@invalid-pad.html
* igt@xe_create@multigpu-create-massive-size:
- shard-bmg: NOTRUN -> [SKIP][125] ([Intel XE#2504] / [Intel XE#7319] / [Intel XE#7350])
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-9/igt@xe_create@multigpu-create-massive-size.html
* igt@xe_eudebug@basic-connect:
- shard-lnl: NOTRUN -> [SKIP][126] ([Intel XE#7636]) +13 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-7/igt@xe_eudebug@basic-connect.html
* igt@xe_eudebug@vm-bind-clear:
- shard-bmg: NOTRUN -> [SKIP][127] ([Intel XE#7636]) +21 other tests skip
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-3/igt@xe_eudebug@vm-bind-clear.html
* igt@xe_eudebug_sriov@deny-eudebug:
- shard-lnl: NOTRUN -> [SKIP][128] ([Intel XE#4518] / [Intel XE#7404])
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@xe_eudebug_sriov@deny-eudebug.html
- shard-bmg: NOTRUN -> [SKIP][129] ([Intel XE#5793] / [Intel XE#7320] / [Intel XE#7464])
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-6/igt@xe_eudebug_sriov@deny-eudebug.html
* igt@xe_evict@evict-beng-cm-threads-small:
- shard-lnl: NOTRUN -> [SKIP][130] ([Intel XE#6540] / [Intel XE#688]) +12 other tests skip
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-6/igt@xe_evict@evict-beng-cm-threads-small.html
* igt@xe_evict@evict-small-multi-queue-priority:
- shard-bmg: NOTRUN -> [SKIP][131] ([Intel XE#7140]) +1 other test skip
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-1/igt@xe_evict@evict-small-multi-queue-priority.html
* igt@xe_exec_balancer@many-cm-parallel-userptr-invalidate:
- shard-lnl: NOTRUN -> [SKIP][132] ([Intel XE#7482]) +19 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-3/igt@xe_exec_balancer@many-cm-parallel-userptr-invalidate.html
* igt@xe_exec_basic@multigpu-once-null-rebind:
- shard-bmg: NOTRUN -> [SKIP][133] ([Intel XE#2322] / [Intel XE#7372]) +13 other tests skip
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-3/igt@xe_exec_basic@multigpu-once-null-rebind.html
* igt@xe_exec_basic@multigpu-once-userptr-invalidate:
- shard-lnl: NOTRUN -> [SKIP][134] ([Intel XE#1392]) +8 other tests skip
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-6/igt@xe_exec_basic@multigpu-once-userptr-invalidate.html
* igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-invalidate-imm:
- shard-bmg: NOTRUN -> [SKIP][135] ([Intel XE#7136]) +21 other tests skip
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-invalidate-imm.html
* igt@xe_exec_fault_mode@twice-multi-queue-userptr-imm:
- shard-lnl: NOTRUN -> [SKIP][136] ([Intel XE#7136]) +12 other tests skip
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@xe_exec_fault_mode@twice-multi-queue-userptr-imm.html
* igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-userptr-invalidate:
- shard-bmg: NOTRUN -> [SKIP][137] ([Intel XE#6874]) +45 other tests skip
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-1/igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-userptr-invalidate.html
* igt@xe_exec_multi_queue@one-queue-basic:
- shard-lnl: NOTRUN -> [SKIP][138] ([Intel XE#6874]) +34 other tests skip
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@xe_exec_multi_queue@one-queue-basic.html
* igt@xe_exec_reset@cm-multi-queue-gt-reset:
- shard-lnl: NOTRUN -> [SKIP][139] ([Intel XE#7866]) +1 other test skip
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-7/igt@xe_exec_reset@cm-multi-queue-gt-reset.html
* igt@xe_exec_reset@multi-queue-gt-reset:
- shard-bmg: NOTRUN -> [SKIP][140] ([Intel XE#7866]) +3 other tests skip
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-1/igt@xe_exec_reset@multi-queue-gt-reset.html
* igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-wt-single-vma:
- shard-lnl: NOTRUN -> [SKIP][141] ([Intel XE#6196])
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-wt-single-vma.html
* igt@xe_exec_system_allocator@process-many-large-mmap-nomemset:
- shard-bmg: [PASS][142] -> [SKIP][143] ([Intel XE#6703]) +134 other tests skip
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@xe_exec_system_allocator@process-many-large-mmap-nomemset.html
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@xe_exec_system_allocator@process-many-large-mmap-nomemset.html
* igt@xe_exec_threads@threads-multi-queue-mixed-fd-userptr-invalidate:
- shard-lnl: NOTRUN -> [SKIP][144] ([Intel XE#7138]) +7 other tests skip
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-1/igt@xe_exec_threads@threads-multi-queue-mixed-fd-userptr-invalidate.html
* igt@xe_exec_threads@threads-multi-queue-mixed-userptr-invalidate-race:
- shard-bmg: NOTRUN -> [SKIP][145] ([Intel XE#7138]) +11 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-1/igt@xe_exec_threads@threads-multi-queue-mixed-userptr-invalidate-race.html
* igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit:
- shard-bmg: NOTRUN -> [SKIP][146] ([Intel XE#2229])
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-1/igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit.html
* igt@xe_live_ktest@xe_eudebug:
- shard-bmg: NOTRUN -> [SKIP][147] ([Intel XE#2833])
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@xe_live_ktest@xe_eudebug.html
* igt@xe_media_fill@media-fill:
- shard-lnl: NOTRUN -> [SKIP][148] ([Intel XE#560] / [Intel XE#7321] / [Intel XE#7453])
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-7/igt@xe_media_fill@media-fill.html
* igt@xe_mmap@pci-membarrier:
- shard-lnl: NOTRUN -> [SKIP][149] ([Intel XE#5100] / [Intel XE#7322] / [Intel XE#7408]) +1 other test skip
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@xe_mmap@pci-membarrier.html
* igt@xe_multigpu_svm@mgpu-concurrent-access-prefetch:
- shard-bmg: NOTRUN -> [SKIP][150] ([Intel XE#6964]) +6 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-3/igt@xe_multigpu_svm@mgpu-concurrent-access-prefetch.html
* igt@xe_multigpu_svm@mgpu-latency-copy-basic:
- shard-lnl: NOTRUN -> [SKIP][151] ([Intel XE#6964]) +1 other test skip
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@xe_multigpu_svm@mgpu-latency-copy-basic.html
* igt@xe_noexec_ping_pong@basic:
- shard-lnl: NOTRUN -> [SKIP][152] ([Intel XE#6259] / [Intel XE#7324] / [Intel XE#7406])
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-6/igt@xe_noexec_ping_pong@basic.html
* igt@xe_page_reclaim@pde-vs-pd:
- shard-lnl: NOTRUN -> [SKIP][153] ([Intel XE#7793]) +2 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@xe_page_reclaim@pde-vs-pd.html
- shard-bmg: NOTRUN -> [SKIP][154] ([Intel XE#7793]) +1 other test skip
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-6/igt@xe_page_reclaim@pde-vs-pd.html
* igt@xe_pat@pat-index-xelp:
- shard-bmg: NOTRUN -> [SKIP][155] ([Intel XE#2245] / [Intel XE#7590])
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@xe_pat@pat-index-xelp.html
* igt@xe_pat@pat-sw-hw-reset-compare:
- shard-bmg: NOTRUN -> [FAIL][156] ([Intel XE#7695]) +2 other tests fail
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-3/igt@xe_pat@pat-sw-hw-reset-compare.html
* igt@xe_pat@xa-app-transient-media-off:
- shard-lnl: NOTRUN -> [SKIP][157] ([Intel XE#7590] / [Intel XE#7772])
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-7/igt@xe_pat@xa-app-transient-media-off.html
* igt@xe_peer2peer@read:
- shard-lnl: NOTRUN -> [SKIP][158] ([Intel XE#1061] / [Intel XE#7326] / [Intel XE#7353])
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-1/igt@xe_peer2peer@read.html
- shard-bmg: NOTRUN -> [SKIP][159] ([Intel XE#2427] / [Intel XE#6953] / [Intel XE#7326] / [Intel XE#7353])
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-10/igt@xe_peer2peer@read.html
* igt@xe_pm@d3cold-multiple-execs:
- shard-bmg: NOTRUN -> [SKIP][160] ([Intel XE#2284] / [Intel XE#7370]) +1 other test skip
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-6/igt@xe_pm@d3cold-multiple-execs.html
- shard-lnl: NOTRUN -> [SKIP][161] ([Intel XE#2284] / [Intel XE#366] / [Intel XE#7370])
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@xe_pm@d3cold-multiple-execs.html
* igt@xe_pm@d3hot-i2c:
- shard-bmg: NOTRUN -> [SKIP][162] ([Intel XE#5742] / [Intel XE#7328] / [Intel XE#7400])
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@xe_pm@d3hot-i2c.html
* igt@xe_pm@s3-exec-after:
- shard-lnl: NOTRUN -> [SKIP][163] ([Intel XE#584] / [Intel XE#7369]) +1 other test skip
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@xe_pm@s3-exec-after.html
* igt@xe_pmu@fn-engine-activity-sched-if-idle:
- shard-lnl: NOTRUN -> [SKIP][164] ([Intel XE#4650] / [Intel XE#7347])
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-3/igt@xe_pmu@fn-engine-activity-sched-if-idle.html
* igt@xe_prefetch_fault@prefetch-fault-svm:
- shard-bmg: NOTRUN -> [SKIP][165] ([Intel XE#7599])
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@xe_prefetch_fault@prefetch-fault-svm.html
* igt@xe_pxp@pxp-termination-key-update-post-suspend:
- shard-bmg: NOTRUN -> [SKIP][166] ([Intel XE#4733] / [Intel XE#7417]) +5 other tests skip
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-6/igt@xe_pxp@pxp-termination-key-update-post-suspend.html
* igt@xe_query@multigpu-query-invalid-cs-cycles:
- shard-bmg: NOTRUN -> [SKIP][167] ([Intel XE#944]) +3 other tests skip
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-9/igt@xe_query@multigpu-query-invalid-cs-cycles.html
* igt@xe_query@multigpu-query-mem-usage:
- shard-lnl: NOTRUN -> [SKIP][168] ([Intel XE#944])
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-7/igt@xe_query@multigpu-query-mem-usage.html
* igt@xe_sriov_admin@exec-quantum-write-readback-vfs-disabled:
- shard-lnl: NOTRUN -> [SKIP][169] ([Intel XE#7174])
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-7/igt@xe_sriov_admin@exec-quantum-write-readback-vfs-disabled.html
* igt@xe_sriov_auto_provisioning@fair-allocation:
- shard-lnl: NOTRUN -> [SKIP][170] ([Intel XE#4130] / [Intel XE#7366]) +1 other test skip
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-1/igt@xe_sriov_auto_provisioning@fair-allocation.html
* igt@xe_sriov_vram@vf-access-beyond:
- shard-lnl: NOTRUN -> [SKIP][171] ([Intel XE#6376] / [Intel XE#7330] / [Intel XE#7422])
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-2/igt@xe_sriov_vram@vf-access-beyond.html
#### Possible fixes ####
* igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3:
- shard-bmg: [FAIL][172] ([Intel XE#3321]) -> [PASS][173]
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3.html
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-4/igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-lnl: [FAIL][174] ([Intel XE#301]) -> [PASS][175] +1 other test pass
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_hdr@invalid-hdr:
- shard-bmg: [SKIP][176] ([Intel XE#1503]) -> [PASS][177]
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-6/igt@kms_hdr@invalid-hdr.html
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-8/igt@kms_hdr@invalid-hdr.html
* igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb16161616f:
- shard-bmg: [SKIP][178] ([Intel XE#7922]) -> [PASS][179] +1 other test pass
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-6/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb16161616f.html
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-8/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb16161616f.html
* igt@kms_pipe_crc_basic@nonblocking-crc:
- shard-bmg: [DMESG-FAIL][180] ([Intel XE#5545] / [Intel XE#7774]) -> [PASS][181] +1 other test pass
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@kms_pipe_crc_basic@nonblocking-crc.html
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-5/igt@kms_pipe_crc_basic@nonblocking-crc.html
* igt@kms_plane_multiple@2x-tiling-none:
- shard-bmg: [ABORT][182] -> [PASS][183]
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-none.html
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-3/igt@kms_plane_multiple@2x-tiling-none.html
* igt@kms_plane_multiple@2x-tiling-none@pipe-c-dp-2-pipe-a-hdmi-a-3:
- shard-bmg: [DMESG-FAIL][184] -> [PASS][185]
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-none@pipe-c-dp-2-pipe-a-hdmi-a-3.html
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-3/igt@kms_plane_multiple@2x-tiling-none@pipe-c-dp-2-pipe-a-hdmi-a-3.html
* igt@kms_plane_multiple@2x-tiling-none@pipe-c-dp-2-pipe-b-hdmi-a-3:
- shard-bmg: [ABORT][186] ([Intel XE#5545] / [Intel XE#6652] / [Intel XE#7814]) -> [PASS][187]
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-none@pipe-c-dp-2-pipe-b-hdmi-a-3.html
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-3/igt@kms_plane_multiple@2x-tiling-none@pipe-c-dp-2-pipe-b-hdmi-a-3.html
* igt@kms_psr@psr2-suspend:
- shard-lnl: [ABORT][188] ([Intel XE#2625]) -> [PASS][189] +4 other tests pass
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-lnl-4/igt@kms_psr@psr2-suspend.html
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-lnl-6/igt@kms_psr@psr2-suspend.html
* igt@xe_exec_system_allocator@process-many-large-execqueues-new-nomemset:
- shard-bmg: [SKIP][190] ([Intel XE#6703]) -> [PASS][191] +24 other tests pass
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@xe_exec_system_allocator@process-many-large-execqueues-new-nomemset.html
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-5/igt@xe_exec_system_allocator@process-many-large-execqueues-new-nomemset.html
* igt@xe_pm@s3-exec-after:
- shard-bmg: [ABORT][192] ([Intel XE#1794]) -> [PASS][193]
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-4/igt@xe_pm@s3-exec-after.html
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-6/igt@xe_pm@s3-exec-after.html
#### Warnings ####
* igt@kms_big_fb@x-tiled-64bpp-rotate-270:
- shard-bmg: [SKIP][194] ([Intel XE#2327]) -> [SKIP][195] ([Intel XE#6703])
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-bmg: [SKIP][196] ([Intel XE#6703]) -> [SKIP][197] ([Intel XE#1124])
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-5/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
- shard-bmg: [SKIP][198] ([Intel XE#1124]) -> [SKIP][199] ([Intel XE#6703]) +2 other tests skip
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
* igt@kms_bw@connected-linear-tiling-4-displays-target-2160x1440p:
- shard-bmg: [SKIP][200] ([Intel XE#7679]) -> [SKIP][201] ([Intel XE#6703])
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_bw@connected-linear-tiling-4-displays-target-2160x1440p.html
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_bw@connected-linear-tiling-4-displays-target-2160x1440p.html
* igt@kms_bw@linear-tiling-4-displays-target-3840x2160p:
- shard-bmg: [SKIP][202] ([Intel XE#367]) -> [SKIP][203] ([Intel XE#6703])
[202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_bw@linear-tiling-4-displays-target-3840x2160p.html
[203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_bw@linear-tiling-4-displays-target-3840x2160p.html
* igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc:
- shard-bmg: [SKIP][204] ([Intel XE#6703]) -> [SKIP][205] ([Intel XE#2887])
[204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc.html
[205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-5/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs:
- shard-bmg: [SKIP][206] ([Intel XE#2887]) -> [SKIP][207] ([Intel XE#6703]) +2 other tests skip
[206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs.html
[207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs.html
* igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode:
- shard-bmg: [SKIP][208] ([Intel XE#2252]) -> [SKIP][209] ([Intel XE#6703]) +1 other test skip
[208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode.html
[209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode.html
* igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
- shard-bmg: [SKIP][210] ([Intel XE#6703]) -> [SKIP][211] ([Intel XE#2252])
[210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html
[211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-5/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html
* igt@kms_content_protection@dp-mst-type-0-hdcp14:
- shard-bmg: [SKIP][212] ([Intel XE#6703]) -> [SKIP][213] ([Intel XE#6974])
[212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@kms_content_protection@dp-mst-type-0-hdcp14.html
[213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-5/igt@kms_content_protection@dp-mst-type-0-hdcp14.html
* igt@kms_content_protection@dp-mst-type-1-suspend-resume:
- shard-bmg: [SKIP][214] ([Intel XE#6974]) -> [SKIP][215] ([Intel XE#6703])
[214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_content_protection@dp-mst-type-1-suspend-resume.html
[215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_content_protection@dp-mst-type-1-suspend-resume.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-bmg: [SKIP][216] ([Intel XE#6703]) -> [FAIL][217] ([Intel XE#7571])
[216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
- shard-bmg: [SKIP][218] ([Intel XE#7178] / [Intel XE#7351]) -> [SKIP][219] ([Intel XE#6703]) +1 other test skip
[218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
[219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-plflip-blt:
- shard-bmg: [SKIP][220] ([Intel XE#6703]) -> [SKIP][221] ([Intel XE#2311]) +1 other test skip
[220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-plflip-blt.html
[221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-blt:
- shard-bmg: [SKIP][222] ([Intel XE#2311]) -> [SKIP][223] ([Intel XE#6703]) +12 other tests skip
[222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-blt.html
[223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt:
- shard-bmg: [SKIP][224] ([Intel XE#4141]) -> [SKIP][225] ([Intel XE#6703]) +2 other tests skip
[224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html
[225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][226] ([Intel XE#6703]) -> [SKIP][227] ([Intel XE#2313]) +2 other tests skip
[226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][228] ([Intel XE#2313]) -> [SKIP][229] ([Intel XE#6703]) +12 other tests skip
[228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-primscrn-pri-indfb-draw-mmap-wc.html
[229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-argb161616f-draw-mmap-wc:
- shard-bmg: [SKIP][230] ([Intel XE#6703]) -> [SKIP][231] ([Intel XE#7061] / [Intel XE#7356])
[230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-argb161616f-draw-mmap-wc.html
[231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-argb161616f-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psrhdr-abgr161616f-draw-blt:
- shard-bmg: [SKIP][232] ([Intel XE#7061]) -> [SKIP][233] ([Intel XE#6703])
[232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_frontbuffer_tracking@psrhdr-abgr161616f-draw-blt.html
[233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_frontbuffer_tracking@psrhdr-abgr161616f-draw-blt.html
* igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping:
- shard-bmg: [SKIP][234] ([Intel XE#7283]) -> [SKIP][235] ([Intel XE#6703])
[234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping.html
[235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping.html
* igt@kms_plane_scaling@planes-downscale-factor-0-75:
- shard-bmg: [SKIP][236] ([Intel XE#2763] / [Intel XE#6886]) -> [SKIP][237] ([Intel XE#6703])
[236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_plane_scaling@planes-downscale-factor-0-75.html
[237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_plane_scaling@planes-downscale-factor-0-75.html
* igt@kms_pm_dc@dc5-retention-flops:
- shard-bmg: [SKIP][238] ([Intel XE#3309] / [Intel XE#7368]) -> [SKIP][239] ([Intel XE#6703])
[238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_pm_dc@dc5-retention-flops.html
[239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_pm_dc@dc5-retention-flops.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-bmg: [SKIP][240] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383] / [Intel XE#836]) -> [SKIP][241] ([Intel XE#6703])
[240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_pm_rpm@modeset-lpsp.html
[241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf:
- shard-bmg: [SKIP][242] ([Intel XE#1489]) -> [SKIP][243] ([Intel XE#6703])
[242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf.html
[243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf:
- shard-bmg: [SKIP][244] ([Intel XE#6703]) -> [SKIP][245] ([Intel XE#1489]) +1 other test skip
[244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf.html
[245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-5/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-bmg: [SKIP][246] ([Intel XE#2387] / [Intel XE#7429]) -> [SKIP][247] ([Intel XE#6703])
[246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_psr2_su@frontbuffer-xrgb8888.html
[247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@pr-dpms:
- shard-bmg: [SKIP][248] ([Intel XE#2234] / [Intel XE#2850]) -> [SKIP][249] ([Intel XE#6703]) +1 other test skip
[248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_psr@pr-dpms.html
[249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_psr@pr-dpms.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
- shard-bmg: [SKIP][250] ([Intel XE#3904] / [Intel XE#7342]) -> [SKIP][251] ([Intel XE#6703])
[250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
[251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
* igt@kms_sharpness_filter@invalid-filter-with-nearest-neighbor:
- shard-bmg: [SKIP][252] ([Intel XE#6703]) -> [SKIP][253] ([Intel XE#6503])
[252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@kms_sharpness_filter@invalid-filter-with-nearest-neighbor.html
[253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-5/igt@kms_sharpness_filter@invalid-filter-with-nearest-neighbor.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-bmg: [SKIP][254] ([Intel XE#2426] / [Intel XE#5848]) -> [FAIL][255] ([Intel XE#1729] / [Intel XE#7424])
[254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html
[255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_vrr@flip-basic-fastset:
- shard-bmg: [SKIP][256] ([Intel XE#6703]) -> [SKIP][257] ([Intel XE#1499])
[256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@kms_vrr@flip-basic-fastset.html
[257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-5/igt@kms_vrr@flip-basic-fastset.html
* igt@xe_eudebug_online@writes-caching-sram-bb-sram-target-sram:
- shard-bmg: [SKIP][258] ([Intel XE#6703]) -> [SKIP][259] ([Intel XE#7636])
[258]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@xe_eudebug_online@writes-caching-sram-bb-sram-target-sram.html
[259]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-5/igt@xe_eudebug_online@writes-caching-sram-bb-sram-target-sram.html
* igt@xe_eudebug_sriov@deny-sriov:
- shard-bmg: [SKIP][260] ([Intel XE#5793] / [Intel XE#7320] / [Intel XE#7464]) -> [SKIP][261] ([Intel XE#6703])
[260]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@xe_eudebug_sriov@deny-sriov.html
[261]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@xe_eudebug_sriov@deny-sriov.html
* igt@xe_evict@evict-small-multi-queue:
- shard-bmg: [SKIP][262] ([Intel XE#7140]) -> [SKIP][263] ([Intel XE#6703])
[262]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@xe_evict@evict-small-multi-queue.html
[263]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@xe_evict@evict-small-multi-queue.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race:
- shard-bmg: [SKIP][264] ([Intel XE#2322] / [Intel XE#7372]) -> [SKIP][265] ([Intel XE#6703])
[264]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race.html
[265]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race.html
* igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind:
- shard-bmg: [SKIP][266] ([Intel XE#6703]) -> [SKIP][267] ([Intel XE#2322] / [Intel XE#7372])
[266]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind.html
[267]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-5/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind.html
* igt@xe_exec_fault_mode@many-execqueues-multi-queue-invalid-userptr-fault:
- shard-bmg: [SKIP][268] ([Intel XE#6703]) -> [SKIP][269] ([Intel XE#7136])
[268]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@xe_exec_fault_mode@many-execqueues-multi-queue-invalid-userptr-fault.html
[269]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-5/igt@xe_exec_fault_mode@many-execqueues-multi-queue-invalid-userptr-fault.html
* igt@xe_exec_fault_mode@twice-multi-queue-userptr:
- shard-bmg: [SKIP][270] ([Intel XE#7136]) -> [SKIP][271] ([Intel XE#6703])
[270]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@xe_exec_fault_mode@twice-multi-queue-userptr.html
[271]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@xe_exec_fault_mode@twice-multi-queue-userptr.html
* igt@xe_exec_multi_queue@many-queues-dyn-priority-smem:
- shard-bmg: [SKIP][272] ([Intel XE#6703]) -> [SKIP][273] ([Intel XE#6874]) +2 other tests skip
[272]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@xe_exec_multi_queue@many-queues-dyn-priority-smem.html
[273]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-5/igt@xe_exec_multi_queue@many-queues-dyn-priority-smem.html
* igt@xe_exec_multi_queue@many-queues-priority-smem:
- shard-bmg: [SKIP][274] ([Intel XE#6874]) -> [SKIP][275] ([Intel XE#6703]) +5 other tests skip
[274]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@xe_exec_multi_queue@many-queues-priority-smem.html
[275]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@xe_exec_multi_queue@many-queues-priority-smem.html
* igt@xe_exec_sip_eudebug@breakpoint-writesip-nodebug:
- shard-bmg: [SKIP][276] ([Intel XE#7636]) -> [SKIP][277] ([Intel XE#6703]) +2 other tests skip
[276]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@xe_exec_sip_eudebug@breakpoint-writesip-nodebug.html
[277]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@xe_exec_sip_eudebug@breakpoint-writesip-nodebug.html
* igt@xe_exec_threads@threads-multi-queue-cm-fd-basic:
- shard-bmg: [SKIP][278] ([Intel XE#6703]) -> [SKIP][279] ([Intel XE#7138])
[278]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-cm-fd-basic.html
[279]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-5/igt@xe_exec_threads@threads-multi-queue-cm-fd-basic.html
* igt@xe_exec_threads@threads-multi-queue-cm-userptr-invalidate-race:
- shard-bmg: [SKIP][280] ([Intel XE#7138]) -> [SKIP][281] ([Intel XE#6703]) +1 other test skip
[280]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@xe_exec_threads@threads-multi-queue-cm-userptr-invalidate-race.html
[281]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-cm-userptr-invalidate-race.html
* igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add:
- shard-bmg: [SKIP][282] ([Intel XE#6703]) -> [SKIP][283] ([Intel XE#6281] / [Intel XE#7426])
[282]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add.html
[283]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-5/igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add.html
* igt@xe_page_reclaim@boundary-split:
- shard-bmg: [SKIP][284] ([Intel XE#6703]) -> [SKIP][285] ([Intel XE#7793])
[284]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@xe_page_reclaim@boundary-split.html
[285]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-5/igt@xe_page_reclaim@boundary-split.html
* igt@xe_pm@d3cold-mmap-vram:
- shard-bmg: [SKIP][286] ([Intel XE#2284] / [Intel XE#7370]) -> [SKIP][287] ([Intel XE#6703])
[286]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@xe_pm@d3cold-mmap-vram.html
[287]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@xe_pm@d3cold-mmap-vram.html
* igt@xe_pxp@pxp-optout:
- shard-bmg: [SKIP][288] ([Intel XE#4733] / [Intel XE#7417]) -> [SKIP][289] ([Intel XE#6703])
[288]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@xe_pxp@pxp-optout.html
[289]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@xe_pxp@pxp-optout.html
* igt@xe_pxp@pxp-stale-bo-exec-post-suspend:
- shard-bmg: [SKIP][290] ([Intel XE#6703]) -> [SKIP][291] ([Intel XE#4733] / [Intel XE#7417])
[290]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-2/igt@xe_pxp@pxp-stale-bo-exec-post-suspend.html
[291]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-5/igt@xe_pxp@pxp-stale-bo-exec-post-suspend.html
* igt@xe_query@multigpu-query-pxp-status:
- shard-bmg: [SKIP][292] ([Intel XE#944]) -> [SKIP][293] ([Intel XE#6703])
[292]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb/shard-bmg-5/igt@xe_query@multigpu-query-pxp-status.html
[293]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/shard-bmg-2/igt@xe_query@multigpu-query-pxp-status.html
[Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
[Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1428
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1468]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1468
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
[Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
[Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
[Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
[Intel XE#2233]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2233
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2245]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2245
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328
[Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
[Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
[Intel XE#2374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2374
[Intel XE#2375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2375
[Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
[Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2427]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2427
[Intel XE#2450]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2450
[Intel XE#2499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2499
[Intel XE#2504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2504
[Intel XE#2625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2625
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
[Intel XE#2833]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2833
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
[Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
[Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
[Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
[Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#3658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3658
[Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4156]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4156
[Intel XE#4294]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4294
[Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
[Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
[Intel XE#4518]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4518
[Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
[Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
[Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
[Intel XE#4650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4650
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
[Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
[Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
[Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
[Intel XE#560]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/560
[Intel XE#5742]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5742
[Intel XE#5793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5793
[Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
[Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
[Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
[Intel XE#5854]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5854
[Intel XE#5857]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5857
[Intel XE#5882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5882
[Intel XE#6010]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6010
[Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
[Intel XE#6126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6126
[Intel XE#6127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6127
[Intel XE#6196]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6196
[Intel XE#6259]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6259
[Intel XE#6281]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6281
[Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
[Intel XE#6376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6376
[Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
[Intel XE#6557]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6557
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#6599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6599
[Intel XE#6652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6652
[Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
[Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
[Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
[Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
[Intel XE#6953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6953
[Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
[Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
[Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701
[Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
[Intel XE#7086]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7086
[Intel XE#7130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7130
[Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
[Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
[Intel XE#7140]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7140
[Intel XE#7174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7174
[Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
[Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
[Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
[Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
[Intel XE#7317]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7317
[Intel XE#7319]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7319
[Intel XE#7320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7320
[Intel XE#7321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7321
[Intel XE#7322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7322
[Intel XE#7324]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7324
[Intel XE#7326]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7326
[Intel XE#7328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7328
[Intel XE#7330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7330
[Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
[Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
[Intel XE#7345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7345
[Intel XE#7347]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7347
[Intel XE#7348]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7348
[Intel XE#7349]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7349
[Intel XE#7350]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7350
[Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
[Intel XE#7353]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7353
[Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
[Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
[Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
[Intel XE#7359]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7359
[Intel XE#7360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7360
[Intel XE#7361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7361
[Intel XE#7366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7366
[Intel XE#7367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7367
[Intel XE#7368]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7368
[Intel XE#7369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7369
[Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
[Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
[Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
[Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
[Intel XE#7377]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7377
[Intel XE#7378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7378
[Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
[Intel XE#7385]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7385
[Intel XE#7386]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7386
[Intel XE#7387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7387
[Intel XE#7390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7390
[Intel XE#7396]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7396
[Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
[Intel XE#7400]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7400
[Intel XE#7404]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7404
[Intel XE#7406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7406
[Intel XE#7408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7408
[Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
[Intel XE#7422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7422
[Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
[Intel XE#7425]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7425
[Intel XE#7426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7426
[Intel XE#7429]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7429
[Intel XE#7442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7442
[Intel XE#7448]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7448
[Intel XE#7453]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7453
[Intel XE#7455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7455
[Intel XE#7464]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7464
[Intel XE#7477]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7477
[Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
[Intel XE#7571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7571
[Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
[Intel XE#7599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7599
[Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
[Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
[Intel XE#7644]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7644
[Intel XE#7676]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7676
[Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
[Intel XE#7695]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7695
[Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
[Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
[Intel XE#7772]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7772
[Intel XE#7774]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7774
[Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
[Intel XE#7794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7794
[Intel XE#7814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7814
[Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
[Intel XE#7866]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7866
[Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
[Intel XE#7915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7915
[Intel XE#7922]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7922
[Intel XE#7950]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7950
[Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
[Intel XE#8076]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8076
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* Linux: xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb -> xe-pw-167391v1
IGT_8939: 8939
xe-5138-11a8456527f00d86dc8b23035c324da194fbbadb: 11a8456527f00d86dc8b23035c324da194fbbadb
xe-pw-167391v1: 167391v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167391v1/index.html
[-- Attachment #2: Type: text/html, Size: 107702 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/xe/ggtt: use full-range drm_mm with reserved nodes on PF
2026-05-27 14:45 [PATCH] drm/xe/ggtt: use full-range drm_mm with reserved nodes on PF Rodrigo Vivi
` (2 preceding siblings ...)
2026-05-28 1:47 ` ✗ Xe.CI.FULL: failure " Patchwork
@ 2026-05-28 22:11 ` Michal Wajdeczko
2026-05-28 22:28 ` Rodrigo Vivi
2026-06-03 12:57 ` [PATCH] drm/xe/ggtt: clear reserved area at GUC_GGTT_TOP Maarten Lankhorst
4 siblings, 1 reply; 13+ messages in thread
From: Michal Wajdeczko @ 2026-05-28 22:11 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx, intel-xe
Cc: Ville Syrjälä, Maarten Lankhorst
On 5/27/2026 4:45 PM, Rodrigo Vivi wrote:
> The PF GGTT allocator was initialised over a relative [0, usable_size)
> range, with ggtt->start added on every address conversion to get the
> actual hardware address. Two consequences of that model were considered
> "horrible hacks":
>
> - ggtt->start (the WOPCM offset) had to be carried around and added
> to every drm_mm result.
hmm, but this an internal detail of the xe_ggtt implementation, so why
would someone else complain about it?
> - The GUC_GGTT_TOP ceiling silently truncated the GGTT range instead
hmm, for the record, this GGTT cap on the top was added back in 2023
commit ab10e976fbda8349163ceee2ce99b2bfc97031b8
Author: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Date: Wed Jun 14 10:47:54 2023 -0700
drm/xe: limit GGTT size to GUC_GGTT_TOP
+ * The GuC address space is limited on both ends of the GGTT, because
+ * the GuC shim HW redirects accesses to those addresses to other HW
+ * areas instead of going through the GGTT. On the bottom end, the GuC
+ * can't access offsets below the WOPCM size, while on the top side the
+ * limit is fixed at GUC_GGTT_TOP. To keep things simple, instead of
+ * checking each object to see if they are accessed by GuC or not, we
+ * just exclude those areas from the allocator. Additionally, to
+ * simplify the driver load, we use the maximum WOPCM size in this logic
> of being made explicit, leaving PTEs in [GUC_GGTT_TOP, total_size)
> untouched during the initial clear.
and that likely will not be changed by this patch as after allocating 'two
permanent zones', the drm_mm_for_each_hole will not iterate over them
>
> Fix this for the PF case by initialising drm_mm over the full hardware
> GGTT range [0, total_size) and permanently reserving the two forbidden
> zones:
>
> - [0, wopcm) — inaccessible below WOPCM
> - [GUC_GGTT_TOP, total_size) — inaccessible above GUC_GGTT_TOP
that looks odds: why pretend to claim manageability of full [0, 4GB)
of the GGTT and then immediately permanently reserve two end zones to
end up with real [wopcm, GUC_TOP) which is what we already have?
>
> A new mm_offset field (zero for PF) carries the base offset used in
> address conversions, unifying the existing VF relative model (where
> mm_offset == vf_base) with the new PF absolute model.
but public xe_ggtt API already uses absolute addressing in PF and VF
> The public
> xe_ggtt_start() / xe_ggtt_size() API continues to return the usable
> [wopcm, GUC_GGTT_TOP) boundaries, so callers such as the SR-IOV PF
> config code are unaffected.
>
> xe_ggtt_shift_nodes() now updates both ggtt->start and ggtt->mm_offset
> so the VF recovery path remains a single O(1) WRITE_ONCE pair.
maybe it's just me - but I can't figure out the real rationale for this
patch - what did I miss?
>
> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Assisted-by: GitHub-Copilot:claude-sonnet-4.6
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/xe/xe_ggtt.c | 123 ++++++++++++++++++++++++++++-------
> 1 file changed, 101 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> index a351c578b170..00a6cd2b8a51 100644
> --- a/drivers/gpu/drm/xe/xe_ggtt.c
> +++ b/drivers/gpu/drm/xe/xe_ggtt.c
> @@ -137,6 +137,17 @@ struct xe_ggtt {
> const struct xe_ggtt_pt_ops *pt_ops;
> /** @mm: The memory manager used to manage individual GGTT allocations */
> struct drm_mm mm;
> + /**
> + * @mm_offset: base offset added to drm_mm node addresses to obtain hardware
> + * GGTT addresses. For PF this is 0 (drm_mm uses absolute hardware addresses).
> + * For VF this equals @start (drm_mm uses relative addresses from VF base).
> + * Updated atomically by xe_ggtt_shift_nodes() during VF recovery.
> + */
> + u64 mm_offset;
> + /** @reserved_bottom: permanently reserved [0, WOPCM) drm_mm node for PF */
> + struct drm_mm_node reserved_bottom;
> + /** @reserved_top: permanently reserved [GUC_GGTT_TOP, total) drm_mm node for PF */
> + struct drm_mm_node reserved_top;
maybe all we need is to separate concepts of:
* raw GGTT - fixed range [0, 4GB)
from
* allocable GGTT - configurable sub-range [start, end)
* [wopcm, GUC_TOP) on PF
* [base, base+size) on VF
and then we can continue to use drm_mm.init(0, end-start) to manage
that [start, end) range in a common way on both PF and VF?
> /** @access_count: counts GGTT writes */
> unsigned int access_count;
> /** @wq: Dedicated unordered work queue to process node removals */
> @@ -318,6 +329,10 @@ static void ggtt_fini_early(struct drm_device *drm, void *arg)
> {
> struct xe_ggtt *ggtt = arg;
>
> + if (drm_mm_node_allocated(&ggtt->reserved_top))
> + drm_mm_remove_node(&ggtt->reserved_top);
> + if (drm_mm_node_allocated(&ggtt->reserved_bottom))
> + drm_mm_remove_node(&ggtt->reserved_bottom);
> destroy_workqueue(ggtt->wq);
> drm_mm_takedown(&ggtt->mm);
> }
> @@ -354,16 +369,66 @@ static const struct xe_ggtt_pt_ops xelpg_pt_wa_ops = {
> .ggtt_get_pte = xe_ggtt_get_pte,
> };
>
> -static void __xe_ggtt_init_early(struct xe_ggtt *ggtt, u64 start, u64 size)
> +/*
> + * __xe_ggtt_init_early - Generic drm_mm initialisation for both PF and VF.
> + *
> + * @start and @size define the usable GGTT range exposed through the public API.
> + * @mm_offset is added to every drm_mm node address to obtain the hardware
> + * address (0 for PF where the drm_mm spans real addresses; @start for VF).
> + * @mm_size is the total span passed to drm_mm_init() (equals @size for VF;
> + * equals the full hardware GGTT size for PF).
> + */
> +static void __xe_ggtt_init_early(struct xe_ggtt *ggtt, u64 start, u64 size,
> + u64 mm_offset, u64 mm_size)
> {
> ggtt->start = start;
> ggtt->size = size;
> - drm_mm_init(&ggtt->mm, 0, size);
> + ggtt->mm_offset = mm_offset;
> + drm_mm_init(&ggtt->mm, 0, mm_size);
> +}
> +
> +/*
> + * __xe_ggtt_reserve_pf_nodes - Permanently reserve the forbidden GGTT zones.
> + *
> + * Must be called after __xe_ggtt_init_early() for the PF case. Reserves
> + * [0, @wopcm) and [@guc_top, @total_size) so the allocator never hands them
> + * out. On failure the drm_mm is torn down and the error is returned.
> + */
> +static int __xe_ggtt_reserve_pf_nodes(struct xe_ggtt *ggtt, u64 wopcm,
> + u64 guc_top, u64 total_size)
> +{
> + int err;
> +
> + /* Reserve [0, wopcm) — GuC cannot access below WOPCM */
> + if (wopcm > 0) {
> + ggtt->reserved_bottom.start = 0;
> + ggtt->reserved_bottom.size = wopcm;
> + err = drm_mm_reserve_node(&ggtt->mm, &ggtt->reserved_bottom);
> + if (WARN_ON(err))
> + goto err_takedown;
> + }
> +
> + /* Reserve [guc_top, total_size) — GuC cannot access above GUC_GGTT_TOP */
> + if (guc_top < total_size) {
> + ggtt->reserved_top.start = guc_top;
> + ggtt->reserved_top.size = total_size - guc_top;
> + err = drm_mm_reserve_node(&ggtt->mm, &ggtt->reserved_top);
> + if (WARN_ON(err))
> + goto err_remove_bottom;
> + }
> +
> + return 0;
> +
> +err_remove_bottom:
> + drm_mm_remove_node(&ggtt->reserved_bottom);
> +err_takedown:
> + drm_mm_takedown(&ggtt->mm);
> + return err;
> }
>
> int xe_ggtt_init_kunit(struct xe_ggtt *ggtt, u32 start, u32 size)
> {
> - __xe_ggtt_init_early(ggtt, start, size);
> + __xe_ggtt_init_early(ggtt, start, size, start, size);
> return 0;
> }
> EXPORT_SYMBOL_IF_KUNIT(xe_ggtt_init_kunit);
> @@ -405,8 +470,13 @@ int xe_ggtt_init_early(struct xe_ggtt *ggtt)
> xe_tile_err(ggtt->tile, "Hardware reported no preallocated GSM\n");
> return -ENOMEM;
> }
> + /*
> + * For PF, ggtt_size holds the full hardware GGTT size. The
> + * WOPCM and GUC_GGTT_TOP limits are enforced via permanently
> + * reserved drm_mm nodes rather than by capping the range.
> + */
> ggtt_start = wopcm;
> - ggtt_size = (gsm_size / 8) * (u64)XE_PAGE_SIZE - ggtt_start;
> + ggtt_size = (gsm_size / 8) * (u64)XE_PAGE_SIZE;
> } else {
> ggtt_start = xe_tile_sriov_vf_ggtt_base(ggtt->tile);
> ggtt_size = xe_tile_sriov_vf_ggtt(ggtt->tile);
> @@ -423,9 +493,6 @@ int xe_ggtt_init_early(struct xe_ggtt *ggtt)
> if (IS_DGFX(xe) && xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K)
> ggtt->flags |= XE_GGTT_FLAGS_64K;
>
> - if (ggtt_size + ggtt_start > GUC_GGTT_TOP)
> - ggtt_size = GUC_GGTT_TOP - ggtt_start;
> -
> if (GRAPHICS_VERx100(xe) >= 1270)
> ggtt->pt_ops =
> (ggtt->tile->media_gt && XE_GT_WA(ggtt->tile->media_gt, 22019338487)) ||
> @@ -438,7 +505,19 @@ int xe_ggtt_init_early(struct xe_ggtt *ggtt)
> if (!ggtt->wq)
> return -ENOMEM;
>
> - __xe_ggtt_init_early(ggtt, ggtt_start, ggtt_size);
> + if (!IS_SRIOV_VF(xe)) {
> + __xe_ggtt_init_early(ggtt, ggtt_start, GUC_GGTT_TOP - ggtt_start,
> + 0, ggtt_size);
> + err = __xe_ggtt_reserve_pf_nodes(ggtt, ggtt_start, GUC_GGTT_TOP,
> + ggtt_size);
> + if (err) {
> + destroy_workqueue(ggtt->wq);
> + return err;
> + }
> + } else {
> + __xe_ggtt_init_early(ggtt, ggtt_start, ggtt_size,
> + ggtt_start, ggtt_size);
> + }
>
> err = drmm_add_action_or_reset(&xe->drm, ggtt_fini_early, ggtt);
> if (err)
> @@ -459,7 +538,7 @@ static void xe_ggtt_initial_clear(struct xe_ggtt *ggtt)
> /* Display may have allocated inside ggtt, so be careful with clearing here */
> mutex_lock(&ggtt->lock);
> drm_mm_for_each_hole(hole, &ggtt->mm, start, end)
> - xe_ggtt_clear(ggtt, ggtt->start + start, end - start);
> + xe_ggtt_clear(ggtt, ggtt->mm_offset + start, end - start);
>
> xe_ggtt_invalidate(ggtt);
> mutex_unlock(&ggtt->lock);
> @@ -613,6 +692,7 @@ void xe_ggtt_shift_nodes(struct xe_ggtt *ggtt, u64 new_start)
>
> /* pairs with READ_ONCE in xe_ggtt_node_addr() */
> WRITE_ONCE(ggtt->start, new_start);
> + WRITE_ONCE(ggtt->mm_offset, new_start);
> }
>
> static int xe_ggtt_insert_node_locked(struct xe_ggtt_node *node,
> @@ -815,20 +895,19 @@ static int __xe_ggtt_insert_bo_at(struct xe_ggtt *ggtt, struct xe_bo *bo,
>
> mutex_lock(&ggtt->lock);
> /*
> - * When inheriting the initial framebuffer, the framebuffer is
> - * physically located at VRAM address 0, and usually at GGTT address 0 too.
> - *
> - * The display code will ask for a GGTT allocation between end of BO and
> - * remainder of GGTT, unaware that the start is reserved by WOPCM.
> + * Convert caller-supplied hardware GGTT addresses to drm_mm-relative
> + * coordinates. For PF mm_offset is 0 so this is a no-op; callers pass
> + * real addresses and the reserved_bottom/top nodes prevent allocations
> + * in the forbidden regions. For VF, mm_offset equals the VF base so
> + * we convert to relative drm_mm space.
> */
> - if (start >= ggtt->start)
> - start -= ggtt->start;
> + if (start >= ggtt->mm_offset)
> + start -= ggtt->mm_offset;
> else
> start = 0;
>
> - /* Should never happen, but since we handle start, fail graciously for end */
> - if (end >= ggtt->start)
> - end -= ggtt->start;
> + if (end >= ggtt->mm_offset)
> + end -= ggtt->mm_offset;
> else
> end = 0;
>
> @@ -923,7 +1002,7 @@ u64 xe_ggtt_largest_hole(struct xe_ggtt *ggtt, u64 alignment, u64 *spare)
>
> mutex_lock(&ggtt->lock);
> drm_mm_for_each_hole(entry, mm, hole_start, hole_end) {
> - hole_start = max(hole_start, ggtt->start);
> + hole_start = max(hole_start, ggtt->mm_offset);
> hole_start = ALIGN(hole_start, alignment);
> hole_end = ALIGN_DOWN(hole_end, alignment);
> if (hole_start >= hole_end)
> @@ -1098,7 +1177,7 @@ u64 xe_ggtt_print_holes(struct xe_ggtt *ggtt, u64 alignment, struct drm_printer
>
> mutex_lock(&ggtt->lock);
> drm_mm_for_each_hole(entry, mm, hole_start, hole_end) {
> - hole_start = max(hole_start, ggtt->start);
> + hole_start = max(hole_start, ggtt->mm_offset);
> hole_start = ALIGN(hole_start, alignment);
> hole_end = ALIGN_DOWN(hole_end, alignment);
> if (hole_start >= hole_end)
> @@ -1152,7 +1231,7 @@ u64 xe_ggtt_read_pte(struct xe_ggtt *ggtt, u64 offset)
> u64 xe_ggtt_node_addr(const struct xe_ggtt_node *node)
> {
> /* pairs with WRITE_ONCE in xe_ggtt_shift_nodes() */
> - return node->base.start + READ_ONCE(node->ggtt->start);
> + return node->base.start + READ_ONCE(node->ggtt->mm_offset);
> }
>
> /**
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/xe/ggtt: use full-range drm_mm with reserved nodes on PF
2026-05-28 22:11 ` [PATCH] " Michal Wajdeczko
@ 2026-05-28 22:28 ` Rodrigo Vivi
2026-05-29 10:50 ` Ville Syrjälä
0 siblings, 1 reply; 13+ messages in thread
From: Rodrigo Vivi @ 2026-05-28 22:28 UTC (permalink / raw)
To: Michal Wajdeczko
Cc: intel-gfx, intel-xe, Ville Syrjälä, Maarten Lankhorst
On Fri, May 29, 2026 at 12:11:22AM +0200, Michal Wajdeczko wrote:
>
>
> On 5/27/2026 4:45 PM, Rodrigo Vivi wrote:
> > The PF GGTT allocator was initialised over a relative [0, usable_size)
> > range, with ggtt->start added on every address conversion to get the
> > actual hardware address. Two consequences of that model were considered
> > "horrible hacks":
> >
> > - ggtt->start (the WOPCM offset) had to be carried around and added
> > to every drm_mm result.
>
> hmm, but this an internal detail of the xe_ggtt implementation, so why
> would someone else complain about it?
>
> > - The GUC_GGTT_TOP ceiling silently truncated the GGTT range instead
>
> hmm, for the record, this GGTT cap on the top was added back in 2023
>
> commit ab10e976fbda8349163ceee2ce99b2bfc97031b8
> Author: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Date: Wed Jun 14 10:47:54 2023 -0700
>
> drm/xe: limit GGTT size to GUC_GGTT_TOP
>
> + * The GuC address space is limited on both ends of the GGTT, because
> + * the GuC shim HW redirects accesses to those addresses to other HW
> + * areas instead of going through the GGTT. On the bottom end, the GuC
> + * can't access offsets below the WOPCM size, while on the top side the
> + * limit is fixed at GUC_GGTT_TOP. To keep things simple, instead of
> + * checking each object to see if they are accessed by GuC or not, we
> + * just exclude those areas from the allocator. Additionally, to
> + * simplify the driver load, we use the maximum WOPCM size in this logic
>
> > of being made explicit, leaving PTEs in [GUC_GGTT_TOP, total_size)
> > untouched during the initial clear.
>
> and that likely will not be changed by this patch as after allocating 'two
> permanent zones', the drm_mm_for_each_hole will not iterate over them
right...
>
> >
> > Fix this for the PF case by initialising drm_mm over the full hardware
> > GGTT range [0, total_size) and permanently reserving the two forbidden
> > zones:
> >
> > - [0, wopcm) — inaccessible below WOPCM
> > - [GUC_GGTT_TOP, total_size) — inaccessible above GUC_GGTT_TOP
>
> that looks odds: why pretend to claim manageability of full [0, 4GB)
> of the GGTT and then immediately permanently reserve two end zones to
> end up with real [wopcm, GUC_TOP) which is what we already have?
yes...
>
> >
> > A new mm_offset field (zero for PF) carries the base offset used in
> > address conversions, unifying the existing VF relative model (where
> > mm_offset == vf_base) with the new PF absolute model.
>
> but public xe_ggtt API already uses absolute addressing in PF and VF
I know...
>
> > The public
> > xe_ggtt_start() / xe_ggtt_size() API continues to return the usable
> > [wopcm, GUC_GGTT_TOP) boundaries, so callers such as the SR-IOV PF
> > config code are unaffected.
> >
> > xe_ggtt_shift_nodes() now updates both ggtt->start and ggtt->mm_offset
> > so the VF recovery path remains a single O(1) WRITE_ONCE pair.
>
> maybe it's just me - but I can't figure out the real rationale for this
> patch - what did I miss?
This series:
https://lore.kernel.org/intel-xe/20260511214122.8468-1-ville.syrjala@linux.intel.com/
And more specifically the discussion in this patch:
https://lore.kernel.org/intel-xe/20260511214122.8468-13-ville.syrjala@linux.intel.com/
>
> >
> > Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Assisted-by: GitHub-Copilot:claude-sonnet-4.6
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_ggtt.c | 123 ++++++++++++++++++++++++++++-------
> > 1 file changed, 101 insertions(+), 22 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> > index a351c578b170..00a6cd2b8a51 100644
> > --- a/drivers/gpu/drm/xe/xe_ggtt.c
> > +++ b/drivers/gpu/drm/xe/xe_ggtt.c
> > @@ -137,6 +137,17 @@ struct xe_ggtt {
> > const struct xe_ggtt_pt_ops *pt_ops;
> > /** @mm: The memory manager used to manage individual GGTT allocations */
> > struct drm_mm mm;
> > + /**
> > + * @mm_offset: base offset added to drm_mm node addresses to obtain hardware
> > + * GGTT addresses. For PF this is 0 (drm_mm uses absolute hardware addresses).
> > + * For VF this equals @start (drm_mm uses relative addresses from VF base).
> > + * Updated atomically by xe_ggtt_shift_nodes() during VF recovery.
> > + */
> > + u64 mm_offset;
> > + /** @reserved_bottom: permanently reserved [0, WOPCM) drm_mm node for PF */
> > + struct drm_mm_node reserved_bottom;
> > + /** @reserved_top: permanently reserved [GUC_GGTT_TOP, total) drm_mm node for PF */
> > + struct drm_mm_node reserved_top;
>
> maybe all we need is to separate concepts of:
>
> * raw GGTT - fixed range [0, 4GB)
>
> from
>
> * allocable GGTT - configurable sub-range [start, end)
> * [wopcm, GUC_TOP) on PF
> * [base, base+size) on VF
>
> and then we can continue to use drm_mm.init(0, end-start) to manage
> that [start, end) range in a common way on both PF and VF?
we need to be able to use a ggtt buffer that comes out of this range,
so I'm afraid it doesn't solve all the cases.
>
>
> > /** @access_count: counts GGTT writes */
> > unsigned int access_count;
> > /** @wq: Dedicated unordered work queue to process node removals */
> > @@ -318,6 +329,10 @@ static void ggtt_fini_early(struct drm_device *drm, void *arg)
> > {
> > struct xe_ggtt *ggtt = arg;
> >
> > + if (drm_mm_node_allocated(&ggtt->reserved_top))
> > + drm_mm_remove_node(&ggtt->reserved_top);
> > + if (drm_mm_node_allocated(&ggtt->reserved_bottom))
> > + drm_mm_remove_node(&ggtt->reserved_bottom);
> > destroy_workqueue(ggtt->wq);
> > drm_mm_takedown(&ggtt->mm);
> > }
> > @@ -354,16 +369,66 @@ static const struct xe_ggtt_pt_ops xelpg_pt_wa_ops = {
> > .ggtt_get_pte = xe_ggtt_get_pte,
> > };
> >
> > -static void __xe_ggtt_init_early(struct xe_ggtt *ggtt, u64 start, u64 size)
> > +/*
> > + * __xe_ggtt_init_early - Generic drm_mm initialisation for both PF and VF.
> > + *
> > + * @start and @size define the usable GGTT range exposed through the public API.
> > + * @mm_offset is added to every drm_mm node address to obtain the hardware
> > + * address (0 for PF where the drm_mm spans real addresses; @start for VF).
> > + * @mm_size is the total span passed to drm_mm_init() (equals @size for VF;
> > + * equals the full hardware GGTT size for PF).
> > + */
> > +static void __xe_ggtt_init_early(struct xe_ggtt *ggtt, u64 start, u64 size,
> > + u64 mm_offset, u64 mm_size)
> > {
> > ggtt->start = start;
> > ggtt->size = size;
> > - drm_mm_init(&ggtt->mm, 0, size);
> > + ggtt->mm_offset = mm_offset;
> > + drm_mm_init(&ggtt->mm, 0, mm_size);
> > +}
> > +
> > +/*
> > + * __xe_ggtt_reserve_pf_nodes - Permanently reserve the forbidden GGTT zones.
> > + *
> > + * Must be called after __xe_ggtt_init_early() for the PF case. Reserves
> > + * [0, @wopcm) and [@guc_top, @total_size) so the allocator never hands them
> > + * out. On failure the drm_mm is torn down and the error is returned.
> > + */
> > +static int __xe_ggtt_reserve_pf_nodes(struct xe_ggtt *ggtt, u64 wopcm,
> > + u64 guc_top, u64 total_size)
> > +{
> > + int err;
> > +
> > + /* Reserve [0, wopcm) — GuC cannot access below WOPCM */
> > + if (wopcm > 0) {
> > + ggtt->reserved_bottom.start = 0;
> > + ggtt->reserved_bottom.size = wopcm;
> > + err = drm_mm_reserve_node(&ggtt->mm, &ggtt->reserved_bottom);
> > + if (WARN_ON(err))
> > + goto err_takedown;
> > + }
> > +
> > + /* Reserve [guc_top, total_size) — GuC cannot access above GUC_GGTT_TOP */
> > + if (guc_top < total_size) {
> > + ggtt->reserved_top.start = guc_top;
> > + ggtt->reserved_top.size = total_size - guc_top;
> > + err = drm_mm_reserve_node(&ggtt->mm, &ggtt->reserved_top);
> > + if (WARN_ON(err))
> > + goto err_remove_bottom;
> > + }
> > +
> > + return 0;
> > +
> > +err_remove_bottom:
> > + drm_mm_remove_node(&ggtt->reserved_bottom);
> > +err_takedown:
> > + drm_mm_takedown(&ggtt->mm);
> > + return err;
> > }
> >
> > int xe_ggtt_init_kunit(struct xe_ggtt *ggtt, u32 start, u32 size)
> > {
> > - __xe_ggtt_init_early(ggtt, start, size);
> > + __xe_ggtt_init_early(ggtt, start, size, start, size);
> > return 0;
> > }
> > EXPORT_SYMBOL_IF_KUNIT(xe_ggtt_init_kunit);
> > @@ -405,8 +470,13 @@ int xe_ggtt_init_early(struct xe_ggtt *ggtt)
> > xe_tile_err(ggtt->tile, "Hardware reported no preallocated GSM\n");
> > return -ENOMEM;
> > }
> > + /*
> > + * For PF, ggtt_size holds the full hardware GGTT size. The
> > + * WOPCM and GUC_GGTT_TOP limits are enforced via permanently
> > + * reserved drm_mm nodes rather than by capping the range.
> > + */
> > ggtt_start = wopcm;
> > - ggtt_size = (gsm_size / 8) * (u64)XE_PAGE_SIZE - ggtt_start;
> > + ggtt_size = (gsm_size / 8) * (u64)XE_PAGE_SIZE;
> > } else {
> > ggtt_start = xe_tile_sriov_vf_ggtt_base(ggtt->tile);
> > ggtt_size = xe_tile_sriov_vf_ggtt(ggtt->tile);
> > @@ -423,9 +493,6 @@ int xe_ggtt_init_early(struct xe_ggtt *ggtt)
> > if (IS_DGFX(xe) && xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K)
> > ggtt->flags |= XE_GGTT_FLAGS_64K;
> >
> > - if (ggtt_size + ggtt_start > GUC_GGTT_TOP)
> > - ggtt_size = GUC_GGTT_TOP - ggtt_start;
> > -
> > if (GRAPHICS_VERx100(xe) >= 1270)
> > ggtt->pt_ops =
> > (ggtt->tile->media_gt && XE_GT_WA(ggtt->tile->media_gt, 22019338487)) ||
> > @@ -438,7 +505,19 @@ int xe_ggtt_init_early(struct xe_ggtt *ggtt)
> > if (!ggtt->wq)
> > return -ENOMEM;
> >
> > - __xe_ggtt_init_early(ggtt, ggtt_start, ggtt_size);
> > + if (!IS_SRIOV_VF(xe)) {
> > + __xe_ggtt_init_early(ggtt, ggtt_start, GUC_GGTT_TOP - ggtt_start,
> > + 0, ggtt_size);
> > + err = __xe_ggtt_reserve_pf_nodes(ggtt, ggtt_start, GUC_GGTT_TOP,
> > + ggtt_size);
> > + if (err) {
> > + destroy_workqueue(ggtt->wq);
> > + return err;
> > + }
> > + } else {
> > + __xe_ggtt_init_early(ggtt, ggtt_start, ggtt_size,
> > + ggtt_start, ggtt_size);
> > + }
> >
> > err = drmm_add_action_or_reset(&xe->drm, ggtt_fini_early, ggtt);
> > if (err)
> > @@ -459,7 +538,7 @@ static void xe_ggtt_initial_clear(struct xe_ggtt *ggtt)
> > /* Display may have allocated inside ggtt, so be careful with clearing here */
> > mutex_lock(&ggtt->lock);
> > drm_mm_for_each_hole(hole, &ggtt->mm, start, end)
> > - xe_ggtt_clear(ggtt, ggtt->start + start, end - start);
> > + xe_ggtt_clear(ggtt, ggtt->mm_offset + start, end - start);
> >
> > xe_ggtt_invalidate(ggtt);
> > mutex_unlock(&ggtt->lock);
> > @@ -613,6 +692,7 @@ void xe_ggtt_shift_nodes(struct xe_ggtt *ggtt, u64 new_start)
> >
> > /* pairs with READ_ONCE in xe_ggtt_node_addr() */
> > WRITE_ONCE(ggtt->start, new_start);
> > + WRITE_ONCE(ggtt->mm_offset, new_start);
> > }
> >
> > static int xe_ggtt_insert_node_locked(struct xe_ggtt_node *node,
> > @@ -815,20 +895,19 @@ static int __xe_ggtt_insert_bo_at(struct xe_ggtt *ggtt, struct xe_bo *bo,
> >
> > mutex_lock(&ggtt->lock);
> > /*
> > - * When inheriting the initial framebuffer, the framebuffer is
> > - * physically located at VRAM address 0, and usually at GGTT address 0 too.
> > - *
> > - * The display code will ask for a GGTT allocation between end of BO and
> > - * remainder of GGTT, unaware that the start is reserved by WOPCM.
> > + * Convert caller-supplied hardware GGTT addresses to drm_mm-relative
> > + * coordinates. For PF mm_offset is 0 so this is a no-op; callers pass
> > + * real addresses and the reserved_bottom/top nodes prevent allocations
> > + * in the forbidden regions. For VF, mm_offset equals the VF base so
> > + * we convert to relative drm_mm space.
> > */
> > - if (start >= ggtt->start)
> > - start -= ggtt->start;
> > + if (start >= ggtt->mm_offset)
> > + start -= ggtt->mm_offset;
> > else
> > start = 0;
> >
> > - /* Should never happen, but since we handle start, fail graciously for end */
> > - if (end >= ggtt->start)
> > - end -= ggtt->start;
> > + if (end >= ggtt->mm_offset)
> > + end -= ggtt->mm_offset;
> > else
> > end = 0;
> >
> > @@ -923,7 +1002,7 @@ u64 xe_ggtt_largest_hole(struct xe_ggtt *ggtt, u64 alignment, u64 *spare)
> >
> > mutex_lock(&ggtt->lock);
> > drm_mm_for_each_hole(entry, mm, hole_start, hole_end) {
> > - hole_start = max(hole_start, ggtt->start);
> > + hole_start = max(hole_start, ggtt->mm_offset);
> > hole_start = ALIGN(hole_start, alignment);
> > hole_end = ALIGN_DOWN(hole_end, alignment);
> > if (hole_start >= hole_end)
> > @@ -1098,7 +1177,7 @@ u64 xe_ggtt_print_holes(struct xe_ggtt *ggtt, u64 alignment, struct drm_printer
> >
> > mutex_lock(&ggtt->lock);
> > drm_mm_for_each_hole(entry, mm, hole_start, hole_end) {
> > - hole_start = max(hole_start, ggtt->start);
> > + hole_start = max(hole_start, ggtt->mm_offset);
> > hole_start = ALIGN(hole_start, alignment);
> > hole_end = ALIGN_DOWN(hole_end, alignment);
> > if (hole_start >= hole_end)
> > @@ -1152,7 +1231,7 @@ u64 xe_ggtt_read_pte(struct xe_ggtt *ggtt, u64 offset)
> > u64 xe_ggtt_node_addr(const struct xe_ggtt_node *node)
> > {
> > /* pairs with WRITE_ONCE in xe_ggtt_shift_nodes() */
> > - return node->base.start + READ_ONCE(node->ggtt->start);
> > + return node->base.start + READ_ONCE(node->ggtt->mm_offset);
> > }
> >
> > /**
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/xe/ggtt: use full-range drm_mm with reserved nodes on PF
2026-05-28 22:28 ` Rodrigo Vivi
@ 2026-05-29 10:50 ` Ville Syrjälä
2026-05-29 21:03 ` Rodrigo Vivi
0 siblings, 1 reply; 13+ messages in thread
From: Ville Syrjälä @ 2026-05-29 10:50 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: Michal Wajdeczko, intel-gfx, intel-xe, Maarten Lankhorst
On Thu, May 28, 2026 at 06:28:47PM -0400, Rodrigo Vivi wrote:
> On Fri, May 29, 2026 at 12:11:22AM +0200, Michal Wajdeczko wrote:
> >
> >
> > On 5/27/2026 4:45 PM, Rodrigo Vivi wrote:
> > > The PF GGTT allocator was initialised over a relative [0, usable_size)
> > > range, with ggtt->start added on every address conversion to get the
> > > actual hardware address. Two consequences of that model were considered
> > > "horrible hacks":
> > >
> > > - ggtt->start (the WOPCM offset) had to be carried around and added
> > > to every drm_mm result.
> >
> > hmm, but this an internal detail of the xe_ggtt implementation, so why
> > would someone else complain about it?
> >
> > > - The GUC_GGTT_TOP ceiling silently truncated the GGTT range instead
> >
> > hmm, for the record, this GGTT cap on the top was added back in 2023
> >
> > commit ab10e976fbda8349163ceee2ce99b2bfc97031b8
> > Author: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > Date: Wed Jun 14 10:47:54 2023 -0700
> >
> > drm/xe: limit GGTT size to GUC_GGTT_TOP
> >
> > + * The GuC address space is limited on both ends of the GGTT, because
> > + * the GuC shim HW redirects accesses to those addresses to other HW
> > + * areas instead of going through the GGTT. On the bottom end, the GuC
> > + * can't access offsets below the WOPCM size, while on the top side the
> > + * limit is fixed at GUC_GGTT_TOP. To keep things simple, instead of
> > + * checking each object to see if they are accessed by GuC or not, we
> > + * just exclude those areas from the allocator. Additionally, to
> > + * simplify the driver load, we use the maximum WOPCM size in this logic
> >
> > > of being made explicit, leaving PTEs in [GUC_GGTT_TOP, total_size)
> > > untouched during the initial clear.
> >
> > and that likely will not be changed by this patch as after allocating 'two
> > permanent zones', the drm_mm_for_each_hole will not iterate over them
>
> right...
>
> >
> > >
> > > Fix this for the PF case by initialising drm_mm over the full hardware
> > > GGTT range [0, total_size) and permanently reserving the two forbidden
> > > zones:
> > >
> > > - [0, wopcm) — inaccessible below WOPCM
> > > - [GUC_GGTT_TOP, total_size) — inaccessible above GUC_GGTT_TOP
> >
> > that looks odds: why pretend to claim manageability of full [0, 4GB)
> > of the GGTT and then immediately permanently reserve two end zones to
> > end up with real [wopcm, GUC_TOP) which is what we already have?
>
> yes...
>
> >
> > >
> > > A new mm_offset field (zero for PF) carries the base offset used in
> > > address conversions, unifying the existing VF relative model (where
> > > mm_offset == vf_base) with the new PF absolute model.
> >
> > but public xe_ggtt API already uses absolute addressing in PF and VF
>
> I know...
>
> >
> > > The public
> > > xe_ggtt_start() / xe_ggtt_size() API continues to return the usable
> > > [wopcm, GUC_GGTT_TOP) boundaries, so callers such as the SR-IOV PF
> > > config code are unaffected.
> > >
> > > xe_ggtt_shift_nodes() now updates both ggtt->start and ggtt->mm_offset
> > > so the VF recovery path remains a single O(1) WRITE_ONCE pair.
> >
> > maybe it's just me - but I can't figure out the real rationale for this
> > patch - what did I miss?
>
> This series:
> https://lore.kernel.org/intel-xe/20260511214122.8468-1-ville.syrjala@linux.intel.com/
>
> And more specifically the discussion in this patch:
> https://lore.kernel.org/intel-xe/20260511214122.8468-13-ville.syrjala@linux.intel.com/
>
> >
> > >
> > > Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > Assisted-by: GitHub-Copilot:claude-sonnet-4.6
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > > drivers/gpu/drm/xe/xe_ggtt.c | 123 ++++++++++++++++++++++++++++-------
> > > 1 file changed, 101 insertions(+), 22 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> > > index a351c578b170..00a6cd2b8a51 100644
> > > --- a/drivers/gpu/drm/xe/xe_ggtt.c
> > > +++ b/drivers/gpu/drm/xe/xe_ggtt.c
> > > @@ -137,6 +137,17 @@ struct xe_ggtt {
> > > const struct xe_ggtt_pt_ops *pt_ops;
> > > /** @mm: The memory manager used to manage individual GGTT allocations */
> > > struct drm_mm mm;
> > > + /**
> > > + * @mm_offset: base offset added to drm_mm node addresses to obtain hardware
> > > + * GGTT addresses. For PF this is 0 (drm_mm uses absolute hardware addresses).
> > > + * For VF this equals @start (drm_mm uses relative addresses from VF base).
> > > + * Updated atomically by xe_ggtt_shift_nodes() during VF recovery.
> > > + */
> > > + u64 mm_offset;
> > > + /** @reserved_bottom: permanently reserved [0, WOPCM) drm_mm node for PF */
> > > + struct drm_mm_node reserved_bottom;
> > > + /** @reserved_top: permanently reserved [GUC_GGTT_TOP, total) drm_mm node for PF */
> > > + struct drm_mm_node reserved_top;
> >
> > maybe all we need is to separate concepts of:
> >
> > * raw GGTT - fixed range [0, 4GB)
> >
> > from
> >
> > * allocable GGTT - configurable sub-range [start, end)
> > * [wopcm, GUC_TOP) on PF
> > * [base, base+size) on VF
> >
> > and then we can continue to use drm_mm.init(0, end-start) to manage
> > that [start, end) range in a common way on both PF and VF?
>
> we need to be able to use a ggtt buffer that comes out of this range,
> so I'm afraid it doesn't solve all the cases.
Basically what the display needs is:
1. specify where in ggtt the buffer was originally placed by the GOP,
this may be partially or fully inside these GuC reserved ranges
2. bind the buffer to some acceptable location (assuming the original
location wasn't acceptable) without overwriting the PTEs for the
original location
I suppose this could be achieved even with this "mm doesn't cover the
ends" hack, but step 1 there becomes a bit dodgy because we can't
insert the mm node if it's fully outside the mm. I suppose it could
still work if you hide it in a function that only validates the real
ggtt offsets, but then ignores the fact that the node can't be
inserted due to being fully inside those reserved ranges. And then
whatever cleans up that original mm node must also ignore the fact
that the node maybe wasn't even allocated. And also
xe_ggtt_initial_clear() will need special code to clear the
reserved ranges.
My original idea was that we'd just include the reserved regions
in the mm, and then the display could just keep the buffer at its
original location, and later the guc code can reserve what is
left over. So we could skip step 2 above completely. But after
a second thought we probably don't want to skip that step because
we might free the display bo later, at which point we might free
up some of the reserved ranges. So I guess we'd still want to keep
step 2. But I think it'd still result in less special cases in the
code. We'd just need the guc code to reserve what it needs, after
the display code has rebound the bo to an acceptable location.
So we'd end up with:
1. insert node for the bo's original ggtt location
2. rebind the display bo to an acceptable ggtt location
3. undo step 1
4. xe_ggtt_initial_clear() (now also clears the reserved ranges
without any special code)
5. guc steals the reserved ranges explicitly
So only two special cases left really, and all the rest
of the code is blissfully unaware of any of it.
Hmm, although hibernation might still be a slight issue for
xe_ggtt_initial_clear(). As in how would the reserved regions
get cleared during resume from hibernation? I have no idea
how the current xe ggtt code handles resume at all...
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/xe/ggtt: use full-range drm_mm with reserved nodes on PF
2026-05-29 10:50 ` Ville Syrjälä
@ 2026-05-29 21:03 ` Rodrigo Vivi
2026-06-03 13:19 ` Ville Syrjälä
0 siblings, 1 reply; 13+ messages in thread
From: Rodrigo Vivi @ 2026-05-29 21:03 UTC (permalink / raw)
To: Ville Syrjälä
Cc: Michal Wajdeczko, intel-gfx, intel-xe, Maarten Lankhorst
On Fri, May 29, 2026 at 01:50:34PM +0300, Ville Syrjälä wrote:
> On Thu, May 28, 2026 at 06:28:47PM -0400, Rodrigo Vivi wrote:
> > On Fri, May 29, 2026 at 12:11:22AM +0200, Michal Wajdeczko wrote:
> > >
> > >
> > > On 5/27/2026 4:45 PM, Rodrigo Vivi wrote:
> > > > The PF GGTT allocator was initialised over a relative [0, usable_size)
> > > > range, with ggtt->start added on every address conversion to get the
> > > > actual hardware address. Two consequences of that model were considered
> > > > "horrible hacks":
> > > >
> > > > - ggtt->start (the WOPCM offset) had to be carried around and added
> > > > to every drm_mm result.
> > >
> > > hmm, but this an internal detail of the xe_ggtt implementation, so why
> > > would someone else complain about it?
> > >
> > > > - The GUC_GGTT_TOP ceiling silently truncated the GGTT range instead
> > >
> > > hmm, for the record, this GGTT cap on the top was added back in 2023
> > >
> > > commit ab10e976fbda8349163ceee2ce99b2bfc97031b8
> > > Author: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > > Date: Wed Jun 14 10:47:54 2023 -0700
> > >
> > > drm/xe: limit GGTT size to GUC_GGTT_TOP
> > >
> > > + * The GuC address space is limited on both ends of the GGTT, because
> > > + * the GuC shim HW redirects accesses to those addresses to other HW
> > > + * areas instead of going through the GGTT. On the bottom end, the GuC
> > > + * can't access offsets below the WOPCM size, while on the top side the
> > > + * limit is fixed at GUC_GGTT_TOP. To keep things simple, instead of
> > > + * checking each object to see if they are accessed by GuC or not, we
> > > + * just exclude those areas from the allocator. Additionally, to
> > > + * simplify the driver load, we use the maximum WOPCM size in this logic
> > >
> > > > of being made explicit, leaving PTEs in [GUC_GGTT_TOP, total_size)
> > > > untouched during the initial clear.
> > >
> > > and that likely will not be changed by this patch as after allocating 'two
> > > permanent zones', the drm_mm_for_each_hole will not iterate over them
> >
> > right...
> >
> > >
> > > >
> > > > Fix this for the PF case by initialising drm_mm over the full hardware
> > > > GGTT range [0, total_size) and permanently reserving the two forbidden
> > > > zones:
> > > >
> > > > - [0, wopcm) — inaccessible below WOPCM
> > > > - [GUC_GGTT_TOP, total_size) — inaccessible above GUC_GGTT_TOP
> > >
> > > that looks odds: why pretend to claim manageability of full [0, 4GB)
> > > of the GGTT and then immediately permanently reserve two end zones to
> > > end up with real [wopcm, GUC_TOP) which is what we already have?
> >
> > yes...
> >
> > >
> > > >
> > > > A new mm_offset field (zero for PF) carries the base offset used in
> > > > address conversions, unifying the existing VF relative model (where
> > > > mm_offset == vf_base) with the new PF absolute model.
> > >
> > > but public xe_ggtt API already uses absolute addressing in PF and VF
> >
> > I know...
> >
> > >
> > > > The public
> > > > xe_ggtt_start() / xe_ggtt_size() API continues to return the usable
> > > > [wopcm, GUC_GGTT_TOP) boundaries, so callers such as the SR-IOV PF
> > > > config code are unaffected.
> > > >
> > > > xe_ggtt_shift_nodes() now updates both ggtt->start and ggtt->mm_offset
> > > > so the VF recovery path remains a single O(1) WRITE_ONCE pair.
> > >
> > > maybe it's just me - but I can't figure out the real rationale for this
> > > patch - what did I miss?
> >
> > This series:
> > https://lore.kernel.org/intel-xe/20260511214122.8468-1-ville.syrjala@linux.intel.com/
> >
> > And more specifically the discussion in this patch:
> > https://lore.kernel.org/intel-xe/20260511214122.8468-13-ville.syrjala@linux.intel.com/
> >
> > >
> > > >
> > > > Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > Assisted-by: GitHub-Copilot:claude-sonnet-4.6
> > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > ---
> > > > drivers/gpu/drm/xe/xe_ggtt.c | 123 ++++++++++++++++++++++++++++-------
> > > > 1 file changed, 101 insertions(+), 22 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> > > > index a351c578b170..00a6cd2b8a51 100644
> > > > --- a/drivers/gpu/drm/xe/xe_ggtt.c
> > > > +++ b/drivers/gpu/drm/xe/xe_ggtt.c
> > > > @@ -137,6 +137,17 @@ struct xe_ggtt {
> > > > const struct xe_ggtt_pt_ops *pt_ops;
> > > > /** @mm: The memory manager used to manage individual GGTT allocations */
> > > > struct drm_mm mm;
> > > > + /**
> > > > + * @mm_offset: base offset added to drm_mm node addresses to obtain hardware
> > > > + * GGTT addresses. For PF this is 0 (drm_mm uses absolute hardware addresses).
> > > > + * For VF this equals @start (drm_mm uses relative addresses from VF base).
> > > > + * Updated atomically by xe_ggtt_shift_nodes() during VF recovery.
> > > > + */
> > > > + u64 mm_offset;
> > > > + /** @reserved_bottom: permanently reserved [0, WOPCM) drm_mm node for PF */
> > > > + struct drm_mm_node reserved_bottom;
> > > > + /** @reserved_top: permanently reserved [GUC_GGTT_TOP, total) drm_mm node for PF */
> > > > + struct drm_mm_node reserved_top;
> > >
> > > maybe all we need is to separate concepts of:
> > >
> > > * raw GGTT - fixed range [0, 4GB)
> > >
> > > from
> > >
> > > * allocable GGTT - configurable sub-range [start, end)
> > > * [wopcm, GUC_TOP) on PF
> > > * [base, base+size) on VF
> > >
> > > and then we can continue to use drm_mm.init(0, end-start) to manage
> > > that [start, end) range in a common way on both PF and VF?
> >
> > we need to be able to use a ggtt buffer that comes out of this range,
> > so I'm afraid it doesn't solve all the cases.
>
> Basically what the display needs is:
> 1. specify where in ggtt the buffer was originally placed by the GOP,
> this may be partially or fully inside these GuC reserved ranges
> 2. bind the buffer to some acceptable location (assuming the original
> location wasn't acceptable) without overwriting the PTEs for the
> original location
>
> I suppose this could be achieved even with this "mm doesn't cover the
> ends" hack, but step 1 there becomes a bit dodgy because we can't
> insert the mm node if it's fully outside the mm. I suppose it could
> still work if you hide it in a function that only validates the real
> ggtt offsets, but then ignores the fact that the node can't be
> inserted due to being fully inside those reserved ranges. And then
> whatever cleans up that original mm node must also ignore the fact
> that the node maybe wasn't even allocated. And also
> xe_ggtt_initial_clear() will need special code to clear the
> reserved ranges.
right, so basically we could keep the xe_ggtt as is and provide
2 hooks:
1. one to reserve the portion of the BIOS FB that goes
inside our managed ggtt area
2. a special clear for this area
And in between you do the rebind with existing infrastructure
to an empty region?! Is this what you are thinking now?
>
> My original idea was that we'd just include the reserved regions
> in the mm, and then the display could just keep the buffer at its
> original location, and later the guc code can reserve what is
> left over. So we could skip step 2 above completely. But after
> a second thought we probably don't want to skip that step because
> we might free the display bo later, at which point we might free
> up some of the reserved ranges. So I guess we'd still want to keep
> step 2. But I think it'd still result in less special cases in the
> code. We'd just need the guc code to reserve what it needs, after
> the display code has rebound the bo to an acceptable location.
>
> So we'd end up with:
> 1. insert node for the bo's original ggtt location
> 2. rebind the display bo to an acceptable ggtt location
> 3. undo step 1
> 4. xe_ggtt_initial_clear() (now also clears the reserved ranges
> without any special code)
> 5. guc steals the reserved ranges explicitly
>
> So only two special cases left really, and all the rest
> of the code is blissfully unaware of any of it.
>
> Hmm, although hibernation might still be a slight issue for
> xe_ggtt_initial_clear(). As in how would the reserved regions
> get cleared during resume from hibernation? I have no idea
> how the current xe ggtt code handles resume at all...
The resume should only restore the pinned bo's one by one, nothing
special. So I guess if we keep the original code we are okay,
but if we start to managing the full range with the reserved areas
we might have some difficulties here on the way...
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH] drm/xe/ggtt: clear reserved area at GUC_GGTT_TOP.
2026-05-27 14:45 [PATCH] drm/xe/ggtt: use full-range drm_mm with reserved nodes on PF Rodrigo Vivi
` (3 preceding siblings ...)
2026-05-28 22:11 ` [PATCH] " Michal Wajdeczko
@ 2026-06-03 12:57 ` Maarten Lankhorst
2026-06-03 13:11 ` Ville Syrjälä
4 siblings, 1 reply; 13+ messages in thread
From: Maarten Lankhorst @ 2026-06-03 12:57 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx, intel-xe
Cc: Ville Syrjälä, Michal Wajdeczko
Hello,
On 5/27/26 16:45, Rodrigo Vivi wrote:
> The PF GGTT allocator was initialised over a relative [0, usable_size)
> range, with ggtt->start added on every address conversion to get the
> actual hardware address. Two consequences of that model were considered
> "horrible hacks":
>
> - ggtt->start (the WOPCM offset) had to be carried around and added
> to every drm_mm result.
This is still the case, only we add a separate variable now that is usually 0.
We always have to ensure that this is correctly accounted
for, otherwise we get subtle bugs, so there's no reason not to use it,
if it's already used everywhere.
Whether it's 0 or wopcm_start doesn't change the result.
> - The GUC_GGTT_TOP ceiling silently truncated the GGTT range instead
> of being made explicit, leaving PTEs in [GUC_GGTT_TOP, total_size)
> untouched during the initial clear.
This is a valid concern, but it's very easily be fixed inside the initial clear
by calling xe_ggtt_clear once more with a comment for !VF case.
Something like below is enough to fix it. Adding a reserved region at the end/start
is not the way to do so and just adds more complications.
---8<---
When initialising GGTT, we never clear the part above GUC_GGTT_TOP.
Add a member to &xe_ggtt that holds the full GGTT size, and clear it
during the pass at xe_ggtt_initial_clear.
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 8ec23862477fc..497b99a932f0d 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -115,6 +115,8 @@ struct xe_ggtt {
u64 start;
/** @size: Total usable size of this GGTT */
u64 size;
+ /** @entire_size: complete size of the accessible GGTT, reserved regions inclusive */
+ u64 entire_size;
/**
* @flags: Flags for this GGTT.
* Acceptable flags:
@@ -406,7 +408,8 @@ int xe_ggtt_init_early(struct xe_ggtt *ggtt)
return -ENOMEM;
}
ggtt_start = wopcm;
- ggtt_size = (gsm_size / 8) * (u64)XE_PAGE_SIZE - ggtt_start;
+ ggtt->entire_size = (gsm_size / 8) * (u64)XE_PAGE_SIZE;
+ ggtt_size = ggtt->entire_size - ggtt_start;
} else {
ggtt_start = xe_tile_sriov_vf_ggtt_base(ggtt->tile);
ggtt_size = xe_tile_sriov_vf_ggtt(ggtt->tile);
@@ -417,6 +420,7 @@ int xe_ggtt_init_early(struct xe_ggtt *ggtt)
ggtt_start, ggtt_start + ggtt_size - 1);
return -ERANGE;
}
+ ggtt->entire_size = ggtt_size;
}
ggtt->gsm = ggtt->tile->mmio.regs + SZ_8M;
@@ -461,6 +465,10 @@ static void xe_ggtt_initial_clear(struct xe_ggtt *ggtt)
drm_mm_for_each_hole(hole, &ggtt->mm, start, end)
xe_ggtt_clear(ggtt, ggtt->start + start, end - start);
+ end = ggtt->start + ggtt->size;
+ if (ggtt->entire_size > end)
+ xe_ggtt_clear(ggtt, end, ggtt->entire_size - end);
+
xe_ggtt_invalidate(ggtt);
mutex_unlock(&ggtt->lock);
}
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/xe/ggtt: clear reserved area at GUC_GGTT_TOP.
2026-06-03 12:57 ` [PATCH] drm/xe/ggtt: clear reserved area at GUC_GGTT_TOP Maarten Lankhorst
@ 2026-06-03 13:11 ` Ville Syrjälä
0 siblings, 0 replies; 13+ messages in thread
From: Ville Syrjälä @ 2026-06-03 13:11 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: Rodrigo Vivi, intel-gfx, intel-xe, Michal Wajdeczko
On Wed, Jun 03, 2026 at 02:57:48PM +0200, Maarten Lankhorst wrote:
> Hello,
>
> On 5/27/26 16:45, Rodrigo Vivi wrote:
> > The PF GGTT allocator was initialised over a relative [0, usable_size)
> > range, with ggtt->start added on every address conversion to get the
> > actual hardware address. Two consequences of that model were considered
> > "horrible hacks":
> >
> > - ggtt->start (the WOPCM offset) had to be carried around and added
> > to every drm_mm result.
> This is still the case, only we add a separate variable now that is usually 0.
> We always have to ensure that this is correctly accounted
> for, otherwise we get subtle bugs, so there's no reason not to use it,
> if it's already used everywhere.
>
> Whether it's 0 or wopcm_start doesn't change the result.
>
> > - The GUC_GGTT_TOP ceiling silently truncated the GGTT range instead
> > of being made explicit, leaving PTEs in [GUC_GGTT_TOP, total_size)
> > untouched during the initial clear.
> This is a valid concern, but it's very easily be fixed inside the initial clear
> by calling xe_ggtt_clear once more with a comment for !VF case.
>
> Something like below is enough to fix it. Adding a reserved region at the end/start
> is not the way to do so and just adds more complications.
> ---8<---
> When initialising GGTT, we never clear the part above GUC_GGTT_TOP.
> Add a member to &xe_ggtt that holds the full GGTT size, and clear it
> during the pass at xe_ggtt_initial_clear.
>
> Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
> ---
> diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> index 8ec23862477fc..497b99a932f0d 100644
> --- a/drivers/gpu/drm/xe/xe_ggtt.c
> +++ b/drivers/gpu/drm/xe/xe_ggtt.c
> @@ -115,6 +115,8 @@ struct xe_ggtt {
> u64 start;
> /** @size: Total usable size of this GGTT */
> u64 size;
> + /** @entire_size: complete size of the accessible GGTT, reserved regions inclusive */
> + u64 entire_size;
> /**
> * @flags: Flags for this GGTT.
> * Acceptable flags:
> @@ -406,7 +408,8 @@ int xe_ggtt_init_early(struct xe_ggtt *ggtt)
> return -ENOMEM;
> }
> ggtt_start = wopcm;
> - ggtt_size = (gsm_size / 8) * (u64)XE_PAGE_SIZE - ggtt_start;
> + ggtt->entire_size = (gsm_size / 8) * (u64)XE_PAGE_SIZE;
> + ggtt_size = ggtt->entire_size - ggtt_start;
> } else {
> ggtt_start = xe_tile_sriov_vf_ggtt_base(ggtt->tile);
> ggtt_size = xe_tile_sriov_vf_ggtt(ggtt->tile);
> @@ -417,6 +420,7 @@ int xe_ggtt_init_early(struct xe_ggtt *ggtt)
> ggtt_start, ggtt_start + ggtt_size - 1);
> return -ERANGE;
> }
> + ggtt->entire_size = ggtt_size;
> }
>
> ggtt->gsm = ggtt->tile->mmio.regs + SZ_8M;
> @@ -461,6 +465,10 @@ static void xe_ggtt_initial_clear(struct xe_ggtt *ggtt)
> drm_mm_for_each_hole(hole, &ggtt->mm, start, end)
> xe_ggtt_clear(ggtt, ggtt->start + start, end - start);
>
> + end = ggtt->start + ggtt->size;
> + if (ggtt->entire_size > end)
> + xe_ggtt_clear(ggtt, end, ggtt->entire_size - end);
You'll need the same thing for the 0 to ggtt->start range.
> +
> xe_ggtt_invalidate(ggtt);
> mutex_unlock(&ggtt->lock);
> }
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/xe/ggtt: use full-range drm_mm with reserved nodes on PF
2026-05-29 21:03 ` Rodrigo Vivi
@ 2026-06-03 13:19 ` Ville Syrjälä
2026-06-03 13:44 ` Rodrigo Vivi
0 siblings, 1 reply; 13+ messages in thread
From: Ville Syrjälä @ 2026-06-03 13:19 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: Michal Wajdeczko, intel-gfx, intel-xe, Maarten Lankhorst
On Fri, May 29, 2026 at 05:03:55PM -0400, Rodrigo Vivi wrote:
> On Fri, May 29, 2026 at 01:50:34PM +0300, Ville Syrjälä wrote:
> > On Thu, May 28, 2026 at 06:28:47PM -0400, Rodrigo Vivi wrote:
> > > On Fri, May 29, 2026 at 12:11:22AM +0200, Michal Wajdeczko wrote:
> > > >
> > > >
> > > > On 5/27/2026 4:45 PM, Rodrigo Vivi wrote:
> > > > > The PF GGTT allocator was initialised over a relative [0, usable_size)
> > > > > range, with ggtt->start added on every address conversion to get the
> > > > > actual hardware address. Two consequences of that model were considered
> > > > > "horrible hacks":
> > > > >
> > > > > - ggtt->start (the WOPCM offset) had to be carried around and added
> > > > > to every drm_mm result.
> > > >
> > > > hmm, but this an internal detail of the xe_ggtt implementation, so why
> > > > would someone else complain about it?
> > > >
> > > > > - The GUC_GGTT_TOP ceiling silently truncated the GGTT range instead
> > > >
> > > > hmm, for the record, this GGTT cap on the top was added back in 2023
> > > >
> > > > commit ab10e976fbda8349163ceee2ce99b2bfc97031b8
> > > > Author: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > > > Date: Wed Jun 14 10:47:54 2023 -0700
> > > >
> > > > drm/xe: limit GGTT size to GUC_GGTT_TOP
> > > >
> > > > + * The GuC address space is limited on both ends of the GGTT, because
> > > > + * the GuC shim HW redirects accesses to those addresses to other HW
> > > > + * areas instead of going through the GGTT. On the bottom end, the GuC
> > > > + * can't access offsets below the WOPCM size, while on the top side the
> > > > + * limit is fixed at GUC_GGTT_TOP. To keep things simple, instead of
> > > > + * checking each object to see if they are accessed by GuC or not, we
> > > > + * just exclude those areas from the allocator. Additionally, to
> > > > + * simplify the driver load, we use the maximum WOPCM size in this logic
> > > >
> > > > > of being made explicit, leaving PTEs in [GUC_GGTT_TOP, total_size)
> > > > > untouched during the initial clear.
> > > >
> > > > and that likely will not be changed by this patch as after allocating 'two
> > > > permanent zones', the drm_mm_for_each_hole will not iterate over them
> > >
> > > right...
> > >
> > > >
> > > > >
> > > > > Fix this for the PF case by initialising drm_mm over the full hardware
> > > > > GGTT range [0, total_size) and permanently reserving the two forbidden
> > > > > zones:
> > > > >
> > > > > - [0, wopcm) — inaccessible below WOPCM
> > > > > - [GUC_GGTT_TOP, total_size) — inaccessible above GUC_GGTT_TOP
> > > >
> > > > that looks odds: why pretend to claim manageability of full [0, 4GB)
> > > > of the GGTT and then immediately permanently reserve two end zones to
> > > > end up with real [wopcm, GUC_TOP) which is what we already have?
> > >
> > > yes...
> > >
> > > >
> > > > >
> > > > > A new mm_offset field (zero for PF) carries the base offset used in
> > > > > address conversions, unifying the existing VF relative model (where
> > > > > mm_offset == vf_base) with the new PF absolute model.
> > > >
> > > > but public xe_ggtt API already uses absolute addressing in PF and VF
> > >
> > > I know...
> > >
> > > >
> > > > > The public
> > > > > xe_ggtt_start() / xe_ggtt_size() API continues to return the usable
> > > > > [wopcm, GUC_GGTT_TOP) boundaries, so callers such as the SR-IOV PF
> > > > > config code are unaffected.
> > > > >
> > > > > xe_ggtt_shift_nodes() now updates both ggtt->start and ggtt->mm_offset
> > > > > so the VF recovery path remains a single O(1) WRITE_ONCE pair.
> > > >
> > > > maybe it's just me - but I can't figure out the real rationale for this
> > > > patch - what did I miss?
> > >
> > > This series:
> > > https://lore.kernel.org/intel-xe/20260511214122.8468-1-ville.syrjala@linux.intel.com/
> > >
> > > And more specifically the discussion in this patch:
> > > https://lore.kernel.org/intel-xe/20260511214122.8468-13-ville.syrjala@linux.intel.com/
> > >
> > > >
> > > > >
> > > > > Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> > > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > > Assisted-by: GitHub-Copilot:claude-sonnet-4.6
> > > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/xe/xe_ggtt.c | 123 ++++++++++++++++++++++++++++-------
> > > > > 1 file changed, 101 insertions(+), 22 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> > > > > index a351c578b170..00a6cd2b8a51 100644
> > > > > --- a/drivers/gpu/drm/xe/xe_ggtt.c
> > > > > +++ b/drivers/gpu/drm/xe/xe_ggtt.c
> > > > > @@ -137,6 +137,17 @@ struct xe_ggtt {
> > > > > const struct xe_ggtt_pt_ops *pt_ops;
> > > > > /** @mm: The memory manager used to manage individual GGTT allocations */
> > > > > struct drm_mm mm;
> > > > > + /**
> > > > > + * @mm_offset: base offset added to drm_mm node addresses to obtain hardware
> > > > > + * GGTT addresses. For PF this is 0 (drm_mm uses absolute hardware addresses).
> > > > > + * For VF this equals @start (drm_mm uses relative addresses from VF base).
> > > > > + * Updated atomically by xe_ggtt_shift_nodes() during VF recovery.
> > > > > + */
> > > > > + u64 mm_offset;
> > > > > + /** @reserved_bottom: permanently reserved [0, WOPCM) drm_mm node for PF */
> > > > > + struct drm_mm_node reserved_bottom;
> > > > > + /** @reserved_top: permanently reserved [GUC_GGTT_TOP, total) drm_mm node for PF */
> > > > > + struct drm_mm_node reserved_top;
> > > >
> > > > maybe all we need is to separate concepts of:
> > > >
> > > > * raw GGTT - fixed range [0, 4GB)
> > > >
> > > > from
> > > >
> > > > * allocable GGTT - configurable sub-range [start, end)
> > > > * [wopcm, GUC_TOP) on PF
> > > > * [base, base+size) on VF
> > > >
> > > > and then we can continue to use drm_mm.init(0, end-start) to manage
> > > > that [start, end) range in a common way on both PF and VF?
> > >
> > > we need to be able to use a ggtt buffer that comes out of this range,
> > > so I'm afraid it doesn't solve all the cases.
> >
> > Basically what the display needs is:
> > 1. specify where in ggtt the buffer was originally placed by the GOP,
> > this may be partially or fully inside these GuC reserved ranges
> > 2. bind the buffer to some acceptable location (assuming the original
> > location wasn't acceptable) without overwriting the PTEs for the
> > original location
> >
> > I suppose this could be achieved even with this "mm doesn't cover the
> > ends" hack, but step 1 there becomes a bit dodgy because we can't
> > insert the mm node if it's fully outside the mm. I suppose it could
> > still work if you hide it in a function that only validates the real
> > ggtt offsets, but then ignores the fact that the node can't be
> > inserted due to being fully inside those reserved ranges. And then
> > whatever cleans up that original mm node must also ignore the fact
> > that the node maybe wasn't even allocated. And also
> > xe_ggtt_initial_clear() will need special code to clear the
> > reserved ranges.
>
> right, so basically we could keep the xe_ggtt as is and provide
> 2 hooks:
>
> 1. one to reserve the portion of the BIOS FB that goes
> inside our managed ggtt area
> 2. a special clear for this area
>
> And in between you do the rebind with existing infrastructure
> to an empty region?! Is this what you are thinking now?
>
> >
> > My original idea was that we'd just include the reserved regions
> > in the mm, and then the display could just keep the buffer at its
> > original location, and later the guc code can reserve what is
> > left over. So we could skip step 2 above completely. But after
> > a second thought we probably don't want to skip that step because
> > we might free the display bo later, at which point we might free
> > up some of the reserved ranges. So I guess we'd still want to keep
> > step 2. But I think it'd still result in less special cases in the
> > code. We'd just need the guc code to reserve what it needs, after
> > the display code has rebound the bo to an acceptable location.
> >
> > So we'd end up with:
> > 1. insert node for the bo's original ggtt location
> > 2. rebind the display bo to an acceptable ggtt location
> > 3. undo step 1
> > 4. xe_ggtt_initial_clear() (now also clears the reserved ranges
> > without any special code)
> > 5. guc steals the reserved ranges explicitly
> >
> > So only two special cases left really, and all the rest
> > of the code is blissfully unaware of any of it.
> >
> > Hmm, although hibernation might still be a slight issue for
> > xe_ggtt_initial_clear(). As in how would the reserved regions
> > get cleared during resume from hibernation? I have no idea
> > how the current xe ggtt code handles resume at all...
>
> The resume should only restore the pinned bo's one by one, nothing
> special.
Looks like currently xe_ggtt_initial_clear() is never even called
during resume from hibernation, so in that case parts of the GGTT
will be left with whatever garbage the GOP put there. So that's
one thing that needs fixing.
> So I guess if we keep the original code we are okay,
> but if we start to managing the full range with the reserved areas
> we might have some difficulties here on the way...
If we had a full range mm I suppose we'd need a bit of special code
to remove the reserved nodes before xe_ggtt_initial_clear() gets
called, at least for the resume from hibernation case.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/xe/ggtt: use full-range drm_mm with reserved nodes on PF
2026-06-03 13:19 ` Ville Syrjälä
@ 2026-06-03 13:44 ` Rodrigo Vivi
2026-06-03 14:54 ` Ville Syrjälä
0 siblings, 1 reply; 13+ messages in thread
From: Rodrigo Vivi @ 2026-06-03 13:44 UTC (permalink / raw)
To: Ville Syrjälä
Cc: Michal Wajdeczko, intel-gfx, intel-xe, Maarten Lankhorst
On Wed, Jun 03, 2026 at 04:19:41PM +0300, Ville Syrjälä wrote:
> On Fri, May 29, 2026 at 05:03:55PM -0400, Rodrigo Vivi wrote:
> > On Fri, May 29, 2026 at 01:50:34PM +0300, Ville Syrjälä wrote:
> > > On Thu, May 28, 2026 at 06:28:47PM -0400, Rodrigo Vivi wrote:
> > > > On Fri, May 29, 2026 at 12:11:22AM +0200, Michal Wajdeczko wrote:
> > > > >
> > > > >
> > > > > On 5/27/2026 4:45 PM, Rodrigo Vivi wrote:
> > > > > > The PF GGTT allocator was initialised over a relative [0, usable_size)
> > > > > > range, with ggtt->start added on every address conversion to get the
> > > > > > actual hardware address. Two consequences of that model were considered
> > > > > > "horrible hacks":
> > > > > >
> > > > > > - ggtt->start (the WOPCM offset) had to be carried around and added
> > > > > > to every drm_mm result.
> > > > >
> > > > > hmm, but this an internal detail of the xe_ggtt implementation, so why
> > > > > would someone else complain about it?
> > > > >
> > > > > > - The GUC_GGTT_TOP ceiling silently truncated the GGTT range instead
> > > > >
> > > > > hmm, for the record, this GGTT cap on the top was added back in 2023
> > > > >
> > > > > commit ab10e976fbda8349163ceee2ce99b2bfc97031b8
> > > > > Author: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > > > > Date: Wed Jun 14 10:47:54 2023 -0700
> > > > >
> > > > > drm/xe: limit GGTT size to GUC_GGTT_TOP
> > > > >
> > > > > + * The GuC address space is limited on both ends of the GGTT, because
> > > > > + * the GuC shim HW redirects accesses to those addresses to other HW
> > > > > + * areas instead of going through the GGTT. On the bottom end, the GuC
> > > > > + * can't access offsets below the WOPCM size, while on the top side the
> > > > > + * limit is fixed at GUC_GGTT_TOP. To keep things simple, instead of
> > > > > + * checking each object to see if they are accessed by GuC or not, we
> > > > > + * just exclude those areas from the allocator. Additionally, to
> > > > > + * simplify the driver load, we use the maximum WOPCM size in this logic
> > > > >
> > > > > > of being made explicit, leaving PTEs in [GUC_GGTT_TOP, total_size)
> > > > > > untouched during the initial clear.
> > > > >
> > > > > and that likely will not be changed by this patch as after allocating 'two
> > > > > permanent zones', the drm_mm_for_each_hole will not iterate over them
> > > >
> > > > right...
> > > >
> > > > >
> > > > > >
> > > > > > Fix this for the PF case by initialising drm_mm over the full hardware
> > > > > > GGTT range [0, total_size) and permanently reserving the two forbidden
> > > > > > zones:
> > > > > >
> > > > > > - [0, wopcm) — inaccessible below WOPCM
> > > > > > - [GUC_GGTT_TOP, total_size) — inaccessible above GUC_GGTT_TOP
> > > > >
> > > > > that looks odds: why pretend to claim manageability of full [0, 4GB)
> > > > > of the GGTT and then immediately permanently reserve two end zones to
> > > > > end up with real [wopcm, GUC_TOP) which is what we already have?
> > > >
> > > > yes...
> > > >
> > > > >
> > > > > >
> > > > > > A new mm_offset field (zero for PF) carries the base offset used in
> > > > > > address conversions, unifying the existing VF relative model (where
> > > > > > mm_offset == vf_base) with the new PF absolute model.
> > > > >
> > > > > but public xe_ggtt API already uses absolute addressing in PF and VF
> > > >
> > > > I know...
> > > >
> > > > >
> > > > > > The public
> > > > > > xe_ggtt_start() / xe_ggtt_size() API continues to return the usable
> > > > > > [wopcm, GUC_GGTT_TOP) boundaries, so callers such as the SR-IOV PF
> > > > > > config code are unaffected.
> > > > > >
> > > > > > xe_ggtt_shift_nodes() now updates both ggtt->start and ggtt->mm_offset
> > > > > > so the VF recovery path remains a single O(1) WRITE_ONCE pair.
> > > > >
> > > > > maybe it's just me - but I can't figure out the real rationale for this
> > > > > patch - what did I miss?
> > > >
> > > > This series:
> > > > https://lore.kernel.org/intel-xe/20260511214122.8468-1-ville.syrjala@linux.intel.com/
> > > >
> > > > And more specifically the discussion in this patch:
> > > > https://lore.kernel.org/intel-xe/20260511214122.8468-13-ville.syrjala@linux.intel.com/
> > > >
> > > > >
> > > > > >
> > > > > > Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > > Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> > > > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > > > Assisted-by: GitHub-Copilot:claude-sonnet-4.6
> > > > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > > > ---
> > > > > > drivers/gpu/drm/xe/xe_ggtt.c | 123 ++++++++++++++++++++++++++++-------
> > > > > > 1 file changed, 101 insertions(+), 22 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> > > > > > index a351c578b170..00a6cd2b8a51 100644
> > > > > > --- a/drivers/gpu/drm/xe/xe_ggtt.c
> > > > > > +++ b/drivers/gpu/drm/xe/xe_ggtt.c
> > > > > > @@ -137,6 +137,17 @@ struct xe_ggtt {
> > > > > > const struct xe_ggtt_pt_ops *pt_ops;
> > > > > > /** @mm: The memory manager used to manage individual GGTT allocations */
> > > > > > struct drm_mm mm;
> > > > > > + /**
> > > > > > + * @mm_offset: base offset added to drm_mm node addresses to obtain hardware
> > > > > > + * GGTT addresses. For PF this is 0 (drm_mm uses absolute hardware addresses).
> > > > > > + * For VF this equals @start (drm_mm uses relative addresses from VF base).
> > > > > > + * Updated atomically by xe_ggtt_shift_nodes() during VF recovery.
> > > > > > + */
> > > > > > + u64 mm_offset;
> > > > > > + /** @reserved_bottom: permanently reserved [0, WOPCM) drm_mm node for PF */
> > > > > > + struct drm_mm_node reserved_bottom;
> > > > > > + /** @reserved_top: permanently reserved [GUC_GGTT_TOP, total) drm_mm node for PF */
> > > > > > + struct drm_mm_node reserved_top;
> > > > >
> > > > > maybe all we need is to separate concepts of:
> > > > >
> > > > > * raw GGTT - fixed range [0, 4GB)
> > > > >
> > > > > from
> > > > >
> > > > > * allocable GGTT - configurable sub-range [start, end)
> > > > > * [wopcm, GUC_TOP) on PF
> > > > > * [base, base+size) on VF
> > > > >
> > > > > and then we can continue to use drm_mm.init(0, end-start) to manage
> > > > > that [start, end) range in a common way on both PF and VF?
> > > >
> > > > we need to be able to use a ggtt buffer that comes out of this range,
> > > > so I'm afraid it doesn't solve all the cases.
> > >
> > > Basically what the display needs is:
> > > 1. specify where in ggtt the buffer was originally placed by the GOP,
> > > this may be partially or fully inside these GuC reserved ranges
> > > 2. bind the buffer to some acceptable location (assuming the original
> > > location wasn't acceptable) without overwriting the PTEs for the
> > > original location
> > >
> > > I suppose this could be achieved even with this "mm doesn't cover the
> > > ends" hack, but step 1 there becomes a bit dodgy because we can't
> > > insert the mm node if it's fully outside the mm. I suppose it could
> > > still work if you hide it in a function that only validates the real
> > > ggtt offsets, but then ignores the fact that the node can't be
> > > inserted due to being fully inside those reserved ranges. And then
> > > whatever cleans up that original mm node must also ignore the fact
> > > that the node maybe wasn't even allocated. And also
> > > xe_ggtt_initial_clear() will need special code to clear the
> > > reserved ranges.
> >
> > right, so basically we could keep the xe_ggtt as is and provide
> > 2 hooks:
> >
> > 1. one to reserve the portion of the BIOS FB that goes
> > inside our managed ggtt area
> > 2. a special clear for this area
> >
> > And in between you do the rebind with existing infrastructure
> > to an empty region?! Is this what you are thinking now?
> >
> > >
> > > My original idea was that we'd just include the reserved regions
> > > in the mm, and then the display could just keep the buffer at its
> > > original location, and later the guc code can reserve what is
> > > left over. So we could skip step 2 above completely. But after
> > > a second thought we probably don't want to skip that step because
> > > we might free the display bo later, at which point we might free
> > > up some of the reserved ranges. So I guess we'd still want to keep
> > > step 2. But I think it'd still result in less special cases in the
> > > code. We'd just need the guc code to reserve what it needs, after
> > > the display code has rebound the bo to an acceptable location.
> > >
> > > So we'd end up with:
> > > 1. insert node for the bo's original ggtt location
> > > 2. rebind the display bo to an acceptable ggtt location
> > > 3. undo step 1
> > > 4. xe_ggtt_initial_clear() (now also clears the reserved ranges
> > > without any special code)
> > > 5. guc steals the reserved ranges explicitly
> > >
> > > So only two special cases left really, and all the rest
> > > of the code is blissfully unaware of any of it.
> > >
> > > Hmm, although hibernation might still be a slight issue for
> > > xe_ggtt_initial_clear(). As in how would the reserved regions
> > > get cleared during resume from hibernation? I have no idea
> > > how the current xe ggtt code handles resume at all...
> >
> > The resume should only restore the pinned bo's one by one, nothing
> > special.
>
> Looks like currently xe_ggtt_initial_clear() is never even called
> during resume from hibernation, so in that case parts of the GGTT
> will be left with whatever garbage the GOP put there. So that's
> one thing that needs fixing.
>
> > So I guess if we keep the original code we are okay,
> > but if we start to managing the full range with the reserved areas
> > we might have some difficulties here on the way...
>
> If we had a full range mm I suppose we'd need a bit of special code
> to remove the reserved nodes before xe_ggtt_initial_clear() gets
> called, at least for the resume from hibernation case.
it looks like Maarten suggestion fix the clear portion.
But for the steps 1 and 3 above we would need a special reservation
with a node area only within our managed area?!
something like (for step 1):
mm_start = max(start, ggtt->start);
mm_end = min(start + size, ggtt->start + ggtt->size);
node->base.start = mm_start - ggtt->start;
node->base.size = mm_end - mm_start;
drm_mm_reserve_node(&ggtt->mm, &node->base);
and another special function to delete this special node
if needed to be created?
Or what do you have on mind for the full area? I believe the full
area is this patch, but with some additions anyway since we need
to handle this buffer plus ensure it gets reserved when we don't
have it...
I'd like to avoid complications like the phys offset addition or
the full range if possible.
Could you please incorporate something simple in a v2 of your series?
Thanks,
Rodrigo.
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/xe/ggtt: use full-range drm_mm with reserved nodes on PF
2026-06-03 13:44 ` Rodrigo Vivi
@ 2026-06-03 14:54 ` Ville Syrjälä
0 siblings, 0 replies; 13+ messages in thread
From: Ville Syrjälä @ 2026-06-03 14:54 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: Michal Wajdeczko, intel-gfx, intel-xe, Maarten Lankhorst
On Wed, Jun 03, 2026 at 09:44:17AM -0400, Rodrigo Vivi wrote:
> On Wed, Jun 03, 2026 at 04:19:41PM +0300, Ville Syrjälä wrote:
> > On Fri, May 29, 2026 at 05:03:55PM -0400, Rodrigo Vivi wrote:
> > > On Fri, May 29, 2026 at 01:50:34PM +0300, Ville Syrjälä wrote:
> > > > On Thu, May 28, 2026 at 06:28:47PM -0400, Rodrigo Vivi wrote:
> > > > > On Fri, May 29, 2026 at 12:11:22AM +0200, Michal Wajdeczko wrote:
> > > > > >
> > > > > >
> > > > > > On 5/27/2026 4:45 PM, Rodrigo Vivi wrote:
> > > > > > > The PF GGTT allocator was initialised over a relative [0, usable_size)
> > > > > > > range, with ggtt->start added on every address conversion to get the
> > > > > > > actual hardware address. Two consequences of that model were considered
> > > > > > > "horrible hacks":
> > > > > > >
> > > > > > > - ggtt->start (the WOPCM offset) had to be carried around and added
> > > > > > > to every drm_mm result.
> > > > > >
> > > > > > hmm, but this an internal detail of the xe_ggtt implementation, so why
> > > > > > would someone else complain about it?
> > > > > >
> > > > > > > - The GUC_GGTT_TOP ceiling silently truncated the GGTT range instead
> > > > > >
> > > > > > hmm, for the record, this GGTT cap on the top was added back in 2023
> > > > > >
> > > > > > commit ab10e976fbda8349163ceee2ce99b2bfc97031b8
> > > > > > Author: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > > > > > Date: Wed Jun 14 10:47:54 2023 -0700
> > > > > >
> > > > > > drm/xe: limit GGTT size to GUC_GGTT_TOP
> > > > > >
> > > > > > + * The GuC address space is limited on both ends of the GGTT, because
> > > > > > + * the GuC shim HW redirects accesses to those addresses to other HW
> > > > > > + * areas instead of going through the GGTT. On the bottom end, the GuC
> > > > > > + * can't access offsets below the WOPCM size, while on the top side the
> > > > > > + * limit is fixed at GUC_GGTT_TOP. To keep things simple, instead of
> > > > > > + * checking each object to see if they are accessed by GuC or not, we
> > > > > > + * just exclude those areas from the allocator. Additionally, to
> > > > > > + * simplify the driver load, we use the maximum WOPCM size in this logic
> > > > > >
> > > > > > > of being made explicit, leaving PTEs in [GUC_GGTT_TOP, total_size)
> > > > > > > untouched during the initial clear.
> > > > > >
> > > > > > and that likely will not be changed by this patch as after allocating 'two
> > > > > > permanent zones', the drm_mm_for_each_hole will not iterate over them
> > > > >
> > > > > right...
> > > > >
> > > > > >
> > > > > > >
> > > > > > > Fix this for the PF case by initialising drm_mm over the full hardware
> > > > > > > GGTT range [0, total_size) and permanently reserving the two forbidden
> > > > > > > zones:
> > > > > > >
> > > > > > > - [0, wopcm) — inaccessible below WOPCM
> > > > > > > - [GUC_GGTT_TOP, total_size) — inaccessible above GUC_GGTT_TOP
> > > > > >
> > > > > > that looks odds: why pretend to claim manageability of full [0, 4GB)
> > > > > > of the GGTT and then immediately permanently reserve two end zones to
> > > > > > end up with real [wopcm, GUC_TOP) which is what we already have?
> > > > >
> > > > > yes...
> > > > >
> > > > > >
> > > > > > >
> > > > > > > A new mm_offset field (zero for PF) carries the base offset used in
> > > > > > > address conversions, unifying the existing VF relative model (where
> > > > > > > mm_offset == vf_base) with the new PF absolute model.
> > > > > >
> > > > > > but public xe_ggtt API already uses absolute addressing in PF and VF
> > > > >
> > > > > I know...
> > > > >
> > > > > >
> > > > > > > The public
> > > > > > > xe_ggtt_start() / xe_ggtt_size() API continues to return the usable
> > > > > > > [wopcm, GUC_GGTT_TOP) boundaries, so callers such as the SR-IOV PF
> > > > > > > config code are unaffected.
> > > > > > >
> > > > > > > xe_ggtt_shift_nodes() now updates both ggtt->start and ggtt->mm_offset
> > > > > > > so the VF recovery path remains a single O(1) WRITE_ONCE pair.
> > > > > >
> > > > > > maybe it's just me - but I can't figure out the real rationale for this
> > > > > > patch - what did I miss?
> > > > >
> > > > > This series:
> > > > > https://lore.kernel.org/intel-xe/20260511214122.8468-1-ville.syrjala@linux.intel.com/
> > > > >
> > > > > And more specifically the discussion in this patch:
> > > > > https://lore.kernel.org/intel-xe/20260511214122.8468-13-ville.syrjala@linux.intel.com/
> > > > >
> > > > > >
> > > > > > >
> > > > > > > Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > > > Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> > > > > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > > > > Assisted-by: GitHub-Copilot:claude-sonnet-4.6
> > > > > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > > > > ---
> > > > > > > drivers/gpu/drm/xe/xe_ggtt.c | 123 ++++++++++++++++++++++++++++-------
> > > > > > > 1 file changed, 101 insertions(+), 22 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> > > > > > > index a351c578b170..00a6cd2b8a51 100644
> > > > > > > --- a/drivers/gpu/drm/xe/xe_ggtt.c
> > > > > > > +++ b/drivers/gpu/drm/xe/xe_ggtt.c
> > > > > > > @@ -137,6 +137,17 @@ struct xe_ggtt {
> > > > > > > const struct xe_ggtt_pt_ops *pt_ops;
> > > > > > > /** @mm: The memory manager used to manage individual GGTT allocations */
> > > > > > > struct drm_mm mm;
> > > > > > > + /**
> > > > > > > + * @mm_offset: base offset added to drm_mm node addresses to obtain hardware
> > > > > > > + * GGTT addresses. For PF this is 0 (drm_mm uses absolute hardware addresses).
> > > > > > > + * For VF this equals @start (drm_mm uses relative addresses from VF base).
> > > > > > > + * Updated atomically by xe_ggtt_shift_nodes() during VF recovery.
> > > > > > > + */
> > > > > > > + u64 mm_offset;
> > > > > > > + /** @reserved_bottom: permanently reserved [0, WOPCM) drm_mm node for PF */
> > > > > > > + struct drm_mm_node reserved_bottom;
> > > > > > > + /** @reserved_top: permanently reserved [GUC_GGTT_TOP, total) drm_mm node for PF */
> > > > > > > + struct drm_mm_node reserved_top;
> > > > > >
> > > > > > maybe all we need is to separate concepts of:
> > > > > >
> > > > > > * raw GGTT - fixed range [0, 4GB)
> > > > > >
> > > > > > from
> > > > > >
> > > > > > * allocable GGTT - configurable sub-range [start, end)
> > > > > > * [wopcm, GUC_TOP) on PF
> > > > > > * [base, base+size) on VF
> > > > > >
> > > > > > and then we can continue to use drm_mm.init(0, end-start) to manage
> > > > > > that [start, end) range in a common way on both PF and VF?
> > > > >
> > > > > we need to be able to use a ggtt buffer that comes out of this range,
> > > > > so I'm afraid it doesn't solve all the cases.
> > > >
> > > > Basically what the display needs is:
> > > > 1. specify where in ggtt the buffer was originally placed by the GOP,
> > > > this may be partially or fully inside these GuC reserved ranges
> > > > 2. bind the buffer to some acceptable location (assuming the original
> > > > location wasn't acceptable) without overwriting the PTEs for the
> > > > original location
> > > >
> > > > I suppose this could be achieved even with this "mm doesn't cover the
> > > > ends" hack, but step 1 there becomes a bit dodgy because we can't
> > > > insert the mm node if it's fully outside the mm. I suppose it could
> > > > still work if you hide it in a function that only validates the real
> > > > ggtt offsets, but then ignores the fact that the node can't be
> > > > inserted due to being fully inside those reserved ranges. And then
> > > > whatever cleans up that original mm node must also ignore the fact
> > > > that the node maybe wasn't even allocated. And also
> > > > xe_ggtt_initial_clear() will need special code to clear the
> > > > reserved ranges.
> > >
> > > right, so basically we could keep the xe_ggtt as is and provide
> > > 2 hooks:
> > >
> > > 1. one to reserve the portion of the BIOS FB that goes
> > > inside our managed ggtt area
> > > 2. a special clear for this area
> > >
> > > And in between you do the rebind with existing infrastructure
> > > to an empty region?! Is this what you are thinking now?
> > >
> > > >
> > > > My original idea was that we'd just include the reserved regions
> > > > in the mm, and then the display could just keep the buffer at its
> > > > original location, and later the guc code can reserve what is
> > > > left over. So we could skip step 2 above completely. But after
> > > > a second thought we probably don't want to skip that step because
> > > > we might free the display bo later, at which point we might free
> > > > up some of the reserved ranges. So I guess we'd still want to keep
> > > > step 2. But I think it'd still result in less special cases in the
> > > > code. We'd just need the guc code to reserve what it needs, after
> > > > the display code has rebound the bo to an acceptable location.
> > > >
> > > > So we'd end up with:
> > > > 1. insert node for the bo's original ggtt location
> > > > 2. rebind the display bo to an acceptable ggtt location
> > > > 3. undo step 1
> > > > 4. xe_ggtt_initial_clear() (now also clears the reserved ranges
> > > > without any special code)
> > > > 5. guc steals the reserved ranges explicitly
> > > >
> > > > So only two special cases left really, and all the rest
> > > > of the code is blissfully unaware of any of it.
> > > >
> > > > Hmm, although hibernation might still be a slight issue for
> > > > xe_ggtt_initial_clear(). As in how would the reserved regions
> > > > get cleared during resume from hibernation? I have no idea
> > > > how the current xe ggtt code handles resume at all...
> > >
> > > The resume should only restore the pinned bo's one by one, nothing
> > > special.
> >
> > Looks like currently xe_ggtt_initial_clear() is never even called
> > during resume from hibernation, so in that case parts of the GGTT
> > will be left with whatever garbage the GOP put there. So that's
> > one thing that needs fixing.
> >
> > > So I guess if we keep the original code we are okay,
> > > but if we start to managing the full range with the reserved areas
> > > we might have some difficulties here on the way...
> >
> > If we had a full range mm I suppose we'd need a bit of special code
> > to remove the reserved nodes before xe_ggtt_initial_clear() gets
> > called, at least for the resume from hibernation case.
>
> it looks like Maarten suggestion fix the clear portion.
> But for the steps 1 and 3 above we would need a special reservation
> with a node area only within our managed area?!
>
> something like (for step 1):
>
> mm_start = max(start, ggtt->start);
> mm_end = min(start + size, ggtt->start + ggtt->size);
>
> node->base.start = mm_start - ggtt->start;
> node->base.size = mm_end - mm_start;
>
> drm_mm_reserve_node(&ggtt->mm, &node->base);
>
> and another special function to delete this special node
> if needed to be created?
Something like that could work.
> Or what do you have on mind for the full area? I believe the full
> area is this patch, but with some additions anyway since we need
> to handle this buffer plus ensure it gets reserved when we don't
> have it...
From the display side the full mm approach shouldn't really
look any different.
>
> I'd like to avoid complications like the phys offset addition
What phys_offset addition are we talking about here?
> or
> the full range if possible.
>
> Could you please incorporate something simple in a v2 of your series?
If you mean me and my initial fb series then I have no plan to
post a v2 of that. What I posted is IMO just fine as is. The
remaining broken corner cases can be fixed afterwards once we
get that new thing to properly protect the current PTEs.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2026-06-03 14:54 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-05-27 14:45 [PATCH] drm/xe/ggtt: use full-range drm_mm with reserved nodes on PF Rodrigo Vivi
2026-05-27 17:42 ` ✓ CI.KUnit: success for " Patchwork
2026-05-27 18:55 ` ✓ Xe.CI.BAT: " Patchwork
2026-05-28 1:47 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-05-28 22:11 ` [PATCH] " Michal Wajdeczko
2026-05-28 22:28 ` Rodrigo Vivi
2026-05-29 10:50 ` Ville Syrjälä
2026-05-29 21:03 ` Rodrigo Vivi
2026-06-03 13:19 ` Ville Syrjälä
2026-06-03 13:44 ` Rodrigo Vivi
2026-06-03 14:54 ` Ville Syrjälä
2026-06-03 12:57 ` [PATCH] drm/xe/ggtt: clear reserved area at GUC_GGTT_TOP Maarten Lankhorst
2026-06-03 13:11 ` Ville Syrjälä
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