[PATCH v8 00/20] CMTG enablement

[PATCH v8 00/20] CMTG enablement

[Animesh Manna]

Common mode timing generator (CMTG) support is added NVL onwards.
Enable CMTG which will be needed by other fearure like dynamic dc
state enablement later.

Testing ongoing, currently counters are incrementing as expected.

Animesh Manna (17):
  drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG
  drm/i915/cmtg: Set CMTG clock select
  drm/i915/cmtg: Add CMTG transcoder offset in struct _device_info
  drm/i915/display: Pass target transcoder to
    intel_set_transcoder_timings()
  drm/i915/display: Skip DP_MIN_HBLANK_CTL programming for CMTG
    transcoders
  drm/i915/display: Pass transcoder to
    intel_set_transcoder_timings_lrr()
  drm/i915/cmtg: Set timings for CMTG by using transcoder timing helpers
  drm/i915/vrr: Pass transcoder to intel_vrr_set_fixed_rr_timings()
  drm/i915/cmtg: Program VRR fixed-rate timings for CMTG transcoder
  drm/i915/cmtg: Program VRR control register for CMTG transcoder
  drm/i915/cmtg: Set link M/N for CMTG transcoder
  drm/i915/cmtg: Add hook to enable CMTG with sync to port
  drm/i915/cmtg: Add a hook to make eDP transcoder secondary
  drm/i915/cmtg: Add CMTG interrupt handling
  drm/i915/cmtg: Add trigger to enable/disable cmtg
  drm/i915/cmtg: Restore CMTG after DC6 exit
  Debug patch

Dibin Moolakadan Subrahmanian (3):
  drm/i915/cmtg: Modify existing hook to disable CMTG
  drm/i915/cmtg: Add CMTG HWGB programming
  drm/i915/cmtg: Add CMTG scan line programming

 drivers/gpu/drm/i915/display/intel_cmtg.c     | 280 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  14 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  24 +-
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  11 +
 drivers/gpu/drm/i915/display/intel_display.c  |  96 ++++--
 drivers/gpu/drm/i915/display/intel_display.h  |   4 +
 .../drm/i915/display/intel_display_device.c   |  14 +
 .../drm/i915/display/intel_display_device.h   |   2 +-
 .../gpu/drm/i915/display/intel_display_irq.c  |  12 +
 .../drm/i915/display/intel_display_limits.h   |   2 +
 .../drm/i915/display/intel_display_power.c    |  17 ++
 .../drm/i915/display/intel_display_power.h    |   2 +
 .../gpu/drm/i915/display/intel_display_regs.h |   2 +
 .../drm/i915/display/intel_display_types.h    |   4 +
 drivers/gpu/drm/i915/display/intel_vrr.c      |  18 +-
 drivers/gpu/drm/i915/display/intel_vrr.h      |   5 +-
 16 files changed, 458 insertions(+), 49 deletions(-)

-- 
2.29.0

[PATCH v8 01/20] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG

[Animesh Manna]

CMTG is supported on transcoder A and transcoder B with EDP,
so add a separate helper intel_cmtg_is_allowed() to check the
prerequisites for enabling CMTG. CMTG will be enabled only in
specific use cases such as PSR2, PR-ALPM, and LOBF, and will be
used in conjunction with the DC3CO feature. DC3co will be enabled
in a separate patch.

Note: Use-case-specific checks and transcoder-port compatibility
validation will be handled part of DC3co feature implementation.

v2:
- Remove separate flag for DC3co from crtc_state. [Uma, Dibin]

v3:
- Do not access power domain members directly. [Jani]

v4:
- Remove check for DC3co state now. if needed add Dc3co allow check
later once Dc3co patches are merged. [Uma]

Bspec: 68915
Reviewed-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c | 14 +++++++++++++-
 drivers/gpu/drm/i915/display/intel_cmtg.h |  4 ++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index e1fdc6fe9762..a279f3dcd1ec 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -4,7 +4,6 @@
  */
 
 #include <linux/string_choices.h>
-#include <linux/types.h>
 
 #include <drm/drm_device.h>
 #include <drm/drm_print.h>
@@ -16,6 +15,7 @@
 #include "intel_display_device.h"
 #include "intel_display_power.h"
 #include "intel_display_regs.h"
+#include "intel_display_types.h"
 
 /**
  * DOC: Common Primary Timing Generator (CMTG)
@@ -185,3 +185,15 @@ void intel_cmtg_sanitize(struct intel_display *display)
 
 	intel_cmtg_disable(display, &cmtg_config);
 }
+
+bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B) &&
+	    DISPLAY_VER(display) == 35 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+		return true;
+
+	return false;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index ba62199adaa2..ed540581738f 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -6,8 +6,12 @@
 #ifndef __INTEL_CMTG_H__
 #define __INTEL_CMTG_H__
 
+#include <linux/types.h>
+
 struct intel_display;
+struct intel_crtc_state;
 
 void intel_cmtg_sanitize(struct intel_display *display);
+bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_CMTG_H__ */
-- 
2.29.0

RE: [PATCH v8 01/20] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Thursday, June 4, 2026 1:24 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v8 01/20] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG
> 
> CMTG is supported on transcoder A and transcoder B with EDP, so add a
> separate helper intel_cmtg_is_allowed() to check the prerequisites for enabling
> CMTG. CMTG will be enabled only in specific use cases such as PSR2, PR-
> ALPM, and LOBF, and will be used in conjunction with the DC3CO feature. DC3co
> will be enabled in a separate patch.
> 
> Note: Use-case-specific checks and transcoder-port compatibility validation will
> be handled part of DC3co feature implementation.
> 
> v2:
> - Remove separate flag for DC3co from crtc_state. [Uma, Dibin]
> 
> v3:
> - Do not access power domain members directly. [Jani]
> 
> v4:
> - Remove check for DC3co state now. if needed add Dc3co allow check later once
> Dc3co patches are merged. [Uma]

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Bspec: 68915
> Reviewed-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c | 14 +++++++++++++-
> drivers/gpu/drm/i915/display/intel_cmtg.h |  4 ++++
>  2 files changed, 17 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index e1fdc6fe9762..a279f3dcd1ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -4,7 +4,6 @@
>   */
> 
>  #include <linux/string_choices.h>
> -#include <linux/types.h>
> 
>  #include <drm/drm_device.h>
>  #include <drm/drm_print.h>
> @@ -16,6 +15,7 @@
>  #include "intel_display_device.h"
>  #include "intel_display_power.h"
>  #include "intel_display_regs.h"
> +#include "intel_display_types.h"
> 
>  /**
>   * DOC: Common Primary Timing Generator (CMTG) @@ -185,3 +185,15 @@
> void intel_cmtg_sanitize(struct intel_display *display)
> 
>  	intel_cmtg_disable(display, &cmtg_config);  }
> +
> +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder ==
> TRANSCODER_B) &&
> +	    DISPLAY_VER(display) == 35 && intel_crtc_has_type(crtc_state,
> INTEL_OUTPUT_EDP))
> +		return true;
> +
> +	return false;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index ba62199adaa2..ed540581738f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -6,8 +6,12 @@
>  #ifndef __INTEL_CMTG_H__
>  #define __INTEL_CMTG_H__
> 
> +#include <linux/types.h>
> +
>  struct intel_display;
> +struct intel_crtc_state;
> 
>  void intel_cmtg_sanitize(struct intel_display *display);
> +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
> 
>  #endif /* __INTEL_CMTG_H__ */
> --
> 2.29.0

RE: [PATCH v8 01/20] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG

[Shankar, Uma]

> -----Original Message-----
> From: Shankar, Uma
> Sent: Wednesday, June 10, 2026 10:47 AM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>
> Subject: RE: [PATCH v8 01/20] drm/i915/cmtg: Add intel_cmtg_is_allowed() for
> CMTG
> 
> 
> 
> > -----Original Message-----
> > From: Manna, Animesh <animesh.manna@intel.com>
> > Sent: Thursday, June 4, 2026 1:24 AM
> > To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan
> > Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>;
> > ville.syrjala@linux.intel.com; Nikula, Jani <jani.nikula@intel.com>;
> > Manna, Animesh <animesh.manna@intel.com>
> > Subject: [PATCH v8 01/20] drm/i915/cmtg: Add intel_cmtg_is_allowed()
> > for CMTG
> >
> > CMTG is supported on transcoder A and transcoder B with EDP, so add a
> > separate helper intel_cmtg_is_allowed() to check the prerequisites for
> > enabling CMTG. CMTG will be enabled only in specific use cases such as
> > PSR2, PR- ALPM, and LOBF, and will be used in conjunction with the
> > DC3CO feature. DC3co will be enabled in a separate patch.
> >
> > Note: Use-case-specific checks and transcoder-port compatibility
> > validation will be handled part of DC3co feature implementation.
> >
> > v2:
> > - Remove separate flag for DC3co from crtc_state. [Uma, Dibin]
> >
> > v3:
> > - Do not access power domain members directly. [Jani]
> >
> > v4:
> > - Remove check for DC3co state now. if needed add Dc3co allow check
> > later once Dc3co patches are merged. [Uma]
> 
> Looks Good to me.
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> 
> > Bspec: 68915
> > Reviewed-by: Dibin Moolakadan Subrahmanian
> > <dibin.moolakadan.subrahmanian@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cmtg.c | 14 +++++++++++++-
> > drivers/gpu/drm/i915/display/intel_cmtg.h |  4 ++++
> >  2 files changed, 17 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > index e1fdc6fe9762..a279f3dcd1ec 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > @@ -4,7 +4,6 @@
> >   */
> >
> >  #include <linux/string_choices.h>
> > -#include <linux/types.h>
> >
> >  #include <drm/drm_device.h>
> >  #include <drm/drm_print.h>
> > @@ -16,6 +15,7 @@
> >  #include "intel_display_device.h"
> >  #include "intel_display_power.h"
> >  #include "intel_display_regs.h"
> > +#include "intel_display_types.h"
> >
> >  /**
> >   * DOC: Common Primary Timing Generator (CMTG) @@ -185,3 +185,15 @@
> > void intel_cmtg_sanitize(struct intel_display *display)
> >
> >  	intel_cmtg_disable(display, &cmtg_config);  }
> > +
> > +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state) {

Missed to add: Since we are exporting this function in header, would be
good to add some comments as per driver policy.

> > +	struct intel_display *display = to_intel_display(crtc_state);
> > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > +
> > +	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder ==
> > TRANSCODER_B) &&
> > +	    DISPLAY_VER(display) == 35 && intel_crtc_has_type(crtc_state,
> > INTEL_OUTPUT_EDP))
> > +		return true;
> > +
> > +	return false;
> > +}
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > index ba62199adaa2..ed540581738f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > @@ -6,8 +6,12 @@
> >  #ifndef __INTEL_CMTG_H__
> >  #define __INTEL_CMTG_H__
> >
> > +#include <linux/types.h>
> > +
> >  struct intel_display;
> > +struct intel_crtc_state;
> >
> >  void intel_cmtg_sanitize(struct intel_display *display);
> > +bool intel_cmtg_is_allowed(const struct intel_crtc_state
> > +*crtc_state);
> >
> >  #endif /* __INTEL_CMTG_H__ */
> > --
> > 2.29.0

[PATCH v8 02/20] drm/i915/cmtg: Set CMTG clock select

[Animesh Manna]

Program the CMTG Clock Select register based on the transcoder used.

v2:
- Correct mask for PHY B. [Jani]
- Use REG_FIELD_PREP() for enable value. [Dibin]
- Extend cmtg clock select for xe3plpd. [Dibin]

v3:
- CMTG support removed for old platform.

v4:
- Optimize further with else-if. [Uma]
- Correct CMTG_CLK_SEL_B_MASK. [Uma]

v5:
- Add transcoder-port compatibility check. [Dibin]

Bspec: 69103
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 22 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  2 ++
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 11 ++++++++++
 4 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index a279f3dcd1ec..fbc8a4f2b9cb 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -197,3 +197,25 @@ bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
 
 	return false;
 }
+
+void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 clk_sel_clr = 0;
+	u32 clk_sel_set = 0;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	if (cpu_transcoder == TRANSCODER_A) {
+		clk_sel_clr = CMTG_CLK_SEL_A_MASK;
+		clk_sel_set = CMTG_CLK_SELECT_PHYA_ENABLE;
+	} else if (cpu_transcoder == TRANSCODER_B) {
+		clk_sel_clr = CMTG_CLK_SEL_B_MASK;
+		clk_sel_set = CMTG_CLK_SELECT_PHYB_ENABLE;
+	}
+
+	if (clk_sel_set)
+		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index ed540581738f..87092ce6d67b 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 945a35578284..4a80b88d88fd 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -10,8 +10,10 @@
 
 #define CMTG_CLK_SEL			_MMIO(0x46160)
 #define CMTG_CLK_SEL_A_MASK		REG_GENMASK(31, 29)
+#define CMTG_CLK_SELECT_PHYA_ENABLE	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x4)
 #define CMTG_CLK_SEL_A_DISABLED		REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0)
 #define CMTG_CLK_SEL_B_MASK		REG_GENMASK(15, 13)
+#define CMTG_CLK_SELECT_PHYB_ENABLE	REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0x6)
 #define CMTG_CLK_SEL_B_DISABLED		REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
 
 #define TRANS_CMTG_CTL_A		_MMIO(0x6fa88)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 24a51ab21b55..452062417ce9 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -9,6 +9,7 @@
 #include <drm/drm_print.h>
 
 #include "intel_alpm.h"
+#include "intel_cmtg.h"
 #include "intel_cx0_phy.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_display_regs.h"
@@ -3418,10 +3419,20 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder,
 void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
 				const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(encoder);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
 		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
+
+	/*
+	 * CMTG can be enabled only when the transcoder and port are compatible
+	 * (transcoder A with port A, transcoder B with port B).
+	 */
+	if (HAS_LT_PHY(display) &&
+	    ((crtc_state->cpu_transcoder == TRANSCODER_A && encoder->port == PORT_A) ||
+	     (crtc_state->cpu_transcoder == TRANSCODER_B && encoder->port == PORT_B)))
+		intel_cmtg_set_clk_select(crtc_state);
 }
 
 /*
-- 
2.29.0

RE: [PATCH v8 02/20] drm/i915/cmtg: Set CMTG clock select

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Thursday, June 4, 2026 1:24 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v8 02/20] drm/i915/cmtg: Set CMTG clock select
> 
> Program the CMTG Clock Select register based on the transcoder used.
> 
> v2:
> - Correct mask for PHY B. [Jani]
> - Use REG_FIELD_PREP() for enable value. [Dibin]
> - Extend cmtg clock select for xe3plpd. [Dibin]
> 
> v3:
> - CMTG support removed for old platform.
> 
> v4:
> - Optimize further with else-if. [Uma]
> - Correct CMTG_CLK_SEL_B_MASK. [Uma]
> 
> v5:
> - Add transcoder-port compatibility check. [Dibin]

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Bspec: 69103
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c     | 22 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
>  .../gpu/drm/i915/display/intel_cmtg_regs.h    |  2 ++
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 11 ++++++++++
>  4 files changed, 36 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index a279f3dcd1ec..fbc8a4f2b9cb 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -197,3 +197,25 @@ bool intel_cmtg_is_allowed(const struct intel_crtc_state
> *crtc_state)
> 
>  	return false;
>  }
> +
> +void intel_cmtg_set_clk_select(const struct intel_crtc_state
> +*crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 clk_sel_clr = 0;
> +	u32 clk_sel_set = 0;
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	if (cpu_transcoder == TRANSCODER_A) {
> +		clk_sel_clr = CMTG_CLK_SEL_A_MASK;
> +		clk_sel_set = CMTG_CLK_SELECT_PHYA_ENABLE;
> +	} else if (cpu_transcoder == TRANSCODER_B) {
> +		clk_sel_clr = CMTG_CLK_SEL_B_MASK;
> +		clk_sel_set = CMTG_CLK_SELECT_PHYB_ENABLE;
> +	}
> +
> +	if (clk_sel_set)
> +		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index ed540581738f..87092ce6d67b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -11,6 +11,7 @@
>  struct intel_display;
>  struct intel_crtc_state;
> 
> +void intel_cmtg_set_clk_select(const struct intel_crtc_state
> +*crtc_state);
>  void intel_cmtg_sanitize(struct intel_display *display);  bool
> intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index 945a35578284..4a80b88d88fd 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -10,8 +10,10 @@
> 
>  #define CMTG_CLK_SEL			_MMIO(0x46160)
>  #define CMTG_CLK_SEL_A_MASK		REG_GENMASK(31, 29)
> +#define CMTG_CLK_SELECT_PHYA_ENABLE
> 	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x4)
>  #define CMTG_CLK_SEL_A_DISABLED
> 	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0)
>  #define CMTG_CLK_SEL_B_MASK		REG_GENMASK(15, 13)
> +#define CMTG_CLK_SELECT_PHYB_ENABLE
> 	REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0x6)
>  #define CMTG_CLK_SEL_B_DISABLED
> 	REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
> 
>  #define TRANS_CMTG_CTL_A		_MMIO(0x6fa88)
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 24a51ab21b55..452062417ce9 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -9,6 +9,7 @@
>  #include <drm/drm_print.h>
> 
>  #include "intel_alpm.h"
> +#include "intel_cmtg.h"
>  #include "intel_cx0_phy.h"
>  #include "intel_cx0_phy_regs.h"
>  #include "intel_display_regs.h"
> @@ -3418,10 +3419,20 @@ void intel_mtl_pll_enable(struct intel_encoder
> *encoder,  void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
>  				const struct intel_crtc_state *crtc_state)  {
> +	struct intel_display *display = to_intel_display(encoder);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> 
>  	if (intel_tc_port_in_tbt_alt_mode(dig_port))
>  		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
> +
> +	/*
> +	 * CMTG can be enabled only when the transcoder and port are
> compatible
> +	 * (transcoder A with port A, transcoder B with port B).
> +	 */
> +	if (HAS_LT_PHY(display) &&
> +	    ((crtc_state->cpu_transcoder == TRANSCODER_A && encoder->port
> == PORT_A) ||
> +	     (crtc_state->cpu_transcoder == TRANSCODER_B && encoder->port
> == PORT_B)))
> +		intel_cmtg_set_clk_select(crtc_state);
>  }
> 
>  /*
> --
> 2.29.0

[PATCH v8 03/20] drm/i915/cmtg: Add CMTG transcoder offset in struct _device_info

[Animesh Manna]

As all cmtg registers offset from base cmtg register is similar to
normal transcoder register, so follow existing way of defining
transcoder register for cmtg as well. Add base CMTG offset in
struct _display_device_info which will be used to derive the actual
register address for platform supporting CMTG.

Bspec: 68989
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 .../gpu/drm/i915/display/intel_display_device.c    | 14 ++++++++++++++
 .../gpu/drm/i915/display/intel_display_device.h    |  2 +-
 .../gpu/drm/i915/display/intel_display_limits.h    |  2 ++
 3 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 69a9f782935c..f17fc2c68472 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -101,6 +101,8 @@ static const struct intel_display_device_info no_display = {};
 #define TRANSCODER_EDP_OFFSET 0x6f000
 #define TRANSCODER_DSI0_OFFSET	0x6b000
 #define TRANSCODER_DSI1_OFFSET	0x6b800
+#define TRANSCODER_CMTG0_OFFSET 0x6F000
+#define TRANSCODER_CMTG1_OFFSET 0x6F100
 
 #define CURSOR_A_OFFSET 0x70080
 #define CURSOR_B_OFFSET 0x700c0
@@ -1352,6 +1354,18 @@ static const struct intel_display_device_info xe2_lpd_display = {
 		BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) |
 		BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D),
 	.__runtime_defaults.has_dbuf_overlap_detection = true,
+	.trans_offsets = {
+		[TRANSCODER_A] = TRANSCODER_A_OFFSET,
+		[TRANSCODER_B] = TRANSCODER_B_OFFSET,
+		[TRANSCODER_C] = TRANSCODER_C_OFFSET,
+		[TRANSCODER_D] = TRANSCODER_D_OFFSET,
+		[TRANSCODER_CMTG0] = TRANSCODER_CMTG0_OFFSET,
+		[TRANSCODER_CMTG1] = TRANSCODER_CMTG1_OFFSET,
+	},
+	.__runtime_defaults.cpu_transcoder_mask =
+		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
+		BIT(TRANSCODER_CMTG0) | BIT(TRANSCODER_CMTG1),
 };
 
 static const struct intel_display_device_info wcl_display = {
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 12e5a522a299..acb9ca87dda7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -292,7 +292,7 @@ struct intel_display_runtime_info {
 	u32 rawclk_freq;
 
 	u8 pipe_mask;
-	u8 cpu_transcoder_mask;
+	u16 cpu_transcoder_mask;
 	u16 port_mask;
 
 	u8 num_sprites[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h b/drivers/gpu/drm/i915/display/intel_display_limits.h
index 453f7b720815..ea89473c177f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_limits.h
+++ b/drivers/gpu/drm/i915/display/intel_display_limits.h
@@ -45,6 +45,8 @@ enum transcoder {
 	TRANSCODER_DSI_1,
 	TRANSCODER_DSI_A = TRANSCODER_DSI_0,	/* legacy DSI */
 	TRANSCODER_DSI_C = TRANSCODER_DSI_1,	/* legacy DSI */
+	TRANSCODER_CMTG0,
+	TRANSCODER_CMTG1,
 
 	I915_MAX_TRANSCODERS
 };
-- 
2.29.0

RE: [PATCH v8 03/20] drm/i915/cmtg: Add CMTG transcoder offset in struct _device_info

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Thursday, June 4, 2026 1:24 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v8 03/20] drm/i915/cmtg: Add CMTG transcoder offset in struct
> _device_info
> 
> As all cmtg registers offset from base cmtg register is similar to normal
> transcoder register, so follow existing way of defining transcoder register for cmtg
> as well. Add base CMTG offset in struct _display_device_info which will be used
> to derive the actual register address for platform supporting CMTG.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Bspec: 68989
> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_device.c    | 14 ++++++++++++++
>  .../gpu/drm/i915/display/intel_display_device.h    |  2 +-
>  .../gpu/drm/i915/display/intel_display_limits.h    |  2 ++
>  3 files changed, 17 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 69a9f782935c..f17fc2c68472 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -101,6 +101,8 @@ static const struct intel_display_device_info no_display =
> {};  #define TRANSCODER_EDP_OFFSET 0x6f000
>  #define TRANSCODER_DSI0_OFFSET	0x6b000
>  #define TRANSCODER_DSI1_OFFSET	0x6b800
> +#define TRANSCODER_CMTG0_OFFSET 0x6F000 #define
> TRANSCODER_CMTG1_OFFSET
> +0x6F100
> 
>  #define CURSOR_A_OFFSET 0x70080
>  #define CURSOR_B_OFFSET 0x700c0
> @@ -1352,6 +1354,18 @@ static const struct intel_display_device_info
> xe2_lpd_display = {
>  		BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) |
>  		BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D),
>  	.__runtime_defaults.has_dbuf_overlap_detection = true,
> +	.trans_offsets = {
> +		[TRANSCODER_A] = TRANSCODER_A_OFFSET,
> +		[TRANSCODER_B] = TRANSCODER_B_OFFSET,
> +		[TRANSCODER_C] = TRANSCODER_C_OFFSET,
> +		[TRANSCODER_D] = TRANSCODER_D_OFFSET,
> +		[TRANSCODER_CMTG0] = TRANSCODER_CMTG0_OFFSET,
> +		[TRANSCODER_CMTG1] = TRANSCODER_CMTG1_OFFSET,
> +	},
> +	.__runtime_defaults.cpu_transcoder_mask =
> +		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
> +		BIT(TRANSCODER_CMTG0) | BIT(TRANSCODER_CMTG1),
>  };
> 
>  static const struct intel_display_device_info wcl_display = { diff --git
> a/drivers/gpu/drm/i915/display/intel_display_device.h
> b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 12e5a522a299..acb9ca87dda7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -292,7 +292,7 @@ struct intel_display_runtime_info {
>  	u32 rawclk_freq;
> 
>  	u8 pipe_mask;
> -	u8 cpu_transcoder_mask;
> +	u16 cpu_transcoder_mask;
>  	u16 port_mask;
> 
>  	u8 num_sprites[I915_MAX_PIPES];
> diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h
> b/drivers/gpu/drm/i915/display/intel_display_limits.h
> index 453f7b720815..ea89473c177f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_limits.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_limits.h
> @@ -45,6 +45,8 @@ enum transcoder {
>  	TRANSCODER_DSI_1,
>  	TRANSCODER_DSI_A = TRANSCODER_DSI_0,	/* legacy DSI */
>  	TRANSCODER_DSI_C = TRANSCODER_DSI_1,	/* legacy DSI */
> +	TRANSCODER_CMTG0,
> +	TRANSCODER_CMTG1,
> 
>  	I915_MAX_TRANSCODERS
>  };
> --
> 2.29.0

[PATCH v8 04/20] drm/i915/display: Pass target transcoder to intel_set_transcoder_timings()

[Animesh Manna]

Let intel_set_transcoder_timings() take the target transcoder as an
explicit argument instead of always using crtc_state->cpu_transcoder.
This makes the helper reusable for callers that need to program timings
for a transcoder other than the CRTC's CPU transcoder.

Update all existing callers to pass crtc_state->cpu_transcoder so there
is no functional change.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 35 ++++++++++----------
 1 file changed, 18 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8e269b71f18e..9031264a34fc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -132,7 +132,8 @@
 #include "vlv_dsi_pll.h"
 #include "vlv_dsi_regs.h"
 
-static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
+static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state,
+					 enum transcoder transcoder);
 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
 static void bdw_set_pipe_misc(struct intel_dsb *dsb,
@@ -1504,7 +1505,7 @@ static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
 					       &crtc_state->dp_m2_n2);
 	}
 
-	intel_set_transcoder_timings(crtc_state);
+	intel_set_transcoder_timings(crtc_state, crtc_state->cpu_transcoder);
 
 	ilk_set_pipeconf(crtc_state);
 }
@@ -1635,7 +1636,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
 					       &crtc_state->dp_m2_n2);
 	}
 
-	intel_set_transcoder_timings(crtc_state);
+	intel_set_transcoder_timings(crtc_state, crtc_state->cpu_transcoder);
 
 	if (cpu_transcoder != TRANSCODER_EDP)
 		intel_de_write(display, TRANS_MULT(display, cpu_transcoder),
@@ -2048,7 +2049,7 @@ static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_st
 					       &crtc_state->dp_m2_n2);
 	}
 
-	intel_set_transcoder_timings(crtc_state);
+	intel_set_transcoder_timings(crtc_state, crtc_state->cpu_transcoder);
 
 	i9xx_set_pipeconf(crtc_state);
 }
@@ -2664,17 +2665,17 @@ transcoder_has_vrr(const struct intel_crtc_state *crtc_state)
 	return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder);
 }
 
-static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
+static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state,
+					 enum transcoder transcoder)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
-	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
 	int vsyncshift = 0;
 
-	drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
+	drm_WARN_ON(display->drm, transcoder_is_dsi(transcoder));
 
 	/* We need to be careful not to changed the adjusted mode, for otherwise
 	 * the hw state checker will get angry at the mismatch. */
@@ -2703,7 +2704,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 	 */
 	if (DISPLAY_VER(display) >= 13) {
 		intel_de_write(display,
-			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
+			       TRANS_SET_CONTEXT_LATENCY(display, transcoder),
 			       crtc_state->set_context_latency);
 
 		/*
@@ -2718,16 +2719,16 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 
 	if (DISPLAY_VER(display) >= 4 && DISPLAY_VER(display) < 35)
 		intel_de_write(display,
-			       TRANS_VSYNCSHIFT(display, cpu_transcoder),
+			       TRANS_VSYNCSHIFT(display, transcoder),
 			       vsyncshift);
 
-	intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
+	intel_de_write(display, TRANS_HTOTAL(display, transcoder),
 		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
 		       HTOTAL(adjusted_mode->crtc_htotal - 1));
-	intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
+	intel_de_write(display, TRANS_HBLANK(display, transcoder),
 		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
 		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
-	intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
+	intel_de_write(display, TRANS_HSYNC(display, transcoder),
 		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
 		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
 
@@ -2740,13 +2741,13 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 	if (intel_vrr_always_use_vrr_tg(display))
 		crtc_vtotal = 1;
 
-	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
+	intel_de_write(display, TRANS_VTOTAL(display, transcoder),
 		       VACTIVE(crtc_vdisplay - 1) |
 		       VTOTAL(crtc_vtotal - 1));
-	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
+	intel_de_write(display, TRANS_VBLANK(display, transcoder),
 		       VBLANK_START(crtc_vblank_start - 1) |
 		       VBLANK_END(crtc_vblank_end - 1));
-	intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
+	intel_de_write(display, TRANS_VSYNC(display, transcoder),
 		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
 		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
 
@@ -2754,7 +2755,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 	 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
 	 * documented on the DDI_FUNC_CTL register description, EDP Input Select
 	 * bits. */
-	if (display->platform.haswell && cpu_transcoder == TRANSCODER_EDP &&
+	if (display->platform.haswell && transcoder == TRANSCODER_EDP &&
 	    (pipe == PIPE_B || pipe == PIPE_C))
 		intel_de_write(display, TRANS_VTOTAL(display, pipe),
 			       VACTIVE(crtc_vdisplay - 1) |
@@ -2769,7 +2770,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 		 * followed by BE which DPRX devices are unable to handle.
 		 * https://groups.vesa.org/wg/DP/document/20494
 		 */
-		intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),
+		intel_de_write(display, DP_MIN_HBLANK_CTL(transcoder),
 			       crtc_state->min_hblank);
 	}
 }
-- 
2.29.0

RE: [PATCH v8 04/20] drm/i915/display: Pass target transcoder to intel_set_transcoder_timings()

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Thursday, June 4, 2026 1:24 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v8 04/20] drm/i915/display: Pass target transcoder to
> intel_set_transcoder_timings()
> 
> Let intel_set_transcoder_timings() take the target transcoder as an explicit
> argument instead of always using crtc_state->cpu_transcoder.
> This makes the helper reusable for callers that need to program timings for a
> transcoder other than the CRTC's CPU transcoder.
> 
> Update all existing callers to pass crtc_state->cpu_transcoder so there is no
> functional change.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 35 ++++++++++----------
>  1 file changed, 18 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 8e269b71f18e..9031264a34fc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -132,7 +132,8 @@
>  #include "vlv_dsi_pll.h"
>  #include "vlv_dsi_regs.h"
> 
> -static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
> +static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state,
> +					 enum transcoder transcoder);
>  static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
> static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);  static
> void bdw_set_pipe_misc(struct intel_dsb *dsb, @@ -1504,7 +1505,7 @@ static
> void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
>  					       &crtc_state->dp_m2_n2);
>  	}
> 
> -	intel_set_transcoder_timings(crtc_state);
> +	intel_set_transcoder_timings(crtc_state, crtc_state->cpu_transcoder);
> 
>  	ilk_set_pipeconf(crtc_state);
>  }
> @@ -1635,7 +1636,7 @@ static void hsw_configure_cpu_transcoder(const struct
> intel_crtc_state *crtc_sta
>  					       &crtc_state->dp_m2_n2);
>  	}
> 
> -	intel_set_transcoder_timings(crtc_state);
> +	intel_set_transcoder_timings(crtc_state, crtc_state->cpu_transcoder);
> 
>  	if (cpu_transcoder != TRANSCODER_EDP)
>  		intel_de_write(display, TRANS_MULT(display, cpu_transcoder),
> @@ -2048,7 +2049,7 @@ static void i9xx_configure_cpu_transcoder(const struct
> intel_crtc_state *crtc_st
>  					       &crtc_state->dp_m2_n2);
>  	}
> 
> -	intel_set_transcoder_timings(crtc_state);
> +	intel_set_transcoder_timings(crtc_state, crtc_state->cpu_transcoder);
> 
>  	i9xx_set_pipeconf(crtc_state);
>  }
> @@ -2664,17 +2665,17 @@ transcoder_has_vrr(const struct intel_crtc_state
> *crtc_state)
>  	return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder);
>  }
> 
> -static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
> +static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state,
> +					 enum transcoder transcoder)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum pipe pipe = crtc->pipe;
> -	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	const struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
>  	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
>  	int vsyncshift = 0;
> 
> -	drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
> +	drm_WARN_ON(display->drm, transcoder_is_dsi(transcoder));
> 
>  	/* We need to be careful not to changed the adjusted mode, for otherwise
>  	 * the hw state checker will get angry at the mismatch. */ @@ -2703,7
> +2704,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state
> *crtc_sta
>  	 */
>  	if (DISPLAY_VER(display) >= 13) {
>  		intel_de_write(display,
> -			       TRANS_SET_CONTEXT_LATENCY(display,
> cpu_transcoder),
> +			       TRANS_SET_CONTEXT_LATENCY(display,
> transcoder),
>  			       crtc_state->set_context_latency);
> 
>  		/*
> @@ -2718,16 +2719,16 @@ static void intel_set_transcoder_timings(const struct
> intel_crtc_state *crtc_sta
> 
>  	if (DISPLAY_VER(display) >= 4 && DISPLAY_VER(display) < 35)
>  		intel_de_write(display,
> -			       TRANS_VSYNCSHIFT(display, cpu_transcoder),
> +			       TRANS_VSYNCSHIFT(display, transcoder),
>  			       vsyncshift);
> 
> -	intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
> +	intel_de_write(display, TRANS_HTOTAL(display, transcoder),
>  		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
>  		       HTOTAL(adjusted_mode->crtc_htotal - 1));
> -	intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
> +	intel_de_write(display, TRANS_HBLANK(display, transcoder),
>  		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
>  		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
> -	intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
> +	intel_de_write(display, TRANS_HSYNC(display, transcoder),
>  		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
>  		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
> 
> @@ -2740,13 +2741,13 @@ static void intel_set_transcoder_timings(const struct
> intel_crtc_state *crtc_sta
>  	if (intel_vrr_always_use_vrr_tg(display))
>  		crtc_vtotal = 1;
> 
> -	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
> +	intel_de_write(display, TRANS_VTOTAL(display, transcoder),
>  		       VACTIVE(crtc_vdisplay - 1) |
>  		       VTOTAL(crtc_vtotal - 1));
> -	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
> +	intel_de_write(display, TRANS_VBLANK(display, transcoder),
>  		       VBLANK_START(crtc_vblank_start - 1) |
>  		       VBLANK_END(crtc_vblank_end - 1));
> -	intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
> +	intel_de_write(display, TRANS_VSYNC(display, transcoder),
>  		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
>  		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
> 
> @@ -2754,7 +2755,7 @@ static void intel_set_transcoder_timings(const struct
> intel_crtc_state *crtc_sta
>  	 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This
> is
>  	 * documented on the DDI_FUNC_CTL register description, EDP Input
> Select
>  	 * bits. */
> -	if (display->platform.haswell && cpu_transcoder == TRANSCODER_EDP
> &&
> +	if (display->platform.haswell && transcoder == TRANSCODER_EDP &&
>  	    (pipe == PIPE_B || pipe == PIPE_C))
>  		intel_de_write(display, TRANS_VTOTAL(display, pipe),
>  			       VACTIVE(crtc_vdisplay - 1) |
> @@ -2769,7 +2770,7 @@ static void intel_set_transcoder_timings(const struct
> intel_crtc_state *crtc_sta
>  		 * followed by BE which DPRX devices are unable to handle.
>  		 * https://groups.vesa.org/wg/DP/document/20494
>  		 */
> -		intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),
> +		intel_de_write(display, DP_MIN_HBLANK_CTL(transcoder),
>  			       crtc_state->min_hblank);
>  	}
>  }
> --
> 2.29.0

Re: [PATCH v8 04/20] drm/i915/display: Pass target transcoder to intel_set_transcoder_timings()

[Ville Syrjälä]

On Thu, Jun 04, 2026 at 01:24:00AM +0530, Animesh Manna wrote:
> Let intel_set_transcoder_timings() take the target transcoder as an
> explicit argument instead of always using crtc_state->cpu_transcoder.
> This makes the helper reusable for callers that need to program timings
> for a transcoder other than the CRTC's CPU transcoder.
> 
> Update all existing callers to pass crtc_state->cpu_transcoder so there
> is no functional change.
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 35 ++++++++++----------
>  1 file changed, 18 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 8e269b71f18e..9031264a34fc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -132,7 +132,8 @@
>  #include "vlv_dsi_pll.h"
>  #include "vlv_dsi_regs.h"
>  
> -static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
> +static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state,
> +					 enum transcoder transcoder);
>  static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
>  static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
>  static void bdw_set_pipe_misc(struct intel_dsb *dsb,
> @@ -1504,7 +1505,7 @@ static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
>  					       &crtc_state->dp_m2_n2);
>  	}
>  
> -	intel_set_transcoder_timings(crtc_state);
> +	intel_set_transcoder_timings(crtc_state, crtc_state->cpu_transcoder);
>  
>  	ilk_set_pipeconf(crtc_state);
>  }
> @@ -1635,7 +1636,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
>  					       &crtc_state->dp_m2_n2);
>  	}
>  
> -	intel_set_transcoder_timings(crtc_state);
> +	intel_set_transcoder_timings(crtc_state, crtc_state->cpu_transcoder);
>  
>  	if (cpu_transcoder != TRANSCODER_EDP)
>  		intel_de_write(display, TRANS_MULT(display, cpu_transcoder),
> @@ -2048,7 +2049,7 @@ static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_st
>  					       &crtc_state->dp_m2_n2);
>  	}
>  
> -	intel_set_transcoder_timings(crtc_state);
> +	intel_set_transcoder_timings(crtc_state, crtc_state->cpu_transcoder);
>  
>  	i9xx_set_pipeconf(crtc_state);
>  }
> @@ -2664,17 +2665,17 @@ transcoder_has_vrr(const struct intel_crtc_state *crtc_state)
>  	return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder);
>  }
>  
> -static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
> +static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state,
> +					 enum transcoder transcoder)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum pipe pipe = crtc->pipe;
> -	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>  	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
>  	int vsyncshift = 0;
>  
> -	drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
> +	drm_WARN_ON(display->drm, transcoder_is_dsi(transcoder));

If you want to rename the variable, then do so in a separate patch.
Mixing the rename with other changes is destroying the signal to
noise ratio of the patch.

>  
>  	/* We need to be careful not to changed the adjusted mode, for otherwise
>  	 * the hw state checker will get angry at the mismatch. */
> @@ -2703,7 +2704,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  	 */
>  	if (DISPLAY_VER(display) >= 13) {
>  		intel_de_write(display,
> -			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
> +			       TRANS_SET_CONTEXT_LATENCY(display, transcoder),
>  			       crtc_state->set_context_latency);
>  
>  		/*
> @@ -2718,16 +2719,16 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  
>  	if (DISPLAY_VER(display) >= 4 && DISPLAY_VER(display) < 35)
>  		intel_de_write(display,
> -			       TRANS_VSYNCSHIFT(display, cpu_transcoder),
> +			       TRANS_VSYNCSHIFT(display, transcoder),
>  			       vsyncshift);
>  
> -	intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
> +	intel_de_write(display, TRANS_HTOTAL(display, transcoder),
>  		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
>  		       HTOTAL(adjusted_mode->crtc_htotal - 1));
> -	intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
> +	intel_de_write(display, TRANS_HBLANK(display, transcoder),
>  		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
>  		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
> -	intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
> +	intel_de_write(display, TRANS_HSYNC(display, transcoder),
>  		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
>  		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
>  
> @@ -2740,13 +2741,13 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  	if (intel_vrr_always_use_vrr_tg(display))
>  		crtc_vtotal = 1;
>  
> -	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
> +	intel_de_write(display, TRANS_VTOTAL(display, transcoder),
>  		       VACTIVE(crtc_vdisplay - 1) |
>  		       VTOTAL(crtc_vtotal - 1));
> -	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
> +	intel_de_write(display, TRANS_VBLANK(display, transcoder),
>  		       VBLANK_START(crtc_vblank_start - 1) |
>  		       VBLANK_END(crtc_vblank_end - 1));
> -	intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
> +	intel_de_write(display, TRANS_VSYNC(display, transcoder),
>  		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
>  		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
>  
> @@ -2754,7 +2755,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  	 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
>  	 * documented on the DDI_FUNC_CTL register description, EDP Input Select
>  	 * bits. */
> -	if (display->platform.haswell && cpu_transcoder == TRANSCODER_EDP &&
> +	if (display->platform.haswell && transcoder == TRANSCODER_EDP &&
>  	    (pipe == PIPE_B || pipe == PIPE_C))
>  		intel_de_write(display, TRANS_VTOTAL(display, pipe),
>  			       VACTIVE(crtc_vdisplay - 1) |
> @@ -2769,7 +2770,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  		 * followed by BE which DPRX devices are unable to handle.
>  		 * https://groups.vesa.org/wg/DP/document/20494
>  		 */
> -		intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),
> +		intel_de_write(display, DP_MIN_HBLANK_CTL(transcoder),
>  			       crtc_state->min_hblank);
>  	}
>  }
> -- 
> 2.29.0

-- 
Ville Syrjälä
Intel

[PATCH v8 05/20] drm/i915/display: Skip DP_MIN_HBLANK_CTL programming for CMTG transcoders

[Animesh Manna]

DP_MIN_HBLANK_CTL is a CPU transcoder register and must not be written
for the CMTG transcoders. Skip the programming when the target
transcoder is TRANSCODER_CMTG0 or TRANSCODER_CMTG1.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9031264a34fc..2c15dd4c6d66 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2761,7 +2761,9 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 			       VACTIVE(crtc_vdisplay - 1) |
 			       VTOTAL(crtc_vtotal - 1));
 
-	if (DISPLAY_VER(display) >= 30) {
+	if (DISPLAY_VER(display) >= 30 &&
+	    transcoder != TRANSCODER_CMTG0 &&
+	    transcoder != TRANSCODER_CMTG1) {
 		/*
 		 * Address issues for resolutions with high refresh rate that
 		 * have small Hblank, specifically where Hblank is smaller than
-- 
2.29.0

RE: [PATCH v8 05/20] drm/i915/display: Skip DP_MIN_HBLANK_CTL programming for CMTG transcoders

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Thursday, June 4, 2026 1:24 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v8 05/20] drm/i915/display: Skip DP_MIN_HBLANK_CTL
> programming for CMTG transcoders
> 
> DP_MIN_HBLANK_CTL is a CPU transcoder register and must not be written for
> the CMTG transcoders. Skip the programming when the target transcoder is
> TRANSCODER_CMTG0 or TRANSCODER_CMTG1.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 9031264a34fc..2c15dd4c6d66 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2761,7 +2761,9 @@ static void intel_set_transcoder_timings(const struct
> intel_crtc_state *crtc_sta
>  			       VACTIVE(crtc_vdisplay - 1) |
>  			       VTOTAL(crtc_vtotal - 1));
> 
> -	if (DISPLAY_VER(display) >= 30) {
> +	if (DISPLAY_VER(display) >= 30 &&
> +	    transcoder != TRANSCODER_CMTG0 &&
> +	    transcoder != TRANSCODER_CMTG1) {
>  		/*
>  		 * Address issues for resolutions with high refresh rate that
>  		 * have small Hblank, specifically where Hblank is smaller than
> --
> 2.29.0

[PATCH v8 06/20] drm/i915/display: Pass transcoder to intel_set_transcoder_timings_lrr()

[Animesh Manna]

Make intel_set_transcoder_timings_lrr() take the target transcoder as an
explicit parameter instead of always using crtc_state->cpu_transcoder.
This allows the LRR timing programming sequence to be reused for other
transcoders (e.g. CMTG).

Move the intel_vrr_set_fixed_rr_timings() and intel_vrr_transcoder_enable()
calls out of intel_set_transcoder_timings_lrr() and into its only caller
intel_pipe_fastset(), so the helper now strictly programs the LRR timing
registers for the given transcoder.

No functional change intended.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 22 ++++++++++----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2c15dd4c6d66..17621f66501f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2777,14 +2777,14 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 	}
 }
 
-static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
+static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state,
+					     enum transcoder transcoder)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
 
-	drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
+	drm_WARN_ON(display->drm, transcoder_is_dsi(transcoder));
 
 	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
 	crtc_vtotal = adjusted_mode->crtc_vtotal;
@@ -2799,7 +2799,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
 
 	if (DISPLAY_VER(display) >= 13) {
 		intel_de_write(display,
-			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
+			       TRANS_SET_CONTEXT_LATENCY(display, transcoder),
 			       crtc_state->set_context_latency);
 
 		/*
@@ -2816,7 +2816,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
 	 * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
 	 * But let's write it anyway to keep the state checker happy.
 	 */
-	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
+	intel_de_write(display, TRANS_VBLANK(display, transcoder),
 		       VBLANK_START(crtc_vblank_start - 1) |
 		       VBLANK_END(crtc_vblank_end - 1));
 	/*
@@ -2832,12 +2832,9 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
 	 * The double buffer latch point for TRANS_VTOTAL
 	 * is the transcoder's undelayed vblank.
 	 */
-	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
+	intel_de_write(display, TRANS_VTOTAL(display, transcoder),
 		       VACTIVE(crtc_vdisplay - 1) |
 		       VTOTAL(crtc_vtotal - 1));
-
-	intel_vrr_set_fixed_rr_timings(crtc_state);
-	intel_vrr_transcoder_enable(crtc_state);
 }
 
 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
@@ -6674,8 +6671,11 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
 		intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
 					       &new_crtc_state->dp_m_n);
 
-	if (new_crtc_state->update_lrr)
-		intel_set_transcoder_timings_lrr(new_crtc_state);
+	if (new_crtc_state->update_lrr) {
+		intel_set_transcoder_timings_lrr(new_crtc_state, new_crtc_state->cpu_transcoder);
+		intel_vrr_set_fixed_rr_timings(new_crtc_state);
+		intel_vrr_transcoder_enable(new_crtc_state);
+	}
 }
 
 static void commit_pipe_pre_planes(struct intel_atomic_state *state,
-- 
2.29.0

RE: [PATCH v8 06/20] drm/i915/display: Pass transcoder to intel_set_transcoder_timings_lrr()

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Thursday, June 4, 2026 1:24 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v8 06/20] drm/i915/display: Pass transcoder to
> intel_set_transcoder_timings_lrr()
> 
> Make intel_set_transcoder_timings_lrr() take the target transcoder as an explicit
> parameter instead of always using crtc_state->cpu_transcoder.
> This allows the LRR timing programming sequence to be reused for other
> transcoders (e.g. CMTG).
> 
> Move the intel_vrr_set_fixed_rr_timings() and intel_vrr_transcoder_enable() calls
> out of intel_set_transcoder_timings_lrr() and into its only caller
> intel_pipe_fastset(), so the helper now strictly programs the LRR timing registers
> for the given transcoder.
> 
> No functional change intended.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 22 ++++++++++----------
>  1 file changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 2c15dd4c6d66..17621f66501f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2777,14 +2777,14 @@ static void intel_set_transcoder_timings(const struct
> intel_crtc_state *crtc_sta
>  	}
>  }
> 
> -static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state
> *crtc_state)
> +static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state
> *crtc_state,
> +					     enum transcoder transcoder)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
> -	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	const struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
>  	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
> 
> -	drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
> +	drm_WARN_ON(display->drm, transcoder_is_dsi(transcoder));
> 
>  	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
>  	crtc_vtotal = adjusted_mode->crtc_vtotal; @@ -2799,7 +2799,7 @@
> static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
> 
>  	if (DISPLAY_VER(display) >= 13) {
>  		intel_de_write(display,
> -			       TRANS_SET_CONTEXT_LATENCY(display,
> cpu_transcoder),
> +			       TRANS_SET_CONTEXT_LATENCY(display,
> transcoder),
>  			       crtc_state->set_context_latency);
> 
>  		/*
> @@ -2816,7 +2816,7 @@ static void intel_set_transcoder_timings_lrr(const
> struct intel_crtc_state *crtc
>  	 * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP
> mode.
>  	 * But let's write it anyway to keep the state checker happy.
>  	 */
> -	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
> +	intel_de_write(display, TRANS_VBLANK(display, transcoder),
>  		       VBLANK_START(crtc_vblank_start - 1) |
>  		       VBLANK_END(crtc_vblank_end - 1));
>  	/*
> @@ -2832,12 +2832,9 @@ static void intel_set_transcoder_timings_lrr(const
> struct intel_crtc_state *crtc
>  	 * The double buffer latch point for TRANS_VTOTAL
>  	 * is the transcoder's undelayed vblank.
>  	 */
> -	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
> +	intel_de_write(display, TRANS_VTOTAL(display, transcoder),
>  		       VACTIVE(crtc_vdisplay - 1) |
>  		       VTOTAL(crtc_vtotal - 1));
> -
> -	intel_vrr_set_fixed_rr_timings(crtc_state);
> -	intel_vrr_transcoder_enable(crtc_state);
>  }
> 
>  static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) @@
> -6674,8 +6671,11 @@ static void intel_pipe_fastset(const struct intel_crtc_state
> *old_crtc_state,
>  		intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state-
> >cpu_transcoder,
>  					       &new_crtc_state->dp_m_n);
> 
> -	if (new_crtc_state->update_lrr)
> -		intel_set_transcoder_timings_lrr(new_crtc_state);
> +	if (new_crtc_state->update_lrr) {
> +		intel_set_transcoder_timings_lrr(new_crtc_state, new_crtc_state-
> >cpu_transcoder);
> +		intel_vrr_set_fixed_rr_timings(new_crtc_state);
> +		intel_vrr_transcoder_enable(new_crtc_state);
> +	}
>  }
> 
>  static void commit_pipe_pre_planes(struct intel_atomic_state *state,
> --
> 2.29.0

[PATCH v8 07/20] drm/i915/cmtg: Set timings for CMTG by using transcoder timing helpers

[Animesh Manna]

Expose intel_set_transcoder_timings() & intel_set_transcoder_timings_lrr()
so that they can program timings on any transcoder, and use them from a
new intel_cmtg_set_timings() helper instead of duplicating the timing
register write sequence for CMTG.

intel_cmtg_set_timings() maps the CPU transcoder to the corresponding
CMTG transcoder (TRANSCODER_A->TRANSCODER_CMTG0, TRANSCODER_B->
TRANSCODER_CMTG1) and calls the shared helper, gated by
intel_cmtg_is_allowed(). It is invoked from hsw_configure_cpu_transcoder()
for the full modeset path and from intel_pipe_fastset() for the LRR
update path.

v2:
- Use sw state instead of reading directly from hardware. [Jani]
- Move set_timing later after encoder enable. [Dibin]

v3:
- Replace id with trans. [Jani]
- Program cmtg set_timing() along with primary transcoder timing.

v4:
- Use _MMIO_TRANS() for cmtg registers instead of direct
multiplication. [Jani]

v5:
- Modify register definition approach and match existing
transcoder definition. [Ville]

v6:
- Reuse transcoder timing helpers. [Ville]

Bspec: 68989
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c    | 25 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h    |  1 +
 drivers/gpu/drm/i915/display/intel_display.c | 13 +++++-----
 drivers/gpu/drm/i915/display/intel_display.h |  4 ++++
 4 files changed, 37 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index fbc8a4f2b9cb..082c04bec9ee 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -219,3 +219,28 @@ void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
 	if (clk_sel_set)
 		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
 }
+
+static inline enum transcoder to_cmtg_transcoder(enum transcoder cpu_transcoder)
+{
+	switch (cpu_transcoder) {
+	case TRANSCODER_A:
+		return TRANSCODER_CMTG0;
+	case TRANSCODER_B:
+		return TRANSCODER_CMTG1;
+	default:
+		return INVALID_TRANSCODER;
+	}
+}
+
+void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
+{
+	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	if (lrr)
+		intel_set_transcoder_timings_lrr(crtc_state, cmtg_transcoder);
+	else
+		intel_set_transcoder_timings(crtc_state, cmtg_transcoder);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 87092ce6d67b..53a44f505dd2 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
 void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 17621f66501f..a6a1da4bd98d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -60,6 +60,7 @@
 #include "intel_bw.h"
 #include "intel_cdclk.h"
 #include "intel_clock_gating.h"
+#include "intel_cmtg.h"
 #include "intel_color.h"
 #include "intel_crt.h"
 #include "intel_crtc.h"
@@ -132,8 +133,6 @@
 #include "vlv_dsi_pll.h"
 #include "vlv_dsi_regs.h"
 
-static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state,
-					 enum transcoder transcoder);
 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
 static void bdw_set_pipe_misc(struct intel_dsb *dsb,
@@ -1637,6 +1636,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
 	}
 
 	intel_set_transcoder_timings(crtc_state, crtc_state->cpu_transcoder);
+	intel_cmtg_set_timings(crtc_state, false);
 
 	if (cpu_transcoder != TRANSCODER_EDP)
 		intel_de_write(display, TRANS_MULT(display, cpu_transcoder),
@@ -2665,8 +2665,8 @@ transcoder_has_vrr(const struct intel_crtc_state *crtc_state)
 	return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder);
 }
 
-static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state,
-					 enum transcoder transcoder)
+void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state,
+				  enum transcoder transcoder)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -2777,8 +2777,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 	}
 }
 
-static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state,
-					     enum transcoder transcoder)
+void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state,
+				      enum transcoder transcoder)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
@@ -6673,6 +6673,7 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
 
 	if (new_crtc_state->update_lrr) {
 		intel_set_transcoder_timings_lrr(new_crtc_state, new_crtc_state->cpu_transcoder);
+		intel_cmtg_set_timings(new_crtc_state, true);
 		intel_vrr_set_fixed_rr_timings(new_crtc_state);
 		intel_vrr_transcoder_enable(new_crtc_state);
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 1963dbc80221..ef7e0506f77f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -424,6 +424,10 @@ void intel_set_m_n(struct intel_display *display,
 		   const struct intel_link_m_n *m_n,
 		   intel_reg_t data_m_reg, intel_reg_t data_n_reg,
 		   intel_reg_t link_m_reg, intel_reg_t link_n_reg);
+void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state,
+				  enum transcoder transcoder);
+void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state,
+				      enum transcoder transcoder);
 void intel_get_m_n(struct intel_display *display,
 		   struct intel_link_m_n *m_n,
 		   intel_reg_t data_m_reg, intel_reg_t data_n_reg,
-- 
2.29.0

RE: [PATCH v8 07/20] drm/i915/cmtg: Set timings for CMTG by using transcoder timing helpers

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Thursday, June 4, 2026 1:24 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v8 07/20] drm/i915/cmtg: Set timings for CMTG by using
> transcoder timing helpers
> 
> Expose intel_set_transcoder_timings() & intel_set_transcoder_timings_lrr()
> so that they can program timings on any transcoder, and use them from a new
> intel_cmtg_set_timings() helper instead of duplicating the timing register write
> sequence for CMTG.
> 
> intel_cmtg_set_timings() maps the CPU transcoder to the corresponding CMTG
> transcoder (TRANSCODER_A->TRANSCODER_CMTG0, TRANSCODER_B->
> TRANSCODER_CMTG1) and calls the shared helper, gated by
> intel_cmtg_is_allowed(). It is invoked from hsw_configure_cpu_transcoder() for
> the full modeset path and from intel_pipe_fastset() for the LRR update path.
> 
> v2:
> - Use sw state instead of reading directly from hardware. [Jani]
> - Move set_timing later after encoder enable. [Dibin]
> 
> v3:
> - Replace id with trans. [Jani]
> - Program cmtg set_timing() along with primary transcoder timing.
> 
> v4:
> - Use _MMIO_TRANS() for cmtg registers instead of direct multiplication. [Jani]
> 
> v5:
> - Modify register definition approach and match existing transcoder definition.
> [Ville]
> 
> v6:
> - Reuse transcoder timing helpers. [Ville]
> 
> Bspec: 68989
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c    | 25 ++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_cmtg.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_display.c | 13 +++++-----
> drivers/gpu/drm/i915/display/intel_display.h |  4 ++++
>  4 files changed, 37 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index fbc8a4f2b9cb..082c04bec9ee 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -219,3 +219,28 @@ void intel_cmtg_set_clk_select(const struct
> intel_crtc_state *crtc_state)
>  	if (clk_sel_set)
>  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
> }
> +
> +static inline enum transcoder to_cmtg_transcoder(enum transcoder
> +cpu_transcoder) {
> +	switch (cpu_transcoder) {
> +	case TRANSCODER_A:
> +		return TRANSCODER_CMTG0;
> +	case TRANSCODER_B:
> +		return TRANSCODER_CMTG1;
> +	default:
> +		return INVALID_TRANSCODER;
> +	}
> +}
> +
> +void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state,
> +bool lrr) {
> +	enum transcoder cmtg_transcoder =
> +to_cmtg_transcoder(crtc_state->cpu_transcoder);

This can get INVALID_TRANSCODER, we should add protection for it.
Check below should help, but better to add an explicit check.

> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	if (lrr)
> +		intel_set_transcoder_timings_lrr(crtc_state, cmtg_transcoder);
> +	else
> +		intel_set_transcoder_timings(crtc_state, cmtg_transcoder); }
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 87092ce6d67b..53a44f505dd2 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -11,6 +11,7 @@
>  struct intel_display;
>  struct intel_crtc_state;
> 
> +void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state,
> +bool lrr);
>  void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);  void
> intel_cmtg_sanitize(struct intel_display *display);  bool
> intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state); diff --git
> a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 17621f66501f..a6a1da4bd98d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -60,6 +60,7 @@
>  #include "intel_bw.h"
>  #include "intel_cdclk.h"
>  #include "intel_clock_gating.h"
> +#include "intel_cmtg.h"
>  #include "intel_color.h"
>  #include "intel_crt.h"
>  #include "intel_crtc.h"
> @@ -132,8 +133,6 @@
>  #include "vlv_dsi_pll.h"
>  #include "vlv_dsi_regs.h"
> 
> -static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state,
> -					 enum transcoder transcoder);
>  static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
> static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);  static
> void bdw_set_pipe_misc(struct intel_dsb *dsb, @@ -1637,6 +1636,7 @@ static
> void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
>  	}
> 
>  	intel_set_transcoder_timings(crtc_state, crtc_state->cpu_transcoder);
> +	intel_cmtg_set_timings(crtc_state, false);
> 
>  	if (cpu_transcoder != TRANSCODER_EDP)
>  		intel_de_write(display, TRANS_MULT(display, cpu_transcoder),
> @@ -2665,8 +2665,8 @@ transcoder_has_vrr(const struct intel_crtc_state
> *crtc_state)
>  	return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder);
>  }
> 
> -static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state,
> -					 enum transcoder transcoder)
> +void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state,
> +				  enum transcoder transcoder)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -2777,8 +2777,8 @@ static void intel_set_transcoder_timings(const struct
> intel_crtc_state *crtc_sta
>  	}
>  }
> 
> -static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state
> *crtc_state,
> -					     enum transcoder transcoder)
> +void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state,
> +				      enum transcoder transcoder)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	const struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode; @@ -6673,6 +6673,7 @@ static void
> intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
> 
>  	if (new_crtc_state->update_lrr) {
>  		intel_set_transcoder_timings_lrr(new_crtc_state, new_crtc_state-
> >cpu_transcoder);
> +		intel_cmtg_set_timings(new_crtc_state, true);

Maybe instead of true and false here, an enum with explicit names can be
used as argument.

With above fixed, this is
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>  		intel_vrr_set_fixed_rr_timings(new_crtc_state);
>  		intel_vrr_transcoder_enable(new_crtc_state);
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 1963dbc80221..ef7e0506f77f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -424,6 +424,10 @@ void intel_set_m_n(struct intel_display *display,
>  		   const struct intel_link_m_n *m_n,
>  		   intel_reg_t data_m_reg, intel_reg_t data_n_reg,
>  		   intel_reg_t link_m_reg, intel_reg_t link_n_reg);
> +void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state,
> +				  enum transcoder transcoder);
> +void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state,
> +				      enum transcoder transcoder);
>  void intel_get_m_n(struct intel_display *display,
>  		   struct intel_link_m_n *m_n,
>  		   intel_reg_t data_m_reg, intel_reg_t data_n_reg,
> --
> 2.29.0

[PATCH v8 08/20] drm/i915/vrr: Pass transcoder to intel_vrr_set_fixed_rr_timings()

[Animesh Manna]

Take the target transcoder as an explicit parameter so the helper can
program VRR VMIN/VMAX/FLIPLINE registers for transcoders other than the
crtc_state->cpu_transcoder (e.g. the CMTG transcoder).

No functional change: all existing callers pass crtc_state->cpu_transcoder.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  2 +-
 drivers/gpu/drm/i915/display/intel_vrr.c     | 14 +++++++-------
 drivers/gpu/drm/i915/display/intel_vrr.h     |  5 ++++-
 3 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a6a1da4bd98d..416dea9e0d36 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6674,7 +6674,7 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
 	if (new_crtc_state->update_lrr) {
 		intel_set_transcoder_timings_lrr(new_crtc_state, new_crtc_state->cpu_transcoder);
 		intel_cmtg_set_timings(new_crtc_state, true);
-		intel_vrr_set_fixed_rr_timings(new_crtc_state);
+		intel_vrr_set_fixed_rr_timings(new_crtc_state, new_crtc_state->cpu_transcoder);
 		intel_vrr_transcoder_enable(new_crtc_state);
 	}
 }
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index e03b5daac5be..15d22de66d63 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -318,19 +318,19 @@ int intel_vrr_fixed_rr_hw_flipline(const struct intel_crtc_state *crtc_state)
 	return intel_vrr_fixed_rr_hw_vtotal(crtc_state);
 }
 
-void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
+void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state,
+				    enum transcoder transcoder)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
 	if (!intel_vrr_possible(crtc_state))
 		return;
 
-	intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
+	intel_de_write(display, TRANS_VRR_VMIN(display, transcoder),
 		       intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1);
-	intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
+	intel_de_write(display, TRANS_VRR_VMAX(display, transcoder),
 		       intel_vrr_fixed_rr_hw_vmax(crtc_state) - 1);
-	intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
+	intel_de_write(display, TRANS_VRR_FLIPLINE(display, transcoder),
 		       intel_vrr_fixed_rr_hw_flipline(crtc_state) - 1);
 }
 
@@ -645,7 +645,7 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 			       lower_32_bits(crtc_state->cmrr.cmrr_n));
 	}
 
-	intel_vrr_set_fixed_rr_timings(crtc_state);
+	intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
 
 	if (!intel_vrr_always_use_vrr_tg(display))
 		intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
@@ -974,7 +974,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 		intel_vrr_tg_disable(old_crtc_state);
 
 	intel_vrr_disable_dc_balancing(old_crtc_state);
-	intel_vrr_set_fixed_rr_timings(old_crtc_state);
+	intel_vrr_set_fixed_rr_timings(old_crtc_state, old_crtc_state->cpu_transcoder);
 }
 
 void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 4f16ca4af91f..2daba0c16162 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -8,6 +8,8 @@
 
 #include <linux/types.h>
 
+#include "intel_display_limits.h"
+
 struct drm_connector_state;
 struct intel_atomic_state;
 struct intel_connector;
@@ -42,7 +44,8 @@ int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state);
 bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state);
 void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state);
 void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
-void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
+void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state,
+				    enum transcoder transcoder);
 void intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
 			 struct intel_crtc *crtc);
 bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
-- 
2.29.0

Re: [PATCH v8 08/20] drm/i915/vrr: Pass transcoder to intel_vrr_set_fixed_rr_timings()

[Jani Nikula]

On Thu, 04 Jun 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index 4f16ca4af91f..2daba0c16162 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -8,6 +8,8 @@
>  
>  #include <linux/types.h>
>  
> +#include "intel_display_limits.h"

Don't include headers from headers if it can be avoided.

> +
>  struct drm_connector_state;
>  struct intel_atomic_state;
>  struct intel_connector;
> @@ -42,7 +44,8 @@ int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state);
>  bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state);
>  void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state);
>  void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
> -void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
> +void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state,
> +				    enum transcoder transcoder);
>  void intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
>  			 struct intel_crtc *crtc);
>  bool intel_vrr_always_use_vrr_tg(struct intel_display *display);

-- 
Jani Nikula, Intel

RE: [PATCH v8 08/20] drm/i915/vrr: Pass transcoder to intel_vrr_set_fixed_rr_timings()

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Thursday, June 4, 2026 1:24 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v8 08/20] drm/i915/vrr: Pass transcoder to
> intel_vrr_set_fixed_rr_timings()
> 
> Take the target transcoder as an explicit parameter so the helper can program
> VRR VMIN/VMAX/FLIPLINE registers for transcoders other than the crtc_state-
> >cpu_transcoder (e.g. the CMTG transcoder).
> 
> No functional change: all existing callers pass crtc_state->cpu_transcoder.
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  2 +-
>  drivers/gpu/drm/i915/display/intel_vrr.c     | 14 +++++++-------
>  drivers/gpu/drm/i915/display/intel_vrr.h     |  5 ++++-
>  3 files changed, 12 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index a6a1da4bd98d..416dea9e0d36 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6674,7 +6674,7 @@ static void intel_pipe_fastset(const struct
> intel_crtc_state *old_crtc_state,
>  	if (new_crtc_state->update_lrr) {
>  		intel_set_transcoder_timings_lrr(new_crtc_state, new_crtc_state-
> >cpu_transcoder);
>  		intel_cmtg_set_timings(new_crtc_state, true);
> -		intel_vrr_set_fixed_rr_timings(new_crtc_state);
> +		intel_vrr_set_fixed_rr_timings(new_crtc_state,
> +new_crtc_state->cpu_transcoder);
>  		intel_vrr_transcoder_enable(new_crtc_state);
>  	}
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index e03b5daac5be..15d22de66d63 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -318,19 +318,19 @@ int intel_vrr_fixed_rr_hw_flipline(const struct
> intel_crtc_state *crtc_state)
>  	return intel_vrr_fixed_rr_hw_vtotal(crtc_state);
>  }
> 
> -void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
> +void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state,
> +				    enum transcoder transcoder)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
> -	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> 
>  	if (!intel_vrr_possible(crtc_state))
>  		return;
> 
> -	intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
> +	intel_de_write(display, TRANS_VRR_VMIN(display, transcoder),
>  		       intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1);
> -	intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
> +	intel_de_write(display, TRANS_VRR_VMAX(display, transcoder),
>  		       intel_vrr_fixed_rr_hw_vmax(crtc_state) - 1);
> -	intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
> +	intel_de_write(display, TRANS_VRR_FLIPLINE(display, transcoder),
>  		       intel_vrr_fixed_rr_hw_flipline(crtc_state) - 1);  }
> 
> @@ -645,7 +645,7 @@ void intel_vrr_set_transcoder_timings(const struct
> intel_crtc_state *crtc_state)
>  			       lower_32_bits(crtc_state->cmrr.cmrr_n));
>  	}
> 
> -	intel_vrr_set_fixed_rr_timings(crtc_state);
> +	intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
> 
>  	if (!intel_vrr_always_use_vrr_tg(display))
>  		intel_de_write(display, TRANS_VRR_CTL(display,
> cpu_transcoder), @@ -974,7 +974,7 @@ void intel_vrr_disable(const struct
> intel_crtc_state *old_crtc_state)
>  		intel_vrr_tg_disable(old_crtc_state);
> 
>  	intel_vrr_disable_dc_balancing(old_crtc_state);
> -	intel_vrr_set_fixed_rr_timings(old_crtc_state);
> +	intel_vrr_set_fixed_rr_timings(old_crtc_state,
> +old_crtc_state->cpu_transcoder);
>  }
> 
>  void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state) diff --
> git a/drivers/gpu/drm/i915/display/intel_vrr.h
> b/drivers/gpu/drm/i915/display/intel_vrr.h
> index 4f16ca4af91f..2daba0c16162 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -8,6 +8,8 @@
> 
>  #include <linux/types.h>
> 
> +#include "intel_display_limits.h"
> +

As Jani pointed, move this include out of the header.
Else all looks Good to me.

Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>  struct drm_connector_state;
>  struct intel_atomic_state;
>  struct intel_connector;
> @@ -42,7 +44,8 @@ int intel_vrr_vmin_vblank_start(const struct intel_crtc_state
> *crtc_state);  bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state);
> void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state);  void
> intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state); -void
> intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
> +void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state,
> +				    enum transcoder transcoder);
>  void intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
>  			 struct intel_crtc *crtc);
>  bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
> --
> 2.29.0

[PATCH v8 09/20] drm/i915/cmtg: Program VRR fixed-rate timings for CMTG transcoder

[Animesh Manna]

Program the VRR registers of CMTG, as the VRR timing generator
will always be enabled for NVL.

Add intel_cmtg_set_vrr_timings() which mirrors the per-transcoder
VRR VMIN/VMAX/FLIPLINE programming on the CMTG transcoder paired
with the pipe's cpu_transcoder.

Invoke it from intel_vrr_set_transcoder_timings() and from the LRR
fastset path, right after the existing intel_vrr_set_fixed_rr_timings()
calls, so the CMTG VRR timing registers stay in sync with the
cpu_transcoder's.

v2: Use sw state instead of reading from hardware. [Jani]
v3: Program cmtg vrr timing registers along with vrr transcoder registers.
v4: Reuse vrr timing programming helper.

Bspec: 68989
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c    | 11 +++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h    |  1 +
 drivers/gpu/drm/i915/display/intel_display.c |  1 +
 drivers/gpu/drm/i915/display/intel_vrr.c     |  2 ++
 4 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 082c04bec9ee..4c8187ddef1f 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -16,6 +16,7 @@
 #include "intel_display_power.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
+#include "intel_vrr.h"
 
 /**
  * DOC: Common Primary Timing Generator (CMTG)
@@ -244,3 +245,13 @@ void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
 	else
 		intel_set_transcoder_timings(crtc_state, cmtg_transcoder);
 }
+
+void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state)
+{
+	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	intel_vrr_set_fixed_rr_timings(crtc_state, cmtg_transcoder);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 53a44f505dd2..899a2744514c 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
 void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 416dea9e0d36..56769a2c7f72 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6675,6 +6675,7 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
 		intel_set_transcoder_timings_lrr(new_crtc_state, new_crtc_state->cpu_transcoder);
 		intel_cmtg_set_timings(new_crtc_state, true);
 		intel_vrr_set_fixed_rr_timings(new_crtc_state, new_crtc_state->cpu_transcoder);
+		intel_cmtg_set_vrr_timings(new_crtc_state);
 		intel_vrr_transcoder_enable(new_crtc_state);
 	}
 }
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 15d22de66d63..2295f6545981 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -7,6 +7,7 @@
 #include <drm/drm_print.h>
 
 #include "intel_alpm.h"
+#include "intel_cmtg.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
@@ -646,6 +647,7 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 	}
 
 	intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
+	intel_cmtg_set_vrr_timings(crtc_state);
 
 	if (!intel_vrr_always_use_vrr_tg(display))
 		intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
-- 
2.29.0

RE: [PATCH v8 09/20] drm/i915/cmtg: Program VRR fixed-rate timings for CMTG transcoder

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Thursday, June 4, 2026 1:24 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v8 09/20] drm/i915/cmtg: Program VRR fixed-rate timings for
> CMTG transcoder
> 
> Program the VRR registers of CMTG, as the VRR timing generator will always be
> enabled for NVL.
> 
> Add intel_cmtg_set_vrr_timings() which mirrors the per-transcoder VRR
> VMIN/VMAX/FLIPLINE programming on the CMTG transcoder paired with the
> pipe's cpu_transcoder.
> 
> Invoke it from intel_vrr_set_transcoder_timings() and from the LRR fastset path,
> right after the existing intel_vrr_set_fixed_rr_timings() calls, so the CMTG VRR
> timing registers stay in sync with the cpu_transcoder's.
> 
> v2: Use sw state instead of reading from hardware. [Jani]
> v3: Program cmtg vrr timing registers along with vrr transcoder registers.
> v4: Reuse vrr timing programming helper.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Bspec: 68989
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c    | 11 +++++++++++
>  drivers/gpu/drm/i915/display/intel_cmtg.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_display.c |  1 +
>  drivers/gpu/drm/i915/display/intel_vrr.c     |  2 ++
>  4 files changed, 15 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 082c04bec9ee..4c8187ddef1f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -16,6 +16,7 @@
>  #include "intel_display_power.h"
>  #include "intel_display_regs.h"
>  #include "intel_display_types.h"
> +#include "intel_vrr.h"
> 
>  /**
>   * DOC: Common Primary Timing Generator (CMTG) @@ -244,3 +245,13 @@
> void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
>  	else
>  		intel_set_transcoder_timings(crtc_state, cmtg_transcoder);  }
> +
> +void intel_cmtg_set_vrr_timings(const struct intel_crtc_state
> +*crtc_state) {
> +	enum transcoder cmtg_transcoder =
> +to_cmtg_transcoder(crtc_state->cpu_transcoder);
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	intel_vrr_set_fixed_rr_timings(crtc_state, cmtg_transcoder); }
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 53a44f505dd2..899a2744514c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -11,6 +11,7 @@
>  struct intel_display;
>  struct intel_crtc_state;
> 
> +void intel_cmtg_set_vrr_timings(const struct intel_crtc_state
> +*crtc_state);
>  void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
> void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);  void
> intel_cmtg_sanitize(struct intel_display *display); diff --git
> a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 416dea9e0d36..56769a2c7f72 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6675,6 +6675,7 @@ static void intel_pipe_fastset(const struct
> intel_crtc_state *old_crtc_state,
>  		intel_set_transcoder_timings_lrr(new_crtc_state, new_crtc_state-
> >cpu_transcoder);
>  		intel_cmtg_set_timings(new_crtc_state, true);
>  		intel_vrr_set_fixed_rr_timings(new_crtc_state, new_crtc_state-
> >cpu_transcoder);
> +		intel_cmtg_set_vrr_timings(new_crtc_state);
>  		intel_vrr_transcoder_enable(new_crtc_state);
>  	}
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 15d22de66d63..2295f6545981 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -7,6 +7,7 @@
>  #include <drm/drm_print.h>
> 
>  #include "intel_alpm.h"
> +#include "intel_cmtg.h"
>  #include "intel_crtc.h"
>  #include "intel_de.h"
>  #include "intel_display_regs.h"
> @@ -646,6 +647,7 @@ void intel_vrr_set_transcoder_timings(const struct
> intel_crtc_state *crtc_state)
>  	}
> 
>  	intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
> +	intel_cmtg_set_vrr_timings(crtc_state);
> 
>  	if (!intel_vrr_always_use_vrr_tg(display))
>  		intel_de_write(display, TRANS_VRR_CTL(display,
> cpu_transcoder),
> --
> 2.29.0

[PATCH v8 10/20] drm/i915/cmtg: Program VRR control register for CMTG transcoder

[Animesh Manna]

Add intel_cmtg_set_vrr_ctl() to program TRANS_VRR_CTL for the
CMTG transcoder. Purposefully avoid using the existing VRR enable
path, as many of its operations are not needed for CMTG.

v2: Use sw state instead of reading from hardware. [Jani]
v3: Program cmtg vrr control register along with vrr transcoder
registers. [R-b from Uma]
v4: Split out from vrr timing registers programming.

Bspec: 68989
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c | 20 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h |  1 +
 drivers/gpu/drm/i915/display/intel_vrr.c  |  2 ++
 3 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 4c8187ddef1f..12f6ef4de0e9 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -17,6 +17,7 @@
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
 #include "intel_vrr.h"
+#include "intel_vrr_regs.h"
 
 /**
  * DOC: Common Primary Timing Generator (CMTG)
@@ -255,3 +256,22 @@ void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state)
 
 	intel_vrr_set_fixed_rr_timings(crtc_state, cmtg_transcoder);
 }
+
+void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
+	u32 vrr_ctl;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	vrr_ctl = VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN |
+		  XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
+
+	/* TODO: The code below may need to be revisited once CMRR is enabled */
+	if (crtc_state->cmrr.enable)
+		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
+
+	intel_de_write(display, TRANS_VRR_CTL(display, cmtg_transcoder), vrr_ctl);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 899a2744514c..c92e3a62ff0d 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -12,6 +12,7 @@ struct intel_display;
 struct intel_crtc_state;
 
 void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
 void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 2295f6545981..d4a2645cd380 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -932,6 +932,8 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
 		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
 
 	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
+
+	intel_cmtg_set_vrr_ctl(crtc_state);
 }
 
 static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
-- 
2.29.0

RE: [PATCH v8 10/20] drm/i915/cmtg: Program VRR control register for CMTG transcoder

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Thursday, June 4, 2026 1:24 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v8 10/20] drm/i915/cmtg: Program VRR control register for
> CMTG transcoder
> 
> Add intel_cmtg_set_vrr_ctl() to program TRANS_VRR_CTL for the CMTG
> transcoder. Purposefully avoid using the existing VRR enable path, as many of its
> operations are not needed for CMTG.
> 
> v2: Use sw state instead of reading from hardware. [Jani]
> v3: Program cmtg vrr control register along with vrr transcoder registers. [R-b
> from Uma]
> v4: Split out from vrr timing registers programming.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Bspec: 68989
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c | 20 ++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_cmtg.h |  1 +
> drivers/gpu/drm/i915/display/intel_vrr.c  |  2 ++
>  3 files changed, 23 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 4c8187ddef1f..12f6ef4de0e9 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -17,6 +17,7 @@
>  #include "intel_display_regs.h"
>  #include "intel_display_types.h"
>  #include "intel_vrr.h"
> +#include "intel_vrr_regs.h"
> 
>  /**
>   * DOC: Common Primary Timing Generator (CMTG) @@ -255,3 +256,22 @@
> void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state)
> 
>  	intel_vrr_set_fixed_rr_timings(crtc_state, cmtg_transcoder);  }
> +
> +void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state-
> >cpu_transcoder);
> +	u32 vrr_ctl;
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	vrr_ctl = VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN |
> +		  XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state-
> >vrr.guardband);
> +
> +	/* TODO: The code below may need to be revisited once CMRR is
> enabled */
> +	if (crtc_state->cmrr.enable)
> +		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
> +
> +	intel_de_write(display, TRANS_VRR_CTL(display, cmtg_transcoder),
> +vrr_ctl); }
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 899a2744514c..c92e3a62ff0d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -12,6 +12,7 @@ struct intel_display;
>  struct intel_crtc_state;
> 
>  void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
> +void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);
>  void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
> void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);  void
> intel_cmtg_sanitize(struct intel_display *display); diff --git
> a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 2295f6545981..d4a2645cd380 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -932,6 +932,8 @@ static void intel_vrr_tg_enable(const struct
> intel_crtc_state *crtc_state,
>  		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
> 
>  	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> vrr_ctl);
> +
> +	intel_cmtg_set_vrr_ctl(crtc_state);
>  }
> 
>  static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
> --
> 2.29.0

[PATCH v8 11/20] drm/i915/cmtg: Set link M/N for CMTG transcoder

[Animesh Manna]

Program CMTG link M/N.
Not much to reuse so add a separate function for CMTG.

Bspec: 68989
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c    | 13 +++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h    |  1 +
 drivers/gpu/drm/i915/display/intel_display.c |  5 ++++-
 3 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 12f6ef4de0e9..94215f455471 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -275,3 +275,16 @@ void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
 
 	intel_de_write(display, TRANS_VRR_CTL(display, cmtg_transcoder), vrr_ctl);
 }
+
+void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
+	const struct intel_link_m_n *m_n = &crtc_state->dp_m_n;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	intel_de_write(display, PIPE_LINK_M1(display, cmtg_transcoder), m_n->link_m);
+	intel_de_write(display, PIPE_LINK_N1(display, cmtg_transcoder), m_n->link_n);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index c92e3a62ff0d..6796eb727eef 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 56769a2c7f72..e4763ac81c39 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1635,6 +1635,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
 					       &crtc_state->dp_m2_n2);
 	}
 
+	intel_cmtg_set_m_n(crtc_state);
 	intel_set_transcoder_timings(crtc_state, crtc_state->cpu_transcoder);
 	intel_cmtg_set_timings(crtc_state, false);
 
@@ -6667,9 +6668,11 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
 	    display->platform.broadwell || display->platform.haswell)
 		hsw_set_linetime_wm(new_crtc_state);
 
-	if (new_crtc_state->update_m_n)
+	if (new_crtc_state->update_m_n) {
 		intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
 					       &new_crtc_state->dp_m_n);
+		intel_cmtg_set_m_n(new_crtc_state);
+	}
 
 	if (new_crtc_state->update_lrr) {
 		intel_set_transcoder_timings_lrr(new_crtc_state, new_crtc_state->cpu_transcoder);
-- 
2.29.0

[PATCH v8 12/20] drm/i915/cmtg: Add hook to enable CMTG with sync to port

[Animesh Manna]

Add a hook to enable CMTG by programming CMTG CTL with Sync to Port.
When CMTG starts running, the Sync to Port bit will be cleared. Add
a wait to check its running status and trigger WARN_ON() on timeout.

Bspec: 69088
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 27 ++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  7 +++--
 3 files changed, 29 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 94215f455471..5780a48363e4 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -105,11 +105,11 @@ static void intel_cmtg_get_config(struct intel_display *display,
 {
 	u32 val;
 
-	val = intel_de_read(display, TRANS_CMTG_CTL_A);
+	val = intel_de_read(display, TRANS_CMTG_CTL(TRANSCODER_A));
 	cmtg_config->cmtg_a_enable = val & CMTG_ENABLE;
 
 	if (intel_cmtg_has_cmtg_b(display)) {
-		val = intel_de_read(display, TRANS_CMTG_CTL_B);
+		val = intel_de_read(display, TRANS_CMTG_CTL(TRANSCODER_B));
 		cmtg_config->cmtg_b_enable = val & CMTG_ENABLE;
 	}
 
@@ -142,14 +142,14 @@ static void intel_cmtg_disable(struct intel_display *display,
 
 	if (cmtg_config->cmtg_a_enable) {
 		drm_dbg_kms(display->drm, "Disabling CMTG A\n");
-		intel_de_rmw(display, TRANS_CMTG_CTL_A, CMTG_ENABLE, 0);
+		intel_de_rmw(display, TRANS_CMTG_CTL(TRANSCODER_A), CMTG_ENABLE, 0);
 		clk_sel_clr |= CMTG_CLK_SEL_A_MASK;
 		clk_sel_set |= CMTG_CLK_SEL_A_DISABLED;
 	}
 
 	if (cmtg_config->cmtg_b_enable) {
 		drm_dbg_kms(display->drm, "Disabling CMTG B\n");
-		intel_de_rmw(display, TRANS_CMTG_CTL_B, CMTG_ENABLE, 0);
+		intel_de_rmw(display, TRANS_CMTG_CTL(TRANSCODER_B), CMTG_ENABLE, 0);
 		clk_sel_clr |= CMTG_CLK_SEL_B_MASK;
 		clk_sel_set |= CMTG_CLK_SEL_B_DISABLED;
 	}
@@ -288,3 +288,22 @@ void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state)
 	intel_de_write(display, PIPE_LINK_M1(display, cmtg_transcoder), m_n->link_m);
 	intel_de_write(display, PIPE_LINK_N1(display, cmtg_transcoder), m_n->link_n);
 }
+
+void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 cmtg_ctl;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	cmtg_ctl = CMTG_SYNC_TO_PORT | CMTG_ENABLE;
+
+	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), 0, cmtg_ctl);
+	if (intel_de_wait_for_clear_ms(display, TRANS_CMTG_CTL(cpu_transcoder),
+				       CMTG_SYNC_TO_PORT, 50)) {
+		drm_WARN(display->drm, 1, "CMTG: %s enable timeout\n",
+			 transcoder_name(cpu_transcoder));
+	}
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 6796eb727eef..64ff6a19948a 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 4a80b88d88fd..a93236bf7b75 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -16,8 +16,11 @@
 #define CMTG_CLK_SELECT_PHYB_ENABLE	REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0x6)
 #define CMTG_CLK_SEL_B_DISABLED		REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
 
-#define TRANS_CMTG_CTL_A		_MMIO(0x6fa88)
-#define TRANS_CMTG_CTL_B		_MMIO(0x6fb88)
+#define _TRANS_CMTG_CTL_A		0x6fa88
+#define _TRANS_CMTG_CTL_B		0x6fb88
+#define TRANS_CMTG_CTL(trans)		_MMIO_TRANS((trans), \
+						    _TRANS_CMTG_CTL_A, _TRANS_CMTG_CTL_B)
 #define  CMTG_ENABLE			REG_BIT(31)
+#define  CMTG_SYNC_TO_PORT		REG_BIT(29)
 
 #endif /* __INTEL_CMTG_REGS_H__ */
-- 
2.29.0

[PATCH v8 13/20] drm/i915/cmtg: Add a hook to make eDP transcoder secondary

[Animesh Manna]

Program DDI_FUNC_CTL2 to configure the eDP transcoder as secondary
to the CMTG transcoder.

v2:
- Update commit header to be more clear. [Uma]

Bspec: 68915
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c          | 14 ++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h          |  1 +
 drivers/gpu/drm/i915/display/intel_display_types.h |  4 ++++
 3 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 5780a48363e4..077653e2f599 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -307,3 +307,17 @@ void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
 			 transcoder_name(cpu_transcoder));
 	}
 }
+
+void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0, CMTG_SECONDARY_MODE);
+	crtc->cmtg.enabled = true;
+	drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 64ff6a19948a..12abbafa7d08 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c21e0c0ef0b1..7ae212efb366 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1573,6 +1573,10 @@ struct intel_crtc {
 #endif
 
 	bool vblank_psr_notify;
+
+	struct {
+		bool enabled;
+	} cmtg;
 };
 
 struct intel_plane_error {
-- 
2.29.0

[PATCH v8 14/20] drm/i915/cmtg: Modify existing hook to disable CMTG

[Animesh Manna]

From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>

Earlier cmtg_disable() used to disable all instances of CMTG
which cannot handle individual request for specific CMTG instance.
Introduce cmtg_disable_all() which will disable all cmtg instances
and cmtg_disable() only disable specific instance.

v2:
- Use intel_de_rmw to simplify. [Uma]

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 62 ++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  1 +
 3 files changed, 49 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 077653e2f599..20b74c2856c4 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -83,6 +83,18 @@ static void intel_cmtg_dump_config(struct intel_display *display,
 		    str_yes_no(cmtg_config->trans_b_secondary));
 }
 
+static inline enum transcoder to_cmtg_transcoder(enum transcoder cpu_transcoder)
+{
+	switch (cpu_transcoder) {
+	case TRANSCODER_A:
+		return TRANSCODER_CMTG0;
+	case TRANSCODER_B:
+		return TRANSCODER_CMTG1;
+	default:
+		return INVALID_TRANSCODER;
+	}
+}
+
 static bool intel_cmtg_transcoder_is_secondary(struct intel_display *display,
 					       enum transcoder trans)
 {
@@ -126,8 +138,8 @@ static bool intel_cmtg_disable_requires_modeset(struct intel_display *display,
 	return cmtg_config->trans_a_secondary || cmtg_config->trans_b_secondary;
 }
 
-static void intel_cmtg_disable(struct intel_display *display,
-			       struct intel_cmtg_config *cmtg_config)
+static void intel_cmtg_disable_all(struct intel_display *display,
+				   struct intel_cmtg_config *cmtg_config)
 {
 	u32 clk_sel_clr = 0;
 	u32 clk_sel_set = 0;
@@ -158,6 +170,38 @@ static void intel_cmtg_disable(struct intel_display *display,
 		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
 }
 
+void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
+	u32 clk_sel_clr = 0;
+
+	if (!crtc->cmtg.enabled)
+		return;
+
+	crtc->cmtg.enabled = false;
+	intel_de_rmw(display, TRANS_VRR_CTL(display, cmtg_transcoder),
+		     VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN, 0);
+
+	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),
+		     CMTG_SECONDARY_MODE, 0);
+
+	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_ENABLE, 0);
+
+	if (intel_de_wait_for_clear_ms(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_STATE, 50)) {
+		drm_WARN(display->drm, 1, "CMTG: %s disable timeout\n",
+			 transcoder_name(cpu_transcoder));
+		return;
+	}
+
+	clk_sel_clr = cpu_transcoder == TRANSCODER_A ? CMTG_CLK_SEL_A_MASK : CMTG_CLK_SEL_B_MASK;
+	intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, 0);
+
+	drm_dbg_kms(display->drm, "CMTG: %s disabled\n", transcoder_name(cpu_transcoder));
+}
+
 /*
  * Read out CMTG configuration and, on platforms that allow disabling it without
  * a modeset, do it.
@@ -185,7 +229,7 @@ void intel_cmtg_sanitize(struct intel_display *display)
 	if (intel_cmtg_disable_requires_modeset(display, &cmtg_config))
 		return;
 
-	intel_cmtg_disable(display, &cmtg_config);
+	intel_cmtg_disable_all(display, &cmtg_config);
 }
 
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
@@ -222,18 +266,6 @@ void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
 		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
 }
 
-static inline enum transcoder to_cmtg_transcoder(enum transcoder cpu_transcoder)
-{
-	switch (cpu_transcoder) {
-	case TRANSCODER_A:
-		return TRANSCODER_CMTG0;
-	case TRANSCODER_B:
-		return TRANSCODER_CMTG1;
-	default:
-		return INVALID_TRANSCODER;
-	}
-}
-
 void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
 {
 	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 12abbafa7d08..79785afccc51 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_disable(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index a93236bf7b75..240a02cd4a3a 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -22,5 +22,6 @@
 						    _TRANS_CMTG_CTL_A, _TRANS_CMTG_CTL_B)
 #define  CMTG_ENABLE			REG_BIT(31)
 #define  CMTG_SYNC_TO_PORT		REG_BIT(29)
+#define  CMTG_STATE			REG_BIT(23)
 
 #endif /* __INTEL_CMTG_REGS_H__ */
-- 
2.29.0

RE: [PATCH v8 14/20] drm/i915/cmtg: Modify existing hook to disable CMTG

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Thursday, June 4, 2026 1:24 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v8 14/20] drm/i915/cmtg: Modify existing hook to disable CMTG
> 
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> 
> Earlier cmtg_disable() used to disable all instances of CMTG which cannot handle
> individual request for specific CMTG instance.
> Introduce cmtg_disable_all() which will disable all cmtg instances and
> cmtg_disable() only disable specific instance.
> 
> v2:
> - Use intel_de_rmw to simplify. [Uma]
> 
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c     | 62 ++++++++++++++-----
>  drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
>  .../gpu/drm/i915/display/intel_cmtg_regs.h    |  1 +
>  3 files changed, 49 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 077653e2f599..20b74c2856c4 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -83,6 +83,18 @@ static void intel_cmtg_dump_config(struct intel_display
> *display,
>  		    str_yes_no(cmtg_config->trans_b_secondary));
>  }
> 
> +static inline enum transcoder to_cmtg_transcoder(enum transcoder
> +cpu_transcoder) {
> +	switch (cpu_transcoder) {
> +	case TRANSCODER_A:
> +		return TRANSCODER_CMTG0;
> +	case TRANSCODER_B:
> +		return TRANSCODER_CMTG1;
> +	default:
> +		return INVALID_TRANSCODER;
> +	}
> +}

This seems to be already defined in patch 7, drop this duplicate.

>  static bool intel_cmtg_transcoder_is_secondary(struct intel_display *display,
>  					       enum transcoder trans)
>  {
> @@ -126,8 +138,8 @@ static bool intel_cmtg_disable_requires_modeset(struct
> intel_display *display,
>  	return cmtg_config->trans_a_secondary || cmtg_config-
> >trans_b_secondary;  }
> 
> -static void intel_cmtg_disable(struct intel_display *display,
> -			       struct intel_cmtg_config *cmtg_config)
> +static void intel_cmtg_disable_all(struct intel_display *display,
> +				   struct intel_cmtg_config *cmtg_config)
>  {
>  	u32 clk_sel_clr = 0;
>  	u32 clk_sel_set = 0;
> @@ -158,6 +170,38 @@ static void intel_cmtg_disable(struct intel_display
> *display,
>  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
> }
> 
> +void intel_cmtg_disable(const struct intel_crtc_state *crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state-
> >cpu_transcoder);
> +	u32 clk_sel_clr = 0;
> +
> +	if (!crtc->cmtg.enabled)
> +		return;
> +
> +	crtc->cmtg.enabled = false;
> +	intel_de_rmw(display, TRANS_VRR_CTL(display, cmtg_transcoder),
> +		     VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN, 0);
> +
> +	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display,
> cpu_transcoder),
> +		     CMTG_SECONDARY_MODE, 0);
> +
> +	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder),
> CMTG_ENABLE, 0);

Should it not be cmtg_transcoder ?

> +
> +	if (intel_de_wait_for_clear_ms(display,
> TRANS_CMTG_CTL(cpu_transcoder), CMTG_STATE, 50)) {
> +		drm_WARN(display->drm, 1, "CMTG: %s disable timeout\n",
> +			 transcoder_name(cpu_transcoder));


Can you add a comment explaining which transcoder is referred here cpu_transcoder or
cmtg_transcoder and why.

> +		return;
> +	}
> +
> +	clk_sel_clr = cpu_transcoder == TRANSCODER_A ?
> CMTG_CLK_SEL_A_MASK : CMTG_CLK_SEL_B_MASK;
> +	intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, 0);
> +
> +	drm_dbg_kms(display->drm, "CMTG: %s disabled\n",
> +transcoder_name(cpu_transcoder)); }
> +
>  /*
>   * Read out CMTG configuration and, on platforms that allow disabling it without
>   * a modeset, do it.
> @@ -185,7 +229,7 @@ void intel_cmtg_sanitize(struct intel_display *display)
>  	if (intel_cmtg_disable_requires_modeset(display, &cmtg_config))
>  		return;
> 
> -	intel_cmtg_disable(display, &cmtg_config);
> +	intel_cmtg_disable_all(display, &cmtg_config);
>  }
> 
>  bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state) @@ -222,18
> +266,6 @@ void intel_cmtg_set_clk_select(const struct intel_crtc_state
> *crtc_state)
>  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
> }
> 
> -static inline enum transcoder to_cmtg_transcoder(enum transcoder
> cpu_transcoder) -{
> -	switch (cpu_transcoder) {
> -	case TRANSCODER_A:
> -		return TRANSCODER_CMTG0;
> -	case TRANSCODER_B:
> -		return TRANSCODER_CMTG1;
> -	default:
> -		return INVALID_TRANSCODER;
> -	}
> -}

Oh this is moved up, but this is unnecessary change part of same series, handle it gracefully instead
of moving across the patches.

> -
>  void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)  {
>  	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state-
> >cpu_transcoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 12abbafa7d08..79785afccc51 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -11,6 +11,7 @@
>  struct intel_display;
>  struct intel_crtc_state;
> 
> +void intel_cmtg_disable(const struct intel_crtc_state *crtc_state);
>  void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state);  void
> intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);  void
> intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state); diff --git
> a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index a93236bf7b75..240a02cd4a3a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -22,5 +22,6 @@
>  						    _TRANS_CMTG_CTL_A,
> _TRANS_CMTG_CTL_B)
>  #define  CMTG_ENABLE			REG_BIT(31)
>  #define  CMTG_SYNC_TO_PORT		REG_BIT(29)
> +#define  CMTG_STATE			REG_BIT(23)
> 
>  #endif /* __INTEL_CMTG_REGS_H__ */
> --
> 2.29.0

[PATCH v8 15/20] drm/i915/cmtg: Add CMTG interrupt handling

[Animesh Manna]

Add support for the CMTG vblank interrupt, which is delivered
through the DE port interrupt block. Enable/disable the interrupt
via the DE port IMR around CMTG enable/disable, and dispatch the
CMTG_VBLANK_{A,B} bits to the corresponding pipe vblank handler in
the gen8 DE IRQ handler.

Wired up for DISPLAY_VER 35. The CMTG interrupt is not enabled via
IER today because CMTG is brought up together with the eDP
transcoder; this can be revisited later.

v2:
- Use consistent DC3co check as used in earlier patches. [Uma]
- Use else-if instead of separate if block. [Uma]
- Merge mask and unmask function as it is similar. [Uma]
- Modify DISPLAY_VER() check. [Uma]

v3:
- Enable only vblank interrupt. [Dibin]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 47 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  2 +
 .../gpu/drm/i915/display/intel_display_irq.c  | 12 +++++
 .../gpu/drm/i915/display/intel_display_regs.h |  2 +
 4 files changed, 63 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 20b74c2856c4..fb57fa41f721 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -13,6 +13,7 @@
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_device.h"
+#include "intel_display_irq.h"
 #include "intel_display_power.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
@@ -353,3 +354,49 @@ void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
 	crtc->cmtg.enabled = true;
 	drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
 }
+
+static void intel_cmtg_mask_interrupt(const struct intel_crtc_state *crtc_state, bool mask)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 interrupt_mask = 0;
+
+	if (cpu_transcoder == TRANSCODER_A)
+		interrupt_mask = CMTG_VBLANK_A;
+	else if (cpu_transcoder == TRANSCODER_B)
+		interrupt_mask = CMTG_VBLANK_B;
+
+	if (mask)
+		bdw_update_port_irq(display, interrupt_mask, 0);
+	else
+		bdw_update_port_irq(display, interrupt_mask, interrupt_mask);
+}
+
+void intel_cmtg_enable_interrupt(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	/*
+	 * TODO: Currently cmtg is enabled along with eDP transcoder so cmtg
+	 * interrupt is not enabled through IER, need to do some fine
+	 * tuning in future.
+	 */
+	spin_lock_irq(&display->irq.lock);
+	intel_cmtg_mask_interrupt(crtc_state, false);
+	spin_unlock_irq(&display->irq.lock);
+}
+
+void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	spin_lock_irq(&display->irq.lock);
+	intel_cmtg_mask_interrupt(crtc_state, true);
+	spin_unlock_irq(&display->irq.lock);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 79785afccc51..8fcb44d6398f 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -21,5 +21,7 @@ void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
 void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_enable_interrupt(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_CMTG_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 4a821b0674fd..7ad722024c87 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1469,6 +1469,18 @@ static void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
 				found = true;
 			}
 
+			if (DISPLAY_VER(display) == 35) {
+				if (iir & (CMTG_VBLANK_A)) {
+					intel_handle_vblank(display, PIPE_A);
+					found = true;
+				}
+
+				if (iir & (CMTG_VBLANK_B)) {
+					intel_handle_vblank(display, PIPE_B);
+					found = true;
+				}
+			}
+
 			if (DISPLAY_VER(display) >= 11) {
 				u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 4321f8b529da..fe851fe39222 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1458,6 +1458,8 @@
 #define  GEN9_AUX_CHANNEL_B		(1 << 25)
 #define  DSI1_TE			(1 << 24)
 #define  DSI0_TE			(1 << 23)
+#define  CMTG_VBLANK_B			(1 << 17)
+#define  CMTG_VBLANK_A			(1 << 14)
 #define  GEN8_DE_PORT_HOTPLUG(hpd_pin)	REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
 #define  BXT_DE_PORT_HOTPLUG_MASK	(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
 					 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
-- 
2.29.0

Re: [PATCH v8 15/20] drm/i915/cmtg: Add CMTG interrupt handling

[Jani Nikula]

On Thu, 04 Jun 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> Add support for the CMTG vblank interrupt, which is delivered
> through the DE port interrupt block. Enable/disable the interrupt
> via the DE port IMR around CMTG enable/disable, and dispatch the
> CMTG_VBLANK_{A,B} bits to the corresponding pipe vblank handler in
> the gen8 DE IRQ handler.
>
> Wired up for DISPLAY_VER 35. The CMTG interrupt is not enabled via
> IER today because CMTG is brought up together with the eDP
> transcoder; this can be revisited later.
>
> v2:
> - Use consistent DC3co check as used in earlier patches. [Uma]
> - Use else-if instead of separate if block. [Uma]
> - Merge mask and unmask function as it is similar. [Uma]
> - Modify DISPLAY_VER() check. [Uma]
>
> v3:
> - Enable only vblank interrupt. [Dibin]
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c     | 47 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_cmtg.h     |  2 +
>  .../gpu/drm/i915/display/intel_display_irq.c  | 12 +++++
>  .../gpu/drm/i915/display/intel_display_regs.h |  2 +
>  4 files changed, 63 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 20b74c2856c4..fb57fa41f721 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -13,6 +13,7 @@
>  #include "intel_crtc.h"
>  #include "intel_de.h"
>  #include "intel_display_device.h"
> +#include "intel_display_irq.h"
>  #include "intel_display_power.h"
>  #include "intel_display_regs.h"
>  #include "intel_display_types.h"
> @@ -353,3 +354,49 @@ void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
>  	crtc->cmtg.enabled = true;
>  	drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
>  }
> +
> +static void intel_cmtg_mask_interrupt(const struct intel_crtc_state *crtc_state, bool mask)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 interrupt_mask = 0;
> +
> +	if (cpu_transcoder == TRANSCODER_A)
> +		interrupt_mask = CMTG_VBLANK_A;
> +	else if (cpu_transcoder == TRANSCODER_B)
> +		interrupt_mask = CMTG_VBLANK_B;
> +
> +	if (mask)
> +		bdw_update_port_irq(display, interrupt_mask, 0);
> +	else
> +		bdw_update_port_irq(display, interrupt_mask, interrupt_mask);

Not a fan of using these directly in more places. The direction should
be for more abstractions.

> +}
> +
> +void intel_cmtg_enable_interrupt(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	/*
> +	 * TODO: Currently cmtg is enabled along with eDP transcoder so cmtg
> +	 * interrupt is not enabled through IER, need to do some fine
> +	 * tuning in future.
> +	 */
> +	spin_lock_irq(&display->irq.lock);
> +	intel_cmtg_mask_interrupt(crtc_state, false);
> +	spin_unlock_irq(&display->irq.lock);
> +}
> +
> +void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	spin_lock_irq(&display->irq.lock);
> +	intel_cmtg_mask_interrupt(crtc_state, true);
> +	spin_unlock_irq(&display->irq.lock);

Ditto with display->irq.lock usage, the direction should be to limit to
fewer places.

> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 79785afccc51..8fcb44d6398f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -21,5 +21,7 @@ void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
>  void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
>  void intel_cmtg_sanitize(struct intel_display *display);
>  bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
> +void intel_cmtg_enable_interrupt(const struct intel_crtc_state *crtc_state);
> +void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state);
>  
>  #endif /* __INTEL_CMTG_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 4a821b0674fd..7ad722024c87 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -1469,6 +1469,18 @@ static void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
>  				found = true;
>  			}
>  
> +			if (DISPLAY_VER(display) == 35) {
> +				if (iir & (CMTG_VBLANK_A)) {
> +					intel_handle_vblank(display, PIPE_A);
> +					found = true;
> +				}
> +
> +				if (iir & (CMTG_VBLANK_B)) {
> +					intel_handle_vblank(display, PIPE_B);
> +					found = true;
> +				}
> +			}
> +
>  			if (DISPLAY_VER(display) >= 11) {
>  				u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 4321f8b529da..fe851fe39222 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -1458,6 +1458,8 @@
>  #define  GEN9_AUX_CHANNEL_B		(1 << 25)
>  #define  DSI1_TE			(1 << 24)
>  #define  DSI0_TE			(1 << 23)
> +#define  CMTG_VBLANK_B			(1 << 17)
> +#define  CMTG_VBLANK_A			(1 << 14)
>  #define  GEN8_DE_PORT_HOTPLUG(hpd_pin)	REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
>  #define  BXT_DE_PORT_HOTPLUG_MASK	(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
>  					 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \

-- 
Jani Nikula, Intel

RE: [PATCH v8 15/20] drm/i915/cmtg: Add CMTG interrupt handling

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Thursday, June 4, 2026 1:24 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v8 15/20] drm/i915/cmtg: Add CMTG interrupt handling
> 
> Add support for the CMTG vblank interrupt, which is delivered through the DE port
> interrupt block. Enable/disable the interrupt via the DE port IMR around CMTG
> enable/disable, and dispatch the CMTG_VBLANK_{A,B} bits to the corresponding
> pipe vblank handler in the gen8 DE IRQ handler.
> 
> Wired up for DISPLAY_VER 35. The CMTG interrupt is not enabled via IER today
> because CMTG is brought up together with the eDP transcoder; this can be
> revisited later.
> 
> v2:
> - Use consistent DC3co check as used in earlier patches. [Uma]
> - Use else-if instead of separate if block. [Uma]
> - Merge mask and unmask function as it is similar. [Uma]
> - Modify DISPLAY_VER() check. [Uma]
> 
> v3:
> - Enable only vblank interrupt. [Dibin]
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c     | 47 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_cmtg.h     |  2 +
>  .../gpu/drm/i915/display/intel_display_irq.c  | 12 +++++
> .../gpu/drm/i915/display/intel_display_regs.h |  2 +
>  4 files changed, 63 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 20b74c2856c4..fb57fa41f721 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -13,6 +13,7 @@
>  #include "intel_crtc.h"
>  #include "intel_de.h"
>  #include "intel_display_device.h"
> +#include "intel_display_irq.h"
>  #include "intel_display_power.h"
>  #include "intel_display_regs.h"
>  #include "intel_display_types.h"
> @@ -353,3 +354,49 @@ void intel_cmtg_enable_ddi(const struct intel_crtc_state
> *crtc_state)
>  	crtc->cmtg.enabled = true;
>  	drm_dbg_kms(display->drm, "CMTG: %s enabled\n",
> transcoder_name(cpu_transcoder));  }
> +
> +static void intel_cmtg_mask_interrupt(const struct intel_crtc_state
> +*crtc_state, bool mask) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 interrupt_mask = 0;
> +
> +	if (cpu_transcoder == TRANSCODER_A)
> +		interrupt_mask = CMTG_VBLANK_A;
> +	else if (cpu_transcoder == TRANSCODER_B)
> +		interrupt_mask = CMTG_VBLANK_B;
> +
> +	if (mask)
> +		bdw_update_port_irq(display, interrupt_mask, 0);
> +	else
> +		bdw_update_port_irq(display, interrupt_mask, interrupt_mask); }
>

Agree with Jani, this can be abstracted better.
Something like:

Add in intel_display_irq.c
void intel_de_port_interrupt_mask(struct intel_display *display, u32 bits, bool mask)
{
    spin_lock_irq(&display->irq.lock);
    bdw_update_port_irq(display, bits, mask ? 0 : bits);
    spin_unlock_irq(&display->irq.lock);
}

and call from various places instead of using the function directly.

> +void intel_cmtg_enable_interrupt(const struct intel_crtc_state
> +*crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	/*
> +	 * TODO: Currently cmtg is enabled along with eDP transcoder so cmtg
> +	 * interrupt is not enabled through IER, need to do some fine
> +	 * tuning in future.
> +	 */
> +	spin_lock_irq(&display->irq.lock);
> +	intel_cmtg_mask_interrupt(crtc_state, false);
> +	spin_unlock_irq(&display->irq.lock);
> +}
> +
> +void intel_cmtg_disable_interrupt(const struct intel_crtc_state
> +*crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	spin_lock_irq(&display->irq.lock);
> +	intel_cmtg_mask_interrupt(crtc_state, true);
> +	spin_unlock_irq(&display->irq.lock);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 79785afccc51..8fcb44d6398f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -21,5 +21,7 @@ void intel_cmtg_set_timings(const struct intel_crtc_state
> *crtc_state, bool lrr)  void intel_cmtg_set_clk_select(const struct intel_crtc_state
> *crtc_state);  void intel_cmtg_sanitize(struct intel_display *display);  bool
> intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
> +void intel_cmtg_enable_interrupt(const struct intel_crtc_state
> +*crtc_state); void intel_cmtg_disable_interrupt(const struct
> +intel_crtc_state *crtc_state);
> 
>  #endif /* __INTEL_CMTG_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
> b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 4a821b0674fd..7ad722024c87 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -1469,6 +1469,18 @@ static void gen8_de_irq_handler(struct intel_display
> *display, u32 master_ctl)
>  				found = true;
>  			}
> 
> +			if (DISPLAY_VER(display) == 35) {
> +				if (iir & (CMTG_VBLANK_A)) {

Redundant parenthesis

> +					intel_handle_vblank(display, PIPE_A);
> +					found = true;
> +				}
> +
> +				if (iir & (CMTG_VBLANK_B)) {

Here as well

> +					intel_handle_vblank(display, PIPE_B);
> +					found = true;
> +				}
> +			}
> +
>  			if (DISPLAY_VER(display) >= 11) {
>  				u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 4321f8b529da..fe851fe39222 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -1458,6 +1458,8 @@
>  #define  GEN9_AUX_CHANNEL_B		(1 << 25)
>  #define  DSI1_TE			(1 << 24)
>  #define  DSI0_TE			(1 << 23)
> +#define  CMTG_VBLANK_B			(1 << 17)
> +#define  CMTG_VBLANK_A			(1 << 14)
>  #define  GEN8_DE_PORT_HOTPLUG(hpd_pin)	REG_BIT(3 +
> _HPD_PIN_DDI(hpd_pin))
>  #define  BXT_DE_PORT_HOTPLUG_MASK
> 	(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
> 
> GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
> --
> 2.29.0

[PATCH v8 16/20] drm/i915/cmtg: Add CMTG HWGB programming

[Animesh Manna]

From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>

Program CMTG guardband to generate the Lower/Upper and early entry
guardband indicators to the DMC for DC3co control.

Bspec: 75253
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 31 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  8 +++++
 3 files changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index fb57fa41f721..cc36784e5253 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -400,3 +400,34 @@ void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state)
 	intel_cmtg_mask_interrupt(crtc_state, true);
 	spin_unlock_irq(&display->irq.lock);
 }
+
+#define DC3CO_ENTRY_LATENCY	55
+#define DC3CO_EXIT_LATENCY	40
+
+void intel_cmtg_set_hwgb(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 breakeven_gb;
+	u32 dc5_exit_latency;
+	u32 line_time_us = 75;
+	u32 val;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	if (crtc_state->linetime)
+		line_time_us = DIV_ROUND_UP(crtc_state->linetime, 8);
+
+	/* Break Even Guardband - DC3co Entry Latency / linetime */
+	breakeven_gb = DIV_ROUND_UP(DC3CO_ENTRY_LATENCY, line_time_us);
+
+	/* DC5 Exit Latency - DC3co Exit Latency / linetime */
+	dc5_exit_latency = DIV_ROUND_UP(DC3CO_EXIT_LATENCY, line_time_us);
+
+	val = REG_FIELD_PREP(CMTG_HW_GB_BREAKEVEN_MASK, breakeven_gb) |
+	      REG_FIELD_PREP(CMTG_HW_GB_DC5_EXIT_LATENCY_MASK, dc5_exit_latency) |
+	      REG_FIELD_PREP(CMTG_HW_GB_UP_LW_BG_DIFF_MASK, 1);
+
+	intel_de_write(display, CMTG_HW_GB(cpu_transcoder), val);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 8fcb44d6398f..2c801a74acf9 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -23,5 +23,6 @@ void intel_cmtg_sanitize(struct intel_display *display);
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_enable_interrupt(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_set_hwgb(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_CMTG_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 240a02cd4a3a..a4a2a2fe6b66 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -24,4 +24,12 @@
 #define  CMTG_SYNC_TO_PORT		REG_BIT(29)
 #define  CMTG_STATE			REG_BIT(23)
 
+#define _CMTG_HW_GB_A				0x6fa8c
+#define _CMTG_HW_GB_B				0x6fb8c
+#define CMTG_HW_GB(trans)			_MMIO_TRANS((trans), \
+							    _CMTG_HW_GB_A, _CMTG_HW_GB_B)
+#define CMTG_HW_GB_BREAKEVEN_MASK		REG_GENMASK(11, 0)
+#define CMTG_HW_GB_DC5_EXIT_LATENCY_MASK	REG_GENMASK(27, 16)
+#define CMTG_HW_GB_UP_LW_BG_DIFF_MASK		REG_GENMASK(31, 28)
+
 #endif /* __INTEL_CMTG_REGS_H__ */
-- 
2.29.0

RE: [PATCH v8 16/20] drm/i915/cmtg: Add CMTG HWGB programming

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Thursday, June 4, 2026 1:24 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v8 16/20] drm/i915/cmtg: Add CMTG HWGB programming
> 
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> 
> Program CMTG guardband to generate the Lower/Upper and early entry
> guardband indicators to the DMC for DC3co control.
> 
> Bspec: 75253
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c     | 31 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
>  .../gpu/drm/i915/display/intel_cmtg_regs.h    |  8 +++++
>  3 files changed, 40 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index fb57fa41f721..cc36784e5253 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -400,3 +400,34 @@ void intel_cmtg_disable_interrupt(const struct
> intel_crtc_state *crtc_state)
>  	intel_cmtg_mask_interrupt(crtc_state, true);
>  	spin_unlock_irq(&display->irq.lock);
>  }
> +
> +#define DC3CO_ENTRY_LATENCY	55
> +#define DC3CO_EXIT_LATENCY	40

Add the bspec reference for this. Also indicate what unit this latency is in.

> +void intel_cmtg_set_hwgb(const struct intel_crtc_state *crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 breakeven_gb;
> +	u32 dc5_exit_latency;
> +	u32 line_time_us = 75;

From where this 75 come from, add a comment.

> +	u32 val;
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	if (crtc_state->linetime)
> +		line_time_us = DIV_ROUND_UP(crtc_state->linetime, 8);
> +
> +	/* Break Even Guardband - DC3co Entry Latency / linetime */
> +	breakeven_gb = DIV_ROUND_UP(DC3CO_ENTRY_LATENCY,
> line_time_us);
> +
> +	/* DC5 Exit Latency - DC3co Exit Latency / linetime */
> +	dc5_exit_latency = DIV_ROUND_UP(DC3CO_EXIT_LATENCY,
> line_time_us);
> +
> +	val = REG_FIELD_PREP(CMTG_HW_GB_BREAKEVEN_MASK,
> breakeven_gb) |
> +	      REG_FIELD_PREP(CMTG_HW_GB_DC5_EXIT_LATENCY_MASK,
> dc5_exit_latency) |
> +	      REG_FIELD_PREP(CMTG_HW_GB_UP_LW_BG_DIFF_MASK, 1);
> +
> +	intel_de_write(display, CMTG_HW_GB(cpu_transcoder), val); 

Should it be cpu_transcoder or cmtg_transcoder ? 


With above fixed, this is
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 8fcb44d6398f..2c801a74acf9 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -23,5 +23,6 @@ void intel_cmtg_sanitize(struct intel_display *display);  bool
> intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);  void
> intel_cmtg_enable_interrupt(const struct intel_crtc_state *crtc_state);  void
> intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state);
> +void intel_cmtg_set_hwgb(const struct intel_crtc_state *crtc_state);
> 
>  #endif /* __INTEL_CMTG_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index 240a02cd4a3a..a4a2a2fe6b66 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -24,4 +24,12 @@
>  #define  CMTG_SYNC_TO_PORT		REG_BIT(29)
>  #define  CMTG_STATE			REG_BIT(23)
> 
> +#define _CMTG_HW_GB_A				0x6fa8c
> +#define _CMTG_HW_GB_B				0x6fb8c
> +#define CMTG_HW_GB(trans)			_MMIO_TRANS((trans), \
> +							    _CMTG_HW_GB_A,
> _CMTG_HW_GB_B)
> +#define CMTG_HW_GB_BREAKEVEN_MASK		REG_GENMASK(11, 0)
> +#define CMTG_HW_GB_DC5_EXIT_LATENCY_MASK	REG_GENMASK(27, 16)
> +#define CMTG_HW_GB_UP_LW_BG_DIFF_MASK
> 	REG_GENMASK(31, 28)
> +
>  #endif /* __INTEL_CMTG_REGS_H__ */
> --
> 2.29.0

[PATCH v8 17/20] drm/i915/cmtg: Add CMTG scan line programming

[Animesh Manna]

From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>

Enable the hardware based guardband calculations which allows
DC3co to remain enabled when timings are changing from one fixed
refresh rate to another fixed refresh rate.

Bspec: 75253
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c      | 2 ++
 drivers/gpu/drm/i915/display/intel_cmtg_regs.h | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index cc36784e5253..1d63b612c44b 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -188,6 +188,7 @@ void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)
 
 	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),
 		     CMTG_SECONDARY_MODE, 0);
+	intel_de_rmw(display, CMTG_SCANLINE_GB1(cpu_transcoder), CMTG_HW_GB_ENABLE, 0);
 
 	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_ENABLE, 0);
 
@@ -351,6 +352,7 @@ void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
 		return;
 
 	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0, CMTG_SECONDARY_MODE);
+	intel_de_rmw(display, CMTG_SCANLINE_GB1(cpu_transcoder), 0, CMTG_HW_GB_ENABLE);
 	crtc->cmtg.enabled = true;
 	drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
 }
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index a4a2a2fe6b66..18dcb665df04 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -32,4 +32,10 @@
 #define CMTG_HW_GB_DC5_EXIT_LATENCY_MASK	REG_GENMASK(27, 16)
 #define CMTG_HW_GB_UP_LW_BG_DIFF_MASK		REG_GENMASK(31, 28)
 
+#define _CMTG_SCANLINE_GB1_A		0x456A0
+#define _CMTG_SCANLINE_GB1_B		0x456C0
+#define CMTG_SCANLINE_GB1(trans)	_MMIO_TRANS((trans), \
+						    _CMTG_SCANLINE_GB1_A, _CMTG_SCANLINE_GB1_B)
+#define  CMTG_HW_GB_ENABLE		REG_BIT(31)
+
 #endif /* __INTEL_CMTG_REGS_H__ */
-- 
2.29.0

RE: [PATCH v8 17/20] drm/i915/cmtg: Add CMTG scan line programming

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Thursday, June 4, 2026 1:24 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v8 17/20] drm/i915/cmtg: Add CMTG scan line programming
> 
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> 
> Enable the hardware based guardband calculations which allows DC3co to remain
> enabled when timings are changing from one fixed refresh rate to another fixed
> refresh rate.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Bspec: 75253
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c      | 2 ++
>  drivers/gpu/drm/i915/display/intel_cmtg_regs.h | 6 ++++++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index cc36784e5253..1d63b612c44b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -188,6 +188,7 @@ void intel_cmtg_disable(const struct intel_crtc_state
> *crtc_state)
> 
>  	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display,
> cpu_transcoder),
>  		     CMTG_SECONDARY_MODE, 0);
> +	intel_de_rmw(display, CMTG_SCANLINE_GB1(cpu_transcoder),
> +CMTG_HW_GB_ENABLE, 0);
> 
>  	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder),
> CMTG_ENABLE, 0);
> 
> @@ -351,6 +352,7 @@ void intel_cmtg_enable_ddi(const struct intel_crtc_state
> *crtc_state)
>  		return;
> 
>  	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display,
> cpu_transcoder), 0, CMTG_SECONDARY_MODE);
> +	intel_de_rmw(display, CMTG_SCANLINE_GB1(cpu_transcoder), 0,
> +CMTG_HW_GB_ENABLE);
>  	crtc->cmtg.enabled = true;
>  	drm_dbg_kms(display->drm, "CMTG: %s enabled\n",
> transcoder_name(cpu_transcoder));  } diff --git
> a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index a4a2a2fe6b66..18dcb665df04 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -32,4 +32,10 @@
>  #define CMTG_HW_GB_DC5_EXIT_LATENCY_MASK	REG_GENMASK(27, 16)
>  #define CMTG_HW_GB_UP_LW_BG_DIFF_MASK
> 	REG_GENMASK(31, 28)
> 
> +#define _CMTG_SCANLINE_GB1_A		0x456A0
> +#define _CMTG_SCANLINE_GB1_B		0x456C0
> +#define CMTG_SCANLINE_GB1(trans)	_MMIO_TRANS((trans), \
> +						    _CMTG_SCANLINE_GB1_A,
> _CMTG_SCANLINE_GB1_B)
> +#define  CMTG_HW_GB_ENABLE		REG_BIT(31)
> +
>  #endif /* __INTEL_CMTG_REGS_H__ */
> --
> 2.29.0

[PATCH v8 18/20] drm/i915/cmtg: Add trigger to enable/disable cmtg

[Animesh Manna]

Enable CMTG with fixed refresh rate mode and with dynamic
dc state enabled.

Disable CMTG with transcoder disable or if there is a transition
to vrr mode from fixed refresh rate mode.

v2:
- Move the enabled flag update to avoid issue in the disable timeout
path. [Uma]

v3:
- Introduce intel_cmtg_program() rather calling multiple cmtg
functions. [Dibin]
- Set clock select before cmtg disable as can lost during dc6
entry. [Dibin]
- Disable cmtg interrupt in crtc-disable(). [Dibin]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c    | 25 ++++++++++----------
 drivers/gpu/drm/i915/display/intel_cmtg.h    |  4 +---
 drivers/gpu/drm/i915/display/intel_display.c | 24 +++++++++++++++++++
 3 files changed, 38 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 1d63b612c44b..b7f4be33ce2e 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -323,15 +323,12 @@ void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state)
 	intel_de_write(display, PIPE_LINK_N1(display, cmtg_transcoder), m_n->link_n);
 }
 
-void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
+static void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	u32 cmtg_ctl;
 
-	if (!intel_cmtg_is_allowed(crtc_state))
-		return;
-
 	cmtg_ctl = CMTG_SYNC_TO_PORT | CMTG_ENABLE;
 
 	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), 0, cmtg_ctl);
@@ -342,15 +339,12 @@ void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
 	}
 }
 
-void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
+static void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
-	if (!intel_cmtg_is_allowed(crtc_state))
-		return;
-
 	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0, CMTG_SECONDARY_MODE);
 	intel_de_rmw(display, CMTG_SCANLINE_GB1(cpu_transcoder), 0, CMTG_HW_GB_ENABLE);
 	crtc->cmtg.enabled = true;
@@ -406,7 +400,7 @@ void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state)
 #define DC3CO_ENTRY_LATENCY	55
 #define DC3CO_EXIT_LATENCY	40
 
-void intel_cmtg_set_hwgb(const struct intel_crtc_state *crtc_state)
+static void intel_cmtg_set_hwgb(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
@@ -415,9 +409,6 @@ void intel_cmtg_set_hwgb(const struct intel_crtc_state *crtc_state)
 	u32 line_time_us = 75;
 	u32 val;
 
-	if (!intel_cmtg_is_allowed(crtc_state))
-		return;
-
 	if (crtc_state->linetime)
 		line_time_us = DIV_ROUND_UP(crtc_state->linetime, 8);
 
@@ -433,3 +424,13 @@ void intel_cmtg_set_hwgb(const struct intel_crtc_state *crtc_state)
 
 	intel_de_write(display, CMTG_HW_GB(cpu_transcoder), val);
 }
+
+void intel_cmtg_program(const struct intel_crtc_state *crtc_state)
+{
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	intel_cmtg_enable_sync(crtc_state);
+	intel_cmtg_set_hwgb(crtc_state);
+	intel_cmtg_enable_ddi(crtc_state);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 2c801a74acf9..51fc3f5a89f4 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -12,8 +12,6 @@ struct intel_display;
 struct intel_crtc_state;
 
 void intel_cmtg_disable(const struct intel_crtc_state *crtc_state);
-void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state);
-void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);
@@ -23,6 +21,6 @@ void intel_cmtg_sanitize(struct intel_display *display);
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_enable_interrupt(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state);
-void intel_cmtg_set_hwgb(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_program(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_CMTG_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e4763ac81c39..e751a4c37842 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1790,6 +1790,11 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
 		intel_atomic_get_old_crtc_state(state, crtc);
 	struct intel_crtc *pipe_crtc;
 
+	if (crtc->cmtg.enabled) {
+		intel_cmtg_set_clk_select(old_crtc_state);
+		intel_cmtg_disable(old_crtc_state);
+		intel_cmtg_disable_interrupt(old_crtc_state);
+	}
 	/*
 	 * FIXME collapse everything to one hook.
 	 * Need care with mst->ddi interactions.
@@ -6878,6 +6883,12 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 	if (intel_crtc_needs_fastset(new_crtc_state) &&
 	    old_crtc_state->inherited)
 		intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
+
+	if (crtc->cmtg.enabled && (intel_crtc_vrr_enabling(state, crtc))) {
+		intel_cmtg_set_clk_select(new_crtc_state);
+		intel_cmtg_disable(new_crtc_state);
+		intel_cmtg_disable_interrupt(new_crtc_state);
+	}
 }
 
 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
@@ -7547,6 +7558,19 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	/* FIXME probably need to sequence this properly */
 	intel_program_dpkgc_latency(state);
 
+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) {
+		bool modeset = intel_crtc_needs_modeset(new_crtc_state);
+
+		/*
+		 * TODO: CMTG needs to be restored on DC6 exit and DC3co entry condition
+		 * need to be checked before calling CMTG functions.
+		 */
+		if (modeset && new_crtc_state->hw.active && !crtc->cmtg.enabled) {
+			intel_cmtg_program(new_crtc_state);
+			intel_cmtg_enable_interrupt(new_crtc_state);
+		}
+	}
+
 	intel_wait_for_vblank_workers(state);
 
 	/* FIXME: We should call drm_atomic_helper_commit_hw_done() here
-- 
2.29.0

RE: [PATCH v8 18/20] drm/i915/cmtg: Add trigger to enable/disable cmtg

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Thursday, June 4, 2026 1:24 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v8 18/20] drm/i915/cmtg: Add trigger to enable/disable cmtg
> 
> Enable CMTG with fixed refresh rate mode and with dynamic dc state enabled.
> 
> Disable CMTG with transcoder disable or if there is a transition to vrr mode from
> fixed refresh rate mode.
> 
> v2:
> - Move the enabled flag update to avoid issue in the disable timeout path. [Uma]
> 
> v3:
> - Introduce intel_cmtg_program() rather calling multiple cmtg functions. [Dibin]
> - Set clock select before cmtg disable as can lost during dc6 entry. [Dibin]
> - Disable cmtg interrupt in crtc-disable(). [Dibin]


> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c    | 25 ++++++++++----------
>  drivers/gpu/drm/i915/display/intel_cmtg.h    |  4 +---
>  drivers/gpu/drm/i915/display/intel_display.c | 24 +++++++++++++++++++
>  3 files changed, 38 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 1d63b612c44b..b7f4be33ce2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -323,15 +323,12 @@ void intel_cmtg_set_m_n(const struct intel_crtc_state
> *crtc_state)
>  	intel_de_write(display, PIPE_LINK_N1(display, cmtg_transcoder), m_n-
> >link_n);  }
> 
> -void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
> +static void intel_cmtg_enable_sync(const struct intel_crtc_state
> +*crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	u32 cmtg_ctl;
> 
> -	if (!intel_cmtg_is_allowed(crtc_state))
> -		return;
> -
>  	cmtg_ctl = CMTG_SYNC_TO_PORT | CMTG_ENABLE;
> 
>  	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), 0, cmtg_ctl);
> @@ -342,15 +339,12 @@ void intel_cmtg_enable_sync(const struct
> intel_crtc_state *crtc_state)
>  	}
>  }
> 
> -void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
> +static void intel_cmtg_enable_ddi(const struct intel_crtc_state
> +*crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> 
> -	if (!intel_cmtg_is_allowed(crtc_state))
> -		return;
> -
>  	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display,
> cpu_transcoder), 0, CMTG_SECONDARY_MODE);
>  	intel_de_rmw(display, CMTG_SCANLINE_GB1(cpu_transcoder), 0,
> CMTG_HW_GB_ENABLE);
>  	crtc->cmtg.enabled = true;
> @@ -406,7 +400,7 @@ void intel_cmtg_disable_interrupt(const struct
> intel_crtc_state *crtc_state)
>  #define DC3CO_ENTRY_LATENCY	55
>  #define DC3CO_EXIT_LATENCY	40
> 
> -void intel_cmtg_set_hwgb(const struct intel_crtc_state *crtc_state)
> +static void intel_cmtg_set_hwgb(const struct intel_crtc_state
> +*crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; @@ -
> 415,9 +409,6 @@ void intel_cmtg_set_hwgb(const struct intel_crtc_state
> *crtc_state)
>  	u32 line_time_us = 75;
>  	u32 val;
> 
> -	if (!intel_cmtg_is_allowed(crtc_state))
> -		return;
> -
>  	if (crtc_state->linetime)
>  		line_time_us = DIV_ROUND_UP(crtc_state->linetime, 8);
> 
> @@ -433,3 +424,13 @@ void intel_cmtg_set_hwgb(const struct intel_crtc_state
> *crtc_state)
> 
>  	intel_de_write(display, CMTG_HW_GB(cpu_transcoder), val);  }
> +
> +void intel_cmtg_program(const struct intel_crtc_state *crtc_state) {
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	intel_cmtg_enable_sync(crtc_state);
> +	intel_cmtg_set_hwgb(crtc_state);
> +	intel_cmtg_enable_ddi(crtc_state);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 2c801a74acf9..51fc3f5a89f4 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -12,8 +12,6 @@ struct intel_display;
>  struct intel_crtc_state;
> 
>  void intel_cmtg_disable(const struct intel_crtc_state *crtc_state); -void
> intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state); -void
> intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);  void
> intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);  void
> intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);  void
> intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state); @@ -23,6 +21,6
> @@ void intel_cmtg_sanitize(struct intel_display *display);  bool
> intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);  void
> intel_cmtg_enable_interrupt(const struct intel_crtc_state *crtc_state);  void
> intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state); -void
> intel_cmtg_set_hwgb(const struct intel_crtc_state *crtc_state);
> +void intel_cmtg_program(const struct intel_crtc_state *crtc_state);
> 
>  #endif /* __INTEL_CMTG_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e4763ac81c39..e751a4c37842 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1790,6 +1790,11 @@ static void hsw_crtc_disable(struct intel_atomic_state
> *state,
>  		intel_atomic_get_old_crtc_state(state, crtc);
>  	struct intel_crtc *pipe_crtc;
> 
> +	if (crtc->cmtg.enabled) {

In this path we differ from enable where we check for cmtg_is_allowed as well.
We can make both enable and disable consistent.

> +		intel_cmtg_set_clk_select(old_crtc_state);
> +		intel_cmtg_disable(old_crtc_state);
> +		intel_cmtg_disable_interrupt(old_crtc_state);
> +	}
>  	/*
>  	 * FIXME collapse everything to one hook.
>  	 * Need care with mst->ddi interactions.
> @@ -6878,6 +6883,12 @@ static void intel_update_crtc(struct intel_atomic_state
> *state,
>  	if (intel_crtc_needs_fastset(new_crtc_state) &&
>  	    old_crtc_state->inherited)
>  		intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
> +
> +	if (crtc->cmtg.enabled && (intel_crtc_vrr_enabling(state, crtc))) {
> +		intel_cmtg_set_clk_select(new_crtc_state);
> +		intel_cmtg_disable(new_crtc_state);
> +		intel_cmtg_disable_interrupt(new_crtc_state);
> +	}
>  }
> 
>  static void intel_old_crtc_state_disables(struct intel_atomic_state *state, @@ -
> 7547,6 +7558,19 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
>  	/* FIXME probably need to sequence this properly */
>  	intel_program_dpkgc_latency(state);
> 
> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) {
> +		bool modeset = intel_crtc_needs_modeset(new_crtc_state);
> +
> +		/*
> +		 * TODO: CMTG needs to be restored on DC6 exit and DC3co
> entry condition
> +		 * need to be checked before calling CMTG functions.
> +		 */

Assuming this is going to be taken care as part of DC3Co enabling.

With above addressed, this is
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> +		if (modeset && new_crtc_state->hw.active && !crtc-
> >cmtg.enabled) {
> +			intel_cmtg_program(new_crtc_state);
> +			intel_cmtg_enable_interrupt(new_crtc_state);
> +		}
> +	}
> +
>  	intel_wait_for_vblank_workers(state);
> 
>  	/* FIXME: We should call drm_atomic_helper_commit_hw_done() here
> --
> 2.29.0

[PATCH v8 19/20] drm/i915/cmtg: Restore CMTG after DC6 exit

[Animesh Manna]

Restore CMTG registers after DC6 exit, as they lose their values
in the low-power state.

v2: Introduce intel_cmtg_restore() instead of calling multiple cmtg
functions. [Uma]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c       |  9 +++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h       |  1 +
 drivers/gpu/drm/i915/display/intel_display.c    | 10 +++++++---
 .../gpu/drm/i915/display/intel_display_power.c  | 17 +++++++++++++++++
 .../gpu/drm/i915/display/intel_display_power.h  |  2 ++
 5 files changed, 36 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index b7f4be33ce2e..8be6f7f28e35 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -434,3 +434,12 @@ void intel_cmtg_program(const struct intel_crtc_state *crtc_state)
 	intel_cmtg_set_hwgb(crtc_state);
 	intel_cmtg_enable_ddi(crtc_state);
 }
+
+void intel_cmtg_restore(const struct intel_crtc_state *crtc_state)
+{
+	intel_cmtg_set_clk_select(crtc_state);
+	intel_cmtg_set_timings(crtc_state, false);
+	intel_cmtg_set_vrr_timings(crtc_state);
+	intel_cmtg_set_vrr_ctl(crtc_state);
+	intel_cmtg_set_m_n(crtc_state);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 51fc3f5a89f4..37f90123c397 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -22,5 +22,6 @@ bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_enable_interrupt(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_program(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_restore(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_CMTG_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e751a4c37842..35fbf1ae210e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7560,12 +7560,16 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) {
 		bool modeset = intel_crtc_needs_modeset(new_crtc_state);
+		bool dc3co_to_dc6 = intel_display_power_get_and_reset_dc3co_to_dc6(display);
 
 		/*
-		 * TODO: CMTG needs to be restored on DC6 exit and DC3co entry condition
-		 * need to be checked before calling CMTG functions.
+		 * TODO: DC3co entry condition need to be checked before calling CMTG functions.
 		 */
-		if (modeset && new_crtc_state->hw.active && !crtc->cmtg.enabled) {
+		if ((modeset || dc3co_to_dc6) &&
+		    new_crtc_state->hw.active && !crtc->cmtg.enabled) {
+			if (dc3co_to_dc6)
+				intel_cmtg_restore(new_crtc_state);
+
 			intel_cmtg_program(new_crtc_state);
 			intel_cmtg_enable_interrupt(new_crtc_state);
 		}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 2e51dfcd5dce..e75002819bf5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -285,6 +285,19 @@ sanitize_target_dc_state(struct intel_display *display,
 	return target_dc_state;
 }
 
+bool intel_display_power_get_and_reset_dc3co_to_dc6(struct intel_display *display)
+{
+	struct i915_power_domains *power_domains = &display->power.domains;
+	bool ret;
+
+	mutex_lock(&power_domains->lock);
+	ret = power_domains->dc3co_to_dc6;
+	power_domains->dc3co_to_dc6 = false;
+	mutex_unlock(&power_domains->lock);
+
+	return ret;
+}
+
 /**
  * intel_display_power_set_target_dc_state - Set target dc state.
  * @display: display device
@@ -320,6 +333,10 @@ void intel_display_power_set_target_dc_state(struct intel_display *display,
 	if (!dc_off_enabled)
 		intel_power_well_enable(display, power_well);
 
+	if (power_domains->target_dc_state == DC_STATE_EN_DC3CO &&
+	    state == DC_STATE_EN_UPTO_DC6)
+		power_domains->dc3co_to_dc6 = true;
+
 	power_domains->target_dc_state = state;
 
 	if (!dc_off_enabled)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 56dc89eed3f8..b9c9b68072af 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -138,6 +138,7 @@ struct i915_power_domains {
 	 */
 	bool initializing;
 	bool display_core_suspended;
+	bool dc3co_to_dc6;
 	int power_well_count;
 
 	u32 dc_state;
@@ -179,6 +180,7 @@ void intel_display_power_sanitize_state(struct intel_display *display);
 
 void intel_display_power_suspend_late(struct intel_display *display, bool s2idle);
 void intel_display_power_resume_early(struct intel_display *display);
+bool intel_display_power_get_and_reset_dc3co_to_dc6(struct intel_display *display);
 void intel_display_power_set_target_dc_state(struct intel_display *display,
 					     u32 state);
 u32 intel_display_power_get_current_dc_state(struct intel_display *display);
-- 
2.29.0

RE: [PATCH v8 19/20] drm/i915/cmtg: Restore CMTG after DC6 exit

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Thursday, June 4, 2026 1:24 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH v8 19/20] drm/i915/cmtg: Restore CMTG after DC6 exit
> 
> Restore CMTG registers after DC6 exit, as they lose their values in the low-power
> state.
> 
> v2: Introduce intel_cmtg_restore() instead of calling multiple cmtg functions.
> [Uma]
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c       |  9 +++++++++
>  drivers/gpu/drm/i915/display/intel_cmtg.h       |  1 +
>  drivers/gpu/drm/i915/display/intel_display.c    | 10 +++++++---
>  .../gpu/drm/i915/display/intel_display_power.c  | 17 +++++++++++++++++
> .../gpu/drm/i915/display/intel_display_power.h  |  2 ++
>  5 files changed, 36 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index b7f4be33ce2e..8be6f7f28e35 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -434,3 +434,12 @@ void intel_cmtg_program(const struct intel_crtc_state
> *crtc_state)
>  	intel_cmtg_set_hwgb(crtc_state);
>  	intel_cmtg_enable_ddi(crtc_state);
>  }
> +
> +void intel_cmtg_restore(const struct intel_crtc_state *crtc_state) {
> +	intel_cmtg_set_clk_select(crtc_state);
> +	intel_cmtg_set_timings(crtc_state, false);
> +	intel_cmtg_set_vrr_timings(crtc_state);
> +	intel_cmtg_set_vrr_ctl(crtc_state);
> +	intel_cmtg_set_m_n(crtc_state);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 51fc3f5a89f4..37f90123c397 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -22,5 +22,6 @@ bool intel_cmtg_is_allowed(const struct intel_crtc_state
> *crtc_state);  void intel_cmtg_enable_interrupt(const struct intel_crtc_state
> *crtc_state);  void intel_cmtg_disable_interrupt(const struct intel_crtc_state
> *crtc_state);  void intel_cmtg_program(const struct intel_crtc_state *crtc_state);
> +void intel_cmtg_restore(const struct intel_crtc_state *crtc_state);
> 
>  #endif /* __INTEL_CMTG_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e751a4c37842..35fbf1ae210e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7560,12 +7560,16 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> 
>  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state) {
>  		bool modeset = intel_crtc_needs_modeset(new_crtc_state);
> +		bool dc3co_to_dc6 =
> +intel_display_power_get_and_reset_dc3co_to_dc6(display);
> 
>  		/*
> -		 * TODO: CMTG needs to be restored on DC6 exit and DC3co
> entry condition
> -		 * need to be checked before calling CMTG functions.
> +		 * TODO: DC3co entry condition need to be checked before calling
> CMTG functions.
>  		 */

Would request @Dibin Moolakadan Subrahmanian to please check this as well.

> -		if (modeset && new_crtc_state->hw.active && !crtc-
> >cmtg.enabled) {
> +		if ((modeset || dc3co_to_dc6) &&
> +		    new_crtc_state->hw.active && !crtc->cmtg.enabled) {
> +			if (dc3co_to_dc6)
> +				intel_cmtg_restore(new_crtc_state);
> +
>  			intel_cmtg_program(new_crtc_state);
>  			intel_cmtg_enable_interrupt(new_crtc_state);
>  		}
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 2e51dfcd5dce..e75002819bf5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -285,6 +285,19 @@ sanitize_target_dc_state(struct intel_display *display,
>  	return target_dc_state;
>  }
> 
> +bool intel_display_power_get_and_reset_dc3co_to_dc6(struct
> +intel_display *display) {
> +	struct i915_power_domains *power_domains = &display->power.domains;
> +	bool ret;
> +
> +	mutex_lock(&power_domains->lock);
> +	ret = power_domains->dc3co_to_dc6;
> +	power_domains->dc3co_to_dc6 = false;
> +	mutex_unlock(&power_domains->lock);
> +

Since this is called in loop for all crtc's, only the first crtc will get this as true.
For all else, this will be false. Can you check this once.

> +	return ret;
> +}
> +
>  /**
>   * intel_display_power_set_target_dc_state - Set target dc state.
>   * @display: display device
> @@ -320,6 +333,10 @@ void intel_display_power_set_target_dc_state(struct
> intel_display *display,
>  	if (!dc_off_enabled)
>  		intel_power_well_enable(display, power_well);
> 
> +	if (power_domains->target_dc_state == DC_STATE_EN_DC3CO &&
> +	    state == DC_STATE_EN_UPTO_DC6)
> +		power_domains->dc3co_to_dc6 = true;

I think this looks a bit off, we are moving from DC6 to DC3Co while the variable being
made true is reverse. Can you re-check the logic again.

> +
>  	power_domains->target_dc_state = state;
> 
>  	if (!dc_off_enabled)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 56dc89eed3f8..b9c9b68072af 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -138,6 +138,7 @@ struct i915_power_domains {
>  	 */
>  	bool initializing;
>  	bool display_core_suspended;
> +	bool dc3co_to_dc6;
>  	int power_well_count;
> 
>  	u32 dc_state;
> @@ -179,6 +180,7 @@ void intel_display_power_sanitize_state(struct
> intel_display *display);
> 
>  void intel_display_power_suspend_late(struct intel_display *display, bool s2idle);
> void intel_display_power_resume_early(struct intel_display *display);
> +bool intel_display_power_get_and_reset_dc3co_to_dc6(struct
> +intel_display *display);
>  void intel_display_power_set_target_dc_state(struct intel_display *display,
>  					     u32 state);
>  u32 intel_display_power_get_current_dc_state(struct intel_display *display);
> --
> 2.29.0

[PATCH v8 20/20] Debug patch

[Animesh Manna]

Debug patch. Not for review.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 8be6f7f28e35..3b23d4517e5e 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -239,6 +239,12 @@ bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
+	/*
+	 * Currently Dc3co patches are not merged so returning false for
+	 * continuing cmtg patch review
+	 */
+	return false;
+
 	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B) &&
 	    DISPLAY_VER(display) == 35 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 		return true;
-- 
2.29.0

✓ CI.KUnit: success for CMTG enablement (rev9)

[Patchwork]

== Series Details ==

Series: CMTG enablement (rev9)
URL   : https://patchwork.freedesktop.org/series/157663/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[21:23:43] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:23:50] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:24:21] Starting KUnit Kernel (1/1)...
[21:24:21] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:24:22] ================== guc_buf (11 subtests) ===================
[21:24:22] [PASSED] test_smallest
[21:24:22] [PASSED] test_largest
[21:24:22] [PASSED] test_granular
[21:24:22] [PASSED] test_unique
[21:24:22] [PASSED] test_overlap
[21:24:22] [PASSED] test_reusable
[21:24:22] [PASSED] test_too_big
[21:24:22] [PASSED] test_flush
[21:24:22] [PASSED] test_lookup
[21:24:22] [PASSED] test_data
[21:24:22] [PASSED] test_class
[21:24:22] ===================== [PASSED] guc_buf =====================
[21:24:22] =================== guc_dbm (7 subtests) ===================
[21:24:22] [PASSED] test_empty
[21:24:22] [PASSED] test_default
[21:24:22] ======================== test_size  ========================
[21:24:22] [PASSED] 4
[21:24:22] [PASSED] 8
[21:24:22] [PASSED] 32
[21:24:22] [PASSED] 256
[21:24:22] ==================== [PASSED] test_size ====================
[21:24:22] ======================= test_reuse  ========================
[21:24:22] [PASSED] 4
[21:24:22] [PASSED] 8
[21:24:22] [PASSED] 32
[21:24:22] [PASSED] 256
[21:24:22] =================== [PASSED] test_reuse ====================
[21:24:22] =================== test_range_overlap  ====================
[21:24:22] [PASSED] 4
[21:24:22] [PASSED] 8
[21:24:22] [PASSED] 32
[21:24:22] [PASSED] 256
[21:24:22] =============== [PASSED] test_range_overlap ================
[21:24:22] =================== test_range_compact  ====================
[21:24:22] [PASSED] 4
[21:24:22] [PASSED] 8
[21:24:22] [PASSED] 32
[21:24:22] [PASSED] 256
[21:24:22] =============== [PASSED] test_range_compact ================
[21:24:22] ==================== test_range_spare  =====================
[21:24:22] [PASSED] 4
[21:24:22] [PASSED] 8
[21:24:22] [PASSED] 32
[21:24:22] [PASSED] 256
[21:24:22] ================ [PASSED] test_range_spare =================
[21:24:22] ===================== [PASSED] guc_dbm =====================
[21:24:22] =================== guc_idm (6 subtests) ===================
[21:24:22] [PASSED] bad_init
[21:24:22] [PASSED] no_init
[21:24:22] [PASSED] init_fini
[21:24:22] [PASSED] check_used
[21:24:22] [PASSED] check_quota
[21:24:22] [PASSED] check_all
[21:24:22] ===================== [PASSED] guc_idm =====================
[21:24:22] ================== no_relay (3 subtests) ===================
[21:24:22] [PASSED] xe_drops_guc2pf_if_not_ready
[21:24:22] [PASSED] xe_drops_guc2vf_if_not_ready
[21:24:22] [PASSED] xe_rejects_send_if_not_ready
[21:24:22] ==================== [PASSED] no_relay =====================
[21:24:22] ================== pf_relay (14 subtests) ==================
[21:24:22] [PASSED] pf_rejects_guc2pf_too_short
[21:24:22] [PASSED] pf_rejects_guc2pf_too_long
[21:24:22] [PASSED] pf_rejects_guc2pf_no_payload
[21:24:22] [PASSED] pf_fails_no_payload
[21:24:22] [PASSED] pf_fails_bad_origin
[21:24:22] [PASSED] pf_fails_bad_type
[21:24:22] [PASSED] pf_txn_reports_error
[21:24:22] [PASSED] pf_txn_sends_pf2guc
[21:24:22] [PASSED] pf_sends_pf2guc
[21:24:22] [SKIPPED] pf_loopback_nop
[21:24:22] [SKIPPED] pf_loopback_echo
[21:24:22] [SKIPPED] pf_loopback_fail
[21:24:22] [SKIPPED] pf_loopback_busy
[21:24:22] [SKIPPED] pf_loopback_retry
[21:24:22] ==================== [PASSED] pf_relay =====================
[21:24:22] ================== vf_relay (3 subtests) ===================
[21:24:22] [PASSED] vf_rejects_guc2vf_too_short
[21:24:22] [PASSED] vf_rejects_guc2vf_too_long
[21:24:22] [PASSED] vf_rejects_guc2vf_no_payload
[21:24:22] ==================== [PASSED] vf_relay =====================
[21:24:22] ================ pf_gt_config (9 subtests) =================
[21:24:22] [PASSED] fair_contexts_1vf
[21:24:22] [PASSED] fair_doorbells_1vf
[21:24:22] [PASSED] fair_ggtt_1vf
[21:24:22] ====================== fair_vram_1vf  ======================
[21:24:22] [PASSED] 3.50 GiB
[21:24:22] [PASSED] 11.5 GiB
[21:24:22] [PASSED] 15.5 GiB
[21:24:22] [PASSED] 31.5 GiB
[21:24:22] [PASSED] 63.5 GiB
[21:24:22] [PASSED] 1.91 GiB
[21:24:22] ================== [PASSED] fair_vram_1vf ==================
[21:24:22] ================ fair_vram_1vf_admin_only  =================
[21:24:22] [PASSED] 3.50 GiB
[21:24:22] [PASSED] 11.5 GiB
[21:24:22] [PASSED] 15.5 GiB
[21:24:22] [PASSED] 31.5 GiB
[21:24:22] [PASSED] 63.5 GiB
[21:24:22] [PASSED] 1.91 GiB
[21:24:22] ============ [PASSED] fair_vram_1vf_admin_only =============
[21:24:22] ====================== fair_contexts  ======================
[21:24:22] [PASSED] 1 VF
[21:24:22] [PASSED] 2 VFs
[21:24:22] [PASSED] 3 VFs
[21:24:22] [PASSED] 4 VFs
[21:24:22] [PASSED] 5 VFs
[21:24:22] [PASSED] 6 VFs
[21:24:22] [PASSED] 7 VFs
[21:24:22] [PASSED] 8 VFs
[21:24:22] [PASSED] 9 VFs
[21:24:22] [PASSED] 10 VFs
[21:24:22] [PASSED] 11 VFs
[21:24:22] [PASSED] 12 VFs
[21:24:22] [PASSED] 13 VFs
[21:24:22] [PASSED] 14 VFs
[21:24:22] [PASSED] 15 VFs
[21:24:22] [PASSED] 16 VFs
[21:24:22] [PASSED] 17 VFs
[21:24:22] [PASSED] 18 VFs
[21:24:22] [PASSED] 19 VFs
[21:24:22] [PASSED] 20 VFs
[21:24:22] [PASSED] 21 VFs
[21:24:22] [PASSED] 22 VFs
[21:24:22] [PASSED] 23 VFs
[21:24:22] [PASSED] 24 VFs
[21:24:22] [PASSED] 25 VFs
[21:24:22] [PASSED] 26 VFs
[21:24:22] [PASSED] 27 VFs
[21:24:22] [PASSED] 28 VFs
[21:24:22] [PASSED] 29 VFs
[21:24:22] [PASSED] 30 VFs
[21:24:22] [PASSED] 31 VFs
[21:24:22] [PASSED] 32 VFs
[21:24:22] [PASSED] 33 VFs
[21:24:22] [PASSED] 34 VFs
[21:24:22] [PASSED] 35 VFs
[21:24:22] [PASSED] 36 VFs
[21:24:22] [PASSED] 37 VFs
[21:24:22] [PASSED] 38 VFs
[21:24:22] [PASSED] 39 VFs
[21:24:22] [PASSED] 40 VFs
[21:24:22] [PASSED] 41 VFs
[21:24:22] [PASSED] 42 VFs
[21:24:22] [PASSED] 43 VFs
[21:24:22] [PASSED] 44 VFs
[21:24:22] [PASSED] 45 VFs
[21:24:22] [PASSED] 46 VFs
[21:24:22] [PASSED] 47 VFs
[21:24:22] [PASSED] 48 VFs
[21:24:22] [PASSED] 49 VFs
[21:24:22] [PASSED] 50 VFs
[21:24:22] [PASSED] 51 VFs
[21:24:22] [PASSED] 52 VFs
[21:24:22] [PASSED] 53 VFs
[21:24:22] [PASSED] 54 VFs
[21:24:22] [PASSED] 55 VFs
[21:24:22] [PASSED] 56 VFs
[21:24:22] [PASSED] 57 VFs
[21:24:22] [PASSED] 58 VFs
[21:24:22] [PASSED] 59 VFs
[21:24:22] [PASSED] 60 VFs
[21:24:22] [PASSED] 61 VFs
[21:24:22] [PASSED] 62 VFs
[21:24:22] [PASSED] 63 VFs
[21:24:22] ================== [PASSED] fair_contexts ==================
[21:24:22] ===================== fair_doorbells  ======================
[21:24:22] [PASSED] 1 VF
[21:24:22] [PASSED] 2 VFs
[21:24:22] [PASSED] 3 VFs
[21:24:22] [PASSED] 4 VFs
[21:24:22] [PASSED] 5 VFs
[21:24:22] [PASSED] 6 VFs
[21:24:22] [PASSED] 7 VFs
[21:24:22] [PASSED] 8 VFs
[21:24:22] [PASSED] 9 VFs
[21:24:22] [PASSED] 10 VFs
[21:24:22] [PASSED] 11 VFs
[21:24:22] [PASSED] 12 VFs
[21:24:22] [PASSED] 13 VFs
[21:24:22] [PASSED] 14 VFs
[21:24:22] [PASSED] 15 VFs
[21:24:22] [PASSED] 16 VFs
[21:24:22] [PASSED] 17 VFs
[21:24:22] [PASSED] 18 VFs
[21:24:22] [PASSED] 19 VFs
[21:24:22] [PASSED] 20 VFs
[21:24:22] [PASSED] 21 VFs
[21:24:22] [PASSED] 22 VFs
[21:24:22] [PASSED] 23 VFs
[21:24:22] [PASSED] 24 VFs
[21:24:22] [PASSED] 25 VFs
[21:24:22] [PASSED] 26 VFs
[21:24:22] [PASSED] 27 VFs
[21:24:22] [PASSED] 28 VFs
[21:24:22] [PASSED] 29 VFs
[21:24:22] [PASSED] 30 VFs
[21:24:22] [PASSED] 31 VFs
[21:24:22] [PASSED] 32 VFs
[21:24:22] [PASSED] 33 VFs
[21:24:22] [PASSED] 34 VFs
[21:24:22] [PASSED] 35 VFs
[21:24:22] [PASSED] 36 VFs
[21:24:22] [PASSED] 37 VFs
[21:24:22] [PASSED] 38 VFs
[21:24:22] [PASSED] 39 VFs
[21:24:22] [PASSED] 40 VFs
[21:24:22] [PASSED] 41 VFs
[21:24:22] [PASSED] 42 VFs
[21:24:22] [PASSED] 43 VFs
[21:24:22] [PASSED] 44 VFs
[21:24:22] [PASSED] 45 VFs
[21:24:22] [PASSED] 46 VFs
[21:24:22] [PASSED] 47 VFs
[21:24:22] [PASSED] 48 VFs
[21:24:22] [PASSED] 49 VFs
[21:24:22] [PASSED] 50 VFs
[21:24:22] [PASSED] 51 VFs
[21:24:22] [PASSED] 52 VFs
[21:24:22] [PASSED] 53 VFs
[21:24:22] [PASSED] 54 VFs
[21:24:22] [PASSED] 55 VFs
[21:24:22] [PASSED] 56 VFs
[21:24:22] [PASSED] 57 VFs
[21:24:22] [PASSED] 58 VFs
[21:24:22] [PASSED] 59 VFs
[21:24:22] [PASSED] 60 VFs
[21:24:22] [PASSED] 61 VFs
[21:24:22] [PASSED] 62 VFs
[21:24:22] [PASSED] 63 VFs
[21:24:22] ================= [PASSED] fair_doorbells ==================
[21:24:22] ======================== fair_ggtt  ========================
[21:24:22] [PASSED] 1 VF
[21:24:22] [PASSED] 2 VFs
[21:24:22] [PASSED] 3 VFs
[21:24:22] [PASSED] 4 VFs
[21:24:22] [PASSED] 5 VFs
[21:24:22] [PASSED] 6 VFs
[21:24:22] [PASSED] 7 VFs
[21:24:22] [PASSED] 8 VFs
[21:24:22] [PASSED] 9 VFs
[21:24:22] [PASSED] 10 VFs
[21:24:22] [PASSED] 11 VFs
[21:24:22] [PASSED] 12 VFs
[21:24:22] [PASSED] 13 VFs
[21:24:22] [PASSED] 14 VFs
[21:24:22] [PASSED] 15 VFs
[21:24:22] [PASSED] 16 VFs
[21:24:22] [PASSED] 17 VFs
[21:24:22] [PASSED] 18 VFs
[21:24:22] [PASSED] 19 VFs
[21:24:22] [PASSED] 20 VFs
[21:24:22] [PASSED] 21 VFs
[21:24:22] [PASSED] 22 VFs
[21:24:22] [PASSED] 23 VFs
[21:24:22] [PASSED] 24 VFs
[21:24:22] [PASSED] 25 VFs
[21:24:22] [PASSED] 26 VFs
[21:24:22] [PASSED] 27 VFs
[21:24:22] [PASSED] 28 VFs
[21:24:22] [PASSED] 29 VFs
[21:24:22] [PASSED] 30 VFs
[21:24:22] [PASSED] 31 VFs
[21:24:22] [PASSED] 32 VFs
[21:24:22] [PASSED] 33 VFs
[21:24:22] [PASSED] 34 VFs
[21:24:22] [PASSED] 35 VFs
[21:24:22] [PASSED] 36 VFs
[21:24:22] [PASSED] 37 VFs
[21:24:22] [PASSED] 38 VFs
[21:24:22] [PASSED] 39 VFs
[21:24:22] [PASSED] 40 VFs
[21:24:22] [PASSED] 41 VFs
[21:24:22] [PASSED] 42 VFs
[21:24:22] [PASSED] 43 VFs
[21:24:22] [PASSED] 44 VFs
[21:24:22] [PASSED] 45 VFs
[21:24:22] [PASSED] 46 VFs
[21:24:22] [PASSED] 47 VFs
[21:24:22] [PASSED] 48 VFs
[21:24:22] [PASSED] 49 VFs
[21:24:22] [PASSED] 50 VFs
[21:24:22] [PASSED] 51 VFs
[21:24:22] [PASSED] 52 VFs
[21:24:22] [PASSED] 53 VFs
[21:24:22] [PASSED] 54 VFs
[21:24:22] [PASSED] 55 VFs
[21:24:22] [PASSED] 56 VFs
[21:24:22] [PASSED] 57 VFs
[21:24:22] [PASSED] 58 VFs
[21:24:22] [PASSED] 59 VFs
[21:24:22] [PASSED] 60 VFs
[21:24:22] [PASSED] 61 VFs
[21:24:22] [PASSED] 62 VFs
[21:24:22] [PASSED] 63 VFs
[21:24:22] ==================== [PASSED] fair_ggtt ====================
[21:24:22] ======================== fair_vram  ========================
[21:24:22] [PASSED] 1 VF
[21:24:22] [PASSED] 2 VFs
[21:24:22] [PASSED] 3 VFs
[21:24:22] [PASSED] 4 VFs
[21:24:22] [PASSED] 5 VFs
[21:24:22] [PASSED] 6 VFs
[21:24:22] [PASSED] 7 VFs
[21:24:22] [PASSED] 8 VFs
[21:24:22] [PASSED] 9 VFs
[21:24:22] [PASSED] 10 VFs
[21:24:22] [PASSED] 11 VFs
[21:24:22] [PASSED] 12 VFs
[21:24:22] [PASSED] 13 VFs
[21:24:22] [PASSED] 14 VFs
[21:24:22] [PASSED] 15 VFs
[21:24:22] [PASSED] 16 VFs
[21:24:22] [PASSED] 17 VFs
[21:24:22] [PASSED] 18 VFs
[21:24:22] [PASSED] 19 VFs
[21:24:22] [PASSED] 20 VFs
[21:24:22] [PASSED] 21 VFs
[21:24:22] [PASSED] 22 VFs
[21:24:22] [PASSED] 23 VFs
[21:24:22] [PASSED] 24 VFs
[21:24:22] [PASSED] 25 VFs
[21:24:22] [PASSED] 26 VFs
[21:24:22] [PASSED] 27 VFs
[21:24:22] [PASSED] 28 VFs
[21:24:22] [PASSED] 29 VFs
[21:24:22] [PASSED] 30 VFs
[21:24:22] [PASSED] 31 VFs
[21:24:22] [PASSED] 32 VFs
[21:24:22] [PASSED] 33 VFs
[21:24:22] [PASSED] 34 VFs
[21:24:22] [PASSED] 35 VFs
[21:24:22] [PASSED] 36 VFs
[21:24:22] [PASSED] 37 VFs
[21:24:22] [PASSED] 38 VFs
[21:24:22] [PASSED] 39 VFs
[21:24:22] [PASSED] 40 VFs
[21:24:22] [PASSED] 41 VFs
[21:24:22] [PASSED] 42 VFs
[21:24:22] [PASSED] 43 VFs
[21:24:22] [PASSED] 44 VFs
[21:24:22] [PASSED] 45 VFs
[21:24:22] [PASSED] 46 VFs
[21:24:22] [PASSED] 47 VFs
[21:24:22] [PASSED] 48 VFs
[21:24:22] [PASSED] 49 VFs
[21:24:22] [PASSED] 50 VFs
[21:24:22] [PASSED] 51 VFs
[21:24:22] [PASSED] 52 VFs
[21:24:22] [PASSED] 53 VFs
[21:24:22] [PASSED] 54 VFs
[21:24:22] [PASSED] 55 VFs
[21:24:22] [PASSED] 56 VFs
[21:24:22] [PASSED] 57 VFs
[21:24:22] [PASSED] 58 VFs
[21:24:22] [PASSED] 59 VFs
[21:24:22] [PASSED] 60 VFs
[21:24:22] [PASSED] 61 VFs
[21:24:22] [PASSED] 62 VFs
[21:24:22] [PASSED] 63 VFs
[21:24:22] ==================== [PASSED] fair_vram ====================
[21:24:22] ================== [PASSED] pf_gt_config ===================
[21:24:22] ===================== lmtt (1 subtest) =====================
[21:24:22] ======================== test_ops  =========================
[21:24:22] [PASSED] 2-level
[21:24:22] [PASSED] multi-level
[21:24:22] ==================== [PASSED] test_ops =====================
[21:24:22] ====================== [PASSED] lmtt =======================
[21:24:22] ================= pf_service (11 subtests) =================
[21:24:22] [PASSED] pf_negotiate_any
[21:24:22] [PASSED] pf_negotiate_base_match
[21:24:22] [PASSED] pf_negotiate_base_newer
[21:24:22] [PASSED] pf_negotiate_base_next
[21:24:22] [SKIPPED] pf_negotiate_base_older
[21:24:22] [PASSED] pf_negotiate_base_prev
[21:24:22] [PASSED] pf_negotiate_latest_match
[21:24:22] [PASSED] pf_negotiate_latest_newer
[21:24:22] [PASSED] pf_negotiate_latest_next
[21:24:22] [SKIPPED] pf_negotiate_latest_older
[21:24:22] [SKIPPED] pf_negotiate_latest_prev
[21:24:22] =================== [PASSED] pf_service ====================
[21:24:22] ================= xe_guc_g2g (2 subtests) ==================
[21:24:22] ============== xe_live_guc_g2g_kunit_default  ==============
[21:24:22] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[21:24:22] ============== xe_live_guc_g2g_kunit_allmem  ===============
[21:24:22] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[21:24:22] =================== [SKIPPED] xe_guc_g2g ===================
[21:24:22] =================== xe_mocs (2 subtests) ===================
[21:24:22] ================ xe_live_mocs_kernel_kunit  ================
[21:24:22] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[21:24:22] ================ xe_live_mocs_reset_kunit  =================
[21:24:22] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[21:24:22] ==================== [SKIPPED] xe_mocs =====================
[21:24:22] ================= xe_migrate (2 subtests) ==================
[21:24:22] ================= xe_migrate_sanity_kunit  =================
[21:24:22] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[21:24:22] ================== xe_validate_ccs_kunit  ==================
[21:24:22] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[21:24:22] =================== [SKIPPED] xe_migrate ===================
[21:24:22] ================== xe_dma_buf (1 subtest) ==================
[21:24:22] ==================== xe_dma_buf_kunit  =====================
[21:24:22] ================ [SKIPPED] xe_dma_buf_kunit ================
[21:24:22] =================== [SKIPPED] xe_dma_buf ===================
[21:24:22] ================= xe_bo_shrink (1 subtest) =================
[21:24:22] =================== xe_bo_shrink_kunit  ====================
[21:24:22] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[21:24:22] ================== [SKIPPED] xe_bo_shrink ==================
[21:24:22] ==================== xe_bo (2 subtests) ====================
[21:24:22] ================== xe_ccs_migrate_kunit  ===================
[21:24:22] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[21:24:22] ==================== xe_bo_evict_kunit  ====================
[21:24:22] =============== [SKIPPED] xe_bo_evict_kunit ================
[21:24:22] ===================== [SKIPPED] xe_bo ======================
[21:24:22] ==================== args (13 subtests) ====================
[21:24:22] [PASSED] count_args_test
[21:24:22] [PASSED] call_args_example
[21:24:22] [PASSED] call_args_test
[21:24:22] [PASSED] drop_first_arg_example
[21:24:22] [PASSED] drop_first_arg_test
[21:24:22] [PASSED] first_arg_example
[21:24:22] [PASSED] first_arg_test
[21:24:22] [PASSED] last_arg_example
[21:24:22] [PASSED] last_arg_test
[21:24:22] [PASSED] pick_arg_example
[21:24:22] [PASSED] if_args_example
[21:24:22] [PASSED] if_args_test
[21:24:22] [PASSED] sep_comma_example
[21:24:22] ====================== [PASSED] args =======================
[21:24:22] =================== xe_pci (3 subtests) ====================
[21:24:22] ==================== check_graphics_ip  ====================
[21:24:22] [PASSED] 12.00 Xe_LP
[21:24:22] [PASSED] 12.10 Xe_LP+
[21:24:22] [PASSED] 12.55 Xe_HPG
[21:24:22] [PASSED] 12.60 Xe_HPC
[21:24:22] [PASSED] 12.70 Xe_LPG
[21:24:22] [PASSED] 12.71 Xe_LPG
[21:24:22] [PASSED] 12.74 Xe_LPG+
[21:24:22] [PASSED] 20.01 Xe2_HPG
[21:24:22] [PASSED] 20.02 Xe2_HPG
[21:24:22] [PASSED] 20.04 Xe2_LPG
[21:24:22] [PASSED] 30.00 Xe3_LPG
[21:24:22] [PASSED] 30.01 Xe3_LPG
[21:24:22] [PASSED] 30.03 Xe3_LPG
[21:24:22] [PASSED] 30.04 Xe3_LPG
[21:24:22] [PASSED] 30.05 Xe3_LPG
[21:24:22] [PASSED] 35.10 Xe3p_LPG
[21:24:22] [PASSED] 35.11 Xe3p_XPC
[21:24:22] ================ [PASSED] check_graphics_ip ================
[21:24:22] ===================== check_media_ip  ======================
[21:24:22] [PASSED] 12.00 Xe_M
[21:24:22] [PASSED] 12.55 Xe_HPM
[21:24:22] [PASSED] 13.00 Xe_LPM+
[21:24:22] [PASSED] 13.01 Xe2_HPM
[21:24:22] [PASSED] 20.00 Xe2_LPM
[21:24:22] [PASSED] 30.00 Xe3_LPM
[21:24:22] [PASSED] 30.02 Xe3_LPM
[21:24:22] [PASSED] 35.00 Xe3p_LPM
[21:24:22] [PASSED] 35.03 Xe3p_HPM
[21:24:22] ================= [PASSED] check_media_ip ==================
[21:24:22] =================== check_platform_desc  ===================
[21:24:22] [PASSED] 0x9A60 (TIGERLAKE)
[21:24:22] [PASSED] 0x9A68 (TIGERLAKE)
[21:24:22] [PASSED] 0x9A70 (TIGERLAKE)
[21:24:22] [PASSED] 0x9A40 (TIGERLAKE)
[21:24:22] [PASSED] 0x9A49 (TIGERLAKE)
[21:24:22] [PASSED] 0x9A59 (TIGERLAKE)
[21:24:22] [PASSED] 0x9A78 (TIGERLAKE)
[21:24:22] [PASSED] 0x9AC0 (TIGERLAKE)
[21:24:22] [PASSED] 0x9AC9 (TIGERLAKE)
[21:24:22] [PASSED] 0x9AD9 (TIGERLAKE)
[21:24:22] [PASSED] 0x9AF8 (TIGERLAKE)
[21:24:22] [PASSED] 0x4C80 (ROCKETLAKE)
[21:24:22] [PASSED] 0x4C8A (ROCKETLAKE)
[21:24:22] [PASSED] 0x4C8B (ROCKETLAKE)
[21:24:22] [PASSED] 0x4C8C (ROCKETLAKE)
[21:24:22] [PASSED] 0x4C90 (ROCKETLAKE)
[21:24:22] [PASSED] 0x4C9A (ROCKETLAKE)
[21:24:22] [PASSED] 0x4680 (ALDERLAKE_S)
[21:24:22] [PASSED] 0x4682 (ALDERLAKE_S)
[21:24:22] [PASSED] 0x4688 (ALDERLAKE_S)
[21:24:22] [PASSED] 0x468A (ALDERLAKE_S)
[21:24:22] [PASSED] 0x468B (ALDERLAKE_S)
[21:24:22] [PASSED] 0x4690 (ALDERLAKE_S)
[21:24:22] [PASSED] 0x4692 (ALDERLAKE_S)
[21:24:22] [PASSED] 0x4693 (ALDERLAKE_S)
[21:24:22] [PASSED] 0x46A0 (ALDERLAKE_P)
[21:24:22] [PASSED] 0x46A1 (ALDERLAKE_P)
[21:24:22] [PASSED] 0x46A2 (ALDERLAKE_P)
[21:24:22] [PASSED] 0x46A3 (ALDERLAKE_P)
[21:24:22] [PASSED] 0x46A6 (ALDERLAKE_P)
[21:24:22] [PASSED] 0x46A8 (ALDERLAKE_P)
[21:24:22] [PASSED] 0x46AA (ALDERLAKE_P)
[21:24:22] [PASSED] 0x462A (ALDERLAKE_P)
[21:24:22] [PASSED] 0x4626 (ALDERLAKE_P)
[21:24:22] [PASSED] 0x4628 (ALDERLAKE_P)
[21:24:22] [PASSED] 0x46B0 (ALDERLAKE_P)
[21:24:22] [PASSED] 0x46B1 (ALDERLAKE_P)
[21:24:22] [PASSED] 0x46B2 (ALDERLAKE_P)
[21:24:22] [PASSED] 0x46B3 (ALDERLAKE_P)
[21:24:22] [PASSED] 0x46C0 (ALDERLAKE_P)
[21:24:22] [PASSED] 0x46C1 (ALDERLAKE_P)
[21:24:22] [PASSED] 0x46C2 (ALDERLAKE_P)
[21:24:22] [PASSED] 0x46C3 (ALDERLAKE_P)
[21:24:22] [PASSED] 0x46D0 (ALDERLAKE_N)
[21:24:22] [PASSED] 0x46D1 (ALDERLAKE_N)
[21:24:22] [PASSED] 0x46D2 (ALDERLAKE_N)
[21:24:22] [PASSED] 0x46D3 (ALDERLAKE_N)
[21:24:22] [PASSED] 0x46D4 (ALDERLAKE_N)
[21:24:22] [PASSED] 0xA721 (ALDERLAKE_P)
[21:24:22] [PASSED] 0xA7A1 (ALDERLAKE_P)
[21:24:22] [PASSED] 0xA7A9 (ALDERLAKE_P)
[21:24:22] [PASSED] 0xA7AC (ALDERLAKE_P)
[21:24:22] [PASSED] 0xA7AD (ALDERLAKE_P)
[21:24:22] [PASSED] 0xA720 (ALDERLAKE_P)
[21:24:22] [PASSED] 0xA7A0 (ALDERLAKE_P)
[21:24:22] [PASSED] 0xA7A8 (ALDERLAKE_P)
[21:24:22] [PASSED] 0xA7AA (ALDERLAKE_P)
[21:24:22] [PASSED] 0xA7AB (ALDERLAKE_P)
[21:24:22] [PASSED] 0xA780 (ALDERLAKE_S)
[21:24:22] [PASSED] 0xA781 (ALDERLAKE_S)
[21:24:22] [PASSED] 0xA782 (ALDERLAKE_S)
[21:24:22] [PASSED] 0xA783 (ALDERLAKE_S)
[21:24:22] [PASSED] 0xA788 (ALDERLAKE_S)
[21:24:22] [PASSED] 0xA789 (ALDERLAKE_S)
[21:24:22] [PASSED] 0xA78A (ALDERLAKE_S)
[21:24:22] [PASSED] 0xA78B (ALDERLAKE_S)
[21:24:22] [PASSED] 0x4905 (DG1)
[21:24:22] [PASSED] 0x4906 (DG1)
[21:24:22] [PASSED] 0x4907 (DG1)
[21:24:22] [PASSED] 0x4908 (DG1)
[21:24:22] [PASSED] 0x4909 (DG1)
[21:24:22] [PASSED] 0x56C0 (DG2)
[21:24:22] [PASSED] 0x56C2 (DG2)
[21:24:22] [PASSED] 0x56C1 (DG2)
[21:24:22] [PASSED] 0x7D51 (METEORLAKE)
[21:24:22] [PASSED] 0x7DD1 (METEORLAKE)
[21:24:22] [PASSED] 0x7D41 (METEORLAKE)
[21:24:22] [PASSED] 0x7D67 (METEORLAKE)
[21:24:22] [PASSED] 0xB640 (METEORLAKE)
[21:24:22] [PASSED] 0x56A0 (DG2)
[21:24:22] [PASSED] 0x56A1 (DG2)
[21:24:22] [PASSED] 0x56A2 (DG2)
[21:24:22] [PASSED] 0x56BE (DG2)
[21:24:22] [PASSED] 0x56BF (DG2)
[21:24:22] [PASSED] 0x5690 (DG2)
[21:24:22] [PASSED] 0x5691 (DG2)
[21:24:22] [PASSED] 0x5692 (DG2)
[21:24:22] [PASSED] 0x56A5 (DG2)
[21:24:22] [PASSED] 0x56A6 (DG2)
[21:24:22] [PASSED] 0x56B0 (DG2)
[21:24:22] [PASSED] 0x56B1 (DG2)
[21:24:22] [PASSED] 0x56BA (DG2)
[21:24:22] [PASSED] 0x56BB (DG2)
[21:24:22] [PASSED] 0x56BC (DG2)
[21:24:22] [PASSED] 0x56BD (DG2)
[21:24:22] [PASSED] 0x5693 (DG2)
[21:24:22] [PASSED] 0x5694 (DG2)
[21:24:22] [PASSED] 0x5695 (DG2)
[21:24:22] [PASSED] 0x56A3 (DG2)
[21:24:22] [PASSED] 0x56A4 (DG2)
[21:24:22] [PASSED] 0x56B2 (DG2)
[21:24:22] [PASSED] 0x56B3 (DG2)
[21:24:22] [PASSED] 0x5696 (DG2)
[21:24:22] [PASSED] 0x5697 (DG2)
[21:24:22] [PASSED] 0xB69 (PVC)
[21:24:22] [PASSED] 0xB6E (PVC)
[21:24:22] [PASSED] 0xBD4 (PVC)
[21:24:22] [PASSED] 0xBD5 (PVC)
[21:24:22] [PASSED] 0xBD6 (PVC)
[21:24:22] [PASSED] 0xBD7 (PVC)
[21:24:22] [PASSED] 0xBD8 (PVC)
[21:24:22] [PASSED] 0xBD9 (PVC)
[21:24:22] [PASSED] 0xBDA (PVC)
[21:24:22] [PASSED] 0xBDB (PVC)
[21:24:22] [PASSED] 0xBE0 (PVC)
[21:24:22] [PASSED] 0xBE1 (PVC)
[21:24:22] [PASSED] 0xBE5 (PVC)
[21:24:22] [PASSED] 0x7D40 (METEORLAKE)
[21:24:22] [PASSED] 0x7D45 (METEORLAKE)
[21:24:22] [PASSED] 0x7D55 (METEORLAKE)
[21:24:22] [PASSED] 0x7D60 (METEORLAKE)
[21:24:22] [PASSED] 0x7DD5 (METEORLAKE)
[21:24:22] [PASSED] 0x6420 (LUNARLAKE)
[21:24:22] [PASSED] 0x64A0 (LUNARLAKE)
[21:24:22] [PASSED] 0x64B0 (LUNARLAKE)
[21:24:22] [PASSED] 0xE202 (BATTLEMAGE)
[21:24:22] [PASSED] 0xE209 (BATTLEMAGE)
[21:24:22] [PASSED] 0xE20B (BATTLEMAGE)
[21:24:22] [PASSED] 0xE20C (BATTLEMAGE)
[21:24:22] [PASSED] 0xE20D (BATTLEMAGE)
[21:24:22] [PASSED] 0xE210 (BATTLEMAGE)
[21:24:22] [PASSED] 0xE211 (BATTLEMAGE)
[21:24:22] [PASSED] 0xE212 (BATTLEMAGE)
[21:24:22] [PASSED] 0xE216 (BATTLEMAGE)
[21:24:22] [PASSED] 0xE220 (BATTLEMAGE)
[21:24:22] [PASSED] 0xE221 (BATTLEMAGE)
[21:24:22] [PASSED] 0xE222 (BATTLEMAGE)
[21:24:22] [PASSED] 0xE223 (BATTLEMAGE)
[21:24:22] [PASSED] 0xB080 (PANTHERLAKE)
[21:24:22] [PASSED] 0xB081 (PANTHERLAKE)
[21:24:22] [PASSED] 0xB082 (PANTHERLAKE)
[21:24:22] [PASSED] 0xB083 (PANTHERLAKE)
[21:24:22] [PASSED] 0xB084 (PANTHERLAKE)
[21:24:22] [PASSED] 0xB085 (PANTHERLAKE)
[21:24:22] [PASSED] 0xB086 (PANTHERLAKE)
[21:24:22] [PASSED] 0xB087 (PANTHERLAKE)
[21:24:22] [PASSED] 0xB08F (PANTHERLAKE)
[21:24:22] [PASSED] 0xB090 (PANTHERLAKE)
[21:24:22] [PASSED] 0xB0A0 (PANTHERLAKE)
[21:24:22] [PASSED] 0xB0B0 (PANTHERLAKE)
[21:24:22] [PASSED] 0xFD80 (PANTHERLAKE)
[21:24:22] [PASSED] 0xFD81 (PANTHERLAKE)
[21:24:22] [PASSED] 0xD740 (NOVALAKE_S)
[21:24:22] [PASSED] 0xD741 (NOVALAKE_S)
[21:24:22] [PASSED] 0xD742 (NOVALAKE_S)
[21:24:22] [PASSED] 0xD743 (NOVALAKE_S)
[21:24:22] [PASSED] 0xD744 (NOVALAKE_S)
[21:24:22] [PASSED] 0xD745 (NOVALAKE_S)
[21:24:22] [PASSED] 0x674C (CRESCENTISLAND)
[21:24:22] [PASSED] 0x674D (CRESCENTISLAND)
[21:24:22] [PASSED] 0x674E (CRESCENTISLAND)
[21:24:22] [PASSED] 0x674F (CRESCENTISLAND)
[21:24:22] [PASSED] 0x6750 (CRESCENTISLAND)
[21:24:22] [PASSED] 0xD750 (NOVALAKE_P)
[21:24:22] [PASSED] 0xD751 (NOVALAKE_P)
[21:24:22] [PASSED] 0xD752 (NOVALAKE_P)
[21:24:22] [PASSED] 0xD753 (NOVALAKE_P)
[21:24:22] [PASSED] 0xD754 (NOVALAKE_P)
[21:24:22] [PASSED] 0xD755 (NOVALAKE_P)
[21:24:22] [PASSED] 0xD756 (NOVALAKE_P)
[21:24:22] [PASSED] 0xD757 (NOVALAKE_P)
[21:24:22] [PASSED] 0xD75F (NOVALAKE_P)
[21:24:22] =============== [PASSED] check_platform_desc ===============
[21:24:22] ===================== [PASSED] xe_pci ======================
[21:24:22] ============= xe_rtp_tables_test (4 subtests) ==============
[21:24:22] ================== xe_rtp_table_gt_test  ===================
[21:24:22] [PASSED] gt_was/14011060649
[21:24:22] [PASSED] gt_was/14011059788
[21:24:22] [PASSED] gt_was/14015795083
[21:24:22] [PASSED] gt_was/16021867713
[21:24:22] [PASSED] gt_was/14019449301
[21:24:22] [PASSED] gt_was/16028005424
[21:24:22] [PASSED] gt_was/14026578760
[21:24:22] [PASSED] gt_was/1409420604
[21:24:22] [PASSED] gt_was/1408615072
[21:24:22] [PASSED] gt_was/22010523718
[21:24:22] [PASSED] gt_was/14011006942
[21:24:22] [PASSED] gt_was/14014830051
[21:24:22] [PASSED] gt_was/18018781329
[21:24:22] [PASSED] gt_was/1509235366
[21:24:22] [PASSED] gt_was/18018781329
[21:24:22] [PASSED] gt_was/16016694945
[21:24:22] [PASSED] gt_was/14018575942
[21:24:22] [PASSED] gt_was/22016670082
[21:24:22] [PASSED] gt_was/22016670082
[21:24:22] [PASSED] gt_was/14017421178
[21:24:22] [PASSED] gt_was/16025250150
[21:24:22] [PASSED] gt_was/14021871409
[21:24:22] [PASSED] gt_was/16021865536
[21:24:22] [PASSED] gt_was/14021486841
[21:24:22] [PASSED] gt_was/14025160223
[21:24:22] [PASSED] gt_was/14026144927, 16029437861
[21:24:22] [PASSED] gt_was/14025635424
[21:24:22] [PASSED] gt_was/16028005424
[21:24:22] ============== [PASSED] xe_rtp_table_gt_test ===============
[21:24:22] ================== xe_rtp_table_gt_test  ===================
[21:24:22] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[21:24:22] [PASSED] gt_tunings/Tuning: 32B Access Enable
[21:24:22] [PASSED] gt_tunings/Tuning: L3 cache
[21:24:22] [PASSED] gt_tunings/Tuning: L3 cache - media
[21:24:22] [PASSED] gt_tunings/Tuning: Compression Overfetch
[21:24:22] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[21:24:22] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[21:24:22] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[21:24:22] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[21:24:22] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[21:24:22] [PASSED] gt_tunings/Tuning: Stateless compression control
[21:24:22] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[21:24:22] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[21:24:22] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[21:24:22] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[21:24:22] ============== [PASSED] xe_rtp_table_gt_test ===============
[21:24:22] ================== xe_rtp_table_oob_test  ==================
[21:24:22] [PASSED] oob_was/1607983814
[21:24:22] [PASSED] oob_was/16010904313
[21:24:22] [PASSED] oob_was/18022495364
[21:24:22] [PASSED] oob_was/22012773006
[21:24:22] [PASSED] oob_was/14014475959
[21:24:22] [PASSED] oob_was/22011391025
[21:24:22] [PASSED] oob_was/22012727170
[21:24:22] [PASSED] oob_was/22012727685
[21:24:22] [PASSED] oob_was/22016596838
[21:24:22] [PASSED] oob_was/18020744125
[21:24:22] [PASSED] oob_was/1409600907
[21:24:22] [PASSED] oob_was/22014953428
[21:24:22] [PASSED] oob_was/16017236439
[21:24:22] [PASSED] oob_was/14019821291
[21:24:22] [PASSED] oob_was/14015076503
[21:24:22] [PASSED] oob_was/14018913170
[21:24:22] [PASSED] oob_was/14018094691
[21:24:22] [PASSED] oob_was/18024947630
[21:24:22] [PASSED] oob_was/16022287689
[21:24:22] [PASSED] oob_was/13011645652
[21:24:22] [PASSED] oob_was/14022293748
[21:24:22] [PASSED] oob_was/22019794406
[21:24:22] [PASSED] oob_was/22019338487
[21:24:22] [PASSED] oob_was/16023588340
[21:24:22] [PASSED] oob_was/14019789679
[21:24:22] [PASSED] oob_was/14022866841
[21:24:22] [PASSED] oob_was/16021333562
[21:24:22] [PASSED] oob_was/14016712196
[21:24:22] [PASSED] oob_was/14015568240
[21:24:22] [PASSED] oob_was/18013179988
[21:24:22] [PASSED] oob_was/1508761755
[21:24:22] [PASSED] oob_was/16023105232
[21:24:22] [PASSED] oob_was/16026508708
[21:24:22] [PASSED] oob_was/14020001231
[21:24:22] [PASSED] oob_was/16023683509
[21:24:22] [PASSED] oob_was/14025515070
[21:24:22] [PASSED] oob_was/15015404425_disable
[21:24:22] [PASSED] oob_was/16026007364
[21:24:22] [PASSED] oob_was/14020316580
[21:24:22] [PASSED] oob_was/14025883347
[21:24:22] ============== [PASSED] xe_rtp_table_oob_test ==============
[21:24:22] ================ xe_rtp_table_dev_oob_test  ================
[21:24:22] [PASSED] device_oob_was/22010954014
[21:24:22] [PASSED] device_oob_was/15015404425
[21:24:22] [PASSED] device_oob_was/22019338487_display
[21:24:22] [PASSED] device_oob_was/14022085890
[21:24:22] [PASSED] device_oob_was/14026539277
[21:24:22] [PASSED] device_oob_was/14026633728
[21:24:22] [PASSED] device_oob_was/14026746987
[21:24:22] [PASSED] device_oob_was/14026779378
[21:24:22] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[21:24:22] =============== [PASSED] xe_rtp_tables_test ================
[21:24:22] =================== xe_rtp (3 subtests) ====================
[21:24:22] =================== xe_rtp_rules_tests  ====================
[21:24:22] [PASSED] no
[21:24:22] [PASSED] yes
[21:24:22] [PASSED] no-and-no
[21:24:22] [PASSED] no-and-yes
[21:24:22] [PASSED] yes-and-no
[21:24:22] [PASSED] yes-and-yes
[21:24:22] [PASSED] no-or-no
[21:24:22] [PASSED] no-or-yes
[21:24:22] [PASSED] yes-or-no
[21:24:22] [PASSED] yes-or-yes
[21:24:22] [PASSED] no-yes-or-yes-no
[21:24:22] [PASSED] no-yes-or-yes-yes
[21:24:22] [PASSED] yes-yes-or-no-yes
[21:24:22] [PASSED] yes-yes-or-yes-yes
[21:24:22] [PASSED] no-no-or-yes-or-no
[21:24:22] [PASSED] or
[21:24:22] [PASSED] or-yes
[21:24:22] [PASSED] or-no
[21:24:22] [PASSED] yes-or
[21:24:22] [PASSED] no-or
[21:24:22] [PASSED] no-or-or-yes
[21:24:22] [PASSED] yes-or-or-no
[21:24:22] [PASSED] no-or-or-no
[21:24:22] [PASSED] missing-context-engine-class
[21:24:22] [PASSED] missing-context-engine-class-or-yes
[21:24:22] [PASSED] missing-context-engine-class-or-or-yes
[21:24:22] =============== [PASSED] xe_rtp_rules_tests ================
[21:24:22] =============== xe_rtp_process_to_sr_tests  ================
[21:24:22] [PASSED] coalesce-same-reg
[21:24:22] [PASSED] no-match-no-add
[21:24:22] [PASSED] two-regs-two-entries
[21:24:22] [PASSED] clr-one-set-other
[21:24:22] [PASSED] set-field
[21:24:22] [PASSED] conflict-duplicate
[21:24:22] [PASSED] conflict-not-disjoint
[21:24:22] [PASSED] conflict-reg-type
[21:24:22] [PASSED] bad-mcr-reg-forced-to-regular
[21:24:22] [PASSED] bad-regular-reg-forced-to-mcr
[21:24:22] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[21:24:22] ================== xe_rtp_process_tests  ===================
[21:24:22] [PASSED] active1
[21:24:22] [PASSED] active2
[21:24:22] [PASSED] active-inactive
[21:24:22] [PASSED] inactive-active
[21:24:22] [PASSED] inactive-active-inactive
[21:24:22] [PASSED] inactive-inactive-inactive
[21:24:22] ============== [PASSED] xe_rtp_process_tests ===============
[21:24:22] ===================== [PASSED] xe_rtp ======================
[21:24:22] ==================== xe_wa (1 subtest) =====================
[21:24:22] ======================== xe_wa_gt  =========================
[21:24:22] [PASSED] TIGERLAKE B0
[21:24:22] [PASSED] DG1 A0
[21:24:22] [PASSED] DG1 B0
[21:24:22] [PASSED] ALDERLAKE_S A0
[21:24:22] [PASSED] ALDERLAKE_S B0
[21:24:22] [PASSED] ALDERLAKE_S C0
[21:24:22] [PASSED] ALDERLAKE_S D0
[21:24:22] [PASSED] ALDERLAKE_P A0
[21:24:22] [PASSED] ALDERLAKE_P B0
[21:24:22] [PASSED] ALDERLAKE_P C0
[21:24:22] [PASSED] ALDERLAKE_S RPLS D0
[21:24:22] [PASSED] ALDERLAKE_P RPLU E0
[21:24:22] [PASSED] DG2 G10 C0
[21:24:22] [PASSED] DG2 G11 B1
[21:24:22] [PASSED] DG2 G12 A1
[21:24:22] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:24:22] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:24:22] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[21:24:22] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[21:24:22] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[21:24:22] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[21:24:22] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[21:24:22] ==================== [PASSED] xe_wa_gt =====================
[21:24:22] ====================== [PASSED] xe_wa ======================
[21:24:22] ============================================================
[21:24:22] Testing complete. Ran 715 tests: passed: 697, skipped: 18
[21:24:22] Elapsed time: 39.011s total, 6.757s configuring, 31.588s building, 0.639s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[21:24:22] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:24:24] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:24:48] Starting KUnit Kernel (1/1)...
[21:24:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:24:48] ============ drm_test_pick_cmdline (2 subtests) ============
[21:24:48] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[21:24:48] =============== drm_test_pick_cmdline_named  ===============
[21:24:48] [PASSED] NTSC
[21:24:48] [PASSED] NTSC-J
[21:24:48] [PASSED] PAL
[21:24:48] [PASSED] PAL-M
[21:24:48] =========== [PASSED] drm_test_pick_cmdline_named ===========
[21:24:48] ============== [PASSED] drm_test_pick_cmdline ==============
[21:24:48] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[21:24:48] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[21:24:48] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[21:24:48] =========== drm_validate_clone_mode (2 subtests) ===========
[21:24:48] ============== drm_test_check_in_clone_mode  ===============
[21:24:48] [PASSED] in_clone_mode
[21:24:48] [PASSED] not_in_clone_mode
[21:24:48] ========== [PASSED] drm_test_check_in_clone_mode ===========
[21:24:48] =============== drm_test_check_valid_clones  ===============
[21:24:48] [PASSED] not_in_clone_mode
[21:24:48] [PASSED] valid_clone
[21:24:48] [PASSED] invalid_clone
[21:24:48] =========== [PASSED] drm_test_check_valid_clones ===========
[21:24:48] ============= [PASSED] drm_validate_clone_mode =============
[21:24:48] ============= drm_validate_modeset (1 subtest) =============
[21:24:48] [PASSED] drm_test_check_connector_changed_modeset
[21:24:48] ============== [PASSED] drm_validate_modeset ===============
[21:24:48] ====== drm_test_bridge_get_current_state (2 subtests) ======
[21:24:48] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[21:24:48] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[21:24:48] ======== [PASSED] drm_test_bridge_get_current_state ========
[21:24:48] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[21:24:48] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[21:24:48] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[21:24:48] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[21:24:48] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[21:24:48] ============== drm_bridge_alloc (2 subtests) ===============
[21:24:48] [PASSED] drm_test_drm_bridge_alloc_basic
[21:24:48] [PASSED] drm_test_drm_bridge_alloc_get_put
[21:24:48] ================ [PASSED] drm_bridge_alloc =================
[21:24:48] ============= drm_cmdline_parser (40 subtests) =============
[21:24:48] [PASSED] drm_test_cmdline_force_d_only
[21:24:48] [PASSED] drm_test_cmdline_force_D_only_dvi
[21:24:48] [PASSED] drm_test_cmdline_force_D_only_hdmi
[21:24:48] [PASSED] drm_test_cmdline_force_D_only_not_digital
[21:24:48] [PASSED] drm_test_cmdline_force_e_only
[21:24:48] [PASSED] drm_test_cmdline_res
[21:24:48] [PASSED] drm_test_cmdline_res_vesa
[21:24:48] [PASSED] drm_test_cmdline_res_vesa_rblank
[21:24:48] [PASSED] drm_test_cmdline_res_rblank
[21:24:48] [PASSED] drm_test_cmdline_res_bpp
[21:24:48] [PASSED] drm_test_cmdline_res_refresh
[21:24:48] [PASSED] drm_test_cmdline_res_bpp_refresh
[21:24:48] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[21:24:48] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[21:24:48] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[21:24:48] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[21:24:48] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[21:24:48] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[21:24:48] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[21:24:48] [PASSED] drm_test_cmdline_res_margins_force_on
[21:24:48] [PASSED] drm_test_cmdline_res_vesa_margins
[21:24:48] [PASSED] drm_test_cmdline_name
[21:24:48] [PASSED] drm_test_cmdline_name_bpp
[21:24:48] [PASSED] drm_test_cmdline_name_option
[21:24:48] [PASSED] drm_test_cmdline_name_bpp_option
[21:24:48] [PASSED] drm_test_cmdline_rotate_0
[21:24:48] [PASSED] drm_test_cmdline_rotate_90
[21:24:48] [PASSED] drm_test_cmdline_rotate_180
[21:24:48] [PASSED] drm_test_cmdline_rotate_270
[21:24:48] [PASSED] drm_test_cmdline_hmirror
[21:24:48] [PASSED] drm_test_cmdline_vmirror
[21:24:48] [PASSED] drm_test_cmdline_margin_options
[21:24:48] [PASSED] drm_test_cmdline_multiple_options
[21:24:48] [PASSED] drm_test_cmdline_bpp_extra_and_option
[21:24:48] [PASSED] drm_test_cmdline_extra_and_option
[21:24:48] [PASSED] drm_test_cmdline_freestanding_options
[21:24:48] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[21:24:48] [PASSED] drm_test_cmdline_panel_orientation
[21:24:48] ================ drm_test_cmdline_invalid  =================
[21:24:48] [PASSED] margin_only
[21:24:48] [PASSED] interlace_only
[21:24:48] [PASSED] res_missing_x
[21:24:48] [PASSED] res_missing_y
[21:24:48] [PASSED] res_bad_y
[21:24:48] [PASSED] res_missing_y_bpp
[21:24:48] [PASSED] res_bad_bpp
[21:24:48] [PASSED] res_bad_refresh
[21:24:48] [PASSED] res_bpp_refresh_force_on_off
[21:24:48] [PASSED] res_invalid_mode
[21:24:48] [PASSED] res_bpp_wrong_place_mode
[21:24:48] [PASSED] name_bpp_refresh
[21:24:48] [PASSED] name_refresh
[21:24:48] [PASSED] name_refresh_wrong_mode
[21:24:48] [PASSED] name_refresh_invalid_mode
[21:24:48] [PASSED] rotate_multiple
[21:24:48] [PASSED] rotate_invalid_val
[21:24:48] [PASSED] rotate_truncated
[21:24:48] [PASSED] invalid_option
[21:24:48] [PASSED] invalid_tv_option
[21:24:48] [PASSED] truncated_tv_option
[21:24:48] ============ [PASSED] drm_test_cmdline_invalid =============
[21:24:48] =============== drm_test_cmdline_tv_options  ===============
[21:24:48] [PASSED] NTSC
[21:24:48] [PASSED] NTSC_443
[21:24:48] [PASSED] NTSC_J
[21:24:48] [PASSED] PAL
[21:24:48] [PASSED] PAL_M
[21:24:48] [PASSED] PAL_N
[21:24:48] [PASSED] SECAM
[21:24:48] [PASSED] MONO_525
[21:24:48] [PASSED] MONO_625
[21:24:48] =========== [PASSED] drm_test_cmdline_tv_options ===========
[21:24:48] =============== [PASSED] drm_cmdline_parser ================
[21:24:48] ========== drmm_connector_hdmi_init (20 subtests) ==========
[21:24:48] [PASSED] drm_test_connector_hdmi_init_valid
[21:24:48] [PASSED] drm_test_connector_hdmi_init_bpc_8
[21:24:48] [PASSED] drm_test_connector_hdmi_init_bpc_10
[21:24:48] [PASSED] drm_test_connector_hdmi_init_bpc_12
[21:24:48] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[21:24:48] [PASSED] drm_test_connector_hdmi_init_bpc_null
[21:24:48] [PASSED] drm_test_connector_hdmi_init_formats_empty
[21:24:48] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[21:24:48] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[21:24:48] [PASSED] supported_formats=0x9 yuv420_allowed=1
[21:24:48] [PASSED] supported_formats=0x9 yuv420_allowed=0
[21:24:48] [PASSED] supported_formats=0x5 yuv420_allowed=1
[21:24:48] [PASSED] supported_formats=0x5 yuv420_allowed=0
[21:24:48] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[21:24:48] [PASSED] drm_test_connector_hdmi_init_null_ddc
[21:24:48] [PASSED] drm_test_connector_hdmi_init_null_product
[21:24:48] [PASSED] drm_test_connector_hdmi_init_null_vendor
[21:24:48] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[21:24:48] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[21:24:48] [PASSED] drm_test_connector_hdmi_init_product_valid
[21:24:48] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[21:24:48] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[21:24:48] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[21:24:48] ========= drm_test_connector_hdmi_init_type_valid  =========
[21:24:48] [PASSED] HDMI-A
[21:24:48] [PASSED] HDMI-B
[21:24:48] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[21:24:48] ======== drm_test_connector_hdmi_init_type_invalid  ========
[21:24:48] [PASSED] Unknown
[21:24:48] [PASSED] VGA
[21:24:48] [PASSED] DVI-I
[21:24:48] [PASSED] DVI-D
[21:24:48] [PASSED] DVI-A
[21:24:48] [PASSED] Composite
[21:24:48] [PASSED] SVIDEO
[21:24:48] [PASSED] LVDS
[21:24:48] [PASSED] Component
[21:24:48] [PASSED] DIN
[21:24:48] [PASSED] DP
[21:24:48] [PASSED] TV
[21:24:48] [PASSED] eDP
[21:24:48] [PASSED] Virtual
[21:24:48] [PASSED] DSI
[21:24:48] [PASSED] DPI
[21:24:48] [PASSED] Writeback
[21:24:48] [PASSED] SPI
[21:24:48] [PASSED] USB
[21:24:48] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[21:24:48] ============ [PASSED] drmm_connector_hdmi_init =============
[21:24:48] ============= drmm_connector_init (3 subtests) =============
[21:24:48] [PASSED] drm_test_drmm_connector_init
[21:24:48] [PASSED] drm_test_drmm_connector_init_null_ddc
[21:24:48] ========= drm_test_drmm_connector_init_type_valid  =========
[21:24:48] [PASSED] Unknown
[21:24:48] [PASSED] VGA
[21:24:48] [PASSED] DVI-I
[21:24:48] [PASSED] DVI-D
[21:24:48] [PASSED] DVI-A
[21:24:48] [PASSED] Composite
[21:24:48] [PASSED] SVIDEO
[21:24:48] [PASSED] LVDS
[21:24:48] [PASSED] Component
[21:24:48] [PASSED] DIN
[21:24:48] [PASSED] DP
[21:24:48] [PASSED] HDMI-A
[21:24:48] [PASSED] HDMI-B
[21:24:48] [PASSED] TV
[21:24:48] [PASSED] eDP
[21:24:48] [PASSED] Virtual
[21:24:48] [PASSED] DSI
[21:24:48] [PASSED] DPI
[21:24:48] [PASSED] Writeback
[21:24:48] [PASSED] SPI
[21:24:48] [PASSED] USB
[21:24:48] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[21:24:48] =============== [PASSED] drmm_connector_init ===============
[21:24:48] ========= drm_connector_dynamic_init (6 subtests) ==========
[21:24:48] [PASSED] drm_test_drm_connector_dynamic_init
[21:24:48] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[21:24:48] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[21:24:48] [PASSED] drm_test_drm_connector_dynamic_init_properties
[21:24:48] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[21:24:48] [PASSED] Unknown
[21:24:48] [PASSED] VGA
[21:24:48] [PASSED] DVI-I
[21:24:48] [PASSED] DVI-D
[21:24:48] [PASSED] DVI-A
[21:24:48] [PASSED] Composite
[21:24:48] [PASSED] SVIDEO
[21:24:48] [PASSED] LVDS
[21:24:48] [PASSED] Component
[21:24:48] [PASSED] DIN
[21:24:48] [PASSED] DP
[21:24:48] [PASSED] HDMI-A
[21:24:48] [PASSED] HDMI-B
[21:24:48] [PASSED] TV
[21:24:48] [PASSED] eDP
[21:24:48] [PASSED] Virtual
[21:24:48] [PASSED] DSI
[21:24:48] [PASSED] DPI
[21:24:48] [PASSED] Writeback
[21:24:48] [PASSED] SPI
[21:24:48] [PASSED] USB
[21:24:48] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[21:24:48] ======== drm_test_drm_connector_dynamic_init_name  =========
[21:24:48] [PASSED] Unknown
[21:24:48] [PASSED] VGA
[21:24:48] [PASSED] DVI-I
[21:24:48] [PASSED] DVI-D
[21:24:48] [PASSED] DVI-A
[21:24:48] [PASSED] Composite
[21:24:48] [PASSED] SVIDEO
[21:24:48] [PASSED] LVDS
[21:24:48] [PASSED] Component
[21:24:48] [PASSED] DIN
[21:24:48] [PASSED] DP
[21:24:48] [PASSED] HDMI-A
[21:24:48] [PASSED] HDMI-B
[21:24:48] [PASSED] TV
[21:24:48] [PASSED] eDP
[21:24:48] [PASSED] Virtual
[21:24:48] [PASSED] DSI
[21:24:48] [PASSED] DPI
[21:24:48] [PASSED] Writeback
[21:24:48] [PASSED] SPI
[21:24:48] [PASSED] USB
[21:24:48] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[21:24:48] =========== [PASSED] drm_connector_dynamic_init ============
[21:24:48] ==== drm_connector_dynamic_register_early (4 subtests) =====
[21:24:48] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[21:24:48] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[21:24:48] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[21:24:48] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[21:24:48] ====== [PASSED] drm_connector_dynamic_register_early =======
[21:24:48] ======= drm_connector_dynamic_register (7 subtests) ========
[21:24:48] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[21:24:48] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[21:24:48] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[21:24:48] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[21:24:48] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[21:24:48] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[21:24:48] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[21:24:48] ========= [PASSED] drm_connector_dynamic_register ==========
[21:24:48] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[21:24:48] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[21:24:48] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[21:24:48] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[21:24:48] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[21:24:48] ========== drm_test_get_tv_mode_from_name_valid  ===========
[21:24:48] [PASSED] NTSC
[21:24:48] [PASSED] NTSC-443
[21:24:48] [PASSED] NTSC-J
[21:24:48] [PASSED] PAL
[21:24:48] [PASSED] PAL-M
[21:24:48] [PASSED] PAL-N
[21:24:48] [PASSED] SECAM
[21:24:48] [PASSED] Mono
[21:24:48] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[21:24:48] [PASSED] drm_test_get_tv_mode_from_name_truncated
[21:24:48] ============ [PASSED] drm_get_tv_mode_from_name ============
[21:24:48] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[21:24:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[21:24:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[21:24:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[21:24:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[21:24:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[21:24:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[21:24:48] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[21:24:48] [PASSED] VIC 96
[21:24:48] [PASSED] VIC 97
[21:24:48] [PASSED] VIC 101
[21:24:48] [PASSED] VIC 102
[21:24:48] [PASSED] VIC 106
[21:24:48] [PASSED] VIC 107
[21:24:48] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[21:24:48] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[21:24:48] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[21:24:48] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[21:24:48] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[21:24:48] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[21:24:48] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[21:24:48] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[21:24:48] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[21:24:48] [PASSED] Automatic
[21:24:48] [PASSED] Full
[21:24:48] [PASSED] Limited 16:235
[21:24:48] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[21:24:48] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[21:24:48] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[21:24:48] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[21:24:48] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[21:24:48] [PASSED] RGB
[21:24:48] [PASSED] YUV 4:2:0
[21:24:48] [PASSED] YUV 4:2:2
[21:24:48] [PASSED] YUV 4:4:4
[21:24:48] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[21:24:48] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[21:24:48] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[21:24:48] ============= drm_damage_helper (21 subtests) ==============
[21:24:48] [PASSED] drm_test_damage_iter_no_damage
[21:24:48] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[21:24:48] [PASSED] drm_test_damage_iter_no_damage_src_moved
[21:24:48] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[21:24:48] [PASSED] drm_test_damage_iter_no_damage_not_visible
[21:24:48] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[21:24:48] [PASSED] drm_test_damage_iter_no_damage_no_fb
[21:24:48] [PASSED] drm_test_damage_iter_simple_damage
[21:24:48] [PASSED] drm_test_damage_iter_single_damage
[21:24:48] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[21:24:48] [PASSED] drm_test_damage_iter_single_damage_outside_src
[21:24:48] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[21:24:48] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[21:24:48] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[21:24:48] [PASSED] drm_test_damage_iter_single_damage_src_moved
[21:24:48] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[21:24:48] [PASSED] drm_test_damage_iter_damage
[21:24:48] [PASSED] drm_test_damage_iter_damage_one_intersect
[21:24:48] [PASSED] drm_test_damage_iter_damage_one_outside
[21:24:48] [PASSED] drm_test_damage_iter_damage_src_moved
[21:24:48] [PASSED] drm_test_damage_iter_damage_not_visible
[21:24:48] ================ [PASSED] drm_damage_helper ================
[21:24:48] ============== drm_dp_mst_helper (3 subtests) ==============
[21:24:48] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[21:24:48] [PASSED] Clock 154000 BPP 30 DSC disabled
[21:24:48] [PASSED] Clock 234000 BPP 30 DSC disabled
[21:24:48] [PASSED] Clock 297000 BPP 24 DSC disabled
[21:24:48] [PASSED] Clock 332880 BPP 24 DSC enabled
[21:24:48] [PASSED] Clock 324540 BPP 24 DSC enabled
[21:24:48] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[21:24:48] ============== drm_test_dp_mst_calc_pbn_div  ===============
[21:24:48] [PASSED] Link rate 2000000 lane count 4
[21:24:48] [PASSED] Link rate 2000000 lane count 2
[21:24:48] [PASSED] Link rate 2000000 lane count 1
[21:24:48] [PASSED] Link rate 1350000 lane count 4
[21:24:48] [PASSED] Link rate 1350000 lane count 2
[21:24:48] [PASSED] Link rate 1350000 lane count 1
[21:24:48] [PASSED] Link rate 1000000 lane count 4
[21:24:48] [PASSED] Link rate 1000000 lane count 2
[21:24:48] [PASSED] Link rate 1000000 lane count 1
[21:24:48] [PASSED] Link rate 810000 lane count 4
[21:24:48] [PASSED] Link rate 810000 lane count 2
[21:24:48] [PASSED] Link rate 810000 lane count 1
[21:24:48] [PASSED] Link rate 540000 lane count 4
[21:24:48] [PASSED] Link rate 540000 lane count 2
[21:24:48] [PASSED] Link rate 540000 lane count 1
[21:24:48] [PASSED] Link rate 270000 lane count 4
[21:24:48] [PASSED] Link rate 270000 lane count 2
[21:24:48] [PASSED] Link rate 270000 lane count 1
[21:24:48] [PASSED] Link rate 162000 lane count 4
[21:24:48] [PASSED] Link rate 162000 lane count 2
[21:24:48] [PASSED] Link rate 162000 lane count 1
[21:24:48] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[21:24:48] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[21:24:48] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[21:24:48] [PASSED] DP_POWER_UP_PHY with port number
[21:24:48] [PASSED] DP_POWER_DOWN_PHY with port number
[21:24:48] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[21:24:48] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[21:24:48] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[21:24:48] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[21:24:48] [PASSED] DP_QUERY_PAYLOAD with port number
[21:24:48] [PASSED] DP_QUERY_PAYLOAD with VCPI
[21:24:48] [PASSED] DP_REMOTE_DPCD_READ with port number
[21:24:48] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[21:24:48] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[21:24:48] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[21:24:48] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[21:24:48] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[21:24:48] [PASSED] DP_REMOTE_I2C_READ with port number
[21:24:48] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[21:24:48] [PASSED] DP_REMOTE_I2C_READ with transactions array
[21:24:48] [PASSED] DP_REMOTE_I2C_WRITE with port number
[21:24:48] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[21:24:48] [PASSED] DP_REMOTE_I2C_WRITE with data array
[21:24:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[21:24:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[21:24:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[21:24:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[21:24:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[21:24:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[21:24:48] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[21:24:48] ================ [PASSED] drm_dp_mst_helper ================
[21:24:48] ================== drm_exec (7 subtests) ===================
[21:24:48] [PASSED] sanitycheck
[21:24:48] [PASSED] test_lock
[21:24:48] [PASSED] test_lock_unlock
[21:24:48] [PASSED] test_duplicates
[21:24:48] [PASSED] test_prepare
[21:24:48] [PASSED] test_prepare_array
[21:24:48] [PASSED] test_multiple_loops
[21:24:48] ==================== [PASSED] drm_exec =====================
[21:24:48] =========== drm_format_helper_test (17 subtests) ===========
[21:24:48] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[21:24:48] [PASSED] single_pixel_source_buffer
[21:24:48] [PASSED] single_pixel_clip_rectangle
[21:24:48] [PASSED] well_known_colors
[21:24:48] [PASSED] destination_pitch
[21:24:48] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[21:24:48] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[21:24:48] [PASSED] single_pixel_source_buffer
[21:24:48] [PASSED] single_pixel_clip_rectangle
[21:24:48] [PASSED] well_known_colors
[21:24:48] [PASSED] destination_pitch
[21:24:48] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[21:24:48] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[21:24:48] [PASSED] single_pixel_source_buffer
[21:24:48] [PASSED] single_pixel_clip_rectangle
[21:24:48] [PASSED] well_known_colors
[21:24:48] [PASSED] destination_pitch
[21:24:48] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[21:24:48] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[21:24:48] [PASSED] single_pixel_source_buffer
[21:24:48] [PASSED] single_pixel_clip_rectangle
[21:24:48] [PASSED] well_known_colors
[21:24:48] [PASSED] destination_pitch
[21:24:48] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[21:24:48] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[21:24:48] [PASSED] single_pixel_source_buffer
[21:24:48] [PASSED] single_pixel_clip_rectangle
[21:24:48] [PASSED] well_known_colors
[21:24:48] [PASSED] destination_pitch
[21:24:48] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[21:24:48] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[21:24:48] [PASSED] single_pixel_source_buffer
[21:24:48] [PASSED] single_pixel_clip_rectangle
[21:24:48] [PASSED] well_known_colors
[21:24:48] [PASSED] destination_pitch
[21:24:48] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[21:24:48] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[21:24:48] [PASSED] single_pixel_source_buffer
[21:24:48] [PASSED] single_pixel_clip_rectangle
[21:24:48] [PASSED] well_known_colors
[21:24:48] [PASSED] destination_pitch
[21:24:48] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[21:24:48] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[21:24:48] [PASSED] single_pixel_source_buffer
[21:24:48] [PASSED] single_pixel_clip_rectangle
[21:24:48] [PASSED] well_known_colors
[21:24:48] [PASSED] destination_pitch
[21:24:48] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[21:24:48] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[21:24:48] [PASSED] single_pixel_source_buffer
[21:24:48] [PASSED] single_pixel_clip_rectangle
[21:24:48] [PASSED] well_known_colors
[21:24:48] [PASSED] destination_pitch
[21:24:48] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[21:24:48] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[21:24:48] [PASSED] single_pixel_source_buffer
[21:24:48] [PASSED] single_pixel_clip_rectangle
[21:24:48] [PASSED] well_known_colors
[21:24:48] [PASSED] destination_pitch
[21:24:48] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[21:24:48] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[21:24:48] [PASSED] single_pixel_source_buffer
[21:24:48] [PASSED] single_pixel_clip_rectangle
[21:24:48] [PASSED] well_known_colors
[21:24:48] [PASSED] destination_pitch
[21:24:48] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[21:24:48] ============== drm_test_fb_xrgb8888_to_mono  ===============
[21:24:48] [PASSED] single_pixel_source_buffer
[21:24:48] [PASSED] single_pixel_clip_rectangle
[21:24:48] [PASSED] well_known_colors
[21:24:48] [PASSED] destination_pitch
[21:24:48] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[21:24:48] ==================== drm_test_fb_swab  =====================
[21:24:48] [PASSED] single_pixel_source_buffer
[21:24:48] [PASSED] single_pixel_clip_rectangle
[21:24:48] [PASSED] well_known_colors
[21:24:48] [PASSED] destination_pitch
[21:24:48] ================ [PASSED] drm_test_fb_swab =================
[21:24:48] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[21:24:48] [PASSED] single_pixel_source_buffer
[21:24:48] [PASSED] single_pixel_clip_rectangle
[21:24:48] [PASSED] well_known_colors
[21:24:48] [PASSED] destination_pitch
[21:24:48] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[21:24:48] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[21:24:48] [PASSED] single_pixel_source_buffer
[21:24:48] [PASSED] single_pixel_clip_rectangle
[21:24:48] [PASSED] well_known_colors
[21:24:48] [PASSED] destination_pitch
[21:24:48] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[21:24:48] ================= drm_test_fb_clip_offset  =================
[21:24:48] [PASSED] pass through
[21:24:48] [PASSED] horizontal offset
[21:24:48] [PASSED] vertical offset
[21:24:48] [PASSED] horizontal and vertical offset
[21:24:48] [PASSED] horizontal offset (custom pitch)
[21:24:48] [PASSED] vertical offset (custom pitch)
[21:24:48] [PASSED] horizontal and vertical offset (custom pitch)
[21:24:48] ============= [PASSED] drm_test_fb_clip_offset =============
[21:24:48] =================== drm_test_fb_memcpy  ====================
[21:24:48] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[21:24:48] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[21:24:48] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[21:24:48] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[21:24:48] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[21:24:48] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[21:24:48] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[21:24:48] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[21:24:48] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[21:24:48] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[21:24:48] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[21:24:48] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[21:24:48] =============== [PASSED] drm_test_fb_memcpy ================
[21:24:48] ============= [PASSED] drm_format_helper_test ==============
[21:24:48] ================= drm_format (18 subtests) =================
[21:24:48] [PASSED] drm_test_format_block_width_invalid
[21:24:48] [PASSED] drm_test_format_block_width_one_plane
[21:24:48] [PASSED] drm_test_format_block_width_two_plane
[21:24:48] [PASSED] drm_test_format_block_width_three_plane
[21:24:48] [PASSED] drm_test_format_block_width_tiled
[21:24:48] [PASSED] drm_test_format_block_height_invalid
[21:24:48] [PASSED] drm_test_format_block_height_one_plane
[21:24:48] [PASSED] drm_test_format_block_height_two_plane
[21:24:48] [PASSED] drm_test_format_block_height_three_plane
[21:24:48] [PASSED] drm_test_format_block_height_tiled
[21:24:48] [PASSED] drm_test_format_min_pitch_invalid
[21:24:48] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[21:24:48] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[21:24:48] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[21:24:48] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[21:24:48] [PASSED] drm_test_format_min_pitch_two_plane
[21:24:48] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[21:24:48] [PASSED] drm_test_format_min_pitch_tiled
[21:24:48] =================== [PASSED] drm_format ====================
[21:24:48] ============== drm_framebuffer (10 subtests) ===============
[21:24:48] ========== drm_test_framebuffer_check_src_coords  ==========
[21:24:48] [PASSED] Success: source fits into fb
[21:24:48] [PASSED] Fail: overflowing fb with x-axis coordinate
[21:24:48] [PASSED] Fail: overflowing fb with y-axis coordinate
[21:24:48] [PASSED] Fail: overflowing fb with source width
[21:24:48] [PASSED] Fail: overflowing fb with source height
[21:24:48] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[21:24:48] [PASSED] drm_test_framebuffer_cleanup
[21:24:48] =============== drm_test_framebuffer_create  ===============
[21:24:48] [PASSED] ABGR8888 normal sizes
[21:24:48] [PASSED] ABGR8888 max sizes
[21:24:48] [PASSED] ABGR8888 pitch greater than min required
[21:24:48] [PASSED] ABGR8888 pitch less than min required
[21:24:48] [PASSED] ABGR8888 Invalid width
[21:24:48] [PASSED] ABGR8888 Invalid buffer handle
[21:24:48] [PASSED] No pixel format
[21:24:48] [PASSED] ABGR8888 Width 0
[21:24:48] [PASSED] ABGR8888 Height 0
[21:24:48] [PASSED] ABGR8888 Out of bound height * pitch combination
[21:24:48] [PASSED] ABGR8888 Large buffer offset
[21:24:48] [PASSED] ABGR8888 Buffer offset for inexistent plane
[21:24:48] [PASSED] ABGR8888 Invalid flag
[21:24:48] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[21:24:48] [PASSED] ABGR8888 Valid buffer modifier
[21:24:48] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[21:24:48] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[21:24:48] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[21:24:48] [PASSED] NV12 Normal sizes
[21:24:48] [PASSED] NV12 Max sizes
[21:24:48] [PASSED] NV12 Invalid pitch
[21:24:48] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[21:24:48] [PASSED] NV12 different  modifier per-plane
[21:24:48] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[21:24:48] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[21:24:48] [PASSED] NV12 Modifier for inexistent plane
[21:24:48] [PASSED] NV12 Handle for inexistent plane
[21:24:48] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[21:24:48] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[21:24:48] [PASSED] YVU420 Normal sizes
[21:24:48] [PASSED] YVU420 Max sizes
[21:24:48] [PASSED] YVU420 Invalid pitch
[21:24:48] [PASSED] YVU420 Different pitches
[21:24:48] [PASSED] YVU420 Different buffer offsets/pitches
[21:24:48] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[21:24:48] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[21:24:48] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[21:24:48] [PASSED] YVU420 Valid modifier
[21:24:48] [PASSED] YVU420 Different modifiers per plane
[21:24:48] [PASSED] YVU420 Modifier for inexistent plane
[21:24:48] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[21:24:48] [PASSED] X0L2 Normal sizes
[21:24:48] [PASSED] X0L2 Max sizes
[21:24:48] [PASSED] X0L2 Invalid pitch
[21:24:48] [PASSED] X0L2 Pitch greater than minimum required
[21:24:48] [PASSED] X0L2 Handle for inexistent plane
[21:24:48] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[21:24:48] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[21:24:48] [PASSED] X0L2 Valid modifier
[21:24:48] [PASSED] X0L2 Modifier for inexistent plane
[21:24:48] =========== [PASSED] drm_test_framebuffer_create ===========
[21:24:48] [PASSED] drm_test_framebuffer_free
[21:24:48] [PASSED] drm_test_framebuffer_init
[21:24:48] [PASSED] drm_test_framebuffer_init_bad_format
[21:24:48] [PASSED] drm_test_framebuffer_init_dev_mismatch
[21:24:48] [PASSED] drm_test_framebuffer_lookup
[21:24:48] [PASSED] drm_test_framebuffer_lookup_inexistent
[21:24:48] [PASSED] drm_test_framebuffer_modifiers_not_supported
[21:24:48] ================= [PASSED] drm_framebuffer =================
[21:24:48] ================ drm_gem_shmem (8 subtests) ================
[21:24:48] [PASSED] drm_gem_shmem_test_obj_create
[21:24:48] [PASSED] drm_gem_shmem_test_obj_create_private
[21:24:48] [PASSED] drm_gem_shmem_test_pin_pages
[21:24:48] [PASSED] drm_gem_shmem_test_vmap
[21:24:48] [PASSED] drm_gem_shmem_test_get_sg_table
[21:24:48] [PASSED] drm_gem_shmem_test_get_pages_sgt
[21:24:48] [PASSED] drm_gem_shmem_test_madvise
[21:24:48] [PASSED] drm_gem_shmem_test_purge
[21:24:48] ================== [PASSED] drm_gem_shmem ==================
[21:24:48] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[21:24:48] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[21:24:48] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[21:24:48] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[21:24:48] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[21:24:48] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[21:24:48] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[21:24:48] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[21:24:48] [PASSED] Automatic
[21:24:48] [PASSED] Full
[21:24:48] [PASSED] Limited 16:235
[21:24:48] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[21:24:48] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[21:24:48] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[21:24:48] [PASSED] drm_test_check_disable_connector
[21:24:48] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[21:24:48] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[21:24:48] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[21:24:48] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[21:24:48] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[21:24:48] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[21:24:48] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[21:24:48] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[21:24:48] [PASSED] drm_test_check_output_bpc_dvi
[21:24:48] [PASSED] drm_test_check_output_bpc_format_vic_1
[21:24:48] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[21:24:48] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[21:24:48] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[21:24:48] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[21:24:48] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[21:24:48] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[21:24:48] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[21:24:48] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[21:24:48] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[21:24:48] [PASSED] drm_test_check_broadcast_rgb_value
[21:24:48] [PASSED] drm_test_check_bpc_8_value
[21:24:48] [PASSED] drm_test_check_bpc_10_value
[21:24:48] [PASSED] drm_test_check_bpc_12_value
[21:24:48] [PASSED] drm_test_check_format_value
[21:24:48] [PASSED] drm_test_check_tmds_char_value
[21:24:48] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[21:24:48] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[21:24:48] [PASSED] drm_test_check_mode_valid
[21:24:48] [PASSED] drm_test_check_mode_valid_reject
[21:24:48] [PASSED] drm_test_check_mode_valid_reject_rate
[21:24:48] [PASSED] drm_test_check_mode_valid_reject_max_clock
[21:24:48] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[21:24:48] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[21:24:48] [PASSED] drm_test_check_infoframes
[21:24:48] [PASSED] drm_test_check_reject_avi_infoframe
[21:24:48] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[21:24:48] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[21:24:48] [PASSED] drm_test_check_reject_audio_infoframe
[21:24:48] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[21:24:48] ================= drm_managed (2 subtests) =================
[21:24:48] [PASSED] drm_test_managed_release_action
[21:24:48] [PASSED] drm_test_managed_run_action
[21:24:48] =================== [PASSED] drm_managed ===================
[21:24:48] =================== drm_mm (6 subtests) ====================
[21:24:48] [PASSED] drm_test_mm_init
[21:24:48] [PASSED] drm_test_mm_debug
[21:24:48] [PASSED] drm_test_mm_align32
[21:24:48] [PASSED] drm_test_mm_align64
[21:24:48] [PASSED] drm_test_mm_lowest
[21:24:48] [PASSED] drm_test_mm_highest
[21:24:48] ===================== [PASSED] drm_mm ======================
[21:24:48] ============= drm_modes_analog_tv (5 subtests) =============
[21:24:48] [PASSED] drm_test_modes_analog_tv_mono_576i
[21:24:48] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[21:24:48] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[21:24:48] [PASSED] drm_test_modes_analog_tv_pal_576i
[21:24:48] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[21:24:48] =============== [PASSED] drm_modes_analog_tv ===============
[21:24:48] ============== drm_plane_helper (2 subtests) ===============
[21:24:48] =============== drm_test_check_plane_state  ================
[21:24:48] [PASSED] clipping_simple
[21:24:48] [PASSED] clipping_rotate_reflect
[21:24:48] [PASSED] positioning_simple
[21:24:48] [PASSED] upscaling
[21:24:48] [PASSED] downscaling
[21:24:48] [PASSED] rounding1
[21:24:48] [PASSED] rounding2
[21:24:48] [PASSED] rounding3
[21:24:48] [PASSED] rounding4
[21:24:48] =========== [PASSED] drm_test_check_plane_state ============
[21:24:48] =========== drm_test_check_invalid_plane_state  ============
[21:24:48] [PASSED] positioning_invalid
[21:24:48] [PASSED] upscaling_invalid
[21:24:48] [PASSED] downscaling_invalid
[21:24:48] ======= [PASSED] drm_test_check_invalid_plane_state ========
[21:24:48] ================ [PASSED] drm_plane_helper =================
[21:24:48] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[21:24:48] ====== drm_test_connector_helper_tv_get_modes_check  =======
[21:24:48] [PASSED] None
[21:24:48] [PASSED] PAL
[21:24:48] [PASSED] NTSC
[21:24:48] [PASSED] Both, NTSC Default
[21:24:48] [PASSED] Both, PAL Default
[21:24:48] [PASSED] Both, NTSC Default, with PAL on command-line
[21:24:48] [PASSED] Both, PAL Default, with NTSC on command-line
[21:24:48] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[21:24:48] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[21:24:48] ================== drm_rect (9 subtests) ===================
[21:24:48] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[21:24:48] [PASSED] drm_test_rect_clip_scaled_not_clipped
[21:24:48] [PASSED] drm_test_rect_clip_scaled_clipped
[21:24:48] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[21:24:48] ================= drm_test_rect_intersect  =================
[21:24:48] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[21:24:48] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[21:24:48] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[21:24:48] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[21:24:48] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[21:24:48] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[21:24:48] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[21:24:48] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[21:24:48] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[21:24:48] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[21:24:48] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[21:24:48] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[21:24:48] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[21:24:48] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[21:24:48] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[21:24:48] ============= [PASSED] drm_test_rect_intersect =============
[21:24:48] ================ drm_test_rect_calc_hscale  ================
[21:24:48] [PASSED] normal use
[21:24:48] [PASSED] out of max range
[21:24:48] [PASSED] out of min range
[21:24:48] [PASSED] zero dst
[21:24:48] [PASSED] negative src
[21:24:48] [PASSED] negative dst
[21:24:48] ============ [PASSED] drm_test_rect_calc_hscale ============
[21:24:48] ================ drm_test_rect_calc_vscale  ================
[21:24:48] [PASSED] normal use
[21:24:48] [PASSED] out of max range
[21:24:48] [PASSED] out of min range
[21:24:48] [PASSED] zero dst
[21:24:48] [PASSED] negative src
[21:24:48] [PASSED] negative dst
[21:24:48] ============ [PASSED] drm_test_rect_calc_vscale ============
[21:24:48] ================== drm_test_rect_rotate  ===================
[21:24:48] [PASSED] reflect-x
[21:24:48] [PASSED] reflect-y
[21:24:48] [PASSED] rotate-0
[21:24:48] [PASSED] rotate-90
[21:24:48] [PASSED] rotate-180
[21:24:48] [PASSED] rotate-270
[21:24:48] ============== [PASSED] drm_test_rect_rotate ===============
[21:24:48] ================ drm_test_rect_rotate_inv  =================
[21:24:48] [PASSED] reflect-x
[21:24:48] [PASSED] reflect-y
[21:24:48] [PASSED] rotate-0
[21:24:48] [PASSED] rotate-90
[21:24:48] [PASSED] rotate-180
[21:24:48] [PASSED] rotate-270
[21:24:48] ============ [PASSED] drm_test_rect_rotate_inv =============
[21:24:48] ==================== [PASSED] drm_rect =====================
[21:24:48] ============ drm_sysfb_modeset_test (1 subtest) ============
[21:24:48] ============ drm_test_sysfb_build_fourcc_list  =============
[21:24:48] [PASSED] no native formats
[21:24:48] [PASSED] XRGB8888 as native format
[21:24:48] [PASSED] remove duplicates
[21:24:48] [PASSED] convert alpha formats
[21:24:48] [PASSED] random formats
[21:24:48] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[21:24:48] ============= [PASSED] drm_sysfb_modeset_test ==============
[21:24:48] ================== drm_fixp (2 subtests) ===================
[21:24:48] [PASSED] drm_test_int2fixp
[21:24:48] [PASSED] drm_test_sm2fixp
[21:24:48] ==================== [PASSED] drm_fixp =====================
[21:24:48] ============================================================
[21:24:48] Testing complete. Ran 621 tests: passed: 621
[21:24:48] Elapsed time: 26.208s total, 1.764s configuring, 24.264s building, 0.179s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[21:24:48] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:24:50] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:25:00] Starting KUnit Kernel (1/1)...
[21:25:00] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:25:00] ================= ttm_device (5 subtests) ==================
[21:25:00] [PASSED] ttm_device_init_basic
[21:25:00] [PASSED] ttm_device_init_multiple
[21:25:00] [PASSED] ttm_device_fini_basic
[21:25:00] [PASSED] ttm_device_init_no_vma_man
[21:25:00] ================== ttm_device_init_pools  ==================
[21:25:00] [PASSED] No DMA allocations, no DMA32 required
[21:25:00] [PASSED] DMA allocations, DMA32 required
[21:25:00] [PASSED] No DMA allocations, DMA32 required
[21:25:00] [PASSED] DMA allocations, no DMA32 required
[21:25:00] ============== [PASSED] ttm_device_init_pools ==============
[21:25:00] =================== [PASSED] ttm_device ====================
[21:25:00] ================== ttm_pool (8 subtests) ===================
[21:25:00] ================== ttm_pool_alloc_basic  ===================
[21:25:00] [PASSED] One page
[21:25:00] [PASSED] More than one page
[21:25:00] [PASSED] Above the allocation limit
[21:25:00] [PASSED] One page, with coherent DMA mappings enabled
[21:25:00] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:25:00] ============== [PASSED] ttm_pool_alloc_basic ===============
[21:25:00] ============== ttm_pool_alloc_basic_dma_addr  ==============
[21:25:00] [PASSED] One page
[21:25:00] [PASSED] More than one page
[21:25:00] [PASSED] Above the allocation limit
[21:25:00] [PASSED] One page, with coherent DMA mappings enabled
[21:25:00] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:25:00] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[21:25:00] [PASSED] ttm_pool_alloc_order_caching_match
[21:25:00] [PASSED] ttm_pool_alloc_caching_mismatch
[21:25:00] [PASSED] ttm_pool_alloc_order_mismatch
[21:25:00] [PASSED] ttm_pool_free_dma_alloc
[21:25:00] [PASSED] ttm_pool_free_no_dma_alloc
[21:25:00] [PASSED] ttm_pool_fini_basic
[21:25:00] ==================== [PASSED] ttm_pool =====================
[21:25:00] ================ ttm_resource (8 subtests) =================
[21:25:00] ================= ttm_resource_init_basic  =================
[21:25:00] [PASSED] Init resource in TTM_PL_SYSTEM
[21:25:00] [PASSED] Init resource in TTM_PL_VRAM
[21:25:00] [PASSED] Init resource in a private placement
[21:25:00] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[21:25:00] ============= [PASSED] ttm_resource_init_basic =============
[21:25:00] [PASSED] ttm_resource_init_pinned
[21:25:00] [PASSED] ttm_resource_fini_basic
[21:25:00] [PASSED] ttm_resource_manager_init_basic
[21:25:00] [PASSED] ttm_resource_manager_usage_basic
[21:25:00] [PASSED] ttm_resource_manager_set_used_basic
[21:25:00] [PASSED] ttm_sys_man_alloc_basic
[21:25:00] [PASSED] ttm_sys_man_free_basic
[21:25:00] ================== [PASSED] ttm_resource ===================
[21:25:00] =================== ttm_tt (15 subtests) ===================
[21:25:00] ==================== ttm_tt_init_basic  ====================
[21:25:00] [PASSED] Page-aligned size
[21:25:00] [PASSED] Extra pages requested
[21:25:00] ================ [PASSED] ttm_tt_init_basic ================
[21:25:00] [PASSED] ttm_tt_init_misaligned
[21:25:00] [PASSED] ttm_tt_fini_basic
[21:25:00] [PASSED] ttm_tt_fini_sg
[21:25:00] [PASSED] ttm_tt_fini_shmem
[21:25:00] [PASSED] ttm_tt_create_basic
[21:25:00] [PASSED] ttm_tt_create_invalid_bo_type
[21:25:00] [PASSED] ttm_tt_create_ttm_exists
[21:25:00] [PASSED] ttm_tt_create_failed
[21:25:00] [PASSED] ttm_tt_destroy_basic
[21:25:00] [PASSED] ttm_tt_populate_null_ttm
[21:25:00] [PASSED] ttm_tt_populate_populated_ttm
[21:25:00] [PASSED] ttm_tt_unpopulate_basic
[21:25:00] [PASSED] ttm_tt_unpopulate_empty_ttm
[21:25:00] [PASSED] ttm_tt_swapin_basic
[21:25:00] ===================== [PASSED] ttm_tt ======================
[21:25:00] =================== ttm_bo (14 subtests) ===================
[21:25:00] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[21:25:00] [PASSED] Cannot be interrupted and sleeps
[21:25:00] [PASSED] Cannot be interrupted, locks straight away
[21:25:00] [PASSED] Can be interrupted, sleeps
[21:25:00] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[21:25:00] [PASSED] ttm_bo_reserve_locked_no_sleep
[21:25:00] [PASSED] ttm_bo_reserve_no_wait_ticket
[21:25:00] [PASSED] ttm_bo_reserve_double_resv
[21:25:00] [PASSED] ttm_bo_reserve_interrupted
[21:25:00] [PASSED] ttm_bo_reserve_deadlock
[21:25:00] [PASSED] ttm_bo_unreserve_basic
[21:25:00] [PASSED] ttm_bo_unreserve_pinned
[21:25:00] [PASSED] ttm_bo_unreserve_bulk
[21:25:00] [PASSED] ttm_bo_fini_basic
[21:25:00] [PASSED] ttm_bo_fini_shared_resv
[21:25:00] [PASSED] ttm_bo_pin_basic
[21:25:00] [PASSED] ttm_bo_pin_unpin_resource
[21:25:00] [PASSED] ttm_bo_multiple_pin_one_unpin
[21:25:00] ===================== [PASSED] ttm_bo ======================
[21:25:00] ============== ttm_bo_validate (22 subtests) ===============
[21:25:00] ============== ttm_bo_init_reserved_sys_man  ===============
[21:25:00] [PASSED] Buffer object for userspace
[21:25:00] [PASSED] Kernel buffer object
[21:25:00] [PASSED] Shared buffer object
[21:25:00] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[21:25:00] ============== ttm_bo_init_reserved_mock_man  ==============
[21:25:00] [PASSED] Buffer object for userspace
[21:25:00] [PASSED] Kernel buffer object
[21:25:00] [PASSED] Shared buffer object
[21:25:00] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[21:25:00] [PASSED] ttm_bo_init_reserved_resv
[21:25:00] ================== ttm_bo_validate_basic  ==================
[21:25:00] [PASSED] Buffer object for userspace
[21:25:00] [PASSED] Kernel buffer object
[21:25:00] [PASSED] Shared buffer object
[21:25:00] ============== [PASSED] ttm_bo_validate_basic ==============
[21:25:00] [PASSED] ttm_bo_validate_invalid_placement
[21:25:00] ============= ttm_bo_validate_same_placement  ==============
[21:25:00] [PASSED] System manager
[21:25:00] [PASSED] VRAM manager
[21:25:00] ========= [PASSED] ttm_bo_validate_same_placement ==========
[21:25:00] [PASSED] ttm_bo_validate_failed_alloc
[21:25:00] [PASSED] ttm_bo_validate_pinned
[21:25:00] [PASSED] ttm_bo_validate_busy_placement
[21:25:00] ================ ttm_bo_validate_multihop  =================
[21:25:00] [PASSED] Buffer object for userspace
[21:25:00] [PASSED] Kernel buffer object
[21:25:00] [PASSED] Shared buffer object
[21:25:00] ============ [PASSED] ttm_bo_validate_multihop =============
[21:25:00] ========== ttm_bo_validate_no_placement_signaled  ==========
[21:25:00] [PASSED] Buffer object in system domain, no page vector
[21:25:00] [PASSED] Buffer object in system domain with an existing page vector
[21:25:00] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[21:25:00] ======== ttm_bo_validate_no_placement_not_signaled  ========
[21:25:00] [PASSED] Buffer object for userspace
[21:25:00] [PASSED] Kernel buffer object
[21:25:00] [PASSED] Shared buffer object
[21:25:00] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[21:25:00] [PASSED] ttm_bo_validate_move_fence_signaled
[21:25:00] ========= ttm_bo_validate_move_fence_not_signaled  =========
[21:25:00] [PASSED] Waits for GPU
[21:25:00] [PASSED] Tries to lock straight away
[21:25:00] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[21:25:00] [PASSED] ttm_bo_validate_swapout
[21:25:00] [PASSED] ttm_bo_validate_happy_evict
[21:25:00] [PASSED] ttm_bo_validate_all_pinned_evict
[21:25:00] [PASSED] ttm_bo_validate_allowed_only_evict
[21:25:00] [PASSED] ttm_bo_validate_deleted_evict
[21:25:00] [PASSED] ttm_bo_validate_busy_domain_evict
[21:25:00] [PASSED] ttm_bo_validate_evict_gutting
[21:25:00] [PASSED] ttm_bo_validate_recrusive_evict
[21:25:00] ================= [PASSED] ttm_bo_validate =================
[21:25:00] ============================================================
[21:25:00] Testing complete. Ran 102 tests: passed: 102
[21:25:00] Elapsed time: 11.557s total, 1.754s configuring, 9.588s building, 0.183s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for CMTG enablement (rev9)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 936 bytes --]

== Series Details ==

Series: CMTG enablement (rev9)
URL   : https://patchwork.freedesktop.org/series/157663/
State : success

== Summary ==

CI Bug Log - changes from xe-5195-5ee88cba0806722ea2c6a969e61a33c061cdc9a4_BAT -> xe-pw-157663v9_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-5195-5ee88cba0806722ea2c6a969e61a33c061cdc9a4 -> xe-pw-157663v9

  IGT_8947: e322bfd77da04314dd310da9a6cf0562b5751f1f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5195-5ee88cba0806722ea2c6a969e61a33c061cdc9a4: 5ee88cba0806722ea2c6a969e61a33c061cdc9a4
  xe-pw-157663v9: 157663v9

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/index.html

[-- Attachment #2: Type: text/html, Size: 1484 bytes --]

✓ Xe.CI.FULL: success for CMTG enablement (rev9)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 14744 bytes --]

== Series Details ==

Series: CMTG enablement (rev9)
URL   : https://patchwork.freedesktop.org/series/157663/
State : success

== Summary ==

CI Bug Log - changes from xe-5195-5ee88cba0806722ea2c6a969e61a33c061cdc9a4_FULL -> xe-pw-157663v9_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-157663v9_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@y-tiled-16bpp-rotate-180:
    - shard-bmg:          NOTRUN -> [SKIP][1] ([Intel XE#1124]) +3 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-3/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html

  * igt@kms_bw@connected-linear-tiling-3-displays-target-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][2] ([Intel XE#7679])
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-3/igt@kms_bw@connected-linear-tiling-3-displays-target-2560x1440p.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs@pipe-b-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#2652]) +8 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-5/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs@pipe-b-dp-2.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#2887]) +4 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-5/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_chamelium_audio@dp-audio-edid:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2252])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-5/igt@kms_chamelium_audio@dp-audio-edid.html

  * igt@kms_chamelium_color@gamma:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#2325] / [Intel XE#7358])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-5/igt@kms_chamelium_color@gamma.html

  * igt@kms_cursor_crc@cursor-sliding-256x85:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2320]) +3 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-3/igt@kms_cursor_crc@cursor-sliding-256x85.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          NOTRUN -> [FAIL][8] ([Intel XE#7571])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#7178] / [Intel XE#7351]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#4141]) +3 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#2311]) +16 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2313]) +20 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-abgr161616f-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#7061])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsrhdr-abgr161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-abgr161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#7061] / [Intel XE#7356])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-abgr161616f-draw-blt.html

  * igt@kms_hdr@static-swap@pipe-a-hdmi-a-3-xrgb2101010:
    - shard-bmg:          [PASS][15] -> [SKIP][16] ([Intel XE#7915]) +1 other test skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5195-5ee88cba0806722ea2c6a969e61a33c061cdc9a4/shard-bmg-6/igt@kms_hdr@static-swap@pipe-a-hdmi-a-3-xrgb2101010.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-3/igt@kms_hdr@static-swap@pipe-a-hdmi-a-3-xrgb2101010.html

  * igt@kms_plane@pixel-format-yf-tiled-modifier-source-clamping:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#7283])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-3/igt@kms_plane@pixel-format-yf-tiled-modifier-source-clamping.html

  * igt@kms_pm_dc@deep-pkgc:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2505] / [Intel XE#7447])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-3/igt@kms_pm_dc@deep-pkgc.html

  * igt@kms_psr2_sf@psr2-cursor-plane-update-sf:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#1489])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-5/igt@kms_psr2_sf@psr2-cursor-plane-update-sf.html

  * igt@kms_psr@fbc-pr-basic:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-3/igt@kms_psr@fbc-pr-basic.html

  * igt@kms_sharpness_filter@invalid-filter-with-scaler:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#6503])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-3/igt@kms_sharpness_filter@invalid-filter-with-scaler.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#1499])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-5/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@xe_eudebug@basic-exec-queues:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#7636]) +5 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-3/igt@xe_eudebug@basic-exec-queues.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2322] / [Intel XE#7372]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-3/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-rebind-imm:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#7136]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-5/igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-rebind-imm.html

  * igt@xe_exec_multi_queue@max-queues-basic:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#6874]) +9 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-3/igt@xe_exec_multi_queue@max-queues-basic.html

  * igt@xe_exec_threads@threads-multi-queue-fd-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#7138]) +1 other test skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-3/igt@xe_exec_threads@threads-multi-queue-fd-userptr-invalidate.html

  * igt@xe_multigpu_svm@mgpu-atomic-op-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#6964])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-3/igt@xe_multigpu_svm@mgpu-atomic-op-prefetch.html

  * igt@xe_pm@s4-d3cold-basic-exec:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#2284] / [Intel XE#7370])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-5/igt@xe_pm@s4-d3cold-basic-exec.html

  * igt@xe_query@multigpu-query-uc-fw-version-huc:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#944])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-3/igt@xe_query@multigpu-query-uc-fw-version-huc.html

  * igt@xe_wedged@wedged-mode-toggle:
    - shard-bmg:          [PASS][31] -> [ABORT][32] ([Intel XE#8007])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5195-5ee88cba0806722ea2c6a969e61a33c061cdc9a4/shard-bmg-10/igt@xe_wedged@wedged-mode-toggle.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-7/igt@xe_wedged@wedged-mode-toggle.html

  
#### Possible fixes ####

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          [FAIL][33] ([Intel XE#301]) -> [PASS][34] +1 other test pass
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5195-5ee88cba0806722ea2c6a969e61a33c061cdc9a4/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-bmg:          [INCOMPLETE][35] ([Intel XE#2049] / [Intel XE#2597] / [Intel XE#8155]) -> [PASS][36] +1 other test pass
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5195-5ee88cba0806722ea2c6a969e61a33c061cdc9a4/shard-bmg-6/igt@kms_flip@flip-vs-suspend.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-3/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_hdr@static-toggle@pipe-a-hdmi-a-3-xrgb16161616f:
    - shard-bmg:          [SKIP][37] ([Intel XE#7915]) -> [PASS][38] +1 other test pass
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5195-5ee88cba0806722ea2c6a969e61a33c061cdc9a4/shard-bmg-7/igt@kms_hdr@static-toggle@pipe-a-hdmi-a-3-xrgb16161616f.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-4/igt@kms_hdr@static-toggle@pipe-a-hdmi-a-3-xrgb16161616f.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][39] ([Intel XE#6321]) -> [PASS][40] +1 other test pass
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5195-5ee88cba0806722ea2c6a969e61a33c061cdc9a4/shard-bmg-3/igt@xe_evict@evict-mixed-many-threads-small.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-1/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_oa@non-zero-reason-all@oag-0:
    - shard-bmg:          [FAIL][41] ([Intel XE#7334]) -> [PASS][42] +1 other test pass
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5195-5ee88cba0806722ea2c6a969e61a33c061cdc9a4/shard-bmg-7/igt@xe_oa@non-zero-reason-all@oag-0.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/shard-bmg-4/igt@xe_oa@non-zero-reason-all@oag-0.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2505]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2505
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7334]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7334
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7447
  [Intel XE#7571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7571
  [Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#7915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7915
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8155]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8155
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-5195-5ee88cba0806722ea2c6a969e61a33c061cdc9a4 -> xe-pw-157663v9

  IGT_8947: e322bfd77da04314dd310da9a6cf0562b5751f1f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5195-5ee88cba0806722ea2c6a969e61a33c061cdc9a4: 5ee88cba0806722ea2c6a969e61a33c061cdc9a4
  xe-pw-157663v9: 157663v9

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v9/index.html

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