[PATCH 0/6] drm/i915/dp: Enable UHBR link rates on tunneled links

[PATCH 0/6] drm/i915/dp: Enable UHBR link rates on tunneled links

[Imre Deak]

This patchset enables UHBR link rates on Thunderbolt tunneled links.

Imre Deak (6):
  drm/dp_tunnel: Add UHBR tunneling support
  drm/i915/dp: End link configuration loops properly
  drm/i915/dp: Enable SST fallback between UHBR and non-UHBR rates
  drm/i915/dp: Remove UHBR dependency from SST fallback kunit test
  drm/i915/dp: Disable UHBR link configs with 1/2 lanes
  drm/i915/dp_tunnel: Add UHBR tunneling support

 drivers/gpu/drm/display/drm_dp_tunnel.c       | 116 +++++++++++++++++-
 .../drm/i915/display/intel_display_types.h    |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  65 ++++++++--
 .../drm/i915/display/intel_dp_link_training.c |   5 -
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   5 +
 .../gpu/drm/i915/display/intel_dp_tunnel.c    |  45 +++++++
 .../gpu/drm/i915/display/intel_dp_tunnel.h    |  17 +++
 .../i915/display/tests/intel_dp_link_test.c   |  62 +++-------
 include/drm/display/drm_dp.h                  |  12 ++
 include/drm/display/drm_dp_tunnel.h           |  21 ++++
 10 files changed, 286 insertions(+), 63 deletions(-)

-- 
2.49.1

[PATCH 1/6] drm/dp_tunnel: Add UHBR tunneling support

[Imre Deak]

Add the DPCD registers and detection required to support UHBR link rates
over Thunderbolt tunnels.

Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/display/drm_dp_tunnel.c | 116 +++++++++++++++++++++++-
 include/drm/display/drm_dp.h            |  12 +++
 include/drm/display/drm_dp_tunnel.h     |  21 +++++
 3 files changed, 148 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/display/drm_dp_tunnel.c b/drivers/gpu/drm/display/drm_dp_tunnel.c
index 76c6bc84a806f..d29ad4116e641 100644
--- a/drivers/gpu/drm/display/drm_dp_tunnel.c
+++ b/drivers/gpu/drm/display/drm_dp_tunnel.c
@@ -111,6 +111,8 @@
 	DPTUN_REG(DP_ALLOCATED_BW) | \
 	DPTUN_REG(DP_TUNNELING_MAX_LINK_RATE) | \
 	DPTUN_REG(DP_TUNNELING_MAX_LANE_COUNT) | \
+	DPTUN_REG(DP_TUNNELING_MAIN_LINK_CHANNEL_CODING) | \
+	DPTUN_REG(DP_TUNNELING_128B132B_LINK_RATE) | \
 	DPTUN_REG(DP_DPTX_BW_ALLOCATION_MODE_CONTROL))
 
 static const DECLARE_BITMAP(dptun_info_regs, 64) = {
@@ -140,11 +142,14 @@ struct drm_dp_tunnel {
 	int estimated_bw;
 	int allocated_bw;
 
+	u8 dprx_128b132b_rates;
 	int max_dprx_rate;
 	u8 max_dprx_lane_count;
 
 	u8 adapter_id;
 
+	bool dprx_128b132b_support:1;
+	bool dprx_128b132b_lane0_mapping_support:1;
 	bool bw_alloc_supported:1;
 	bool bw_alloc_enabled:1;
 	bool has_io_error:1;
@@ -260,9 +265,46 @@ static int tunnel_reg_bw_granularity(const struct drm_dp_tunnel_regs *regs)
 	return (250000 << gr) / 8;
 }
 
+static bool tunnel_reg_dprx_128b132b_support(const struct drm_dp_tunnel_regs *regs)
+{
+	return tunnel_reg(regs, DP_TUNNELING_MAIN_LINK_CHANNEL_CODING) & DP_128B132B_DP_SUPPORTED;
+}
+
+static bool tunnel_reg_dprx_128b132b_lane0_mapping_support(const struct drm_dp_tunnel_regs *regs)
+{
+	return tunnel_reg(regs, DP_TUNNELING_128B132B_LINK_RATE) &
+	       DP_TUNNELING_128B132B_LL_LANE0_MAPPING_SUPPORT;
+}
+
+static u8 tunnel_reg_dprx_128b132b_rates(const struct drm_dp_tunnel_regs *regs)
+{
+	if (!tunnel_reg_dprx_128b132b_support(regs))
+		return 0;
+
+	return tunnel_reg(regs, DP_TUNNELING_128B132B_LINK_RATE) &
+	       DP_TUNNELING_128B132B_LINK_RATE_MASK;
+}
+
+static u8 max_128b132b_rate(u8 rates)
+{
+	if (rates & DP_TUNNELING_20GBPS_PER_LANE_SUPPORT)
+		return DP_TUNNELING_20GBPS_PER_LANE_SUPPORT;
+	else if (rates & DP_TUNNELING_13_5GBPS_PER_LANE_SUPPORT)
+		return DP_TUNNELING_13_5GBPS_PER_LANE_SUPPORT;
+	else if (rates & DP_TUNNELING_10GBPS_PER_LANE_SUPPORT)
+		return DP_TUNNELING_10GBPS_PER_LANE_SUPPORT;
+
+	WARN_ON(rates);
+
+	return 0;
+}
+
 static int tunnel_reg_max_dprx_rate(const struct drm_dp_tunnel_regs *regs)
 {
-	u8 bw_code = tunnel_reg(regs, DP_TUNNELING_MAX_LINK_RATE);
+	u8 bw_code = max_128b132b_rate(tunnel_reg_dprx_128b132b_rates(regs));
+
+	if (!bw_code)
+		bw_code = tunnel_reg(regs, DP_TUNNELING_MAX_LINK_RATE);
 
 	return drm_dp_bw_code_to_link_rate(bw_code);
 }
@@ -706,6 +748,23 @@ static bool update_dprx_caps(struct drm_dp_tunnel *tunnel, const struct drm_dp_t
 {
 	bool changed = false;
 
+	if (tunnel_reg_dprx_128b132b_support(regs) != tunnel->dprx_128b132b_support) {
+		tunnel->dprx_128b132b_support = tunnel_reg_dprx_128b132b_support(regs);
+		changed = true;
+	}
+
+	if (tunnel_reg_dprx_128b132b_lane0_mapping_support(regs) !=
+	    tunnel->dprx_128b132b_lane0_mapping_support) {
+		tunnel->dprx_128b132b_lane0_mapping_support =
+			tunnel_reg_dprx_128b132b_lane0_mapping_support(regs);
+		changed = true;
+	}
+
+	if (tunnel_reg_dprx_128b132b_rates(regs) != tunnel->dprx_128b132b_rates) {
+		tunnel->dprx_128b132b_rates = tunnel_reg_dprx_128b132b_rates(regs);
+		changed = true;
+	}
+
 	if (tunnel_reg_max_dprx_rate(regs) != tunnel->max_dprx_rate) {
 		tunnel->max_dprx_rate = tunnel_reg_max_dprx_rate(regs);
 		changed = true;
@@ -1331,6 +1390,61 @@ int drm_dp_tunnel_handle_irq(struct drm_dp_tunnel_mgr *mgr, struct drm_dp_aux *a
 }
 EXPORT_SYMBOL(drm_dp_tunnel_handle_irq);
 
+/**
+ * drm_dp_tunnel_128b132b_supported - Query if 128b132b is supported by the tunnel's DPRX
+ * @tunnel: Tunnel object
+ *
+ * The function is used to query if 128b132b is supported by the DPRX connected
+ * to @tunnel.
+ *
+ * Returns %true if 128b132b is supported by the DPRX.
+ */
+bool drm_dp_tunnel_128b132b_supported(const struct drm_dp_tunnel *tunnel)
+{
+	return tunnel->dprx_128b132b_support;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_128b132b_supported);
+
+/**
+ * drm_dp_tunnel_128b132b_lane0_mapping_supported - Check 128b/132b lane 0 mapping support
+ * @tunnel: Tunnel object
+ *
+ * Check whether the DP-out adapter always maps lane 0 as expected by the
+ * DPRX on a tunneled 128b/132b link. If the function returns %true, one- and
+ * two-lane configurations with UHBR link rates can always be used. If it
+ * returns %false, using one or two lanes with UHBR link rates may cause a
+ * lane-count conversion failure in the DPRX, requiring corrective action by
+ * the source during link training. See DP Standard v2.1b, section
+ * 3.5.2.16.3, 128b/132b DPRX Lane Count Conversion Failure Indication and
+ * Corrective Action.
+ *
+ * A four-lane configuration can always be used, provided that the DPRX
+ * supports it, regardless of the function's return value.
+ *
+ * Returns %true if the DP-out adapter supports the 128b/132b lane 0 mapping.
+ */
+bool drm_dp_tunnel_128b132b_lane0_mapping_supported(const struct drm_dp_tunnel *tunnel)
+{
+	return tunnel->dprx_128b132b_lane0_mapping_support;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_128b132b_lane0_mapping_supported);
+
+/**
+ * drm_dp_tunnel_128b132b_dprx_rates - Query the supported 128b132b rates of the tunnel's DPRX
+ * @tunnel: Tunnel object
+ *
+ * The function is used to query the supported 128b132b rates of the DPRX connected
+ * to @tunnel. Note that the related DP_128B132B_SUPPROTED_LINK_RATES DPCD
+ * register will indicate no supported 128B132B rates for a tunneled DPRX.
+ *
+ * Returns the mask of supported 128b132b rates.
+ */
+u8 drm_dp_tunnel_128b132b_dprx_rates(const struct drm_dp_tunnel *tunnel)
+{
+	return tunnel->dprx_128b132b_rates;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_128b132b_dprx_rates);
+
 /**
  * drm_dp_tunnel_max_dprx_rate - Query the maximum rate of the tunnel's DPRX
  * @tunnel: Tunnel object
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 7154216e0aff9..8b0ca36083dd1 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1506,6 +1506,18 @@
 #define DP_TUNNELING_MAX_LANE_COUNT			0xe0029
 #define  DP_TUNNELING_MAX_LANE_COUNT_MASK		0x1f
 
+#define DP_TUNNELING_MAIN_LINK_CHANNEL_CODING		0xe002b
+#define  DP_128B132B_DP_SUPPORTED			(1 << 0)
+
+#define DP_TUNNELING_128B132B_LINK_RATE			0xe002c
+#define  DP_TUNNELING_13_5GBPS_PER_LANE_SUPPORT		(1 << 2)
+#define  DP_TUNNELING_20GBPS_PER_LANE_SUPPORT		(1 << 1)
+#define  DP_TUNNELING_10GBPS_PER_LANE_SUPPORT		(1 << 0)
+#define  DP_TUNNELING_128B132B_LINK_RATE_MASK		(DP_TUNNELING_10GBPS_PER_LANE_SUPPORT | \
+							 DP_TUNNELING_13_5GBPS_PER_LANE_SUPPORT | \
+							 DP_TUNNELING_20GBPS_PER_LANE_SUPPORT)
+#define  DP_TUNNELING_128B132B_LL_LANE0_MAPPING_SUPPORT	(1 << 7)
+
 #define DP_DPTX_BW_ALLOCATION_MODE_CONTROL		0xe0030
 #define  DP_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE	(1 << 7)
 #define  DP_UNMASK_BW_ALLOCATION_IRQ			(1 << 6)
diff --git a/include/drm/display/drm_dp_tunnel.h b/include/drm/display/drm_dp_tunnel.h
index 57f5e90ba8fda..b5e665560a47e 100644
--- a/include/drm/display/drm_dp_tunnel.h
+++ b/include/drm/display/drm_dp_tunnel.h
@@ -63,6 +63,9 @@ void drm_dp_tunnel_set_io_error(struct drm_dp_tunnel *tunnel);
 int drm_dp_tunnel_handle_irq(struct drm_dp_tunnel_mgr *mgr,
 			     struct drm_dp_aux *aux);
 
+bool drm_dp_tunnel_128b132b_supported(const struct drm_dp_tunnel *tunnel);
+bool drm_dp_tunnel_128b132b_lane0_mapping_supported(const struct drm_dp_tunnel *tunnel);
+u8 drm_dp_tunnel_128b132b_dprx_rates(const struct drm_dp_tunnel *tunnel);
 int drm_dp_tunnel_max_dprx_rate(const struct drm_dp_tunnel *tunnel);
 int drm_dp_tunnel_max_dprx_lane_count(const struct drm_dp_tunnel *tunnel);
 int drm_dp_tunnel_available_bw(const struct drm_dp_tunnel *tunnel);
@@ -173,6 +176,24 @@ drm_dp_tunnel_handle_irq(struct drm_dp_tunnel_mgr *mgr,
 	return -EOPNOTSUPP;
 }
 
+static inline bool
+drm_dp_tunnel_128b132b_supported(const struct drm_dp_tunnel *tunnel)
+{
+	return false;
+}
+
+static inline bool
+drm_dp_tunnel_128b132b_lane0_mapping_supported(const struct drm_dp_tunnel *tunnel)
+{
+	return false;
+}
+
+static inline u8
+drm_dp_tunnel_128b132b_dprx_rates(const struct drm_dp_tunnel *tunnel)
+{
+	return 0;
+}
+
 static inline int
 drm_dp_tunnel_max_dprx_rate(const struct drm_dp_tunnel *tunnel)
 {
-- 
2.49.1

RE: [PATCH 1/6] drm/dp_tunnel: Add UHBR tunneling support

[Kandpal, Suraj]

> Subject: [PATCH 1/6] drm/dp_tunnel: Add UHBR tunneling support
> 
> Add the DPCD registers and detection required to support UHBR link rates over
> Thunderbolt tunnels.
> 
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Imre Deak <imre.deak@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/display/drm_dp_tunnel.c | 116 +++++++++++++++++++++++-
>  include/drm/display/drm_dp.h            |  12 +++
>  include/drm/display/drm_dp_tunnel.h     |  21 +++++
>  3 files changed, 148 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/display/drm_dp_tunnel.c
> b/drivers/gpu/drm/display/drm_dp_tunnel.c
> index 76c6bc84a806f..d29ad4116e641 100644
> --- a/drivers/gpu/drm/display/drm_dp_tunnel.c
> +++ b/drivers/gpu/drm/display/drm_dp_tunnel.c
> @@ -111,6 +111,8 @@
>  	DPTUN_REG(DP_ALLOCATED_BW) | \
>  	DPTUN_REG(DP_TUNNELING_MAX_LINK_RATE) | \
>  	DPTUN_REG(DP_TUNNELING_MAX_LANE_COUNT) | \
> +	DPTUN_REG(DP_TUNNELING_MAIN_LINK_CHANNEL_CODING) | \
> +	DPTUN_REG(DP_TUNNELING_128B132B_LINK_RATE) | \
>  	DPTUN_REG(DP_DPTX_BW_ALLOCATION_MODE_CONTROL))
> 
>  static const DECLARE_BITMAP(dptun_info_regs, 64) = { @@ -140,11 +142,14
> @@ struct drm_dp_tunnel {
>  	int estimated_bw;
>  	int allocated_bw;
> 
> +	u8 dprx_128b132b_rates;
>  	int max_dprx_rate;
>  	u8 max_dprx_lane_count;
> 
>  	u8 adapter_id;
> 
> +	bool dprx_128b132b_support:1;
> +	bool dprx_128b132b_lane0_mapping_support:1;
>  	bool bw_alloc_supported:1;
>  	bool bw_alloc_enabled:1;
>  	bool has_io_error:1;
> @@ -260,9 +265,46 @@ static int tunnel_reg_bw_granularity(const struct
> drm_dp_tunnel_regs *regs)
>  	return (250000 << gr) / 8;
>  }
> 
> +static bool tunnel_reg_dprx_128b132b_support(const struct
> +drm_dp_tunnel_regs *regs) {
> +	return tunnel_reg(regs,
> DP_TUNNELING_MAIN_LINK_CHANNEL_CODING) &
> +DP_128B132B_DP_SUPPORTED; }
> +
> +static bool tunnel_reg_dprx_128b132b_lane0_mapping_support(const struct
> +drm_dp_tunnel_regs *regs) {
> +	return tunnel_reg(regs, DP_TUNNELING_128B132B_LINK_RATE) &
> +	       DP_TUNNELING_128B132B_LL_LANE0_MAPPING_SUPPORT;
> +}
> +
> +static u8 tunnel_reg_dprx_128b132b_rates(const struct
> +drm_dp_tunnel_regs *regs) {
> +	if (!tunnel_reg_dprx_128b132b_support(regs))
> +		return 0;
> +
> +	return tunnel_reg(regs, DP_TUNNELING_128B132B_LINK_RATE) &
> +	       DP_TUNNELING_128B132B_LINK_RATE_MASK;
> +}
> +
> +static u8 max_128b132b_rate(u8 rates)
> +{
> +	if (rates & DP_TUNNELING_20GBPS_PER_LANE_SUPPORT)
> +		return DP_TUNNELING_20GBPS_PER_LANE_SUPPORT;
> +	else if (rates & DP_TUNNELING_13_5GBPS_PER_LANE_SUPPORT)
> +		return DP_TUNNELING_13_5GBPS_PER_LANE_SUPPORT;
> +	else if (rates & DP_TUNNELING_10GBPS_PER_LANE_SUPPORT)
> +		return DP_TUNNELING_10GBPS_PER_LANE_SUPPORT;
> +
> +	WARN_ON(rates);
> +
> +	return 0;
> +}
> +
>  static int tunnel_reg_max_dprx_rate(const struct drm_dp_tunnel_regs *regs)  {
> -	u8 bw_code = tunnel_reg(regs, DP_TUNNELING_MAX_LINK_RATE);
> +	u8 bw_code =
> max_128b132b_rate(tunnel_reg_dprx_128b132b_rates(regs));
> +
> +	if (!bw_code)
> +		bw_code = tunnel_reg(regs,
> DP_TUNNELING_MAX_LINK_RATE);
> 
>  	return drm_dp_bw_code_to_link_rate(bw_code);
>  }
> @@ -706,6 +748,23 @@ static bool update_dprx_caps(struct drm_dp_tunnel
> *tunnel, const struct drm_dp_t  {
>  	bool changed = false;
> 
> +	if (tunnel_reg_dprx_128b132b_support(regs) != tunnel-
> >dprx_128b132b_support) {
> +		tunnel->dprx_128b132b_support =
> tunnel_reg_dprx_128b132b_support(regs);
> +		changed = true;
> +	}
> +
> +	if (tunnel_reg_dprx_128b132b_lane0_mapping_support(regs) !=
> +	    tunnel->dprx_128b132b_lane0_mapping_support) {
> +		tunnel->dprx_128b132b_lane0_mapping_support =
> +
> 	tunnel_reg_dprx_128b132b_lane0_mapping_support(regs);
> +		changed = true;
> +	}
> +
> +	if (tunnel_reg_dprx_128b132b_rates(regs) != tunnel-
> >dprx_128b132b_rates) {
> +		tunnel->dprx_128b132b_rates =
> tunnel_reg_dprx_128b132b_rates(regs);
> +		changed = true;
> +	}
> +
>  	if (tunnel_reg_max_dprx_rate(regs) != tunnel->max_dprx_rate) {
>  		tunnel->max_dprx_rate = tunnel_reg_max_dprx_rate(regs);
>  		changed = true;
> @@ -1331,6 +1390,61 @@ int drm_dp_tunnel_handle_irq(struct
> drm_dp_tunnel_mgr *mgr, struct drm_dp_aux *a  }
> EXPORT_SYMBOL(drm_dp_tunnel_handle_irq);
> 
> +/**
> + * drm_dp_tunnel_128b132b_supported - Query if 128b132b is supported by
> +the tunnel's DPRX
> + * @tunnel: Tunnel object
> + *
> + * The function is used to query if 128b132b is supported by the DPRX
> +connected
> + * to @tunnel.
> + *
> + * Returns %true if 128b132b is supported by the DPRX.
> + */
> +bool drm_dp_tunnel_128b132b_supported(const struct drm_dp_tunnel
> +*tunnel) {
> +	return tunnel->dprx_128b132b_support;
> +}
> +EXPORT_SYMBOL(drm_dp_tunnel_128b132b_supported);
> +
> +/**
> + * drm_dp_tunnel_128b132b_lane0_mapping_supported - Check 128b/132b
> +lane 0 mapping support
> + * @tunnel: Tunnel object
> + *
> + * Check whether the DP-out adapter always maps lane 0 as expected by
> +the
> + * DPRX on a tunneled 128b/132b link. If the function returns %true,
> +one- and
> + * two-lane configurations with UHBR link rates can always be used. If
> +it
> + * returns %false, using one or two lanes with UHBR link rates may
> +cause a
> + * lane-count conversion failure in the DPRX, requiring corrective
> +action by
> + * the source during link training. See DP Standard v2.1b, section
> + * 3.5.2.16.3, 128b/132b DPRX Lane Count Conversion Failure Indication
> +and
> + * Corrective Action.
> + *
> + * A four-lane configuration can always be used, provided that the DPRX
> + * supports it, regardless of the function's return value.
> + *
> + * Returns %true if the DP-out adapter supports the 128b/132b lane 0
> mapping.
> + */
> +bool drm_dp_tunnel_128b132b_lane0_mapping_supported(const struct
> +drm_dp_tunnel *tunnel) {
> +	return tunnel->dprx_128b132b_lane0_mapping_support;
> +}
> +EXPORT_SYMBOL(drm_dp_tunnel_128b132b_lane0_mapping_supported);
> +
> +/**
> + * drm_dp_tunnel_128b132b_dprx_rates - Query the supported 128b132b
> +rates of the tunnel's DPRX
> + * @tunnel: Tunnel object
> + *
> + * The function is used to query the supported 128b132b rates of the
> +DPRX connected
> + * to @tunnel. Note that the related DP_128B132B_SUPPROTED_LINK_RATES
> +DPCD
> + * register will indicate no supported 128B132B rates for a tunneled DPRX.
> + *
> + * Returns the mask of supported 128b132b rates.
> + */
> +u8 drm_dp_tunnel_128b132b_dprx_rates(const struct drm_dp_tunnel
> +*tunnel) {
> +	return tunnel->dprx_128b132b_rates;
> +}
> +EXPORT_SYMBOL(drm_dp_tunnel_128b132b_dprx_rates);
> +
>  /**
>   * drm_dp_tunnel_max_dprx_rate - Query the maximum rate of the tunnel's
> DPRX
>   * @tunnel: Tunnel object
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index 7154216e0aff9..8b0ca36083dd1 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -1506,6 +1506,18 @@
>  #define DP_TUNNELING_MAX_LANE_COUNT			0xe0029
>  #define  DP_TUNNELING_MAX_LANE_COUNT_MASK		0x1f
> 
> +#define DP_TUNNELING_MAIN_LINK_CHANNEL_CODING
> 	0xe002b
> +#define  DP_128B132B_DP_SUPPORTED			(1 << 0)
> +
> +#define DP_TUNNELING_128B132B_LINK_RATE			0xe002c
> +#define  DP_TUNNELING_13_5GBPS_PER_LANE_SUPPORT		(1 <<
> 2)
> +#define  DP_TUNNELING_20GBPS_PER_LANE_SUPPORT		(1 <<
> 1)
> +#define  DP_TUNNELING_10GBPS_PER_LANE_SUPPORT		(1 <<
> 0)
> +#define  DP_TUNNELING_128B132B_LINK_RATE_MASK
> 	(DP_TUNNELING_10GBPS_PER_LANE_SUPPORT | \
> +
> DP_TUNNELING_13_5GBPS_PER_LANE_SUPPORT | \
> +
> DP_TUNNELING_20GBPS_PER_LANE_SUPPORT)
> +#define  DP_TUNNELING_128B132B_LL_LANE0_MAPPING_SUPPORT	(1 <<
> 7)
> +
>  #define DP_DPTX_BW_ALLOCATION_MODE_CONTROL		0xe0030
>  #define  DP_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE	(1 <<
> 7)
>  #define  DP_UNMASK_BW_ALLOCATION_IRQ			(1 << 6)
> diff --git a/include/drm/display/drm_dp_tunnel.h
> b/include/drm/display/drm_dp_tunnel.h
> index 57f5e90ba8fda..b5e665560a47e 100644
> --- a/include/drm/display/drm_dp_tunnel.h
> +++ b/include/drm/display/drm_dp_tunnel.h
> @@ -63,6 +63,9 @@ void drm_dp_tunnel_set_io_error(struct drm_dp_tunnel
> *tunnel);  int drm_dp_tunnel_handle_irq(struct drm_dp_tunnel_mgr *mgr,
>  			     struct drm_dp_aux *aux);
> 
> +bool drm_dp_tunnel_128b132b_supported(const struct drm_dp_tunnel
> +*tunnel); bool drm_dp_tunnel_128b132b_lane0_mapping_supported(const
> +struct drm_dp_tunnel *tunnel);
> +u8 drm_dp_tunnel_128b132b_dprx_rates(const struct drm_dp_tunnel
> +*tunnel);
>  int drm_dp_tunnel_max_dprx_rate(const struct drm_dp_tunnel *tunnel);  int
> drm_dp_tunnel_max_dprx_lane_count(const struct drm_dp_tunnel *tunnel);
> int drm_dp_tunnel_available_bw(const struct drm_dp_tunnel *tunnel); @@ -
> 173,6 +176,24 @@ drm_dp_tunnel_handle_irq(struct drm_dp_tunnel_mgr
> *mgr,
>  	return -EOPNOTSUPP;
>  }
> 
> +static inline bool
> +drm_dp_tunnel_128b132b_supported(const struct drm_dp_tunnel *tunnel) {
> +	return false;
> +}
> +
> +static inline bool
> +drm_dp_tunnel_128b132b_lane0_mapping_supported(const struct
> +drm_dp_tunnel *tunnel) {
> +	return false;
> +}
> +
> +static inline u8
> +drm_dp_tunnel_128b132b_dprx_rates(const struct drm_dp_tunnel *tunnel)
> {
> +	return 0;
> +}
> +
>  static inline int
>  drm_dp_tunnel_max_dprx_rate(const struct drm_dp_tunnel *tunnel)  {
> --
> 2.49.1

Re: [PATCH 1/6] drm/dp_tunnel: Add UHBR tunneling support

[Imre Deak]

Hi Thomas, Maarten, Maxime,

could you please ack merging this patch via the Intel trees? It adds the
DP tunnel register definitions for UHBR link rates and reading/parsing
them, which are then used later in this patchset by the Intel driver.

Thanks,
Imre

On Tue, Jul 14, 2026 at 06:26:55PM +0300, Imre Deak wrote:
> Add the DPCD registers and detection required to support UHBR link rates
> over Thunderbolt tunnels.
> 
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/display/drm_dp_tunnel.c | 116 +++++++++++++++++++++++-
>  include/drm/display/drm_dp.h            |  12 +++
>  include/drm/display/drm_dp_tunnel.h     |  21 +++++
>  3 files changed, 148 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/display/drm_dp_tunnel.c b/drivers/gpu/drm/display/drm_dp_tunnel.c
> index 76c6bc84a806f..d29ad4116e641 100644
> --- a/drivers/gpu/drm/display/drm_dp_tunnel.c
> +++ b/drivers/gpu/drm/display/drm_dp_tunnel.c
> @@ -111,6 +111,8 @@
>  	DPTUN_REG(DP_ALLOCATED_BW) | \
>  	DPTUN_REG(DP_TUNNELING_MAX_LINK_RATE) | \
>  	DPTUN_REG(DP_TUNNELING_MAX_LANE_COUNT) | \
> +	DPTUN_REG(DP_TUNNELING_MAIN_LINK_CHANNEL_CODING) | \
> +	DPTUN_REG(DP_TUNNELING_128B132B_LINK_RATE) | \
>  	DPTUN_REG(DP_DPTX_BW_ALLOCATION_MODE_CONTROL))
>  
>  static const DECLARE_BITMAP(dptun_info_regs, 64) = {
> @@ -140,11 +142,14 @@ struct drm_dp_tunnel {
>  	int estimated_bw;
>  	int allocated_bw;
>  
> +	u8 dprx_128b132b_rates;
>  	int max_dprx_rate;
>  	u8 max_dprx_lane_count;
>  
>  	u8 adapter_id;
>  
> +	bool dprx_128b132b_support:1;
> +	bool dprx_128b132b_lane0_mapping_support:1;
>  	bool bw_alloc_supported:1;
>  	bool bw_alloc_enabled:1;
>  	bool has_io_error:1;
> @@ -260,9 +265,46 @@ static int tunnel_reg_bw_granularity(const struct drm_dp_tunnel_regs *regs)
>  	return (250000 << gr) / 8;
>  }
>  
> +static bool tunnel_reg_dprx_128b132b_support(const struct drm_dp_tunnel_regs *regs)
> +{
> +	return tunnel_reg(regs, DP_TUNNELING_MAIN_LINK_CHANNEL_CODING) & DP_128B132B_DP_SUPPORTED;
> +}
> +
> +static bool tunnel_reg_dprx_128b132b_lane0_mapping_support(const struct drm_dp_tunnel_regs *regs)
> +{
> +	return tunnel_reg(regs, DP_TUNNELING_128B132B_LINK_RATE) &
> +	       DP_TUNNELING_128B132B_LL_LANE0_MAPPING_SUPPORT;
> +}
> +
> +static u8 tunnel_reg_dprx_128b132b_rates(const struct drm_dp_tunnel_regs *regs)
> +{
> +	if (!tunnel_reg_dprx_128b132b_support(regs))
> +		return 0;
> +
> +	return tunnel_reg(regs, DP_TUNNELING_128B132B_LINK_RATE) &
> +	       DP_TUNNELING_128B132B_LINK_RATE_MASK;
> +}
> +
> +static u8 max_128b132b_rate(u8 rates)
> +{
> +	if (rates & DP_TUNNELING_20GBPS_PER_LANE_SUPPORT)
> +		return DP_TUNNELING_20GBPS_PER_LANE_SUPPORT;
> +	else if (rates & DP_TUNNELING_13_5GBPS_PER_LANE_SUPPORT)
> +		return DP_TUNNELING_13_5GBPS_PER_LANE_SUPPORT;
> +	else if (rates & DP_TUNNELING_10GBPS_PER_LANE_SUPPORT)
> +		return DP_TUNNELING_10GBPS_PER_LANE_SUPPORT;
> +
> +	WARN_ON(rates);
> +
> +	return 0;
> +}
> +
>  static int tunnel_reg_max_dprx_rate(const struct drm_dp_tunnel_regs *regs)
>  {
> -	u8 bw_code = tunnel_reg(regs, DP_TUNNELING_MAX_LINK_RATE);
> +	u8 bw_code = max_128b132b_rate(tunnel_reg_dprx_128b132b_rates(regs));
> +
> +	if (!bw_code)
> +		bw_code = tunnel_reg(regs, DP_TUNNELING_MAX_LINK_RATE);
>  
>  	return drm_dp_bw_code_to_link_rate(bw_code);
>  }
> @@ -706,6 +748,23 @@ static bool update_dprx_caps(struct drm_dp_tunnel *tunnel, const struct drm_dp_t
>  {
>  	bool changed = false;
>  
> +	if (tunnel_reg_dprx_128b132b_support(regs) != tunnel->dprx_128b132b_support) {
> +		tunnel->dprx_128b132b_support = tunnel_reg_dprx_128b132b_support(regs);
> +		changed = true;
> +	}
> +
> +	if (tunnel_reg_dprx_128b132b_lane0_mapping_support(regs) !=
> +	    tunnel->dprx_128b132b_lane0_mapping_support) {
> +		tunnel->dprx_128b132b_lane0_mapping_support =
> +			tunnel_reg_dprx_128b132b_lane0_mapping_support(regs);
> +		changed = true;
> +	}
> +
> +	if (tunnel_reg_dprx_128b132b_rates(regs) != tunnel->dprx_128b132b_rates) {
> +		tunnel->dprx_128b132b_rates = tunnel_reg_dprx_128b132b_rates(regs);
> +		changed = true;
> +	}
> +
>  	if (tunnel_reg_max_dprx_rate(regs) != tunnel->max_dprx_rate) {
>  		tunnel->max_dprx_rate = tunnel_reg_max_dprx_rate(regs);
>  		changed = true;
> @@ -1331,6 +1390,61 @@ int drm_dp_tunnel_handle_irq(struct drm_dp_tunnel_mgr *mgr, struct drm_dp_aux *a
>  }
>  EXPORT_SYMBOL(drm_dp_tunnel_handle_irq);
>  
> +/**
> + * drm_dp_tunnel_128b132b_supported - Query if 128b132b is supported by the tunnel's DPRX
> + * @tunnel: Tunnel object
> + *
> + * The function is used to query if 128b132b is supported by the DPRX connected
> + * to @tunnel.
> + *
> + * Returns %true if 128b132b is supported by the DPRX.
> + */
> +bool drm_dp_tunnel_128b132b_supported(const struct drm_dp_tunnel *tunnel)
> +{
> +	return tunnel->dprx_128b132b_support;
> +}
> +EXPORT_SYMBOL(drm_dp_tunnel_128b132b_supported);
> +
> +/**
> + * drm_dp_tunnel_128b132b_lane0_mapping_supported - Check 128b/132b lane 0 mapping support
> + * @tunnel: Tunnel object
> + *
> + * Check whether the DP-out adapter always maps lane 0 as expected by the
> + * DPRX on a tunneled 128b/132b link. If the function returns %true, one- and
> + * two-lane configurations with UHBR link rates can always be used. If it
> + * returns %false, using one or two lanes with UHBR link rates may cause a
> + * lane-count conversion failure in the DPRX, requiring corrective action by
> + * the source during link training. See DP Standard v2.1b, section
> + * 3.5.2.16.3, 128b/132b DPRX Lane Count Conversion Failure Indication and
> + * Corrective Action.
> + *
> + * A four-lane configuration can always be used, provided that the DPRX
> + * supports it, regardless of the function's return value.
> + *
> + * Returns %true if the DP-out adapter supports the 128b/132b lane 0 mapping.
> + */
> +bool drm_dp_tunnel_128b132b_lane0_mapping_supported(const struct drm_dp_tunnel *tunnel)
> +{
> +	return tunnel->dprx_128b132b_lane0_mapping_support;
> +}
> +EXPORT_SYMBOL(drm_dp_tunnel_128b132b_lane0_mapping_supported);
> +
> +/**
> + * drm_dp_tunnel_128b132b_dprx_rates - Query the supported 128b132b rates of the tunnel's DPRX
> + * @tunnel: Tunnel object
> + *
> + * The function is used to query the supported 128b132b rates of the DPRX connected
> + * to @tunnel. Note that the related DP_128B132B_SUPPROTED_LINK_RATES DPCD
> + * register will indicate no supported 128B132B rates for a tunneled DPRX.
> + *
> + * Returns the mask of supported 128b132b rates.
> + */
> +u8 drm_dp_tunnel_128b132b_dprx_rates(const struct drm_dp_tunnel *tunnel)
> +{
> +	return tunnel->dprx_128b132b_rates;
> +}
> +EXPORT_SYMBOL(drm_dp_tunnel_128b132b_dprx_rates);
> +
>  /**
>   * drm_dp_tunnel_max_dprx_rate - Query the maximum rate of the tunnel's DPRX
>   * @tunnel: Tunnel object
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index 7154216e0aff9..8b0ca36083dd1 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -1506,6 +1506,18 @@
>  #define DP_TUNNELING_MAX_LANE_COUNT			0xe0029
>  #define  DP_TUNNELING_MAX_LANE_COUNT_MASK		0x1f
>  
> +#define DP_TUNNELING_MAIN_LINK_CHANNEL_CODING		0xe002b
> +#define  DP_128B132B_DP_SUPPORTED			(1 << 0)
> +
> +#define DP_TUNNELING_128B132B_LINK_RATE			0xe002c
> +#define  DP_TUNNELING_13_5GBPS_PER_LANE_SUPPORT		(1 << 2)
> +#define  DP_TUNNELING_20GBPS_PER_LANE_SUPPORT		(1 << 1)
> +#define  DP_TUNNELING_10GBPS_PER_LANE_SUPPORT		(1 << 0)
> +#define  DP_TUNNELING_128B132B_LINK_RATE_MASK		(DP_TUNNELING_10GBPS_PER_LANE_SUPPORT | \
> +							 DP_TUNNELING_13_5GBPS_PER_LANE_SUPPORT | \
> +							 DP_TUNNELING_20GBPS_PER_LANE_SUPPORT)
> +#define  DP_TUNNELING_128B132B_LL_LANE0_MAPPING_SUPPORT	(1 << 7)
> +
>  #define DP_DPTX_BW_ALLOCATION_MODE_CONTROL		0xe0030
>  #define  DP_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE	(1 << 7)
>  #define  DP_UNMASK_BW_ALLOCATION_IRQ			(1 << 6)
> diff --git a/include/drm/display/drm_dp_tunnel.h b/include/drm/display/drm_dp_tunnel.h
> index 57f5e90ba8fda..b5e665560a47e 100644
> --- a/include/drm/display/drm_dp_tunnel.h
> +++ b/include/drm/display/drm_dp_tunnel.h
> @@ -63,6 +63,9 @@ void drm_dp_tunnel_set_io_error(struct drm_dp_tunnel *tunnel);
>  int drm_dp_tunnel_handle_irq(struct drm_dp_tunnel_mgr *mgr,
>  			     struct drm_dp_aux *aux);
>  
> +bool drm_dp_tunnel_128b132b_supported(const struct drm_dp_tunnel *tunnel);
> +bool drm_dp_tunnel_128b132b_lane0_mapping_supported(const struct drm_dp_tunnel *tunnel);
> +u8 drm_dp_tunnel_128b132b_dprx_rates(const struct drm_dp_tunnel *tunnel);
>  int drm_dp_tunnel_max_dprx_rate(const struct drm_dp_tunnel *tunnel);
>  int drm_dp_tunnel_max_dprx_lane_count(const struct drm_dp_tunnel *tunnel);
>  int drm_dp_tunnel_available_bw(const struct drm_dp_tunnel *tunnel);
> @@ -173,6 +176,24 @@ drm_dp_tunnel_handle_irq(struct drm_dp_tunnel_mgr *mgr,
>  	return -EOPNOTSUPP;
>  }
>  
> +static inline bool
> +drm_dp_tunnel_128b132b_supported(const struct drm_dp_tunnel *tunnel)
> +{
> +	return false;
> +}
> +
> +static inline bool
> +drm_dp_tunnel_128b132b_lane0_mapping_supported(const struct drm_dp_tunnel *tunnel)
> +{
> +	return false;
> +}
> +
> +static inline u8
> +drm_dp_tunnel_128b132b_dprx_rates(const struct drm_dp_tunnel *tunnel)
> +{
> +	return 0;
> +}
> +
>  static inline int
>  drm_dp_tunnel_max_dprx_rate(const struct drm_dp_tunnel *tunnel)
>  {
> -- 
> 2.49.1
> 

[PATCH 2/6] drm/i915/dp: End link configuration loops properly

[Imre Deak]

Call intel_dp_link_caps_iter_end() after the link configuration loops.
At the moment this call only clears the iteration object, so the lack of
call didn't cause an actual issue.

Cc: Luca Coelho <luciano.coelho@intel.com>
Fixes: 7266df62ed0a7 ("drm/i915/dp: Iterate configurations via link_caps for SST non-DSC")
Fixes: 4f104fc10a461 ("drm/i915/dp: Iterate configurations via link_caps for SST DSC")
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0922d23b284ca..0d2c696b9e4b0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1688,6 +1688,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
 	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
 	struct intel_dp_link_caps_order order =
 		intel_dp_link_caps_connector_compute_order(connector);
+	int err = -EINVAL;
 	int link_avail;
 
 	for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16);
@@ -1718,12 +1719,18 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
 				pipe_config->pipe_bpp = bpp;
 				pipe_config->port_clock = link_config.rate;
 
-				return 0;
+				err = 0;
+
+				break;
 			}
 		}
+		intel_dp_link_caps_iter_end(&iter);
+
+		if (!err)
+			break;
 	}
 
-	return -EINVAL;
+	return err;
 }
 
 int intel_dp_dsc_max_src_input_bpc(struct intel_display *display)
@@ -1924,6 +1931,7 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
 		intel_dp_link_caps_connector_compute_order(connector);
 	struct intel_dp_link_config link_config;
 	struct intel_dp_link_caps_iter iter;
+	int err = -EINVAL;
 
 	intel_dp_link_caps_iter_start(&iter, link_caps, order, limits->link_config_filter);
 	for_each_dp_link_config(&iter, &link_config) {
@@ -1966,10 +1974,13 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
 				continue;
 		}
 
-		return 0;
-	}
+		err = 0;
 
-	return -EINVAL;
+		break;
+	}
+	intel_dp_link_caps_iter_end(&iter);
+
+	return err;
 }
 
 static u16 intel_dp_dsc_max_delta_bppx16(const struct intel_connector *connector,
-- 
2.49.1

RE: [PATCH 2/6] drm/i915/dp: End link configuration loops properly

[Kandpal, Suraj]

> Subject: [PATCH 2/6] drm/i915/dp: End link configuration loops properly
> 
> Call intel_dp_link_caps_iter_end() after the link configuration loops.
> At the moment this call only clears the iteration object, so the lack of call didn't
> cause an actual issue.
> 
> Cc: Luca Coelho <luciano.coelho@intel.com>
> Fixes: 7266df62ed0a7 ("drm/i915/dp: Iterate configurations via link_caps for
> SST non-DSC")
> Fixes: 4f104fc10a461 ("drm/i915/dp: Iterate configurations via link_caps for SST
> DSC")
> Signed-off-by: Imre Deak <imre.deak@intel.com>

LGTM
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 21 ++++++++++++++++-----
>  1 file changed, 16 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0922d23b284ca..0d2c696b9e4b0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1688,6 +1688,7 @@ intel_dp_compute_link_config_wide(struct intel_dp
> *intel_dp,
>  	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
>  	struct intel_dp_link_caps_order order =
>  		intel_dp_link_caps_connector_compute_order(connector);
> +	int err = -EINVAL;
>  	int link_avail;
> 
>  	for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16);
> @@ -1718,12 +1719,18 @@ intel_dp_compute_link_config_wide(struct
> intel_dp *intel_dp,
>  				pipe_config->pipe_bpp = bpp;
>  				pipe_config->port_clock = link_config.rate;
> 
> -				return 0;
> +				err = 0;
> +
> +				break;
>  			}
>  		}
> +		intel_dp_link_caps_iter_end(&iter);
> +
> +		if (!err)
> +			break;
>  	}
> 
> -	return -EINVAL;
> +	return err;
>  }
> 
>  int intel_dp_dsc_max_src_input_bpc(struct intel_display *display) @@ -1924,6
> +1931,7 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
>  		intel_dp_link_caps_connector_compute_order(connector);
>  	struct intel_dp_link_config link_config;
>  	struct intel_dp_link_caps_iter iter;
> +	int err = -EINVAL;
> 
>  	intel_dp_link_caps_iter_start(&iter, link_caps, order, limits-
> >link_config_filter);
>  	for_each_dp_link_config(&iter, &link_config) { @@ -1966,10 +1974,13
> @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
>  				continue;
>  		}
> 
> -		return 0;
> -	}
> +		err = 0;
> 
> -	return -EINVAL;
> +		break;
> +	}
> +	intel_dp_link_caps_iter_end(&iter);
> +
> +	return err;
>  }
> 
>  static u16 intel_dp_dsc_max_delta_bppx16(const struct intel_connector
> *connector,
> --
> 2.49.1

[PATCH 3/6] drm/i915/dp: Enable SST fallback between UHBR and non-UHBR rates

[Imre Deak]

Enable link training fallback between UHBR and non-UHBR link rates on DP
SST links. This was disabled so far to preserve the fallback behavior.
There isn't a known issue related to such a fallback and DP MST has been
using this for a while already. Also, enabling UHBR rates over
Thunderbolt tunnels in a follow-up change, which at least on some links
supports only 4 lanes and not 1 or 2 lanes on UHBR, makes a
UHBR->non-UHBR fallback scenario more likely.

At the same time align the corresponding link training fallback kunit
test, allowing a UHBR <-> non-UHBR fallback there as well.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../gpu/drm/i915/display/intel_dp_link_training.c |  5 -----
 .../drm/i915/display/tests/intel_dp_link_test.c   | 15 +++------------
 2 files changed, 3 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index fa55664c9d98e..cb92cff906146 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1874,11 +1874,6 @@ static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crt
 			continue;
 		}
 
-		if (!is_mst &&
-		    drm_dp_is_uhbr_rate(config.rate) !=
-		    drm_dp_is_uhbr_rate(old_config.rate))
-			continue;
-
 		*new_link_rate = config.rate;
 		*new_lane_count = config.lane_count;
 		new_found = true;
diff --git a/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c b/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
index e1c356ba11b59..776d93f333851 100644
--- a/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
+++ b/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
@@ -1199,11 +1199,6 @@ get_fallback_configs_for_output_type(struct kunit *test,
 	}
 }
 
-static bool output_type_allows_uhbr_fallback(enum intel_output_type output_type)
-{
-	return output_type == INTEL_OUTPUT_DP_MST;
-}
-
 static void assert_config_is_supported(const struct test_config_table *expected_table,
 				       const struct intel_dp_link_config *config)
 {
@@ -1230,14 +1225,10 @@ static bool get_fallback_config(const struct test_config_table *expected_table,
 		const struct intel_dp_link_config *config =
 			&config_set->entries[i];
 
-		if (output_type_allows_uhbr_fallback(output_type) ||
-		    (drm_dp_is_uhbr_rate(target_config->rate) ==
-		     drm_dp_is_uhbr_rate(config->rate))) {
-			assert_config_is_supported(expected_table, config);
-			*fallback_config = *config;
+		assert_config_is_supported(expected_table, config);
+		*fallback_config = *config;
 
-			return true;
-		}
+		return true;
 	}
 
 	return false;
-- 
2.49.1

RE: [PATCH 3/6] drm/i915/dp: Enable SST fallback between UHBR and non-UHBR rates

[Kandpal, Suraj]

> Subject: [PATCH 3/6] drm/i915/dp: Enable SST fallback between UHBR and non-
> UHBR rates
> 
> Enable link training fallback between UHBR and non-UHBR link rates on DP SST
> links. This was disabled so far to preserve the fallback behavior.
> There isn't a known issue related to such a fallback and DP MST has been using
> this for a while already. Also, enabling UHBR rates over Thunderbolt tunnels in
> a follow-up change, which at least on some links supports only 4 lanes and not 1
> or 2 lanes on UHBR, makes a
> UHBR->non-UHBR fallback scenario more likely.
> 
> At the same time align the corresponding link training fallback kunit test,
> allowing a UHBR <-> non-UHBR fallback there as well.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  .../gpu/drm/i915/display/intel_dp_link_training.c |  5 -----
>  .../drm/i915/display/tests/intel_dp_link_test.c   | 15 +++------------
>  2 files changed, 3 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index fa55664c9d98e..cb92cff906146 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -1874,11 +1874,6 @@ static bool reduce_link_params(struct intel_dp
> *intel_dp, const struct intel_crt
>  			continue;
>  		}
> 
> -		if (!is_mst &&
> -		    drm_dp_is_uhbr_rate(config.rate) !=
> -		    drm_dp_is_uhbr_rate(old_config.rate))
> -			continue;
> -
>  		*new_link_rate = config.rate;
>  		*new_lane_count = config.lane_count;
>  		new_found = true;
> diff --git a/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
> b/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
> index e1c356ba11b59..776d93f333851 100644
> --- a/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
> +++ b/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
> @@ -1199,11 +1199,6 @@ get_fallback_configs_for_output_type(struct kunit
> *test,
>  	}
>  }
> 
> -static bool output_type_allows_uhbr_fallback(enum intel_output_type
> output_type) -{
> -	return output_type == INTEL_OUTPUT_DP_MST;
> -}
> -
>  static void assert_config_is_supported(const struct test_config_table
> *expected_table,
>  				       const struct intel_dp_link_config *config)  {
> @@ -1230,14 +1225,10 @@ static bool get_fallback_config(const struct
> test_config_table *expected_table,
>  		const struct intel_dp_link_config *config =
>  			&config_set->entries[i];
> 
> -		if (output_type_allows_uhbr_fallback(output_type) ||
> -		    (drm_dp_is_uhbr_rate(target_config->rate) ==
> -		     drm_dp_is_uhbr_rate(config->rate))) {
> -			assert_config_is_supported(expected_table, config);
> -			*fallback_config = *config;
> +		assert_config_is_supported(expected_table, config);
> +		*fallback_config = *config;
> 
> -			return true;
> -		}
> +		return true;
>  	}
> 
>  	return false;
> --
> 2.49.1

[PATCH 4/6] drm/i915/dp: Remove UHBR dependency from SST fallback kunit test

[Imre Deak]

After fallback between UHBR and non-UHBR link rates got enabled in a
previous change, there is no need to test fallback sequences for UHBR
and non-UHBR rates separately. Make the test simply start from the
maximum (UHBR) rate.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../i915/display/tests/intel_dp_link_test.c   | 47 +++++--------------
 1 file changed, 12 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c b/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
index 776d93f333851..67c6fe9f1812a 100644
--- a/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
+++ b/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
@@ -1101,7 +1101,7 @@ static void intel_dp_link_test_fallback_for_edp(struct kunit *test)
 }
 
 static bool test_fallback_from_target(struct test_config_table *expected_table,
-				      enum intel_output_type output_type, int max_rate,
+				      enum intel_output_type output_type,
 				      const struct intel_dp_link_config *expected_target_config,
 				      const struct intel_dp_link_config *expected_fallback_config)
 {
@@ -1123,8 +1123,7 @@ static bool test_fallback_from_target(struct test_config_table *expected_table,
 	/* Get the max connector config, optionally filtered to the max_rate limit. */
 	lc_ops->iter_start(&iter, link_caps, fallback_order, INTEL_DP_LINK_CAPS_FILTER_ALL);
 	for_each_dp_link_config(&iter, &iter_config)
-		if (max_rate == 0 || iter_config.rate <= max_rate)
-			break;
+		break;
 	lc_ops->iter_end(&iter);
 
 	KUNIT_EXPECT_TRUE(test, link_configs_match(&iter_config,
@@ -1236,7 +1235,6 @@ static bool get_fallback_config(const struct test_config_table *expected_table,
 
 static bool get_target_config(const struct test_config_table *expected_table,
 			      enum intel_output_type output_type,
-			      int max_rate,
 			      struct intel_dp_link_config *target)
 {
 	struct kunit *test = expected_table->test;
@@ -1248,20 +1246,17 @@ static bool get_target_config(const struct test_config_table *expected_table,
 		const struct intel_dp_link_config *config =
 			&config_set->entries[i];
 
-		if (config->rate <= max_rate) {
-			assert_config_is_supported(expected_table, config);
-			*target = *config;
+		assert_config_is_supported(expected_table, config);
+		*target = *config;
 
-			return true;
-		}
+		return true;
 	}
 
 	return false;
 }
 
 static void test_fallback_seq(struct kunit *test,
-			      enum intel_output_type output_type,
-			      bool uhbr)
+			      enum intel_output_type output_type)
 {
 	struct test_ctx *ctx = test->priv;
 	struct intel_dp_link_caps *link_caps = ctx->dev.dig_port.dp.link.caps;
@@ -1273,12 +1268,6 @@ static void test_fallback_seq(struct kunit *test,
 	struct intel_dp_link_config target_config;
 	int fallback_count = 0;
 	bool target_found;
-	int max_rate;
-
-	if (uhbr)
-		max_rate = expected_table.rates.entries[expected_table.rates.size - 1];
-	else
-		max_rate = 810000;
 
 	dig_port->base.type = output_type;
 	ctx->dev.dig_port.dp.use_max_params = false;
@@ -1287,7 +1276,7 @@ static void test_fallback_seq(struct kunit *test,
 
 	/* Get the initial target config. */
 	target_found = get_target_config(&expected_table, output_type,
-					 max_rate, &target_config);
+					 &target_config);
 	KUNIT_ASSERT_TRUE(test, target_found);
 
 	for (;;) {
@@ -1296,16 +1285,10 @@ static void test_fallback_seq(struct kunit *test,
 					 &target_config, &fallback_config))
 			fallback_config = INTEL_DP_LINK_CONFIG_NULL;
 
-		if (!test_fallback_from_target(&expected_table, output_type, max_rate,
+		if (!test_fallback_from_target(&expected_table, output_type,
 					       &target_config, &fallback_config))
 			break;
 
-		/*
-		 * The fallback changed the max rate allowed for the next
-		 * target.
-		 */
-		max_rate = fallback_config.rate;
-
 		/* Simply select the fallback config as the next target. */
 		target_config = fallback_config;
 
@@ -1314,14 +1297,9 @@ static void test_fallback_seq(struct kunit *test,
 	}
 }
 
-static void intel_dp_link_test_fallback_for_sst_max_non_uhbr(struct kunit *test)
+static void intel_dp_link_test_fallback_for_sst(struct kunit *test)
 {
-	test_fallback_seq(test, INTEL_OUTPUT_DP, false);
-}
-
-static void intel_dp_link_test_fallback_for_sst_max_uhbr(struct kunit *test)
-{
-	test_fallback_seq(test, INTEL_OUTPUT_DP, true);
+	test_fallback_seq(test, INTEL_OUTPUT_DP);
 }
 
 static void intel_dp_link_test_fallback_for_mst(struct kunit *test)
@@ -1330,7 +1308,7 @@ static void intel_dp_link_test_fallback_for_mst(struct kunit *test)
 
 	ctx->dev.connector.mst.dp = &ctx->dev.dig_port.dp;
 
-	test_fallback_seq(test, INTEL_OUTPUT_DP_MST, true);
+	test_fallback_seq(test, INTEL_OUTPUT_DP_MST);
 }
 
 static struct kunit_case intel_dp_link_test_cases[] = {
@@ -1352,8 +1330,7 @@ static struct kunit_case intel_dp_link_test_cases[] = {
 	KUNIT_CASE(intel_dp_link_caps_test_update_params_expand_disable_random),
 
 	KUNIT_CASE(intel_dp_link_test_fallback_for_edp),
-	KUNIT_CASE(intel_dp_link_test_fallback_for_sst_max_non_uhbr),
-	KUNIT_CASE(intel_dp_link_test_fallback_for_sst_max_uhbr),
+	KUNIT_CASE(intel_dp_link_test_fallback_for_sst),
 	KUNIT_CASE(intel_dp_link_test_fallback_for_mst),
 
 	{}
-- 
2.49.1

RE: [PATCH 4/6] drm/i915/dp: Remove UHBR dependency from SST fallback kunit test

[Kandpal, Suraj]

> Subject: [PATCH 4/6] drm/i915/dp: Remove UHBR dependency from SST fallback
> kunit test
> 
> After fallback between UHBR and non-UHBR link rates got enabled in a previous
> change, there is no need to test fallback sequences for UHBR and non-UHBR
> rates separately. Make the test simply start from the maximum (UHBR) rate.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  .../i915/display/tests/intel_dp_link_test.c   | 47 +++++--------------
>  1 file changed, 12 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
> b/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
> index 776d93f333851..67c6fe9f1812a 100644
> --- a/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
> +++ b/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
> @@ -1101,7 +1101,7 @@ static void intel_dp_link_test_fallback_for_edp(struct
> kunit *test)  }
> 
>  static bool test_fallback_from_target(struct test_config_table *expected_table,
> -				      enum intel_output_type output_type, int
> max_rate,
> +				      enum intel_output_type output_type,
>  				      const struct intel_dp_link_config
> *expected_target_config,
>  				      const struct intel_dp_link_config
> *expected_fallback_config)  { @@ -1123,8 +1123,7 @@ static bool
> test_fallback_from_target(struct test_config_table *expected_table,
>  	/* Get the max connector config, optionally filtered to the max_rate
> limit. */
>  	lc_ops->iter_start(&iter, link_caps, fallback_order,
> INTEL_DP_LINK_CAPS_FILTER_ALL);
>  	for_each_dp_link_config(&iter, &iter_config)
> -		if (max_rate == 0 || iter_config.rate <= max_rate)
> -			break;
> +		break;
>  	lc_ops->iter_end(&iter);
> 
>  	KUNIT_EXPECT_TRUE(test, link_configs_match(&iter_config, @@ -
> 1236,7 +1235,6 @@ static bool get_fallback_config(const struct
> test_config_table *expected_table,
> 
>  static bool get_target_config(const struct test_config_table *expected_table,
>  			      enum intel_output_type output_type,
> -			      int max_rate,
>  			      struct intel_dp_link_config *target)  {
>  	struct kunit *test = expected_table->test; @@ -1248,20 +1246,17 @@
> static bool get_target_config(const struct test_config_table *expected_table,
>  		const struct intel_dp_link_config *config =
>  			&config_set->entries[i];
> 
> -		if (config->rate <= max_rate) {
> -			assert_config_is_supported(expected_table, config);
> -			*target = *config;
> +		assert_config_is_supported(expected_table, config);
> +		*target = *config;
> 
> -			return true;
> -		}
> +		return true;
>  	}
> 
>  	return false;
>  }
> 
>  static void test_fallback_seq(struct kunit *test,
> -			      enum intel_output_type output_type,
> -			      bool uhbr)
> +			      enum intel_output_type output_type)
>  {
>  	struct test_ctx *ctx = test->priv;
>  	struct intel_dp_link_caps *link_caps = ctx->dev.dig_port.dp.link.caps;
> @@ -1273,12 +1268,6 @@ static void test_fallback_seq(struct kunit *test,
>  	struct intel_dp_link_config target_config;
>  	int fallback_count = 0;
>  	bool target_found;
> -	int max_rate;
> -
> -	if (uhbr)
> -		max_rate =
> expected_table.rates.entries[expected_table.rates.size - 1];
> -	else
> -		max_rate = 810000;
> 
>  	dig_port->base.type = output_type;
>  	ctx->dev.dig_port.dp.use_max_params = false; @@ -1287,7 +1276,7
> @@ static void test_fallback_seq(struct kunit *test,
> 
>  	/* Get the initial target config. */
>  	target_found = get_target_config(&expected_table, output_type,
> -					 max_rate, &target_config);
> +					 &target_config);
>  	KUNIT_ASSERT_TRUE(test, target_found);
> 
>  	for (;;) {
> @@ -1296,16 +1285,10 @@ static void test_fallback_seq(struct kunit *test,
>  					 &target_config, &fallback_config))
>  			fallback_config = INTEL_DP_LINK_CONFIG_NULL;
> 
> -		if (!test_fallback_from_target(&expected_table, output_type,
> max_rate,
> +		if (!test_fallback_from_target(&expected_table, output_type,
>  					       &target_config, &fallback_config))
>  			break;
> 
> -		/*
> -		 * The fallback changed the max rate allowed for the next
> -		 * target.
> -		 */
> -		max_rate = fallback_config.rate;
> -
>  		/* Simply select the fallback config as the next target. */
>  		target_config = fallback_config;
> 
> @@ -1314,14 +1297,9 @@ static void test_fallback_seq(struct kunit *test,
>  	}
>  }
> 
> -static void intel_dp_link_test_fallback_for_sst_max_non_uhbr(struct kunit
> *test)
> +static void intel_dp_link_test_fallback_for_sst(struct kunit *test)
>  {
> -	test_fallback_seq(test, INTEL_OUTPUT_DP, false);
> -}
> -
> -static void intel_dp_link_test_fallback_for_sst_max_uhbr(struct kunit *test) -{
> -	test_fallback_seq(test, INTEL_OUTPUT_DP, true);
> +	test_fallback_seq(test, INTEL_OUTPUT_DP);
>  }
> 
>  static void intel_dp_link_test_fallback_for_mst(struct kunit *test) @@ -1330,7
> +1308,7 @@ static void intel_dp_link_test_fallback_for_mst(struct kunit *test)
> 
>  	ctx->dev.connector.mst.dp = &ctx->dev.dig_port.dp;
> 
> -	test_fallback_seq(test, INTEL_OUTPUT_DP_MST, true);
> +	test_fallback_seq(test, INTEL_OUTPUT_DP_MST);
>  }
> 
>  static struct kunit_case intel_dp_link_test_cases[] = { @@ -1352,8 +1330,7
> @@ static struct kunit_case intel_dp_link_test_cases[] = {
> 
> 	KUNIT_CASE(intel_dp_link_caps_test_update_params_expand_disable_
> random),
> 
>  	KUNIT_CASE(intel_dp_link_test_fallback_for_edp),
> -	KUNIT_CASE(intel_dp_link_test_fallback_for_sst_max_non_uhbr),
> -	KUNIT_CASE(intel_dp_link_test_fallback_for_sst_max_uhbr),
> +	KUNIT_CASE(intel_dp_link_test_fallback_for_sst),
>  	KUNIT_CASE(intel_dp_link_test_fallback_for_mst),
> 
>  	{}
> --
> 2.49.1

[PATCH 5/6] drm/i915/dp: Disable UHBR link configs with 1/2 lanes

[Imre Deak]

Disable 1 and 2 lane link configurations on UHBR tunneled links,
according to DP Standard v2.1b "3.5.2.16.3 128b/132b DPRX Lane Count
Conversion Failure Indication and Corrective Action". A tunnel can
indicate if it's not affected by this limitation, check for that and
skip disabling the unsupported lanes for a well-behaving tunnel.

The Standard in the same section also describes a workaround for 2 lanes
which requires assisstance from the sink, where the sink indicates at
the end of the link training sequence if the link training must be
retried. This mechanism also requires quirking out some sinks - based on
the sink's DPCD OUI and EDID identifications - which doesn't implement
this link training feedback indication properly. This patch leaves the
implementation of this workaround for a follow-up, but prepares for it
already by detecting the supported number of lane counts at a place
where both DPCD OUI and EDID is available for the quirk detection.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  7 +++
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |  5 +++
 .../gpu/drm/i915/display/intel_dp_tunnel.c    | 45 +++++++++++++++++++
 .../gpu/drm/i915/display/intel_dp_tunnel.h    | 17 +++++++
 5 files changed, 75 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c048da7d6fea7..adde53dc9dce3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1871,6 +1871,7 @@ struct intel_dp {
 
 	struct drm_dp_tunnel *tunnel;
 	bool tunnel_suspended:1;
+	u8 disabled_uhbr_lane_mask;
 
 	struct {
 		struct intel_dp_mst_encoder *stream_encoders[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0d2c696b9e4b0..e0b95fbf7db0a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3629,6 +3629,8 @@ void intel_dp_reset_link_params(struct intel_dp *intel_dp)
 	 * was called.
 	 */
 	intel_dp_link_caps_reset(intel_dp->link.caps);
+	intel_dp_tunnel_uhbr_lanes_wa_apply(intel_dp);
+
 	intel_dp->link.mst_probed_lane_count = 0;
 	intel_dp->link.mst_probed_rate = 0;
 	intel_dp_link_training_reset(intel_dp->link.training);
@@ -6281,6 +6283,8 @@ intel_dp_detect(struct drm_connector *_connector,
 
 		intel_dp_tunnel_disconnect(intel_dp);
 
+		intel_dp_tunnel_uhbr_lanes_wa_reset(intel_dp);
+
 		goto out_unset_edid;
 	}
 
@@ -6345,6 +6349,9 @@ intel_dp_detect(struct drm_connector *_connector,
 	if (intel_dp_is_edp(intel_dp) || connector->detect_edid)
 		status = connector_status_connected;
 
+	if (intel_dp_tunnel_uhbr_lanes_wa_setup(intel_dp))
+		intel_dp_tunnel_uhbr_lanes_wa_apply(intel_dp);
+
 out_unset_edid:
 	if (status != connector_status_connected && !intel_dp->is_mst)
 		intel_dp_unset_edid(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index df6e54508e5d4..7cbef16ab38b1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1453,6 +1453,11 @@ static int mst_connector_get_ddc_modes(struct drm_connector *_connector)
 
 	drm_edid_free(drm_edid);
 
+	if (intel_dp_tunnel_uhbr_lanes_wa_setup(intel_dp)) {
+		intel_dp_flush_connector_commits(connector);
+		intel_dp_tunnel_uhbr_lanes_wa_apply(intel_dp);
+	}
+
 	return ret;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
index 49fa4c9699b61..2199396345646 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
@@ -831,6 +831,51 @@ void intel_dp_tunnel_atomic_alloc_bw(struct intel_atomic_state *state)
 	atomic_increase_bw(state);
 }
 
+static u8 lane_count_mask(int lane_count)
+{
+	return BIT(ilog2(lane_count));
+}
+
+void intel_dp_tunnel_uhbr_lanes_wa_apply(struct intel_dp *intel_dp)
+{
+	struct intel_connector *connector = intel_dp->attached_connector;
+	struct intel_dp_link_caps_order order =
+		intel_dp_link_caps_connector_compute_order(connector);
+	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
+	struct intel_dp_link_config link_config;
+	struct intel_dp_link_caps_iter iter;
+
+	if (!intel_dp->disabled_uhbr_lane_mask)
+		return;
+
+	intel_dp_link_caps_iter_start(&iter, link_caps, order, INTEL_DP_LINK_CAPS_FILTER_ALL);
+	for_each_dp_link_config(&iter, &link_config) {
+		if (drm_dp_is_uhbr_rate(link_config.rate) &&
+		    lane_count_mask(link_config.lane_count) & intel_dp->disabled_uhbr_lane_mask)
+			intel_dp_link_caps_disable_config(link_caps, &link_config);
+	}
+	intel_dp_link_caps_iter_end(&iter);
+}
+
+bool intel_dp_tunnel_uhbr_lanes_wa_setup(struct intel_dp *intel_dp)
+{
+	u8 old_mask = intel_dp->disabled_uhbr_lane_mask;
+
+	if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp) ||
+	    drm_dp_tunnel_128b132b_lane0_mapping_supported(intel_dp->tunnel))
+		intel_dp->disabled_uhbr_lane_mask = 0;
+	else
+		/* TODO: Add support for keeping 2 lanes enabled as well. */
+		intel_dp->disabled_uhbr_lane_mask = lane_count_mask(1) | lane_count_mask(2);
+
+	return intel_dp->disabled_uhbr_lane_mask != old_mask;
+}
+
+void intel_dp_tunnel_uhbr_lanes_wa_reset(struct intel_dp *intel_dp)
+{
+	intel_dp->disabled_uhbr_lane_mask = 0;
+}
+
 /**
  * intel_dp_tunnel_mgr_init - Initialize the DP tunnel manager
  * @display: display device
diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.h b/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
index 8273e681a5128..13fc8fbb6e306 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
@@ -54,6 +54,10 @@ int intel_dp_tunnel_atomic_check_state(struct intel_atomic_state *state,
 
 void intel_dp_tunnel_atomic_alloc_bw(struct intel_atomic_state *state);
 
+void intel_dp_tunnel_uhbr_lanes_wa_apply(struct intel_dp *intel_dp);
+bool intel_dp_tunnel_uhbr_lanes_wa_setup(struct intel_dp *intel_dp);
+void intel_dp_tunnel_uhbr_lanes_wa_reset(struct intel_dp *intel_dp);
+
 int intel_dp_tunnel_mgr_init(struct intel_display *display);
 void intel_dp_tunnel_mgr_cleanup(struct intel_display *display);
 
@@ -129,6 +133,19 @@ intel_dp_tunnel_atomic_alloc_bw(struct intel_atomic_state *state)
 	return 0;
 }
 
+static inline void intel_dp_tunnel_uhbr_lanes_wa_apply(struct intel_dp *intel_dp)
+{
+}
+
+static inline bool intel_dp_tunnel_uhbr_lanes_wa_setup(struct intel_dp *intel_dp)
+{
+	return false;
+}
+
+static inline void intel_dp_tunnel_uhbr_lanes_wa_reset(struct intel_dp *intel_dp)
+{
+}
+
 static inline int
 intel_dp_tunnel_mgr_init(struct intel_display *display)
 {
-- 
2.49.1

RE: [PATCH 5/6] drm/i915/dp: Disable UHBR link configs with 1/2 lanes

[Kandpal, Suraj]

> Subject: [PATCH 5/6] drm/i915/dp: Disable UHBR link configs with 1/2 lanes
> 
> Disable 1 and 2 lane link configurations on UHBR tunneled links, according to
> DP Standard v2.1b "3.5.2.16.3 128b/132b DPRX Lane Count Conversion Failure
> Indication and Corrective Action". A tunnel can indicate if it's not affected by
> this limitation, check for that and skip disabling the unsupported lanes for a
> well-behaving tunnel.
> 
> The Standard in the same section also describes a workaround for 2 lanes which
> requires assisstance from the sink, where the sink indicates at the end of the
> link training sequence if the link training must be retried. This mechanism also
> requires quirking out some sinks - based on the sink's DPCD OUI and EDID
> identifications - which doesn't implement this link training feedback indication
> properly. This patch leaves the implementation of this workaround for a follow-
> up, but prepares for it already by detecting the supported number of lane
> counts at a place where both DPCD OUI and EDID is available for the quirk
> detection.
> 

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c       |  7 +++
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   |  5 +++
>  .../gpu/drm/i915/display/intel_dp_tunnel.c    | 45 +++++++++++++++++++
>  .../gpu/drm/i915/display/intel_dp_tunnel.h    | 17 +++++++
>  5 files changed, 75 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c048da7d6fea7..adde53dc9dce3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1871,6 +1871,7 @@ struct intel_dp {
> 
>  	struct drm_dp_tunnel *tunnel;
>  	bool tunnel_suspended:1;
> +	u8 disabled_uhbr_lane_mask;
> 
>  	struct {
>  		struct intel_dp_mst_encoder
> *stream_encoders[I915_MAX_PIPES]; diff --git
> a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0d2c696b9e4b0..e0b95fbf7db0a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3629,6 +3629,8 @@ void intel_dp_reset_link_params(struct intel_dp
> *intel_dp)
>  	 * was called.
>  	 */
>  	intel_dp_link_caps_reset(intel_dp->link.caps);
> +	intel_dp_tunnel_uhbr_lanes_wa_apply(intel_dp);
> +
>  	intel_dp->link.mst_probed_lane_count = 0;
>  	intel_dp->link.mst_probed_rate = 0;
>  	intel_dp_link_training_reset(intel_dp->link.training);
> @@ -6281,6 +6283,8 @@ intel_dp_detect(struct drm_connector *_connector,
> 
>  		intel_dp_tunnel_disconnect(intel_dp);
> 
> +		intel_dp_tunnel_uhbr_lanes_wa_reset(intel_dp);
> +
>  		goto out_unset_edid;
>  	}
> 
> @@ -6345,6 +6349,9 @@ intel_dp_detect(struct drm_connector *_connector,
>  	if (intel_dp_is_edp(intel_dp) || connector->detect_edid)
>  		status = connector_status_connected;
> 
> +	if (intel_dp_tunnel_uhbr_lanes_wa_setup(intel_dp))
> +		intel_dp_tunnel_uhbr_lanes_wa_apply(intel_dp);
> +
>  out_unset_edid:
>  	if (status != connector_status_connected && !intel_dp->is_mst)
>  		intel_dp_unset_edid(intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index df6e54508e5d4..7cbef16ab38b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -1453,6 +1453,11 @@ static int mst_connector_get_ddc_modes(struct
> drm_connector *_connector)
> 
>  	drm_edid_free(drm_edid);
> 
> +	if (intel_dp_tunnel_uhbr_lanes_wa_setup(intel_dp)) {
> +		intel_dp_flush_connector_commits(connector);
> +		intel_dp_tunnel_uhbr_lanes_wa_apply(intel_dp);
> +	}
> +
>  	return ret;
>  }
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> index 49fa4c9699b61..2199396345646 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> @@ -831,6 +831,51 @@ void intel_dp_tunnel_atomic_alloc_bw(struct
> intel_atomic_state *state)
>  	atomic_increase_bw(state);
>  }
> 
> +static u8 lane_count_mask(int lane_count) {
> +	return BIT(ilog2(lane_count));
> +}
> +
> +void intel_dp_tunnel_uhbr_lanes_wa_apply(struct intel_dp *intel_dp) {
> +	struct intel_connector *connector = intel_dp->attached_connector;
> +	struct intel_dp_link_caps_order order =
> +		intel_dp_link_caps_connector_compute_order(connector);
> +	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
> +	struct intel_dp_link_config link_config;
> +	struct intel_dp_link_caps_iter iter;
> +
> +	if (!intel_dp->disabled_uhbr_lane_mask)
> +		return;
> +
> +	intel_dp_link_caps_iter_start(&iter, link_caps, order,
> INTEL_DP_LINK_CAPS_FILTER_ALL);
> +	for_each_dp_link_config(&iter, &link_config) {
> +		if (drm_dp_is_uhbr_rate(link_config.rate) &&
> +		    lane_count_mask(link_config.lane_count) & intel_dp-
> >disabled_uhbr_lane_mask)
> +			intel_dp_link_caps_disable_config(link_caps,
> &link_config);
> +	}
> +	intel_dp_link_caps_iter_end(&iter);
> +}
> +
> +bool intel_dp_tunnel_uhbr_lanes_wa_setup(struct intel_dp *intel_dp) {
> +	u8 old_mask = intel_dp->disabled_uhbr_lane_mask;
> +
> +	if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp) ||
> +	    drm_dp_tunnel_128b132b_lane0_mapping_supported(intel_dp-
> >tunnel))
> +		intel_dp->disabled_uhbr_lane_mask = 0;
> +	else
> +		/* TODO: Add support for keeping 2 lanes enabled as well. */
> +		intel_dp->disabled_uhbr_lane_mask = lane_count_mask(1) |
> +lane_count_mask(2);
> +
> +	return intel_dp->disabled_uhbr_lane_mask != old_mask; }
> +
> +void intel_dp_tunnel_uhbr_lanes_wa_reset(struct intel_dp *intel_dp) {
> +	intel_dp->disabled_uhbr_lane_mask = 0; }
> +
>  /**
>   * intel_dp_tunnel_mgr_init - Initialize the DP tunnel manager
>   * @display: display device
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
> b/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
> index 8273e681a5128..13fc8fbb6e306 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
> @@ -54,6 +54,10 @@ int intel_dp_tunnel_atomic_check_state(struct
> intel_atomic_state *state,
> 
>  void intel_dp_tunnel_atomic_alloc_bw(struct intel_atomic_state *state);
> 
> +void intel_dp_tunnel_uhbr_lanes_wa_apply(struct intel_dp *intel_dp);
> +bool intel_dp_tunnel_uhbr_lanes_wa_setup(struct intel_dp *intel_dp);
> +void intel_dp_tunnel_uhbr_lanes_wa_reset(struct intel_dp *intel_dp);
> +
>  int intel_dp_tunnel_mgr_init(struct intel_display *display);  void
> intel_dp_tunnel_mgr_cleanup(struct intel_display *display);
> 
> @@ -129,6 +133,19 @@ intel_dp_tunnel_atomic_alloc_bw(struct
> intel_atomic_state *state)
>  	return 0;
>  }
> 
> +static inline void intel_dp_tunnel_uhbr_lanes_wa_apply(struct intel_dp
> +*intel_dp) { }
> +
> +static inline bool intel_dp_tunnel_uhbr_lanes_wa_setup(struct intel_dp
> +*intel_dp) {
> +	return false;
> +}
> +
> +static inline void intel_dp_tunnel_uhbr_lanes_wa_reset(struct intel_dp
> +*intel_dp) { }
> +
>  static inline int
>  intel_dp_tunnel_mgr_init(struct intel_display *display)  {
> --
> 2.49.1

[PATCH 6/6] drm/i915/dp_tunnel: Add UHBR tunneling support

[Imre Deak]

Add support for UHBR link rates on Thunderbolt tunneled links.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 37 +++++++++++++++++++++----
 1 file changed, 32 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e0b95fbf7db0a..eab22b161ea1a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -191,6 +191,29 @@ static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
 	intel_dp->num_sink_rates = 1;
 }
 
+static bool dprx_supports_128b132b(struct intel_dp *intel_dp)
+{
+	if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
+		return drm_dp_tunnel_128b132b_supported(intel_dp->tunnel);
+	else
+		return drm_dp_128b132b_supported(intel_dp->dpcd);
+}
+
+static u8 dprx_128b132b_link_rates(struct intel_dp *intel_dp, u8 no_bwa_rates)
+{
+	u8 ret;
+
+	if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
+		return no_bwa_rates;
+
+	ret = drm_dp_tunnel_128b132b_dprx_rates(intel_dp->tunnel);
+	static_assert(DP_TUNNELING_10GBPS_PER_LANE_SUPPORT == DP_UHBR10 &&
+		      DP_TUNNELING_13_5GBPS_PER_LANE_SUPPORT == DP_UHBR13_5 &&
+		      DP_TUNNELING_20GBPS_PER_LANE_SUPPORT == DP_UHBR20);
+
+	return ret;
+}
+
 /* update sink rates from dpcd */
 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
 {
@@ -199,6 +222,7 @@ static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
 	};
 	int i, max_rate;
 	int max_lttpr_rate;
+	u8 uhbr_rates = 0;
 
 	if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 		/* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
@@ -224,17 +248,20 @@ static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
 		intel_dp->sink_rates[i] = dp_rates[i];
 	}
 
+	/*
+	 * The following register must be read unconditionally for the later
+	 * DP tunnel 128b132b detection to work, see DP Standard v2.1 5.14.3 .
+	 */
+	drm_dp_dpcd_read_byte(&intel_dp->aux, DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
+
 	/*
 	 * Sink rates for 128b/132b. If set, sink should support all 8b/10b
 	 * rates and 10 Gbps.
 	 */
-	if (drm_dp_128b132b_supported(intel_dp->dpcd)) {
-		u8 uhbr_rates = 0;
-
+	if (dprx_supports_128b132b(intel_dp)) {
 		BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
 
-		drm_dp_dpcd_readb(&intel_dp->aux,
-				  DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
+		uhbr_rates = dprx_128b132b_link_rates(intel_dp, uhbr_rates);
 
 		if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
 			/* We have a repeater */
-- 
2.49.1

RE: [PATCH 6/6] drm/i915/dp_tunnel: Add UHBR tunneling support

[Kandpal, Suraj]

> Subject: [PATCH 6/6] drm/i915/dp_tunnel: Add UHBR tunneling support
> 
> Add support for UHBR link rates on Thunderbolt tunneled links.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 37 +++++++++++++++++++++----
>  1 file changed, 32 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index e0b95fbf7db0a..eab22b161ea1a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -191,6 +191,29 @@ static void intel_dp_set_default_sink_rates(struct
> intel_dp *intel_dp)
>  	intel_dp->num_sink_rates = 1;
>  }
> 
> +static bool dprx_supports_128b132b(struct intel_dp *intel_dp) {
> +	if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
> +		return drm_dp_tunnel_128b132b_supported(intel_dp->tunnel);
> +	else
> +		return drm_dp_128b132b_supported(intel_dp->dpcd);
> +}
> +
> +static u8 dprx_128b132b_link_rates(struct intel_dp *intel_dp, u8
> +no_bwa_rates) {
> +	u8 ret;
> +
> +	if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
> +		return no_bwa_rates;
> +
> +	ret = drm_dp_tunnel_128b132b_dprx_rates(intel_dp->tunnel);
> +	static_assert(DP_TUNNELING_10GBPS_PER_LANE_SUPPORT ==
> DP_UHBR10 &&
> +		      DP_TUNNELING_13_5GBPS_PER_LANE_SUPPORT ==
> DP_UHBR13_5 &&
> +		      DP_TUNNELING_20GBPS_PER_LANE_SUPPORT ==
> DP_UHBR20);
> +
> +	return ret;
> +}
> +
>  /* update sink rates from dpcd */
>  static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)  { @@ -
> 199,6 +222,7 @@ static void intel_dp_set_dpcd_sink_rates(struct intel_dp
> *intel_dp)
>  	};
>  	int i, max_rate;
>  	int max_lttpr_rate;
> +	u8 uhbr_rates = 0;
> 
>  	if (drm_dp_has_quirk(&intel_dp->desc,
> DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
>  		/* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel
> */ @@ -224,17 +248,20 @@ static void intel_dp_set_dpcd_sink_rates(struct
> intel_dp *intel_dp)
>  		intel_dp->sink_rates[i] = dp_rates[i];
>  	}
> 
> +	/*
> +	 * The following register must be read unconditionally for the later
> +	 * DP tunnel 128b132b detection to work, see DP Standard v2.1 5.14.3 .
> +	 */
> +	drm_dp_dpcd_read_byte(&intel_dp->aux,
> +DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
> +
>  	/*
>  	 * Sink rates for 128b/132b. If set, sink should support all 8b/10b
>  	 * rates and 10 Gbps.
>  	 */
> -	if (drm_dp_128b132b_supported(intel_dp->dpcd)) {
> -		u8 uhbr_rates = 0;
> -
> +	if (dprx_supports_128b132b(intel_dp)) {
>  		BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) <
> ARRAY_SIZE(dp_rates) + 3);
> 
> -		drm_dp_dpcd_readb(&intel_dp->aux,
> -				  DP_128B132B_SUPPORTED_LINK_RATES,
> &uhbr_rates);
> +		uhbr_rates = dprx_128b132b_link_rates(intel_dp, uhbr_rates);
> 
>  		if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
>  			/* We have a repeater */
> --
> 2.49.1

✗ CI.checkpatch: warning for drm/i915/dp: Enable UHBR link rates on tunneled links

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Enable UHBR link rates on tunneled links
URL   : https://patchwork.freedesktop.org/series/170424/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
061140b9bc586ae7f40abc1249c97e1cc72d1b9d
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 351a14a3af91735a75f41fd899224725417d0d66
Author: Imre Deak <imre.deak@intel.com>
Date:   Tue Jul 14 18:27:00 2026 +0300

    drm/i915/dp_tunnel: Add UHBR tunneling support
    
    Add support for UHBR link rates on Thunderbolt tunneled links.
    
    Signed-off-by: Imre Deak <imre.deak@intel.com>
+ /mt/dim checkpatch 5974bf0dae59523b3ae9f53e67a394e76b926a04 drm-intel
2012777e6cfd drm/dp_tunnel: Add UHBR tunneling support
1adbd5a21932 drm/i915/dp: End link configuration loops properly
8e3b5c066f52 drm/i915/dp: Enable SST fallback between UHBR and non-UHBR rates
8bf4e58688e0 drm/i915/dp: Remove UHBR dependency from SST fallback kunit test
7ef0ce299d8c drm/i915/dp: Disable UHBR link configs with 1/2 lanes
351a14a3af91 drm/i915/dp_tunnel: Add UHBR tunneling support
-:34: WARNING:CONSTANT_COMPARISON: Comparisons should place the constant on the right side of the test
#34: FILE: drivers/gpu/drm/i915/display/intel_dp.c:210:
+	static_assert(DP_TUNNELING_10GBPS_PER_LANE_SUPPORT == DP_UHBR10 &&

-:35: WARNING:CONSTANT_COMPARISON: Comparisons should place the constant on the right side of the test
#35: FILE: drivers/gpu/drm/i915/display/intel_dp.c:211:
+		      DP_TUNNELING_13_5GBPS_PER_LANE_SUPPORT == DP_UHBR13_5 &&

total: 0 errors, 2 warnings, 0 checks, 61 lines checked

✓ CI.KUnit: success for drm/i915/dp: Enable UHBR link rates on tunneled links

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Enable UHBR link rates on tunneled links
URL   : https://patchwork.freedesktop.org/series/170424/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[15:33:47] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:33:51] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:34:23] Starting KUnit Kernel (1/1)...
[15:34:23] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:34:23] ================== guc_buf (11 subtests) ===================
[15:34:23] [PASSED] test_smallest
[15:34:23] [PASSED] test_largest
[15:34:23] [PASSED] test_granular
[15:34:23] [PASSED] test_unique
[15:34:23] [PASSED] test_overlap
[15:34:23] [PASSED] test_reusable
[15:34:23] [PASSED] test_too_big
[15:34:23] [PASSED] test_flush
[15:34:23] [PASSED] test_lookup
[15:34:23] [PASSED] test_data
[15:34:23] [PASSED] test_class
[15:34:23] ===================== [PASSED] guc_buf =====================
[15:34:23] =================== guc_dbm (7 subtests) ===================
[15:34:23] [PASSED] test_empty
[15:34:23] [PASSED] test_default
[15:34:23] ======================== test_size  ========================
[15:34:23] [PASSED] 4
[15:34:23] [PASSED] 8
[15:34:23] [PASSED] 32
[15:34:23] [PASSED] 256
[15:34:23] ==================== [PASSED] test_size ====================
[15:34:23] ======================= test_reuse  ========================
[15:34:23] [PASSED] 4
[15:34:23] [PASSED] 8
[15:34:23] [PASSED] 32
[15:34:23] [PASSED] 256
[15:34:23] =================== [PASSED] test_reuse ====================
[15:34:23] =================== test_range_overlap  ====================
[15:34:23] [PASSED] 4
[15:34:23] [PASSED] 8
[15:34:23] [PASSED] 32
[15:34:23] [PASSED] 256
[15:34:23] =============== [PASSED] test_range_overlap ================
[15:34:23] =================== test_range_compact  ====================
[15:34:23] [PASSED] 4
[15:34:23] [PASSED] 8
[15:34:23] [PASSED] 32
[15:34:23] [PASSED] 256
[15:34:23] =============== [PASSED] test_range_compact ================
[15:34:23] ==================== test_range_spare  =====================
[15:34:23] [PASSED] 4
[15:34:23] [PASSED] 8
[15:34:23] [PASSED] 32
[15:34:23] [PASSED] 256
[15:34:23] ================ [PASSED] test_range_spare =================
[15:34:23] ===================== [PASSED] guc_dbm =====================
[15:34:23] =================== guc_idm (6 subtests) ===================
[15:34:23] [PASSED] bad_init
[15:34:23] [PASSED] no_init
[15:34:23] [PASSED] init_fini
[15:34:23] [PASSED] check_used
[15:34:23] [PASSED] check_quota
[15:34:23] [PASSED] check_all
[15:34:23] ===================== [PASSED] guc_idm =====================
[15:34:23] =============== guc_klv_helpers (9 subtests) ===============
[15:34:23] [PASSED] test_count
[15:34:23] [PASSED] test_encode_u32
[15:34:23] [PASSED] test_encode_u64
[15:34:23] [PASSED] test_encode_string
[15:34:23] [PASSED] test_encode_object_raw
[15:34:23] [PASSED] test_encode_object_klv
[15:34:23] [PASSED] test_encode_object_nested
[15:34:23] [PASSED] test_encode_object_basic
[15:34:23] [PASSED] test_print
[15:34:23] ================= [PASSED] guc_klv_helpers =================
[15:34:23] ================== no_relay (3 subtests) ===================
[15:34:23] [PASSED] xe_drops_guc2pf_if_not_ready
[15:34:23] [PASSED] xe_drops_guc2vf_if_not_ready
[15:34:23] [PASSED] xe_rejects_send_if_not_ready
[15:34:23] ==================== [PASSED] no_relay =====================
[15:34:23] ================== pf_relay (14 subtests) ==================
[15:34:23] [PASSED] pf_rejects_guc2pf_too_short
[15:34:23] [PASSED] pf_rejects_guc2pf_too_long
[15:34:23] [PASSED] pf_rejects_guc2pf_no_payload
[15:34:23] [PASSED] pf_fails_no_payload
[15:34:23] [PASSED] pf_fails_bad_origin
[15:34:23] [PASSED] pf_fails_bad_type
[15:34:23] [PASSED] pf_txn_reports_error
[15:34:23] [PASSED] pf_txn_sends_pf2guc
[15:34:23] [PASSED] pf_sends_pf2guc
[15:34:23] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[15:34:23] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[15:34:23] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[15:34:23] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[15:34:23] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[15:34:23] ==================== [PASSED] pf_relay =====================
[15:34:23] ================== vf_relay (3 subtests) ===================
[15:34:23] [PASSED] vf_rejects_guc2vf_too_short
[15:34:23] [PASSED] vf_rejects_guc2vf_too_long
[15:34:23] [PASSED] vf_rejects_guc2vf_no_payload
[15:34:23] ==================== [PASSED] vf_relay =====================
[15:34:23] ================ pf_gt_config (9 subtests) =================
[15:34:23] [PASSED] fair_contexts_1vf
[15:34:23] [PASSED] fair_doorbells_1vf
[15:34:23] [PASSED] fair_ggtt_1vf
[15:34:23] ====================== fair_vram_1vf  ======================
[15:34:23] [PASSED] 3.50 GiB
[15:34:23] [PASSED] 11.5 GiB
[15:34:23] [PASSED] 15.5 GiB
[15:34:23] [PASSED] 31.5 GiB
[15:34:23] [PASSED] 63.5 GiB
[15:34:23] [PASSED] 1.91 GiB
[15:34:23] ================== [PASSED] fair_vram_1vf ==================
[15:34:23] ================ fair_vram_1vf_admin_only  =================
[15:34:23] [PASSED] 3.50 GiB
[15:34:23] [PASSED] 11.5 GiB
[15:34:23] [PASSED] 15.5 GiB
[15:34:23] [PASSED] 31.5 GiB
[15:34:23] [PASSED] 63.5 GiB
[15:34:23] [PASSED] 1.91 GiB
[15:34:23] ============ [PASSED] fair_vram_1vf_admin_only =============
[15:34:23] ====================== fair_contexts  ======================
[15:34:23] [PASSED] 1 VF
[15:34:23] [PASSED] 2 VFs
[15:34:23] [PASSED] 3 VFs
[15:34:23] [PASSED] 4 VFs
[15:34:23] [PASSED] 5 VFs
[15:34:23] [PASSED] 6 VFs
[15:34:23] [PASSED] 7 VFs
[15:34:23] [PASSED] 8 VFs
[15:34:23] [PASSED] 9 VFs
[15:34:23] [PASSED] 10 VFs
[15:34:23] [PASSED] 11 VFs
[15:34:23] [PASSED] 12 VFs
[15:34:23] [PASSED] 13 VFs
[15:34:23] [PASSED] 14 VFs
[15:34:23] [PASSED] 15 VFs
[15:34:23] [PASSED] 16 VFs
[15:34:23] [PASSED] 17 VFs
[15:34:23] [PASSED] 18 VFs
[15:34:23] [PASSED] 19 VFs
[15:34:23] [PASSED] 20 VFs
[15:34:23] [PASSED] 21 VFs
[15:34:23] [PASSED] 22 VFs
[15:34:23] [PASSED] 23 VFs
[15:34:23] [PASSED] 24 VFs
[15:34:23] [PASSED] 25 VFs
[15:34:23] [PASSED] 26 VFs
[15:34:23] [PASSED] 27 VFs
[15:34:23] [PASSED] 28 VFs
[15:34:23] [PASSED] 29 VFs
[15:34:23] [PASSED] 30 VFs
[15:34:23] [PASSED] 31 VFs
[15:34:23] [PASSED] 32 VFs
[15:34:23] [PASSED] 33 VFs
[15:34:23] [PASSED] 34 VFs
[15:34:23] [PASSED] 35 VFs
[15:34:23] [PASSED] 36 VFs
[15:34:23] [PASSED] 37 VFs
[15:34:23] [PASSED] 38 VFs
[15:34:23] [PASSED] 39 VFs
[15:34:23] [PASSED] 40 VFs
[15:34:23] [PASSED] 41 VFs
[15:34:23] [PASSED] 42 VFs
[15:34:23] [PASSED] 43 VFs
[15:34:23] [PASSED] 44 VFs
[15:34:23] [PASSED] 45 VFs
[15:34:23] [PASSED] 46 VFs
[15:34:23] [PASSED] 47 VFs
[15:34:23] [PASSED] 48 VFs
[15:34:23] [PASSED] 49 VFs
[15:34:23] [PASSED] 50 VFs
[15:34:23] [PASSED] 51 VFs
[15:34:23] [PASSED] 52 VFs
[15:34:23] [PASSED] 53 VFs
[15:34:23] [PASSED] 54 VFs
[15:34:23] [PASSED] 55 VFs
[15:34:23] [PASSED] 56 VFs
[15:34:23] [PASSED] 57 VFs
[15:34:23] [PASSED] 58 VFs
[15:34:23] [PASSED] 59 VFs
[15:34:23] [PASSED] 60 VFs
[15:34:23] [PASSED] 61 VFs
[15:34:23] [PASSED] 62 VFs
[15:34:23] [PASSED] 63 VFs
[15:34:23] ================== [PASSED] fair_contexts ==================
[15:34:23] ===================== fair_doorbells  ======================
[15:34:23] [PASSED] 1 VF
[15:34:23] [PASSED] 2 VFs
[15:34:23] [PASSED] 3 VFs
[15:34:23] [PASSED] 4 VFs
[15:34:23] [PASSED] 5 VFs
[15:34:23] [PASSED] 6 VFs
[15:34:23] [PASSED] 7 VFs
[15:34:23] [PASSED] 8 VFs
[15:34:23] [PASSED] 9 VFs
[15:34:23] [PASSED] 10 VFs
[15:34:23] [PASSED] 11 VFs
[15:34:23] [PASSED] 12 VFs
[15:34:23] [PASSED] 13 VFs
[15:34:23] [PASSED] 14 VFs
[15:34:23] [PASSED] 15 VFs
[15:34:23] [PASSED] 16 VFs
[15:34:23] [PASSED] 17 VFs
[15:34:23] [PASSED] 18 VFs
[15:34:23] [PASSED] 19 VFs
[15:34:23] [PASSED] 20 VFs
[15:34:23] [PASSED] 21 VFs
[15:34:23] [PASSED] 22 VFs
[15:34:23] [PASSED] 23 VFs
[15:34:23] [PASSED] 24 VFs
[15:34:23] [PASSED] 25 VFs
[15:34:23] [PASSED] 26 VFs
[15:34:23] [PASSED] 27 VFs
[15:34:23] [PASSED] 28 VFs
[15:34:23] [PASSED] 29 VFs
[15:34:23] [PASSED] 30 VFs
[15:34:23] [PASSED] 31 VFs
[15:34:23] [PASSED] 32 VFs
[15:34:23] [PASSED] 33 VFs
[15:34:23] [PASSED] 34 VFs
[15:34:23] [PASSED] 35 VFs
[15:34:23] [PASSED] 36 VFs
[15:34:23] [PASSED] 37 VFs
[15:34:23] [PASSED] 38 VFs
[15:34:23] [PASSED] 39 VFs
[15:34:23] [PASSED] 40 VFs
[15:34:23] [PASSED] 41 VFs
[15:34:23] [PASSED] 42 VFs
[15:34:23] [PASSED] 43 VFs
[15:34:23] [PASSED] 44 VFs
[15:34:23] [PASSED] 45 VFs
[15:34:23] [PASSED] 46 VFs
[15:34:23] [PASSED] 47 VFs
[15:34:23] [PASSED] 48 VFs
[15:34:23] [PASSED] 49 VFs
[15:34:23] [PASSED] 50 VFs
[15:34:23] [PASSED] 51 VFs
[15:34:23] [PASSED] 52 VFs
[15:34:23] [PASSED] 53 VFs
[15:34:23] [PASSED] 54 VFs
[15:34:23] [PASSED] 55 VFs
[15:34:23] [PASSED] 56 VFs
[15:34:23] [PASSED] 57 VFs
[15:34:23] [PASSED] 58 VFs
[15:34:23] [PASSED] 59 VFs
[15:34:23] [PASSED] 60 VFs
[15:34:23] [PASSED] 61 VFs
[15:34:23] [PASSED] 62 VFs
[15:34:23] [PASSED] 63 VFs
[15:34:23] ================= [PASSED] fair_doorbells ==================
[15:34:23] ======================== fair_ggtt  ========================
[15:34:23] [PASSED] 1 VF
[15:34:23] [PASSED] 2 VFs
[15:34:23] [PASSED] 3 VFs
[15:34:23] [PASSED] 4 VFs
[15:34:23] [PASSED] 5 VFs
[15:34:23] [PASSED] 6 VFs
[15:34:23] [PASSED] 7 VFs
[15:34:23] [PASSED] 8 VFs
[15:34:23] [PASSED] 9 VFs
[15:34:23] [PASSED] 10 VFs
[15:34:23] [PASSED] 11 VFs
[15:34:23] [PASSED] 12 VFs
[15:34:23] [PASSED] 13 VFs
[15:34:23] [PASSED] 14 VFs
[15:34:23] [PASSED] 15 VFs
[15:34:23] [PASSED] 16 VFs
[15:34:23] [PASSED] 17 VFs
[15:34:23] [PASSED] 18 VFs
[15:34:23] [PASSED] 19 VFs
[15:34:23] [PASSED] 20 VFs
[15:34:23] [PASSED] 21 VFs
[15:34:23] [PASSED] 22 VFs
[15:34:23] [PASSED] 23 VFs
[15:34:23] [PASSED] 24 VFs
[15:34:23] [PASSED] 25 VFs
[15:34:23] [PASSED] 26 VFs
[15:34:23] [PASSED] 27 VFs
[15:34:23] [PASSED] 28 VFs
[15:34:23] [PASSED] 29 VFs
[15:34:23] [PASSED] 30 VFs
[15:34:23] [PASSED] 31 VFs
[15:34:23] [PASSED] 32 VFs
[15:34:23] [PASSED] 33 VFs
[15:34:23] [PASSED] 34 VFs
[15:34:23] [PASSED] 35 VFs
[15:34:23] [PASSED] 36 VFs
[15:34:23] [PASSED] 37 VFs
[15:34:23] [PASSED] 38 VFs
[15:34:23] [PASSED] 39 VFs
[15:34:23] [PASSED] 40 VFs
[15:34:23] [PASSED] 41 VFs
[15:34:23] [PASSED] 42 VFs
[15:34:23] [PASSED] 43 VFs
[15:34:23] [PASSED] 44 VFs
[15:34:23] [PASSED] 45 VFs
[15:34:23] [PASSED] 46 VFs
[15:34:23] [PASSED] 47 VFs
[15:34:23] [PASSED] 48 VFs
[15:34:23] [PASSED] 49 VFs
[15:34:23] [PASSED] 50 VFs
[15:34:23] [PASSED] 51 VFs
[15:34:23] [PASSED] 52 VFs
[15:34:23] [PASSED] 53 VFs
[15:34:23] [PASSED] 54 VFs
[15:34:23] [PASSED] 55 VFs
[15:34:23] [PASSED] 56 VFs
[15:34:23] [PASSED] 57 VFs
[15:34:23] [PASSED] 58 VFs
[15:34:23] [PASSED] 59 VFs
[15:34:23] [PASSED] 60 VFs
[15:34:23] [PASSED] 61 VFs
[15:34:23] [PASSED] 62 VFs
[15:34:23] [PASSED] 63 VFs
[15:34:23] ==================== [PASSED] fair_ggtt ====================
[15:34:23] ======================== fair_vram  ========================
[15:34:23] [PASSED] 1 VF
[15:34:23] [PASSED] 2 VFs
[15:34:23] [PASSED] 3 VFs
[15:34:23] [PASSED] 4 VFs
[15:34:23] [PASSED] 5 VFs
[15:34:23] [PASSED] 6 VFs
[15:34:23] [PASSED] 7 VFs
[15:34:23] [PASSED] 8 VFs
[15:34:23] [PASSED] 9 VFs
[15:34:23] [PASSED] 10 VFs
[15:34:23] [PASSED] 11 VFs
[15:34:23] [PASSED] 12 VFs
[15:34:23] [PASSED] 13 VFs
[15:34:24] [PASSED] 14 VFs
[15:34:24] [PASSED] 15 VFs
[15:34:24] [PASSED] 16 VFs
[15:34:24] [PASSED] 17 VFs
[15:34:24] [PASSED] 18 VFs
[15:34:24] [PASSED] 19 VFs
[15:34:24] [PASSED] 20 VFs
[15:34:24] [PASSED] 21 VFs
[15:34:24] [PASSED] 22 VFs
[15:34:24] [PASSED] 23 VFs
[15:34:24] [PASSED] 24 VFs
[15:34:24] [PASSED] 25 VFs
[15:34:24] [PASSED] 26 VFs
[15:34:24] [PASSED] 27 VFs
[15:34:24] [PASSED] 28 VFs
[15:34:24] [PASSED] 29 VFs
[15:34:24] [PASSED] 30 VFs
[15:34:24] [PASSED] 31 VFs
[15:34:24] [PASSED] 32 VFs
[15:34:24] [PASSED] 33 VFs
[15:34:24] [PASSED] 34 VFs
[15:34:24] [PASSED] 35 VFs
[15:34:24] [PASSED] 36 VFs
[15:34:24] [PASSED] 37 VFs
[15:34:24] [PASSED] 38 VFs
[15:34:24] [PASSED] 39 VFs
[15:34:24] [PASSED] 40 VFs
[15:34:24] [PASSED] 41 VFs
[15:34:24] [PASSED] 42 VFs
[15:34:24] [PASSED] 43 VFs
[15:34:24] [PASSED] 44 VFs
[15:34:24] [PASSED] 45 VFs
[15:34:24] [PASSED] 46 VFs
[15:34:24] [PASSED] 47 VFs
[15:34:24] [PASSED] 48 VFs
[15:34:24] [PASSED] 49 VFs
[15:34:24] [PASSED] 50 VFs
[15:34:24] [PASSED] 51 VFs
[15:34:24] [PASSED] 52 VFs
[15:34:24] [PASSED] 53 VFs
[15:34:24] [PASSED] 54 VFs
[15:34:24] [PASSED] 55 VFs
[15:34:24] [PASSED] 56 VFs
[15:34:24] [PASSED] 57 VFs
[15:34:24] [PASSED] 58 VFs
[15:34:24] [PASSED] 59 VFs
[15:34:24] [PASSED] 60 VFs
[15:34:24] [PASSED] 61 VFs
[15:34:24] [PASSED] 62 VFs
[15:34:24] [PASSED] 63 VFs
[15:34:24] ==================== [PASSED] fair_vram ====================
[15:34:24] ================== [PASSED] pf_gt_config ===================
[15:34:24] ===================== lmtt (1 subtest) =====================
[15:34:24] ======================== test_ops  =========================
[15:34:24] [PASSED] 2-level
[15:34:24] [PASSED] multi-level
[15:34:24] ==================== [PASSED] test_ops =====================
[15:34:24] ====================== [PASSED] lmtt =======================
[15:34:24] ================= sriov_packet (1 subtest) =================
[15:34:24] [PASSED] test_descriptor_init
[15:34:24] ================== [PASSED] sriov_packet ===================
[15:34:24] ================= pf_service (11 subtests) =================
[15:34:24] [PASSED] pf_negotiate_any
[15:34:24] [PASSED] pf_negotiate_base_match
[15:34:24] [PASSED] pf_negotiate_base_newer
[15:34:24] [PASSED] pf_negotiate_base_next
[15:34:24] [SKIPPED] pf_negotiate_base_older (no older minor)
[15:34:24] [PASSED] pf_negotiate_base_prev
[15:34:24] [PASSED] pf_negotiate_latest_match
[15:34:24] [PASSED] pf_negotiate_latest_newer
[15:34:24] [PASSED] pf_negotiate_latest_next
[15:34:24] [SKIPPED] pf_negotiate_latest_older (no older minor)
[15:34:24] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[15:34:24] =================== [PASSED] pf_service ====================
[15:34:24] ================= xe_guc_g2g (2 subtests) ==================
[15:34:24] ============== xe_live_guc_g2g_kunit_default  ==============
[15:34:24] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[15:34:24] ============== xe_live_guc_g2g_kunit_allmem  ===============
[15:34:24] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[15:34:24] =================== [SKIPPED] xe_guc_g2g ===================
[15:34:24] =================== xe_mocs (2 subtests) ===================
[15:34:24] ================ xe_live_mocs_kernel_kunit  ================
[15:34:24] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[15:34:24] ================ xe_live_mocs_reset_kunit  =================
[15:34:24] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[15:34:24] ==================== [SKIPPED] xe_mocs =====================
[15:34:24] ================= xe_migrate (2 subtests) ==================
[15:34:24] ================= xe_migrate_sanity_kunit  =================
[15:34:24] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[15:34:24] ================== xe_validate_ccs_kunit  ==================
[15:34:24] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[15:34:24] =================== [SKIPPED] xe_migrate ===================
[15:34:24] ================== xe_dma_buf (1 subtest) ==================
[15:34:24] ==================== xe_dma_buf_kunit  =====================
[15:34:24] ================ [SKIPPED] xe_dma_buf_kunit ================
[15:34:24] =================== [SKIPPED] xe_dma_buf ===================
[15:34:24] ================= xe_bo_shrink (1 subtest) =================
[15:34:24] =================== xe_bo_shrink_kunit  ====================
[15:34:24] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[15:34:24] ================== [SKIPPED] xe_bo_shrink ==================
[15:34:24] ==================== xe_bo (2 subtests) ====================
[15:34:24] ================== xe_ccs_migrate_kunit  ===================
[15:34:24] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[15:34:24] ==================== xe_bo_evict_kunit  ====================
[15:34:24] =============== [SKIPPED] xe_bo_evict_kunit ================
[15:34:24] ===================== [SKIPPED] xe_bo ======================
[15:34:24] ==================== args (13 subtests) ====================
[15:34:24] [PASSED] count_args_test
[15:34:24] [PASSED] call_args_example
[15:34:24] [PASSED] call_args_test
[15:34:24] [PASSED] drop_first_arg_example
[15:34:24] [PASSED] drop_first_arg_test
[15:34:24] [PASSED] first_arg_example
[15:34:24] [PASSED] first_arg_test
[15:34:24] [PASSED] last_arg_example
[15:34:24] [PASSED] last_arg_test
[15:34:24] [PASSED] pick_arg_example
[15:34:24] [PASSED] if_args_example
[15:34:24] [PASSED] if_args_test
[15:34:24] [PASSED] sep_comma_example
[15:34:24] ====================== [PASSED] args =======================
[15:34:24] =================== xe_pci (3 subtests) ====================
[15:34:24] ==================== check_graphics_ip  ====================
[15:34:24] [PASSED] 12.00 Xe_LP
[15:34:24] [PASSED] 12.10 Xe_LP+
[15:34:24] [PASSED] 12.55 Xe_HPG
[15:34:24] [PASSED] 12.60 Xe_HPC
[15:34:24] [PASSED] 12.70 Xe_LPG
[15:34:24] [PASSED] 12.71 Xe_LPG
[15:34:24] [PASSED] 12.74 Xe_LPG+
[15:34:24] [PASSED] 20.01 Xe2_HPG
[15:34:24] [PASSED] 20.02 Xe2_HPG
[15:34:24] [PASSED] 20.04 Xe2_LPG
[15:34:24] [PASSED] 30.00 Xe3_LPG
[15:34:24] [PASSED] 30.01 Xe3_LPG
[15:34:24] [PASSED] 30.03 Xe3_LPG
[15:34:24] [PASSED] 30.04 Xe3_LPG
[15:34:24] [PASSED] 30.05 Xe3_LPG
[15:34:24] [PASSED] 35.10 Xe3p_LPG
[15:34:24] [PASSED] 35.11 Xe3p_XPC
[15:34:24] ================ [PASSED] check_graphics_ip ================
[15:34:24] ===================== check_media_ip  ======================
[15:34:24] [PASSED] 12.00 Xe_M
[15:34:24] [PASSED] 12.55 Xe_HPM
[15:34:24] [PASSED] 13.00 Xe_LPM+
[15:34:24] [PASSED] 13.01 Xe2_HPM
[15:34:24] [PASSED] 20.00 Xe2_LPM
[15:34:24] [PASSED] 30.00 Xe3_LPM
[15:34:24] [PASSED] 30.02 Xe3_LPM
[15:34:24] [PASSED] 35.00 Xe3p_LPM
[15:34:24] [PASSED] 35.03 Xe3p_HPM
[15:34:24] ================= [PASSED] check_media_ip ==================
[15:34:24] =================== check_platform_desc  ===================
[15:34:24] [PASSED] 0x9A60 (TIGERLAKE)
[15:34:24] [PASSED] 0x9A68 (TIGERLAKE)
[15:34:24] [PASSED] 0x9A70 (TIGERLAKE)
[15:34:24] [PASSED] 0x9A40 (TIGERLAKE)
[15:34:24] [PASSED] 0x9A49 (TIGERLAKE)
[15:34:24] [PASSED] 0x9A59 (TIGERLAKE)
[15:34:24] [PASSED] 0x9A78 (TIGERLAKE)
[15:34:24] [PASSED] 0x9AC0 (TIGERLAKE)
[15:34:24] [PASSED] 0x9AC9 (TIGERLAKE)
[15:34:24] [PASSED] 0x9AD9 (TIGERLAKE)
[15:34:24] [PASSED] 0x9AF8 (TIGERLAKE)
[15:34:24] [PASSED] 0x4C80 (ROCKETLAKE)
[15:34:24] [PASSED] 0x4C8A (ROCKETLAKE)
[15:34:24] [PASSED] 0x4C8B (ROCKETLAKE)
[15:34:24] [PASSED] 0x4C8C (ROCKETLAKE)
[15:34:24] [PASSED] 0x4C90 (ROCKETLAKE)
[15:34:24] [PASSED] 0x4C9A (ROCKETLAKE)
[15:34:24] [PASSED] 0x4680 (ALDERLAKE_S)
[15:34:24] [PASSED] 0x4682 (ALDERLAKE_S)
[15:34:24] [PASSED] 0x4688 (ALDERLAKE_S)
[15:34:24] [PASSED] 0x468A (ALDERLAKE_S)
[15:34:24] [PASSED] 0x468B (ALDERLAKE_S)
[15:34:24] [PASSED] 0x4690 (ALDERLAKE_S)
[15:34:24] [PASSED] 0x4692 (ALDERLAKE_S)
[15:34:24] [PASSED] 0x4693 (ALDERLAKE_S)
[15:34:24] [PASSED] 0x46A0 (ALDERLAKE_P)
[15:34:24] [PASSED] 0x46A1 (ALDERLAKE_P)
[15:34:24] [PASSED] 0x46A2 (ALDERLAKE_P)
[15:34:24] [PASSED] 0x46A3 (ALDERLAKE_P)
[15:34:24] [PASSED] 0x46A6 (ALDERLAKE_P)
[15:34:24] [PASSED] 0x46A8 (ALDERLAKE_P)
[15:34:24] [PASSED] 0x46AA (ALDERLAKE_P)
[15:34:24] [PASSED] 0x462A (ALDERLAKE_P)
[15:34:24] [PASSED] 0x4626 (ALDERLAKE_P)
[15:34:24] [PASSED] 0x4628 (ALDERLAKE_P)
[15:34:24] [PASSED] 0x46B0 (ALDERLAKE_P)
[15:34:24] [PASSED] 0x46B1 (ALDERLAKE_P)
[15:34:24] [PASSED] 0x46B2 (ALDERLAKE_P)
[15:34:24] [PASSED] 0x46B3 (ALDERLAKE_P)
[15:34:24] [PASSED] 0x46C0 (ALDERLAKE_P)
[15:34:24] [PASSED] 0x46C1 (ALDERLAKE_P)
[15:34:24] [PASSED] 0x46C2 (ALDERLAKE_P)
[15:34:24] [PASSED] 0x46C3 (ALDERLAKE_P)
[15:34:24] [PASSED] 0x46D0 (ALDERLAKE_N)
[15:34:24] [PASSED] 0x46D1 (ALDERLAKE_N)
[15:34:24] [PASSED] 0x46D2 (ALDERLAKE_N)
[15:34:24] [PASSED] 0x46D3 (ALDERLAKE_N)
[15:34:24] [PASSED] 0x46D4 (ALDERLAKE_N)
[15:34:24] [PASSED] 0xA721 (ALDERLAKE_P)
[15:34:24] [PASSED] 0xA7A1 (ALDERLAKE_P)
[15:34:24] [PASSED] 0xA7A9 (ALDERLAKE_P)
[15:34:24] [PASSED] 0xA7AC (ALDERLAKE_P)
[15:34:24] [PASSED] 0xA7AD (ALDERLAKE_P)
[15:34:24] [PASSED] 0xA720 (ALDERLAKE_P)
[15:34:24] [PASSED] 0xA7A0 (ALDERLAKE_P)
[15:34:24] [PASSED] 0xA7A8 (ALDERLAKE_P)
[15:34:24] [PASSED] 0xA7AA (ALDERLAKE_P)
[15:34:24] [PASSED] 0xA7AB (ALDERLAKE_P)
[15:34:24] [PASSED] 0xA780 (ALDERLAKE_S)
[15:34:24] [PASSED] 0xA781 (ALDERLAKE_S)
[15:34:24] [PASSED] 0xA782 (ALDERLAKE_S)
[15:34:24] [PASSED] 0xA783 (ALDERLAKE_S)
[15:34:24] [PASSED] 0xA788 (ALDERLAKE_S)
[15:34:24] [PASSED] 0xA789 (ALDERLAKE_S)
[15:34:24] [PASSED] 0xA78A (ALDERLAKE_S)
[15:34:24] [PASSED] 0xA78B (ALDERLAKE_S)
[15:34:24] [PASSED] 0x4905 (DG1)
[15:34:24] [PASSED] 0x4906 (DG1)
[15:34:24] [PASSED] 0x4907 (DG1)
[15:34:24] [PASSED] 0x4908 (DG1)
[15:34:24] [PASSED] 0x4909 (DG1)
[15:34:24] [PASSED] 0x56C0 (DG2)
[15:34:24] [PASSED] 0x56C2 (DG2)
[15:34:24] [PASSED] 0x56C1 (DG2)
[15:34:24] [PASSED] 0x7D51 (METEORLAKE)
[15:34:24] [PASSED] 0x7DD1 (METEORLAKE)
[15:34:24] [PASSED] 0x7D41 (METEORLAKE)
[15:34:24] [PASSED] 0x7D67 (METEORLAKE)
[15:34:24] [PASSED] 0xB640 (METEORLAKE)
[15:34:24] [PASSED] 0x56A0 (DG2)
[15:34:24] [PASSED] 0x56A1 (DG2)
[15:34:24] [PASSED] 0x56A2 (DG2)
[15:34:24] [PASSED] 0x56BE (DG2)
[15:34:24] [PASSED] 0x56BF (DG2)
[15:34:24] [PASSED] 0x5690 (DG2)
[15:34:24] [PASSED] 0x5691 (DG2)
[15:34:24] [PASSED] 0x5692 (DG2)
[15:34:24] [PASSED] 0x56A5 (DG2)
[15:34:24] [PASSED] 0x56A6 (DG2)
[15:34:24] [PASSED] 0x56B0 (DG2)
[15:34:24] [PASSED] 0x56B1 (DG2)
[15:34:24] [PASSED] 0x56BA (DG2)
[15:34:24] [PASSED] 0x56BB (DG2)
[15:34:24] [PASSED] 0x56BC (DG2)
[15:34:24] [PASSED] 0x56BD (DG2)
[15:34:24] [PASSED] 0x5693 (DG2)
[15:34:24] [PASSED] 0x5694 (DG2)
[15:34:24] [PASSED] 0x5695 (DG2)
[15:34:24] [PASSED] 0x56A3 (DG2)
[15:34:24] [PASSED] 0x56A4 (DG2)
[15:34:24] [PASSED] 0x56B2 (DG2)
[15:34:24] [PASSED] 0x56B3 (DG2)
[15:34:24] [PASSED] 0x5696 (DG2)
[15:34:24] [PASSED] 0x5697 (DG2)
[15:34:24] [PASSED] 0xB69 (PVC)
[15:34:24] [PASSED] 0xB6E (PVC)
[15:34:24] [PASSED] 0xBD4 (PVC)
[15:34:24] [PASSED] 0xBD5 (PVC)
[15:34:24] [PASSED] 0xBD6 (PVC)
[15:34:24] [PASSED] 0xBD7 (PVC)
[15:34:24] [PASSED] 0xBD8 (PVC)
[15:34:24] [PASSED] 0xBD9 (PVC)
[15:34:24] [PASSED] 0xBDA (PVC)
[15:34:24] [PASSED] 0xBDB (PVC)
[15:34:24] [PASSED] 0xBE0 (PVC)
[15:34:24] [PASSED] 0xBE1 (PVC)
[15:34:24] [PASSED] 0xBE5 (PVC)
[15:34:24] [PASSED] 0x7D40 (METEORLAKE)
[15:34:24] [PASSED] 0x7D45 (METEORLAKE)
[15:34:24] [PASSED] 0x7D55 (METEORLAKE)
[15:34:24] [PASSED] 0x7D60 (METEORLAKE)
[15:34:24] [PASSED] 0x7DD5 (METEORLAKE)
[15:34:24] [PASSED] 0x6420 (LUNARLAKE)
[15:34:24] [PASSED] 0x64A0 (LUNARLAKE)
[15:34:24] [PASSED] 0x64B0 (LUNARLAKE)
[15:34:24] [PASSED] 0xE202 (BATTLEMAGE)
[15:34:24] [PASSED] 0xE209 (BATTLEMAGE)
[15:34:24] [PASSED] 0xE20B (BATTLEMAGE)
[15:34:24] [PASSED] 0xE20C (BATTLEMAGE)
[15:34:24] [PASSED] 0xE20D (BATTLEMAGE)
[15:34:24] [PASSED] 0xE210 (BATTLEMAGE)
[15:34:24] [PASSED] 0xE211 (BATTLEMAGE)
[15:34:24] [PASSED] 0xE212 (BATTLEMAGE)
[15:34:24] [PASSED] 0xE216 (BATTLEMAGE)
[15:34:24] [PASSED] 0xE220 (BATTLEMAGE)
[15:34:24] [PASSED] 0xE221 (BATTLEMAGE)
[15:34:24] [PASSED] 0xE222 (BATTLEMAGE)
[15:34:24] [PASSED] 0xE223 (BATTLEMAGE)
[15:34:24] [PASSED] 0xB080 (PANTHERLAKE)
[15:34:24] [PASSED] 0xB081 (PANTHERLAKE)
[15:34:24] [PASSED] 0xB082 (PANTHERLAKE)
[15:34:24] [PASSED] 0xB083 (PANTHERLAKE)
[15:34:24] [PASSED] 0xB084 (PANTHERLAKE)
[15:34:24] [PASSED] 0xB085 (PANTHERLAKE)
[15:34:24] [PASSED] 0xB086 (PANTHERLAKE)
[15:34:24] [PASSED] 0xB087 (PANTHERLAKE)
[15:34:24] [PASSED] 0xB08F (PANTHERLAKE)
[15:34:24] [PASSED] 0xB090 (PANTHERLAKE)
[15:34:24] [PASSED] 0xB0A0 (PANTHERLAKE)
[15:34:24] [PASSED] 0xB0B0 (PANTHERLAKE)
[15:34:24] [PASSED] 0xFD80 (PANTHERLAKE)
[15:34:24] [PASSED] 0xFD81 (PANTHERLAKE)
[15:34:24] [PASSED] 0xD740 (NOVALAKE_S)
[15:34:24] [PASSED] 0xD741 (NOVALAKE_S)
[15:34:24] [PASSED] 0xD742 (NOVALAKE_S)
[15:34:24] [PASSED] 0xD743 (NOVALAKE_S)
[15:34:24] [PASSED] 0xD745 (NOVALAKE_S)
[15:34:24] [PASSED] 0xD74A (NOVALAKE_S)
[15:34:24] [PASSED] 0xD74B (NOVALAKE_S)
[15:34:24] [PASSED] 0x674C (CRESCENTISLAND)
[15:34:24] [PASSED] 0x674D (CRESCENTISLAND)
[15:34:24] [PASSED] 0x674E (CRESCENTISLAND)
[15:34:24] [PASSED] 0x674F (CRESCENTISLAND)
[15:34:24] [PASSED] 0x6750 (CRESCENTISLAND)
[15:34:24] [PASSED] 0xD750 (NOVALAKE_P)
[15:34:24] [PASSED] 0xD751 (NOVALAKE_P)
[15:34:24] [PASSED] 0xD752 (NOVALAKE_P)
[15:34:24] [PASSED] 0xD753 (NOVALAKE_P)
[15:34:24] [PASSED] 0xD754 (NOVALAKE_P)
[15:34:24] [PASSED] 0xD755 (NOVALAKE_P)
[15:34:24] [PASSED] 0xD756 (NOVALAKE_P)
[15:34:24] [PASSED] 0xD757 (NOVALAKE_P)
[15:34:24] [PASSED] 0xD75F (NOVALAKE_P)
[15:34:24] =============== [PASSED] check_platform_desc ===============
[15:34:24] ===================== [PASSED] xe_pci ======================
[15:34:24] ============= xe_rtp_tables_test (5 subtests) ==============
[15:34:24] ================== xe_rtp_table_gt_test  ===================
[15:34:24] [PASSED] gt_was/14011060649
[15:34:24] [PASSED] gt_was/14011059788
[15:34:24] [PASSED] gt_was/14015795083
[15:34:24] [PASSED] gt_was/16021867713
[15:34:24] [PASSED] gt_was/14019449301
[15:34:24] [PASSED] gt_was/16028005424
[15:34:24] [PASSED] gt_was/14026578760
[15:34:24] [PASSED] gt_was/1409420604
[15:34:24] [PASSED] gt_was/1408615072
[15:34:24] [PASSED] gt_was/22010523718
[15:34:24] [PASSED] gt_was/14011006942
[15:34:24] [PASSED] gt_was/14014830051
[15:34:24] [PASSED] gt_was/18018781329
[15:34:24] [PASSED] gt_was/1509235366
[15:34:24] [PASSED] gt_was/18018781329
[15:34:24] [PASSED] gt_was/16016694945
[15:34:24] [PASSED] gt_was/14018575942
[15:34:24] [PASSED] gt_was/22016670082
[15:34:24] [PASSED] gt_was/22016670082
[15:34:24] [PASSED] gt_was/14017421178
[15:34:24] [PASSED] gt_was/16025250150
[15:34:24] [PASSED] gt_was/14021871409
[15:34:24] [PASSED] gt_was/16021865536
[15:34:24] [PASSED] gt_was/14021486841
[15:34:24] [PASSED] gt_was/14025160223
[15:34:24] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[15:34:24] [PASSED] gt_was/14025635424
[15:34:24] [PASSED] gt_was/16028005424
[15:34:24] ============== [PASSED] xe_rtp_table_gt_test ===============
[15:34:24] ================== xe_rtp_table_gt_test  ===================
[15:34:24] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[15:34:24] [PASSED] gt_tunings/Tuning: 32B Access Enable
[15:34:24] [PASSED] gt_tunings/Tuning: L3 cache
[15:34:24] [PASSED] gt_tunings/Tuning: L3 cache - media
[15:34:24] [PASSED] gt_tunings/Tuning: Compression Overfetch
[15:34:24] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[15:34:24] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[15:34:24] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[15:34:24] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[15:34:24] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[15:34:24] [PASSED] gt_tunings/Tuning: Stateless compression control
[15:34:24] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[15:34:24] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[15:34:24] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[15:34:24] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[15:34:24] ============== [PASSED] xe_rtp_table_gt_test ===============
[15:34:24] ================== xe_rtp_table_oob_test  ==================
[15:34:24] [PASSED] oob_was/1607983814
[15:34:24] [PASSED] oob_was/16010904313
[15:34:24] [PASSED] oob_was/18022495364
[15:34:24] [PASSED] oob_was/22012773006
[15:34:24] [PASSED] oob_was/14014475959
[15:34:24] [PASSED] oob_was/22011391025
[15:34:24] [PASSED] oob_was/22012727170
[15:34:24] [PASSED] oob_was/22012727685
[15:34:24] [PASSED] oob_was/22016596838
[15:34:24] [PASSED] oob_was/18020744125
[15:34:24] [PASSED] oob_was/1409600907
[15:34:24] [PASSED] oob_was/22014953428
[15:34:24] [PASSED] oob_was/16017236439
[15:34:24] [PASSED] oob_was/14019821291
[15:34:24] [PASSED] oob_was/14015076503
[15:34:24] [PASSED] oob_was/14018913170
[15:34:24] [PASSED] oob_was/14018094691
[15:34:24] [PASSED] oob_was/18024947630
[15:34:24] [PASSED] oob_was/16022287689
[15:34:24] [PASSED] oob_was/13011645652
[15:34:24] [PASSED] oob_was/14022293748
[15:34:24] [PASSED] oob_was/22019794406
[15:34:24] [PASSED] oob_was/22019338487
[15:34:24] [PASSED] oob_was/16023588340
[15:34:24] [PASSED] oob_was/14019789679
[15:34:24] [PASSED] oob_was/14022866841
[15:34:24] [PASSED] oob_was/16021333562
[15:34:24] [PASSED] oob_was/14016712196
[15:34:24] [PASSED] oob_was/14015568240
[15:34:24] [PASSED] oob_was/18013179988
[15:34:24] [PASSED] oob_was/1508761755
[15:34:24] [PASSED] oob_was/16023105232
[15:34:24] [PASSED] oob_was/16026508708
[15:34:24] [PASSED] oob_was/14020001231
[15:34:24] [PASSED] oob_was/16023683509
[15:34:24] [PASSED] oob_was/14025515070
[15:34:24] [PASSED] oob_was/15015404425_disable
[15:34:24] [PASSED] oob_was/16026007364
[15:34:24] [PASSED] oob_was/14020316580
[15:34:24] [PASSED] oob_was/14025883347
[15:34:24] [PASSED] oob_was/16029380221
[15:34:24] [PASSED] oob_was/22022079272
[15:34:24] [PASSED] oob_was/16029897822
[15:34:24] ============== [PASSED] xe_rtp_table_oob_test ==============
[15:34:24] ================ xe_rtp_table_dev_oob_test  ================
[15:34:24] [PASSED] device_oob_was/22010954014
[15:34:24] [PASSED] device_oob_was/15015404425
[15:34:24] [PASSED] device_oob_was/22019338487_display
[15:34:24] [PASSED] device_oob_was/14022085890
[15:34:24] [PASSED] device_oob_was/14026539277
[15:34:24] [PASSED] device_oob_was/14026633728
[15:34:24] [PASSED] device_oob_was/14026746987
[15:34:24] [PASSED] device_oob_was/14026779378
[15:34:24] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[15:34:24] ========== xe_rtp_table_missing_upper_bound_test  ==========
[15:34:24] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[15:34:24] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[15:34:24] [PASSED] register_whitelist/1806527549
[15:34:24] [PASSED] register_whitelist/allow_read_ctx_timestamp
[15:34:24] [PASSED] register_whitelist/allow_read_queue_timestamp
[15:34:24] [PASSED] register_whitelist/16014440446
[15:34:24] [PASSED] register_whitelist/16017236439
[15:34:24] [PASSED] register_whitelist/16020183090
[15:34:24] [PASSED] register_whitelist/14024997852
[15:34:24] [PASSED] register_whitelist/14024997852
[15:34:24] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[15:34:24] =============== [PASSED] xe_rtp_tables_test ================
[15:34:24] =================== xe_rtp (3 subtests) ====================
[15:34:24] =================== xe_rtp_rules_tests  ====================
[15:34:24] [PASSED] no
[15:34:24] [PASSED] yes
[15:34:24] [PASSED] no-and-no
[15:34:24] [PASSED] no-and-yes
[15:34:24] [PASSED] yes-and-no
[15:34:24] [PASSED] yes-and-yes
[15:34:24] [PASSED] no-or-no
[15:34:24] [PASSED] no-or-yes
[15:34:24] [PASSED] yes-or-no
[15:34:24] [PASSED] yes-or-yes
[15:34:24] [PASSED] no-yes-or-yes-no
[15:34:24] [PASSED] no-yes-or-yes-yes
[15:34:24] [PASSED] yes-yes-or-no-yes
[15:34:24] [PASSED] yes-yes-or-yes-yes
[15:34:24] [PASSED] no-no-or-yes-or-no
[15:34:24] [PASSED] or
[15:34:24] [PASSED] or-yes
[15:34:24] [PASSED] or-no
[15:34:24] [PASSED] yes-or
[15:34:24] [PASSED] no-or
[15:34:24] [PASSED] no-or-or-yes
[15:34:24] [PASSED] yes-or-or-no
[15:34:24] [PASSED] no-or-or-no
[15:34:24] [PASSED] missing-context-engine-class
[15:34:24] [PASSED] missing-context-engine-class-or-yes
[15:34:24] [PASSED] missing-context-engine-class-or-or-yes
[15:34:24] =============== [PASSED] xe_rtp_rules_tests ================
[15:34:24] =============== xe_rtp_process_to_sr_tests  ================
[15:34:24] [PASSED] coalesce-same-reg
[15:34:24] [PASSED] coalesce-same-reg-literal-and-func
[15:34:24] [PASSED] no-match-no-add
[15:34:24] [PASSED] two-regs-two-entries
[15:34:24] [PASSED] clr-one-set-other
[15:34:24] [PASSED] set-field
[15:34:24] [PASSED] conflict-duplicate
[15:34:24] [PASSED] conflict-not-disjoint
[15:34:24] [PASSED] conflict-not-disjoint-literal-and-func
[15:34:24] [PASSED] conflict-reg-type
[15:34:24] [PASSED] bad-mcr-reg-forced-to-regular
[15:34:24] [PASSED] bad-regular-reg-forced-to-mcr
[15:34:24] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[15:34:24] ================== xe_rtp_process_tests  ===================
[15:34:24] [PASSED] active1
[15:34:24] [PASSED] active2
[15:34:24] [PASSED] active-inactive
[15:34:24] [PASSED] inactive-active
[15:34:24] [PASSED] inactive-active-inactive
[15:34:24] [PASSED] inactive-inactive-inactive
[15:34:24] ============== [PASSED] xe_rtp_process_tests ===============
[15:34:24] ===================== [PASSED] xe_rtp ======================
[15:34:24] ==================== xe_wa (1 subtest) =====================
[15:34:24] ======================== xe_wa_gt  =========================
[15:34:24] [PASSED] TIGERLAKE B0
[15:34:24] [PASSED] DG1 A0
[15:34:24] [PASSED] DG1 B0
[15:34:24] [PASSED] ALDERLAKE_S A0
[15:34:24] [PASSED] ALDERLAKE_S B0
[15:34:24] [PASSED] ALDERLAKE_S C0
[15:34:24] [PASSED] ALDERLAKE_S D0
[15:34:24] [PASSED] ALDERLAKE_P A0
[15:34:24] [PASSED] ALDERLAKE_P B0
[15:34:24] [PASSED] ALDERLAKE_P C0
[15:34:24] [PASSED] ALDERLAKE_S RPLS D0
[15:34:24] [PASSED] ALDERLAKE_P RPLU E0
[15:34:24] [PASSED] DG2 G10 C0
[15:34:24] [PASSED] DG2 G11 B1
[15:34:24] [PASSED] DG2 G12 A1
[15:34:24] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[15:34:24] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[15:34:24] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[15:34:24] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[15:34:24] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[15:34:24] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[15:34:24] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[15:34:24] ==================== [PASSED] xe_wa_gt =====================
[15:34:24] ====================== [PASSED] xe_wa ======================
[15:34:24] ============================================================
[15:34:24] Testing complete. Ran 741 tests: passed: 723, skipped: 18
[15:34:24] Elapsed time: 36.663s total, 4.373s configuring, 31.624s building, 0.651s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[15:34:24] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:34:26] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:34:50] Starting KUnit Kernel (1/1)...
[15:34:50] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:34:50] ============ drm_test_pick_cmdline (2 subtests) ============
[15:34:50] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[15:34:50] =============== drm_test_pick_cmdline_named  ===============
[15:34:50] [PASSED] NTSC
[15:34:50] [PASSED] NTSC-J
[15:34:50] [PASSED] PAL
[15:34:50] [PASSED] PAL-M
[15:34:50] =========== [PASSED] drm_test_pick_cmdline_named ===========
[15:34:50] ============== [PASSED] drm_test_pick_cmdline ==============
[15:34:50] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[15:34:50] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[15:34:50] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[15:34:50] =========== drm_validate_clone_mode (2 subtests) ===========
[15:34:50] ============== drm_test_check_in_clone_mode  ===============
[15:34:50] [PASSED] in_clone_mode
[15:34:50] [PASSED] not_in_clone_mode
[15:34:50] ========== [PASSED] drm_test_check_in_clone_mode ===========
[15:34:50] =============== drm_test_check_valid_clones  ===============
[15:34:50] [PASSED] not_in_clone_mode
[15:34:50] [PASSED] valid_clone
[15:34:50] [PASSED] invalid_clone
[15:34:50] =========== [PASSED] drm_test_check_valid_clones ===========
[15:34:50] ============= [PASSED] drm_validate_clone_mode =============
[15:34:50] ============= drm_validate_modeset (1 subtest) =============
[15:34:50] [PASSED] drm_test_check_connector_changed_modeset
[15:34:50] ============== [PASSED] drm_validate_modeset ===============
[15:34:50] ====== drm_test_bridge_get_current_state (2 subtests) ======
[15:34:50] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[15:34:50] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[15:34:50] ======== [PASSED] drm_test_bridge_get_current_state ========
[15:34:50] ====== drm_test_bridge_helper_reset_crtc (4 subtests) ======
[15:34:50] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[15:34:50] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[15:34:50] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[15:34:50] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[15:34:50] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[15:34:50] ============== drm_bridge_alloc (2 subtests) ===============
[15:34:50] [PASSED] drm_test_drm_bridge_alloc_basic
[15:34:50] [PASSED] drm_test_drm_bridge_alloc_get_put
[15:34:50] ================ [PASSED] drm_bridge_alloc =================
[15:34:50] ============= drm_bridge_bus_fmt (5 subtests) ==============
[15:34:50] [PASSED] drm_test_bridge_rgb_yuv_rgb
[15:34:50] [PASSED] drm_test_bridge_must_convert_to_yuv444
[15:34:50] [PASSED] drm_test_bridge_hdmi_auto_rgb
[15:34:50] [PASSED] drm_test_bridge_auto_first
[15:34:50] [PASSED] drm_test_bridge_rgb_yuv_no_path
[15:34:50] =============== [PASSED] drm_bridge_bus_fmt ================
[15:34:50] ============= drm_cmdline_parser (40 subtests) =============
[15:34:50] [PASSED] drm_test_cmdline_force_d_only
[15:34:50] [PASSED] drm_test_cmdline_force_D_only_dvi
[15:34:50] [PASSED] drm_test_cmdline_force_D_only_hdmi
[15:34:50] [PASSED] drm_test_cmdline_force_D_only_not_digital
[15:34:50] [PASSED] drm_test_cmdline_force_e_only
[15:34:50] [PASSED] drm_test_cmdline_res
[15:34:50] [PASSED] drm_test_cmdline_res_vesa
[15:34:50] [PASSED] drm_test_cmdline_res_vesa_rblank
[15:34:50] [PASSED] drm_test_cmdline_res_rblank
[15:34:50] [PASSED] drm_test_cmdline_res_bpp
[15:34:50] [PASSED] drm_test_cmdline_res_refresh
[15:34:50] [PASSED] drm_test_cmdline_res_bpp_refresh
[15:34:50] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[15:34:50] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[15:34:50] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[15:34:50] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[15:34:50] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[15:34:50] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[15:34:50] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[15:34:50] [PASSED] drm_test_cmdline_res_margins_force_on
[15:34:50] [PASSED] drm_test_cmdline_res_vesa_margins
[15:34:50] [PASSED] drm_test_cmdline_name
[15:34:50] [PASSED] drm_test_cmdline_name_bpp
[15:34:50] [PASSED] drm_test_cmdline_name_option
[15:34:50] [PASSED] drm_test_cmdline_name_bpp_option
[15:34:50] [PASSED] drm_test_cmdline_rotate_0
[15:34:50] [PASSED] drm_test_cmdline_rotate_90
[15:34:50] [PASSED] drm_test_cmdline_rotate_180
[15:34:50] [PASSED] drm_test_cmdline_rotate_270
[15:34:50] [PASSED] drm_test_cmdline_hmirror
[15:34:50] [PASSED] drm_test_cmdline_vmirror
[15:34:50] [PASSED] drm_test_cmdline_margin_options
[15:34:50] [PASSED] drm_test_cmdline_multiple_options
[15:34:50] [PASSED] drm_test_cmdline_bpp_extra_and_option
[15:34:50] [PASSED] drm_test_cmdline_extra_and_option
[15:34:50] [PASSED] drm_test_cmdline_freestanding_options
[15:34:50] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[15:34:50] [PASSED] drm_test_cmdline_panel_orientation
[15:34:50] ================ drm_test_cmdline_invalid  =================
[15:34:50] [PASSED] margin_only
[15:34:50] [PASSED] interlace_only
[15:34:50] [PASSED] res_missing_x
[15:34:50] [PASSED] res_missing_y
[15:34:50] [PASSED] res_bad_y
[15:34:50] [PASSED] res_missing_y_bpp
[15:34:50] [PASSED] res_bad_bpp
[15:34:50] [PASSED] res_bad_refresh
[15:34:50] [PASSED] res_bpp_refresh_force_on_off
[15:34:50] [PASSED] res_invalid_mode
[15:34:50] [PASSED] res_bpp_wrong_place_mode
[15:34:50] [PASSED] name_bpp_refresh
[15:34:50] [PASSED] name_refresh
[15:34:50] [PASSED] name_refresh_wrong_mode
[15:34:50] [PASSED] name_refresh_invalid_mode
[15:34:50] [PASSED] rotate_multiple
[15:34:50] [PASSED] rotate_invalid_val
[15:34:50] [PASSED] rotate_truncated
[15:34:50] [PASSED] invalid_option
[15:34:50] [PASSED] invalid_tv_option
[15:34:50] [PASSED] truncated_tv_option
[15:34:50] ============ [PASSED] drm_test_cmdline_invalid =============
[15:34:50] =============== drm_test_cmdline_tv_options  ===============
[15:34:50] [PASSED] NTSC
[15:34:50] [PASSED] NTSC_443
[15:34:50] [PASSED] NTSC_J
[15:34:50] [PASSED] PAL
[15:34:50] [PASSED] PAL_M
[15:34:50] [PASSED] PAL_N
[15:34:50] [PASSED] SECAM
[15:34:50] [PASSED] MONO_525
[15:34:50] [PASSED] MONO_625
[15:34:50] =========== [PASSED] drm_test_cmdline_tv_options ===========
[15:34:50] =============== [PASSED] drm_cmdline_parser ================
[15:34:50] ========== drmm_connector_hdmi_init (20 subtests) ==========
[15:34:50] [PASSED] drm_test_connector_hdmi_init_valid
[15:34:50] [PASSED] drm_test_connector_hdmi_init_bpc_8
[15:34:50] [PASSED] drm_test_connector_hdmi_init_bpc_10
[15:34:50] [PASSED] drm_test_connector_hdmi_init_bpc_12
[15:34:50] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[15:34:50] [PASSED] drm_test_connector_hdmi_init_bpc_null
[15:34:50] [PASSED] drm_test_connector_hdmi_init_formats_empty
[15:34:50] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[15:34:50] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[15:34:50] [PASSED] supported_formats=0x9 yuv420_allowed=1
[15:34:50] [PASSED] supported_formats=0x9 yuv420_allowed=0
[15:34:50] [PASSED] supported_formats=0x5 yuv420_allowed=1
[15:34:50] [PASSED] supported_formats=0x5 yuv420_allowed=0
[15:34:50] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[15:34:50] [PASSED] drm_test_connector_hdmi_init_null_ddc
[15:34:50] [PASSED] drm_test_connector_hdmi_init_null_product
[15:34:50] [PASSED] drm_test_connector_hdmi_init_null_vendor
[15:34:50] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[15:34:50] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[15:34:50] [PASSED] drm_test_connector_hdmi_init_product_valid
[15:34:50] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[15:34:50] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[15:34:50] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[15:34:50] ========= drm_test_connector_hdmi_init_type_valid  =========
[15:34:50] [PASSED] HDMI-A
[15:34:50] [PASSED] HDMI-B
[15:34:50] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[15:34:50] ======== drm_test_connector_hdmi_init_type_invalid  ========
[15:34:50] [PASSED] Unknown
[15:34:50] [PASSED] VGA
[15:34:50] [PASSED] DVI-I
[15:34:50] [PASSED] DVI-D
[15:34:50] [PASSED] DVI-A
[15:34:50] [PASSED] Composite
[15:34:50] [PASSED] SVIDEO
[15:34:50] [PASSED] LVDS
[15:34:50] [PASSED] Component
[15:34:50] [PASSED] DIN
[15:34:50] [PASSED] DP
[15:34:50] [PASSED] TV
[15:34:50] [PASSED] eDP
[15:34:50] [PASSED] Virtual
[15:34:50] [PASSED] DSI
[15:34:50] [PASSED] DPI
[15:34:50] [PASSED] Writeback
[15:34:50] [PASSED] SPI
[15:34:50] [PASSED] USB
[15:34:50] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[15:34:50] ============ [PASSED] drmm_connector_hdmi_init =============
[15:34:50] ============= drmm_connector_init (3 subtests) =============
[15:34:50] [PASSED] drm_test_drmm_connector_init
[15:34:50] [PASSED] drm_test_drmm_connector_init_null_ddc
[15:34:50] ========= drm_test_drmm_connector_init_type_valid  =========
[15:34:50] [PASSED] Unknown
[15:34:50] [PASSED] VGA
[15:34:50] [PASSED] DVI-I
[15:34:50] [PASSED] DVI-D
[15:34:50] [PASSED] DVI-A
[15:34:50] [PASSED] Composite
[15:34:50] [PASSED] SVIDEO
[15:34:50] [PASSED] LVDS
[15:34:50] [PASSED] Component
[15:34:50] [PASSED] DIN
[15:34:50] [PASSED] DP
[15:34:50] [PASSED] HDMI-A
[15:34:50] [PASSED] HDMI-B
[15:34:50] [PASSED] TV
[15:34:50] [PASSED] eDP
[15:34:50] [PASSED] Virtual
[15:34:50] [PASSED] DSI
[15:34:50] [PASSED] DPI
[15:34:50] [PASSED] Writeback
[15:34:50] [PASSED] SPI
[15:34:50] [PASSED] USB
[15:34:50] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[15:34:50] =============== [PASSED] drmm_connector_init ===============
[15:34:50] ========= drm_connector_dynamic_init (6 subtests) ==========
[15:34:50] [PASSED] drm_test_drm_connector_dynamic_init
[15:34:50] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[15:34:50] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[15:34:50] [PASSED] drm_test_drm_connector_dynamic_init_properties
[15:34:50] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[15:34:50] [PASSED] Unknown
[15:34:50] [PASSED] VGA
[15:34:50] [PASSED] DVI-I
[15:34:50] [PASSED] DVI-D
[15:34:50] [PASSED] DVI-A
[15:34:50] [PASSED] Composite
[15:34:50] [PASSED] SVIDEO
[15:34:50] [PASSED] LVDS
[15:34:50] [PASSED] Component
[15:34:50] [PASSED] DIN
[15:34:50] [PASSED] DP
[15:34:50] [PASSED] HDMI-A
[15:34:50] [PASSED] HDMI-B
[15:34:50] [PASSED] TV
[15:34:50] [PASSED] eDP
[15:34:50] [PASSED] Virtual
[15:34:50] [PASSED] DSI
[15:34:50] [PASSED] DPI
[15:34:50] [PASSED] Writeback
[15:34:50] [PASSED] SPI
[15:34:50] [PASSED] USB
[15:34:50] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[15:34:50] ======== drm_test_drm_connector_dynamic_init_name  =========
[15:34:50] [PASSED] Unknown
[15:34:50] [PASSED] VGA
[15:34:50] [PASSED] DVI-I
[15:34:50] [PASSED] DVI-D
[15:34:50] [PASSED] DVI-A
[15:34:50] [PASSED] Composite
[15:34:50] [PASSED] SVIDEO
[15:34:50] [PASSED] LVDS
[15:34:50] [PASSED] Component
[15:34:50] [PASSED] DIN
[15:34:50] [PASSED] DP
[15:34:50] [PASSED] HDMI-A
[15:34:50] [PASSED] HDMI-B
[15:34:50] [PASSED] TV
[15:34:50] [PASSED] eDP
[15:34:50] [PASSED] Virtual
[15:34:50] [PASSED] DSI
[15:34:50] [PASSED] DPI
[15:34:50] [PASSED] Writeback
[15:34:50] [PASSED] SPI
[15:34:50] [PASSED] USB
[15:34:50] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[15:34:50] =========== [PASSED] drm_connector_dynamic_init ============
[15:34:50] ==== drm_connector_dynamic_register_early (4 subtests) =====
[15:34:50] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[15:34:50] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[15:34:50] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[15:34:50] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[15:34:50] ====== [PASSED] drm_connector_dynamic_register_early =======
[15:34:50] ======= drm_connector_dynamic_register (7 subtests) ========
[15:34:50] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[15:34:50] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[15:34:50] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[15:34:50] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[15:34:50] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[15:34:50] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[15:34:50] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[15:34:50] ========= [PASSED] drm_connector_dynamic_register ==========
[15:34:50] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[15:34:50] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[15:34:50] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[15:34:50] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[15:34:50] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[15:34:50] ========== drm_test_get_tv_mode_from_name_valid  ===========
[15:34:50] [PASSED] NTSC
[15:34:50] [PASSED] NTSC-443
[15:34:50] [PASSED] NTSC-J
[15:34:50] [PASSED] PAL
[15:34:50] [PASSED] PAL-M
[15:34:50] [PASSED] PAL-N
[15:34:50] [PASSED] SECAM
[15:34:50] [PASSED] Mono
[15:34:50] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[15:34:50] [PASSED] drm_test_get_tv_mode_from_name_truncated
[15:34:50] ============ [PASSED] drm_get_tv_mode_from_name ============
[15:34:50] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[15:34:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[15:34:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[15:34:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[15:34:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[15:34:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[15:34:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[15:34:50] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[15:34:50] [PASSED] VIC 96
[15:34:50] [PASSED] VIC 97
[15:34:50] [PASSED] VIC 101
[15:34:50] [PASSED] VIC 102
[15:34:50] [PASSED] VIC 106
[15:34:50] [PASSED] VIC 107
[15:34:50] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[15:34:50] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[15:34:50] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[15:34:50] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[15:34:50] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[15:34:50] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[15:34:50] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[15:34:50] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[15:34:50] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[15:34:50] [PASSED] Automatic
[15:34:50] [PASSED] Full
[15:34:50] [PASSED] Limited 16:235
[15:34:50] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[15:34:50] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[15:34:50] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[15:34:50] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[15:34:50] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[15:34:50] [PASSED] RGB
[15:34:50] [PASSED] YUV 4:2:0
[15:34:50] [PASSED] YUV 4:2:2
[15:34:50] [PASSED] YUV 4:4:4
[15:34:50] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[15:34:50] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[15:34:50] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[15:34:50] ============= drm_damage_helper (21 subtests) ==============
[15:34:50] [PASSED] drm_test_damage_iter_no_damage
[15:34:50] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[15:34:50] [PASSED] drm_test_damage_iter_no_damage_src_moved
[15:34:50] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[15:34:50] [PASSED] drm_test_damage_iter_no_damage_not_visible
[15:34:50] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[15:34:50] [PASSED] drm_test_damage_iter_no_damage_no_fb
[15:34:50] [PASSED] drm_test_damage_iter_simple_damage
[15:34:50] [PASSED] drm_test_damage_iter_single_damage
[15:34:50] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[15:34:50] [PASSED] drm_test_damage_iter_single_damage_outside_src
[15:34:50] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[15:34:50] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[15:34:50] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[15:34:50] [PASSED] drm_test_damage_iter_single_damage_src_moved
[15:34:50] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[15:34:50] [PASSED] drm_test_damage_iter_damage
[15:34:50] [PASSED] drm_test_damage_iter_damage_one_intersect
[15:34:50] [PASSED] drm_test_damage_iter_damage_one_outside
[15:34:50] [PASSED] drm_test_damage_iter_damage_src_moved
[15:34:50] [PASSED] drm_test_damage_iter_damage_not_visible
[15:34:50] ================ [PASSED] drm_damage_helper ================
[15:34:50] ============== drm_dp_mst_helper (3 subtests) ==============
[15:34:50] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[15:34:50] [PASSED] Clock 154000 BPP 30 DSC disabled
[15:34:50] [PASSED] Clock 234000 BPP 30 DSC disabled
[15:34:50] [PASSED] Clock 297000 BPP 24 DSC disabled
[15:34:50] [PASSED] Clock 332880 BPP 24 DSC enabled
[15:34:50] [PASSED] Clock 324540 BPP 24 DSC enabled
[15:34:50] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[15:34:50] ============== drm_test_dp_mst_calc_pbn_div  ===============
[15:34:50] [PASSED] Link rate 2000000 lane count 4
[15:34:50] [PASSED] Link rate 2000000 lane count 2
[15:34:50] [PASSED] Link rate 2000000 lane count 1
[15:34:50] [PASSED] Link rate 1350000 lane count 4
[15:34:50] [PASSED] Link rate 1350000 lane count 2
[15:34:50] [PASSED] Link rate 1350000 lane count 1
[15:34:50] [PASSED] Link rate 1000000 lane count 4
[15:34:50] [PASSED] Link rate 1000000 lane count 2
[15:34:50] [PASSED] Link rate 1000000 lane count 1
[15:34:50] [PASSED] Link rate 810000 lane count 4
[15:34:50] [PASSED] Link rate 810000 lane count 2
[15:34:50] [PASSED] Link rate 810000 lane count 1
[15:34:50] [PASSED] Link rate 540000 lane count 4
[15:34:50] [PASSED] Link rate 540000 lane count 2
[15:34:50] [PASSED] Link rate 540000 lane count 1
[15:34:50] [PASSED] Link rate 270000 lane count 4
[15:34:50] [PASSED] Link rate 270000 lane count 2
[15:34:50] [PASSED] Link rate 270000 lane count 1
[15:34:50] [PASSED] Link rate 162000 lane count 4
[15:34:50] [PASSED] Link rate 162000 lane count 2
[15:34:50] [PASSED] Link rate 162000 lane count 1
[15:34:50] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[15:34:50] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[15:34:50] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[15:34:50] [PASSED] DP_POWER_UP_PHY with port number
[15:34:50] [PASSED] DP_POWER_DOWN_PHY with port number
[15:34:50] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[15:34:50] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[15:34:50] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[15:34:50] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[15:34:50] [PASSED] DP_QUERY_PAYLOAD with port number
[15:34:50] [PASSED] DP_QUERY_PAYLOAD with VCPI
[15:34:50] [PASSED] DP_REMOTE_DPCD_READ with port number
[15:34:50] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[15:34:50] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[15:34:50] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[15:34:50] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[15:34:50] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[15:34:50] [PASSED] DP_REMOTE_I2C_READ with port number
[15:34:50] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[15:34:50] [PASSED] DP_REMOTE_I2C_READ with transactions array
[15:34:50] [PASSED] DP_REMOTE_I2C_WRITE with port number
[15:34:50] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[15:34:50] [PASSED] DP_REMOTE_I2C_WRITE with data array
[15:34:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[15:34:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[15:34:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[15:34:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[15:34:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[15:34:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[15:34:50] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[15:34:50] ================ [PASSED] drm_dp_mst_helper ================
[15:34:50] ================== drm_exec (7 subtests) ===================
[15:34:50] [PASSED] sanitycheck
[15:34:50] [PASSED] test_lock
[15:34:50] [PASSED] test_lock_unlock
[15:34:50] [PASSED] test_duplicates
[15:34:50] [PASSED] test_prepare
[15:34:50] [PASSED] test_prepare_array
[15:34:50] [PASSED] test_multiple_loops
[15:34:50] ==================== [PASSED] drm_exec =====================
[15:34:50] =========== drm_format_helper_test (17 subtests) ===========
[15:34:50] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[15:34:50] [PASSED] single_pixel_source_buffer
[15:34:50] [PASSED] single_pixel_clip_rectangle
[15:34:50] [PASSED] well_known_colors
[15:34:50] [PASSED] destination_pitch
[15:34:50] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[15:34:50] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[15:34:50] [PASSED] single_pixel_source_buffer
[15:34:50] [PASSED] single_pixel_clip_rectangle
[15:34:50] [PASSED] well_known_colors
[15:34:50] [PASSED] destination_pitch
[15:34:50] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[15:34:50] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[15:34:50] [PASSED] single_pixel_source_buffer
[15:34:50] [PASSED] single_pixel_clip_rectangle
[15:34:50] [PASSED] well_known_colors
[15:34:50] [PASSED] destination_pitch
[15:34:50] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[15:34:50] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[15:34:50] [PASSED] single_pixel_source_buffer
[15:34:50] [PASSED] single_pixel_clip_rectangle
[15:34:50] [PASSED] well_known_colors
[15:34:50] [PASSED] destination_pitch
[15:34:50] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[15:34:50] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[15:34:50] [PASSED] single_pixel_source_buffer
[15:34:50] [PASSED] single_pixel_clip_rectangle
[15:34:50] [PASSED] well_known_colors
[15:34:50] [PASSED] destination_pitch
[15:34:50] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[15:34:50] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[15:34:50] [PASSED] single_pixel_source_buffer
[15:34:50] [PASSED] single_pixel_clip_rectangle
[15:34:50] [PASSED] well_known_colors
[15:34:50] [PASSED] destination_pitch
[15:34:50] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[15:34:50] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[15:34:50] [PASSED] single_pixel_source_buffer
[15:34:50] [PASSED] single_pixel_clip_rectangle
[15:34:50] [PASSED] well_known_colors
[15:34:50] [PASSED] destination_pitch
[15:34:50] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[15:34:50] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[15:34:50] [PASSED] single_pixel_source_buffer
[15:34:50] [PASSED] single_pixel_clip_rectangle
[15:34:50] [PASSED] well_known_colors
[15:34:50] [PASSED] destination_pitch
[15:34:50] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[15:34:50] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[15:34:50] [PASSED] single_pixel_source_buffer
[15:34:50] [PASSED] single_pixel_clip_rectangle
[15:34:50] [PASSED] well_known_colors
[15:34:50] [PASSED] destination_pitch
[15:34:50] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[15:34:50] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[15:34:50] [PASSED] single_pixel_source_buffer
[15:34:50] [PASSED] single_pixel_clip_rectangle
[15:34:50] [PASSED] well_known_colors
[15:34:50] [PASSED] destination_pitch
[15:34:50] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[15:34:50] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[15:34:50] [PASSED] single_pixel_source_buffer
[15:34:50] [PASSED] single_pixel_clip_rectangle
[15:34:50] [PASSED] well_known_colors
[15:34:50] [PASSED] destination_pitch
[15:34:50] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[15:34:50] ============== drm_test_fb_xrgb8888_to_mono  ===============
[15:34:50] [PASSED] single_pixel_source_buffer
[15:34:50] [PASSED] single_pixel_clip_rectangle
[15:34:50] [PASSED] well_known_colors
[15:34:50] [PASSED] destination_pitch
[15:34:50] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[15:34:50] ==================== drm_test_fb_swab  =====================
[15:34:50] [PASSED] single_pixel_source_buffer
[15:34:50] [PASSED] single_pixel_clip_rectangle
[15:34:50] [PASSED] well_known_colors
[15:34:50] [PASSED] destination_pitch
[15:34:50] ================ [PASSED] drm_test_fb_swab =================
[15:34:50] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[15:34:50] [PASSED] single_pixel_source_buffer
[15:34:50] [PASSED] single_pixel_clip_rectangle
[15:34:50] [PASSED] well_known_colors
[15:34:50] [PASSED] destination_pitch
[15:34:50] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[15:34:50] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[15:34:50] [PASSED] single_pixel_source_buffer
[15:34:50] [PASSED] single_pixel_clip_rectangle
[15:34:50] [PASSED] well_known_colors
[15:34:50] [PASSED] destination_pitch
[15:34:50] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[15:34:50] ================= drm_test_fb_clip_offset  =================
[15:34:50] [PASSED] pass through
[15:34:50] [PASSED] horizontal offset
[15:34:50] [PASSED] vertical offset
[15:34:50] [PASSED] horizontal and vertical offset
[15:34:50] [PASSED] horizontal offset (custom pitch)
[15:34:50] [PASSED] vertical offset (custom pitch)
[15:34:50] [PASSED] horizontal and vertical offset (custom pitch)
[15:34:50] ============= [PASSED] drm_test_fb_clip_offset =============
[15:34:50] =================== drm_test_fb_memcpy  ====================
[15:34:50] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[15:34:50] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[15:34:50] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[15:34:50] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[15:34:50] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[15:34:50] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[15:34:50] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[15:34:50] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[15:34:50] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[15:34:50] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[15:34:50] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[15:34:50] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[15:34:50] =============== [PASSED] drm_test_fb_memcpy ================
[15:34:50] ============= [PASSED] drm_format_helper_test ==============
[15:34:50] ================= drm_format (18 subtests) =================
[15:34:50] [PASSED] drm_test_format_block_width_invalid
[15:34:50] [PASSED] drm_test_format_block_width_one_plane
[15:34:50] [PASSED] drm_test_format_block_width_two_plane
[15:34:50] [PASSED] drm_test_format_block_width_three_plane
[15:34:50] [PASSED] drm_test_format_block_width_tiled
[15:34:50] [PASSED] drm_test_format_block_height_invalid
[15:34:50] [PASSED] drm_test_format_block_height_one_plane
[15:34:50] [PASSED] drm_test_format_block_height_two_plane
[15:34:50] [PASSED] drm_test_format_block_height_three_plane
[15:34:50] [PASSED] drm_test_format_block_height_tiled
[15:34:50] [PASSED] drm_test_format_min_pitch_invalid
[15:34:50] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[15:34:50] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[15:34:50] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[15:34:50] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[15:34:50] [PASSED] drm_test_format_min_pitch_two_plane
[15:34:50] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[15:34:50] [PASSED] drm_test_format_min_pitch_tiled
[15:34:50] =================== [PASSED] drm_format ====================
[15:34:50] ============== drm_framebuffer (10 subtests) ===============
[15:34:50] ========== drm_test_framebuffer_check_src_coords  ==========
[15:34:50] [PASSED] Success: source fits into fb
[15:34:50] [PASSED] Fail: overflowing fb with x-axis coordinate
[15:34:50] [PASSED] Fail: overflowing fb with y-axis coordinate
[15:34:50] [PASSED] Fail: overflowing fb with source width
[15:34:50] [PASSED] Fail: overflowing fb with source height
[15:34:50] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[15:34:50] [PASSED] drm_test_framebuffer_cleanup
[15:34:50] =============== drm_test_framebuffer_create  ===============
[15:34:50] [PASSED] ABGR8888 normal sizes
[15:34:50] [PASSED] ABGR8888 max sizes
[15:34:50] [PASSED] ABGR8888 pitch greater than min required
[15:34:50] [PASSED] ABGR8888 pitch less than min required
[15:34:50] [PASSED] ABGR8888 Invalid width
[15:34:50] [PASSED] ABGR8888 Invalid buffer handle
[15:34:50] [PASSED] No pixel format
[15:34:50] [PASSED] ABGR8888 Width 0
[15:34:50] [PASSED] ABGR8888 Height 0
[15:34:50] [PASSED] ABGR8888 Out of bound height * pitch combination
[15:34:50] [PASSED] ABGR8888 Large buffer offset
[15:34:50] [PASSED] ABGR8888 Buffer offset for inexistent plane
[15:34:50] [PASSED] ABGR8888 Invalid flag
[15:34:50] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[15:34:50] [PASSED] ABGR8888 Valid buffer modifier
[15:34:50] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[15:34:50] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[15:34:50] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[15:34:50] [PASSED] NV12 Normal sizes
[15:34:50] [PASSED] NV12 Max sizes
[15:34:50] [PASSED] NV12 Invalid pitch
[15:34:50] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[15:34:50] [PASSED] NV12 different  modifier per-plane
[15:34:50] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[15:34:50] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[15:34:50] [PASSED] NV12 Modifier for inexistent plane
[15:34:50] [PASSED] NV12 Handle for inexistent plane
[15:34:50] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[15:34:50] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[15:34:50] [PASSED] YVU420 Normal sizes
[15:34:50] [PASSED] YVU420 Max sizes
[15:34:50] [PASSED] YVU420 Invalid pitch
[15:34:50] [PASSED] YVU420 Different pitches
[15:34:50] [PASSED] YVU420 Different buffer offsets/pitches
[15:34:50] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[15:34:50] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[15:34:50] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[15:34:50] [PASSED] YVU420 Valid modifier
[15:34:50] [PASSED] YVU420 Different modifiers per plane
[15:34:50] [PASSED] YVU420 Modifier for inexistent plane
[15:34:50] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[15:34:50] [PASSED] X0L2 Normal sizes
[15:34:50] [PASSED] X0L2 Max sizes
[15:34:50] [PASSED] X0L2 Invalid pitch
[15:34:50] [PASSED] X0L2 Pitch greater than minimum required
[15:34:50] [PASSED] X0L2 Handle for inexistent plane
[15:34:50] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[15:34:50] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[15:34:50] [PASSED] X0L2 Valid modifier
[15:34:50] [PASSED] X0L2 Modifier for inexistent plane
[15:34:50] =========== [PASSED] drm_test_framebuffer_create ===========
[15:34:50] [PASSED] drm_test_framebuffer_free
[15:34:50] [PASSED] drm_test_framebuffer_init
[15:34:50] [PASSED] drm_test_framebuffer_init_bad_format
[15:34:50] [PASSED] drm_test_framebuffer_init_dev_mismatch
[15:34:50] [PASSED] drm_test_framebuffer_lookup
[15:34:50] [PASSED] drm_test_framebuffer_lookup_inexistent
[15:34:50] [PASSED] drm_test_framebuffer_modifiers_not_supported
[15:34:50] ================= [PASSED] drm_framebuffer =================
[15:34:50] ================ drm_gem_shmem (8 subtests) ================
[15:34:50] [PASSED] drm_gem_shmem_test_obj_create
[15:34:50] [PASSED] drm_gem_shmem_test_obj_create_private
[15:34:50] [PASSED] drm_gem_shmem_test_pin_pages
[15:34:50] [PASSED] drm_gem_shmem_test_vmap
[15:34:50] [PASSED] drm_gem_shmem_test_get_sg_table
[15:34:50] [PASSED] drm_gem_shmem_test_get_pages_sgt
[15:34:50] [PASSED] drm_gem_shmem_test_madvise
[15:34:50] [PASSED] drm_gem_shmem_test_purge
[15:34:50] ================== [PASSED] drm_gem_shmem ==================
[15:34:50] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[15:34:50] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[15:34:50] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[15:34:50] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[15:34:50] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[15:34:50] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[15:34:50] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[15:34:50] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[15:34:50] [PASSED] Automatic
[15:34:50] [PASSED] Full
[15:34:50] [PASSED] Limited 16:235
[15:34:50] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[15:34:50] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[15:34:50] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[15:34:50] [PASSED] drm_test_check_disable_connector
[15:34:50] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[15:34:50] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[15:34:50] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[15:34:50] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[15:34:50] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[15:34:50] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[15:34:50] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[15:34:50] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[15:34:50] [PASSED] drm_test_check_output_bpc_dvi
[15:34:50] [PASSED] drm_test_check_output_bpc_format_vic_1
[15:34:50] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[15:34:50] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[15:34:50] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[15:34:50] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[15:34:50] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[15:34:50] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[15:34:50] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[15:34:50] ============ drm_test_check_hdmi_color_format  =============
[15:34:50] [PASSED] AUTO -> RGB
[15:34:50] [PASSED] YCBCR422 -> YUV422
[15:34:50] [PASSED] YCBCR420 -> YUV420
[15:34:50] [PASSED] YCBCR444 -> YUV444
[15:34:50] [PASSED] RGB -> RGB
[15:34:50] ======== [PASSED] drm_test_check_hdmi_color_format =========
[15:34:50] ======== drm_test_check_hdmi_color_format_420_only  ========
[15:34:50] [PASSED] RGB should fail
[15:34:50] [PASSED] YUV444 should fail
[15:34:50] [PASSED] YUV422 should fail
[15:34:50] [PASSED] YUV420 should work
[15:34:50] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[15:34:50] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[15:34:50] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[15:34:50] [PASSED] drm_test_check_broadcast_rgb_value
[15:34:50] [PASSED] drm_test_check_bpc_8_value
[15:34:50] [PASSED] drm_test_check_bpc_10_value
[15:34:50] [PASSED] drm_test_check_bpc_12_value
[15:34:50] [PASSED] drm_test_check_format_value
[15:34:50] [PASSED] drm_test_check_tmds_char_value
[15:34:50] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[15:34:50] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[15:34:50] [PASSED] drm_test_check_mode_valid
[15:34:50] [PASSED] drm_test_check_mode_valid_reject
[15:34:50] [PASSED] drm_test_check_mode_valid_reject_rate
[15:34:50] [PASSED] drm_test_check_mode_valid_reject_max_clock
[15:34:50] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[15:34:50] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[15:34:50] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[15:34:50] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[15:34:50] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[15:34:50] [PASSED] drm_test_check_infoframes
[15:34:50] [PASSED] drm_test_check_reject_avi_infoframe
[15:34:50] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[15:34:50] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[15:34:50] [PASSED] drm_test_check_reject_audio_infoframe
[15:34:50] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[15:34:50] ================= drm_managed (2 subtests) =================
[15:34:50] [PASSED] drm_test_managed_release_action
[15:34:50] [PASSED] drm_test_managed_run_action
[15:34:50] =================== [PASSED] drm_managed ===================
[15:34:50] =================== drm_mm (6 subtests) ====================
[15:34:50] [PASSED] drm_test_mm_init
[15:34:50] [PASSED] drm_test_mm_debug
[15:34:50] [PASSED] drm_test_mm_align32
[15:34:50] [PASSED] drm_test_mm_align64
[15:34:50] [PASSED] drm_test_mm_lowest
[15:34:50] [PASSED] drm_test_mm_highest
[15:34:50] ===================== [PASSED] drm_mm ======================
[15:34:50] ============= drm_modes_analog_tv (5 subtests) =============
[15:34:50] [PASSED] drm_test_modes_analog_tv_mono_576i
[15:34:50] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[15:34:50] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[15:34:50] [PASSED] drm_test_modes_analog_tv_pal_576i
[15:34:50] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[15:34:50] =============== [PASSED] drm_modes_analog_tv ===============
[15:34:50] ============== drm_plane_helper (2 subtests) ===============
[15:34:50] =============== drm_test_check_plane_state  ================
[15:34:50] [PASSED] clipping_simple
[15:34:50] [PASSED] clipping_rotate_reflect
[15:34:50] [PASSED] positioning_simple
[15:34:50] [PASSED] upscaling
[15:34:50] [PASSED] downscaling
[15:34:50] [PASSED] rounding1
[15:34:50] [PASSED] rounding2
[15:34:50] [PASSED] rounding3
[15:34:50] [PASSED] rounding4
[15:34:50] =========== [PASSED] drm_test_check_plane_state ============
[15:34:50] =========== drm_test_check_invalid_plane_state  ============
[15:34:50] [PASSED] positioning_invalid
[15:34:50] [PASSED] upscaling_invalid
[15:34:50] [PASSED] downscaling_invalid
[15:34:50] ======= [PASSED] drm_test_check_invalid_plane_state ========
[15:34:50] ================ [PASSED] drm_plane_helper =================
[15:34:50] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[15:34:50] ====== drm_test_connector_helper_tv_get_modes_check  =======
[15:34:50] [PASSED] None
[15:34:50] [PASSED] PAL
[15:34:50] [PASSED] NTSC
[15:34:50] [PASSED] Both, NTSC Default
[15:34:50] [PASSED] Both, PAL Default
[15:34:50] [PASSED] Both, NTSC Default, with PAL on command-line
[15:34:50] [PASSED] Both, PAL Default, with NTSC on command-line
[15:34:50] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[15:34:50] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[15:34:50] ================== drm_rect (9 subtests) ===================
[15:34:50] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[15:34:50] [PASSED] drm_test_rect_clip_scaled_not_clipped
[15:34:50] [PASSED] drm_test_rect_clip_scaled_clipped
[15:34:50] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[15:34:50] ================= drm_test_rect_intersect  =================
[15:34:50] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[15:34:50] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[15:34:50] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[15:34:50] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[15:34:50] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[15:34:50] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[15:34:50] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[15:34:50] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[15:34:50] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[15:34:50] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[15:34:50] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[15:34:50] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[15:34:50] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[15:34:50] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[15:34:50] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[15:34:50] ============= [PASSED] drm_test_rect_intersect =============
[15:34:50] ================ drm_test_rect_calc_hscale  ================
[15:34:50] [PASSED] normal use
[15:34:50] [PASSED] out of max range
[15:34:50] [PASSED] out of min range
[15:34:50] [PASSED] zero dst
[15:34:50] [PASSED] negative src
[15:34:50] [PASSED] negative dst
[15:34:50] ============ [PASSED] drm_test_rect_calc_hscale ============
[15:34:50] ================ drm_test_rect_calc_vscale  ================
[15:34:50] [PASSED] normal use
[15:34:50] [PASSED] out of max range
[15:34:50] [PASSED] out of min range
[15:34:50] [PASSED] zero dst
[15:34:50] [PASSED] negative src
[15:34:50] [PASSED] negative dst
[15:34:50] ============ [PASSED] drm_test_rect_calc_vscale ============
[15:34:50] ================== drm_test_rect_rotate  ===================
[15:34:50] [PASSED] reflect-x
[15:34:50] [PASSED] reflect-y
[15:34:50] [PASSED] rotate-0
[15:34:50] [PASSED] rotate-90
[15:34:50] [PASSED] rotate-180
[15:34:50] [PASSED] rotate-270
[15:34:50] ============== [PASSED] drm_test_rect_rotate ===============
[15:34:50] ================ drm_test_rect_rotate_inv  =================
[15:34:50] [PASSED] reflect-x
[15:34:50] [PASSED] reflect-y
[15:34:50] [PASSED] rotate-0
[15:34:50] [PASSED] rotate-90
[15:34:50] [PASSED] rotate-180
[15:34:50] [PASSED] rotate-270
[15:34:50] ============ [PASSED] drm_test_rect_rotate_inv =============
[15:34:50] ==================== [PASSED] drm_rect =====================
[15:34:50] ============ drm_sysfb_modeset_test (1 subtest) ============
[15:34:50] ============ drm_test_sysfb_build_fourcc_list  =============
[15:34:50] [PASSED] no native formats
[15:34:50] [PASSED] XRGB8888 as native format
[15:34:50] [PASSED] remove duplicates
[15:34:50] [PASSED] convert alpha formats
[15:34:50] [PASSED] random formats
[15:34:50] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[15:34:50] ============= [PASSED] drm_sysfb_modeset_test ==============
[15:34:50] ================== drm_fixp (2 subtests) ===================
[15:34:50] [PASSED] drm_test_int2fixp
[15:34:50] [PASSED] drm_test_sm2fixp
[15:34:50] ==================== [PASSED] drm_fixp =====================
[15:34:50] ============================================================
[15:34:50] Testing complete. Ran 639 tests: passed: 639
[15:34:50] Elapsed time: 26.554s total, 1.816s configuring, 24.573s building, 0.146s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[15:34:50] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:34:52] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:35:02] Starting KUnit Kernel (1/1)...
[15:35:02] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:35:02] ================= ttm_device (5 subtests) ==================
[15:35:02] [PASSED] ttm_device_init_basic
[15:35:02] [PASSED] ttm_device_init_multiple
[15:35:02] [PASSED] ttm_device_fini_basic
[15:35:02] [PASSED] ttm_device_init_no_vma_man
[15:35:02] ================== ttm_device_init_pools  ==================
[15:35:02] [PASSED] No DMA allocations, no DMA32 required
[15:35:02] [PASSED] DMA allocations, DMA32 required
[15:35:02] [PASSED] No DMA allocations, DMA32 required
[15:35:02] [PASSED] DMA allocations, no DMA32 required
[15:35:02] ============== [PASSED] ttm_device_init_pools ==============
[15:35:02] =================== [PASSED] ttm_device ====================
[15:35:02] ================== ttm_pool (8 subtests) ===================
[15:35:02] ================== ttm_pool_alloc_basic  ===================
[15:35:02] [PASSED] One page
[15:35:02] [PASSED] More than one page
[15:35:02] [PASSED] Above the allocation limit
[15:35:02] [PASSED] One page, with coherent DMA mappings enabled
[15:35:02] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[15:35:02] ============== [PASSED] ttm_pool_alloc_basic ===============
[15:35:02] ============== ttm_pool_alloc_basic_dma_addr  ==============
[15:35:02] [PASSED] One page
[15:35:02] [PASSED] More than one page
[15:35:02] [PASSED] Above the allocation limit
[15:35:02] [PASSED] One page, with coherent DMA mappings enabled
[15:35:02] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[15:35:02] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[15:35:02] [PASSED] ttm_pool_alloc_order_caching_match
[15:35:02] [PASSED] ttm_pool_alloc_caching_mismatch
[15:35:02] [PASSED] ttm_pool_alloc_order_mismatch
[15:35:02] [PASSED] ttm_pool_free_dma_alloc
[15:35:02] [PASSED] ttm_pool_free_no_dma_alloc
[15:35:02] [PASSED] ttm_pool_fini_basic
[15:35:02] ==================== [PASSED] ttm_pool =====================
[15:35:02] ================ ttm_resource (8 subtests) =================
[15:35:02] ================= ttm_resource_init_basic  =================
[15:35:02] [PASSED] Init resource in TTM_PL_SYSTEM
[15:35:02] [PASSED] Init resource in TTM_PL_VRAM
[15:35:02] [PASSED] Init resource in a private placement
[15:35:02] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[15:35:02] ============= [PASSED] ttm_resource_init_basic =============
[15:35:02] [PASSED] ttm_resource_init_pinned
[15:35:02] [PASSED] ttm_resource_fini_basic
[15:35:02] [PASSED] ttm_resource_manager_init_basic
[15:35:02] [PASSED] ttm_resource_manager_usage_basic
[15:35:02] [PASSED] ttm_resource_manager_set_used_basic
[15:35:02] [PASSED] ttm_sys_man_alloc_basic
[15:35:02] [PASSED] ttm_sys_man_free_basic
[15:35:02] ================== [PASSED] ttm_resource ===================
[15:35:02] =================== ttm_tt (15 subtests) ===================
[15:35:02] ==================== ttm_tt_init_basic  ====================
[15:35:02] [PASSED] Page-aligned size
[15:35:02] [PASSED] Extra pages requested
[15:35:02] ================ [PASSED] ttm_tt_init_basic ================
[15:35:02] [PASSED] ttm_tt_init_misaligned
[15:35:02] [PASSED] ttm_tt_fini_basic
[15:35:02] [PASSED] ttm_tt_fini_sg
[15:35:02] [PASSED] ttm_tt_fini_shmem
[15:35:02] [PASSED] ttm_tt_create_basic
[15:35:02] [PASSED] ttm_tt_create_invalid_bo_type
[15:35:02] [PASSED] ttm_tt_create_ttm_exists
[15:35:02] [PASSED] ttm_tt_create_failed
[15:35:02] [PASSED] ttm_tt_destroy_basic
[15:35:02] [PASSED] ttm_tt_populate_null_ttm
[15:35:02] [PASSED] ttm_tt_populate_populated_ttm
[15:35:02] [PASSED] ttm_tt_unpopulate_basic
[15:35:02] [PASSED] ttm_tt_unpopulate_empty_ttm
[15:35:02] [PASSED] ttm_tt_swapin_basic
[15:35:02] ===================== [PASSED] ttm_tt ======================
[15:35:02] =================== ttm_bo (14 subtests) ===================
[15:35:02] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[15:35:02] [PASSED] Cannot be interrupted and sleeps
[15:35:02] [PASSED] Cannot be interrupted, locks straight away
[15:35:02] [PASSED] Can be interrupted, sleeps
[15:35:02] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[15:35:02] [PASSED] ttm_bo_reserve_locked_no_sleep
[15:35:02] [PASSED] ttm_bo_reserve_no_wait_ticket
[15:35:02] [PASSED] ttm_bo_reserve_double_resv
[15:35:02] [PASSED] ttm_bo_reserve_interrupted
[15:35:02] [PASSED] ttm_bo_reserve_deadlock
[15:35:02] [PASSED] ttm_bo_unreserve_basic
[15:35:02] [PASSED] ttm_bo_unreserve_pinned
[15:35:02] [PASSED] ttm_bo_unreserve_bulk
[15:35:02] [PASSED] ttm_bo_fini_basic
[15:35:02] [PASSED] ttm_bo_fini_shared_resv
[15:35:02] [PASSED] ttm_bo_pin_basic
[15:35:02] [PASSED] ttm_bo_pin_unpin_resource
[15:35:02] [PASSED] ttm_bo_multiple_pin_one_unpin
[15:35:02] ===================== [PASSED] ttm_bo ======================
[15:35:02] ============== ttm_bo_validate (22 subtests) ===============
[15:35:02] ============== ttm_bo_init_reserved_sys_man  ===============
[15:35:02] [PASSED] Buffer object for userspace
[15:35:02] [PASSED] Kernel buffer object
[15:35:02] [PASSED] Shared buffer object
[15:35:02] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[15:35:02] ============== ttm_bo_init_reserved_mock_man  ==============
[15:35:02] [PASSED] Buffer object for userspace
[15:35:02] [PASSED] Kernel buffer object
[15:35:02] [PASSED] Shared buffer object
[15:35:02] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[15:35:02] [PASSED] ttm_bo_init_reserved_resv
[15:35:02] ================== ttm_bo_validate_basic  ==================
[15:35:02] [PASSED] Buffer object for userspace
[15:35:02] [PASSED] Kernel buffer object
[15:35:02] [PASSED] Shared buffer object
[15:35:02] ============== [PASSED] ttm_bo_validate_basic ==============
[15:35:02] [PASSED] ttm_bo_validate_invalid_placement
[15:35:02] ============= ttm_bo_validate_same_placement  ==============
[15:35:02] [PASSED] System manager
[15:35:02] [PASSED] VRAM manager
[15:35:02] ========= [PASSED] ttm_bo_validate_same_placement ==========
[15:35:02] [PASSED] ttm_bo_validate_failed_alloc
[15:35:02] [PASSED] ttm_bo_validate_pinned
[15:35:02] [PASSED] ttm_bo_validate_busy_placement
[15:35:02] ================ ttm_bo_validate_multihop  =================
[15:35:02] [PASSED] Buffer object for userspace
[15:35:02] [PASSED] Kernel buffer object
[15:35:02] [PASSED] Shared buffer object
[15:35:02] ============ [PASSED] ttm_bo_validate_multihop =============
[15:35:02] ========== ttm_bo_validate_no_placement_signaled  ==========
[15:35:02] [PASSED] Buffer object in system domain, no page vector
[15:35:02] [PASSED] Buffer object in system domain with an existing page vector
[15:35:02] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[15:35:02] ======== ttm_bo_validate_no_placement_not_signaled  ========
[15:35:02] [PASSED] Buffer object for userspace
[15:35:02] [PASSED] Kernel buffer object
[15:35:02] [PASSED] Shared buffer object
[15:35:02] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[15:35:02] [PASSED] ttm_bo_validate_move_fence_signaled
[15:35:02] ========= ttm_bo_validate_move_fence_not_signaled  =========
[15:35:02] [PASSED] Waits for GPU
[15:35:02] [PASSED] Tries to lock straight away
[15:35:02] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[15:35:02] [PASSED] ttm_bo_validate_swapout
[15:35:02] [PASSED] ttm_bo_validate_happy_evict
[15:35:02] [PASSED] ttm_bo_validate_all_pinned_evict
[15:35:02] [PASSED] ttm_bo_validate_allowed_only_evict
[15:35:02] [PASSED] ttm_bo_validate_deleted_evict
[15:35:02] [PASSED] ttm_bo_validate_busy_domain_evict
[15:35:02] [PASSED] ttm_bo_validate_evict_gutting
[15:35:02] [PASSED] ttm_bo_validate_recrusive_evict
[15:35:02] ================= [PASSED] ttm_bo_validate =================
[15:35:02] ============================================================
[15:35:02] Testing complete. Ran 102 tests: passed: 102
[15:35:02] Elapsed time: 11.964s total, 1.788s configuring, 9.960s building, 0.184s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915/dp: Enable UHBR link rates on tunneled links

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 960 bytes --]

== Series Details ==

Series: drm/i915/dp: Enable UHBR link rates on tunneled links
URL   : https://patchwork.freedesktop.org/series/170424/
State : success

== Summary ==

CI Bug Log - changes from xe-5399-45c0f0c41055eb52626f68070e895739d22531a6_BAT -> xe-pw-170424v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 12)
------------------------------

  Missing    (1): bat-bmg-2 


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-5399-45c0f0c41055eb52626f68070e895739d22531a6 -> xe-pw-170424v1

  IGT_9006: 6380a8af26359dd222e22679442272ded836c463 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5399-45c0f0c41055eb52626f68070e895739d22531a6: 45c0f0c41055eb52626f68070e895739d22531a6
  xe-pw-170424v1: 170424v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/index.html

[-- Attachment #2: Type: text/html, Size: 1508 bytes --]

✓ Xe.CI.FULL: success for drm/i915/dp: Enable UHBR link rates on tunneled links

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 15821 bytes --]

== Series Details ==

Series: drm/i915/dp: Enable UHBR link rates on tunneled links
URL   : https://patchwork.freedesktop.org/series/170424/
State : success

== Summary ==

CI Bug Log - changes from xe-5399-45c0f0c41055eb52626f68070e895739d22531a6_FULL -> xe-pw-170424v1_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-170424v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-bmg:          NOTRUN -> [SKIP][1] ([Intel XE#2370])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][2] ([Intel XE#2327]) +1 other test skip
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#1124]) +1 other test skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html

  * igt@kms_ccs@crc-primary-basic-y-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#2887]) +1 other test skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@kms_ccs@crc-primary-basic-y-tiled-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [PASS][5] -> [INCOMPLETE][6] ([Intel XE#7084] / [Intel XE#8150]) +1 other test incomplete
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5399-45c0f0c41055eb52626f68070e895739d22531a6/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#3432])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs.html

  * igt@kms_chamelium_edid@hdmi-edid-change-during-hibernate:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2252]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@kms_chamelium_edid@hdmi-edid-change-during-hibernate.html

  * igt@kms_content_protection@atomic:
    - shard-bmg:          NOTRUN -> [FAIL][9] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@kms_content_protection@atomic.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#2320]) +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_dsc@dsc-basic:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#8265])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@kms_dsc@dsc-basic.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-lnl:          [PASS][12] -> [FAIL][13] ([Intel XE#301] / [Intel XE#3149])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5399-45c0f0c41055eb52626f68070e895739d22531a6/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#7178] / [Intel XE#7351])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html

  * igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-pri-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2311]) +11 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrshdr-argb161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#7061]) +1 other test skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@kms_frontbuffer_tracking@drrshdr-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#4141]) +2 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-shrfb-plflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2313]) +10 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-shrfb-plflip-blt.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#6911] / [Intel XE#7466])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_plane@pixel-format-yf-tiled-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#7283])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@kms_plane@pixel-format-yf-tiled-modifier.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#1489])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html

  * igt@kms_psr@fbc-pr-primary-render:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@kms_psr@fbc-pr-primary-render.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#1499])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [PASS][24] -> [INCOMPLETE][25] ([Intel XE#6321] / [Intel XE#8355])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5399-45c0f0c41055eb52626f68070e895739d22531a6/shard-bmg-9/igt@xe_evict@evict-mixed-many-threads-small.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-4/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#2322] / [Intel XE#7372]) +1 other test skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-rebind.html

  * igt@xe_exec_fault_mode@twice-multi-queue:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#8374]) +2 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@xe_exec_fault_mode@twice-multi-queue.html

  * igt@xe_exec_multi_queue@two-queues-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#8364]) +5 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@xe_exec_multi_queue@two-queues-userptr.html

  * igt@xe_exec_reset@long-spin-comp-reuse-many-preempt-threads:
    - shard-bmg:          [PASS][29] -> [FAIL][30] ([Intel XE#7850])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5399-45c0f0c41055eb52626f68070e895739d22531a6/shard-bmg-9/igt@xe_exec_reset@long-spin-comp-reuse-many-preempt-threads.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-4/igt@xe_exec_reset@long-spin-comp-reuse-many-preempt-threads.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#8378]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-userptr-rebind.html

  * igt@xe_query@multigpu-query-oa-units:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#944])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@xe_query@multigpu-query-oa-units.html

  
#### Possible fixes ####

  * igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
    - shard-bmg:          [FAIL][33] ([Intel XE#3098] / [Intel XE#3149]) -> [PASS][34] +1 other test pass
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5399-45c0f0c41055eb52626f68070e895739d22531a6/shard-bmg-1/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-10/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [FAIL][35] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5399-45c0f0c41055eb52626f68070e895739d22531a6/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_ggtt_init_early:
    - shard-bmg:          [ABORT][37] ([Intel XE#8007]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5399-45c0f0c41055eb52626f68070e895739d22531a6/shard-bmg-5/igt@xe_fault_injection@inject-fault-probe-function-xe_ggtt_init_early.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-3/igt@xe_fault_injection@inject-fault-probe-function-xe_ggtt_init_early.html

  
#### Warnings ####

  * igt@kms_flip@2x-flip-vs-blocking-wf-vblank@cd-dp2-hdmi-a3:
    - shard-bmg:          [FAIL][39] ([Intel XE#3149] / [Intel XE#6266]) -> [FAIL][40] ([Intel XE#3098] / [Intel XE#3149]) +1 other test fail
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5399-45c0f0c41055eb52626f68070e895739d22531a6/shard-bmg-4/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@cd-dp2-hdmi-a3.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-bmg-5/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@cd-dp2-hdmi-a3.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-lnl:          [FAIL][41] ([Intel XE#301] / [Intel XE#3149]) -> [FAIL][42] ([Intel XE#301])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5399-45c0f0c41055eb52626f68070e895739d22531a6/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][43] ([Intel XE#301]) -> [FAIL][44] ([Intel XE#301] / [Intel XE#3149])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5399-45c0f0c41055eb52626f68070e895739d22531a6/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-lnl:          [SKIP][45] ([Intel XE#7905]) -> [ABORT][46] ([Intel XE#8007])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5399-45c0f0c41055eb52626f68070e895739d22531a6/shard-lnl-4/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-scndscrn-cur-indfb-draw-mmap-wc.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/shard-lnl-4/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2370
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#6266]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6266
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7466
  [Intel XE#7850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7850
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8150
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-5399-45c0f0c41055eb52626f68070e895739d22531a6 -> xe-pw-170424v1

  IGT_9006: 6380a8af26359dd222e22679442272ded836c463 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5399-45c0f0c41055eb52626f68070e895739d22531a6: 45c0f0c41055eb52626f68070e895739d22531a6
  xe-pw-170424v1: 170424v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170424v1/index.html

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