[PATCH v2 0/2] drm/xe/sysctrl: Add fwctl support for System Controller

[PATCH v2 0/2] drm/xe/sysctrl: Add fwctl support for System Controller

[Anoop, Vijay]

From: Anoop Vijay <anoop.c.vijay@intel.com>

This series adds FWCTL support for the Xe System Controller (sysctrl)
firmware.

The Xe System Controller is a firmware-managed entity responsible for
selected platform-level control and coordination tasks on Intel Xe3p
discrete GPU platforms. This series registers a
FWCTL_DEVICE_TYPE_XE_SYSCTRL device so userspace can query sysctrl
capabilities and issue RPC requests through the generic
/dev/fwctl/fwctlN interface.

Supported operations are ECC status query, RAS error-injection
capability query, and RAS error injection, each gated by the
appropriate FWCTL_RPC scope and a per-context capability bit.

---
v2: (Rodrigo)
- Rename FWCTL_DEVICE_TYPE_XE to FWCTL_DEVICE_TYPE_XE_SYSCTRL, one type
  per firmware instead of a shared Xe-wide type
- Rename xe.h to xe_sysctrl.h to match
- Squash uapi and type definitions into a single patch
- Replace validate_scope() with explicit per-op scope/capability checks
  in xe_sysctrl_fwctl_rpc()
---

Anoop Vijay (2):
  drm/xe/sysctrl: Add System Controller get application status
  drm/xe/sysctrl: Add fwctl support for System Controller

 Documentation/userspace-api/fwctl/index.rst   |   1 +
 .../userspace-api/fwctl/xe_sysctrl.rst        | 120 +++++++++
 drivers/gpu/drm/xe/Kconfig                    |   1 +
 drivers/gpu/drm/xe/Makefile                   |   1 +
 drivers/gpu/drm/xe/xe_device.c                |   5 +
 drivers/gpu/drm/xe/xe_sysctrl.c               |  82 ++++++
 drivers/gpu/drm/xe/xe_sysctrl.h               |   2 +
 drivers/gpu/drm/xe/xe_sysctrl_fwctl.c         | 251 ++++++++++++++++++
 drivers/gpu/drm/xe/xe_sysctrl_fwctl.h         |  13 +
 drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h | 151 +++++++++++
 include/uapi/fwctl/fwctl.h                    |   1 +
 include/uapi/fwctl/xe_sysctrl.h               | 117 ++++++++
 12 files changed, 745 insertions(+)
 create mode 100644 Documentation/userspace-api/fwctl/xe_sysctrl.rst
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_fwctl.c
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_fwctl.h
 create mode 100644 include/uapi/fwctl/xe_sysctrl.h

-- 
2.43.0

[PATCH v2 1/2] drm/xe/sysctrl: Add System Controller get application status

[Anoop, Vijay]

From: Anoop Vijay <anoop.c.vijay@intel.com>

Do not review, CI only.

Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
---
 drivers/gpu/drm/xe/xe_sysctrl.c               | 82 +++++++++++++++++++
 drivers/gpu/drm/xe/xe_sysctrl.h               |  2 +
 drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h | 65 +++++++++++++++
 3 files changed, 149 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
index 1db20be8158b..8eac58647265 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl.c
+++ b/drivers/gpu/drm/xe/xe_sysctrl.c
@@ -13,9 +13,11 @@
 #include "xe_device.h"
 #include "xe_mmio.h"
 #include "xe_pm.h"
+#include "xe_printk.h"
 #include "xe_soc_remapper.h"
 #include "xe_sysctrl.h"
 #include "xe_sysctrl_mailbox.h"
+#include "xe_sysctrl_mailbox_types.h"
 #include "xe_sysctrl_types.h"
 
 /**
@@ -130,3 +132,83 @@ void xe_sysctrl_pm_resume(struct xe_device *xe)
 
 	xe_sysctrl_mailbox_init(sc);
 }
+
+static enum xe_sysctrl_fw_status
+xe_sysctrl_check_app_status(struct xe_device *xe, enum xe_sysctrl_app_id app_id)
+{
+	struct xe_sysctrl_app_status_req req = {};
+	struct xe_sysctrl_app_status_resp resp = {};
+	struct xe_sysctrl_mailbox_command cmd = {};
+	size_t out_len = 0;
+	u32 flags;
+	int ret;
+
+	if (!xe->info.has_sysctrl)
+		return XE_SYSCTRL_FIRMWARE_APP_NOTSUPP;
+
+	req.app_id = (u8)app_id;
+
+	xe_sysctrl_create_command(&cmd, XE_SYSCTRL_GROUP_CORE, XE_SYSCTRL_CMD_GET_APP_STATUS_BY_ID,
+				  &req, sizeof(req), &resp, sizeof(resp));
+
+	ret = xe_sysctrl_send_command(&xe->sc, &cmd, &out_len);
+	if (ret)
+		return XE_SYSCTRL_FIRMWARE_COMM_FAILURE;
+
+	if (out_len != sizeof(resp)) {
+		xe_err(xe, "sysctrl: unexpected get app status response length %zu (expected %zu)\n",
+		       out_len, sizeof(resp));
+		return XE_SYSCTRL_FIRMWARE_COMM_FAILURE;
+	}
+
+	flags = resp.flags;
+
+	if (!(flags & XE_SYSCTRL_APP_RESP_VALID))
+		return XE_SYSCTRL_FIRMWARE_APP_INVALID;
+
+	if (!(flags & XE_SYSCTRL_APP_RESP_BOOTED))
+		return XE_SYSCTRL_FIRMWARE_APP_NOT_LOADED;
+
+	if (!(flags & XE_SYSCTRL_APP_RESP_INITIALIZED))
+		return XE_SYSCTRL_FIRMWARE_APP_BOOTED;
+
+	return XE_SYSCTRL_FIRMWARE_APP_INITIALIZED;
+}
+
+/**
+ * xe_sysctrl_is_oobmsm_fw_ready() - Check if oCode firmware is fully initialized
+ * @xe: xe device instance
+ *
+ * Returns true if oCode firmware has reached the initialized state, indicating
+ * it is ready to handle requests. Returns true also on platforms without System
+ * Controller support, as there is no firmware gate to wait on.
+ *
+ * Return: true if oCode is initialized or sysctrl is not present, false otherwise
+ */
+bool xe_sysctrl_is_oobmsm_fw_ready(struct xe_device *xe)
+{
+	enum xe_sysctrl_fw_status status =
+		xe_sysctrl_check_app_status(xe, XE_SYSCTRL_APP_OCODE);
+
+	return status == XE_SYSCTRL_FIRMWARE_APP_INITIALIZED ||
+	       status == XE_SYSCTRL_FIRMWARE_APP_NOTSUPP;
+}
+
+/**
+ * xe_sysctrl_is_diag_fw_ready() - Check if diag firmware is fully initialized
+ * @xe: xe device instance
+ *
+ * Returns true if diag firmware has reached the initialized state, indicating
+ * it is ready to handle requests. Returns true also on platforms without System
+ * Controller support, as there is no firmware gate to wait on.
+ *
+ * Return: true if diag firmware is initialized or sysctrl is not present, false otherwise
+ */
+bool xe_sysctrl_is_diag_fw_ready(struct xe_device *xe)
+{
+	enum xe_sysctrl_fw_status status =
+		xe_sysctrl_check_app_status(xe, XE_SYSCTRL_APP_DIAG);
+
+	return status == XE_SYSCTRL_FIRMWARE_APP_INITIALIZED ||
+	       status == XE_SYSCTRL_FIRMWARE_APP_NOTSUPP;
+}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
index 090dffb6d55f..b69a3f474236 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl.h
@@ -20,5 +20,7 @@ void xe_sysctrl_event(struct xe_sysctrl *sc);
 int xe_sysctrl_init(struct xe_device *xe);
 void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
 void xe_sysctrl_pm_resume(struct xe_device *xe);
+bool xe_sysctrl_is_oobmsm_fw_ready(struct xe_device *xe);
+bool xe_sysctrl_is_diag_fw_ready(struct xe_device *xe);
 
 #endif
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
index d0341538ad05..b507e1553cbb 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
@@ -14,9 +14,11 @@
  * enum xe_sysctrl_group - System Controller command groups
  *
  * @XE_SYSCTRL_GROUP_GFSP: GFSP group
+ * @XE_SYSCTRL_GROUP_CORE: Core group
  */
 enum xe_sysctrl_group {
 	XE_SYSCTRL_GROUP_GFSP			= 0x01,
+	XE_SYSCTRL_GROUP_CORE			= 0xFF,
 };
 
 /**
@@ -38,6 +40,69 @@ enum xe_sysctrl_gfsp_cmd {
 	XE_SYSCTRL_CMD_SET_HEALTH		= 0x0C,
 };
 
+/**
+ * enum xe_sysctrl_core_cmd - Commands supported by Core group
+ *
+ * @XE_SYSCTRL_CMD_GET_APP_STATUS_BY_ID: Retrieve application status by ID
+ */
+enum xe_sysctrl_core_cmd {
+	XE_SYSCTRL_CMD_GET_APP_STATUS_BY_ID		= 0x05,
+};
+
+/**
+ * struct xe_sysctrl_app_status_req - Get application status request
+ *
+ * @app_id: Application ID for which to retrieve status
+ */
+struct xe_sysctrl_app_status_req {
+	u8 app_id;
+} __packed;
+
+/**
+ * struct xe_sysctrl_app_status_resp - Get application status response
+ * @flags: Application status flags (see XE_SYSCTRL_APP_RESP_* definitions)
+ */
+struct xe_sysctrl_app_status_resp {
+	u32 flags;
+} __packed;
+
+/** XE_SYSCTRL_APP_RESP_VALID - app_id is recognized by System Controller firmware */
+#define XE_SYSCTRL_APP_RESP_VALID		BIT(0)
+/** XE_SYSCTRL_APP_RESP_BOOTED - application has completed its boot sequence */
+#define XE_SYSCTRL_APP_RESP_BOOTED		BIT(1)
+/** XE_SYSCTRL_APP_RESP_INITIALIZED - application has completed all post-boot initialization */
+#define XE_SYSCTRL_APP_RESP_INITIALIZED		BIT(2)
+
+/**
+ * enum xe_sysctrl_fw_status - System Controller firmware application lifecycle states
+ *
+ * @XE_SYSCTRL_FIRMWARE_APP_INVALID: app_id is not recognized by firmware
+ * @XE_SYSCTRL_FIRMWARE_APP_NOT_LOADED: application is known but has not yet booted
+ * @XE_SYSCTRL_FIRMWARE_APP_BOOTED: boot sequence completed, post-boot init pending
+ * @XE_SYSCTRL_FIRMWARE_APP_INITIALIZED: application fully operational
+ * @XE_SYSCTRL_FIRMWARE_APP_NOTSUPP: System Controller not available on this device
+ * @XE_SYSCTRL_FIRMWARE_COMM_FAILURE: communication with System Controller firmware failed
+ */
+enum xe_sysctrl_fw_status {
+	XE_SYSCTRL_FIRMWARE_APP_INVALID,
+	XE_SYSCTRL_FIRMWARE_APP_NOT_LOADED,
+	XE_SYSCTRL_FIRMWARE_APP_BOOTED,
+	XE_SYSCTRL_FIRMWARE_APP_INITIALIZED,
+	XE_SYSCTRL_FIRMWARE_APP_NOTSUPP,
+	XE_SYSCTRL_FIRMWARE_COMM_FAILURE,
+};
+
+/**
+ * enum xe_sysctrl_app_id - Known System Controller application identifiers
+ *
+ * @XE_SYSCTRL_APP_OCODE: oCode application (firmware ID 12)
+ * @XE_SYSCTRL_APP_DIAG: diag application (firmware ID 13)
+ */
+enum xe_sysctrl_app_id {
+	XE_SYSCTRL_APP_OCODE	= 0x0C,
+	XE_SYSCTRL_APP_DIAG	= 0x0D,
+};
+
 /**
  * struct xe_sysctrl_mailbox_command - System Controller mailbox command
  */
-- 
2.43.0

[PATCH v2 2/2] drm/xe/sysctrl: Add fwctl support for System Controller

[Anoop, Vijay]

From: Anoop Vijay <anoop.c.vijay@intel.com>

Add fwctl support for Xe System Controller (sysctrl), a
firmware-managed entity that provides platform-level control and
coordination on Intel Xe3p discrete GPUs.

Register a XE_SYSCTRL device to allow userspace to query sysctrl
capabilities and issue RPCs through /dev/fwctl/fwctlN. Initial
RPCs support ECC status queries and RAS error injection.

Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
---
v2: (Rodrigo)
- Rename FWCTL_DEVICE_TYPE_XE to FWCTL_DEVICE_TYPE_XE_SYSCTRL, one type
  per firmware instead of a shared Xe-wide type
- Rename xe.h to xe_sysctrl.h to match
- Squash uapi and type definitions into a single patch
- Replace validate_scope() with explicit per-op scope/capability checks
  in xe_sysctrl_fwctl_rpc()
---
 Documentation/userspace-api/fwctl/index.rst   |   1 +
 .../userspace-api/fwctl/xe_sysctrl.rst        | 120 +++++++++
 drivers/gpu/drm/xe/Kconfig                    |   1 +
 drivers/gpu/drm/xe/Makefile                   |   1 +
 drivers/gpu/drm/xe/xe_device.c                |   5 +
 drivers/gpu/drm/xe/xe_sysctrl_fwctl.c         | 251 ++++++++++++++++++
 drivers/gpu/drm/xe/xe_sysctrl_fwctl.h         |  13 +
 drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h |  86 ++++++
 include/uapi/fwctl/fwctl.h                    |   1 +
 include/uapi/fwctl/xe_sysctrl.h               | 117 ++++++++
 10 files changed, 596 insertions(+)
 create mode 100644 Documentation/userspace-api/fwctl/xe_sysctrl.rst
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_fwctl.c
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_fwctl.h
 create mode 100644 include/uapi/fwctl/xe_sysctrl.h

diff --git a/Documentation/userspace-api/fwctl/index.rst b/Documentation/userspace-api/fwctl/index.rst
index 8062f7629654..f6fca11e6aac 100644
--- a/Documentation/userspace-api/fwctl/index.rst
+++ b/Documentation/userspace-api/fwctl/index.rst
@@ -13,3 +13,4 @@ to securely construct and execute RPCs inside device firmware.
    bnxt_fwctl
    fwctl-cxl
    pds_fwctl
+   xe_sysctrl
diff --git a/Documentation/userspace-api/fwctl/xe_sysctrl.rst b/Documentation/userspace-api/fwctl/xe_sysctrl.rst
new file mode 100644
index 000000000000..6dfc9e70b683
--- /dev/null
+++ b/Documentation/userspace-api/fwctl/xe_sysctrl.rst
@@ -0,0 +1,120 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=======================
+fwctl xe_sysctrl driver
+=======================
+
+:Author: Intel Corporation
+
+Overview
+========
+
+The Xe System Controller (sysctrl) firmware exposes a fwctl service that
+the xe driver registers as a ``FWCTL_DEVICE_TYPE_XE_SYSCTRL`` device.
+Userspace opens the resulting ``/dev/fwctl/fwctlN`` node to query ECC
+status and RAS error injection capabilities and to issue RAS error
+injection requests to the sysctrl firmware.
+
+xe_sysctrl User API
+====================
+
+.. kernel-doc:: include/uapi/fwctl/xe_sysctrl.h
+
+1. Driver info query
+---------------------
+
+The application issues ``FWCTL_INFO`` to retrieve a
+``struct fwctl_info_xe_sysctrl`` and inspect ``uctx_caps`` to determine
+which of the ``FWCTL_XE_SYSCTRL_CAP_*`` capabilities are available on this
+platform and in this security context.
+
+2. Send RPC requests
+---------------------
+
+Each RPC uses a single ``struct fwctl_rpc_xe_sysctrl`` as both the
+``FWCTL_RPC`` ``in`` and ``out`` buffer; the driver fills in ``data`` in
+place. ``op`` selects one of the ``enum fwctl_xe_sysctrl_op`` operations.
+The kernel rejects the request if the scope of the ``FWCTL_RPC`` call is
+lower than the minimum required by the requested ``op``, as documented above.
+
+Code example of querying ECC status
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. code-block:: c
+
+        static int xe_sysctrl_get_ecc(int fd, __u32 *supported, __u32 *enabled)
+        {
+                struct fwctl_rpc_xe_sysctrl sysctrl_rpc = {
+                        .op = FWCTL_XE_SYSCTRL_OP_ECC_STATUS_GET,
+                };
+                struct fwctl_rpc rpc = {
+                        .size = sizeof(rpc),
+                        .scope = FWCTL_RPC_CONFIGURATION,
+                        .in_len = sizeof(sysctrl_rpc),
+                        .out_len = sizeof(sysctrl_rpc),
+                        .in = (__aligned_u64)&sysctrl_rpc,
+                        .out = (__aligned_u64)&sysctrl_rpc,
+                };
+                int ret;
+
+                ret = ioctl(fd, FWCTL_RPC, &rpc);
+                if (ret)
+                        return ret;
+
+                *supported = sysctrl_rpc.data[0];
+                *enabled = sysctrl_rpc.data[1];
+                return 0;
+        }
+
+Code example of querying RAS injection capabilities and injecting an error
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. code-block:: c
+
+        static int xe_sysctrl_get_ras_caps(int fd, __u32 *capability_mask, __u32 *flags)
+        {
+                struct fwctl_rpc_xe_sysctrl sysctrl_rpc = {
+                        .op = FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS,
+                };
+                struct fwctl_rpc rpc = {
+                        .size = sizeof(rpc),
+                        .scope = FWCTL_RPC_CONFIGURATION,
+                        .in_len = sizeof(sysctrl_rpc),
+                        .out_len = sizeof(sysctrl_rpc),
+                        .in = (__aligned_u64)&sysctrl_rpc,
+                        .out = (__aligned_u64)&sysctrl_rpc,
+                };
+                int ret;
+
+                ret = ioctl(fd, FWCTL_RPC, &rpc);
+                if (ret)
+                        return ret;
+
+                *capability_mask = sysctrl_rpc.data[0];
+                *flags = sysctrl_rpc.data[1];
+                return 0;
+        }
+
+        static int xe_sysctrl_ras_inject(int fd, __u32 error_inj)
+        {
+                struct fwctl_rpc_xe_sysctrl sysctrl_rpc = {
+                        .op = FWCTL_XE_SYSCTRL_OP_RAS_INJECT,
+                        .data[0] = error_inj,
+                };
+                struct fwctl_rpc rpc = {
+                        .size = sizeof(rpc),
+                        .scope = FWCTL_RPC_DEBUG_WRITE,
+                        .in_len = sizeof(sysctrl_rpc),
+                        .out_len = sizeof(sysctrl_rpc),
+                        .in = (__aligned_u64)&sysctrl_rpc,
+                        .out = (__aligned_u64)&sysctrl_rpc,
+                };
+
+                /*
+                 * Callers should confirm error_inj is set in capability_mask,
+                 * and that flags allows injection (FWCTL_XE_SYSCTRL_RAS_INJ_ALLOWED),
+                 * as returned by xe_sysctrl_get_ras_caps() above, before injecting.
+                 */
+                return ioctl(fd, FWCTL_RPC, &rpc);
+        }
+
diff --git a/drivers/gpu/drm/xe/Kconfig b/drivers/gpu/drm/xe/Kconfig
index 4d7dcaff2b91..a472cb52dded 100644
--- a/drivers/gpu/drm/xe/Kconfig
+++ b/drivers/gpu/drm/xe/Kconfig
@@ -25,6 +25,7 @@ config DRM_XE
 	select DRM_MIPI_DSI
 	select RELAY
 	select IRQ_WORK
+	select FWCTL
 	# xe depends on ACPI_VIDEO when ACPI is enabled
 	# but for select to work, need to select ACPI_VIDEO's dependencies, ick
 	select BACKLIGHT_CLASS_DEVICE if ACPI
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 44ed055439d4..6560185c0ca7 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -128,6 +128,7 @@ xe-y += xe_bb.o \
 	xe_sync.o \
 	xe_sysctrl.o \
 	xe_sysctrl_event.o \
+	xe_sysctrl_fwctl.o \
 	xe_sysctrl_mailbox.o \
 	xe_tile.o \
 	xe_tile_sysfs.o \
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index d25d02b24898..dc7df793d4b9 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -68,6 +68,7 @@
 #include "xe_sriov.h"
 #include "xe_svm.h"
 #include "xe_sysctrl.h"
+#include "xe_sysctrl_fwctl.h"
 #include "xe_tile.h"
 #include "xe_ttm_stolen_mgr.h"
 #include "xe_ttm_sys_mgr.h"
@@ -1028,6 +1029,10 @@ int xe_device_probe(struct xe_device *xe)
 	if (err)
 		return err;
 
+	err = xe_sysctrl_fwctl_init(xe);
+	if (err)
+		return err;
+
 	xe_ras_init(xe);
 
 	/*
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_fwctl.c b/drivers/gpu/drm/xe/xe_sysctrl_fwctl.c
new file mode 100644
index 000000000000..27a40efa0787
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_fwctl.c
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include <linux/errno.h>
+#include <linux/fwctl.h>
+#include <linux/slab.h>
+
+#include <uapi/fwctl/xe_sysctrl.h>
+
+#include "xe_device.h"
+#include "xe_pm.h"
+#include "xe_printk.h"
+#include "xe_sysctrl.h"
+#include "xe_sysctrl_fwctl.h"
+#include "xe_sysctrl_mailbox.h"
+#include "xe_sysctrl_mailbox_types.h"
+
+struct xe_sysctrl_fwctl_dev {
+	struct fwctl_device fwctl;
+	struct xe_device *xe;
+};
+
+DEFINE_FREE(xe_sysctrl_fwctl, struct xe_sysctrl_fwctl_dev *, if (_T) fwctl_put(&_T->fwctl))
+
+struct xe_sysctrl_fwctl_uctx {
+	struct fwctl_uctx uctx;
+	u32 uctx_caps;
+};
+
+static int xe_sysctrl_fwctl_uctx_open(struct fwctl_uctx *uctx)
+{
+	struct xe_sysctrl_fwctl_dev *fwctl_dev =
+		container_of(uctx->fwctl, struct xe_sysctrl_fwctl_dev, fwctl);
+	struct xe_sysctrl_fwctl_uctx *sc_uctx =
+		container_of(uctx, struct xe_sysctrl_fwctl_uctx, uctx);
+	struct xe_device *xe = fwctl_dev->xe;
+
+	xe_pm_runtime_get(xe);
+
+	sc_uctx->uctx_caps = FWCTL_XE_SYSCTRL_CAP_ECC;
+	if (xe_sysctrl_is_diag_fw_ready(xe))
+		sc_uctx->uctx_caps |= FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT;
+
+	return 0;
+}
+
+static void xe_sysctrl_fwctl_uctx_close(struct fwctl_uctx *uctx)
+{
+	struct xe_sysctrl_fwctl_dev *fwctl_dev =
+		container_of(uctx->fwctl, struct xe_sysctrl_fwctl_dev, fwctl);
+
+	xe_pm_runtime_put(fwctl_dev->xe);
+}
+
+static void *xe_sysctrl_fwctl_info(struct fwctl_uctx *uctx, size_t *length)
+{
+	struct xe_sysctrl_fwctl_uctx *sc_uctx =
+		container_of(uctx, struct xe_sysctrl_fwctl_uctx, uctx);
+	struct fwctl_info_xe_sysctrl *info;
+
+	info = kzalloc_obj(*info);
+	if (!info)
+		return ERR_PTR(-ENOMEM);
+
+	info->uctx_caps = sc_uctx->uctx_caps;
+
+	*length = sizeof(*info);
+	return info;
+}
+
+static int sysctrl_rpc_ecc_status_get(struct xe_device *xe,
+				      struct fwctl_rpc_xe_sysctrl *rpc)
+{
+	struct xe_sysctrl_feature_cap_resp resp = {};
+	struct xe_sysctrl_mailbox_command cmd = {0};
+	size_t out_len = 0;
+	int ret;
+
+	xe_sysctrl_create_command(&cmd, XE_SYSCTRL_GROUP_GFSP_RUNTIME,
+				  XE_SYSCTRL_CMD_GET_FEATURE_CAPABILITY_STATE_INFO,
+				  NULL, 0, &resp, sizeof(resp));
+
+	ret = xe_sysctrl_send_command(&xe->sc, &cmd, &out_len);
+	if (ret)
+		return ret;
+
+	if (out_len < 2 * sizeof(u32)) {
+		xe_err(xe, "sysctrl fwctl: ECC status response too short (%zu B)\n",
+		       out_len);
+		return -EIO;
+	}
+
+	rpc->data[0] = resp.supported_features & XE_SYSCTRL_FEATURE_ECC ? 1 : 0;
+	rpc->data[1] = resp.enabled_features & XE_SYSCTRL_FEATURE_ECC ? 1 : 0;
+	return 0;
+}
+
+static int sysctrl_rpc_ras_get_caps(struct xe_device *xe,
+				    struct fwctl_rpc_xe_sysctrl *rpc)
+{
+	struct xe_sysctrl_ras_err_inj_cap_resp resp = {};
+	struct xe_sysctrl_mailbox_command cmd = {0};
+	size_t out_len = 0;
+	int ret;
+
+	xe_sysctrl_create_command(&cmd, XE_SYSCTRL_GROUP_DIAG,
+				  XE_SYSCTRL_CMD_RAS_ERR_INJ_CAPABILITY,
+				  NULL, 0, &resp, sizeof(resp));
+
+	ret = xe_sysctrl_send_command(&xe->sc, &cmd, &out_len);
+	if (ret)
+		return ret;
+
+	rpc->data[0] = resp.capability_mask;
+	rpc->data[1] = resp.flags;
+	return 0;
+}
+
+static int sysctrl_rpc_ras_inject(struct xe_device *xe,
+				  struct fwctl_rpc_xe_sysctrl *rpc)
+{
+	struct xe_sysctrl_ras_err_inj_req req = {
+		.error_inj	   = rpc->data[0],
+		.additional_params = rpc->data[1],
+	};
+	struct xe_sysctrl_mailbox_command cmd = {0};
+	size_t out_len = 0;
+
+	xe_sysctrl_create_command(&cmd, XE_SYSCTRL_GROUP_DIAG,
+				  XE_SYSCTRL_CMD_RAS_ERR_INJECT,
+				  &req, sizeof(req), NULL, 0);
+
+	return xe_sysctrl_send_command(&xe->sc, &cmd, &out_len);
+}
+
+static void *xe_sysctrl_fwctl_rpc(struct fwctl_uctx *uctx,
+				  enum fwctl_rpc_scope scope,
+				  void *rpc_in, size_t in_len,
+				  size_t *out_len)
+{
+	struct xe_sysctrl_fwctl_dev *fwctl_dev =
+		container_of(uctx->fwctl, struct xe_sysctrl_fwctl_dev, fwctl);
+	struct xe_sysctrl_fwctl_uctx *sc_uctx =
+		container_of(uctx, struct xe_sysctrl_fwctl_uctx, uctx);
+	struct xe_device *xe = fwctl_dev->xe;
+	struct fwctl_rpc_xe_sysctrl *rpc;
+	int ret;
+
+	if (in_len != sizeof(*rpc) || *out_len < sizeof(*rpc))
+		return ERR_PTR(-EMSGSIZE);
+
+	rpc = rpc_in;
+
+	if (rpc->flags)
+		return ERR_PTR(-EINVAL);
+
+	switch (rpc->op) {
+	case FWCTL_XE_SYSCTRL_OP_ECC_STATUS_GET:
+		if (!(sc_uctx->uctx_caps & FWCTL_XE_SYSCTRL_CAP_ECC))
+			return ERR_PTR(-EPERM);
+		if (scope < FWCTL_RPC_CONFIGURATION)
+			return ERR_PTR(-EBADMSG);
+		ret = sysctrl_rpc_ecc_status_get(xe, rpc);
+		if (ret)
+			return ERR_PTR(ret);
+		break;
+
+	case FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS:
+		if (!(sc_uctx->uctx_caps & FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT))
+			return ERR_PTR(-EPERM);
+		if (scope < FWCTL_RPC_CONFIGURATION)
+			return ERR_PTR(-EBADMSG);
+		ret = sysctrl_rpc_ras_get_caps(xe, rpc);
+		if (ret)
+			return ERR_PTR(ret);
+		break;
+
+	case FWCTL_XE_SYSCTRL_OP_RAS_INJECT:
+		if (!(sc_uctx->uctx_caps & FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT))
+			return ERR_PTR(-EPERM);
+		if (scope < FWCTL_RPC_DEBUG_WRITE)
+			return ERR_PTR(-EBADMSG);
+		ret = sysctrl_rpc_ras_inject(xe, rpc);
+		if (ret)
+			return ERR_PTR(ret);
+		break;
+
+	default:
+		return ERR_PTR(-EBADMSG);
+	}
+
+	*out_len = sizeof(*rpc);
+	return rpc_in;
+}
+
+static const struct fwctl_ops xe_sysctrl_fwctl_ops = {
+	.device_type = FWCTL_DEVICE_TYPE_XE_SYSCTRL,
+	.uctx_size = sizeof(struct xe_sysctrl_fwctl_uctx),
+	.open_uctx = xe_sysctrl_fwctl_uctx_open,
+	.close_uctx = xe_sysctrl_fwctl_uctx_close,
+	.info = xe_sysctrl_fwctl_info,
+	.fw_rpc = xe_sysctrl_fwctl_rpc,
+};
+
+static void xe_sysctrl_fwctl_fini(void *arg)
+{
+	struct fwctl_device *fwctl = arg;
+
+	fwctl_unregister(fwctl);
+	fwctl_put(fwctl);
+}
+
+/**
+ * xe_sysctrl_fwctl_init() - Initialize fwctl interface for System Controller
+ * @xe: xe device instance
+ *
+ * Registers a fwctl device that exposes System Controller debug and
+ * diagnostic functionality to userspace, on platforms where System
+ * Controller is supported.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int xe_sysctrl_fwctl_init(struct xe_device *xe)
+{
+	struct xe_sysctrl_fwctl_dev *fwctl_dev __free(xe_sysctrl_fwctl) =
+		fwctl_alloc_device(xe->drm.dev, &xe_sysctrl_fwctl_ops,
+				   struct xe_sysctrl_fwctl_dev, fwctl);
+	int err;
+
+	if (!xe->info.has_soc_remapper_sysctrl)
+		return 0;
+
+	if (!xe->info.has_sysctrl)
+		return 0;
+
+	if (!fwctl_dev)
+		return -ENOMEM;
+
+	fwctl_dev->xe = xe;
+
+	err = fwctl_register(&fwctl_dev->fwctl);
+	if (err)
+		return err;
+
+	return devm_add_action_or_reset(xe->drm.dev, xe_sysctrl_fwctl_fini,
+					&no_free_ptr(fwctl_dev)->fwctl);
+}
+
+MODULE_IMPORT_NS("FWCTL");
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_fwctl.h b/drivers/gpu/drm/xe/xe_sysctrl_fwctl.h
new file mode 100644
index 000000000000..730f31e0d697
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_fwctl.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_FWCTL_H_
+#define _XE_SYSCTRL_FWCTL_H_
+
+struct xe_device;
+
+int xe_sysctrl_fwctl_init(struct xe_device *xe);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
index b507e1553cbb..7f39fd1a418a 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
@@ -14,10 +14,14 @@
  * enum xe_sysctrl_group - System Controller command groups
  *
  * @XE_SYSCTRL_GROUP_GFSP: GFSP group
+ * @XE_SYSCTRL_GROUP_DIAG: Diag group
+ * @XE_SYSCTRL_GROUP_GFSP_RUNTIME: GFSP runtime group
  * @XE_SYSCTRL_GROUP_CORE: Core group
  */
 enum xe_sysctrl_group {
 	XE_SYSCTRL_GROUP_GFSP			= 0x01,
+	XE_SYSCTRL_GROUP_DIAG			= 0x02,
+	XE_SYSCTRL_GROUP_GFSP_RUNTIME		= 0x31,
 	XE_SYSCTRL_GROUP_CORE			= 0xFF,
 };
 
@@ -103,6 +107,88 @@ enum xe_sysctrl_app_id {
 	XE_SYSCTRL_APP_DIAG	= 0x0D,
 };
 
+/**
+ * enum xe_sysctrl_diag_cmd - Commands supported by DIAG group
+ *
+ * @XE_SYSCTRL_CMD_RAS_ERR_INJ_CAPABILITY: Query supported RAS injection types
+ * @XE_SYSCTRL_CMD_RAS_ERR_INJECT: Inject a RAS error into an IP block
+ */
+enum xe_sysctrl_diag_cmd {
+	XE_SYSCTRL_CMD_RAS_ERR_INJ_CAPABILITY	= 0x01,
+	XE_SYSCTRL_CMD_RAS_ERR_INJECT		= 0x02,
+};
+
+/**
+ * struct xe_sysctrl_ras_err_inj_cap_resp - RAS_ERR_INJ_CAPABILITY response payload
+ *
+ * Response payload for XE_SYSCTRL_CMD_RAS_ERR_INJ_CAPABILITY.  The mailbox
+ * layer strips the application message header before writing to this buffer.
+ *
+ * @capability_mask: OR of firmware-defined capability values indicating which
+ *                   injection classes are supported on this platform (see
+ *                   enum fwctl_xe_sysctrl_ras_inj_cap in
+ *                   include/uapi/fwctl/xe_sysctrl.h for bit definitions)
+ * @flags:           Bitmask; bit FWCTL_XE_SYSCTRL_RAS_INJ_ALLOWED (see
+ *                   include/uapi/fwctl/xe_sysctrl.h) indicates whether RAS
+ *                   error injection is currently allowed by hardware
+ *                   security policy.
+ * @reserved:        Must be zero
+ */
+struct xe_sysctrl_ras_err_inj_cap_resp {
+	u32 capability_mask;
+	u32 flags;
+	u32 reserved[2];
+} __packed;
+
+/**
+ * struct xe_sysctrl_ras_err_inj_req - RAS_ERR_INJECT request payload
+ *
+ * Request payload for XE_SYSCTRL_CMD_RAS_ERR_INJECT.  The mailbox layer
+ * prepends the application message header before sending.
+ *
+ * @error_inj:    One of the enum fwctl_xe_sysctrl_ras_inj_cap bit values
+ *                (include/uapi/fwctl/xe_sysctrl.h), selecting the class of
+ *                error to inject.
+ * @additional_params: Reserved for future use; must be 0 for most injection
+ *                    types
+ */
+struct xe_sysctrl_ras_err_inj_req {
+	u32 error_inj;
+	u32 additional_params;
+} __packed;
+
+/**
+ * enum xe_sysctrl_gfsp_runtime_cmd - Commands for the GFSP runtime group (0x31)
+ *
+ * @XE_SYSCTRL_CMD_GET_FEATURE_CAPABILITY_STATE_INFO: Read ECC feature state.
+ *	No input payload.  Response: struct xe_sysctrl_feature_cap_resp.
+ */
+enum xe_sysctrl_gfsp_runtime_cmd {
+	XE_SYSCTRL_CMD_GET_FEATURE_CAPABILITY_STATE_INFO	= 0x10,
+};
+
+/** XE_SYSCTRL_FEATURE_ECC - ECC feature bit in FSP runtime capability bitmasks */
+#define XE_SYSCTRL_FEATURE_ECC	BIT(0)
+
+/**
+ * struct xe_sysctrl_feature_cap_resp - ECC feature state
+ *
+ * Response layout for XE_SYSCTRL_CMD_GET_FEATURE_CAPABILITY_STATE_INFO.
+ *
+ * @supported_features: Features supported by the product
+ * @enabled_features: Features currently enabled
+ * @configurable_features: Features modifiable by software
+ * @pending_features: Feature state pending after next reboot
+ * @default_features: Default feature state from build configuration
+ */
+struct xe_sysctrl_feature_cap_resp {
+	u32 supported_features;
+	u32 enabled_features;
+	u32 configurable_features;
+	u32 pending_features;
+	u32 default_features;
+} __packed;
+
 /**
  * struct xe_sysctrl_mailbox_command - System Controller mailbox command
  */
diff --git a/include/uapi/fwctl/fwctl.h b/include/uapi/fwctl/fwctl.h
index 2d6d4049c205..34901d36cd51 100644
--- a/include/uapi/fwctl/fwctl.h
+++ b/include/uapi/fwctl/fwctl.h
@@ -46,6 +46,7 @@ enum fwctl_device_type {
 	FWCTL_DEVICE_TYPE_CXL = 2,
 	FWCTL_DEVICE_TYPE_BNXT = 3,
 	FWCTL_DEVICE_TYPE_PDS = 4,
+	FWCTL_DEVICE_TYPE_XE_SYSCTRL = 5,
 };
 
 /**
diff --git a/include/uapi/fwctl/xe_sysctrl.h b/include/uapi/fwctl/xe_sysctrl.h
new file mode 100644
index 000000000000..a4d117d906e3
--- /dev/null
+++ b/include/uapi/fwctl/xe_sysctrl.h
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/* Copyright © 2026 Intel Corporation */
+#ifndef _UAPI_FWCTL_XE_SYSCTRL_H_
+#define _UAPI_FWCTL_XE_SYSCTRL_H_
+
+#include <linux/bits.h>
+#include <linux/types.h>
+
+/**
+ * enum fwctl_xe_sysctrl_uctx_caps - capability flags in fwctl_info_xe_sysctrl.uctx_caps
+ *
+ * @FWCTL_XE_SYSCTRL_CAP_ECC: ECC status query is supported on this platform
+ * @FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT: RAS error injection is supported;
+ *      requires diag firmware to be loaded and ready
+ */
+enum fwctl_xe_sysctrl_uctx_caps {
+	FWCTL_XE_SYSCTRL_CAP_ECC		= (1U << 0),
+	FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT	= (1U << 1),
+};
+
+/**
+ * struct fwctl_info_xe_sysctrl - device data returned by FWCTL_INFO
+ * @uctx_caps: Bitmask of available capabilities (see %fwctl_xe_sysctrl_uctx_caps)
+ * @rsvd: Reserved, must be zero
+ */
+struct fwctl_info_xe_sysctrl {
+	__u32 uctx_caps;
+	__u32 rsvd[7];
+};
+
+/**
+ * enum fwctl_xe_sysctrl_ras_inj_cap - RAS error injection capability bits
+ *
+ * Used both in the @capability_mask output of %FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS
+ * and as the @error_inj input of %FWCTL_XE_SYSCTRL_OP_RAS_INJECT. Userspace
+ * must confirm a bit is set in @capability_mask before injecting that class.
+ *
+ * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_COMPUTE_CORR: Compute block correctable error
+ * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_COMPUTE_UCORR: Compute block uncorrectable error
+ * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_MEMORY_UCORR: Memory subsystem uncorrectable error
+ * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_FABRIC_UCORR: Fabric interconnect uncorrectable error
+ * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PCIE_CORR: PCIe subsystem correctable error
+ * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PCIE_UCORR: PCIe subsystem uncorrectable error
+ * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PLATFORM_UCORR: Platform-level uncorrectable error
+ */
+enum fwctl_xe_sysctrl_ras_inj_cap {
+	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_COMPUTE_CORR	= 0x0001U,
+	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_COMPUTE_UCORR	= 0x0002U,
+	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_MEMORY_UCORR	= 0x0004U,
+	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_FABRIC_UCORR	= 0x0008U,
+	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PCIE_CORR		= 0x0010U,
+	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PCIE_UCORR		= 0x0020U,
+	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PLATFORM_UCORR	= 0x0040U,
+};
+
+/* FWCTL_XE_SYSCTRL_RAS_INJ_ALLOWED - bit in the RAS_GET_CAPS flags field
+ * indicating RAS error injection is currently allowed by hardware security
+ * policy.
+ */
+#define FWCTL_XE_SYSCTRL_RAS_INJ_ALLOWED	(1U << 0)
+
+/**
+ * enum fwctl_xe_sysctrl_op - RPC operation codes for xe_sysctrl fwctl
+ *
+ * @FWCTL_XE_SYSCTRL_OP_ECC_STATUS_GET: Read ECC feature state from GFSP firmware
+ *	(GFSP runtime group, GET_FEATURE_CAPABILITY_STATE_INFO, BIT(0) = ECC).
+ *	Requires: %FWCTL_XE_SYSCTRL_CAP_ECC in uctx_caps.
+ *	Scope: %FWCTL_RPC_CONFIGURATION.
+ *	in:  op, flags=0, data[0..13] ignored.
+ *	out: data[0] = 1 if ECC is supported by this product, 0 otherwise.
+ *	     data[1] = 1 if ECC is currently enabled, 0 otherwise.
+ *
+ * @FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS: Query RAS error injection capability from
+ *	diag firmware (DIAG group, RAS_ERR_INJ_CAPABILITY command).
+ *	Requires: %FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT in uctx_caps.
+ *	Scope: %FWCTL_RPC_CONFIGURATION.
+ *	in:  op, flags=0, data[0..13] ignored.
+ *	out: data[0] = capability_mask, an OR of %fwctl_xe_sysctrl_ras_inj_cap
+ *	                bits indicating which injection classes are supported,
+ *	     data[1] = flags; bit %FWCTL_XE_SYSCTRL_RAS_INJ_ALLOWED indicates
+ *	                whether RAS error injection is currently allowed by
+ *	                hardware security policy, other bits are reserved for
+ *	                future use.
+ *
+ * @FWCTL_XE_SYSCTRL_OP_RAS_INJECT: Inject a RAS error via diag firmware
+ *	(DIAG group, RAS_ERR_INJECT command).
+ *	Requires: %FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT in uctx_caps.
+ *	Scope: %FWCTL_RPC_DEBUG_WRITE.
+ *	in:  data[0] = error_inj, one of the %fwctl_xe_sysctrl_ras_inj_cap
+ *	                bit values. Userspace must confirm this bit is set in
+ *	                the capability_mask returned by
+ *	                %FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS (and that its flags
+ *	                field currently allows injection) before issuing this
+ *	                request; behavior for an unsupported value is
+ *	                firmware-defined,
+ *	     data[1] = additional_params (reserved; 0 for most injection types).
+ *	out: no additional output data (success indicated by ioctl return code).
+ */
+enum fwctl_xe_sysctrl_op {
+	FWCTL_XE_SYSCTRL_OP_ECC_STATUS_GET	= 1,
+	FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS	= 2,
+	FWCTL_XE_SYSCTRL_OP_RAS_INJECT		= 3,
+};
+
+/**
+ * struct fwctl_rpc_xe_sysctrl - RPC request/response envelope
+ * @op: Operation code (see %fwctl_xe_sysctrl_op)
+ * @flags: Must be 0
+ * @data: Operation-specific payload (see %fwctl_xe_sysctrl_op for layout)
+ */
+struct fwctl_rpc_xe_sysctrl {
+	__u32 op;
+	__u32 flags;
+	__u32 data[14];
+};
+
+#endif
-- 
2.43.0

✗ CI.checkpatch: warning for drm/xe/sysctrl: Add fwctl support for System Controller

[Patchwork]

== Series Details ==

Series: drm/xe/sysctrl: Add fwctl support for System Controller
URL   : https://patchwork.freedesktop.org/series/171728/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
061140b9bc586ae7f40abc1249c97e1cc72d1b9d
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 2fd72f0df0d57872501470d25ac4019f3c401397
Author: Anoop Vijay <anoop.c.vijay@intel.com>
Date:   Thu Aug 6 05:03:12 2026 -0700

    drm/xe/sysctrl: Add fwctl support for System Controller
    
    Add fwctl support for Xe System Controller (sysctrl), a
    firmware-managed entity that provides platform-level control and
    coordination on Intel Xe3p discrete GPUs.
    
    Register a XE_SYSCTRL device to allow userspace to query sysctrl
    capabilities and issue RPCs through /dev/fwctl/fwctlN. Initial
    RPCs support ECC status queries and RAS error injection.
    
    Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
+ /mt/dim checkpatch 0c5c2db8c2dc01242496cc2ad63ca8ff787d6a40 drm-intel
0d55485a08bb drm/xe/sysctrl: Add System Controller get application status
2fd72f0df0d5 drm/xe/sysctrl: Add fwctl support for System Controller
-:26: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#26: 
new file mode 100644

-:228: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (0, 0)
#228: FILE: drivers/gpu/drm/xe/xe_sysctrl_fwctl.c:25:
+DEFINE_FREE(xe_sysctrl_fwctl, struct xe_sysctrl_fwctl_dev *, if (_T) fwctl_put(&_T->fwctl))
[...]
+struct xe_sysctrl_fwctl_uctx {

total: 0 errors, 2 warnings, 0 checks, 645 lines checked

✓ CI.KUnit: success for drm/xe/sysctrl: Add fwctl support for System Controller

[Patchwork]

== Series Details ==

Series: drm/xe/sysctrl: Add fwctl support for System Controller
URL   : https://patchwork.freedesktop.org/series/171728/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[12:09:37] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:09:42] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:10:14] Starting KUnit Kernel (1/1)...
[12:10:14] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:10:14] ================== guc_buf (11 subtests) ===================
[12:10:14] [PASSED] test_smallest
[12:10:14] [PASSED] test_largest
[12:10:14] [PASSED] test_granular
[12:10:14] [PASSED] test_unique
[12:10:14] [PASSED] test_overlap
[12:10:14] [PASSED] test_reusable
[12:10:14] [PASSED] test_too_big
[12:10:14] [PASSED] test_flush
[12:10:14] [PASSED] test_lookup
[12:10:14] [PASSED] test_data
[12:10:14] [PASSED] test_class
[12:10:14] ===================== [PASSED] guc_buf =====================
[12:10:14] =================== guc_dbm (7 subtests) ===================
[12:10:14] [PASSED] test_empty
[12:10:14] [PASSED] test_default
[12:10:14] ======================== test_size  ========================
[12:10:14] [PASSED] 4
[12:10:14] [PASSED] 8
[12:10:14] [PASSED] 32
[12:10:14] [PASSED] 256
[12:10:14] ==================== [PASSED] test_size ====================
[12:10:14] ======================= test_reuse  ========================
[12:10:14] [PASSED] 4
[12:10:14] [PASSED] 8
[12:10:14] [PASSED] 32
[12:10:14] [PASSED] 256
[12:10:14] =================== [PASSED] test_reuse ====================
[12:10:14] =================== test_range_overlap  ====================
[12:10:14] [PASSED] 4
[12:10:14] [PASSED] 8
[12:10:14] [PASSED] 32
[12:10:14] [PASSED] 256
[12:10:14] =============== [PASSED] test_range_overlap ================
[12:10:14] =================== test_range_compact  ====================
[12:10:14] [PASSED] 4
[12:10:14] [PASSED] 8
[12:10:14] [PASSED] 32
[12:10:14] [PASSED] 256
[12:10:14] =============== [PASSED] test_range_compact ================
[12:10:14] ==================== test_range_spare  =====================
[12:10:14] [PASSED] 4
[12:10:14] [PASSED] 8
[12:10:14] [PASSED] 32
[12:10:14] [PASSED] 256
[12:10:14] ================ [PASSED] test_range_spare =================
[12:10:14] ===================== [PASSED] guc_dbm =====================
[12:10:14] =================== guc_idm (6 subtests) ===================
[12:10:14] [PASSED] bad_init
[12:10:14] [PASSED] no_init
[12:10:14] [PASSED] init_fini
[12:10:14] [PASSED] check_used
[12:10:14] [PASSED] check_quota
[12:10:14] [PASSED] check_all
[12:10:14] ===================== [PASSED] guc_idm =====================
[12:10:14] =============== guc_klv_helpers (9 subtests) ===============
[12:10:14] [PASSED] test_count
[12:10:14] [PASSED] test_encode_u32
[12:10:14] [PASSED] test_encode_u64
[12:10:14] [PASSED] test_encode_string
[12:10:14] [PASSED] test_encode_object_raw
[12:10:14] [PASSED] test_encode_object_klv
[12:10:14] [PASSED] test_encode_object_nested
[12:10:14] [PASSED] test_encode_object_basic
[12:10:14] [PASSED] test_print
[12:10:14] ================= [PASSED] guc_klv_helpers =================
[12:10:14] ================== no_relay (3 subtests) ===================
[12:10:14] [PASSED] xe_drops_guc2pf_if_not_ready
[12:10:14] [PASSED] xe_drops_guc2vf_if_not_ready
[12:10:14] [PASSED] xe_rejects_send_if_not_ready
[12:10:14] ==================== [PASSED] no_relay =====================
[12:10:14] ================== pf_relay (14 subtests) ==================
[12:10:14] [PASSED] pf_rejects_guc2pf_too_short
[12:10:14] [PASSED] pf_rejects_guc2pf_too_long
[12:10:14] [PASSED] pf_rejects_guc2pf_no_payload
[12:10:14] [PASSED] pf_fails_no_payload
[12:10:14] [PASSED] pf_fails_bad_origin
[12:10:14] [PASSED] pf_fails_bad_type
[12:10:14] [PASSED] pf_txn_reports_error
[12:10:14] [PASSED] pf_txn_sends_pf2guc
[12:10:14] [PASSED] pf_sends_pf2guc
[12:10:14] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[12:10:14] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[12:10:14] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[12:10:14] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[12:10:14] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[12:10:14] ==================== [PASSED] pf_relay =====================
[12:10:14] ================== vf_relay (3 subtests) ===================
[12:10:14] [PASSED] vf_rejects_guc2vf_too_short
[12:10:14] [PASSED] vf_rejects_guc2vf_too_long
[12:10:14] [PASSED] vf_rejects_guc2vf_no_payload
[12:10:14] ==================== [PASSED] vf_relay =====================
[12:10:14] ================ pf_gt_config (9 subtests) =================
[12:10:14] [PASSED] fair_contexts_1vf
[12:10:14] [PASSED] fair_doorbells_1vf
[12:10:14] [PASSED] fair_ggtt_1vf
[12:10:14] ====================== fair_vram_1vf  ======================
[12:10:14] [PASSED] 3.50 GiB
[12:10:14] [PASSED] 11.5 GiB
[12:10:14] [PASSED] 15.5 GiB
[12:10:14] [PASSED] 31.5 GiB
[12:10:14] [PASSED] 63.5 GiB
[12:10:14] [PASSED] 1.91 GiB
[12:10:14] ================== [PASSED] fair_vram_1vf ==================
[12:10:14] ================ fair_vram_1vf_admin_only  =================
[12:10:14] [PASSED] 3.50 GiB
[12:10:14] [PASSED] 11.5 GiB
[12:10:14] [PASSED] 15.5 GiB
[12:10:14] [PASSED] 31.5 GiB
[12:10:14] [PASSED] 63.5 GiB
[12:10:14] [PASSED] 1.91 GiB
[12:10:14] ============ [PASSED] fair_vram_1vf_admin_only =============
[12:10:14] ====================== fair_contexts  ======================
[12:10:14] [PASSED] 1 VF
[12:10:14] [PASSED] 2 VFs
[12:10:14] [PASSED] 3 VFs
[12:10:14] [PASSED] 4 VFs
[12:10:14] [PASSED] 5 VFs
[12:10:14] [PASSED] 6 VFs
[12:10:14] [PASSED] 7 VFs
[12:10:14] [PASSED] 8 VFs
[12:10:14] [PASSED] 9 VFs
[12:10:14] [PASSED] 10 VFs
[12:10:14] [PASSED] 11 VFs
[12:10:14] [PASSED] 12 VFs
[12:10:14] [PASSED] 13 VFs
[12:10:14] [PASSED] 14 VFs
[12:10:14] [PASSED] 15 VFs
[12:10:14] [PASSED] 16 VFs
[12:10:14] [PASSED] 17 VFs
[12:10:14] [PASSED] 18 VFs
[12:10:14] [PASSED] 19 VFs
[12:10:14] [PASSED] 20 VFs
[12:10:14] [PASSED] 21 VFs
[12:10:14] [PASSED] 22 VFs
[12:10:14] [PASSED] 23 VFs
[12:10:14] [PASSED] 24 VFs
[12:10:14] [PASSED] 25 VFs
[12:10:14] [PASSED] 26 VFs
[12:10:14] [PASSED] 27 VFs
[12:10:14] [PASSED] 28 VFs
[12:10:14] [PASSED] 29 VFs
[12:10:14] [PASSED] 30 VFs
[12:10:14] [PASSED] 31 VFs
[12:10:14] [PASSED] 32 VFs
[12:10:14] [PASSED] 33 VFs
[12:10:14] [PASSED] 34 VFs
[12:10:14] [PASSED] 35 VFs
[12:10:14] [PASSED] 36 VFs
[12:10:14] [PASSED] 37 VFs
[12:10:14] [PASSED] 38 VFs
[12:10:14] [PASSED] 39 VFs
[12:10:14] [PASSED] 40 VFs
[12:10:14] [PASSED] 41 VFs
[12:10:14] [PASSED] 42 VFs
[12:10:14] [PASSED] 43 VFs
[12:10:14] [PASSED] 44 VFs
[12:10:14] [PASSED] 45 VFs
[12:10:14] [PASSED] 46 VFs
[12:10:14] [PASSED] 47 VFs
[12:10:14] [PASSED] 48 VFs
[12:10:14] [PASSED] 49 VFs
[12:10:14] [PASSED] 50 VFs
[12:10:14] [PASSED] 51 VFs
[12:10:14] [PASSED] 52 VFs
[12:10:14] [PASSED] 53 VFs
[12:10:14] [PASSED] 54 VFs
[12:10:14] [PASSED] 55 VFs
[12:10:14] [PASSED] 56 VFs
[12:10:14] [PASSED] 57 VFs
[12:10:14] [PASSED] 58 VFs
[12:10:14] [PASSED] 59 VFs
[12:10:14] [PASSED] 60 VFs
[12:10:14] [PASSED] 61 VFs
[12:10:14] [PASSED] 62 VFs
[12:10:14] [PASSED] 63 VFs
[12:10:14] ================== [PASSED] fair_contexts ==================
[12:10:14] ===================== fair_doorbells  ======================
[12:10:14] [PASSED] 1 VF
[12:10:14] [PASSED] 2 VFs
[12:10:14] [PASSED] 3 VFs
[12:10:14] [PASSED] 4 VFs
[12:10:14] [PASSED] 5 VFs
[12:10:14] [PASSED] 6 VFs
[12:10:14] [PASSED] 7 VFs
[12:10:14] [PASSED] 8 VFs
[12:10:14] [PASSED] 9 VFs
[12:10:14] [PASSED] 10 VFs
[12:10:14] [PASSED] 11 VFs
[12:10:14] [PASSED] 12 VFs
[12:10:14] [PASSED] 13 VFs
[12:10:14] [PASSED] 14 VFs
[12:10:14] [PASSED] 15 VFs
[12:10:14] [PASSED] 16 VFs
[12:10:14] [PASSED] 17 VFs
[12:10:14] [PASSED] 18 VFs
[12:10:14] [PASSED] 19 VFs
[12:10:14] [PASSED] 20 VFs
[12:10:14] [PASSED] 21 VFs
[12:10:14] [PASSED] 22 VFs
[12:10:14] [PASSED] 23 VFs
[12:10:14] [PASSED] 24 VFs
[12:10:14] [PASSED] 25 VFs
[12:10:14] [PASSED] 26 VFs
[12:10:14] [PASSED] 27 VFs
[12:10:14] [PASSED] 28 VFs
[12:10:14] [PASSED] 29 VFs
[12:10:14] [PASSED] 30 VFs
[12:10:14] [PASSED] 31 VFs
[12:10:14] [PASSED] 32 VFs
[12:10:14] [PASSED] 33 VFs
[12:10:14] [PASSED] 34 VFs
[12:10:14] [PASSED] 35 VFs
[12:10:14] [PASSED] 36 VFs
[12:10:14] [PASSED] 37 VFs
[12:10:14] [PASSED] 38 VFs
[12:10:14] [PASSED] 39 VFs
[12:10:14] [PASSED] 40 VFs
[12:10:14] [PASSED] 41 VFs
[12:10:14] [PASSED] 42 VFs
[12:10:14] [PASSED] 43 VFs
[12:10:14] [PASSED] 44 VFs
[12:10:14] [PASSED] 45 VFs
[12:10:14] [PASSED] 46 VFs
[12:10:14] [PASSED] 47 VFs
[12:10:14] [PASSED] 48 VFs
[12:10:14] [PASSED] 49 VFs
[12:10:14] [PASSED] 50 VFs
[12:10:14] [PASSED] 51 VFs
[12:10:14] [PASSED] 52 VFs
[12:10:14] [PASSED] 53 VFs
[12:10:14] [PASSED] 54 VFs
[12:10:14] [PASSED] 55 VFs
[12:10:14] [PASSED] 56 VFs
[12:10:14] [PASSED] 57 VFs
[12:10:14] [PASSED] 58 VFs
[12:10:14] [PASSED] 59 VFs
[12:10:14] [PASSED] 60 VFs
[12:10:14] [PASSED] 61 VFs
[12:10:14] [PASSED] 62 VFs
[12:10:14] [PASSED] 63 VFs
[12:10:14] ================= [PASSED] fair_doorbells ==================
[12:10:14] ======================== fair_ggtt  ========================
[12:10:14] [PASSED] 1 VF
[12:10:14] [PASSED] 2 VFs
[12:10:14] [PASSED] 3 VFs
[12:10:14] [PASSED] 4 VFs
[12:10:14] [PASSED] 5 VFs
[12:10:14] [PASSED] 6 VFs
[12:10:14] [PASSED] 7 VFs
[12:10:14] [PASSED] 8 VFs
[12:10:14] [PASSED] 9 VFs
[12:10:14] [PASSED] 10 VFs
[12:10:14] [PASSED] 11 VFs
[12:10:14] [PASSED] 12 VFs
[12:10:14] [PASSED] 13 VFs
[12:10:14] [PASSED] 14 VFs
[12:10:14] [PASSED] 15 VFs
[12:10:14] [PASSED] 16 VFs
[12:10:14] [PASSED] 17 VFs
[12:10:14] [PASSED] 18 VFs
[12:10:14] [PASSED] 19 VFs
[12:10:14] [PASSED] 20 VFs
[12:10:14] [PASSED] 21 VFs
[12:10:14] [PASSED] 22 VFs
[12:10:14] [PASSED] 23 VFs
[12:10:14] [PASSED] 24 VFs
[12:10:14] [PASSED] 25 VFs
[12:10:14] [PASSED] 26 VFs
[12:10:14] [PASSED] 27 VFs
[12:10:14] [PASSED] 28 VFs
[12:10:14] [PASSED] 29 VFs
[12:10:14] [PASSED] 30 VFs
[12:10:14] [PASSED] 31 VFs
[12:10:14] [PASSED] 32 VFs
[12:10:14] [PASSED] 33 VFs
[12:10:14] [PASSED] 34 VFs
[12:10:14] [PASSED] 35 VFs
[12:10:14] [PASSED] 36 VFs
[12:10:14] [PASSED] 37 VFs
[12:10:14] [PASSED] 38 VFs
[12:10:14] [PASSED] 39 VFs
[12:10:14] [PASSED] 40 VFs
[12:10:14] [PASSED] 41 VFs
[12:10:14] [PASSED] 42 VFs
[12:10:14] [PASSED] 43 VFs
[12:10:14] [PASSED] 44 VFs
[12:10:14] [PASSED] 45 VFs
[12:10:14] [PASSED] 46 VFs
[12:10:14] [PASSED] 47 VFs
[12:10:14] [PASSED] 48 VFs
[12:10:14] [PASSED] 49 VFs
[12:10:14] [PASSED] 50 VFs
[12:10:14] [PASSED] 51 VFs
[12:10:14] [PASSED] 52 VFs
[12:10:14] [PASSED] 53 VFs
[12:10:14] [PASSED] 54 VFs
[12:10:14] [PASSED] 55 VFs
[12:10:14] [PASSED] 56 VFs
[12:10:14] [PASSED] 57 VFs
[12:10:14] [PASSED] 58 VFs
[12:10:14] [PASSED] 59 VFs
[12:10:14] [PASSED] 60 VFs
[12:10:14] [PASSED] 61 VFs
[12:10:14] [PASSED] 62 VFs
[12:10:14] [PASSED] 63 VFs
[12:10:14] ==================== [PASSED] fair_ggtt ====================
[12:10:14] ======================== fair_vram  ========================
[12:10:14] [PASSED] 1 VF
[12:10:14] [PASSED] 2 VFs
[12:10:14] [PASSED] 3 VFs
[12:10:14] [PASSED] 4 VFs
[12:10:14] [PASSED] 5 VFs
[12:10:14] [PASSED] 6 VFs
[12:10:14] [PASSED] 7 VFs
[12:10:14] [PASSED] 8 VFs
[12:10:14] [PASSED] 9 VFs
[12:10:14] [PASSED] 10 VFs
[12:10:14] [PASSED] 11 VFs
[12:10:14] [PASSED] 12 VFs
[12:10:14] [PASSED] 13 VFs
[12:10:14] [PASSED] 14 VFs
[12:10:14] [PASSED] 15 VFs
[12:10:14] [PASSED] 16 VFs
[12:10:14] [PASSED] 17 VFs
[12:10:14] [PASSED] 18 VFs
[12:10:14] [PASSED] 19 VFs
[12:10:14] [PASSED] 20 VFs
[12:10:14] [PASSED] 21 VFs
[12:10:14] [PASSED] 22 VFs
[12:10:14] [PASSED] 23 VFs
[12:10:14] [PASSED] 24 VFs
[12:10:14] [PASSED] 25 VFs
[12:10:14] [PASSED] 26 VFs
[12:10:14] [PASSED] 27 VFs
[12:10:14] [PASSED] 28 VFs
[12:10:14] [PASSED] 29 VFs
[12:10:14] [PASSED] 30 VFs
[12:10:14] [PASSED] 31 VFs
[12:10:14] [PASSED] 32 VFs
[12:10:14] [PASSED] 33 VFs
[12:10:14] [PASSED] 34 VFs
[12:10:14] [PASSED] 35 VFs
[12:10:14] [PASSED] 36 VFs
[12:10:14] [PASSED] 37 VFs
[12:10:14] [PASSED] 38 VFs
[12:10:14] [PASSED] 39 VFs
[12:10:14] [PASSED] 40 VFs
[12:10:14] [PASSED] 41 VFs
[12:10:14] [PASSED] 42 VFs
[12:10:14] [PASSED] 43 VFs
[12:10:14] [PASSED] 44 VFs
[12:10:14] [PASSED] 45 VFs
[12:10:14] [PASSED] 46 VFs
[12:10:14] [PASSED] 47 VFs
[12:10:14] [PASSED] 48 VFs
[12:10:14] [PASSED] 49 VFs
[12:10:14] [PASSED] 50 VFs
[12:10:14] [PASSED] 51 VFs
[12:10:14] [PASSED] 52 VFs
[12:10:14] [PASSED] 53 VFs
[12:10:14] [PASSED] 54 VFs
[12:10:14] [PASSED] 55 VFs
[12:10:14] [PASSED] 56 VFs
[12:10:14] [PASSED] 57 VFs
[12:10:14] [PASSED] 58 VFs
[12:10:14] [PASSED] 59 VFs
[12:10:14] [PASSED] 60 VFs
[12:10:14] [PASSED] 61 VFs
[12:10:14] [PASSED] 62 VFs
[12:10:14] [PASSED] 63 VFs
[12:10:14] ==================== [PASSED] fair_vram ====================
[12:10:14] ================== [PASSED] pf_gt_config ===================
[12:10:14] ===================== lmtt (1 subtest) =====================
[12:10:14] ======================== test_ops  =========================
[12:10:14] [PASSED] 2-level
[12:10:14] [PASSED] multi-level
[12:10:14] ==================== [PASSED] test_ops =====================
[12:10:14] ====================== [PASSED] lmtt =======================
[12:10:14] ================= sriov_packet (1 subtest) =================
[12:10:14] [PASSED] test_descriptor_init
[12:10:14] ================== [PASSED] sriov_packet ===================
[12:10:14] ================= pf_service (11 subtests) =================
[12:10:14] [PASSED] pf_negotiate_any
[12:10:14] [PASSED] pf_negotiate_base_match
[12:10:14] [PASSED] pf_negotiate_base_newer
[12:10:14] [PASSED] pf_negotiate_base_next
[12:10:14] [SKIPPED] pf_negotiate_base_older (no older minor)
[12:10:14] [PASSED] pf_negotiate_base_prev
[12:10:14] [PASSED] pf_negotiate_latest_match
[12:10:14] [PASSED] pf_negotiate_latest_newer
[12:10:14] [PASSED] pf_negotiate_latest_next
[12:10:14] [SKIPPED] pf_negotiate_latest_older (no older minor)
[12:10:14] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[12:10:14] =================== [PASSED] pf_service ====================
[12:10:14] ================= xe_guc_g2g (2 subtests) ==================
[12:10:14] ============== xe_live_guc_g2g_kunit_default  ==============
[12:10:14] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[12:10:14] ============== xe_live_guc_g2g_kunit_allmem  ===============
[12:10:14] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[12:10:14] =================== [SKIPPED] xe_guc_g2g ===================
[12:10:14] =================== xe_mocs (2 subtests) ===================
[12:10:14] ================ xe_live_mocs_kernel_kunit  ================
[12:10:14] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[12:10:14] ================ xe_live_mocs_reset_kunit  =================
[12:10:14] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[12:10:14] ==================== [SKIPPED] xe_mocs =====================
[12:10:14] ================= xe_migrate (2 subtests) ==================
[12:10:14] ================= xe_migrate_sanity_kunit  =================
[12:10:14] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[12:10:14] ================== xe_validate_ccs_kunit  ==================
[12:10:14] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[12:10:14] =================== [SKIPPED] xe_migrate ===================
[12:10:14] ================== xe_dma_buf (1 subtest) ==================
[12:10:14] ==================== xe_dma_buf_kunit  =====================
[12:10:14] ================ [SKIPPED] xe_dma_buf_kunit ================
[12:10:14] =================== [SKIPPED] xe_dma_buf ===================
[12:10:14] ================= xe_bo_shrink (1 subtest) =================
[12:10:14] =================== xe_bo_shrink_kunit  ====================
[12:10:14] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[12:10:14] ================== [SKIPPED] xe_bo_shrink ==================
[12:10:14] ==================== xe_bo (2 subtests) ====================
[12:10:14] ================== xe_ccs_migrate_kunit  ===================
[12:10:14] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[12:10:14] ==================== xe_bo_evict_kunit  ====================
[12:10:14] =============== [SKIPPED] xe_bo_evict_kunit ================
[12:10:14] ===================== [SKIPPED] xe_bo ======================
[12:10:14] ==================== args (13 subtests) ====================
[12:10:14] [PASSED] count_args_test
[12:10:14] [PASSED] call_args_example
[12:10:14] [PASSED] call_args_test
[12:10:14] [PASSED] drop_first_arg_example
[12:10:14] [PASSED] drop_first_arg_test
[12:10:14] [PASSED] first_arg_example
[12:10:14] [PASSED] first_arg_test
[12:10:14] [PASSED] last_arg_example
[12:10:14] [PASSED] last_arg_test
[12:10:14] [PASSED] pick_arg_example
[12:10:14] [PASSED] if_args_example
[12:10:14] [PASSED] if_args_test
[12:10:14] [PASSED] sep_comma_example
[12:10:14] ====================== [PASSED] args =======================
[12:10:14] =================== xe_pci (3 subtests) ====================
[12:10:14] ==================== check_graphics_ip  ====================
[12:10:14] [PASSED] 12.00 Xe_LP
[12:10:14] [PASSED] 12.10 Xe_LP+
[12:10:14] [PASSED] 12.55 Xe_HPG
[12:10:14] [PASSED] 12.60 Xe_HPC
[12:10:14] [PASSED] 12.70 Xe_LPG
[12:10:14] [PASSED] 12.71 Xe_LPG
[12:10:14] [PASSED] 12.74 Xe_LPG+
[12:10:14] [PASSED] 20.01 Xe2_HPG
[12:10:14] [PASSED] 20.02 Xe2_HPG
[12:10:14] [PASSED] 20.04 Xe2_LPG
[12:10:14] [PASSED] 30.00 Xe3_LPG
[12:10:14] [PASSED] 30.01 Xe3_LPG
[12:10:14] [PASSED] 30.03 Xe3_LPG
[12:10:14] [PASSED] 30.04 Xe3_LPG
[12:10:14] [PASSED] 30.05 Xe3_LPG
[12:10:14] [PASSED] 35.10 Xe3p_LPG
[12:10:14] [PASSED] 35.11 Xe3p_XPC
[12:10:14] ================ [PASSED] check_graphics_ip ================
[12:10:14] ===================== check_media_ip  ======================
[12:10:14] [PASSED] 12.00 Xe_M
[12:10:14] [PASSED] 12.55 Xe_HPM
[12:10:14] [PASSED] 13.00 Xe_LPM+
[12:10:14] [PASSED] 13.01 Xe2_HPM
[12:10:14] [PASSED] 20.00 Xe2_LPM
[12:10:14] [PASSED] 30.00 Xe3_LPM
[12:10:14] [PASSED] 30.02 Xe3_LPM
[12:10:14] [PASSED] 35.00 Xe3p_LPM
[12:10:14] [PASSED] 35.03 Xe3p_HPM
[12:10:14] ================= [PASSED] check_media_ip ==================
[12:10:14] =================== check_platform_desc  ===================
[12:10:14] [PASSED] 0x9A60 (TIGERLAKE)
[12:10:14] [PASSED] 0x9A68 (TIGERLAKE)
[12:10:14] [PASSED] 0x9A70 (TIGERLAKE)
[12:10:14] [PASSED] 0x9A40 (TIGERLAKE)
[12:10:14] [PASSED] 0x9A49 (TIGERLAKE)
[12:10:14] [PASSED] 0x9A59 (TIGERLAKE)
[12:10:14] [PASSED] 0x9A78 (TIGERLAKE)
[12:10:14] [PASSED] 0x9AC0 (TIGERLAKE)
[12:10:14] [PASSED] 0x9AC9 (TIGERLAKE)
[12:10:14] [PASSED] 0x9AD9 (TIGERLAKE)
[12:10:14] [PASSED] 0x9AF8 (TIGERLAKE)
[12:10:14] [PASSED] 0x4C80 (ROCKETLAKE)
[12:10:14] [PASSED] 0x4C8A (ROCKETLAKE)
[12:10:14] [PASSED] 0x4C8B (ROCKETLAKE)
[12:10:14] [PASSED] 0x4C8C (ROCKETLAKE)
[12:10:14] [PASSED] 0x4C90 (ROCKETLAKE)
[12:10:14] [PASSED] 0x4C9A (ROCKETLAKE)
[12:10:14] [PASSED] 0x4680 (ALDERLAKE_S)
[12:10:14] [PASSED] 0x4682 (ALDERLAKE_S)
[12:10:14] [PASSED] 0x4688 (ALDERLAKE_S)
[12:10:14] [PASSED] 0x468A (ALDERLAKE_S)
[12:10:14] [PASSED] 0x468B (ALDERLAKE_S)
[12:10:14] [PASSED] 0x4690 (ALDERLAKE_S)
[12:10:14] [PASSED] 0x4692 (ALDERLAKE_S)
[12:10:14] [PASSED] 0x4693 (ALDERLAKE_S)
[12:10:14] [PASSED] 0x46A0 (ALDERLAKE_P)
[12:10:14] [PASSED] 0x46A1 (ALDERLAKE_P)
[12:10:14] [PASSED] 0x46A2 (ALDERLAKE_P)
[12:10:14] [PASSED] 0x46A3 (ALDERLAKE_P)
[12:10:14] [PASSED] 0x46A6 (ALDERLAKE_P)
[12:10:14] [PASSED] 0x46A8 (ALDERLAKE_P)
[12:10:14] [PASSED] 0x46AA (ALDERLAKE_P)
[12:10:14] [PASSED] 0x462A (ALDERLAKE_P)
[12:10:14] [PASSED] 0x4626 (ALDERLAKE_P)
[12:10:14] [PASSED] 0x4628 (ALDERLAKE_P)
[12:10:14] [PASSED] 0x46B0 (ALDERLAKE_P)
[12:10:14] [PASSED] 0x46B1 (ALDERLAKE_P)
[12:10:14] [PASSED] 0x46B2 (ALDERLAKE_P)
[12:10:14] [PASSED] 0x46B3 (ALDERLAKE_P)
[12:10:14] [PASSED] 0x46C0 (ALDERLAKE_P)
[12:10:14] [PASSED] 0x46C1 (ALDERLAKE_P)
[12:10:14] [PASSED] 0x46C2 (ALDERLAKE_P)
[12:10:14] [PASSED] 0x46C3 (ALDERLAKE_P)
[12:10:14] [PASSED] 0x46D0 (ALDERLAKE_N)
[12:10:14] [PASSED] 0x46D1 (ALDERLAKE_N)
[12:10:14] [PASSED] 0x46D2 (ALDERLAKE_N)
[12:10:14] [PASSED] 0x46D3 (ALDERLAKE_N)
[12:10:14] [PASSED] 0x46D4 (ALDERLAKE_N)
[12:10:14] [PASSED] 0xA721 (ALDERLAKE_P)
[12:10:14] [PASSED] 0xA7A1 (ALDERLAKE_P)
[12:10:14] [PASSED] 0xA7A9 (ALDERLAKE_P)
[12:10:14] [PASSED] 0xA7AC (ALDERLAKE_P)
[12:10:14] [PASSED] 0xA7AD (ALDERLAKE_P)
[12:10:14] [PASSED] 0xA720 (ALDERLAKE_P)
[12:10:14] [PASSED] 0xA7A0 (ALDERLAKE_P)
[12:10:14] [PASSED] 0xA7A8 (ALDERLAKE_P)
[12:10:14] [PASSED] 0xA7AA (ALDERLAKE_P)
[12:10:14] [PASSED] 0xA7AB (ALDERLAKE_P)
[12:10:14] [PASSED] 0xA780 (ALDERLAKE_S)
[12:10:14] [PASSED] 0xA781 (ALDERLAKE_S)
[12:10:14] [PASSED] 0xA782 (ALDERLAKE_S)
[12:10:14] [PASSED] 0xA783 (ALDERLAKE_S)
[12:10:14] [PASSED] 0xA788 (ALDERLAKE_S)
[12:10:14] [PASSED] 0xA789 (ALDERLAKE_S)
[12:10:14] [PASSED] 0xA78A (ALDERLAKE_S)
[12:10:14] [PASSED] 0xA78B (ALDERLAKE_S)
[12:10:14] [PASSED] 0x4905 (DG1)
[12:10:14] [PASSED] 0x4906 (DG1)
[12:10:14] [PASSED] 0x4907 (DG1)
[12:10:14] [PASSED] 0x4908 (DG1)
[12:10:14] [PASSED] 0x4909 (DG1)
[12:10:14] [PASSED] 0x56C0 (DG2)
[12:10:14] [PASSED] 0x56C2 (DG2)
[12:10:14] [PASSED] 0x56C1 (DG2)
[12:10:14] [PASSED] 0x7D51 (METEORLAKE)
[12:10:14] [PASSED] 0x7DD1 (METEORLAKE)
[12:10:14] [PASSED] 0x7D41 (METEORLAKE)
[12:10:14] [PASSED] 0x7D67 (METEORLAKE)
[12:10:14] [PASSED] 0xB640 (METEORLAKE)
[12:10:14] [PASSED] 0x56A0 (DG2)
[12:10:14] [PASSED] 0x56A1 (DG2)
[12:10:14] [PASSED] 0x56A2 (DG2)
[12:10:14] [PASSED] 0x56BE (DG2)
[12:10:14] [PASSED] 0x56BF (DG2)
[12:10:14] [PASSED] 0x5690 (DG2)
[12:10:14] [PASSED] 0x5691 (DG2)
[12:10:14] [PASSED] 0x5692 (DG2)
[12:10:14] [PASSED] 0x56A5 (DG2)
[12:10:14] [PASSED] 0x56A6 (DG2)
[12:10:14] [PASSED] 0x56B0 (DG2)
[12:10:14] [PASSED] 0x56B1 (DG2)
[12:10:14] [PASSED] 0x56BA (DG2)
[12:10:14] [PASSED] 0x56BB (DG2)
[12:10:14] [PASSED] 0x56BC (DG2)
[12:10:14] [PASSED] 0x56BD (DG2)
[12:10:14] [PASSED] 0x5693 (DG2)
[12:10:14] [PASSED] 0x5694 (DG2)
[12:10:14] [PASSED] 0x5695 (DG2)
[12:10:14] [PASSED] 0x56A3 (DG2)
[12:10:14] [PASSED] 0x56A4 (DG2)
[12:10:14] [PASSED] 0x56B2 (DG2)
[12:10:14] [PASSED] 0x56B3 (DG2)
[12:10:14] [PASSED] 0x5696 (DG2)
[12:10:14] [PASSED] 0x5697 (DG2)
[12:10:14] [PASSED] 0xB69 (PVC)
[12:10:14] [PASSED] 0xB6E (PVC)
[12:10:14] [PASSED] 0xBD4 (PVC)
[12:10:14] [PASSED] 0xBD5 (PVC)
[12:10:14] [PASSED] 0xBD6 (PVC)
[12:10:14] [PASSED] 0xBD7 (PVC)
[12:10:14] [PASSED] 0xBD8 (PVC)
[12:10:14] [PASSED] 0xBD9 (PVC)
[12:10:14] [PASSED] 0xBDA (PVC)
[12:10:14] [PASSED] 0xBDB (PVC)
[12:10:14] [PASSED] 0xBE0 (PVC)
[12:10:14] [PASSED] 0xBE1 (PVC)
[12:10:14] [PASSED] 0xBE5 (PVC)
[12:10:14] [PASSED] 0x7D40 (METEORLAKE)
[12:10:14] [PASSED] 0x7D45 (METEORLAKE)
[12:10:14] [PASSED] 0x7D55 (METEORLAKE)
[12:10:14] [PASSED] 0x7D60 (METEORLAKE)
[12:10:14] [PASSED] 0x7DD5 (METEORLAKE)
[12:10:14] [PASSED] 0x6420 (LUNARLAKE)
[12:10:14] [PASSED] 0x64A0 (LUNARLAKE)
[12:10:14] [PASSED] 0x64B0 (LUNARLAKE)
[12:10:14] [PASSED] 0xE202 (BATTLEMAGE)
[12:10:14] [PASSED] 0xE209 (BATTLEMAGE)
[12:10:14] [PASSED] 0xE20B (BATTLEMAGE)
[12:10:14] [PASSED] 0xE20C (BATTLEMAGE)
[12:10:14] [PASSED] 0xE20D (BATTLEMAGE)
[12:10:14] [PASSED] 0xE210 (BATTLEMAGE)
[12:10:14] [PASSED] 0xE211 (BATTLEMAGE)
[12:10:14] [PASSED] 0xE212 (BATTLEMAGE)
[12:10:14] [PASSED] 0xE216 (BATTLEMAGE)
[12:10:14] [PASSED] 0xE220 (BATTLEMAGE)
[12:10:14] [PASSED] 0xE221 (BATTLEMAGE)
[12:10:14] [PASSED] 0xE222 (BATTLEMAGE)
[12:10:14] [PASSED] 0xE223 (BATTLEMAGE)
[12:10:14] [PASSED] 0xB080 (PANTHERLAKE)
[12:10:14] [PASSED] 0xB081 (PANTHERLAKE)
[12:10:14] [PASSED] 0xB082 (PANTHERLAKE)
[12:10:14] [PASSED] 0xB083 (PANTHERLAKE)
[12:10:14] [PASSED] 0xB084 (PANTHERLAKE)
[12:10:14] [PASSED] 0xB085 (PANTHERLAKE)
[12:10:14] [PASSED] 0xB086 (PANTHERLAKE)
[12:10:14] [PASSED] 0xB087 (PANTHERLAKE)
[12:10:14] [PASSED] 0xB08F (PANTHERLAKE)
[12:10:14] [PASSED] 0xB090 (PANTHERLAKE)
[12:10:14] [PASSED] 0xB0A0 (PANTHERLAKE)
[12:10:14] [PASSED] 0xB0B0 (PANTHERLAKE)
[12:10:14] [PASSED] 0xFD80 (PANTHERLAKE)
[12:10:14] [PASSED] 0xFD81 (PANTHERLAKE)
[12:10:14] [PASSED] 0xD740 (NOVALAKE_S)
[12:10:14] [PASSED] 0xD741 (NOVALAKE_S)
[12:10:14] [PASSED] 0xD742 (NOVALAKE_S)
[12:10:14] [PASSED] 0xD743 (NOVALAKE_S)
[12:10:14] [PASSED] 0xD745 (NOVALAKE_S)
[12:10:14] [PASSED] 0xD74A (NOVALAKE_S)
[12:10:14] [PASSED] 0xD74B (NOVALAKE_S)
[12:10:14] [PASSED] 0x674C (CRESCENTISLAND)
[12:10:14] [PASSED] 0x674D (CRESCENTISLAND)
[12:10:14] [PASSED] 0x674E (CRESCENTISLAND)
[12:10:14] [PASSED] 0x674F (CRESCENTISLAND)
[12:10:14] [PASSED] 0x6750 (CRESCENTISLAND)
[12:10:14] [PASSED] 0xD750 (NOVALAKE_P)
[12:10:14] [PASSED] 0xD751 (NOVALAKE_P)
[12:10:14] [PASSED] 0xD752 (NOVALAKE_P)
[12:10:14] [PASSED] 0xD753 (NOVALAKE_P)
[12:10:14] [PASSED] 0xD754 (NOVALAKE_P)
[12:10:14] [PASSED] 0xD755 (NOVALAKE_P)
[12:10:14] [PASSED] 0xD756 (NOVALAKE_P)
[12:10:14] [PASSED] 0xD757 (NOVALAKE_P)
[12:10:14] [PASSED] 0xD75F (NOVALAKE_P)
[12:10:14] =============== [PASSED] check_platform_desc ===============
[12:10:14] ===================== [PASSED] xe_pci ======================
[12:10:14] ============= xe_rtp_tables_test (5 subtests) ==============
[12:10:14] ================== xe_rtp_table_gt_test  ===================
[12:10:14] [PASSED] gt_was/14011060649
[12:10:14] [PASSED] gt_was/14011059788
[12:10:14] [PASSED] gt_was/14015795083
[12:10:14] [PASSED] gt_was/16021867713
[12:10:14] [PASSED] gt_was/14019449301
[12:10:14] [PASSED] gt_was/16028005424
[12:10:14] [PASSED] gt_was/14026578760
[12:10:14] [PASSED] gt_was/1409420604
[12:10:14] [PASSED] gt_was/1408615072
[12:10:14] [PASSED] gt_was/22010523718
[12:10:14] [PASSED] gt_was/14011006942
[12:10:14] [PASSED] gt_was/14014830051
[12:10:14] [PASSED] gt_was/18018781329
[12:10:14] [PASSED] gt_was/1509235366
[12:10:14] [PASSED] gt_was/18018781329
[12:10:14] [PASSED] gt_was/16016694945
[12:10:14] [PASSED] gt_was/14018575942
[12:10:14] [PASSED] gt_was/22016670082
[12:10:14] [PASSED] gt_was/22016670082
[12:10:14] [PASSED] gt_was/14017421178
[12:10:14] [PASSED] gt_was/16025250150
[12:10:14] [PASSED] gt_was/14021871409
[12:10:14] [PASSED] gt_was/16021865536
[12:10:14] [PASSED] gt_was/14021486841
[12:10:14] [PASSED] gt_was/14025160223
[12:10:14] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[12:10:14] [PASSED] gt_was/14025635424
[12:10:14] [PASSED] gt_was/16028005424
[12:10:14] ============== [PASSED] xe_rtp_table_gt_test ===============
[12:10:14] ================== xe_rtp_table_gt_test  ===================
[12:10:14] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[12:10:14] [PASSED] gt_tunings/Tuning: 32B Access Enable
[12:10:14] [PASSED] gt_tunings/Tuning: L3 cache
[12:10:14] [PASSED] gt_tunings/Tuning: L3 cache - media
[12:10:14] [PASSED] gt_tunings/Tuning: Compression Overfetch
[12:10:14] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[12:10:14] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[12:10:14] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[12:10:14] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[12:10:14] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[12:10:14] [PASSED] gt_tunings/Tuning: Stateless compression control
[12:10:14] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[12:10:14] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[12:10:14] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[12:10:14] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[12:10:14] ============== [PASSED] xe_rtp_table_gt_test ===============
[12:10:14] ================== xe_rtp_table_oob_test  ==================
[12:10:14] [PASSED] oob_was/1607983814
[12:10:14] [PASSED] oob_was/16010904313
[12:10:14] [PASSED] oob_was/18022495364
[12:10:14] [PASSED] oob_was/22012773006
[12:10:14] [PASSED] oob_was/14014475959
[12:10:14] [PASSED] oob_was/22011391025
[12:10:14] [PASSED] oob_was/22012727170
[12:10:14] [PASSED] oob_was/22012727685
[12:10:14] [PASSED] oob_was/22016596838
[12:10:14] [PASSED] oob_was/18020744125
[12:10:14] [PASSED] oob_was/1409600907
[12:10:14] [PASSED] oob_was/22014953428
[12:10:14] [PASSED] oob_was/16017236439
[12:10:14] [PASSED] oob_was/14019821291
[12:10:14] [PASSED] oob_was/14015076503
[12:10:14] [PASSED] oob_was/14018913170
[12:10:14] [PASSED] oob_was/14018094691
[12:10:14] [PASSED] oob_was/18024947630
[12:10:14] [PASSED] oob_was/16022287689
[12:10:14] [PASSED] oob_was/13011645652
[12:10:14] [PASSED] oob_was/14022293748
[12:10:14] [PASSED] oob_was/22019794406
[12:10:14] [PASSED] oob_was/22019338487
[12:10:14] [PASSED] oob_was/16023588340
[12:10:14] [PASSED] oob_was/14019789679
[12:10:14] [PASSED] oob_was/14022866841
[12:10:14] [PASSED] oob_was/16021333562
[12:10:14] [PASSED] oob_was/14016712196
[12:10:14] [PASSED] oob_was/14015568240
[12:10:14] [PASSED] oob_was/18013179988
[12:10:14] [PASSED] oob_was/1508761755
[12:10:14] [PASSED] oob_was/16023105232
[12:10:14] [PASSED] oob_was/16026508708
[12:10:14] [PASSED] oob_was/14020001231
[12:10:14] [PASSED] oob_was/16023683509
[12:10:14] [PASSED] oob_was/14025515070
[12:10:14] [PASSED] oob_was/15015404425_disable
[12:10:14] [PASSED] oob_was/16026007364
[12:10:14] [PASSED] oob_was/14020316580
[12:10:14] [PASSED] oob_was/14025883347
[12:10:14] [PASSED] oob_was/16029380221
[12:10:14] [PASSED] oob_was/22022079272
[12:10:14] [PASSED] oob_was/16029897822
[12:10:14] [PASSED] oob_was/14027054324
[12:10:14] ============== [PASSED] xe_rtp_table_oob_test ==============
[12:10:14] ================ xe_rtp_table_dev_oob_test  ================
[12:10:14] [PASSED] device_oob_was/22010954014
[12:10:14] [PASSED] device_oob_was/15015404425
[12:10:14] [PASSED] device_oob_was/22019338487_display
[12:10:14] [PASSED] device_oob_was/14022085890
[12:10:14] [PASSED] device_oob_was/14026539277
[12:10:14] [PASSED] device_oob_was/14026633728
[12:10:14] [PASSED] device_oob_was/14026746987
[12:10:14] [PASSED] device_oob_was/14026779378
[12:10:14] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[12:10:14] ========== xe_rtp_table_missing_upper_bound_test  ==========
[12:10:14] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[12:10:14] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[12:10:14] [PASSED] register_whitelist/1806527549
[12:10:14] [PASSED] register_whitelist/allow_read_ctx_timestamp
[12:10:14] [PASSED] register_whitelist/allow_read_queue_timestamp
[12:10:14] [PASSED] register_whitelist/16014440446
[12:10:14] [PASSED] register_whitelist/16017236439
[12:10:14] [PASSED] register_whitelist/16020183090
[12:10:14] [PASSED] register_whitelist/14024997852
[12:10:14] [PASSED] register_whitelist/14024997852
[12:10:14] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[12:10:14] =============== [PASSED] xe_rtp_tables_test ================
[12:10:14] =================== xe_rtp (3 subtests) ====================
[12:10:14] =================== xe_rtp_rules_tests  ====================
[12:10:14] [PASSED] no
[12:10:14] [PASSED] yes
[12:10:14] [PASSED] no-and-no
[12:10:14] [PASSED] no-and-yes
[12:10:14] [PASSED] yes-and-no
[12:10:14] [PASSED] yes-and-yes
[12:10:14] [PASSED] no-or-no
[12:10:14] [PASSED] no-or-yes
[12:10:14] [PASSED] yes-or-no
[12:10:14] [PASSED] yes-or-yes
[12:10:14] [PASSED] no-yes-or-yes-no
[12:10:14] [PASSED] no-yes-or-yes-yes
[12:10:14] [PASSED] yes-yes-or-no-yes
[12:10:14] [PASSED] yes-yes-or-yes-yes
[12:10:14] [PASSED] no-no-or-yes-or-no
[12:10:14] [PASSED] or
[12:10:14] [PASSED] or-yes
[12:10:14] [PASSED] or-no
[12:10:14] [PASSED] yes-or
[12:10:14] [PASSED] no-or
[12:10:14] [PASSED] no-or-or-yes
[12:10:14] [PASSED] yes-or-or-no
[12:10:14] [PASSED] no-or-or-no
[12:10:14] [PASSED] missing-context-engine-class
[12:10:14] [PASSED] missing-context-engine-class-or-yes
[12:10:14] [PASSED] missing-context-engine-class-or-or-yes
[12:10:14] =============== [PASSED] xe_rtp_rules_tests ================
[12:10:14] =============== xe_rtp_process_to_sr_tests  ================
[12:10:14] [PASSED] coalesce-same-reg
[12:10:14] [PASSED] coalesce-same-reg-literal-and-func
[12:10:14] [PASSED] no-match-no-add
[12:10:14] [PASSED] two-regs-two-entries
[12:10:14] [PASSED] clr-one-set-other
[12:10:14] [PASSED] set-field
[12:10:14] [PASSED] conflict-duplicate
[12:10:14] [PASSED] conflict-not-disjoint
[12:10:14] [PASSED] conflict-not-disjoint-literal-and-func
[12:10:14] [PASSED] conflict-reg-type
[12:10:14] [PASSED] bad-mcr-reg-forced-to-regular
[12:10:14] [PASSED] bad-regular-reg-forced-to-mcr
[12:10:14] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[12:10:14] ================== xe_rtp_process_tests  ===================
[12:10:14] [PASSED] active1
[12:10:14] [PASSED] active2
[12:10:14] [PASSED] active-inactive
[12:10:14] [PASSED] inactive-active
[12:10:14] [PASSED] inactive-active-inactive
[12:10:14] [PASSED] inactive-inactive-inactive
[12:10:14] ============== [PASSED] xe_rtp_process_tests ===============
[12:10:14] ===================== [PASSED] xe_rtp ======================
[12:10:14] ==================== xe_wa (1 subtest) =====================
[12:10:14] ======================== xe_wa_gt  =========================
[12:10:14] [PASSED] TIGERLAKE B0
[12:10:14] [PASSED] DG1 A0
[12:10:14] [PASSED] DG1 B0
[12:10:14] [PASSED] ALDERLAKE_S A0
[12:10:14] [PASSED] ALDERLAKE_S B0
[12:10:14] [PASSED] ALDERLAKE_S C0
[12:10:14] [PASSED] ALDERLAKE_S D0
[12:10:14] [PASSED] ALDERLAKE_P A0
[12:10:14] [PASSED] ALDERLAKE_P B0
[12:10:14] [PASSED] ALDERLAKE_P C0
[12:10:14] [PASSED] ALDERLAKE_S RPLS D0
[12:10:14] [PASSED] ALDERLAKE_P RPLU E0
[12:10:14] [PASSED] DG2 G10 C0
[12:10:14] [PASSED] DG2 G11 B1
[12:10:14] [PASSED] DG2 G12 A1
[12:10:14] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:10:14] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:10:14] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[12:10:14] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[12:10:14] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[12:10:14] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[12:10:14] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[12:10:14] ==================== [PASSED] xe_wa_gt =====================
[12:10:14] ====================== [PASSED] xe_wa ======================
[12:10:14] ============================================================
[12:10:14] Testing complete. Ran 742 tests: passed: 724, skipped: 18
[12:10:14] Elapsed time: 37.001s total, 4.455s configuring, 31.881s building, 0.633s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[12:10:15] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:10:16] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:10:41] Starting KUnit Kernel (1/1)...
[12:10:41] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:10:41] ============ drm_test_pick_cmdline (2 subtests) ============
[12:10:41] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[12:10:41] =============== drm_test_pick_cmdline_named  ===============
[12:10:41] [PASSED] NTSC
[12:10:41] [PASSED] NTSC-J
[12:10:41] [PASSED] PAL
[12:10:41] [PASSED] PAL-M
[12:10:41] =========== [PASSED] drm_test_pick_cmdline_named ===========
[12:10:41] ============== [PASSED] drm_test_pick_cmdline ==============
[12:10:41] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[12:10:41] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[12:10:41] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[12:10:41] =========== drm_validate_clone_mode (2 subtests) ===========
[12:10:41] ============== drm_test_check_in_clone_mode  ===============
[12:10:41] [PASSED] in_clone_mode
[12:10:41] [PASSED] not_in_clone_mode
[12:10:41] ========== [PASSED] drm_test_check_in_clone_mode ===========
[12:10:41] =============== drm_test_check_valid_clones  ===============
[12:10:41] [PASSED] not_in_clone_mode
[12:10:41] [PASSED] valid_clone
[12:10:41] [PASSED] invalid_clone
[12:10:41] =========== [PASSED] drm_test_check_valid_clones ===========
[12:10:41] ============= [PASSED] drm_validate_clone_mode =============
[12:10:41] ============= drm_validate_modeset (1 subtest) =============
[12:10:41] [PASSED] drm_test_check_connector_changed_modeset
[12:10:41] ============== [PASSED] drm_validate_modeset ===============
[12:10:41] ====== drm_test_bridge_get_current_state (1 subtest) =======
[12:10:41] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[12:10:41] ======== [PASSED] drm_test_bridge_get_current_state ========
[12:10:41] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[12:10:41] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[12:10:41] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[12:10:41] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[12:10:41] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[12:10:41] ============== drm_bridge_alloc (2 subtests) ===============
[12:10:41] [PASSED] drm_test_drm_bridge_alloc_basic
[12:10:41] [PASSED] drm_test_drm_bridge_alloc_get_put
[12:10:41] ================ [PASSED] drm_bridge_alloc =================
[12:10:41] ============= drm_bridge_bus_fmt (5 subtests) ==============
[12:10:41] [PASSED] drm_test_bridge_rgb_yuv_rgb
[12:10:41] [PASSED] drm_test_bridge_must_convert_to_yuv444
[12:10:41] [PASSED] drm_test_bridge_hdmi_auto_rgb
[12:10:41] [PASSED] drm_test_bridge_auto_first
[12:10:41] [PASSED] drm_test_bridge_rgb_yuv_no_path
[12:10:41] =============== [PASSED] drm_bridge_bus_fmt ================
[12:10:41] ============= drm_cmdline_parser (40 subtests) =============
[12:10:41] [PASSED] drm_test_cmdline_force_d_only
[12:10:41] [PASSED] drm_test_cmdline_force_D_only_dvi
[12:10:41] [PASSED] drm_test_cmdline_force_D_only_hdmi
[12:10:41] [PASSED] drm_test_cmdline_force_D_only_not_digital
[12:10:41] [PASSED] drm_test_cmdline_force_e_only
[12:10:41] [PASSED] drm_test_cmdline_res
[12:10:41] [PASSED] drm_test_cmdline_res_vesa
[12:10:41] [PASSED] drm_test_cmdline_res_vesa_rblank
[12:10:41] [PASSED] drm_test_cmdline_res_rblank
[12:10:41] [PASSED] drm_test_cmdline_res_bpp
[12:10:41] [PASSED] drm_test_cmdline_res_refresh
[12:10:41] [PASSED] drm_test_cmdline_res_bpp_refresh
[12:10:41] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[12:10:41] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[12:10:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[12:10:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[12:10:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[12:10:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[12:10:41] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[12:10:41] [PASSED] drm_test_cmdline_res_margins_force_on
[12:10:41] [PASSED] drm_test_cmdline_res_vesa_margins
[12:10:41] [PASSED] drm_test_cmdline_name
[12:10:41] [PASSED] drm_test_cmdline_name_bpp
[12:10:41] [PASSED] drm_test_cmdline_name_option
[12:10:41] [PASSED] drm_test_cmdline_name_bpp_option
[12:10:41] [PASSED] drm_test_cmdline_rotate_0
[12:10:41] [PASSED] drm_test_cmdline_rotate_90
[12:10:41] [PASSED] drm_test_cmdline_rotate_180
[12:10:41] [PASSED] drm_test_cmdline_rotate_270
[12:10:41] [PASSED] drm_test_cmdline_hmirror
[12:10:41] [PASSED] drm_test_cmdline_vmirror
[12:10:41] [PASSED] drm_test_cmdline_margin_options
[12:10:41] [PASSED] drm_test_cmdline_multiple_options
[12:10:41] [PASSED] drm_test_cmdline_bpp_extra_and_option
[12:10:41] [PASSED] drm_test_cmdline_extra_and_option
[12:10:41] [PASSED] drm_test_cmdline_freestanding_options
[12:10:41] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[12:10:41] [PASSED] drm_test_cmdline_panel_orientation
[12:10:41] ================ drm_test_cmdline_invalid  =================
[12:10:41] [PASSED] margin_only
[12:10:41] [PASSED] interlace_only
[12:10:41] [PASSED] res_missing_x
[12:10:41] [PASSED] res_missing_y
[12:10:41] [PASSED] res_bad_y
[12:10:41] [PASSED] res_missing_y_bpp
[12:10:41] [PASSED] res_bad_bpp
[12:10:41] [PASSED] res_bad_refresh
[12:10:41] [PASSED] res_bpp_refresh_force_on_off
[12:10:41] [PASSED] res_invalid_mode
[12:10:41] [PASSED] res_bpp_wrong_place_mode
[12:10:41] [PASSED] name_bpp_refresh
[12:10:41] [PASSED] name_refresh
[12:10:41] [PASSED] name_refresh_wrong_mode
[12:10:41] [PASSED] name_refresh_invalid_mode
[12:10:41] [PASSED] rotate_multiple
[12:10:41] [PASSED] rotate_invalid_val
[12:10:41] [PASSED] rotate_truncated
[12:10:41] [PASSED] invalid_option
[12:10:41] [PASSED] invalid_tv_option
[12:10:41] [PASSED] truncated_tv_option
[12:10:41] ============ [PASSED] drm_test_cmdline_invalid =============
[12:10:41] =============== drm_test_cmdline_tv_options  ===============
[12:10:41] [PASSED] NTSC
[12:10:41] [PASSED] NTSC_443
[12:10:41] [PASSED] NTSC_J
[12:10:41] [PASSED] PAL
[12:10:41] [PASSED] PAL_M
[12:10:41] [PASSED] PAL_N
[12:10:41] [PASSED] SECAM
[12:10:41] [PASSED] MONO_525
[12:10:41] [PASSED] MONO_625
[12:10:41] =========== [PASSED] drm_test_cmdline_tv_options ===========
[12:10:41] =============== [PASSED] drm_cmdline_parser ================
[12:10:41] ========== drmm_connector_hdmi_init (20 subtests) ==========
[12:10:41] [PASSED] drm_test_connector_hdmi_init_valid
[12:10:41] [PASSED] drm_test_connector_hdmi_init_bpc_8
[12:10:41] [PASSED] drm_test_connector_hdmi_init_bpc_10
[12:10:41] [PASSED] drm_test_connector_hdmi_init_bpc_12
[12:10:41] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[12:10:41] [PASSED] drm_test_connector_hdmi_init_bpc_null
[12:10:41] [PASSED] drm_test_connector_hdmi_init_formats_empty
[12:10:41] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[12:10:41] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[12:10:41] [PASSED] supported_formats=0x9 yuv420_allowed=1
[12:10:41] [PASSED] supported_formats=0x9 yuv420_allowed=0
[12:10:41] [PASSED] supported_formats=0x5 yuv420_allowed=1
[12:10:41] [PASSED] supported_formats=0x5 yuv420_allowed=0
[12:10:41] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[12:10:41] [PASSED] drm_test_connector_hdmi_init_null_ddc
[12:10:41] [PASSED] drm_test_connector_hdmi_init_null_product
[12:10:41] [PASSED] drm_test_connector_hdmi_init_null_vendor
[12:10:41] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[12:10:41] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[12:10:41] [PASSED] drm_test_connector_hdmi_init_product_valid
[12:10:41] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[12:10:41] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[12:10:41] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[12:10:41] ========= drm_test_connector_hdmi_init_type_valid  =========
[12:10:41] [PASSED] HDMI-A
[12:10:41] [PASSED] HDMI-B
[12:10:41] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[12:10:41] ======== drm_test_connector_hdmi_init_type_invalid  ========
[12:10:41] [PASSED] Unknown
[12:10:41] [PASSED] VGA
[12:10:41] [PASSED] DVI-I
[12:10:41] [PASSED] DVI-D
[12:10:41] [PASSED] DVI-A
[12:10:41] [PASSED] Composite
[12:10:41] [PASSED] SVIDEO
[12:10:41] [PASSED] LVDS
[12:10:41] [PASSED] Component
[12:10:41] [PASSED] DIN
[12:10:41] [PASSED] DP
[12:10:41] [PASSED] TV
[12:10:41] [PASSED] eDP
[12:10:41] [PASSED] Virtual
[12:10:41] [PASSED] DSI
[12:10:41] [PASSED] DPI
[12:10:41] [PASSED] Writeback
[12:10:41] [PASSED] SPI
[12:10:41] [PASSED] USB
[12:10:41] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[12:10:41] ============ [PASSED] drmm_connector_hdmi_init =============
[12:10:41] ============= drmm_connector_init (3 subtests) =============
[12:10:41] [PASSED] drm_test_drmm_connector_init
[12:10:41] [PASSED] drm_test_drmm_connector_init_null_ddc
[12:10:41] ========= drm_test_drmm_connector_init_type_valid  =========
[12:10:41] [PASSED] Unknown
[12:10:41] [PASSED] VGA
[12:10:41] [PASSED] DVI-I
[12:10:41] [PASSED] DVI-D
[12:10:41] [PASSED] DVI-A
[12:10:41] [PASSED] Composite
[12:10:41] [PASSED] SVIDEO
[12:10:41] [PASSED] LVDS
[12:10:41] [PASSED] Component
[12:10:41] [PASSED] DIN
[12:10:41] [PASSED] DP
[12:10:41] [PASSED] HDMI-A
[12:10:41] [PASSED] HDMI-B
[12:10:41] [PASSED] TV
[12:10:41] [PASSED] eDP
[12:10:41] [PASSED] Virtual
[12:10:41] [PASSED] DSI
[12:10:41] [PASSED] DPI
[12:10:41] [PASSED] Writeback
[12:10:41] [PASSED] SPI
[12:10:41] [PASSED] USB
[12:10:41] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[12:10:41] =============== [PASSED] drmm_connector_init ===============
[12:10:41] ========= drm_connector_dynamic_init (6 subtests) ==========
[12:10:41] [PASSED] drm_test_drm_connector_dynamic_init
[12:10:41] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[12:10:41] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[12:10:41] [PASSED] drm_test_drm_connector_dynamic_init_properties
[12:10:41] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[12:10:41] [PASSED] Unknown
[12:10:41] [PASSED] VGA
[12:10:41] [PASSED] DVI-I
[12:10:41] [PASSED] DVI-D
[12:10:41] [PASSED] DVI-A
[12:10:41] [PASSED] Composite
[12:10:41] [PASSED] SVIDEO
[12:10:41] [PASSED] LVDS
[12:10:41] [PASSED] Component
[12:10:41] [PASSED] DIN
[12:10:41] [PASSED] DP
[12:10:41] [PASSED] HDMI-A
[12:10:41] [PASSED] HDMI-B
[12:10:41] [PASSED] TV
[12:10:41] [PASSED] eDP
[12:10:41] [PASSED] Virtual
[12:10:41] [PASSED] DSI
[12:10:41] [PASSED] DPI
[12:10:41] [PASSED] Writeback
[12:10:41] [PASSED] SPI
[12:10:41] [PASSED] USB
[12:10:41] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[12:10:41] ======== drm_test_drm_connector_dynamic_init_name  =========
[12:10:41] [PASSED] Unknown
[12:10:41] [PASSED] VGA
[12:10:41] [PASSED] DVI-I
[12:10:41] [PASSED] DVI-D
[12:10:41] [PASSED] DVI-A
[12:10:41] [PASSED] Composite
[12:10:41] [PASSED] SVIDEO
[12:10:41] [PASSED] LVDS
[12:10:41] [PASSED] Component
[12:10:41] [PASSED] DIN
[12:10:41] [PASSED] DP
[12:10:41] [PASSED] HDMI-A
[12:10:41] [PASSED] HDMI-B
[12:10:41] [PASSED] TV
[12:10:41] [PASSED] eDP
[12:10:41] [PASSED] Virtual
[12:10:41] [PASSED] DSI
[12:10:41] [PASSED] DPI
[12:10:41] [PASSED] Writeback
[12:10:41] [PASSED] SPI
[12:10:41] [PASSED] USB
[12:10:41] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[12:10:41] =========== [PASSED] drm_connector_dynamic_init ============
[12:10:41] ==== drm_connector_dynamic_register_early (4 subtests) =====
[12:10:41] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[12:10:41] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[12:10:41] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[12:10:41] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[12:10:41] ====== [PASSED] drm_connector_dynamic_register_early =======
[12:10:41] ======= drm_connector_dynamic_register (7 subtests) ========
[12:10:41] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[12:10:41] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[12:10:41] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[12:10:41] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[12:10:41] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[12:10:41] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[12:10:41] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[12:10:41] ========= [PASSED] drm_connector_dynamic_register ==========
[12:10:41] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[12:10:41] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[12:10:41] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[12:10:41] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[12:10:41] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[12:10:41] ========== drm_test_get_tv_mode_from_name_valid  ===========
[12:10:41] [PASSED] NTSC
[12:10:41] [PASSED] NTSC-443
[12:10:41] [PASSED] NTSC-J
[12:10:41] [PASSED] PAL
[12:10:41] [PASSED] PAL-M
[12:10:41] [PASSED] PAL-N
[12:10:41] [PASSED] SECAM
[12:10:41] [PASSED] Mono
[12:10:41] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[12:10:41] [PASSED] drm_test_get_tv_mode_from_name_truncated
[12:10:41] ============ [PASSED] drm_get_tv_mode_from_name ============
[12:10:41] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[12:10:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[12:10:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[12:10:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[12:10:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[12:10:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[12:10:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[12:10:41] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[12:10:41] [PASSED] VIC 96
[12:10:41] [PASSED] VIC 97
[12:10:41] [PASSED] VIC 101
[12:10:41] [PASSED] VIC 102
[12:10:41] [PASSED] VIC 106
[12:10:41] [PASSED] VIC 107
[12:10:41] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[12:10:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[12:10:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[12:10:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[12:10:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[12:10:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[12:10:41] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[12:10:41] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[12:10:41] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[12:10:41] [PASSED] Automatic
[12:10:41] [PASSED] Full
[12:10:41] [PASSED] Limited 16:235
[12:10:41] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[12:10:41] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[12:10:41] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[12:10:41] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[12:10:41] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[12:10:41] [PASSED] RGB
[12:10:41] [PASSED] YUV 4:2:0
[12:10:41] [PASSED] YUV 4:2:2
[12:10:41] [PASSED] YUV 4:4:4
[12:10:41] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[12:10:41] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[12:10:41] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[12:10:41] ============= drm_damage_helper (21 subtests) ==============
[12:10:41] [PASSED] drm_test_damage_iter_no_damage
[12:10:41] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[12:10:41] [PASSED] drm_test_damage_iter_no_damage_src_moved
[12:10:41] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[12:10:41] [PASSED] drm_test_damage_iter_no_damage_not_visible
[12:10:41] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[12:10:41] [PASSED] drm_test_damage_iter_no_damage_no_fb
[12:10:41] [PASSED] drm_test_damage_iter_simple_damage
[12:10:41] [PASSED] drm_test_damage_iter_single_damage
[12:10:41] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[12:10:41] [PASSED] drm_test_damage_iter_single_damage_outside_src
[12:10:41] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[12:10:41] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[12:10:41] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[12:10:41] [PASSED] drm_test_damage_iter_single_damage_src_moved
[12:10:41] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[12:10:41] [PASSED] drm_test_damage_iter_damage
[12:10:41] [PASSED] drm_test_damage_iter_damage_one_intersect
[12:10:41] [PASSED] drm_test_damage_iter_damage_one_outside
[12:10:41] [PASSED] drm_test_damage_iter_damage_src_moved
[12:10:41] [PASSED] drm_test_damage_iter_damage_not_visible
[12:10:41] ================ [PASSED] drm_damage_helper ================
[12:10:41] ============== drm_dp_mst_helper (3 subtests) ==============
[12:10:41] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[12:10:41] [PASSED] Clock 154000 BPP 30 DSC disabled
[12:10:41] [PASSED] Clock 234000 BPP 30 DSC disabled
[12:10:41] [PASSED] Clock 297000 BPP 24 DSC disabled
[12:10:41] [PASSED] Clock 332880 BPP 24 DSC enabled
[12:10:41] [PASSED] Clock 324540 BPP 24 DSC enabled
[12:10:41] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[12:10:41] ============== drm_test_dp_mst_calc_pbn_div  ===============
[12:10:41] [PASSED] Link rate 2000000 lane count 4
[12:10:41] [PASSED] Link rate 2000000 lane count 2
[12:10:41] [PASSED] Link rate 2000000 lane count 1
[12:10:41] [PASSED] Link rate 1350000 lane count 4
[12:10:41] [PASSED] Link rate 1350000 lane count 2
[12:10:41] [PASSED] Link rate 1350000 lane count 1
[12:10:41] [PASSED] Link rate 1000000 lane count 4
[12:10:41] [PASSED] Link rate 1000000 lane count 2
[12:10:41] [PASSED] Link rate 1000000 lane count 1
[12:10:41] [PASSED] Link rate 810000 lane count 4
[12:10:41] [PASSED] Link rate 810000 lane count 2
[12:10:41] [PASSED] Link rate 810000 lane count 1
[12:10:41] [PASSED] Link rate 540000 lane count 4
[12:10:41] [PASSED] Link rate 540000 lane count 2
[12:10:41] [PASSED] Link rate 540000 lane count 1
[12:10:41] [PASSED] Link rate 270000 lane count 4
[12:10:41] [PASSED] Link rate 270000 lane count 2
[12:10:41] [PASSED] Link rate 270000 lane count 1
[12:10:41] [PASSED] Link rate 162000 lane count 4
[12:10:41] [PASSED] Link rate 162000 lane count 2
[12:10:41] [PASSED] Link rate 162000 lane count 1
[12:10:41] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[12:10:41] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[12:10:41] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[12:10:41] [PASSED] DP_POWER_UP_PHY with port number
[12:10:41] [PASSED] DP_POWER_DOWN_PHY with port number
[12:10:41] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[12:10:41] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[12:10:41] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[12:10:41] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[12:10:41] [PASSED] DP_QUERY_PAYLOAD with port number
[12:10:41] [PASSED] DP_QUERY_PAYLOAD with VCPI
[12:10:41] [PASSED] DP_REMOTE_DPCD_READ with port number
[12:10:41] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[12:10:41] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[12:10:41] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[12:10:41] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[12:10:41] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[12:10:41] [PASSED] DP_REMOTE_I2C_READ with port number
[12:10:41] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[12:10:41] [PASSED] DP_REMOTE_I2C_READ with transactions array
[12:10:41] [PASSED] DP_REMOTE_I2C_WRITE with port number
[12:10:41] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[12:10:41] [PASSED] DP_REMOTE_I2C_WRITE with data array
[12:10:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[12:10:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[12:10:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[12:10:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[12:10:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[12:10:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[12:10:41] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[12:10:41] ================ [PASSED] drm_dp_mst_helper ================
[12:10:41] ================== drm_exec (7 subtests) ===================
[12:10:41] [PASSED] sanitycheck
[12:10:41] [PASSED] test_lock
[12:10:41] [PASSED] test_lock_unlock
[12:10:41] [PASSED] test_duplicates
[12:10:41] [PASSED] test_prepare
[12:10:41] [PASSED] test_prepare_array
[12:10:41] [PASSED] test_multiple_loops
[12:10:41] ==================== [PASSED] drm_exec =====================
[12:10:41] =========== drm_format_helper_test (17 subtests) ===========
[12:10:41] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[12:10:41] [PASSED] single_pixel_source_buffer
[12:10:41] [PASSED] single_pixel_clip_rectangle
[12:10:41] [PASSED] well_known_colors
[12:10:41] [PASSED] destination_pitch
[12:10:41] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[12:10:41] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[12:10:41] [PASSED] single_pixel_source_buffer
[12:10:41] [PASSED] single_pixel_clip_rectangle
[12:10:41] [PASSED] well_known_colors
[12:10:41] [PASSED] destination_pitch
[12:10:41] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[12:10:41] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[12:10:41] [PASSED] single_pixel_source_buffer
[12:10:41] [PASSED] single_pixel_clip_rectangle
[12:10:41] [PASSED] well_known_colors
[12:10:41] [PASSED] destination_pitch
[12:10:41] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[12:10:41] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[12:10:41] [PASSED] single_pixel_source_buffer
[12:10:41] [PASSED] single_pixel_clip_rectangle
[12:10:41] [PASSED] well_known_colors
[12:10:41] [PASSED] destination_pitch
[12:10:41] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[12:10:41] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[12:10:41] [PASSED] single_pixel_source_buffer
[12:10:41] [PASSED] single_pixel_clip_rectangle
[12:10:41] [PASSED] well_known_colors
[12:10:41] [PASSED] destination_pitch
[12:10:41] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[12:10:41] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[12:10:41] [PASSED] single_pixel_source_buffer
[12:10:41] [PASSED] single_pixel_clip_rectangle
[12:10:41] [PASSED] well_known_colors
[12:10:41] [PASSED] destination_pitch
[12:10:41] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[12:10:41] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[12:10:41] [PASSED] single_pixel_source_buffer
[12:10:41] [PASSED] single_pixel_clip_rectangle
[12:10:41] [PASSED] well_known_colors
[12:10:41] [PASSED] destination_pitch
[12:10:41] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[12:10:41] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[12:10:41] [PASSED] single_pixel_source_buffer
[12:10:41] [PASSED] single_pixel_clip_rectangle
[12:10:41] [PASSED] well_known_colors
[12:10:41] [PASSED] destination_pitch
[12:10:41] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[12:10:41] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[12:10:41] [PASSED] single_pixel_source_buffer
[12:10:41] [PASSED] single_pixel_clip_rectangle
[12:10:41] [PASSED] well_known_colors
[12:10:41] [PASSED] destination_pitch
[12:10:41] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[12:10:41] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[12:10:41] [PASSED] single_pixel_source_buffer
[12:10:41] [PASSED] single_pixel_clip_rectangle
[12:10:41] [PASSED] well_known_colors
[12:10:41] [PASSED] destination_pitch
[12:10:41] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[12:10:41] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[12:10:41] [PASSED] single_pixel_source_buffer
[12:10:41] [PASSED] single_pixel_clip_rectangle
[12:10:41] [PASSED] well_known_colors
[12:10:41] [PASSED] destination_pitch
[12:10:41] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[12:10:41] ============== drm_test_fb_xrgb8888_to_mono  ===============
[12:10:41] [PASSED] single_pixel_source_buffer
[12:10:41] [PASSED] single_pixel_clip_rectangle
[12:10:41] [PASSED] well_known_colors
[12:10:41] [PASSED] destination_pitch
[12:10:41] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[12:10:41] ==================== drm_test_fb_swab  =====================
[12:10:41] [PASSED] single_pixel_source_buffer
[12:10:41] [PASSED] single_pixel_clip_rectangle
[12:10:41] [PASSED] well_known_colors
[12:10:41] [PASSED] destination_pitch
[12:10:41] ================ [PASSED] drm_test_fb_swab =================
[12:10:41] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[12:10:41] [PASSED] single_pixel_source_buffer
[12:10:41] [PASSED] single_pixel_clip_rectangle
[12:10:41] [PASSED] well_known_colors
[12:10:41] [PASSED] destination_pitch
[12:10:41] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[12:10:41] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[12:10:41] [PASSED] single_pixel_source_buffer
[12:10:41] [PASSED] single_pixel_clip_rectangle
[12:10:41] [PASSED] well_known_colors
[12:10:41] [PASSED] destination_pitch
[12:10:41] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[12:10:41] ================= drm_test_fb_clip_offset  =================
[12:10:41] [PASSED] pass through
[12:10:41] [PASSED] horizontal offset
[12:10:41] [PASSED] vertical offset
[12:10:41] [PASSED] horizontal and vertical offset
[12:10:41] [PASSED] horizontal offset (custom pitch)
[12:10:41] [PASSED] vertical offset (custom pitch)
[12:10:41] [PASSED] horizontal and vertical offset (custom pitch)
[12:10:41] ============= [PASSED] drm_test_fb_clip_offset =============
[12:10:41] =================== drm_test_fb_memcpy  ====================
[12:10:41] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[12:10:41] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[12:10:41] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[12:10:41] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[12:10:41] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[12:10:41] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[12:10:41] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[12:10:41] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[12:10:41] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[12:10:41] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[12:10:41] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[12:10:41] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[12:10:41] =============== [PASSED] drm_test_fb_memcpy ================
[12:10:41] ============= [PASSED] drm_format_helper_test ==============
[12:10:41] ================= drm_format (18 subtests) =================
[12:10:41] [PASSED] drm_test_format_block_width_invalid
[12:10:41] [PASSED] drm_test_format_block_width_one_plane
[12:10:41] [PASSED] drm_test_format_block_width_two_plane
[12:10:41] [PASSED] drm_test_format_block_width_three_plane
[12:10:41] [PASSED] drm_test_format_block_width_tiled
[12:10:41] [PASSED] drm_test_format_block_height_invalid
[12:10:41] [PASSED] drm_test_format_block_height_one_plane
[12:10:41] [PASSED] drm_test_format_block_height_two_plane
[12:10:41] [PASSED] drm_test_format_block_height_three_plane
[12:10:41] [PASSED] drm_test_format_block_height_tiled
[12:10:41] [PASSED] drm_test_format_min_pitch_invalid
[12:10:41] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[12:10:41] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[12:10:41] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[12:10:41] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[12:10:41] [PASSED] drm_test_format_min_pitch_two_plane
[12:10:41] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[12:10:41] [PASSED] drm_test_format_min_pitch_tiled
[12:10:41] =================== [PASSED] drm_format ====================
[12:10:41] ============== drm_framebuffer (10 subtests) ===============
[12:10:41] ========== drm_test_framebuffer_check_src_coords  ==========
[12:10:41] [PASSED] Success: source fits into fb
[12:10:41] [PASSED] Fail: overflowing fb with x-axis coordinate
[12:10:41] [PASSED] Fail: overflowing fb with y-axis coordinate
[12:10:41] [PASSED] Fail: overflowing fb with source width
[12:10:41] [PASSED] Fail: overflowing fb with source height
[12:10:41] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[12:10:41] [PASSED] drm_test_framebuffer_cleanup
[12:10:41] =============== drm_test_framebuffer_create  ===============
[12:10:41] [PASSED] ABGR8888 normal sizes
[12:10:41] [PASSED] ABGR8888 max sizes
[12:10:41] [PASSED] ABGR8888 pitch greater than min required
[12:10:41] [PASSED] ABGR8888 pitch less than min required
[12:10:41] [PASSED] ABGR8888 Invalid width
[12:10:41] [PASSED] ABGR8888 Invalid buffer handle
[12:10:41] [PASSED] No pixel format
[12:10:41] [PASSED] ABGR8888 Width 0
[12:10:41] [PASSED] ABGR8888 Height 0
[12:10:41] [PASSED] ABGR8888 Out of bound height * pitch combination
[12:10:41] [PASSED] ABGR8888 Large buffer offset
[12:10:41] [PASSED] ABGR8888 Buffer offset for inexistent plane
[12:10:41] [PASSED] ABGR8888 Invalid flag
[12:10:41] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[12:10:41] [PASSED] ABGR8888 Valid buffer modifier
[12:10:41] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[12:10:41] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[12:10:41] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[12:10:41] [PASSED] NV12 Normal sizes
[12:10:41] [PASSED] NV12 Max sizes
[12:10:41] [PASSED] NV12 Invalid pitch
[12:10:41] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[12:10:41] [PASSED] NV12 different  modifier per-plane
[12:10:41] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[12:10:41] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[12:10:41] [PASSED] NV12 Modifier for inexistent plane
[12:10:41] [PASSED] NV12 Handle for inexistent plane
[12:10:41] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[12:10:41] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[12:10:41] [PASSED] YVU420 Normal sizes
[12:10:41] [PASSED] YVU420 Max sizes
[12:10:41] [PASSED] YVU420 Invalid pitch
[12:10:41] [PASSED] YVU420 Different pitches
[12:10:41] [PASSED] YVU420 Different buffer offsets/pitches
[12:10:41] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[12:10:41] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[12:10:41] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[12:10:41] [PASSED] YVU420 Valid modifier
[12:10:41] [PASSED] YVU420 Different modifiers per plane
[12:10:41] [PASSED] YVU420 Modifier for inexistent plane
[12:10:41] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[12:10:41] [PASSED] X0L2 Normal sizes
[12:10:41] [PASSED] X0L2 Max sizes
[12:10:41] [PASSED] X0L2 Invalid pitch
[12:10:41] [PASSED] X0L2 Pitch greater than minimum required
[12:10:41] [PASSED] X0L2 Handle for inexistent plane
[12:10:41] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[12:10:41] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[12:10:41] [PASSED] X0L2 Valid modifier
[12:10:41] [PASSED] X0L2 Modifier for inexistent plane
[12:10:41] =========== [PASSED] drm_test_framebuffer_create ===========
[12:10:41] [PASSED] drm_test_framebuffer_free
[12:10:41] [PASSED] drm_test_framebuffer_init
[12:10:41] [PASSED] drm_test_framebuffer_init_bad_format
[12:10:41] [PASSED] drm_test_framebuffer_init_dev_mismatch
[12:10:41] [PASSED] drm_test_framebuffer_lookup
[12:10:41] [PASSED] drm_test_framebuffer_lookup_inexistent
[12:10:41] [PASSED] drm_test_framebuffer_modifiers_not_supported
[12:10:41] ================= [PASSED] drm_framebuffer =================
[12:10:41] ================ drm_gem_shmem (8 subtests) ================
[12:10:41] [PASSED] drm_gem_shmem_test_obj_create
[12:10:41] [PASSED] drm_gem_shmem_test_obj_create_private
[12:10:41] [PASSED] drm_gem_shmem_test_pin_pages
[12:10:41] [PASSED] drm_gem_shmem_test_vmap
[12:10:41] [PASSED] drm_gem_shmem_test_get_sg_table
[12:10:41] [PASSED] drm_gem_shmem_test_get_pages_sgt
[12:10:41] [PASSED] drm_gem_shmem_test_madvise
[12:10:41] [PASSED] drm_gem_shmem_test_purge
[12:10:41] ================== [PASSED] drm_gem_shmem ==================
[12:10:41] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[12:10:41] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[12:10:41] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[12:10:41] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[12:10:41] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[12:10:41] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[12:10:41] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[12:10:41] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[12:10:41] [PASSED] Automatic
[12:10:41] [PASSED] Full
[12:10:41] [PASSED] Limited 16:235
[12:10:41] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[12:10:41] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[12:10:41] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[12:10:41] [PASSED] drm_test_check_disable_connector
[12:10:41] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[12:10:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[12:10:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[12:10:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[12:10:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[12:10:41] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[12:10:41] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[12:10:41] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[12:10:41] [PASSED] drm_test_check_output_bpc_dvi
[12:10:41] [PASSED] drm_test_check_output_bpc_format_vic_1
[12:10:41] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[12:10:41] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[12:10:41] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[12:10:41] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[12:10:41] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[12:10:41] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[12:10:41] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[12:10:41] ============ drm_test_check_hdmi_color_format  =============
[12:10:41] [PASSED] AUTO -> RGB
[12:10:41] [PASSED] YCBCR422 -> YUV422
[12:10:41] [PASSED] YCBCR420 -> YUV420
[12:10:41] [PASSED] YCBCR444 -> YUV444
[12:10:41] [PASSED] RGB -> RGB
[12:10:41] ======== [PASSED] drm_test_check_hdmi_color_format =========
[12:10:41] ======== drm_test_check_hdmi_color_format_420_only  ========
[12:10:41] [PASSED] RGB should fail
[12:10:41] [PASSED] YUV444 should fail
[12:10:41] [PASSED] YUV422 should fail
[12:10:41] [PASSED] YUV420 should work
[12:10:41] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[12:10:41] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[12:10:41] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[12:10:41] [PASSED] drm_test_check_broadcast_rgb_value
[12:10:41] [PASSED] drm_test_check_bpc_8_value
[12:10:41] [PASSED] drm_test_check_bpc_10_value
[12:10:41] [PASSED] drm_test_check_bpc_12_value
[12:10:41] [PASSED] drm_test_check_format_value
[12:10:41] [PASSED] drm_test_check_tmds_char_value
[12:10:41] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[12:10:41] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[12:10:41] [PASSED] drm_test_check_mode_valid
[12:10:41] [PASSED] drm_test_check_mode_valid_reject
[12:10:41] [PASSED] drm_test_check_mode_valid_reject_rate
[12:10:41] [PASSED] drm_test_check_mode_valid_reject_max_clock
[12:10:41] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[12:10:41] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[12:10:41] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[12:10:41] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[12:10:41] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[12:10:41] [PASSED] drm_test_check_infoframes
[12:10:41] [PASSED] drm_test_check_reject_avi_infoframe
[12:10:41] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[12:10:41] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[12:10:41] [PASSED] drm_test_check_reject_audio_infoframe
[12:10:41] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[12:10:41] ================= drm_managed (2 subtests) =================
[12:10:41] [PASSED] drm_test_managed_release_action
[12:10:41] [PASSED] drm_test_managed_run_action
[12:10:41] =================== [PASSED] drm_managed ===================
[12:10:41] =================== drm_mm (6 subtests) ====================
[12:10:41] [PASSED] drm_test_mm_init
[12:10:41] [PASSED] drm_test_mm_debug
[12:10:41] [PASSED] drm_test_mm_align32
[12:10:41] [PASSED] drm_test_mm_align64
[12:10:41] [PASSED] drm_test_mm_lowest
[12:10:41] [PASSED] drm_test_mm_highest
[12:10:41] ===================== [PASSED] drm_mm ======================
[12:10:41] ============= drm_modes_analog_tv (5 subtests) =============
[12:10:41] [PASSED] drm_test_modes_analog_tv_mono_576i
[12:10:41] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[12:10:41] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[12:10:41] [PASSED] drm_test_modes_analog_tv_pal_576i
[12:10:41] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[12:10:41] =============== [PASSED] drm_modes_analog_tv ===============
[12:10:41] ============== drm_plane_helper (2 subtests) ===============
[12:10:41] =============== drm_test_check_plane_state  ================
[12:10:41] [PASSED] clipping_simple
[12:10:41] [PASSED] clipping_rotate_reflect
[12:10:41] [PASSED] positioning_simple
[12:10:41] [PASSED] upscaling
[12:10:41] [PASSED] downscaling
[12:10:41] [PASSED] rounding1
[12:10:41] [PASSED] rounding2
[12:10:41] [PASSED] rounding3
[12:10:41] [PASSED] rounding4
[12:10:41] =========== [PASSED] drm_test_check_plane_state ============
[12:10:41] =========== drm_test_check_invalid_plane_state  ============
[12:10:41] [PASSED] positioning_invalid
[12:10:41] [PASSED] upscaling_invalid
[12:10:41] [PASSED] downscaling_invalid
[12:10:41] ======= [PASSED] drm_test_check_invalid_plane_state ========
[12:10:41] ================ [PASSED] drm_plane_helper =================
[12:10:41] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[12:10:41] ====== drm_test_connector_helper_tv_get_modes_check  =======
[12:10:41] [PASSED] None
[12:10:41] [PASSED] PAL
[12:10:41] [PASSED] NTSC
[12:10:41] [PASSED] Both, NTSC Default
[12:10:41] [PASSED] Both, PAL Default
[12:10:41] [PASSED] Both, NTSC Default, with PAL on command-line
[12:10:41] [PASSED] Both, PAL Default, with NTSC on command-line
[12:10:41] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[12:10:41] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[12:10:41] ================== drm_rect (9 subtests) ===================
[12:10:41] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[12:10:41] [PASSED] drm_test_rect_clip_scaled_not_clipped
[12:10:41] [PASSED] drm_test_rect_clip_scaled_clipped
[12:10:41] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[12:10:41] ================= drm_test_rect_intersect  =================
[12:10:41] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[12:10:41] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[12:10:41] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[12:10:41] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[12:10:41] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[12:10:41] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[12:10:41] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[12:10:41] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[12:10:41] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[12:10:41] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[12:10:41] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[12:10:41] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[12:10:41] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[12:10:41] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[12:10:41] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[12:10:41] ============= [PASSED] drm_test_rect_intersect =============
[12:10:41] ================ drm_test_rect_calc_hscale  ================
[12:10:41] [PASSED] normal use
[12:10:41] [PASSED] out of max range
[12:10:41] [PASSED] out of min range
[12:10:41] [PASSED] zero dst
[12:10:41] [PASSED] negative src
[12:10:41] [PASSED] negative dst
[12:10:41] ============ [PASSED] drm_test_rect_calc_hscale ============
[12:10:41] ================ drm_test_rect_calc_vscale  ================
[12:10:41] [PASSED] normal use
[12:10:41] [PASSED] out of max range
[12:10:41] [PASSED] out of min range
[12:10:41] [PASSED] zero dst
[12:10:41] [PASSED] negative src
[12:10:41] [PASSED] negative dst
[12:10:41] ============ [PASSED] drm_test_rect_calc_vscale ============
[12:10:41] ================== drm_test_rect_rotate  ===================
[12:10:41] [PASSED] reflect-x
[12:10:41] [PASSED] reflect-y
[12:10:41] [PASSED] rotate-0
[12:10:41] [PASSED] rotate-90
[12:10:41] [PASSED] rotate-180
[12:10:41] [PASSED] rotate-270
[12:10:41] ============== [PASSED] drm_test_rect_rotate ===============
[12:10:41] ================ drm_test_rect_rotate_inv  =================
[12:10:41] [PASSED] reflect-x
[12:10:41] [PASSED] reflect-y
[12:10:41] [PASSED] rotate-0
[12:10:41] [PASSED] rotate-90
[12:10:41] [PASSED] rotate-180
[12:10:41] [PASSED] rotate-270
[12:10:41] ============ [PASSED] drm_test_rect_rotate_inv =============
[12:10:41] ==================== [PASSED] drm_rect =====================
[12:10:41] ============ drm_sysfb_modeset_test (1 subtest) ============
[12:10:41] ============ drm_test_sysfb_build_fourcc_list  =============
[12:10:41] [PASSED] no native formats
[12:10:41] [PASSED] XRGB8888 as native format
[12:10:41] [PASSED] remove duplicates
[12:10:41] [PASSED] convert alpha formats
[12:10:41] [PASSED] random formats
[12:10:41] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[12:10:41] ============= [PASSED] drm_sysfb_modeset_test ==============
[12:10:41] ================== drm_fixp (2 subtests) ===================
[12:10:41] [PASSED] drm_test_int2fixp
[12:10:41] [PASSED] drm_test_sm2fixp
[12:10:41] ==================== [PASSED] drm_fixp =====================
[12:10:41] ============================================================
[12:10:41] Testing complete. Ran 637 tests: passed: 637
[12:10:41] Elapsed time: 26.647s total, 1.810s configuring, 24.671s building, 0.149s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[12:10:41] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:10:43] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:10:53] Starting KUnit Kernel (1/1)...
[12:10:53] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:10:53] ================= ttm_device (5 subtests) ==================
[12:10:53] [PASSED] ttm_device_init_basic
[12:10:53] [PASSED] ttm_device_init_multiple
[12:10:53] [PASSED] ttm_device_fini_basic
[12:10:53] [PASSED] ttm_device_init_no_vma_man
[12:10:53] ================== ttm_device_init_pools  ==================
[12:10:53] [PASSED] No DMA allocations, no DMA32 required
[12:10:53] [PASSED] DMA allocations, DMA32 required
[12:10:53] [PASSED] No DMA allocations, DMA32 required
[12:10:53] [PASSED] DMA allocations, no DMA32 required
[12:10:53] ============== [PASSED] ttm_device_init_pools ==============
[12:10:53] =================== [PASSED] ttm_device ====================
[12:10:53] ================== ttm_pool (8 subtests) ===================
[12:10:53] ================== ttm_pool_alloc_basic  ===================
[12:10:53] [PASSED] One page
[12:10:53] [PASSED] More than one page
[12:10:53] [PASSED] Above the allocation limit
[12:10:53] [PASSED] One page, with coherent DMA mappings enabled
[12:10:53] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:10:53] ============== [PASSED] ttm_pool_alloc_basic ===============
[12:10:53] ============== ttm_pool_alloc_basic_dma_addr  ==============
[12:10:53] [PASSED] One page
[12:10:53] [PASSED] More than one page
[12:10:53] [PASSED] Above the allocation limit
[12:10:53] [PASSED] One page, with coherent DMA mappings enabled
[12:10:53] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:10:53] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[12:10:53] [PASSED] ttm_pool_alloc_order_caching_match
[12:10:53] [PASSED] ttm_pool_alloc_caching_mismatch
[12:10:53] [PASSED] ttm_pool_alloc_order_mismatch
[12:10:53] [PASSED] ttm_pool_free_dma_alloc
[12:10:53] [PASSED] ttm_pool_free_no_dma_alloc
[12:10:53] [PASSED] ttm_pool_fini_basic
[12:10:53] ==================== [PASSED] ttm_pool =====================
[12:10:53] ================ ttm_resource (8 subtests) =================
[12:10:53] ================= ttm_resource_init_basic  =================
[12:10:53] [PASSED] Init resource in TTM_PL_SYSTEM
[12:10:53] [PASSED] Init resource in TTM_PL_VRAM
[12:10:53] [PASSED] Init resource in a private placement
[12:10:53] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[12:10:53] ============= [PASSED] ttm_resource_init_basic =============
[12:10:53] [PASSED] ttm_resource_init_pinned
[12:10:53] [PASSED] ttm_resource_fini_basic
[12:10:53] [PASSED] ttm_resource_manager_init_basic
[12:10:53] [PASSED] ttm_resource_manager_usage_basic
[12:10:53] [PASSED] ttm_resource_manager_set_used_basic
[12:10:53] [PASSED] ttm_sys_man_alloc_basic
[12:10:53] [PASSED] ttm_sys_man_free_basic
[12:10:53] ================== [PASSED] ttm_resource ===================
[12:10:53] =================== ttm_tt (15 subtests) ===================
[12:10:53] ==================== ttm_tt_init_basic  ====================
[12:10:53] [PASSED] Page-aligned size
[12:10:53] [PASSED] Extra pages requested
[12:10:53] ================ [PASSED] ttm_tt_init_basic ================
[12:10:53] [PASSED] ttm_tt_init_misaligned
[12:10:53] [PASSED] ttm_tt_fini_basic
[12:10:53] [PASSED] ttm_tt_fini_sg
[12:10:53] [PASSED] ttm_tt_fini_shmem
[12:10:53] [PASSED] ttm_tt_create_basic
[12:10:53] [PASSED] ttm_tt_create_invalid_bo_type
[12:10:53] [PASSED] ttm_tt_create_ttm_exists
[12:10:53] [PASSED] ttm_tt_create_failed
[12:10:53] [PASSED] ttm_tt_destroy_basic
[12:10:53] [PASSED] ttm_tt_populate_null_ttm
[12:10:53] [PASSED] ttm_tt_populate_populated_ttm
[12:10:53] [PASSED] ttm_tt_unpopulate_basic
[12:10:53] [PASSED] ttm_tt_unpopulate_empty_ttm
[12:10:53] [PASSED] ttm_tt_swapin_basic
[12:10:53] ===================== [PASSED] ttm_tt ======================
[12:10:53] =================== ttm_bo (14 subtests) ===================
[12:10:53] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[12:10:53] [PASSED] Cannot be interrupted and sleeps
[12:10:53] [PASSED] Cannot be interrupted, locks straight away
[12:10:53] [PASSED] Can be interrupted, sleeps
[12:10:53] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[12:10:53] [PASSED] ttm_bo_reserve_locked_no_sleep
[12:10:53] [PASSED] ttm_bo_reserve_no_wait_ticket
[12:10:53] [PASSED] ttm_bo_reserve_double_resv
[12:10:53] [PASSED] ttm_bo_reserve_interrupted
[12:10:53] [PASSED] ttm_bo_reserve_deadlock
[12:10:53] [PASSED] ttm_bo_unreserve_basic
[12:10:53] [PASSED] ttm_bo_unreserve_pinned
[12:10:53] [PASSED] ttm_bo_unreserve_bulk
[12:10:53] [PASSED] ttm_bo_fini_basic
[12:10:53] [PASSED] ttm_bo_fini_shared_resv
[12:10:53] [PASSED] ttm_bo_pin_basic
[12:10:53] [PASSED] ttm_bo_pin_unpin_resource
[12:10:53] [PASSED] ttm_bo_multiple_pin_one_unpin
[12:10:53] ===================== [PASSED] ttm_bo ======================
[12:10:53] ============== ttm_bo_validate (22 subtests) ===============
[12:10:53] ============== ttm_bo_init_reserved_sys_man  ===============
[12:10:53] [PASSED] Buffer object for userspace
[12:10:53] [PASSED] Kernel buffer object
[12:10:53] [PASSED] Shared buffer object
[12:10:53] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[12:10:53] ============== ttm_bo_init_reserved_mock_man  ==============
[12:10:53] [PASSED] Buffer object for userspace
[12:10:53] [PASSED] Kernel buffer object
[12:10:53] [PASSED] Shared buffer object
[12:10:53] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[12:10:53] [PASSED] ttm_bo_init_reserved_resv
[12:10:53] ================== ttm_bo_validate_basic  ==================
[12:10:53] [PASSED] Buffer object for userspace
[12:10:53] [PASSED] Kernel buffer object
[12:10:53] [PASSED] Shared buffer object
[12:10:53] ============== [PASSED] ttm_bo_validate_basic ==============
[12:10:53] [PASSED] ttm_bo_validate_invalid_placement
[12:10:53] ============= ttm_bo_validate_same_placement  ==============
[12:10:53] [PASSED] System manager
[12:10:53] [PASSED] VRAM manager
[12:10:53] ========= [PASSED] ttm_bo_validate_same_placement ==========
[12:10:53] [PASSED] ttm_bo_validate_failed_alloc
[12:10:53] [PASSED] ttm_bo_validate_pinned
[12:10:53] [PASSED] ttm_bo_validate_busy_placement
[12:10:53] ================ ttm_bo_validate_multihop  =================
[12:10:53] [PASSED] Buffer object for userspace
[12:10:53] [PASSED] Kernel buffer object
[12:10:53] [PASSED] Shared buffer object
[12:10:53] ============ [PASSED] ttm_bo_validate_multihop =============
[12:10:53] ========== ttm_bo_validate_no_placement_signaled  ==========
[12:10:53] [PASSED] Buffer object in system domain, no page vector
[12:10:53] [PASSED] Buffer object in system domain with an existing page vector
[12:10:53] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[12:10:53] ======== ttm_bo_validate_no_placement_not_signaled  ========
[12:10:53] [PASSED] Buffer object for userspace
[12:10:53] [PASSED] Kernel buffer object
[12:10:53] [PASSED] Shared buffer object
[12:10:53] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[12:10:53] [PASSED] ttm_bo_validate_move_fence_signaled
[12:10:53] ========= ttm_bo_validate_move_fence_not_signaled  =========
[12:10:53] [PASSED] Waits for GPU
[12:10:53] [PASSED] Tries to lock straight away
[12:10:53] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[12:10:53] [PASSED] ttm_bo_validate_swapout
[12:10:53] [PASSED] ttm_bo_validate_happy_evict
[12:10:53] [PASSED] ttm_bo_validate_all_pinned_evict
[12:10:53] [PASSED] ttm_bo_validate_allowed_only_evict
[12:10:53] [PASSED] ttm_bo_validate_deleted_evict
[12:10:53] [PASSED] ttm_bo_validate_busy_domain_evict
[12:10:53] [PASSED] ttm_bo_validate_evict_gutting
[12:10:53] [PASSED] ttm_bo_validate_recrusive_evict
[12:10:53] ================= [PASSED] ttm_bo_validate =================
[12:10:53] ============================================================
[12:10:53] Testing complete. Ran 102 tests: passed: 102
[12:10:53] Elapsed time: 11.972s total, 1.831s configuring, 9.927s building, 0.179s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/xe/sysctrl: Add fwctl support for System Controller

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 918 bytes --]

== Series Details ==

Series: drm/xe/sysctrl: Add fwctl support for System Controller
URL   : https://patchwork.freedesktop.org/series/171728/
State : success

== Summary ==

CI Bug Log - changes from xe-5552-8d11ccdc98daac5e969243b42907fd060a650091_BAT -> xe-pw-171728v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (15 -> 14)
------------------------------

  Missing    (1): bat-wcl-2 


Changes
-------

  No changes found


Build changes
-------------

  * IGT: IGT_9041 -> IGT_9043
  * Linux: xe-5552-8d11ccdc98daac5e969243b42907fd060a650091 -> xe-pw-171728v1

  IGT_9041: 9041
  IGT_9043: 9043
  xe-5552-8d11ccdc98daac5e969243b42907fd060a650091: 8d11ccdc98daac5e969243b42907fd060a650091
  xe-pw-171728v1: 171728v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/index.html

[-- Attachment #2: Type: text/html, Size: 1480 bytes --]

✗ Xe.CI.FULL: failure for drm/xe/sysctrl: Add fwctl support for System Controller

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 23056 bytes --]

== Series Details ==

Series: drm/xe/sysctrl: Add fwctl support for System Controller
URL   : https://patchwork.freedesktop.org/series/171728/
State : failure

== Summary ==

CI Bug Log - changes from xe-5552-8d11ccdc98daac5e969243b42907fd060a650091_FULL -> xe-pw-171728v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-171728v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-171728v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-171728v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@sriov_basic@pf-unbind-with-vfs-enabled-numvfs-all:
    - shard-bmg:          NOTRUN -> [ABORT][1]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-bmg-5/igt@sriov_basic@pf-unbind-with-vfs-enabled-numvfs-all.html
    - shard-lnl:          NOTRUN -> [SKIP][2] +1 other test skip
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-6/igt@sriov_basic@pf-unbind-with-vfs-enabled-numvfs-all.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [PASS][3] -> [ABORT][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5552-8d11ccdc98daac5e969243b42907fd060a650091/shard-bmg-9/igt@xe_evict@evict-mixed-many-threads-small.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-bmg-10/igt@xe_evict@evict-mixed-many-threads-small.html

  
Known issues
------------

  Here are the changes found in xe-pw-171728v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@intel_hwmon@hwmon-write:
    - shard-bmg:          [PASS][5] -> [FAIL][6] ([Intel XE#8583])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5552-8d11ccdc98daac5e969243b42907fd060a650091/shard-bmg-6/igt@intel_hwmon@hwmon-write.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-bmg-10/igt@intel_hwmon@hwmon-write.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][7] ([Intel XE#3658] / [Intel XE#7360])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-7/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-0:
    - shard-lnl:          NOTRUN -> [SKIP][8] ([Intel XE#1124]) +2 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-6/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html

  * igt@kms_bw@linear-tiling-3-displays-target-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#367])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-5/igt@kms_bw@linear-tiling-3-displays-target-2160x1440p.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][10] ([Intel XE#2887]) +3 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-5/igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_chamelium_hpd@dp-hpd-storm:
    - shard-lnl:          NOTRUN -> [SKIP][11] ([Intel XE#373])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-4/igt@kms_chamelium_hpd@dp-hpd-storm.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-lnl:          NOTRUN -> [SKIP][12] ([Intel XE#307] / [Intel XE#6974])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-4/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_cursor_crc@cursor-sliding-128x42:
    - shard-lnl:          NOTRUN -> [SKIP][13] ([Intel XE#1424]) +1 other test skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-3/igt@kms_cursor_crc@cursor-sliding-128x42.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
    - shard-lnl:          NOTRUN -> [SKIP][14] ([Intel XE#309] / [Intel XE#7343])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-8/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-lnl:          NOTRUN -> [SKIP][15] ([Intel XE#8265])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-5/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_flip@2x-dpms-vs-vblank-race:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#1421])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-1/igt@kms_flip@2x-dpms-vs-vblank-race.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-lnl:          [PASS][17] -> [FAIL][18] ([Intel XE#301] / [Intel XE#3149])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5552-8d11ccdc98daac5e969243b42907fd060a650091/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][19] ([Intel XE#7178] / [Intel XE#7351])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-1/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-msflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][20] ([Intel XE#6312] / [Intel XE#651]) +2 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-7/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@drrshdr-1p-rte:
    - shard-lnl:          NOTRUN -> [SKIP][21] ([Intel XE#6312]) +3 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-1/igt@kms_frontbuffer_tracking@drrshdr-1p-rte.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-spr-indfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][22] ([Intel XE#7905]) +6 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-7/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-pri-shrfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][23] ([Intel XE#7865]) +2 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-5/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-fullscreen:
    - shard-lnl:          NOTRUN -> [SKIP][24] ([Intel XE#656] / [Intel XE#7905]) +6 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-abgr161616f-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#7061])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcpsrhdr-abgr161616f-draw-mmap-wc.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][26] ([Intel XE#7086] / [Intel XE#7390])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-5/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-lnl:          NOTRUN -> [FAIL][27] ([Intel XE#8399])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-2/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-lnl:          NOTRUN -> [SKIP][28] ([Intel XE#2893] / [Intel XE#4608] / [Intel XE#7304])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-7/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#4608])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-7/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#4608] / [Intel XE#7304])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-7/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-b-edp-1.html

  * igt@kms_psr@pr-primary-render:
    - shard-lnl:          NOTRUN -> [SKIP][31] ([Intel XE#1406])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-8/igt@kms_psr@pr-primary-render.html

  * igt@kms_rotation_crc@bad-pixel-format:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-4/igt@kms_rotation_crc@bad-pixel-format.html

  * igt@xe_evict@evict-threads-small-multi-vm:
    - shard-lnl:          NOTRUN -> [SKIP][33] ([Intel XE#6540] / [Intel XE#688]) +2 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-1/igt@xe_evict@evict-threads-small-multi-vm.html

  * igt@xe_exec_balancer@no-exec-virtual-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][34] ([Intel XE#7482]) +2 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-7/igt@xe_exec_balancer@no-exec-virtual-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap:
    - shard-lnl:          NOTRUN -> [SKIP][35] ([Intel XE#1392]) +1 other test skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-8/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap.html

  * igt@xe_exec_fault_mode@many-multi-queue-invalid-fault:
    - shard-lnl:          NOTRUN -> [SKIP][36] ([Intel XE#8374])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-2/igt@xe_exec_fault_mode@many-multi-queue-invalid-fault.html

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][37] ([Intel XE#8364]) +6 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-4/igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-userptr-invalidate.html

  * igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-basic:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#8378]) +2 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-7/igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-basic.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_wopcm_init:
    - shard-bmg:          [PASS][39] -> [ABORT][40] ([Intel XE#8007]) +2 other tests abort
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5552-8d11ccdc98daac5e969243b42907fd060a650091/shard-bmg-3/igt@xe_fault_injection@inject-fault-probe-function-xe_wopcm_init.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-bmg-4/igt@xe_fault_injection@inject-fault-probe-function-xe_wopcm_init.html

  * igt@xe_pat@pat-index-xelp:
    - shard-lnl:          NOTRUN -> [SKIP][41] ([Intel XE#7590] / [Intel XE#977])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-5/igt@xe_pat@pat-index-xelp.html

  * igt@xe_pm@s4-d3cold-basic-exec:
    - shard-lnl:          NOTRUN -> [SKIP][42] ([Intel XE#2284] / [Intel XE#366] / [Intel XE#7370])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-2/igt@xe_pm@s4-d3cold-basic-exec.html

  * igt@xe_sriov_flr@flr-vf1-clear:
    - shard-bmg:          [PASS][43] -> [FAIL][44] ([Intel XE#6569])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5552-8d11ccdc98daac5e969243b42907fd060a650091/shard-bmg-5/igt@xe_sriov_flr@flr-vf1-clear.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-bmg-4/igt@xe_sriov_flr@flr-vf1-clear.html

  * igt@xe_sriov_vram@vf-access-after-resize-down:
    - shard-bmg:          [PASS][45] -> [FAIL][46] ([Intel XE#7992])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5552-8d11ccdc98daac5e969243b42907fd060a650091/shard-bmg-5/igt@xe_sriov_vram@vf-access-after-resize-down.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-bmg-1/igt@xe_sriov_vram@vf-access-after-resize-down.html

  * igt@xe_survivability@i2c-functionality:
    - shard-lnl:          NOTRUN -> [SKIP][47] ([Intel XE#8415])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-4/igt@xe_survivability@i2c-functionality.html

  * igt@xe_vm@overcommit-nonfault-vram-lr-external-nodefer:
    - shard-lnl:          NOTRUN -> [SKIP][48] ([Intel XE#7892])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-7/igt@xe_vm@overcommit-nonfault-vram-lr-external-nodefer.html

  
#### Possible fixes ####

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [FAIL][49] ([Intel XE#7571]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5552-8d11ccdc98daac5e969243b42907fd060a650091/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          [FAIL][51] ([Intel XE#301]) -> [PASS][52] +2 other tests pass
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5552-8d11ccdc98daac5e969243b42907fd060a650091/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-lnl:          [FAIL][53] ([Intel XE#8399]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5552-8d11ccdc98daac5e969243b42907fd060a650091/shard-lnl-4/igt@kms_pm_dc@dc5-psr.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-1/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_setmode@basic@pipe-b-edp-1:
    - shard-lnl:          [FAIL][55] ([Intel XE#8618]) -> [PASS][56] +2 other tests pass
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5552-8d11ccdc98daac5e969243b42907fd060a650091/shard-lnl-2/igt@kms_setmode@basic@pipe-b-edp-1.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-2/igt@kms_setmode@basic@pipe-b-edp-1.html

  * igt@xe_sriov_scheduling@equal-throughput-normal-priority@numvfs-random-gt0-rcs0:
    - shard-bmg:          [FAIL][57] ([Intel XE#7992]) -> [PASS][58] +1 other test pass
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5552-8d11ccdc98daac5e969243b42907fd060a650091/shard-bmg-10/igt@xe_sriov_scheduling@equal-throughput-normal-priority@numvfs-random-gt0-rcs0.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-bmg-10/igt@xe_sriov_scheduling@equal-throughput-normal-priority@numvfs-random-gt0-rcs0.html

  * igt@xe_sriov_scheduling@equal-throughput-normal-priority@numvfs-random-gt1-vcs0:
    - shard-bmg:          [FAIL][59] ([Intel XE#8526]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5552-8d11ccdc98daac5e969243b42907fd060a650091/shard-bmg-10/igt@xe_sriov_scheduling@equal-throughput-normal-priority@numvfs-random-gt1-vcs0.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-bmg-10/igt@xe_sriov_scheduling@equal-throughput-normal-priority@numvfs-random-gt1-vcs0.html

  
#### Warnings ####

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
    - shard-lnl:          [SKIP][61] ([Intel XE#309] / [Intel XE#7343]) -> [SKIP][62] ([Intel XE#309] / [Intel XE#7343] / [Intel XE#7935])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5552-8d11ccdc98daac5e969243b42907fd060a650091/shard-lnl-2/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][63] ([Intel XE#301]) -> [FAIL][64] ([Intel XE#301] / [Intel XE#3149])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5552-8d11ccdc98daac5e969243b42907fd060a650091/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][65] ([Intel XE#2426] / [Intel XE#5848]) -> [FAIL][66] ([Intel XE#1729] / [Intel XE#7424])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5552-8d11ccdc98daac5e969243b42907fd060a650091/shard-bmg-8/igt@kms_tiled_display@basic-test-pattern.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern.html

  * igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add:
    - shard-bmg:          [SKIP][67] ([Intel XE#6281] / [Intel XE#7426]) -> [ABORT][68] ([Intel XE#8007])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5552-8d11ccdc98daac5e969243b42907fd060a650091/shard-bmg-4/igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/shard-bmg-1/igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3658
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#6281]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6281
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6569
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7086]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7086
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7360
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7390
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7426
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7571
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7892]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7892
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#7935]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7935
  [Intel XE#7992]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7992
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8399
  [Intel XE#8415]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8415
  [Intel XE#8526]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8526
  [Intel XE#8583]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8583
  [Intel XE#8618]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8618
  [Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977


Build changes
-------------

  * IGT: IGT_9041 -> IGT_9043
  * Linux: xe-5552-8d11ccdc98daac5e969243b42907fd060a650091 -> xe-pw-171728v1

  IGT_9041: 9041
  IGT_9043: 9043
  xe-5552-8d11ccdc98daac5e969243b42907fd060a650091: 8d11ccdc98daac5e969243b42907fd060a650091
  xe-pw-171728v1: 171728v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171728v1/index.html

[-- Attachment #2: Type: text/html, Size: 25817 bytes --]

Re: [PATCH v2 2/2] drm/xe/sysctrl: Add fwctl support for System Controller

[Umesh Nerlige Ramappa]

On Thu, Aug 06, 2026 at 05:03:12AM -0700, Anoop, Vijay wrote:
>From: Anoop Vijay <anoop.c.vijay@intel.com>
>
>Add fwctl support for Xe System Controller (sysctrl), a
>firmware-managed entity that provides platform-level control and
>coordination on Intel Xe3p discrete GPUs.
>
>Register a XE_SYSCTRL device to allow userspace to query sysctrl
>capabilities and issue RPCs through /dev/fwctl/fwctlN. Initial
>RPCs support ECC status queries and RAS error injection.
>
>Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
>---
>v2: (Rodrigo)
>- Rename FWCTL_DEVICE_TYPE_XE to FWCTL_DEVICE_TYPE_XE_SYSCTRL, one type
>  per firmware instead of a shared Xe-wide type
>- Rename xe.h to xe_sysctrl.h to match
>- Squash uapi and type definitions into a single patch
>- Replace validate_scope() with explicit per-op scope/capability checks
>  in xe_sysctrl_fwctl_rpc()
>---
> Documentation/userspace-api/fwctl/index.rst   |   1 +
> .../userspace-api/fwctl/xe_sysctrl.rst        | 120 +++++++++
> drivers/gpu/drm/xe/Kconfig                    |   1 +
> drivers/gpu/drm/xe/Makefile                   |   1 +
> drivers/gpu/drm/xe/xe_device.c                |   5 +
> drivers/gpu/drm/xe/xe_sysctrl_fwctl.c         | 251 ++++++++++++++++++
> drivers/gpu/drm/xe/xe_sysctrl_fwctl.h         |  13 +
> drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h |  86 ++++++
> include/uapi/fwctl/fwctl.h                    |   1 +
> include/uapi/fwctl/xe_sysctrl.h               | 117 ++++++++
> 10 files changed, 596 insertions(+)
> create mode 100644 Documentation/userspace-api/fwctl/xe_sysctrl.rst
> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_fwctl.c
> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_fwctl.h
> create mode 100644 include/uapi/fwctl/xe_sysctrl.h
>
>diff --git a/Documentation/userspace-api/fwctl/index.rst b/Documentation/userspace-api/fwctl/index.rst
>index 8062f7629654..f6fca11e6aac 100644
>--- a/Documentation/userspace-api/fwctl/index.rst
>+++ b/Documentation/userspace-api/fwctl/index.rst
>@@ -13,3 +13,4 @@ to securely construct and execute RPCs inside device firmware.
>    bnxt_fwctl
>    fwctl-cxl
>    pds_fwctl
>+   xe_sysctrl
>diff --git a/Documentation/userspace-api/fwctl/xe_sysctrl.rst b/Documentation/userspace-api/fwctl/xe_sysctrl.rst
>new file mode 100644
>index 000000000000..6dfc9e70b683
>--- /dev/null
>+++ b/Documentation/userspace-api/fwctl/xe_sysctrl.rst
>@@ -0,0 +1,120 @@
>+.. SPDX-License-Identifier: GPL-2.0
>+
>+=======================
>+fwctl xe_sysctrl driver
>+=======================
>+
>+:Author: Intel Corporation
>+
>+Overview
>+========
>+
>+The Xe System Controller (sysctrl) firmware exposes a fwctl service that
>+the xe driver registers as a ``FWCTL_DEVICE_TYPE_XE_SYSCTRL`` device.
>+Userspace opens the resulting ``/dev/fwctl/fwctlN`` node to query ECC
>+status and RAS error injection capabilities and to issue RAS error
>+injection requests to the sysctrl firmware.
>+
>+xe_sysctrl User API
>+====================
>+
>+.. kernel-doc:: include/uapi/fwctl/xe_sysctrl.h
>+
>+1. Driver info query
>+---------------------
>+
>+The application issues ``FWCTL_INFO`` to retrieve a
>+``struct fwctl_info_xe_sysctrl`` and inspect ``uctx_caps`` to determine
>+which of the ``FWCTL_XE_SYSCTRL_CAP_*`` capabilities are available on this
>+platform and in this security context.
>+
>+2. Send RPC requests
>+---------------------
>+
>+Each RPC uses a single ``struct fwctl_rpc_xe_sysctrl`` as both the
>+``FWCTL_RPC`` ``in`` and ``out`` buffer; the driver fills in ``data`` in
>+place. ``op`` selects one of the ``enum fwctl_xe_sysctrl_op`` operations.
>+The kernel rejects the request if the scope of the ``FWCTL_RPC`` call is
>+lower than the minimum required by the requested ``op``, as documented above.
>+
>+Code example of querying ECC status
>+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>+
>+.. code-block:: c
>+
>+        static int xe_sysctrl_get_ecc(int fd, __u32 *supported, __u32 *enabled)
>+        {
>+                struct fwctl_rpc_xe_sysctrl sysctrl_rpc = {
>+                        .op = FWCTL_XE_SYSCTRL_OP_ECC_STATUS_GET,
>+                };
>+                struct fwctl_rpc rpc = {
>+                        .size = sizeof(rpc),
>+                        .scope = FWCTL_RPC_CONFIGURATION,
>+                        .in_len = sizeof(sysctrl_rpc),
>+                        .out_len = sizeof(sysctrl_rpc),
>+                        .in = (__aligned_u64)&sysctrl_rpc,
>+                        .out = (__aligned_u64)&sysctrl_rpc,
>+                };
>+                int ret;
>+
>+                ret = ioctl(fd, FWCTL_RPC, &rpc);
>+                if (ret)
>+                        return ret;
>+
>+                *supported = sysctrl_rpc.data[0];
>+                *enabled = sysctrl_rpc.data[1];
>+                return 0;
>+        }
>+
>+Code example of querying RAS injection capabilities and injecting an error
>+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>+
>+.. code-block:: c
>+
>+        static int xe_sysctrl_get_ras_caps(int fd, __u32 *capability_mask, __u32 *flags)
>+        {
>+                struct fwctl_rpc_xe_sysctrl sysctrl_rpc = {
>+                        .op = FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS,
>+                };
>+                struct fwctl_rpc rpc = {
>+                        .size = sizeof(rpc),
>+                        .scope = FWCTL_RPC_CONFIGURATION,
>+                        .in_len = sizeof(sysctrl_rpc),
>+                        .out_len = sizeof(sysctrl_rpc),
>+                        .in = (__aligned_u64)&sysctrl_rpc,
>+                        .out = (__aligned_u64)&sysctrl_rpc,
>+                };
>+                int ret;
>+
>+                ret = ioctl(fd, FWCTL_RPC, &rpc);
>+                if (ret)
>+                        return ret;
>+
>+                *capability_mask = sysctrl_rpc.data[0];
>+                *flags = sysctrl_rpc.data[1];
>+                return 0;
>+        }
>+
>+        static int xe_sysctrl_ras_inject(int fd, __u32 error_inj)
>+        {
>+                struct fwctl_rpc_xe_sysctrl sysctrl_rpc = {
>+                        .op = FWCTL_XE_SYSCTRL_OP_RAS_INJECT,
>+                        .data[0] = error_inj,
>+                };
>+                struct fwctl_rpc rpc = {
>+                        .size = sizeof(rpc),
>+                        .scope = FWCTL_RPC_DEBUG_WRITE,
>+                        .in_len = sizeof(sysctrl_rpc),
>+                        .out_len = sizeof(sysctrl_rpc),
>+                        .in = (__aligned_u64)&sysctrl_rpc,
>+                        .out = (__aligned_u64)&sysctrl_rpc,
>+                };
>+
>+                /*
>+                 * Callers should confirm error_inj is set in capability_mask,
>+                 * and that flags allows injection (FWCTL_XE_SYSCTRL_RAS_INJ_ALLOWED),
>+                 * as returned by xe_sysctrl_get_ras_caps() above, before injecting.
>+                 */
>+                return ioctl(fd, FWCTL_RPC, &rpc);
>+        }

You could just use one function example that injects an error. Part of 
that implementation would be to query if error injections is available.  
That way you can just do away with the comment above.

>+
>diff --git a/drivers/gpu/drm/xe/Kconfig b/drivers/gpu/drm/xe/Kconfig
>index 4d7dcaff2b91..a472cb52dded 100644
>--- a/drivers/gpu/drm/xe/Kconfig
>+++ b/drivers/gpu/drm/xe/Kconfig
>@@ -25,6 +25,7 @@ config DRM_XE
> 	select DRM_MIPI_DSI
> 	select RELAY
> 	select IRQ_WORK
>+	select FWCTL
> 	# xe depends on ACPI_VIDEO when ACPI is enabled
> 	# but for select to work, need to select ACPI_VIDEO's dependencies, ick
> 	select BACKLIGHT_CLASS_DEVICE if ACPI
>diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>index 44ed055439d4..6560185c0ca7 100644
>--- a/drivers/gpu/drm/xe/Makefile
>+++ b/drivers/gpu/drm/xe/Makefile
>@@ -128,6 +128,7 @@ xe-y += xe_bb.o \
> 	xe_sync.o \
> 	xe_sysctrl.o \
> 	xe_sysctrl_event.o \
>+	xe_sysctrl_fwctl.o \
> 	xe_sysctrl_mailbox.o \
> 	xe_tile.o \
> 	xe_tile_sysfs.o \
>diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
>index d25d02b24898..dc7df793d4b9 100644
>--- a/drivers/gpu/drm/xe/xe_device.c
>+++ b/drivers/gpu/drm/xe/xe_device.c
>@@ -68,6 +68,7 @@
> #include "xe_sriov.h"
> #include "xe_svm.h"
> #include "xe_sysctrl.h"
>+#include "xe_sysctrl_fwctl.h"
> #include "xe_tile.h"
> #include "xe_ttm_stolen_mgr.h"
> #include "xe_ttm_sys_mgr.h"
>@@ -1028,6 +1029,10 @@ int xe_device_probe(struct xe_device *xe)
> 	if (err)
> 		return err;
>
>+	err = xe_sysctrl_fwctl_init(xe);
>+	if (err)
>+		return err;
>+
> 	xe_ras_init(xe);
>
> 	/*
>diff --git a/drivers/gpu/drm/xe/xe_sysctrl_fwctl.c b/drivers/gpu/drm/xe/xe_sysctrl_fwctl.c
>new file mode 100644
>index 000000000000..27a40efa0787
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/xe_sysctrl_fwctl.c
>@@ -0,0 +1,251 @@
>+// SPDX-License-Identifier: MIT
>+/*
>+ * Copyright © 2026 Intel Corporation
>+ */
>+
>+#include <linux/errno.h>
>+#include <linux/fwctl.h>
>+#include <linux/slab.h>
>+
>+#include <uapi/fwctl/xe_sysctrl.h>
>+
>+#include "xe_device.h"
>+#include "xe_pm.h"
>+#include "xe_printk.h"
>+#include "xe_sysctrl.h"
>+#include "xe_sysctrl_fwctl.h"
>+#include "xe_sysctrl_mailbox.h"
>+#include "xe_sysctrl_mailbox_types.h"
>+
>+struct xe_sysctrl_fwctl_dev {
>+	struct fwctl_device fwctl;
>+	struct xe_device *xe;
>+};
>+
>+DEFINE_FREE(xe_sysctrl_fwctl, struct xe_sysctrl_fwctl_dev *, if (_T) fwctl_put(&_T->fwctl))
>+
>+struct xe_sysctrl_fwctl_uctx {
>+	struct fwctl_uctx uctx;
>+	u32 uctx_caps;
>+};
>+
>+static int xe_sysctrl_fwctl_uctx_open(struct fwctl_uctx *uctx)
>+{
>+	struct xe_sysctrl_fwctl_dev *fwctl_dev =
>+		container_of(uctx->fwctl, struct xe_sysctrl_fwctl_dev, fwctl);
>+	struct xe_sysctrl_fwctl_uctx *sc_uctx =
>+		container_of(uctx, struct xe_sysctrl_fwctl_uctx, uctx);
>+	struct xe_device *xe = fwctl_dev->xe;
>+
>+	xe_pm_runtime_get(xe);
>+
>+	sc_uctx->uctx_caps = FWCTL_XE_SYSCTRL_CAP_ECC;
>+	if (xe_sysctrl_is_diag_fw_ready(xe))
>+		sc_uctx->uctx_caps |= FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT;
>+
>+	return 0;
>+}
>+
>+static void xe_sysctrl_fwctl_uctx_close(struct fwctl_uctx *uctx)
>+{
>+	struct xe_sysctrl_fwctl_dev *fwctl_dev =
>+		container_of(uctx->fwctl, struct xe_sysctrl_fwctl_dev, fwctl);
>+
>+	xe_pm_runtime_put(fwctl_dev->xe);
>+}
>+
>+static void *xe_sysctrl_fwctl_info(struct fwctl_uctx *uctx, size_t *length)
>+{
>+	struct xe_sysctrl_fwctl_uctx *sc_uctx =
>+		container_of(uctx, struct xe_sysctrl_fwctl_uctx, uctx);
>+	struct fwctl_info_xe_sysctrl *info;
>+
>+	info = kzalloc_obj(*info);
>+	if (!info)
>+		return ERR_PTR(-ENOMEM);
>+
>+	info->uctx_caps = sc_uctx->uctx_caps;
>+
>+	*length = sizeof(*info);
>+	return info;
>+}
>+
>+static int sysctrl_rpc_ecc_status_get(struct xe_device *xe,
>+				      struct fwctl_rpc_xe_sysctrl *rpc)
>+{
>+	struct xe_sysctrl_feature_cap_resp resp = {};
>+	struct xe_sysctrl_mailbox_command cmd = {0};
>+	size_t out_len = 0;
>+	int ret;
>+
>+	xe_sysctrl_create_command(&cmd, XE_SYSCTRL_GROUP_GFSP_RUNTIME,
>+				  XE_SYSCTRL_CMD_GET_FEATURE_CAPABILITY_STATE_INFO,
>+				  NULL, 0, &resp, sizeof(resp));
>+
>+	ret = xe_sysctrl_send_command(&xe->sc, &cmd, &out_len);
>+	if (ret)
>+		return ret;
>+
>+	if (out_len < 2 * sizeof(u32)) {
>+		xe_err(xe, "sysctrl fwctl: ECC status response too short (%zu B)\n",
>+		       out_len);
>+		return -EIO;
>+	}
>+
>+	rpc->data[0] = resp.supported_features & XE_SYSCTRL_FEATURE_ECC ? 1 : 0;
>+	rpc->data[1] = resp.enabled_features & XE_SYSCTRL_FEATURE_ECC ? 1 : 0;
>+	return 0;
>+}
>+
>+static int sysctrl_rpc_ras_get_caps(struct xe_device *xe,
>+				    struct fwctl_rpc_xe_sysctrl *rpc)
>+{
>+	struct xe_sysctrl_ras_err_inj_cap_resp resp = {};
>+	struct xe_sysctrl_mailbox_command cmd = {0};
>+	size_t out_len = 0;
>+	int ret;
>+
>+	xe_sysctrl_create_command(&cmd, XE_SYSCTRL_GROUP_DIAG,
>+				  XE_SYSCTRL_CMD_RAS_ERR_INJ_CAPABILITY,
>+				  NULL, 0, &resp, sizeof(resp));
>+
>+	ret = xe_sysctrl_send_command(&xe->sc, &cmd, &out_len);
>+	if (ret)
>+		return ret;

Not checking for short reponse here like in the ECC function above?

>+
>+	rpc->data[0] = resp.capability_mask;
>+	rpc->data[1] = resp.flags;
>+	return 0;
>+}
>+
>+static int sysctrl_rpc_ras_inject(struct xe_device *xe,
>+				  struct fwctl_rpc_xe_sysctrl *rpc)
>+{
>+	struct xe_sysctrl_ras_err_inj_req req = {
>+		.error_inj	   = rpc->data[0],
>+		.additional_params = rpc->data[1],
>+	};
>+	struct xe_sysctrl_mailbox_command cmd = {0};
>+	size_t out_len = 0;
>+

We should check if the type of inject is supported. It may mean that we 
cache the err injection capabilities early on (during init). Is that 
possible?

>+	xe_sysctrl_create_command(&cmd, XE_SYSCTRL_GROUP_DIAG,
>+				  XE_SYSCTRL_CMD_RAS_ERR_INJECT,
>+				  &req, sizeof(req), NULL, 0);
>+
>+	return xe_sysctrl_send_command(&xe->sc, &cmd, &out_len);
>+}
>+
>+static void *xe_sysctrl_fwctl_rpc(struct fwctl_uctx *uctx,
>+				  enum fwctl_rpc_scope scope,
>+				  void *rpc_in, size_t in_len,
>+				  size_t *out_len)
>+{
>+	struct xe_sysctrl_fwctl_dev *fwctl_dev =
>+		container_of(uctx->fwctl, struct xe_sysctrl_fwctl_dev, fwctl);
>+	struct xe_sysctrl_fwctl_uctx *sc_uctx =
>+		container_of(uctx, struct xe_sysctrl_fwctl_uctx, uctx);
>+	struct xe_device *xe = fwctl_dev->xe;
>+	struct fwctl_rpc_xe_sysctrl *rpc;
>+	int ret;
>+
>+	if (in_len != sizeof(*rpc) || *out_len < sizeof(*rpc))
>+		return ERR_PTR(-EMSGSIZE);
>+
>+	rpc = rpc_in;
>+
>+	if (rpc->flags)
>+		return ERR_PTR(-EINVAL);
>+
>+	switch (rpc->op) {
>+	case FWCTL_XE_SYSCTRL_OP_ECC_STATUS_GET:
>+		if (!(sc_uctx->uctx_caps & FWCTL_XE_SYSCTRL_CAP_ECC))
>+			return ERR_PTR(-EPERM);


EPERM doesn't look correct here. i.e. if the caller were an ADMIN, would 
this work?

If the caller is trying an RPC that is not available, then this should 
be EINVAL. Same for the below cases.


>+		if (scope < FWCTL_RPC_CONFIGURATION)
>+			return ERR_PTR(-EBADMSG);
>+		ret = sysctrl_rpc_ecc_status_get(xe, rpc);
>+		if (ret)
>+			return ERR_PTR(ret);
>+		break;
>+
>+	case FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS:
>+		if (!(sc_uctx->uctx_caps & FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT))
>+			return ERR_PTR(-EPERM);
>+		if (scope < FWCTL_RPC_CONFIGURATION)
>+			return ERR_PTR(-EBADMSG);
>+		ret = sysctrl_rpc_ras_get_caps(xe, rpc);
>+		if (ret)
>+			return ERR_PTR(ret);
>+		break;

Do these capabilities change at runtime? If not, why not just cache them 
after first read?

>+
>+	case FWCTL_XE_SYSCTRL_OP_RAS_INJECT:
>+		if (!(sc_uctx->uctx_caps & FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT))
>+			return ERR_PTR(-EPERM);
>+		if (scope < FWCTL_RPC_DEBUG_WRITE)
>+			return ERR_PTR(-EBADMSG);
>+		ret = sysctrl_rpc_ras_inject(xe, rpc);
>+		if (ret)
>+			return ERR_PTR(ret);
>+		break;
>+
>+	default:
>+		return ERR_PTR(-EBADMSG);
>+	}
>+
>+	*out_len = sizeof(*rpc);
>+	return rpc_in;
>+}
>+
>+static const struct fwctl_ops xe_sysctrl_fwctl_ops = {
>+	.device_type = FWCTL_DEVICE_TYPE_XE_SYSCTRL,
>+	.uctx_size = sizeof(struct xe_sysctrl_fwctl_uctx),
>+	.open_uctx = xe_sysctrl_fwctl_uctx_open,
>+	.close_uctx = xe_sysctrl_fwctl_uctx_close,
>+	.info = xe_sysctrl_fwctl_info,
>+	.fw_rpc = xe_sysctrl_fwctl_rpc,
>+};
>+
>+static void xe_sysctrl_fwctl_fini(void *arg)
>+{
>+	struct fwctl_device *fwctl = arg;
>+
>+	fwctl_unregister(fwctl);
>+	fwctl_put(fwctl);
>+}
>+
>+/**
>+ * xe_sysctrl_fwctl_init() - Initialize fwctl interface for System Controller
>+ * @xe: xe device instance
>+ *
>+ * Registers a fwctl device that exposes System Controller debug and
>+ * diagnostic functionality to userspace, on platforms where System
>+ * Controller is supported.
>+ *
>+ * Return: 0 on success, error code on failure
>+ */
>+int xe_sysctrl_fwctl_init(struct xe_device *xe)
>+{
>+	struct xe_sysctrl_fwctl_dev *fwctl_dev __free(xe_sysctrl_fwctl) =
>+		fwctl_alloc_device(xe->drm.dev, &xe_sysctrl_fwctl_ops,
>+				   struct xe_sysctrl_fwctl_dev, fwctl);
>+	int err;
>+
>+	if (!xe->info.has_soc_remapper_sysctrl)
>+		return 0;
>+
>+	if (!xe->info.has_sysctrl)
>+		return 0;
>+
>+	if (!fwctl_dev)
>+		return -ENOMEM;
>+
>+	fwctl_dev->xe = xe;
>+
>+	err = fwctl_register(&fwctl_dev->fwctl);
>+	if (err)
>+		return err;
>+
>+	return devm_add_action_or_reset(xe->drm.dev, xe_sysctrl_fwctl_fini,
>+					&no_free_ptr(fwctl_dev)->fwctl);
>+}
>+
>+MODULE_IMPORT_NS("FWCTL");
>diff --git a/drivers/gpu/drm/xe/xe_sysctrl_fwctl.h b/drivers/gpu/drm/xe/xe_sysctrl_fwctl.h
>new file mode 100644
>index 000000000000..730f31e0d697
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/xe_sysctrl_fwctl.h
>@@ -0,0 +1,13 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2026 Intel Corporation
>+ */
>+
>+#ifndef _XE_SYSCTRL_FWCTL_H_
>+#define _XE_SYSCTRL_FWCTL_H_
>+
>+struct xe_device;
>+
>+int xe_sysctrl_fwctl_init(struct xe_device *xe);
>+
>+#endif
>diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
>index b507e1553cbb..7f39fd1a418a 100644
>--- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
>+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
>@@ -14,10 +14,14 @@
>  * enum xe_sysctrl_group - System Controller command groups
>  *
>  * @XE_SYSCTRL_GROUP_GFSP: GFSP group
>+ * @XE_SYSCTRL_GROUP_DIAG: Diag group
>+ * @XE_SYSCTRL_GROUP_GFSP_RUNTIME: GFSP runtime group
>  * @XE_SYSCTRL_GROUP_CORE: Core group
>  */
> enum xe_sysctrl_group {
> 	XE_SYSCTRL_GROUP_GFSP			= 0x01,
>+	XE_SYSCTRL_GROUP_DIAG			= 0x02,
>+	XE_SYSCTRL_GROUP_GFSP_RUNTIME		= 0x31,
> 	XE_SYSCTRL_GROUP_CORE			= 0xFF,
> };
>
>@@ -103,6 +107,88 @@ enum xe_sysctrl_app_id {
> 	XE_SYSCTRL_APP_DIAG	= 0x0D,
> };
>
>+/**
>+ * enum xe_sysctrl_diag_cmd - Commands supported by DIAG group
>+ *
>+ * @XE_SYSCTRL_CMD_RAS_ERR_INJ_CAPABILITY: Query supported RAS injection types
>+ * @XE_SYSCTRL_CMD_RAS_ERR_INJECT: Inject a RAS error into an IP block
>+ */
>+enum xe_sysctrl_diag_cmd {
>+	XE_SYSCTRL_CMD_RAS_ERR_INJ_CAPABILITY	= 0x01,
>+	XE_SYSCTRL_CMD_RAS_ERR_INJECT		= 0x02,
>+};
>+
>+/**
>+ * struct xe_sysctrl_ras_err_inj_cap_resp - RAS_ERR_INJ_CAPABILITY response payload
>+ *
>+ * Response payload for XE_SYSCTRL_CMD_RAS_ERR_INJ_CAPABILITY.  The mailbox
>+ * layer strips the application message header before writing to this buffer.
>+ *
>+ * @capability_mask: OR of firmware-defined capability values indicating which
>+ *                   injection classes are supported on this platform (see
>+ *                   enum fwctl_xe_sysctrl_ras_inj_cap in
>+ *                   include/uapi/fwctl/xe_sysctrl.h for bit definitions)
>+ * @flags:           Bitmask; bit FWCTL_XE_SYSCTRL_RAS_INJ_ALLOWED (see
>+ *                   include/uapi/fwctl/xe_sysctrl.h) indicates whether RAS
>+ *                   error injection is currently allowed by hardware
>+ *                   security policy.
>+ * @reserved:        Must be zero
>+ */
>+struct xe_sysctrl_ras_err_inj_cap_resp {
>+	u32 capability_mask;
>+	u32 flags;
>+	u32 reserved[2];
>+} __packed;
>+
>+/**
>+ * struct xe_sysctrl_ras_err_inj_req - RAS_ERR_INJECT request payload
>+ *
>+ * Request payload for XE_SYSCTRL_CMD_RAS_ERR_INJECT.  The mailbox layer
>+ * prepends the application message header before sending.
>+ *
>+ * @error_inj:    One of the enum fwctl_xe_sysctrl_ras_inj_cap bit values
>+ *                (include/uapi/fwctl/xe_sysctrl.h), selecting the class of
>+ *                error to inject.
>+ * @additional_params: Reserved for future use; must be 0 for most injection
>+ *                    types
>+ */
>+struct xe_sysctrl_ras_err_inj_req {
>+	u32 error_inj;
>+	u32 additional_params;
>+} __packed;
>+
>+/**
>+ * enum xe_sysctrl_gfsp_runtime_cmd - Commands for the GFSP runtime group (0x31)
>+ *
>+ * @XE_SYSCTRL_CMD_GET_FEATURE_CAPABILITY_STATE_INFO: Read ECC feature state.
>+ *	No input payload.  Response: struct xe_sysctrl_feature_cap_resp.
>+ */
>+enum xe_sysctrl_gfsp_runtime_cmd {
>+	XE_SYSCTRL_CMD_GET_FEATURE_CAPABILITY_STATE_INFO	= 0x10,
>+};
>+
>+/** XE_SYSCTRL_FEATURE_ECC - ECC feature bit in FSP runtime capability bitmasks */
>+#define XE_SYSCTRL_FEATURE_ECC	BIT(0)
>+
>+/**
>+ * struct xe_sysctrl_feature_cap_resp - ECC feature state
>+ *
>+ * Response layout for XE_SYSCTRL_CMD_GET_FEATURE_CAPABILITY_STATE_INFO.
>+ *
>+ * @supported_features: Features supported by the product
>+ * @enabled_features: Features currently enabled
>+ * @configurable_features: Features modifiable by software
>+ * @pending_features: Feature state pending after next reboot
>+ * @default_features: Default feature state from build configuration
>+ */
>+struct xe_sysctrl_feature_cap_resp {
>+	u32 supported_features;
>+	u32 enabled_features;
>+	u32 configurable_features;
>+	u32 pending_features;
>+	u32 default_features;
>+} __packed;
>+
> /**
>  * struct xe_sysctrl_mailbox_command - System Controller mailbox command
>  */
>diff --git a/include/uapi/fwctl/fwctl.h b/include/uapi/fwctl/fwctl.h
>index 2d6d4049c205..34901d36cd51 100644
>--- a/include/uapi/fwctl/fwctl.h
>+++ b/include/uapi/fwctl/fwctl.h
>@@ -46,6 +46,7 @@ enum fwctl_device_type {
> 	FWCTL_DEVICE_TYPE_CXL = 2,
> 	FWCTL_DEVICE_TYPE_BNXT = 3,
> 	FWCTL_DEVICE_TYPE_PDS = 4,
>+	FWCTL_DEVICE_TYPE_XE_SYSCTRL = 5,
> };
>
> /**
>diff --git a/include/uapi/fwctl/xe_sysctrl.h b/include/uapi/fwctl/xe_sysctrl.h
>new file mode 100644
>index 000000000000..a4d117d906e3
>--- /dev/null
>+++ b/include/uapi/fwctl/xe_sysctrl.h
>@@ -0,0 +1,117 @@
>+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
>+/* Copyright © 2026 Intel Corporation */
>+#ifndef _UAPI_FWCTL_XE_SYSCTRL_H_
>+#define _UAPI_FWCTL_XE_SYSCTRL_H_
>+
>+#include <linux/bits.h>
>+#include <linux/types.h>
>+
>+/**
>+ * enum fwctl_xe_sysctrl_uctx_caps - capability flags in fwctl_info_xe_sysctrl.uctx_caps
>+ *
>+ * @FWCTL_XE_SYSCTRL_CAP_ECC: ECC status query is supported on this platform
>+ * @FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT: RAS error injection is supported;
>+ *      requires diag firmware to be loaded and ready
>+ */
>+enum fwctl_xe_sysctrl_uctx_caps {
>+	FWCTL_XE_SYSCTRL_CAP_ECC		= (1U << 0),
>+	FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT	= (1U << 1),

BIT(0)
BIT(1)

>+};
>+
>+/**
>+ * struct fwctl_info_xe_sysctrl - device data returned by FWCTL_INFO
>+ * @uctx_caps: Bitmask of available capabilities (see %fwctl_xe_sysctrl_uctx_caps)
>+ * @rsvd: Reserved, must be zero
>+ */
>+struct fwctl_info_xe_sysctrl {
>+	__u32 uctx_caps;
>+	__u32 rsvd[7];
>+};
>+
>+/**
>+ * enum fwctl_xe_sysctrl_ras_inj_cap - RAS error injection capability bits
>+ *
>+ * Used both in the @capability_mask output of %FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS
>+ * and as the @error_inj input of %FWCTL_XE_SYSCTRL_OP_RAS_INJECT. Userspace
>+ * must confirm a bit is set in @capability_mask before injecting that class.
>+ *
>+ * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_COMPUTE_CORR: Compute block correctable error
>+ * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_COMPUTE_UCORR: Compute block uncorrectable error
>+ * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_MEMORY_UCORR: Memory subsystem uncorrectable error
>+ * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_FABRIC_UCORR: Fabric interconnect uncorrectable error
>+ * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PCIE_CORR: PCIe subsystem correctable error
>+ * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PCIE_UCORR: PCIe subsystem uncorrectable error
>+ * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PLATFORM_UCORR: Platform-level uncorrectable error
>+ */
>+enum fwctl_xe_sysctrl_ras_inj_cap {
>+	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_COMPUTE_CORR	= 0x0001U,
>+	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_COMPUTE_UCORR	= 0x0002U,
>+	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_MEMORY_UCORR	= 0x0004U,
>+	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_FABRIC_UCORR	= 0x0008U,
>+	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PCIE_CORR		= 0x0010U,
>+	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PCIE_UCORR		= 0x0020U,
>+	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PLATFORM_UCORR	= 0x0040U,

Same here, why not use BIT?

Thanks,
Umesh

>+};
>+
>+/* FWCTL_XE_SYSCTRL_RAS_INJ_ALLOWED - bit in the RAS_GET_CAPS flags field
>+ * indicating RAS error injection is currently allowed by hardware security
>+ * policy.
>+ */
>+#define FWCTL_XE_SYSCTRL_RAS_INJ_ALLOWED	(1U << 0)
>+
>+/**
>+ * enum fwctl_xe_sysctrl_op - RPC operation codes for xe_sysctrl fwctl
>+ *
>+ * @FWCTL_XE_SYSCTRL_OP_ECC_STATUS_GET: Read ECC feature state from GFSP firmware
>+ *	(GFSP runtime group, GET_FEATURE_CAPABILITY_STATE_INFO, BIT(0) = ECC).
>+ *	Requires: %FWCTL_XE_SYSCTRL_CAP_ECC in uctx_caps.
>+ *	Scope: %FWCTL_RPC_CONFIGURATION.
>+ *	in:  op, flags=0, data[0..13] ignored.
>+ *	out: data[0] = 1 if ECC is supported by this product, 0 otherwise.
>+ *	     data[1] = 1 if ECC is currently enabled, 0 otherwise.
>+ *
>+ * @FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS: Query RAS error injection capability from
>+ *	diag firmware (DIAG group, RAS_ERR_INJ_CAPABILITY command).
>+ *	Requires: %FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT in uctx_caps.
>+ *	Scope: %FWCTL_RPC_CONFIGURATION.
>+ *	in:  op, flags=0, data[0..13] ignored.
>+ *	out: data[0] = capability_mask, an OR of %fwctl_xe_sysctrl_ras_inj_cap
>+ *	                bits indicating which injection classes are supported,
>+ *	     data[1] = flags; bit %FWCTL_XE_SYSCTRL_RAS_INJ_ALLOWED indicates
>+ *	                whether RAS error injection is currently allowed by
>+ *	                hardware security policy, other bits are reserved for
>+ *	                future use.
>+ *
>+ * @FWCTL_XE_SYSCTRL_OP_RAS_INJECT: Inject a RAS error via diag firmware
>+ *	(DIAG group, RAS_ERR_INJECT command).
>+ *	Requires: %FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT in uctx_caps.
>+ *	Scope: %FWCTL_RPC_DEBUG_WRITE.
>+ *	in:  data[0] = error_inj, one of the %fwctl_xe_sysctrl_ras_inj_cap
>+ *	                bit values. Userspace must confirm this bit is set in
>+ *	                the capability_mask returned by
>+ *	                %FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS (and that its flags
>+ *	                field currently allows injection) before issuing this
>+ *	                request; behavior for an unsupported value is
>+ *	                firmware-defined,
>+ *	     data[1] = additional_params (reserved; 0 for most injection types).
>+ *	out: no additional output data (success indicated by ioctl return code).
>+ */
>+enum fwctl_xe_sysctrl_op {
>+	FWCTL_XE_SYSCTRL_OP_ECC_STATUS_GET	= 1,
>+	FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS	= 2,
>+	FWCTL_XE_SYSCTRL_OP_RAS_INJECT		= 3,
>+};
>+
>+/**
>+ * struct fwctl_rpc_xe_sysctrl - RPC request/response envelope
>+ * @op: Operation code (see %fwctl_xe_sysctrl_op)
>+ * @flags: Must be 0
>+ * @data: Operation-specific payload (see %fwctl_xe_sysctrl_op for layout)
>+ */
>+struct fwctl_rpc_xe_sysctrl {
>+	__u32 op;
>+	__u32 flags;
>+	__u32 data[14];
>+};
>+
>+#endif
>-- 
>2.43.0
>

Re: [PATCH v2 2/2] drm/xe/sysctrl: Add fwctl support for System Controller

[Rodrigo Vivi]

On Mon, Aug 10, 2026 at 02:11:25PM -0700, Umesh Nerlige Ramappa wrote:
> On Thu, Aug 06, 2026 at 05:03:12AM -0700, Anoop, Vijay wrote:
> > From: Anoop Vijay <anoop.c.vijay@intel.com>
> > 
> > Add fwctl support for Xe System Controller (sysctrl), a
> > firmware-managed entity that provides platform-level control and
> > coordination on Intel Xe3p discrete GPUs.
> > 
> > Register a XE_SYSCTRL device to allow userspace to query sysctrl
> > capabilities and issue RPCs through /dev/fwctl/fwctlN. Initial
> > RPCs support ECC status queries and RAS error injection.
> > 
> > Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
> > ---
> > v2: (Rodrigo)
> > - Rename FWCTL_DEVICE_TYPE_XE to FWCTL_DEVICE_TYPE_XE_SYSCTRL, one type
> >  per firmware instead of a shared Xe-wide type
> > - Rename xe.h to xe_sysctrl.h to match
> > - Squash uapi and type definitions into a single patch
> > - Replace validate_scope() with explicit per-op scope/capability checks
> >  in xe_sysctrl_fwctl_rpc()
> > ---
> > Documentation/userspace-api/fwctl/index.rst   |   1 +
> > .../userspace-api/fwctl/xe_sysctrl.rst        | 120 +++++++++
> > drivers/gpu/drm/xe/Kconfig                    |   1 +
> > drivers/gpu/drm/xe/Makefile                   |   1 +
> > drivers/gpu/drm/xe/xe_device.c                |   5 +
> > drivers/gpu/drm/xe/xe_sysctrl_fwctl.c         | 251 ++++++++++++++++++
> > drivers/gpu/drm/xe/xe_sysctrl_fwctl.h         |  13 +
> > drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h |  86 ++++++
> > include/uapi/fwctl/fwctl.h                    |   1 +

On your next version, please Cc the right addresses:

$ ./scripts/get_maintainer.pl include/uapi/fwctl/
Dave Jiang <dave.jiang@intel.com> (maintainer:FWCTL SUBSYSTEM)
Jason Gunthorpe <jgg@ziepe.ca> (maintainer:FWCTL SUBSYSTEM)
Saeed Mahameed <saeedm@nvidia.com> (maintainer:FWCTL SUBSYSTEM)
Jonathan Cameron <jic23@kernel.org> (reviewer:FWCTL SUBSYSTEM)


> > include/uapi/fwctl/xe_sysctrl.h               | 117 ++++++++

To make our future life easier we might ask them to get the maintainership
of our files:

diff --git a/MAINTAINERS b/MAINTAINERS
index 928b3ba23a76..0b912f4b986e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13016,6 +13016,8 @@ C:      irc://irc.oftc.net/xe
 T:     git https://gitlab.freedesktop.org/drm/xe/kernel.git
 F:     Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
 F:     Documentation/gpu/xe/
+F:     Documentation/userspace-api/fwctl/xe_*
+F:     include/uapi/fwctl/xe_*
 F:     drivers/gpu/drm/xe/
 F:     include/drm/intel/
 F:     include/uapi/drm/xe_drm.h


> > 10 files changed, 596 insertions(+)
> > create mode 100644 Documentation/userspace-api/fwctl/xe_sysctrl.rst
> > create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_fwctl.c
> > create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_fwctl.h
> > create mode 100644 include/uapi/fwctl/xe_sysctrl.h
> > 
> > diff --git a/Documentation/userspace-api/fwctl/index.rst b/Documentation/userspace-api/fwctl/index.rst
> > index 8062f7629654..f6fca11e6aac 100644
> > --- a/Documentation/userspace-api/fwctl/index.rst
> > +++ b/Documentation/userspace-api/fwctl/index.rst
> > @@ -13,3 +13,4 @@ to securely construct and execute RPCs inside device firmware.
> >    bnxt_fwctl
> >    fwctl-cxl
> >    pds_fwctl
> > +   xe_sysctrl
> > diff --git a/Documentation/userspace-api/fwctl/xe_sysctrl.rst b/Documentation/userspace-api/fwctl/xe_sysctrl.rst
> > new file mode 100644
> > index 000000000000..6dfc9e70b683
> > --- /dev/null
> > +++ b/Documentation/userspace-api/fwctl/xe_sysctrl.rst
> > @@ -0,0 +1,120 @@
> > +.. SPDX-License-Identifier: GPL-2.0
> > +
> > +=======================
> > +fwctl xe_sysctrl driver
> > +=======================
> > +
> > +:Author: Intel Corporation
> > +
> > +Overview
> > +========
> > +
> > +The Xe System Controller (sysctrl) firmware exposes a fwctl service that
> > +the xe driver registers as a ``FWCTL_DEVICE_TYPE_XE_SYSCTRL`` device.
> > +Userspace opens the resulting ``/dev/fwctl/fwctlN`` node to query ECC
> > +status and RAS error injection capabilities and to issue RAS error
> > +injection requests to the sysctrl firmware.
> > +
> > +xe_sysctrl User API
> > +====================
> > +
> > +.. kernel-doc:: include/uapi/fwctl/xe_sysctrl.h
> > +
> > +1. Driver info query
> > +---------------------
> > +
> > +The application issues ``FWCTL_INFO`` to retrieve a
> > +``struct fwctl_info_xe_sysctrl`` and inspect ``uctx_caps`` to determine
> > +which of the ``FWCTL_XE_SYSCTRL_CAP_*`` capabilities are available on this
> > +platform and in this security context.
> > +
> > +2. Send RPC requests
> > +---------------------
> > +
> > +Each RPC uses a single ``struct fwctl_rpc_xe_sysctrl`` as both the
> > +``FWCTL_RPC`` ``in`` and ``out`` buffer; the driver fills in ``data`` in
> > +place. ``op`` selects one of the ``enum fwctl_xe_sysctrl_op`` operations.
> > +The kernel rejects the request if the scope of the ``FWCTL_RPC`` call is
> > +lower than the minimum required by the requested ``op``, as documented above.
> > +
> > +Code example of querying ECC status
> > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > +
> > +.. code-block:: c
> > +
> > +        static int xe_sysctrl_get_ecc(int fd, __u32 *supported, __u32 *enabled)
> > +        {
> > +                struct fwctl_rpc_xe_sysctrl sysctrl_rpc = {
> > +                        .op = FWCTL_XE_SYSCTRL_OP_ECC_STATUS_GET,
> > +                };
> > +                struct fwctl_rpc rpc = {
> > +                        .size = sizeof(rpc),
> > +                        .scope = FWCTL_RPC_CONFIGURATION,
> > +                        .in_len = sizeof(sysctrl_rpc),
> > +                        .out_len = sizeof(sysctrl_rpc),
> > +                        .in = (__aligned_u64)&sysctrl_rpc,
> > +                        .out = (__aligned_u64)&sysctrl_rpc,
> > +                };
> > +                int ret;
> > +
> > +                ret = ioctl(fd, FWCTL_RPC, &rpc);
> > +                if (ret)
> > +                        return ret;
> > +
> > +                *supported = sysctrl_rpc.data[0];
> > +                *enabled = sysctrl_rpc.data[1];
> > +                return 0;
> > +        }
> > +
> > +Code example of querying RAS injection capabilities and injecting an error
> > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > +
> > +.. code-block:: c
> > +
> > +        static int xe_sysctrl_get_ras_caps(int fd, __u32 *capability_mask, __u32 *flags)
> > +        {
> > +                struct fwctl_rpc_xe_sysctrl sysctrl_rpc = {
> > +                        .op = FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS,
> > +                };
> > +                struct fwctl_rpc rpc = {
> > +                        .size = sizeof(rpc),
> > +                        .scope = FWCTL_RPC_CONFIGURATION,
> > +                        .in_len = sizeof(sysctrl_rpc),
> > +                        .out_len = sizeof(sysctrl_rpc),
> > +                        .in = (__aligned_u64)&sysctrl_rpc,
> > +                        .out = (__aligned_u64)&sysctrl_rpc,
> > +                };
> > +                int ret;
> > +
> > +                ret = ioctl(fd, FWCTL_RPC, &rpc);
> > +                if (ret)
> > +                        return ret;
> > +
> > +                *capability_mask = sysctrl_rpc.data[0];
> > +                *flags = sysctrl_rpc.data[1];
> > +                return 0;
> > +        }
> > +
> > +        static int xe_sysctrl_ras_inject(int fd, __u32 error_inj)
> > +        {
> > +                struct fwctl_rpc_xe_sysctrl sysctrl_rpc = {
> > +                        .op = FWCTL_XE_SYSCTRL_OP_RAS_INJECT,
> > +                        .data[0] = error_inj,
> > +                };
> > +                struct fwctl_rpc rpc = {
> > +                        .size = sizeof(rpc),
> > +                        .scope = FWCTL_RPC_DEBUG_WRITE,
> > +                        .in_len = sizeof(sysctrl_rpc),
> > +                        .out_len = sizeof(sysctrl_rpc),
> > +                        .in = (__aligned_u64)&sysctrl_rpc,
> > +                        .out = (__aligned_u64)&sysctrl_rpc,
> > +                };
> > +
> > +                /*
> > +                 * Callers should confirm error_inj is set in capability_mask,
> > +                 * and that flags allows injection (FWCTL_XE_SYSCTRL_RAS_INJ_ALLOWED),
> > +                 * as returned by xe_sysctrl_get_ras_caps() above, before injecting.
> > +                 */
> > +                return ioctl(fd, FWCTL_RPC, &rpc);
> > +        }
> 
> You could just use one function example that injects an error. Part of that
> implementation would be to query if error injections is available.  That way
> you can just do away with the comment above.
> 
> > +
> > diff --git a/drivers/gpu/drm/xe/Kconfig b/drivers/gpu/drm/xe/Kconfig
> > index 4d7dcaff2b91..a472cb52dded 100644
> > --- a/drivers/gpu/drm/xe/Kconfig
> > +++ b/drivers/gpu/drm/xe/Kconfig
> > @@ -25,6 +25,7 @@ config DRM_XE
> > 	select DRM_MIPI_DSI
> > 	select RELAY
> > 	select IRQ_WORK
> > +	select FWCTL
> > 	# xe depends on ACPI_VIDEO when ACPI is enabled
> > 	# but for select to work, need to select ACPI_VIDEO's dependencies, ick
> > 	select BACKLIGHT_CLASS_DEVICE if ACPI
> > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> > index 44ed055439d4..6560185c0ca7 100644
> > --- a/drivers/gpu/drm/xe/Makefile
> > +++ b/drivers/gpu/drm/xe/Makefile
> > @@ -128,6 +128,7 @@ xe-y += xe_bb.o \
> > 	xe_sync.o \
> > 	xe_sysctrl.o \
> > 	xe_sysctrl_event.o \
> > +	xe_sysctrl_fwctl.o \
> > 	xe_sysctrl_mailbox.o \
> > 	xe_tile.o \
> > 	xe_tile_sysfs.o \
> > diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> > index d25d02b24898..dc7df793d4b9 100644
> > --- a/drivers/gpu/drm/xe/xe_device.c
> > +++ b/drivers/gpu/drm/xe/xe_device.c
> > @@ -68,6 +68,7 @@
> > #include "xe_sriov.h"
> > #include "xe_svm.h"
> > #include "xe_sysctrl.h"
> > +#include "xe_sysctrl_fwctl.h"
> > #include "xe_tile.h"
> > #include "xe_ttm_stolen_mgr.h"
> > #include "xe_ttm_sys_mgr.h"
> > @@ -1028,6 +1029,10 @@ int xe_device_probe(struct xe_device *xe)
> > 	if (err)
> > 		return err;
> > 
> > +	err = xe_sysctrl_fwctl_init(xe);
> > +	if (err)
> > +		return err;
> > +
> > 	xe_ras_init(xe);
> > 
> > 	/*
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_fwctl.c b/drivers/gpu/drm/xe/xe_sysctrl_fwctl.c
> > new file mode 100644
> > index 000000000000..27a40efa0787
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_fwctl.c
> > @@ -0,0 +1,251 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#include <linux/errno.h>
> > +#include <linux/fwctl.h>
> > +#include <linux/slab.h>
> > +
> > +#include <uapi/fwctl/xe_sysctrl.h>
> > +
> > +#include "xe_device.h"
> > +#include "xe_pm.h"
> > +#include "xe_printk.h"
> > +#include "xe_sysctrl.h"
> > +#include "xe_sysctrl_fwctl.h"
> > +#include "xe_sysctrl_mailbox.h"
> > +#include "xe_sysctrl_mailbox_types.h"
> > +
> > +struct xe_sysctrl_fwctl_dev {
> > +	struct fwctl_device fwctl;
> > +	struct xe_device *xe;
> > +};
> > +
> > +DEFINE_FREE(xe_sysctrl_fwctl, struct xe_sysctrl_fwctl_dev *, if (_T) fwctl_put(&_T->fwctl))
> > +
> > +struct xe_sysctrl_fwctl_uctx {
> > +	struct fwctl_uctx uctx;
> > +	u32 uctx_caps;
> > +};
> > +
> > +static int xe_sysctrl_fwctl_uctx_open(struct fwctl_uctx *uctx)
> > +{
> > +	struct xe_sysctrl_fwctl_dev *fwctl_dev =
> > +		container_of(uctx->fwctl, struct xe_sysctrl_fwctl_dev, fwctl);
> > +	struct xe_sysctrl_fwctl_uctx *sc_uctx =
> > +		container_of(uctx, struct xe_sysctrl_fwctl_uctx, uctx);
> > +	struct xe_device *xe = fwctl_dev->xe;
> > +
> > +	xe_pm_runtime_get(xe);
> > +
> > +	sc_uctx->uctx_caps = FWCTL_XE_SYSCTRL_CAP_ECC;
> > +	if (xe_sysctrl_is_diag_fw_ready(xe))
> > +		sc_uctx->uctx_caps |= FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT;
> > +
> > +	return 0;
> > +}
> > +
> > +static void xe_sysctrl_fwctl_uctx_close(struct fwctl_uctx *uctx)
> > +{
> > +	struct xe_sysctrl_fwctl_dev *fwctl_dev =
> > +		container_of(uctx->fwctl, struct xe_sysctrl_fwctl_dev, fwctl);
> > +
> > +	xe_pm_runtime_put(fwctl_dev->xe);
> > +}
> > +
> > +static void *xe_sysctrl_fwctl_info(struct fwctl_uctx *uctx, size_t *length)
> > +{
> > +	struct xe_sysctrl_fwctl_uctx *sc_uctx =
> > +		container_of(uctx, struct xe_sysctrl_fwctl_uctx, uctx);
> > +	struct fwctl_info_xe_sysctrl *info;
> > +
> > +	info = kzalloc_obj(*info);
> > +	if (!info)
> > +		return ERR_PTR(-ENOMEM);
> > +
> > +	info->uctx_caps = sc_uctx->uctx_caps;
> > +
> > +	*length = sizeof(*info);
> > +	return info;
> > +}
> > +
> > +static int sysctrl_rpc_ecc_status_get(struct xe_device *xe,
> > +				      struct fwctl_rpc_xe_sysctrl *rpc)
> > +{
> > +	struct xe_sysctrl_feature_cap_resp resp = {};
> > +	struct xe_sysctrl_mailbox_command cmd = {0};
> > +	size_t out_len = 0;
> > +	int ret;
> > +
> > +	xe_sysctrl_create_command(&cmd, XE_SYSCTRL_GROUP_GFSP_RUNTIME,
> > +				  XE_SYSCTRL_CMD_GET_FEATURE_CAPABILITY_STATE_INFO,
> > +				  NULL, 0, &resp, sizeof(resp));
> > +
> > +	ret = xe_sysctrl_send_command(&xe->sc, &cmd, &out_len);
> > +	if (ret)
> > +		return ret;
> > +
> > +	if (out_len < 2 * sizeof(u32)) {
> > +		xe_err(xe, "sysctrl fwctl: ECC status response too short (%zu B)\n",
> > +		       out_len);
> > +		return -EIO;
> > +	}
> > +
> > +	rpc->data[0] = resp.supported_features & XE_SYSCTRL_FEATURE_ECC ? 1 : 0;
> > +	rpc->data[1] = resp.enabled_features & XE_SYSCTRL_FEATURE_ECC ? 1 : 0;
> > +	return 0;
> > +}
> > +
> > +static int sysctrl_rpc_ras_get_caps(struct xe_device *xe,
> > +				    struct fwctl_rpc_xe_sysctrl *rpc)
> > +{
> > +	struct xe_sysctrl_ras_err_inj_cap_resp resp = {};
> > +	struct xe_sysctrl_mailbox_command cmd = {0};
> > +	size_t out_len = 0;
> > +	int ret;
> > +
> > +	xe_sysctrl_create_command(&cmd, XE_SYSCTRL_GROUP_DIAG,
> > +				  XE_SYSCTRL_CMD_RAS_ERR_INJ_CAPABILITY,
> > +				  NULL, 0, &resp, sizeof(resp));
> > +
> > +	ret = xe_sysctrl_send_command(&xe->sc, &cmd, &out_len);
> > +	if (ret)
> > +		return ret;
> 
> Not checking for short reponse here like in the ECC function above?
> 
> > +
> > +	rpc->data[0] = resp.capability_mask;
> > +	rpc->data[1] = resp.flags;
> > +	return 0;
> > +}
> > +
> > +static int sysctrl_rpc_ras_inject(struct xe_device *xe,
> > +				  struct fwctl_rpc_xe_sysctrl *rpc)
> > +{
> > +	struct xe_sysctrl_ras_err_inj_req req = {
> > +		.error_inj	   = rpc->data[0],
> > +		.additional_params = rpc->data[1],
> > +	};
> > +	struct xe_sysctrl_mailbox_command cmd = {0};
> > +	size_t out_len = 0;
> > +
> 
> We should check if the type of inject is supported. It may mean that we
> cache the err injection capabilities early on (during init). Is that
> possible?

it is already checking on the rpc function below, no?!

> 
> > +	xe_sysctrl_create_command(&cmd, XE_SYSCTRL_GROUP_DIAG,
> > +				  XE_SYSCTRL_CMD_RAS_ERR_INJECT,
> > +				  &req, sizeof(req), NULL, 0);
> > +
> > +	return xe_sysctrl_send_command(&xe->sc, &cmd, &out_len);
> > +}
> > +
> > +static void *xe_sysctrl_fwctl_rpc(struct fwctl_uctx *uctx,
> > +				  enum fwctl_rpc_scope scope,
> > +				  void *rpc_in, size_t in_len,
> > +				  size_t *out_len)
> > +{
> > +	struct xe_sysctrl_fwctl_dev *fwctl_dev =
> > +		container_of(uctx->fwctl, struct xe_sysctrl_fwctl_dev, fwctl);
> > +	struct xe_sysctrl_fwctl_uctx *sc_uctx =
> > +		container_of(uctx, struct xe_sysctrl_fwctl_uctx, uctx);
> > +	struct xe_device *xe = fwctl_dev->xe;
> > +	struct fwctl_rpc_xe_sysctrl *rpc;
> > +	int ret;
> > +
> > +	if (in_len != sizeof(*rpc) || *out_len < sizeof(*rpc))
> > +		return ERR_PTR(-EMSGSIZE);
> > +
> > +	rpc = rpc_in;
> > +
> > +	if (rpc->flags)
> > +		return ERR_PTR(-EINVAL);
> > +
> > +	switch (rpc->op) {
> > +	case FWCTL_XE_SYSCTRL_OP_ECC_STATUS_GET:
> > +		if (!(sc_uctx->uctx_caps & FWCTL_XE_SYSCTRL_CAP_ECC))
> > +			return ERR_PTR(-EPERM);
> 
> 
> EPERM doesn't look correct here. i.e. if the caller were an ADMIN, would
> this work?
> 
> If the caller is trying an RPC that is not available, then this should be
> EINVAL. Same for the below cases.

right, I believe here EINVAL is the best.
But if we need to check for FW permissions given out-of-band even to
admins, then we we need some check on the command result on the injection
function above and then in that case return the -EPERM;

> 
> 
> > +		if (scope < FWCTL_RPC_CONFIGURATION)
> > +			return ERR_PTR(-EBADMSG);
> > +		ret = sysctrl_rpc_ecc_status_get(xe, rpc);
> > +		if (ret)
> > +			return ERR_PTR(ret);
> > +		break;
> > +
> > +	case FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS:
> > +		if (!(sc_uctx->uctx_caps & FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT))
> > +			return ERR_PTR(-EPERM);
> > +		if (scope < FWCTL_RPC_CONFIGURATION)
> > +			return ERR_PTR(-EBADMSG);
> > +		ret = sysctrl_rpc_ras_get_caps(xe, rpc);
> > +		if (ret)
> > +			return ERR_PTR(ret);
> > +		break;
> 
> Do these capabilities change at runtime? If not, why not just cache them
> after first read?

if I remember correctly this is a mandatory thing in FWCTL.. to ensure we
only send valid bits.

> 
> > +
> > +	case FWCTL_XE_SYSCTRL_OP_RAS_INJECT:
> > +		if (!(sc_uctx->uctx_caps & FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT))
> > +			return ERR_PTR(-EPERM);
> > +		if (scope < FWCTL_RPC_DEBUG_WRITE)
> > +			return ERR_PTR(-EBADMSG);
> > +		ret = sysctrl_rpc_ras_inject(xe, rpc);
> > +		if (ret)
> > +			return ERR_PTR(ret);
> > +		break;
> > +
> > +	default:
> > +		return ERR_PTR(-EBADMSG);
> > +	}
> > +
> > +	*out_len = sizeof(*rpc);
> > +	return rpc_in;
> > +}
> > +
> > +static const struct fwctl_ops xe_sysctrl_fwctl_ops = {
> > +	.device_type = FWCTL_DEVICE_TYPE_XE_SYSCTRL,
> > +	.uctx_size = sizeof(struct xe_sysctrl_fwctl_uctx),
> > +	.open_uctx = xe_sysctrl_fwctl_uctx_open,
> > +	.close_uctx = xe_sysctrl_fwctl_uctx_close,
> > +	.info = xe_sysctrl_fwctl_info,
> > +	.fw_rpc = xe_sysctrl_fwctl_rpc,
> > +};
> > +
> > +static void xe_sysctrl_fwctl_fini(void *arg)
> > +{
> > +	struct fwctl_device *fwctl = arg;
> > +
> > +	fwctl_unregister(fwctl);
> > +	fwctl_put(fwctl);
> > +}
> > +
> > +/**
> > + * xe_sysctrl_fwctl_init() - Initialize fwctl interface for System Controller
> > + * @xe: xe device instance
> > + *
> > + * Registers a fwctl device that exposes System Controller debug and
> > + * diagnostic functionality to userspace, on platforms where System
> > + * Controller is supported.
> > + *
> > + * Return: 0 on success, error code on failure
> > + */
> > +int xe_sysctrl_fwctl_init(struct xe_device *xe)
> > +{
> > +	struct xe_sysctrl_fwctl_dev *fwctl_dev __free(xe_sysctrl_fwctl) =
> > +		fwctl_alloc_device(xe->drm.dev, &xe_sysctrl_fwctl_ops,
> > +				   struct xe_sysctrl_fwctl_dev, fwctl);
> > +	int err;
> > +
> > +	if (!xe->info.has_soc_remapper_sysctrl)
> > +		return 0;
> > +
> > +	if (!xe->info.has_sysctrl)
> > +		return 0;
> > +
> > +	if (!fwctl_dev)
> > +		return -ENOMEM;
> > +
> > +	fwctl_dev->xe = xe;
> > +
> > +	err = fwctl_register(&fwctl_dev->fwctl);
> > +	if (err)
> > +		return err;
> > +
> > +	return devm_add_action_or_reset(xe->drm.dev, xe_sysctrl_fwctl_fini,
> > +					&no_free_ptr(fwctl_dev)->fwctl);
> > +}
> > +
> > +MODULE_IMPORT_NS("FWCTL");
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_fwctl.h b/drivers/gpu/drm/xe/xe_sysctrl_fwctl.h
> > new file mode 100644
> > index 000000000000..730f31e0d697
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_fwctl.h
> > @@ -0,0 +1,13 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_SYSCTRL_FWCTL_H_
> > +#define _XE_SYSCTRL_FWCTL_H_
> > +
> > +struct xe_device;
> > +
> > +int xe_sysctrl_fwctl_init(struct xe_device *xe);
> > +
> > +#endif
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> > index b507e1553cbb..7f39fd1a418a 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> > @@ -14,10 +14,14 @@
> >  * enum xe_sysctrl_group - System Controller command groups
> >  *
> >  * @XE_SYSCTRL_GROUP_GFSP: GFSP group
> > + * @XE_SYSCTRL_GROUP_DIAG: Diag group
> > + * @XE_SYSCTRL_GROUP_GFSP_RUNTIME: GFSP runtime group
> >  * @XE_SYSCTRL_GROUP_CORE: Core group
> >  */
> > enum xe_sysctrl_group {
> > 	XE_SYSCTRL_GROUP_GFSP			= 0x01,
> > +	XE_SYSCTRL_GROUP_DIAG			= 0x02,
> > +	XE_SYSCTRL_GROUP_GFSP_RUNTIME		= 0x31,
> > 	XE_SYSCTRL_GROUP_CORE			= 0xFF,
> > };
> > 
> > @@ -103,6 +107,88 @@ enum xe_sysctrl_app_id {
> > 	XE_SYSCTRL_APP_DIAG	= 0x0D,
> > };
> > 
> > +/**
> > + * enum xe_sysctrl_diag_cmd - Commands supported by DIAG group
> > + *
> > + * @XE_SYSCTRL_CMD_RAS_ERR_INJ_CAPABILITY: Query supported RAS injection types
> > + * @XE_SYSCTRL_CMD_RAS_ERR_INJECT: Inject a RAS error into an IP block
> > + */
> > +enum xe_sysctrl_diag_cmd {
> > +	XE_SYSCTRL_CMD_RAS_ERR_INJ_CAPABILITY	= 0x01,
> > +	XE_SYSCTRL_CMD_RAS_ERR_INJECT		= 0x02,
> > +};
> > +
> > +/**
> > + * struct xe_sysctrl_ras_err_inj_cap_resp - RAS_ERR_INJ_CAPABILITY response payload
> > + *
> > + * Response payload for XE_SYSCTRL_CMD_RAS_ERR_INJ_CAPABILITY.  The mailbox
> > + * layer strips the application message header before writing to this buffer.
> > + *
> > + * @capability_mask: OR of firmware-defined capability values indicating which
> > + *                   injection classes are supported on this platform (see
> > + *                   enum fwctl_xe_sysctrl_ras_inj_cap in
> > + *                   include/uapi/fwctl/xe_sysctrl.h for bit definitions)
> > + * @flags:           Bitmask; bit FWCTL_XE_SYSCTRL_RAS_INJ_ALLOWED (see
> > + *                   include/uapi/fwctl/xe_sysctrl.h) indicates whether RAS
> > + *                   error injection is currently allowed by hardware
> > + *                   security policy.
> > + * @reserved:        Must be zero
> > + */
> > +struct xe_sysctrl_ras_err_inj_cap_resp {
> > +	u32 capability_mask;
> > +	u32 flags;
> > +	u32 reserved[2];
> > +} __packed;
> > +
> > +/**
> > + * struct xe_sysctrl_ras_err_inj_req - RAS_ERR_INJECT request payload
> > + *
> > + * Request payload for XE_SYSCTRL_CMD_RAS_ERR_INJECT.  The mailbox layer
> > + * prepends the application message header before sending.
> > + *
> > + * @error_inj:    One of the enum fwctl_xe_sysctrl_ras_inj_cap bit values
> > + *                (include/uapi/fwctl/xe_sysctrl.h), selecting the class of
> > + *                error to inject.
> > + * @additional_params: Reserved for future use; must be 0 for most injection
> > + *                    types
> > + */
> > +struct xe_sysctrl_ras_err_inj_req {
> > +	u32 error_inj;
> > +	u32 additional_params;
> > +} __packed;
> > +
> > +/**
> > + * enum xe_sysctrl_gfsp_runtime_cmd - Commands for the GFSP runtime group (0x31)
> > + *
> > + * @XE_SYSCTRL_CMD_GET_FEATURE_CAPABILITY_STATE_INFO: Read ECC feature state.
> > + *	No input payload.  Response: struct xe_sysctrl_feature_cap_resp.
> > + */
> > +enum xe_sysctrl_gfsp_runtime_cmd {
> > +	XE_SYSCTRL_CMD_GET_FEATURE_CAPABILITY_STATE_INFO	= 0x10,
> > +};
> > +
> > +/** XE_SYSCTRL_FEATURE_ECC - ECC feature bit in FSP runtime capability bitmasks */
> > +#define XE_SYSCTRL_FEATURE_ECC	BIT(0)
> > +
> > +/**
> > + * struct xe_sysctrl_feature_cap_resp - ECC feature state
> > + *
> > + * Response layout for XE_SYSCTRL_CMD_GET_FEATURE_CAPABILITY_STATE_INFO.
> > + *
> > + * @supported_features: Features supported by the product
> > + * @enabled_features: Features currently enabled
> > + * @configurable_features: Features modifiable by software
> > + * @pending_features: Feature state pending after next reboot
> > + * @default_features: Default feature state from build configuration
> > + */
> > +struct xe_sysctrl_feature_cap_resp {
> > +	u32 supported_features;
> > +	u32 enabled_features;
> > +	u32 configurable_features;
> > +	u32 pending_features;
> > +	u32 default_features;
> > +} __packed;
> > +
> > /**
> >  * struct xe_sysctrl_mailbox_command - System Controller mailbox command
> >  */
> > diff --git a/include/uapi/fwctl/fwctl.h b/include/uapi/fwctl/fwctl.h
> > index 2d6d4049c205..34901d36cd51 100644
> > --- a/include/uapi/fwctl/fwctl.h
> > +++ b/include/uapi/fwctl/fwctl.h
> > @@ -46,6 +46,7 @@ enum fwctl_device_type {
> > 	FWCTL_DEVICE_TYPE_CXL = 2,
> > 	FWCTL_DEVICE_TYPE_BNXT = 3,
> > 	FWCTL_DEVICE_TYPE_PDS = 4,
> > +	FWCTL_DEVICE_TYPE_XE_SYSCTRL = 5,
> > };
> > 
> > /**
> > diff --git a/include/uapi/fwctl/xe_sysctrl.h b/include/uapi/fwctl/xe_sysctrl.h
> > new file mode 100644
> > index 000000000000..a4d117d906e3
> > --- /dev/null
> > +++ b/include/uapi/fwctl/xe_sysctrl.h
> > @@ -0,0 +1,117 @@
> > +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
> > +/* Copyright © 2026 Intel Corporation */
> > +#ifndef _UAPI_FWCTL_XE_SYSCTRL_H_
> > +#define _UAPI_FWCTL_XE_SYSCTRL_H_
> > +
> > +#include <linux/bits.h>
> > +#include <linux/types.h>
> > +
> > +/**
> > + * enum fwctl_xe_sysctrl_uctx_caps - capability flags in fwctl_info_xe_sysctrl.uctx_caps
> > + *
> > + * @FWCTL_XE_SYSCTRL_CAP_ECC: ECC status query is supported on this platform
> > + * @FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT: RAS error injection is supported;
> > + *      requires diag firmware to be loaded and ready
> > + */
> > +enum fwctl_xe_sysctrl_uctx_caps {
> > +	FWCTL_XE_SYSCTRL_CAP_ECC		= (1U << 0),
> > +	FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT	= (1U << 1),
> 
> BIT(0)
> BIT(1)
> 
> > +};
> > +
> > +/**
> > + * struct fwctl_info_xe_sysctrl - device data returned by FWCTL_INFO
> > + * @uctx_caps: Bitmask of available capabilities (see %fwctl_xe_sysctrl_uctx_caps)
> > + * @rsvd: Reserved, must be zero
> > + */
> > +struct fwctl_info_xe_sysctrl {
> > +	__u32 uctx_caps;
> > +	__u32 rsvd[7];
> > +};
> > +
> > +/**
> > + * enum fwctl_xe_sysctrl_ras_inj_cap - RAS error injection capability bits
> > + *
> > + * Used both in the @capability_mask output of %FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS
> > + * and as the @error_inj input of %FWCTL_XE_SYSCTRL_OP_RAS_INJECT. Userspace
> > + * must confirm a bit is set in @capability_mask before injecting that class.
> > + *
> > + * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_COMPUTE_CORR: Compute block correctable error
> > + * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_COMPUTE_UCORR: Compute block uncorrectable error
> > + * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_MEMORY_UCORR: Memory subsystem uncorrectable error
> > + * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_FABRIC_UCORR: Fabric interconnect uncorrectable error
> > + * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PCIE_CORR: PCIe subsystem correctable error
> > + * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PCIE_UCORR: PCIe subsystem uncorrectable error
> > + * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PLATFORM_UCORR: Platform-level uncorrectable error
> > + */
> > +enum fwctl_xe_sysctrl_ras_inj_cap {
> > +	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_COMPUTE_CORR	= 0x0001U,
> > +	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_COMPUTE_UCORR	= 0x0002U,
> > +	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_MEMORY_UCORR	= 0x0004U,
> > +	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_FABRIC_UCORR	= 0x0008U,
> > +	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PCIE_CORR		= 0x0010U,
> > +	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PCIE_UCORR		= 0x0020U,
> > +	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PLATFORM_UCORR	= 0x0040U,
> 
> Same here, why not use BIT?
> 
> Thanks,
> Umesh
> 
> > +};
> > +
> > +/* FWCTL_XE_SYSCTRL_RAS_INJ_ALLOWED - bit in the RAS_GET_CAPS flags field
> > + * indicating RAS error injection is currently allowed by hardware security
> > + * policy.
> > + */
> > +#define FWCTL_XE_SYSCTRL_RAS_INJ_ALLOWED	(1U << 0)
> > +
> > +/**
> > + * enum fwctl_xe_sysctrl_op - RPC operation codes for xe_sysctrl fwctl
> > + *
> > + * @FWCTL_XE_SYSCTRL_OP_ECC_STATUS_GET: Read ECC feature state from GFSP firmware
> > + *	(GFSP runtime group, GET_FEATURE_CAPABILITY_STATE_INFO, BIT(0) = ECC).
> > + *	Requires: %FWCTL_XE_SYSCTRL_CAP_ECC in uctx_caps.
> > + *	Scope: %FWCTL_RPC_CONFIGURATION.
> > + *	in:  op, flags=0, data[0..13] ignored.
> > + *	out: data[0] = 1 if ECC is supported by this product, 0 otherwise.
> > + *	     data[1] = 1 if ECC is currently enabled, 0 otherwise.
> > + *
> > + * @FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS: Query RAS error injection capability from
> > + *	diag firmware (DIAG group, RAS_ERR_INJ_CAPABILITY command).
> > + *	Requires: %FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT in uctx_caps.
> > + *	Scope: %FWCTL_RPC_CONFIGURATION.
> > + *	in:  op, flags=0, data[0..13] ignored.
> > + *	out: data[0] = capability_mask, an OR of %fwctl_xe_sysctrl_ras_inj_cap
> > + *	                bits indicating which injection classes are supported,
> > + *	     data[1] = flags; bit %FWCTL_XE_SYSCTRL_RAS_INJ_ALLOWED indicates
> > + *	                whether RAS error injection is currently allowed by
> > + *	                hardware security policy, other bits are reserved for
> > + *	                future use.
> > + *
> > + * @FWCTL_XE_SYSCTRL_OP_RAS_INJECT: Inject a RAS error via diag firmware
> > + *	(DIAG group, RAS_ERR_INJECT command).
> > + *	Requires: %FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT in uctx_caps.
> > + *	Scope: %FWCTL_RPC_DEBUG_WRITE.
> > + *	in:  data[0] = error_inj, one of the %fwctl_xe_sysctrl_ras_inj_cap
> > + *	                bit values. Userspace must confirm this bit is set in
> > + *	                the capability_mask returned by
> > + *	                %FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS (and that its flags
> > + *	                field currently allows injection) before issuing this
> > + *	                request; behavior for an unsupported value is
> > + *	                firmware-defined,
> > + *	     data[1] = additional_params (reserved; 0 for most injection types).
> > + *	out: no additional output data (success indicated by ioctl return code).
> > + */
> > +enum fwctl_xe_sysctrl_op {
> > +	FWCTL_XE_SYSCTRL_OP_ECC_STATUS_GET	= 1,
> > +	FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS	= 2,
> > +	FWCTL_XE_SYSCTRL_OP_RAS_INJECT		= 3,
> > +};
> > +
> > +/**
> > + * struct fwctl_rpc_xe_sysctrl - RPC request/response envelope
> > + * @op: Operation code (see %fwctl_xe_sysctrl_op)
> > + * @flags: Must be 0
> > + * @data: Operation-specific payload (see %fwctl_xe_sysctrl_op for layout)
> > + */
> > +struct fwctl_rpc_xe_sysctrl {
> > +	__u32 op;
> > +	__u32 flags;
> > +	__u32 data[14];
> > +};
> > +
> > +#endif
> > -- 
> > 2.43.0
> > 

Re: [PATCH v2 2/2] drm/xe/sysctrl: Add fwctl support for System Controller

[Umesh Nerlige Ramappa]

On Tue, Aug 25, 2026 at 05:51:59PM -0400, Rodrigo Vivi wrote:
>On Mon, Aug 10, 2026 at 02:11:25PM -0700, Umesh Nerlige Ramappa wrote:
>> On Thu, Aug 06, 2026 at 05:03:12AM -0700, Anoop, Vijay wrote:
>> > From: Anoop Vijay <anoop.c.vijay@intel.com>
>> >
>> > Add fwctl support for Xe System Controller (sysctrl), a
>> > firmware-managed entity that provides platform-level control and
>> > coordination on Intel Xe3p discrete GPUs.
>> >
>> > Register a XE_SYSCTRL device to allow userspace to query sysctrl
>> > capabilities and issue RPCs through /dev/fwctl/fwctlN. Initial
>> > RPCs support ECC status queries and RAS error injection.
>> >
>> > Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
>> > ---
>> > v2: (Rodrigo)
>> > - Rename FWCTL_DEVICE_TYPE_XE to FWCTL_DEVICE_TYPE_XE_SYSCTRL, one type
>> >  per firmware instead of a shared Xe-wide type
>> > - Rename xe.h to xe_sysctrl.h to match
>> > - Squash uapi and type definitions into a single patch
>> > - Replace validate_scope() with explicit per-op scope/capability checks
>> >  in xe_sysctrl_fwctl_rpc()
>> > ---
>> > Documentation/userspace-api/fwctl/index.rst   |   1 +
>> > .../userspace-api/fwctl/xe_sysctrl.rst        | 120 +++++++++
>> > drivers/gpu/drm/xe/Kconfig                    |   1 +
>> > drivers/gpu/drm/xe/Makefile                   |   1 +
>> > drivers/gpu/drm/xe/xe_device.c                |   5 +
>> > drivers/gpu/drm/xe/xe_sysctrl_fwctl.c         | 251 ++++++++++++++++++
>> > drivers/gpu/drm/xe/xe_sysctrl_fwctl.h         |  13 +
>> > drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h |  86 ++++++
>> > include/uapi/fwctl/fwctl.h                    |   1 +
>
>On your next version, please Cc the right addresses:
>
>$ ./scripts/get_maintainer.pl include/uapi/fwctl/
>Dave Jiang <dave.jiang@intel.com> (maintainer:FWCTL SUBSYSTEM)
>Jason Gunthorpe <jgg@ziepe.ca> (maintainer:FWCTL SUBSYSTEM)
>Saeed Mahameed <saeedm@nvidia.com> (maintainer:FWCTL SUBSYSTEM)
>Jonathan Cameron <jic23@kernel.org> (reviewer:FWCTL SUBSYSTEM)
>
>
>> > include/uapi/fwctl/xe_sysctrl.h               | 117 ++++++++
>
>To make our future life easier we might ask them to get the maintainership
>of our files:
>
>diff --git a/MAINTAINERS b/MAINTAINERS
>index 928b3ba23a76..0b912f4b986e 100644
>--- a/MAINTAINERS
>+++ b/MAINTAINERS
>@@ -13016,6 +13016,8 @@ C:      irc://irc.oftc.net/xe
> T:     git https://gitlab.freedesktop.org/drm/xe/kernel.git
> F:     Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> F:     Documentation/gpu/xe/
>+F:     Documentation/userspace-api/fwctl/xe_*
>+F:     include/uapi/fwctl/xe_*
> F:     drivers/gpu/drm/xe/
> F:     include/drm/intel/
> F:     include/uapi/drm/xe_drm.h
>
>
>> > 10 files changed, 596 insertions(+)
>> > create mode 100644 Documentation/userspace-api/fwctl/xe_sysctrl.rst
>> > create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_fwctl.c
>> > create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_fwctl.h
>> > create mode 100644 include/uapi/fwctl/xe_sysctrl.h
>> >
>> > diff --git a/Documentation/userspace-api/fwctl/index.rst b/Documentation/userspace-api/fwctl/index.rst
>> > index 8062f7629654..f6fca11e6aac 100644
>> > --- a/Documentation/userspace-api/fwctl/index.rst
>> > +++ b/Documentation/userspace-api/fwctl/index.rst
>> > @@ -13,3 +13,4 @@ to securely construct and execute RPCs inside device firmware.
>> >    bnxt_fwctl
>> >    fwctl-cxl
>> >    pds_fwctl
>> > +   xe_sysctrl
>> > diff --git a/Documentation/userspace-api/fwctl/xe_sysctrl.rst b/Documentation/userspace-api/fwctl/xe_sysctrl.rst
>> > new file mode 100644
>> > index 000000000000..6dfc9e70b683
>> > --- /dev/null
>> > +++ b/Documentation/userspace-api/fwctl/xe_sysctrl.rst
>> > @@ -0,0 +1,120 @@
>> > +.. SPDX-License-Identifier: GPL-2.0
>> > +
>> > +=======================
>> > +fwctl xe_sysctrl driver
>> > +=======================
>> > +
>> > +:Author: Intel Corporation
>> > +
>> > +Overview
>> > +========
>> > +
>> > +The Xe System Controller (sysctrl) firmware exposes a fwctl service that
>> > +the xe driver registers as a ``FWCTL_DEVICE_TYPE_XE_SYSCTRL`` device.
>> > +Userspace opens the resulting ``/dev/fwctl/fwctlN`` node to query ECC
>> > +status and RAS error injection capabilities and to issue RAS error
>> > +injection requests to the sysctrl firmware.
>> > +
>> > +xe_sysctrl User API
>> > +====================
>> > +
>> > +.. kernel-doc:: include/uapi/fwctl/xe_sysctrl.h
>> > +
>> > +1. Driver info query
>> > +---------------------
>> > +
>> > +The application issues ``FWCTL_INFO`` to retrieve a
>> > +``struct fwctl_info_xe_sysctrl`` and inspect ``uctx_caps`` to determine
>> > +which of the ``FWCTL_XE_SYSCTRL_CAP_*`` capabilities are available on this
>> > +platform and in this security context.
>> > +
>> > +2. Send RPC requests
>> > +---------------------
>> > +
>> > +Each RPC uses a single ``struct fwctl_rpc_xe_sysctrl`` as both the
>> > +``FWCTL_RPC`` ``in`` and ``out`` buffer; the driver fills in ``data`` in
>> > +place. ``op`` selects one of the ``enum fwctl_xe_sysctrl_op`` operations.
>> > +The kernel rejects the request if the scope of the ``FWCTL_RPC`` call is
>> > +lower than the minimum required by the requested ``op``, as documented above.
>> > +
>> > +Code example of querying ECC status
>> > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> > +
>> > +.. code-block:: c
>> > +
>> > +        static int xe_sysctrl_get_ecc(int fd, __u32 *supported, __u32 *enabled)
>> > +        {
>> > +                struct fwctl_rpc_xe_sysctrl sysctrl_rpc = {
>> > +                        .op = FWCTL_XE_SYSCTRL_OP_ECC_STATUS_GET,
>> > +                };
>> > +                struct fwctl_rpc rpc = {
>> > +                        .size = sizeof(rpc),
>> > +                        .scope = FWCTL_RPC_CONFIGURATION,
>> > +                        .in_len = sizeof(sysctrl_rpc),
>> > +                        .out_len = sizeof(sysctrl_rpc),
>> > +                        .in = (__aligned_u64)&sysctrl_rpc,
>> > +                        .out = (__aligned_u64)&sysctrl_rpc,
>> > +                };
>> > +                int ret;
>> > +
>> > +                ret = ioctl(fd, FWCTL_RPC, &rpc);
>> > +                if (ret)
>> > +                        return ret;
>> > +
>> > +                *supported = sysctrl_rpc.data[0];
>> > +                *enabled = sysctrl_rpc.data[1];
>> > +                return 0;
>> > +        }
>> > +
>> > +Code example of querying RAS injection capabilities and injecting an error
>> > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> > +
>> > +.. code-block:: c
>> > +
>> > +        static int xe_sysctrl_get_ras_caps(int fd, __u32 *capability_mask, __u32 *flags)
>> > +        {
>> > +                struct fwctl_rpc_xe_sysctrl sysctrl_rpc = {
>> > +                        .op = FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS,
>> > +                };
>> > +                struct fwctl_rpc rpc = {
>> > +                        .size = sizeof(rpc),
>> > +                        .scope = FWCTL_RPC_CONFIGURATION,
>> > +                        .in_len = sizeof(sysctrl_rpc),
>> > +                        .out_len = sizeof(sysctrl_rpc),
>> > +                        .in = (__aligned_u64)&sysctrl_rpc,
>> > +                        .out = (__aligned_u64)&sysctrl_rpc,
>> > +                };
>> > +                int ret;
>> > +
>> > +                ret = ioctl(fd, FWCTL_RPC, &rpc);
>> > +                if (ret)
>> > +                        return ret;
>> > +
>> > +                *capability_mask = sysctrl_rpc.data[0];
>> > +                *flags = sysctrl_rpc.data[1];
>> > +                return 0;
>> > +        }
>> > +
>> > +        static int xe_sysctrl_ras_inject(int fd, __u32 error_inj)
>> > +        {
>> > +                struct fwctl_rpc_xe_sysctrl sysctrl_rpc = {
>> > +                        .op = FWCTL_XE_SYSCTRL_OP_RAS_INJECT,
>> > +                        .data[0] = error_inj,
>> > +                };
>> > +                struct fwctl_rpc rpc = {
>> > +                        .size = sizeof(rpc),
>> > +                        .scope = FWCTL_RPC_DEBUG_WRITE,
>> > +                        .in_len = sizeof(sysctrl_rpc),
>> > +                        .out_len = sizeof(sysctrl_rpc),
>> > +                        .in = (__aligned_u64)&sysctrl_rpc,
>> > +                        .out = (__aligned_u64)&sysctrl_rpc,
>> > +                };
>> > +
>> > +                /*
>> > +                 * Callers should confirm error_inj is set in capability_mask,
>> > +                 * and that flags allows injection (FWCTL_XE_SYSCTRL_RAS_INJ_ALLOWED),
>> > +                 * as returned by xe_sysctrl_get_ras_caps() above, before injecting.
>> > +                 */
>> > +                return ioctl(fd, FWCTL_RPC, &rpc);
>> > +        }
>>
>> You could just use one function example that injects an error. Part of that
>> implementation would be to query if error injections is available.  That way
>> you can just do away with the comment above.
>>
>> > +
>> > diff --git a/drivers/gpu/drm/xe/Kconfig b/drivers/gpu/drm/xe/Kconfig
>> > index 4d7dcaff2b91..a472cb52dded 100644
>> > --- a/drivers/gpu/drm/xe/Kconfig
>> > +++ b/drivers/gpu/drm/xe/Kconfig
>> > @@ -25,6 +25,7 @@ config DRM_XE
>> > 	select DRM_MIPI_DSI
>> > 	select RELAY
>> > 	select IRQ_WORK
>> > +	select FWCTL
>> > 	# xe depends on ACPI_VIDEO when ACPI is enabled
>> > 	# but for select to work, need to select ACPI_VIDEO's dependencies, ick
>> > 	select BACKLIGHT_CLASS_DEVICE if ACPI
>> > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>> > index 44ed055439d4..6560185c0ca7 100644
>> > --- a/drivers/gpu/drm/xe/Makefile
>> > +++ b/drivers/gpu/drm/xe/Makefile
>> > @@ -128,6 +128,7 @@ xe-y += xe_bb.o \
>> > 	xe_sync.o \
>> > 	xe_sysctrl.o \
>> > 	xe_sysctrl_event.o \
>> > +	xe_sysctrl_fwctl.o \
>> > 	xe_sysctrl_mailbox.o \
>> > 	xe_tile.o \
>> > 	xe_tile_sysfs.o \
>> > diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
>> > index d25d02b24898..dc7df793d4b9 100644
>> > --- a/drivers/gpu/drm/xe/xe_device.c
>> > +++ b/drivers/gpu/drm/xe/xe_device.c
>> > @@ -68,6 +68,7 @@
>> > #include "xe_sriov.h"
>> > #include "xe_svm.h"
>> > #include "xe_sysctrl.h"
>> > +#include "xe_sysctrl_fwctl.h"
>> > #include "xe_tile.h"
>> > #include "xe_ttm_stolen_mgr.h"
>> > #include "xe_ttm_sys_mgr.h"
>> > @@ -1028,6 +1029,10 @@ int xe_device_probe(struct xe_device *xe)
>> > 	if (err)
>> > 		return err;
>> >
>> > +	err = xe_sysctrl_fwctl_init(xe);
>> > +	if (err)
>> > +		return err;
>> > +
>> > 	xe_ras_init(xe);
>> >
>> > 	/*
>> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_fwctl.c b/drivers/gpu/drm/xe/xe_sysctrl_fwctl.c
>> > new file mode 100644
>> > index 000000000000..27a40efa0787
>> > --- /dev/null
>> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_fwctl.c
>> > @@ -0,0 +1,251 @@
>> > +// SPDX-License-Identifier: MIT
>> > +/*
>> > + * Copyright © 2026 Intel Corporation
>> > + */
>> > +
>> > +#include <linux/errno.h>
>> > +#include <linux/fwctl.h>
>> > +#include <linux/slab.h>
>> > +
>> > +#include <uapi/fwctl/xe_sysctrl.h>
>> > +
>> > +#include "xe_device.h"
>> > +#include "xe_pm.h"
>> > +#include "xe_printk.h"
>> > +#include "xe_sysctrl.h"
>> > +#include "xe_sysctrl_fwctl.h"
>> > +#include "xe_sysctrl_mailbox.h"
>> > +#include "xe_sysctrl_mailbox_types.h"
>> > +
>> > +struct xe_sysctrl_fwctl_dev {
>> > +	struct fwctl_device fwctl;
>> > +	struct xe_device *xe;
>> > +};
>> > +
>> > +DEFINE_FREE(xe_sysctrl_fwctl, struct xe_sysctrl_fwctl_dev *, if (_T) fwctl_put(&_T->fwctl))
>> > +
>> > +struct xe_sysctrl_fwctl_uctx {
>> > +	struct fwctl_uctx uctx;
>> > +	u32 uctx_caps;
>> > +};
>> > +
>> > +static int xe_sysctrl_fwctl_uctx_open(struct fwctl_uctx *uctx)
>> > +{
>> > +	struct xe_sysctrl_fwctl_dev *fwctl_dev =
>> > +		container_of(uctx->fwctl, struct xe_sysctrl_fwctl_dev, fwctl);
>> > +	struct xe_sysctrl_fwctl_uctx *sc_uctx =
>> > +		container_of(uctx, struct xe_sysctrl_fwctl_uctx, uctx);
>> > +	struct xe_device *xe = fwctl_dev->xe;
>> > +
>> > +	xe_pm_runtime_get(xe);
>> > +
>> > +	sc_uctx->uctx_caps = FWCTL_XE_SYSCTRL_CAP_ECC;
>> > +	if (xe_sysctrl_is_diag_fw_ready(xe))
>> > +		sc_uctx->uctx_caps |= FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT;
>> > +
>> > +	return 0;
>> > +}
>> > +
>> > +static void xe_sysctrl_fwctl_uctx_close(struct fwctl_uctx *uctx)
>> > +{
>> > +	struct xe_sysctrl_fwctl_dev *fwctl_dev =
>> > +		container_of(uctx->fwctl, struct xe_sysctrl_fwctl_dev, fwctl);
>> > +
>> > +	xe_pm_runtime_put(fwctl_dev->xe);
>> > +}
>> > +
>> > +static void *xe_sysctrl_fwctl_info(struct fwctl_uctx *uctx, size_t *length)
>> > +{
>> > +	struct xe_sysctrl_fwctl_uctx *sc_uctx =
>> > +		container_of(uctx, struct xe_sysctrl_fwctl_uctx, uctx);
>> > +	struct fwctl_info_xe_sysctrl *info;
>> > +
>> > +	info = kzalloc_obj(*info);
>> > +	if (!info)
>> > +		return ERR_PTR(-ENOMEM);
>> > +
>> > +	info->uctx_caps = sc_uctx->uctx_caps;
>> > +
>> > +	*length = sizeof(*info);
>> > +	return info;
>> > +}
>> > +
>> > +static int sysctrl_rpc_ecc_status_get(struct xe_device *xe,
>> > +				      struct fwctl_rpc_xe_sysctrl *rpc)
>> > +{
>> > +	struct xe_sysctrl_feature_cap_resp resp = {};
>> > +	struct xe_sysctrl_mailbox_command cmd = {0};
>> > +	size_t out_len = 0;
>> > +	int ret;
>> > +
>> > +	xe_sysctrl_create_command(&cmd, XE_SYSCTRL_GROUP_GFSP_RUNTIME,
>> > +				  XE_SYSCTRL_CMD_GET_FEATURE_CAPABILITY_STATE_INFO,
>> > +				  NULL, 0, &resp, sizeof(resp));
>> > +
>> > +	ret = xe_sysctrl_send_command(&xe->sc, &cmd, &out_len);
>> > +	if (ret)
>> > +		return ret;
>> > +
>> > +	if (out_len < 2 * sizeof(u32)) {
>> > +		xe_err(xe, "sysctrl fwctl: ECC status response too short (%zu B)\n",
>> > +		       out_len);
>> > +		return -EIO;
>> > +	}
>> > +
>> > +	rpc->data[0] = resp.supported_features & XE_SYSCTRL_FEATURE_ECC ? 1 : 0;
>> > +	rpc->data[1] = resp.enabled_features & XE_SYSCTRL_FEATURE_ECC ? 1 : 0;
>> > +	return 0;
>> > +}
>> > +
>> > +static int sysctrl_rpc_ras_get_caps(struct xe_device *xe,
>> > +				    struct fwctl_rpc_xe_sysctrl *rpc)
>> > +{
>> > +	struct xe_sysctrl_ras_err_inj_cap_resp resp = {};
>> > +	struct xe_sysctrl_mailbox_command cmd = {0};
>> > +	size_t out_len = 0;
>> > +	int ret;
>> > +
>> > +	xe_sysctrl_create_command(&cmd, XE_SYSCTRL_GROUP_DIAG,
>> > +				  XE_SYSCTRL_CMD_RAS_ERR_INJ_CAPABILITY,
>> > +				  NULL, 0, &resp, sizeof(resp));
>> > +
>> > +	ret = xe_sysctrl_send_command(&xe->sc, &cmd, &out_len);
>> > +	if (ret)
>> > +		return ret;
>>
>> Not checking for short reponse here like in the ECC function above?
>>
>> > +
>> > +	rpc->data[0] = resp.capability_mask;
>> > +	rpc->data[1] = resp.flags;
>> > +	return 0;
>> > +}
>> > +
>> > +static int sysctrl_rpc_ras_inject(struct xe_device *xe,
>> > +				  struct fwctl_rpc_xe_sysctrl *rpc)
>> > +{
>> > +	struct xe_sysctrl_ras_err_inj_req req = {
>> > +		.error_inj	   = rpc->data[0],
>> > +		.additional_params = rpc->data[1],
>> > +	};
>> > +	struct xe_sysctrl_mailbox_command cmd = {0};
>> > +	size_t out_len = 0;
>> > +
>>
>> We should check if the type of inject is supported. It may mean that we
>> cache the err injection capabilities early on (during init). Is that
>> possible?
>
>it is already checking on the rpc function below, no?!
>

oh, my bad. I overlooked that.

>>
>> > +	xe_sysctrl_create_command(&cmd, XE_SYSCTRL_GROUP_DIAG,
>> > +				  XE_SYSCTRL_CMD_RAS_ERR_INJECT,
>> > +				  &req, sizeof(req), NULL, 0);
>> > +
>> > +	return xe_sysctrl_send_command(&xe->sc, &cmd, &out_len);
>> > +}
>> > +
>> > +static void *xe_sysctrl_fwctl_rpc(struct fwctl_uctx *uctx,
>> > +				  enum fwctl_rpc_scope scope,
>> > +				  void *rpc_in, size_t in_len,
>> > +				  size_t *out_len)
>> > +{
>> > +	struct xe_sysctrl_fwctl_dev *fwctl_dev =
>> > +		container_of(uctx->fwctl, struct xe_sysctrl_fwctl_dev, fwctl);
>> > +	struct xe_sysctrl_fwctl_uctx *sc_uctx =
>> > +		container_of(uctx, struct xe_sysctrl_fwctl_uctx, uctx);
>> > +	struct xe_device *xe = fwctl_dev->xe;
>> > +	struct fwctl_rpc_xe_sysctrl *rpc;
>> > +	int ret;
>> > +
>> > +	if (in_len != sizeof(*rpc) || *out_len < sizeof(*rpc))
>> > +		return ERR_PTR(-EMSGSIZE);
>> > +
>> > +	rpc = rpc_in;
>> > +
>> > +	if (rpc->flags)
>> > +		return ERR_PTR(-EINVAL);
>> > +
>> > +	switch (rpc->op) {
>> > +	case FWCTL_XE_SYSCTRL_OP_ECC_STATUS_GET:
>> > +		if (!(sc_uctx->uctx_caps & FWCTL_XE_SYSCTRL_CAP_ECC))
>> > +			return ERR_PTR(-EPERM);
>>
>>
>> EPERM doesn't look correct here. i.e. if the caller were an ADMIN, would
>> this work?
>>
>> If the caller is trying an RPC that is not available, then this should be
>> EINVAL. Same for the below cases.
>
>right, I believe here EINVAL is the best.
>But if we need to check for FW permissions given out-of-band even to
>admins, then we we need some check on the command result on the injection
>function above and then in that case return the -EPERM;

Agree, if command result provides that info, it can be used.

>
>>
>>
>> > +		if (scope < FWCTL_RPC_CONFIGURATION)
>> > +			return ERR_PTR(-EBADMSG);
>> > +		ret = sysctrl_rpc_ecc_status_get(xe, rpc);
>> > +		if (ret)
>> > +			return ERR_PTR(ret);
>> > +		break;
>> > +
>> > +	case FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS:
>> > +		if (!(sc_uctx->uctx_caps & FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT))
>> > +			return ERR_PTR(-EPERM);
>> > +		if (scope < FWCTL_RPC_CONFIGURATION)
>> > +			return ERR_PTR(-EBADMSG);
>> > +		ret = sysctrl_rpc_ras_get_caps(xe, rpc);
>> > +		if (ret)
>> > +			return ERR_PTR(ret);
>> > +		break;
>>
>> Do these capabilities change at runtime? If not, why not just cache them
>> after first read?
>
>if I remember correctly this is a mandatory thing in FWCTL.. to ensure we
>only send valid bits.

ok, got it.

Thanks,
Umesh
>>
>> > +
>> > +	case FWCTL_XE_SYSCTRL_OP_RAS_INJECT:
>> > +		if (!(sc_uctx->uctx_caps & FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT))
>> > +			return ERR_PTR(-EPERM);
>> > +		if (scope < FWCTL_RPC_DEBUG_WRITE)
>> > +			return ERR_PTR(-EBADMSG);
>> > +		ret = sysctrl_rpc_ras_inject(xe, rpc);
>> > +		if (ret)
>> > +			return ERR_PTR(ret);
>> > +		break;
>> > +
>> > +	default:
>> > +		return ERR_PTR(-EBADMSG);
>> > +	}
>> > +
>> > +	*out_len = sizeof(*rpc);
>> > +	return rpc_in;
>> > +}
>> > +
>> > +static const struct fwctl_ops xe_sysctrl_fwctl_ops = {
>> > +	.device_type = FWCTL_DEVICE_TYPE_XE_SYSCTRL,
>> > +	.uctx_size = sizeof(struct xe_sysctrl_fwctl_uctx),
>> > +	.open_uctx = xe_sysctrl_fwctl_uctx_open,
>> > +	.close_uctx = xe_sysctrl_fwctl_uctx_close,
>> > +	.info = xe_sysctrl_fwctl_info,
>> > +	.fw_rpc = xe_sysctrl_fwctl_rpc,
>> > +};
>> > +
>> > +static void xe_sysctrl_fwctl_fini(void *arg)
>> > +{
>> > +	struct fwctl_device *fwctl = arg;
>> > +
>> > +	fwctl_unregister(fwctl);
>> > +	fwctl_put(fwctl);
>> > +}
>> > +
>> > +/**
>> > + * xe_sysctrl_fwctl_init() - Initialize fwctl interface for System Controller
>> > + * @xe: xe device instance
>> > + *
>> > + * Registers a fwctl device that exposes System Controller debug and
>> > + * diagnostic functionality to userspace, on platforms where System
>> > + * Controller is supported.
>> > + *
>> > + * Return: 0 on success, error code on failure
>> > + */
>> > +int xe_sysctrl_fwctl_init(struct xe_device *xe)
>> > +{
>> > +	struct xe_sysctrl_fwctl_dev *fwctl_dev __free(xe_sysctrl_fwctl) =
>> > +		fwctl_alloc_device(xe->drm.dev, &xe_sysctrl_fwctl_ops,
>> > +				   struct xe_sysctrl_fwctl_dev, fwctl);
>> > +	int err;
>> > +
>> > +	if (!xe->info.has_soc_remapper_sysctrl)
>> > +		return 0;
>> > +
>> > +	if (!xe->info.has_sysctrl)
>> > +		return 0;
>> > +
>> > +	if (!fwctl_dev)
>> > +		return -ENOMEM;
>> > +
>> > +	fwctl_dev->xe = xe;
>> > +
>> > +	err = fwctl_register(&fwctl_dev->fwctl);
>> > +	if (err)
>> > +		return err;
>> > +
>> > +	return devm_add_action_or_reset(xe->drm.dev, xe_sysctrl_fwctl_fini,
>> > +					&no_free_ptr(fwctl_dev)->fwctl);
>> > +}
>> > +
>> > +MODULE_IMPORT_NS("FWCTL");
>> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_fwctl.h b/drivers/gpu/drm/xe/xe_sysctrl_fwctl.h
>> > new file mode 100644
>> > index 000000000000..730f31e0d697
>> > --- /dev/null
>> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_fwctl.h
>> > @@ -0,0 +1,13 @@
>> > +/* SPDX-License-Identifier: MIT */
>> > +/*
>> > + * Copyright © 2026 Intel Corporation
>> > + */
>> > +
>> > +#ifndef _XE_SYSCTRL_FWCTL_H_
>> > +#define _XE_SYSCTRL_FWCTL_H_
>> > +
>> > +struct xe_device;
>> > +
>> > +int xe_sysctrl_fwctl_init(struct xe_device *xe);
>> > +
>> > +#endif
>> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
>> > index b507e1553cbb..7f39fd1a418a 100644
>> > --- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
>> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
>> > @@ -14,10 +14,14 @@
>> >  * enum xe_sysctrl_group - System Controller command groups
>> >  *
>> >  * @XE_SYSCTRL_GROUP_GFSP: GFSP group
>> > + * @XE_SYSCTRL_GROUP_DIAG: Diag group
>> > + * @XE_SYSCTRL_GROUP_GFSP_RUNTIME: GFSP runtime group
>> >  * @XE_SYSCTRL_GROUP_CORE: Core group
>> >  */
>> > enum xe_sysctrl_group {
>> > 	XE_SYSCTRL_GROUP_GFSP			= 0x01,
>> > +	XE_SYSCTRL_GROUP_DIAG			= 0x02,
>> > +	XE_SYSCTRL_GROUP_GFSP_RUNTIME		= 0x31,
>> > 	XE_SYSCTRL_GROUP_CORE			= 0xFF,
>> > };
>> >
>> > @@ -103,6 +107,88 @@ enum xe_sysctrl_app_id {
>> > 	XE_SYSCTRL_APP_DIAG	= 0x0D,
>> > };
>> >
>> > +/**
>> > + * enum xe_sysctrl_diag_cmd - Commands supported by DIAG group
>> > + *
>> > + * @XE_SYSCTRL_CMD_RAS_ERR_INJ_CAPABILITY: Query supported RAS injection types
>> > + * @XE_SYSCTRL_CMD_RAS_ERR_INJECT: Inject a RAS error into an IP block
>> > + */
>> > +enum xe_sysctrl_diag_cmd {
>> > +	XE_SYSCTRL_CMD_RAS_ERR_INJ_CAPABILITY	= 0x01,
>> > +	XE_SYSCTRL_CMD_RAS_ERR_INJECT		= 0x02,
>> > +};
>> > +
>> > +/**
>> > + * struct xe_sysctrl_ras_err_inj_cap_resp - RAS_ERR_INJ_CAPABILITY response payload
>> > + *
>> > + * Response payload for XE_SYSCTRL_CMD_RAS_ERR_INJ_CAPABILITY.  The mailbox
>> > + * layer strips the application message header before writing to this buffer.
>> > + *
>> > + * @capability_mask: OR of firmware-defined capability values indicating which
>> > + *                   injection classes are supported on this platform (see
>> > + *                   enum fwctl_xe_sysctrl_ras_inj_cap in
>> > + *                   include/uapi/fwctl/xe_sysctrl.h for bit definitions)
>> > + * @flags:           Bitmask; bit FWCTL_XE_SYSCTRL_RAS_INJ_ALLOWED (see
>> > + *                   include/uapi/fwctl/xe_sysctrl.h) indicates whether RAS
>> > + *                   error injection is currently allowed by hardware
>> > + *                   security policy.
>> > + * @reserved:        Must be zero
>> > + */
>> > +struct xe_sysctrl_ras_err_inj_cap_resp {
>> > +	u32 capability_mask;
>> > +	u32 flags;
>> > +	u32 reserved[2];
>> > +} __packed;
>> > +
>> > +/**
>> > + * struct xe_sysctrl_ras_err_inj_req - RAS_ERR_INJECT request payload
>> > + *
>> > + * Request payload for XE_SYSCTRL_CMD_RAS_ERR_INJECT.  The mailbox layer
>> > + * prepends the application message header before sending.
>> > + *
>> > + * @error_inj:    One of the enum fwctl_xe_sysctrl_ras_inj_cap bit values
>> > + *                (include/uapi/fwctl/xe_sysctrl.h), selecting the class of
>> > + *                error to inject.
>> > + * @additional_params: Reserved for future use; must be 0 for most injection
>> > + *                    types
>> > + */
>> > +struct xe_sysctrl_ras_err_inj_req {
>> > +	u32 error_inj;
>> > +	u32 additional_params;
>> > +} __packed;
>> > +
>> > +/**
>> > + * enum xe_sysctrl_gfsp_runtime_cmd - Commands for the GFSP runtime group (0x31)
>> > + *
>> > + * @XE_SYSCTRL_CMD_GET_FEATURE_CAPABILITY_STATE_INFO: Read ECC feature state.
>> > + *	No input payload.  Response: struct xe_sysctrl_feature_cap_resp.
>> > + */
>> > +enum xe_sysctrl_gfsp_runtime_cmd {
>> > +	XE_SYSCTRL_CMD_GET_FEATURE_CAPABILITY_STATE_INFO	= 0x10,
>> > +};
>> > +
>> > +/** XE_SYSCTRL_FEATURE_ECC - ECC feature bit in FSP runtime capability bitmasks */
>> > +#define XE_SYSCTRL_FEATURE_ECC	BIT(0)
>> > +
>> > +/**
>> > + * struct xe_sysctrl_feature_cap_resp - ECC feature state
>> > + *
>> > + * Response layout for XE_SYSCTRL_CMD_GET_FEATURE_CAPABILITY_STATE_INFO.
>> > + *
>> > + * @supported_features: Features supported by the product
>> > + * @enabled_features: Features currently enabled
>> > + * @configurable_features: Features modifiable by software
>> > + * @pending_features: Feature state pending after next reboot
>> > + * @default_features: Default feature state from build configuration
>> > + */
>> > +struct xe_sysctrl_feature_cap_resp {
>> > +	u32 supported_features;
>> > +	u32 enabled_features;
>> > +	u32 configurable_features;
>> > +	u32 pending_features;
>> > +	u32 default_features;
>> > +} __packed;
>> > +
>> > /**
>> >  * struct xe_sysctrl_mailbox_command - System Controller mailbox command
>> >  */
>> > diff --git a/include/uapi/fwctl/fwctl.h b/include/uapi/fwctl/fwctl.h
>> > index 2d6d4049c205..34901d36cd51 100644
>> > --- a/include/uapi/fwctl/fwctl.h
>> > +++ b/include/uapi/fwctl/fwctl.h
>> > @@ -46,6 +46,7 @@ enum fwctl_device_type {
>> > 	FWCTL_DEVICE_TYPE_CXL = 2,
>> > 	FWCTL_DEVICE_TYPE_BNXT = 3,
>> > 	FWCTL_DEVICE_TYPE_PDS = 4,
>> > +	FWCTL_DEVICE_TYPE_XE_SYSCTRL = 5,
>> > };
>> >
>> > /**
>> > diff --git a/include/uapi/fwctl/xe_sysctrl.h b/include/uapi/fwctl/xe_sysctrl.h
>> > new file mode 100644
>> > index 000000000000..a4d117d906e3
>> > --- /dev/null
>> > +++ b/include/uapi/fwctl/xe_sysctrl.h
>> > @@ -0,0 +1,117 @@
>> > +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
>> > +/* Copyright © 2026 Intel Corporation */
>> > +#ifndef _UAPI_FWCTL_XE_SYSCTRL_H_
>> > +#define _UAPI_FWCTL_XE_SYSCTRL_H_
>> > +
>> > +#include <linux/bits.h>
>> > +#include <linux/types.h>
>> > +
>> > +/**
>> > + * enum fwctl_xe_sysctrl_uctx_caps - capability flags in fwctl_info_xe_sysctrl.uctx_caps
>> > + *
>> > + * @FWCTL_XE_SYSCTRL_CAP_ECC: ECC status query is supported on this platform
>> > + * @FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT: RAS error injection is supported;
>> > + *      requires diag firmware to be loaded and ready
>> > + */
>> > +enum fwctl_xe_sysctrl_uctx_caps {
>> > +	FWCTL_XE_SYSCTRL_CAP_ECC		= (1U << 0),
>> > +	FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT	= (1U << 1),
>>
>> BIT(0)
>> BIT(1)
>>
>> > +};
>> > +
>> > +/**
>> > + * struct fwctl_info_xe_sysctrl - device data returned by FWCTL_INFO
>> > + * @uctx_caps: Bitmask of available capabilities (see %fwctl_xe_sysctrl_uctx_caps)
>> > + * @rsvd: Reserved, must be zero
>> > + */
>> > +struct fwctl_info_xe_sysctrl {
>> > +	__u32 uctx_caps;
>> > +	__u32 rsvd[7];
>> > +};
>> > +
>> > +/**
>> > + * enum fwctl_xe_sysctrl_ras_inj_cap - RAS error injection capability bits
>> > + *
>> > + * Used both in the @capability_mask output of %FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS
>> > + * and as the @error_inj input of %FWCTL_XE_SYSCTRL_OP_RAS_INJECT. Userspace
>> > + * must confirm a bit is set in @capability_mask before injecting that class.
>> > + *
>> > + * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_COMPUTE_CORR: Compute block correctable error
>> > + * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_COMPUTE_UCORR: Compute block uncorrectable error
>> > + * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_MEMORY_UCORR: Memory subsystem uncorrectable error
>> > + * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_FABRIC_UCORR: Fabric interconnect uncorrectable error
>> > + * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PCIE_CORR: PCIe subsystem correctable error
>> > + * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PCIE_UCORR: PCIe subsystem uncorrectable error
>> > + * @FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PLATFORM_UCORR: Platform-level uncorrectable error
>> > + */
>> > +enum fwctl_xe_sysctrl_ras_inj_cap {
>> > +	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_COMPUTE_CORR	= 0x0001U,
>> > +	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_COMPUTE_UCORR	= 0x0002U,
>> > +	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_MEMORY_UCORR	= 0x0004U,
>> > +	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_FABRIC_UCORR	= 0x0008U,
>> > +	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PCIE_CORR		= 0x0010U,
>> > +	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PCIE_UCORR		= 0x0020U,
>> > +	FWCTL_XE_SYSCTRL_RAS_INJ_CAP_PLATFORM_UCORR	= 0x0040U,
>>
>> Same here, why not use BIT?
>>
>> Thanks,
>> Umesh
>>
>> > +};
>> > +
>> > +/* FWCTL_XE_SYSCTRL_RAS_INJ_ALLOWED - bit in the RAS_GET_CAPS flags field
>> > + * indicating RAS error injection is currently allowed by hardware security
>> > + * policy.
>> > + */
>> > +#define FWCTL_XE_SYSCTRL_RAS_INJ_ALLOWED	(1U << 0)
>> > +
>> > +/**
>> > + * enum fwctl_xe_sysctrl_op - RPC operation codes for xe_sysctrl fwctl
>> > + *
>> > + * @FWCTL_XE_SYSCTRL_OP_ECC_STATUS_GET: Read ECC feature state from GFSP firmware
>> > + *	(GFSP runtime group, GET_FEATURE_CAPABILITY_STATE_INFO, BIT(0) = ECC).
>> > + *	Requires: %FWCTL_XE_SYSCTRL_CAP_ECC in uctx_caps.
>> > + *	Scope: %FWCTL_RPC_CONFIGURATION.
>> > + *	in:  op, flags=0, data[0..13] ignored.
>> > + *	out: data[0] = 1 if ECC is supported by this product, 0 otherwise.
>> > + *	     data[1] = 1 if ECC is currently enabled, 0 otherwise.
>> > + *
>> > + * @FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS: Query RAS error injection capability from
>> > + *	diag firmware (DIAG group, RAS_ERR_INJ_CAPABILITY command).
>> > + *	Requires: %FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT in uctx_caps.
>> > + *	Scope: %FWCTL_RPC_CONFIGURATION.
>> > + *	in:  op, flags=0, data[0..13] ignored.
>> > + *	out: data[0] = capability_mask, an OR of %fwctl_xe_sysctrl_ras_inj_cap
>> > + *	                bits indicating which injection classes are supported,
>> > + *	     data[1] = flags; bit %FWCTL_XE_SYSCTRL_RAS_INJ_ALLOWED indicates
>> > + *	                whether RAS error injection is currently allowed by
>> > + *	                hardware security policy, other bits are reserved for
>> > + *	                future use.
>> > + *
>> > + * @FWCTL_XE_SYSCTRL_OP_RAS_INJECT: Inject a RAS error via diag firmware
>> > + *	(DIAG group, RAS_ERR_INJECT command).
>> > + *	Requires: %FWCTL_XE_SYSCTRL_CAP_RAS_ERROR_INJECT in uctx_caps.
>> > + *	Scope: %FWCTL_RPC_DEBUG_WRITE.
>> > + *	in:  data[0] = error_inj, one of the %fwctl_xe_sysctrl_ras_inj_cap
>> > + *	                bit values. Userspace must confirm this bit is set in
>> > + *	                the capability_mask returned by
>> > + *	                %FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS (and that its flags
>> > + *	                field currently allows injection) before issuing this
>> > + *	                request; behavior for an unsupported value is
>> > + *	                firmware-defined,
>> > + *	     data[1] = additional_params (reserved; 0 for most injection types).
>> > + *	out: no additional output data (success indicated by ioctl return code).
>> > + */
>> > +enum fwctl_xe_sysctrl_op {
>> > +	FWCTL_XE_SYSCTRL_OP_ECC_STATUS_GET	= 1,
>> > +	FWCTL_XE_SYSCTRL_OP_RAS_GET_CAPS	= 2,
>> > +	FWCTL_XE_SYSCTRL_OP_RAS_INJECT		= 3,
>> > +};
>> > +
>> > +/**
>> > + * struct fwctl_rpc_xe_sysctrl - RPC request/response envelope
>> > + * @op: Operation code (see %fwctl_xe_sysctrl_op)
>> > + * @flags: Must be 0
>> > + * @data: Operation-specific payload (see %fwctl_xe_sysctrl_op for layout)
>> > + */
>> > +struct fwctl_rpc_xe_sysctrl {
>> > +	__u32 op;
>> > +	__u32 flags;
>> > +	__u32 data[14];
>> > +};
>> > +
>> > +#endif
>> > --
>> > 2.43.0
>> >