[PATCH 0/3] drm/xe/hwmon: Update hwmon thermal mailbox handling

[PATCH 0/3] drm/xe/hwmon: Update hwmon thermal mailbox handling

[Karthik Poosa]

This series adds CRI-specific temperature sensor handling to the Xe
hwmon implementation.
 
CRI platforms may report unavailable temperature sensors and support
a variable number of VRAM temperature channels depending on platform
configuration. This series adds the required sensor presence checks and
uses platform-reported thermal configuration data to expose only valid
temperature-related hwmon attributes.
 
The series also corrects the telemetry group selection used for memory
controller temperature reporting.

Karthik Poosa (3):
  drm/xe/hwmon: Detect unavailable temperature sensors
  drm/xe/hwmon: Use VRAM temperature sensor count from thermal config on
    CRI
  drm/xe/hwmon: Correct group selection for memory controller
    temperature

 drivers/gpu/drm/xe/xe_hwmon.c     | 116 +++++++++++++++++++++++++-----
 drivers/gpu/drm/xe/xe_pcode_api.h |   1 +
 2 files changed, 98 insertions(+), 19 deletions(-)

-- 
2.25.1

[PATCH 1/3] drm/xe/hwmon: Detect unavailable temperature sensors

[Karthik Poosa]

Add is_temp_valid() to validate sensor presence.
A temperature reading of 0xFF on CRI platforms indicates that the
corresponding sensor is not present and should be treated as unavailable.

Use this check from xe_hwmon_temp_is_visible() callback so that attributes
for unavailable sensors are not exposed during hwmon device registration.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 79 +++++++++++++++++++++++++++++------
 1 file changed, 66 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 5284cab6703d..2c4eba4b8f8f 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -813,12 +813,21 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
 	return ret;
 }
 
+static inline bool is_temp_valid(const struct xe_hwmon *hwmon, u8 value)
+{
+	/* Value of 0xFF indicates unavailable sensor for platforms from CRI. */
+	if (hwmon->xe->info.platform >= XE_CRESCENTISLAND)
+		return value != U8_MAX;
+	else
+		return value != 0;
+}
+
 static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
 	u32 *dword = (u32 *)hwmon->temp.value;
+	int ret, i, count = 0;
 	s32 average = 0;
-	int ret, i;
 
 	for (i = 0; i < DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32)); i++) {
 		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
@@ -828,11 +837,25 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 		drm_dbg(&hwmon->xe->drm, "thermal data for group %d val 0x%x\n", i, dword[i]);
 	}
 
-	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++)
-		average += hwmon->temp.value[i];
+	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++) {
+		if (is_temp_valid(hwmon, hwmon->temp.value[i])) {
+			average += hwmon->temp.value[i];
+			count++;
+		} else {
+			drm_dbg(&hwmon->xe->drm, "mc temp sensor %d not available, val 0x%x\n",
+				i, hwmon->temp.value[i]);
+		}
+	}
+
+	if (!count) {
+		drm_warn(&hwmon->xe->drm, "no memory temp sensors available!\n");
+		return -ENXIO;
+	}
+
+	average /= count;
+	if (val)
+		*val = average * MILLIDEGREE_PER_DEGREE;
 
-	average /= (hwmon->temp.count - TEMP_INDEX_MCTRL - 1);
-	*val = average * MILLIDEGREE_PER_DEGREE;
 	return 0;
 }
 
@@ -852,7 +875,13 @@ static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
 		data = REG_FIELD_GET(PCIE_SENSOR_MASK, data);
 
 	data = REG_FIELD_GET(TEMP_MASK, data);
-	*val = (s8)data * MILLIDEGREE_PER_DEGREE;
+	if (!is_temp_valid(hwmon, data)) {
+		drm_warn(&hwmon->xe->drm, "pcie temp sensor not available, val 0x%x\n", data);
+		return -ENXIO;
+	}
+
+	if (val)
+		*val = (s8)data * MILLIDEGREE_PER_DEGREE;
 
 	return 0;
 }
@@ -956,11 +985,21 @@ static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
 	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
 	int vram_id = channel - CHANNEL_VRAM_N;
 	struct xe_reg vram_reg;
+	u32 reg_val;
+	u8 temp;
 
 	vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
-	if (!xe_reg_is_valid(vram_reg) || !xe_mmio_read32(mmio, vram_reg))
+	if (!xe_reg_is_valid(vram_reg))
 		return false;
 
+	reg_val = xe_mmio_read32(mmio, vram_reg);
+	temp = REG_FIELD_GET(TEMP_MASK, reg_val);
+	if (!is_temp_valid(hwmon, temp)) {
+		drm_dbg(&hwmon->xe->drm, "vram channel %d unavailable, val 0x%x\n", vram_id,
+			reg_val);
+		return false;
+	}
+
 	/* Create label only for available vram channel */
 	sprintf(hwmon->temp.vram_label[vram_id], "vram_ch_%d", vram_id);
 	return true;
@@ -977,8 +1016,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 		case CHANNEL_VRAM:
 			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
 		case CHANNEL_MCTRL:
+			return !get_mc_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
 		case CHANNEL_PCIE:
-			return hwmon->temp.count ? 0444 : 0;
+			return !get_pcie_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
 			return (is_vram_ch_available(hwmon, channel) &&
 				hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN]) ? 0444 : 0;
@@ -992,8 +1032,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 		case CHANNEL_VRAM:
 			return hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT] ? 0444 : 0;
 		case CHANNEL_MCTRL:
+			return !get_mc_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
 		case CHANNEL_PCIE:
-			return hwmon->temp.count ? 0444 : 0;
+			return !get_pcie_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
 			return (is_vram_ch_available(hwmon, channel) &&
 				hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT]) ? 0444 : 0;
@@ -1011,12 +1052,24 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 	case hwmon_temp_label:
 		switch (channel) {
 		case CHANNEL_PKG:
-		case CHANNEL_VRAM:
-			return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
-								channel)) ? 0444 : 0;
+		case CHANNEL_VRAM: {
+			struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
+			struct xe_reg reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
+			u32 reg_val;
+			u8 temp;
+
+			if (!xe_reg_is_valid(reg))
+				return 0;
+
+			reg_val = xe_mmio_read32(mmio, reg);
+			temp = REG_FIELD_GET(TEMP_MASK, reg_val);
+
+			return is_temp_valid(hwmon, temp) ? 0444 : 0;
+		}
 		case CHANNEL_MCTRL:
+			return !get_mc_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
 		case CHANNEL_PCIE:
-			return hwmon->temp.count ? 0444 : 0;
+			return !get_pcie_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
 			return is_vram_ch_available(hwmon, channel) ? 0444 : 0;
 		default:
-- 
2.25.1

[PATCH 2/3] drm/xe/hwmon: Use VRAM temperature sensor count from thermal config on CRI

[Karthik Poosa]

Read the number of VRAM temperature sensor channels from the second byte
of READ_THERMAL_CONFIG on CRI platforms. Use the reported count to avoid
exposing hwmon attributes for unavailable VRAM temperature sensors, while
retaining the maximum supported channel count on non-CRI platforms.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c     | 35 ++++++++++++++++++++++++++-----
 drivers/gpu/drm/xe/xe_pcode_api.h |  1 +
 2 files changed, 31 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 2c4eba4b8f8f..6e7cb250e628 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -39,7 +39,8 @@ enum xe_hwmon_reg_operation {
 	REG_READ64,
 };
 
-#define MAX_VRAM_CHANNELS      (16)
+/* Maximum number of VRAM channels supported by Xe */
+#define MAX_VRAM_CHANNELS      (80)
 
 enum xe_hwmon_channel {
 	CHANNEL_CARD,
@@ -48,6 +49,7 @@ enum xe_hwmon_channel {
 	CHANNEL_MCTRL,
 	CHANNEL_PCIE,
 	CHANNEL_VRAM_N,
+	/* Compile-time upper bound; actual channel count is hwmon->temp.vram_count */
 	CHANNEL_VRAM_N_MAX = CHANNEL_VRAM_N + MAX_VRAM_CHANNELS - 1,
 	CHANNEL_MAX,
 };
@@ -144,10 +146,12 @@ struct xe_hwmon_thermal_info {
 	};
 	/** @count: no of temperature sensors available for the platform */
 	u8 count;
+	/** @vram_count: number of VRAM temperature sensors available for the platform */
+	u8 vram_count;
 	/** @value: signed value from each sensor */
 	s8 value[U8_MAX];
-	/** @vram_label: vram label names */
-	char vram_label[MAX_VRAM_CHANNELS][MAX_LABEL_SIZE];
+	/** @vram_label: vram label names, dynamically allocated based on vram_count */
+	char (*vram_label)[MAX_LABEL_SIZE];
 };
 
 /**
@@ -271,7 +275,7 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg
 				return BMG_PACKAGE_TEMPERATURE;
 			else if (channel == CHANNEL_VRAM)
 				return BMG_VRAM_TEMPERATURE;
-			else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
+			else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count))
 				return BMG_VRAM_TEMPERATURE_N(channel - CHANNEL_VRAM_N);
 		} else if (xe->info.platform == XE_DG2) {
 			if (channel == CHANNEL_PKG)
@@ -810,6 +814,17 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
 	drm_dbg(&hwmon->xe->drm, "thermal config count 0x%x\n", config);
 	hwmon->temp.count = REG_FIELD_GET(TEMP_MASK, config);
 
+	if (hwmon->xe->info.platform >= XE_CRESCENTISLAND) {
+		hwmon->temp.vram_count = REG_FIELD_GET(VRAM_COUNT_MASK, config);
+		if (hwmon->temp.vram_count > MAX_VRAM_CHANNELS && hwmon->temp.vram_count) {
+			drm_warn(&hwmon->xe->drm, "VRAM channel count %d exceeds max %d, clamping\n",
+				 hwmon->temp.vram_count, MAX_VRAM_CHANNELS);
+			hwmon->temp.vram_count = MAX_VRAM_CHANNELS;
+		}
+	} else {
+		hwmon->temp.vram_count = 16; /* For older platforms, max is 16 VRAM channels */
+	}
+
 	return ret;
 }
 
@@ -988,6 +1003,9 @@ static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
 	u32 reg_val;
 	u8 temp;
 
+	if (vram_id >= hwmon->temp.vram_count)
+		return false;
+
 	vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
 	if (!xe_reg_is_valid(vram_reg))
 		return false;
@@ -1516,7 +1534,7 @@ static int xe_hwmon_read_label(struct device *dev,
 			*str = "mctrl";
 		else if (channel == CHANNEL_PCIE)
 			*str = "pcie";
-		else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
+		else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count))
 			*str = hwmon->temp.vram_label[channel - CHANNEL_VRAM_N];
 		return 0;
 	case hwmon_power:
@@ -1645,6 +1663,13 @@ int xe_hwmon_register(struct xe_device *xe)
 
 	xe_hwmon_get_preregistration_info(hwmon);
 
+	hwmon->temp.vram_label = devm_kcalloc(dev, hwmon->temp.vram_count,
+					      MAX_LABEL_SIZE, GFP_KERNEL);
+	if (!hwmon->temp.vram_label) {
+		xe->hwmon = NULL;
+		return -ENOMEM;
+	}
+
 	drm_dbg(&xe->drm, "Register xe hwmon interface\n");
 
 	/*  hwmon_dev points to device hwmon<i> */
diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
index 94575c476e3d..e1079eff72c6 100644
--- a/drivers/gpu/drm/xe/xe_pcode_api.h
+++ b/drivers/gpu/drm/xe/xe_pcode_api.h
@@ -57,6 +57,7 @@
 #define   PCODE_THERMAL_INFO			0x25
 #define     READ_THERMAL_LIMITS			0x0
 #define     READ_THERMAL_CONFIG			0x1
+#define       VRAM_COUNT_MASK			REG_GENMASK(15, 8)
 #define     READ_THERMAL_DATA			0x2
 #define       PCIE_SENSOR_GROUP_ID		0x2
 #define       PCIE_SENSOR_MASK			REG_GENMASK(31, 16)
-- 
2.25.1

[PATCH 3/3] drm/xe/hwmon: Correct group selection for memory controller temperature

[Karthik Poosa]

Read all the necessary groups when reading memory controller
temperature in get_mc_temp().

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Fixes: 3a0cb885e111 ("drm/xe/hwmon: Expose memory controller temperature")
---
 drivers/gpu/drm/xe/xe_hwmon.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 6e7cb250e628..286f43320ce0 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -844,7 +844,7 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 	int ret, i, count = 0;
 	s32 average = 0;
 
-	for (i = 0; i < DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32)); i++) {
+	for (i = 0; i < DIV_ROUND_UP(hwmon->temp.count, sizeof(u32)); i++) {
 		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
 				    (dword + i), NULL);
 		if (ret)
-- 
2.25.1

[PATCH 0/3] drm/xe/hwmon: Update hwmon thermal mailbox handling

[Karthik Poosa]

This series adds CRI-specific temperature sensor handling to the Xe
hwmon implementation.
 
CRI platforms may report unavailable temperature sensors and support
a variable number of VRAM temperature channels depending on platform
configuration. This series adds the required sensor presence checks and
uses platform-reported thermal configuration data to expose only valid
temperature-related hwmon attributes.
 
The series also corrects the telemetry group selection used for memory
controller temperature reporting.

Karthik Poosa (3):
  drm/xe/hwmon: Detect unavailable temperature sensors
  drm/xe/hwmon: Use VRAM temperature sensor count from thermal config on
    CRI
  drm/xe/hwmon: Correct group selection for memory controller
    temperature

 drivers/gpu/drm/xe/xe_hwmon.c     | 116 +++++++++++++++++++++++++-----
 drivers/gpu/drm/xe/xe_pcode_api.h |   1 +
 2 files changed, 98 insertions(+), 19 deletions(-)

-- 
2.25.1

[PATCH 1/3] drm/xe/hwmon: Detect unavailable temperature sensors

[Karthik Poosa]

Add is_temp_valid() to validate sensor presence.
A temperature reading of 0xFF on CRI platforms indicates that the
corresponding sensor is not present and should be treated as unavailable.

Use this check from xe_hwmon_temp_is_visible() callback so that attributes
for unavailable sensors are not exposed during hwmon device registration.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 79 +++++++++++++++++++++++++++++------
 1 file changed, 66 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 5284cab6703d..2c4eba4b8f8f 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -813,12 +813,21 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
 	return ret;
 }
 
+static inline bool is_temp_valid(const struct xe_hwmon *hwmon, u8 value)
+{
+	/* Value of 0xFF indicates unavailable sensor for platforms from CRI. */
+	if (hwmon->xe->info.platform >= XE_CRESCENTISLAND)
+		return value != U8_MAX;
+	else
+		return value != 0;
+}
+
 static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
 	u32 *dword = (u32 *)hwmon->temp.value;
+	int ret, i, count = 0;
 	s32 average = 0;
-	int ret, i;
 
 	for (i = 0; i < DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32)); i++) {
 		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
@@ -828,11 +837,25 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 		drm_dbg(&hwmon->xe->drm, "thermal data for group %d val 0x%x\n", i, dword[i]);
 	}
 
-	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++)
-		average += hwmon->temp.value[i];
+	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++) {
+		if (is_temp_valid(hwmon, hwmon->temp.value[i])) {
+			average += hwmon->temp.value[i];
+			count++;
+		} else {
+			drm_dbg(&hwmon->xe->drm, "mc temp sensor %d not available, val 0x%x\n",
+				i, hwmon->temp.value[i]);
+		}
+	}
+
+	if (!count) {
+		drm_warn(&hwmon->xe->drm, "no memory temp sensors available!\n");
+		return -ENXIO;
+	}
+
+	average /= count;
+	if (val)
+		*val = average * MILLIDEGREE_PER_DEGREE;
 
-	average /= (hwmon->temp.count - TEMP_INDEX_MCTRL - 1);
-	*val = average * MILLIDEGREE_PER_DEGREE;
 	return 0;
 }
 
@@ -852,7 +875,13 @@ static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
 		data = REG_FIELD_GET(PCIE_SENSOR_MASK, data);
 
 	data = REG_FIELD_GET(TEMP_MASK, data);
-	*val = (s8)data * MILLIDEGREE_PER_DEGREE;
+	if (!is_temp_valid(hwmon, data)) {
+		drm_warn(&hwmon->xe->drm, "pcie temp sensor not available, val 0x%x\n", data);
+		return -ENXIO;
+	}
+
+	if (val)
+		*val = (s8)data * MILLIDEGREE_PER_DEGREE;
 
 	return 0;
 }
@@ -956,11 +985,21 @@ static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
 	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
 	int vram_id = channel - CHANNEL_VRAM_N;
 	struct xe_reg vram_reg;
+	u32 reg_val;
+	u8 temp;
 
 	vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
-	if (!xe_reg_is_valid(vram_reg) || !xe_mmio_read32(mmio, vram_reg))
+	if (!xe_reg_is_valid(vram_reg))
 		return false;
 
+	reg_val = xe_mmio_read32(mmio, vram_reg);
+	temp = REG_FIELD_GET(TEMP_MASK, reg_val);
+	if (!is_temp_valid(hwmon, temp)) {
+		drm_dbg(&hwmon->xe->drm, "vram channel %d unavailable, val 0x%x\n", vram_id,
+			reg_val);
+		return false;
+	}
+
 	/* Create label only for available vram channel */
 	sprintf(hwmon->temp.vram_label[vram_id], "vram_ch_%d", vram_id);
 	return true;
@@ -977,8 +1016,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 		case CHANNEL_VRAM:
 			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
 		case CHANNEL_MCTRL:
+			return !get_mc_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
 		case CHANNEL_PCIE:
-			return hwmon->temp.count ? 0444 : 0;
+			return !get_pcie_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
 			return (is_vram_ch_available(hwmon, channel) &&
 				hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN]) ? 0444 : 0;
@@ -992,8 +1032,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 		case CHANNEL_VRAM:
 			return hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT] ? 0444 : 0;
 		case CHANNEL_MCTRL:
+			return !get_mc_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
 		case CHANNEL_PCIE:
-			return hwmon->temp.count ? 0444 : 0;
+			return !get_pcie_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
 			return (is_vram_ch_available(hwmon, channel) &&
 				hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT]) ? 0444 : 0;
@@ -1011,12 +1052,24 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 	case hwmon_temp_label:
 		switch (channel) {
 		case CHANNEL_PKG:
-		case CHANNEL_VRAM:
-			return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
-								channel)) ? 0444 : 0;
+		case CHANNEL_VRAM: {
+			struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
+			struct xe_reg reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
+			u32 reg_val;
+			u8 temp;
+
+			if (!xe_reg_is_valid(reg))
+				return 0;
+
+			reg_val = xe_mmio_read32(mmio, reg);
+			temp = REG_FIELD_GET(TEMP_MASK, reg_val);
+
+			return is_temp_valid(hwmon, temp) ? 0444 : 0;
+		}
 		case CHANNEL_MCTRL:
+			return !get_mc_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
 		case CHANNEL_PCIE:
-			return hwmon->temp.count ? 0444 : 0;
+			return !get_pcie_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
 			return is_vram_ch_available(hwmon, channel) ? 0444 : 0;
 		default:
-- 
2.25.1

[PATCH 2/3] drm/xe/hwmon: Use VRAM temperature sensor count from thermal config on CRI

[Karthik Poosa]

Read the number of VRAM temperature sensor channels from the second byte
of READ_THERMAL_CONFIG on CRI platforms. Use the reported count to avoid
exposing hwmon attributes for unavailable VRAM temperature sensors, while
retaining the maximum supported channel count on non-CRI platforms.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c     | 35 ++++++++++++++++++++++++++-----
 drivers/gpu/drm/xe/xe_pcode_api.h |  1 +
 2 files changed, 31 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 2c4eba4b8f8f..6e7cb250e628 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -39,7 +39,8 @@ enum xe_hwmon_reg_operation {
 	REG_READ64,
 };
 
-#define MAX_VRAM_CHANNELS      (16)
+/* Maximum number of VRAM channels supported by Xe */
+#define MAX_VRAM_CHANNELS      (80)
 
 enum xe_hwmon_channel {
 	CHANNEL_CARD,
@@ -48,6 +49,7 @@ enum xe_hwmon_channel {
 	CHANNEL_MCTRL,
 	CHANNEL_PCIE,
 	CHANNEL_VRAM_N,
+	/* Compile-time upper bound; actual channel count is hwmon->temp.vram_count */
 	CHANNEL_VRAM_N_MAX = CHANNEL_VRAM_N + MAX_VRAM_CHANNELS - 1,
 	CHANNEL_MAX,
 };
@@ -144,10 +146,12 @@ struct xe_hwmon_thermal_info {
 	};
 	/** @count: no of temperature sensors available for the platform */
 	u8 count;
+	/** @vram_count: number of VRAM temperature sensors available for the platform */
+	u8 vram_count;
 	/** @value: signed value from each sensor */
 	s8 value[U8_MAX];
-	/** @vram_label: vram label names */
-	char vram_label[MAX_VRAM_CHANNELS][MAX_LABEL_SIZE];
+	/** @vram_label: vram label names, dynamically allocated based on vram_count */
+	char (*vram_label)[MAX_LABEL_SIZE];
 };
 
 /**
@@ -271,7 +275,7 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg
 				return BMG_PACKAGE_TEMPERATURE;
 			else if (channel == CHANNEL_VRAM)
 				return BMG_VRAM_TEMPERATURE;
-			else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
+			else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count))
 				return BMG_VRAM_TEMPERATURE_N(channel - CHANNEL_VRAM_N);
 		} else if (xe->info.platform == XE_DG2) {
 			if (channel == CHANNEL_PKG)
@@ -810,6 +814,17 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
 	drm_dbg(&hwmon->xe->drm, "thermal config count 0x%x\n", config);
 	hwmon->temp.count = REG_FIELD_GET(TEMP_MASK, config);
 
+	if (hwmon->xe->info.platform >= XE_CRESCENTISLAND) {
+		hwmon->temp.vram_count = REG_FIELD_GET(VRAM_COUNT_MASK, config);
+		if (hwmon->temp.vram_count > MAX_VRAM_CHANNELS && hwmon->temp.vram_count) {
+			drm_warn(&hwmon->xe->drm, "VRAM channel count %d exceeds max %d, clamping\n",
+				 hwmon->temp.vram_count, MAX_VRAM_CHANNELS);
+			hwmon->temp.vram_count = MAX_VRAM_CHANNELS;
+		}
+	} else {
+		hwmon->temp.vram_count = 16; /* For older platforms, max is 16 VRAM channels */
+	}
+
 	return ret;
 }
 
@@ -988,6 +1003,9 @@ static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
 	u32 reg_val;
 	u8 temp;
 
+	if (vram_id >= hwmon->temp.vram_count)
+		return false;
+
 	vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
 	if (!xe_reg_is_valid(vram_reg))
 		return false;
@@ -1516,7 +1534,7 @@ static int xe_hwmon_read_label(struct device *dev,
 			*str = "mctrl";
 		else if (channel == CHANNEL_PCIE)
 			*str = "pcie";
-		else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
+		else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count))
 			*str = hwmon->temp.vram_label[channel - CHANNEL_VRAM_N];
 		return 0;
 	case hwmon_power:
@@ -1645,6 +1663,13 @@ int xe_hwmon_register(struct xe_device *xe)
 
 	xe_hwmon_get_preregistration_info(hwmon);
 
+	hwmon->temp.vram_label = devm_kcalloc(dev, hwmon->temp.vram_count,
+					      MAX_LABEL_SIZE, GFP_KERNEL);
+	if (!hwmon->temp.vram_label) {
+		xe->hwmon = NULL;
+		return -ENOMEM;
+	}
+
 	drm_dbg(&xe->drm, "Register xe hwmon interface\n");
 
 	/*  hwmon_dev points to device hwmon<i> */
diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
index 94575c476e3d..e1079eff72c6 100644
--- a/drivers/gpu/drm/xe/xe_pcode_api.h
+++ b/drivers/gpu/drm/xe/xe_pcode_api.h
@@ -57,6 +57,7 @@
 #define   PCODE_THERMAL_INFO			0x25
 #define     READ_THERMAL_LIMITS			0x0
 #define     READ_THERMAL_CONFIG			0x1
+#define       VRAM_COUNT_MASK			REG_GENMASK(15, 8)
 #define     READ_THERMAL_DATA			0x2
 #define       PCIE_SENSOR_GROUP_ID		0x2
 #define       PCIE_SENSOR_MASK			REG_GENMASK(31, 16)
-- 
2.25.1

[PATCH 3/3] drm/xe/hwmon: Correct group selection for memory controller temperature

[Karthik Poosa]

Read all the necessary groups when reading memory controller
temperature in get_mc_temp().

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Fixes: 3a0cb885e111 ("drm/xe/hwmon: Expose memory controller temperature")
---
 drivers/gpu/drm/xe/xe_hwmon.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 6e7cb250e628..286f43320ce0 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -844,7 +844,7 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 	int ret, i, count = 0;
 	s32 average = 0;
 
-	for (i = 0; i < DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32)); i++) {
+	for (i = 0; i < DIV_ROUND_UP(hwmon->temp.count, sizeof(u32)); i++) {
 		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
 				    (dword + i), NULL);
 		if (ret)
-- 
2.25.1

Re: [PATCH 3/3] drm/xe/hwmon: Correct group selection for memory controller temperature

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Out-of-bounds write of 1 byte into `hwmon->temp.value` when reading thermal data from pcode if the sensor count exceeds 252.
--

--- Patch [3]: [PATCH 3/3] drm/xe/hwmon: Correct group selection for memory controller temperature ---
commit d6bd40537c53d76ef6df15e33458ad0d982f56b1
Author: Karthik Poosa <karthik.poosa@intel.com>

drm/xe/hwmon: Correct group selection for memory controller temperature
    
This patch corrects the memory controller temperature group selection by
updating get_mc_temp() to read all necessary groups based on the actual
sensor count rather than a hardcoded maximum.

> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c

[ ... ]

> @@ -820,7 +820,7 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>  	int ret, i, count = 0;
>  	s32 average = 0;
>  
> -	for (i = 0; i < DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32)); i++) {
> +	for (i = 0; i < DIV_ROUND_UP(hwmon->temp.count, sizeof(u32)); i++) {

[Severity: Medium]
Could this lead to an out-of-bounds write into hwmon->temp.value if the
hardware returns a sensor count greater than 252?

If hwmon->temp.count is between 253 and 255, the DIV_ROUND_UP calculation
evaluates to 64. The loop will execute 64 times, reading 4 bytes per
iteration, resulting in 256 bytes being written to the dword pointer.

Since dword points to hwmon->temp.value, which is sized at 255 bytes, this
will write past the end of the array by 1 byte.

>  		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
>  				    (dword + i), NULL);
>  		if (ret)

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824184137.2164727-1-karthik.poosa@intel.com?part=3

Re: [PATCH 2/3] drm/xe/hwmon: Use VRAM temperature sensor count from thermal config on CRI

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Regression / Missing Initialization of vram_count disables MMIO sensors
- [Medium] Incomplete Implementation / Unexposed Hardware Monitoring Channels
- [Medium] Dead Code / Unreachable Feature for XE_CRESCENTISLAND (CRI) platforms
--

--- Patch [2]: [PATCH 2/3] drm/xe/hwmon: Use VRAM temperature sensor count from thermal config on CRI ---
commit dad00759fd95979bfa227e2bf51f1aad6c7133a4
Author: Karthik Poosa <karthik.poosa@intel.com>
Subject: drm/xe/hwmon: Use VRAM temperature sensor count from thermal config on CRI

This patch dynamically reads the number of VRAM temperature channels on
Crescent Island platforms. It increases the maximum channel count and uses
the pcode thermal config to determine available sensors.

> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index c15312b0858ca..8c8a519711230 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -39,7 +39,8 @@ enum xe_hwmon_reg_operation {
>  	REG_READ64,
>  };
>  
> -#define MAX_VRAM_CHANNELS      (16)
> +/* Maximum number of VRAM channels supported by Xe */
> +#define MAX_VRAM_CHANNELS      (80)

[Severity: Medium]
Will the hwmon subsystem actually expose these additional channels?

Looking at the hwmon_info array in xe_hwmon.c, it is statically defined
with exactly 21 temperature items, ending with a NULL terminator.
Because the hwmon core stops iterating at the terminator, sensors past
vram_ch_16 won't be queried or exported to sysfs, making this increase
to 80 ineffective.

[ ... ]

> @@ -786,6 +790,17 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>  	drm_dbg(&hwmon->xe->drm, "thermal config count 0x%x\n", config);
>  	hwmon->temp.count = REG_FIELD_GET(TEMP_MASK, config);
>  
> +	if (hwmon->xe->info.platform >= XE_CRESCENTISLAND) {
> +		hwmon->temp.vram_count = REG_FIELD_GET(VRAM_COUNT_MASK, config);

[Severity: Medium]
Are the parsed VRAM channels accessible on Crescent Island platforms?

When is_vram_ch_available() runs, it calls xe_hwmon_get_reg() to get the
temperature register. However, xe_hwmon_get_reg() does not currently have
a branch for XE_CRESCENTISLAND in the REG_TEMP switch case.

Because it falls through and returns XE_REG(0), xe_reg_is_valid() will
fail in is_vram_ch_available(), making these newly parsed sensors
unreachable for CRI platforms.

> +		if (hwmon->temp.vram_count > MAX_VRAM_CHANNELS && hwmon->temp.vram_count) {
> +			drm_warn(&hwmon->xe->drm, "VRAM channel count %d exceeds max %d, clamping\n",
> +				 hwmon->temp.vram_count, MAX_VRAM_CHANNELS);
> +			hwmon->temp.vram_count = MAX_VRAM_CHANNELS;
> +		}
> +	} else {
> +		hwmon->temp.vram_count = 16; /* For older platforms, max is 16 VRAM channels */
> +	}
> +
>  	return ret;
>  }

[ ... ]

> @@ -964,6 +979,9 @@ static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
>  	u32 reg_val;
>  	u8 temp;
>  
> +	if (vram_id >= hwmon->temp.vram_count)
> +		return false;

[Severity: High]
Does this new check rely on pcode succeeding for older platforms?

If xe_hwmon_pcode_read_thermal_info() returns early due to a pcode mailbox
error when reading READ_THERMAL_LIMITS or READ_THERMAL_CONFIG, or is skipped
entirely, hwmon->temp.vram_count will remain 0.

Because of this check, an early return would unconditionally disable all
MMIO-based VRAM temperature sensors on platforms like BMG, losing existing
functionality. Previously, these sensors relied on a static maximum and
were completely decoupled from pcode initialization success.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824184137.2164727-1-karthik.poosa@intel.com?part=2

Re: [PATCH 2/3] drm/xe/hwmon: Use VRAM temperature sensor count from thermal config on CRI

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:

New issues:
- [High] VRAM temperature sensors are silently lost on platforms where the thermal mailbox read fails or is unsupported.
- [High] The dynamic VRAM temperature sensor count feature for CRI is completely non-functional due to missing static attribute definitions and register mappings.

Pre-existing issues:
- [Medium] The hardware monitoring device is registered directly from the DRM subsystem rather than using an auxiliary device driver.
--

--- Patch [2]: [PATCH 2/3] drm/xe/hwmon: Use VRAM temperature sensor count from thermal config on CRI ---
commit ef0f46c26d79ec5ef4b877579a9d69bdbc93ae6c
Author: Karthik Poosa <karthik.poosa@intel.com>
Subject: drm/xe/hwmon: Use VRAM temperature sensor count from thermal config on CRI

This patch reads the number of VRAM temperature sensor channels from the
second byte of READ_THERMAL_CONFIG on CRI platforms. It uses this reported
count to cap the exposed hwmon attributes for VRAM temperature sensors,
while retaining the maximum supported channel count for non-CRI platforms.

> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index c15312b0858ca..8c8a519711230 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c

[ ... ]

> @@ -786,6 +790,17 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>  	drm_dbg(&hwmon->xe->drm, "thermal config count 0x%x\n", config);
>  	hwmon->temp.count = REG_FIELD_GET(TEMP_MASK, config);
>  
> +	if (hwmon->xe->info.platform >= XE_CRESCENTISLAND) {
> +		hwmon->temp.vram_count = REG_FIELD_GET(VRAM_COUNT_MASK, config);
> +		if (hwmon->temp.vram_count > MAX_VRAM_CHANNELS && hwmon->temp.vram_count) {
> +			drm_warn(&hwmon->xe->drm, "VRAM channel count %d exceeds max %d, clamping\n",
> +				 hwmon->temp.vram_count, MAX_VRAM_CHANNELS);
> +			hwmon->temp.vram_count = MAX_VRAM_CHANNELS;
> +		}

[Severity: High]
Can the extra sensors on CRI platforms actually be exposed to sysfs?

The HWMON_CHANNEL_INFO(temp, ...) static attribute array doesn't appear
to be expanded in this patch. Since the static array caps the maximum
channels visible to sysfs, won't the hwmon core stop querying early
regardless of the dynamic vram_count value?

Also, looking at xe_hwmon_get_reg(), there doesn't seem to be a branch 
for XE_CRESCENTISLAND under the REG_TEMP case. Will is_vram_ch_available()
receive an invalid register and fail for all VRAM sensors on CRI?

> +	} else {
> +		hwmon->temp.vram_count = 16; /* For older platforms, max is 16 VRAM channels */
> +	}
> +
>  	return ret;
>  }

[Severity: High]
If xe_pcode_read() fails earlier in xe_hwmon_pcode_read_thermal_info(), the
function returns early. Does this leave hwmon->temp.vram_count uninitialized 
at 0 instead of setting the fallback value of 16?

> @@ -964,6 +979,9 @@ static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
>  	u32 reg_val;
>  	u8 temp;
>  
> +	if (vram_id >= hwmon->temp.vram_count)
> +		return false;
> +

[Severity: High]
If vram_count was left at 0 due to an early return during the pcode read,
this bounds check will unconditionally return false. 

Does this mean a transient pcode error permanently disables all VRAM
temperature monitoring on older platforms, whereas previously the channels
were still exposed?

[ ... ]

> @@ -1621,6 +1639,13 @@ int xe_hwmon_register(struct xe_device *xe)
>  
>  	xe_hwmon_get_preregistration_info(hwmon);
>  
> +	hwmon->temp.vram_label = devm_kcalloc(dev, hwmon->temp.vram_count,
> +					      MAX_LABEL_SIZE, GFP_KERNEL);
> +	if (!hwmon->temp.vram_label) {
> +		xe->hwmon = NULL;
> +		return -ENOMEM;
> +	}
> +
>  	drm_dbg(&xe->drm, "Register xe hwmon interface\n");
>  
>  	/*  hwmon_dev points to device hwmon<i> */

[Severity: Medium]
This is a pre-existing issue, but should this hardware monitoring device be
registered using an auxiliary device driver?

The hwmon subsystem documentation dictates that if the main functionality of
a chip is not hardware monitoring (such as a DRM controller), its hardware
monitoring functionality should be implemented as an auxiliary device driver
in drivers/hwmon/, rather than being registered directly from the DRM
subsystem.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824184137.2164727-1-karthik.poosa@intel.com?part=2

Re: [PATCH 3/3] drm/xe/hwmon: Correct group selection for memory controller temperature

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Buffer overflow in memory controller temperature read loop due to unsafe loop upper bound.
--

--- Patch [3]: [PATCH 3/3] drm/xe/hwmon: Correct group selection for memory controller temperature ---
commit 06143d547f9d92b56105a4e1bd787aaee0504176
Author: Karthik Poosa <karthik.poosa@intel.com>

drm/xe/hwmon: Correct group selection for memory controller temperature

This commit updates get_mc_temp() to read all necessary groups based on
hwmon->temp.count instead of the TEMP_LIMIT_MAX macro.

> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -820,7 +820,7 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>  	int ret, i, count = 0;
>  	s32 average = 0;
>  
> -	for (i = 0; i < DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32)); i++) {
> +	for (i = 0; i < DIV_ROUND_UP(hwmon->temp.count, sizeof(u32)); i++) {
>  		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
>  				    (dword + i), NULL);

[Severity: High]
If hwmon->temp.count is populated directly from a hardware register field
without validation, could it take values up to 255?

If hwmon->temp.count is between 253 and 255, DIV_ROUND_UP will evaluate to 64.
The loop would execute 64 times, reading 4 bytes per iteration and writing a
total of 256 bytes into the dword array, which aliases hwmon->temp.value.

Since hwmon->temp.value is defined as s8 value[U8_MAX] (exactly 255 bytes),
does this cause a 1-byte out-of-bounds write past the end of the array?

While this overflow might currently land in struct padding due to alignment
requirements of subsequent fields, could it corrupt adjacent data if the
struct layout changes in the future?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824184137.2164727-1-karthik.poosa@intel.com?part=3

Re: [PATCH 1/3] drm/xe/hwmon: Detect unavailable temperature sensors

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Incorrect bitmask in `is_vram_ch_available()` evaluates the wrong bits, improperly hiding valid VRAM sensors.
- [Medium] Incorrect short-circuit logic in `is_visible` causes unconditional hardware polling, leading to permanently hidden attributes on transient errors and excessive `drm_warn` log spam.
--

--- Patch [1]: [PATCH 1/3] drm/xe/hwmon: Detect unavailable temperature sensors ---
commit 0fa4d58443299c1d66e99a6115caeb31a5bd8c21
Author: Karthik Poosa <karthik.poosa@intel.com>

drm/xe/hwmon: Detect unavailable temperature sensors

Add is_temp_valid() to validate sensor presence.
A temperature reading of 0xFF on CRI platforms indicates that the
corresponding sensor is not present and should be treated as unavailable.
Use this check from xe_hwmon_temp_is_visible() callback so that attributes
for unavailable sensors are not exposed during hwmon device registration.

> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index de3f2aeffc3fb..c15312b0858ca 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c

[ ... ]

> @@ -932,11 +961,21 @@ static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
>  	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
>  	int vram_id = channel - CHANNEL_VRAM_N;
>  	struct xe_reg vram_reg;
> +	u32 reg_val;
> +	u8 temp;
>  
>  	vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
> -	if (!xe_reg_is_valid(vram_reg) || !xe_mmio_read32(mmio, vram_reg))
> +	if (!xe_reg_is_valid(vram_reg))
>  		return false;
>  
> +	reg_val = xe_mmio_read32(mmio, vram_reg);
> +	temp = REG_FIELD_GET(TEMP_MASK, reg_val);
> +	if (!is_temp_valid(hwmon, temp)) {

[Severity: High]
Does this code extract the correct bits for CHANNEL_VRAM_N?

For CHANNEL_VRAM_N, the hardware register stores the temperature in bits 30:8
(TEMP_MASK_VRAM_N). However, is_vram_ch_available() extracts the value using
TEMP_MASK (bits 7:0).

By evaluating unrelated bits against the sentinel value (0 or 0xFF), can this
cause valid VRAM sensors to be improperly hidden if the lower bits happen to
match the sentinel?

> +		drm_dbg(&hwmon->xe->drm, "vram channel %d unavailable, val 0x%x\n", vram_id,
> +			reg_val);
> +		return false;
> +	}
> +
>  	/* Create label only for available vram channel */
>  	sprintf(hwmon->temp.vram_label[vram_id], "vram_ch_%d", vram_id);
>  	return true;

[ ... ]

> @@ -953,8 +992,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  		case CHANNEL_VRAM:
>  			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
>  		case CHANNEL_MCTRL:
> +			return !get_mc_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
>  		case CHANNEL_PCIE:
> -			return hwmon->temp.count ? 0444 : 0;
> +			return !get_pcie_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;

[Severity: Medium]
Does this reversed short-circuit logic cause unconditional hardware polling and
log spam?

Since !get_mc_temp() and !get_pcie_temp() are evaluated before checking
hwmon->temp.count, they will trigger PCODE reads even when the count is 0.

Furthermore, xe_hwmon_temp_is_visible() executes up to 5 times per channel
during hwmon registration. If a sensor is legitimately missing, the new
drm_warn() statements in get_mc_temp() and get_pcie_temp() will repeatedly
spam the kernel log with warnings for expected missing hardware.

Could this early polling also cause valid attributes to be permanently hidden
if a transient PCODE timeout occurs during registration?

>  		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
>  			return (is_vram_ch_available(hwmon, channel) &&
>  				hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN]) ? 0444 : 0;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824184137.2164727-1-karthik.poosa@intel.com?part=1

Re: [PATCH 1/3] drm/xe/hwmon: Detect unavailable temperature sensors

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Incorrect register bitmask `TEMP_MASK` extracts fractional temperature instead of integer, improperly hiding valid VRAM sensors.
- [Medium] Inverted short-circuit evaluation causes unconditional hardware PCODE reads and excessive log spam during hwmon registration.
- [Medium] Threshold limit sysfs attributes are exposed for unavailable sensors due to missing validity checks.
--

--- Patch [1]: [PATCH 1/3] drm/xe/hwmon: Detect unavailable temperature sensors ---
commit de3d36ad17dd257811068fa1f47a4b3779a65fb1
Author: Karthik Poosa <karthik.poosa@intel.com>

drm/xe/hwmon: Detect unavailable temperature sensors

Add is_temp_valid() to validate sensor presence.
A temperature reading of 0xFF on CRI platforms indicates that the
corresponding sensor is not present and should be treated as unavailable.

Use this check from xe_hwmon_temp_is_visible() callback so that attributes
for unavailable sensors are not exposed during hwmon device registration.

> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index de3f2aeffc3fb..c15312b0858ca 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c

[ ... ]

> @@ -804,11 +813,25 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>  		drm_dbg(&hwmon->xe->drm, "thermal data for group %d val 0x%x\n", i, dword[i]);
>  	}
>  
> -	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++)
> -		average += hwmon->temp.value[i];
> +	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++) {
> +		if (is_temp_valid(hwmon, hwmon->temp.value[i])) {
> +			average += hwmon->temp.value[i];
> +			count++;
> +		} else {
> +			drm_dbg(&hwmon->xe->drm, "mc temp sensor %d not available, val 0x%x\n",
> +				i, hwmon->temp.value[i]);
> +		}
> +	}
> +
> +	if (!count) {
> +		drm_warn(&hwmon->xe->drm, "no memory temp sensors available!\n");

[Severity: Medium]
Will this warning be emitted multiple times during device registration?

Because hwmon subsystem core evaluates the is_visible callback multiple times
per channel, and the logic in xe_hwmon_temp_is_visible() evaluates 
get_mc_temp() first, this warning may trigger excessively if the sensor is 
intentionally absent.

> +		return -ENXIO;
> +	}
> +
> +	average /= count;
> +	if (val)
> +		*val = average * MILLIDEGREE_PER_DEGREE;
>  
> -	average /= (hwmon->temp.count - TEMP_INDEX_MCTRL - 1);
> -	*val = average * MILLIDEGREE_PER_DEGREE;
>  	return 0;
>  }

[ ... ]

> @@ -932,11 +961,21 @@ static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
>  	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
>  	int vram_id = channel - CHANNEL_VRAM_N;
>  	struct xe_reg vram_reg;
> +	u32 reg_val;
> +	u8 temp;
>  
>  	vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
> -	if (!xe_reg_is_valid(vram_reg) || !xe_mmio_read32(mmio, vram_reg))
> +	if (!xe_reg_is_valid(vram_reg))
>  		return false;
>  
> +	reg_val = xe_mmio_read32(mmio, vram_reg);
> +	temp = REG_FIELD_GET(TEMP_MASK, reg_val);

[Severity: High]
Does this extract the correct bits for the VRAM channel temperature value?

For CHANNEL_VRAM_N, TEMP_MASK extracts bits 7:0, which may represent the
fractional part of the temperature rather than the integer temperature. 
The integer temperature is typically in bits 31:8 and extracted with
TEMP_MASK_VRAM_N.

If a valid sensor has a temperature with a 0 fractional part (or 0xFF on newer
platforms), could it be falsely detected as missing and hidden?

> +	if (!is_temp_valid(hwmon, temp)) {
> +		drm_dbg(&hwmon->xe->drm, "vram channel %d unavailable, val 0x%x\n", vram_id,
> +			reg_val);
> +		return false;
> +	}
> +
>  	/* Create label only for available vram channel */
>  	sprintf(hwmon->temp.vram_label[vram_id], "vram_ch_%d", vram_id);
>  	return true;
> @@ -953,8 +992,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  		case CHANNEL_VRAM:
>  			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;

[Severity: Medium]
Will this expose threshold limit attributes for unavailable sensors?

The input attribute for CHANNEL_PKG and CHANNEL_VRAM is now correctly hidden
if the sensor returns an unavailable sentinel. However, hwmon_temp_emergency
and hwmon_temp_crit do not seem to check is_temp_valid() for these channels.
Could this lead to userspace seeing emergency/crit attributes for sensors 
that don't actually exist?

>  		case CHANNEL_MCTRL:
> +			return !get_mc_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;

[Severity: Medium]
Does this execute a synchronous hardware read before checking hwmon->temp.count?

Because this uses !get_mc_temp(hwmon, NULL) && hwmon->temp.count,
get_mc_temp() is unconditionally executed first due to left-to-right
evaluation. If temp.count is 0, should the condition short-circuit before
performing the hardware read by placing the temp.count check first?

>  		case CHANNEL_PCIE:
> -			return hwmon->temp.count ? 0444 : 0;
> +			return !get_pcie_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824184137.2164727-1-karthik.poosa@intel.com?part=1

✓ CI.KUnit: success for drm/xe/hwmon: Update hwmon thermal mailbox handling

[Patchwork]

== Series Details ==

Series: drm/xe/hwmon: Update hwmon thermal mailbox handling
URL   : https://patchwork.freedesktop.org/series/172689/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[23:00:32] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:00:37] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:01:09] Starting KUnit Kernel (1/1)...
[23:01:09] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:01:09] ================== guc_buf (11 subtests) ===================
[23:01:09] [PASSED] test_smallest
[23:01:09] [PASSED] test_largest
[23:01:09] [PASSED] test_granular
[23:01:09] [PASSED] test_unique
[23:01:09] [PASSED] test_overlap
[23:01:09] [PASSED] test_reusable
[23:01:09] [PASSED] test_too_big
[23:01:09] [PASSED] test_flush
[23:01:09] [PASSED] test_lookup
[23:01:09] [PASSED] test_data
[23:01:09] [PASSED] test_class
[23:01:09] ===================== [PASSED] guc_buf =====================
[23:01:09] =================== guc_dbm (7 subtests) ===================
[23:01:09] [PASSED] test_empty
[23:01:09] [PASSED] test_default
[23:01:09] ======================== test_size  ========================
[23:01:09] [PASSED] 4
[23:01:09] [PASSED] 8
[23:01:09] [PASSED] 32
[23:01:09] [PASSED] 256
[23:01:09] ==================== [PASSED] test_size ====================
[23:01:09] ======================= test_reuse  ========================
[23:01:09] [PASSED] 4
[23:01:09] [PASSED] 8
[23:01:09] [PASSED] 32
[23:01:09] [PASSED] 256
[23:01:09] =================== [PASSED] test_reuse ====================
[23:01:09] =================== test_range_overlap  ====================
[23:01:09] [PASSED] 4
[23:01:09] [PASSED] 8
[23:01:09] [PASSED] 32
[23:01:09] [PASSED] 256
[23:01:09] =============== [PASSED] test_range_overlap ================
[23:01:09] =================== test_range_compact  ====================
[23:01:09] [PASSED] 4
[23:01:09] [PASSED] 8
[23:01:09] [PASSED] 32
[23:01:09] [PASSED] 256
[23:01:09] =============== [PASSED] test_range_compact ================
[23:01:09] ==================== test_range_spare  =====================
[23:01:09] [PASSED] 4
[23:01:09] [PASSED] 8
[23:01:09] [PASSED] 32
[23:01:09] [PASSED] 256
[23:01:09] ================ [PASSED] test_range_spare =================
[23:01:09] ===================== [PASSED] guc_dbm =====================
[23:01:09] =================== guc_idm (6 subtests) ===================
[23:01:09] [PASSED] bad_init
[23:01:09] [PASSED] no_init
[23:01:09] [PASSED] init_fini
[23:01:09] [PASSED] check_used
[23:01:09] [PASSED] check_quota
[23:01:09] [PASSED] check_all
[23:01:09] ===================== [PASSED] guc_idm =====================
[23:01:09] =============== guc_klv_helpers (9 subtests) ===============
[23:01:09] [PASSED] test_count
[23:01:09] [PASSED] test_encode_u32
[23:01:09] [PASSED] test_encode_u64
[23:01:09] [PASSED] test_encode_string
[23:01:09] [PASSED] test_encode_object_raw
[23:01:09] [PASSED] test_encode_object_klv
[23:01:09] [PASSED] test_encode_object_nested
[23:01:09] [PASSED] test_encode_object_basic
[23:01:09] [PASSED] test_print
[23:01:09] ================= [PASSED] guc_klv_helpers =================
[23:01:09] =================== xe_log (4 subtests) ====================
[23:01:09] [PASSED] demo_cper
[23:01:09] [PASSED] demo_dmesg
[23:01:09] ======================= test_dmesg  ========================
[23:01:09] [PASSED] test_fatal
[23:01:09] [PASSED] test_fatal_tile
[23:01:09] [PASSED] test_fatal_gt
[23:01:09] [PASSED] test_fatal_comp
[23:01:09] [PASSED] test_fatal_comp_tile
[23:01:09] [PASSED] test_fatal_comp_gt
[23:01:09] [PASSED] test_fatal_all
[23:01:09] [PASSED] test_recoverable
[23:01:09] [PASSED] test_recoverable_tile
[23:01:09] [PASSED] test_recoverable_gt
[23:01:09] [PASSED] test_recoverable_comp
[23:01:09] [PASSED] test_recoverable_comp_tile
[23:01:09] [PASSED] test_recoverable_comp_gt
[23:01:09] [PASSED] test_recoverable_all
[23:01:09] [PASSED] test_info
[23:01:09] [PASSED] test_info_tile
[23:01:09] [PASSED] test_info_gt
[23:01:09] [PASSED] test_info_err
[23:01:09] [PASSED] test_info_comp
[23:01:09] [PASSED] test_info_comp_tile
[23:01:09] [PASSED] test_info_comp_gt
[23:01:09] [PASSED] test_info_all
[23:01:09] [PASSED] test_hw_fatal
[23:01:09] [PASSED] test_hw_recoverable
[23:01:09] [PASSED] test_hw_corrected
[23:01:09] [PASSED] test_hw_informational
[23:01:09] =================== [PASSED] test_dmesg ====================
[23:01:09] ====================== test_invalid  =======================
[23:01:09] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[23:01:09] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[23:01:09] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[23:01:09] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[23:01:09] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[23:01:09] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[23:01:09] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[23:01:09] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[23:01:09] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[23:01:09] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[23:01:09] ================== [SKIPPED] test_invalid ==================
[23:01:09] ===================== [PASSED] xe_log ======================
[23:01:09] ================== no_relay (3 subtests) ===================
[23:01:09] [PASSED] xe_drops_guc2pf_if_not_ready
[23:01:09] [PASSED] xe_drops_guc2vf_if_not_ready
[23:01:09] [PASSED] xe_rejects_send_if_not_ready
[23:01:09] ==================== [PASSED] no_relay =====================
[23:01:09] ================== pf_relay (14 subtests) ==================
[23:01:09] [PASSED] pf_rejects_guc2pf_too_short
[23:01:09] [PASSED] pf_rejects_guc2pf_too_long
[23:01:09] [PASSED] pf_rejects_guc2pf_no_payload
[23:01:09] [PASSED] pf_fails_no_payload
[23:01:09] [PASSED] pf_fails_bad_origin
[23:01:09] [PASSED] pf_fails_bad_type
[23:01:09] [PASSED] pf_txn_reports_error
[23:01:09] [PASSED] pf_txn_sends_pf2guc
[23:01:09] [PASSED] pf_sends_pf2guc
[23:01:09] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[23:01:09] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[23:01:09] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[23:01:09] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[23:01:09] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[23:01:09] ==================== [PASSED] pf_relay =====================
[23:01:09] ================== vf_relay (3 subtests) ===================
[23:01:09] [PASSED] vf_rejects_guc2vf_too_short
[23:01:09] [PASSED] vf_rejects_guc2vf_too_long
[23:01:09] [PASSED] vf_rejects_guc2vf_no_payload
[23:01:09] ==================== [PASSED] vf_relay =====================
[23:01:09] ================ pf_gt_config (9 subtests) =================
[23:01:09] [PASSED] fair_contexts_1vf
[23:01:09] [PASSED] fair_doorbells_1vf
[23:01:09] [PASSED] fair_ggtt_1vf
[23:01:09] ====================== fair_vram_1vf  ======================
[23:01:09] [PASSED] 3.50 GiB
[23:01:09] [PASSED] 11.5 GiB
[23:01:09] [PASSED] 15.5 GiB
[23:01:09] [PASSED] 31.5 GiB
[23:01:09] [PASSED] 63.5 GiB
[23:01:09] [PASSED] 1.91 GiB
[23:01:09] ================== [PASSED] fair_vram_1vf ==================
[23:01:09] ================ fair_vram_1vf_admin_only  =================
[23:01:09] [PASSED] 3.50 GiB
[23:01:09] [PASSED] 11.5 GiB
[23:01:09] [PASSED] 15.5 GiB
[23:01:09] [PASSED] 31.5 GiB
[23:01:09] [PASSED] 63.5 GiB
[23:01:09] [PASSED] 1.91 GiB
[23:01:09] ============ [PASSED] fair_vram_1vf_admin_only =============
[23:01:09] ====================== fair_contexts  ======================
[23:01:09] [PASSED] 1 VF
[23:01:09] [PASSED] 2 VFs
[23:01:09] [PASSED] 3 VFs
[23:01:09] [PASSED] 4 VFs
[23:01:09] [PASSED] 5 VFs
[23:01:09] [PASSED] 6 VFs
[23:01:09] [PASSED] 7 VFs
[23:01:09] [PASSED] 8 VFs
[23:01:09] [PASSED] 9 VFs
[23:01:09] [PASSED] 10 VFs
[23:01:09] [PASSED] 11 VFs
[23:01:09] [PASSED] 12 VFs
[23:01:09] [PASSED] 13 VFs
[23:01:09] [PASSED] 14 VFs
[23:01:09] [PASSED] 15 VFs
[23:01:09] [PASSED] 16 VFs
[23:01:09] [PASSED] 17 VFs
[23:01:09] [PASSED] 18 VFs
[23:01:09] [PASSED] 19 VFs
[23:01:09] [PASSED] 20 VFs
[23:01:09] [PASSED] 21 VFs
[23:01:09] [PASSED] 22 VFs
[23:01:09] [PASSED] 23 VFs
[23:01:09] [PASSED] 24 VFs
[23:01:09] [PASSED] 25 VFs
[23:01:09] [PASSED] 26 VFs
[23:01:09] [PASSED] 27 VFs
[23:01:09] [PASSED] 28 VFs
[23:01:09] [PASSED] 29 VFs
[23:01:09] [PASSED] 30 VFs
[23:01:09] [PASSED] 31 VFs
[23:01:09] [PASSED] 32 VFs
[23:01:09] [PASSED] 33 VFs
[23:01:09] [PASSED] 34 VFs
[23:01:09] [PASSED] 35 VFs
[23:01:09] [PASSED] 36 VFs
[23:01:09] [PASSED] 37 VFs
[23:01:09] [PASSED] 38 VFs
[23:01:09] [PASSED] 39 VFs
[23:01:09] [PASSED] 40 VFs
[23:01:09] [PASSED] 41 VFs
[23:01:09] [PASSED] 42 VFs
[23:01:09] [PASSED] 43 VFs
[23:01:09] [PASSED] 44 VFs
[23:01:09] [PASSED] 45 VFs
[23:01:09] [PASSED] 46 VFs
[23:01:09] [PASSED] 47 VFs
[23:01:09] [PASSED] 48 VFs
[23:01:09] [PASSED] 49 VFs
[23:01:09] [PASSED] 50 VFs
[23:01:09] [PASSED] 51 VFs
[23:01:09] [PASSED] 52 VFs
[23:01:09] [PASSED] 53 VFs
[23:01:09] [PASSED] 54 VFs
[23:01:09] [PASSED] 55 VFs
[23:01:09] [PASSED] 56 VFs
[23:01:09] [PASSED] 57 VFs
[23:01:09] [PASSED] 58 VFs
[23:01:09] [PASSED] 59 VFs
[23:01:09] [PASSED] 60 VFs
[23:01:09] [PASSED] 61 VFs
[23:01:09] [PASSED] 62 VFs
[23:01:09] [PASSED] 63 VFs
[23:01:09] ================== [PASSED] fair_contexts ==================
[23:01:09] ===================== fair_doorbells  ======================
[23:01:09] [PASSED] 1 VF
[23:01:09] [PASSED] 2 VFs
[23:01:09] [PASSED] 3 VFs
[23:01:09] [PASSED] 4 VFs
[23:01:09] [PASSED] 5 VFs
[23:01:09] [PASSED] 6 VFs
[23:01:09] [PASSED] 7 VFs
[23:01:09] [PASSED] 8 VFs
[23:01:09] [PASSED] 9 VFs
[23:01:09] [PASSED] 10 VFs
[23:01:09] [PASSED] 11 VFs
[23:01:09] [PASSED] 12 VFs
[23:01:09] [PASSED] 13 VFs
[23:01:09] [PASSED] 14 VFs
[23:01:09] [PASSED] 15 VFs
[23:01:09] [PASSED] 16 VFs
[23:01:09] [PASSED] 17 VFs
[23:01:09] [PASSED] 18 VFs
[23:01:09] [PASSED] 19 VFs
[23:01:09] [PASSED] 20 VFs
[23:01:09] [PASSED] 21 VFs
[23:01:09] [PASSED] 22 VFs
[23:01:09] [PASSED] 23 VFs
[23:01:09] [PASSED] 24 VFs
[23:01:09] [PASSED] 25 VFs
[23:01:09] [PASSED] 26 VFs
[23:01:09] [PASSED] 27 VFs
[23:01:09] [PASSED] 28 VFs
[23:01:09] [PASSED] 29 VFs
[23:01:09] [PASSED] 30 VFs
[23:01:09] [PASSED] 31 VFs
[23:01:09] [PASSED] 32 VFs
[23:01:09] [PASSED] 33 VFs
[23:01:09] [PASSED] 34 VFs
[23:01:09] [PASSED] 35 VFs
[23:01:09] [PASSED] 36 VFs
[23:01:09] [PASSED] 37 VFs
[23:01:09] [PASSED] 38 VFs
[23:01:09] [PASSED] 39 VFs
[23:01:09] [PASSED] 40 VFs
[23:01:09] [PASSED] 41 VFs
[23:01:09] [PASSED] 42 VFs
[23:01:09] [PASSED] 43 VFs
[23:01:09] [PASSED] 44 VFs
[23:01:09] [PASSED] 45 VFs
[23:01:09] [PASSED] 46 VFs
[23:01:09] [PASSED] 47 VFs
[23:01:09] [PASSED] 48 VFs
[23:01:09] [PASSED] 49 VFs
[23:01:09] [PASSED] 50 VFs
[23:01:09] [PASSED] 51 VFs
[23:01:09] [PASSED] 52 VFs
[23:01:09] [PASSED] 53 VFs
[23:01:09] [PASSED] 54 VFs
[23:01:09] [PASSED] 55 VFs
[23:01:09] [PASSED] 56 VFs
[23:01:09] [PASSED] 57 VFs
[23:01:09] [PASSED] 58 VFs
[23:01:09] [PASSED] 59 VFs
[23:01:09] [PASSED] 60 VFs
[23:01:09] [PASSED] 61 VFs
[23:01:09] [PASSED] 62 VFs
[23:01:09] [PASSED] 63 VFs
[23:01:09] ================= [PASSED] fair_doorbells ==================
[23:01:09] ======================== fair_ggtt  ========================
[23:01:09] [PASSED] 1 VF
[23:01:09] [PASSED] 2 VFs
[23:01:09] [PASSED] 3 VFs
[23:01:09] [PASSED] 4 VFs
[23:01:09] [PASSED] 5 VFs
[23:01:09] [PASSED] 6 VFs
[23:01:09] [PASSED] 7 VFs
[23:01:09] [PASSED] 8 VFs
[23:01:09] [PASSED] 9 VFs
[23:01:09] [PASSED] 10 VFs
[23:01:09] [PASSED] 11 VFs
[23:01:09] [PASSED] 12 VFs
[23:01:09] [PASSED] 13 VFs
[23:01:09] [PASSED] 14 VFs
[23:01:09] [PASSED] 15 VFs
[23:01:09] [PASSED] 16 VFs
[23:01:09] [PASSED] 17 VFs
[23:01:09] [PASSED] 18 VFs
[23:01:09] [PASSED] 19 VFs
[23:01:09] [PASSED] 20 VFs
[23:01:09] [PASSED] 21 VFs
[23:01:09] [PASSED] 22 VFs
[23:01:09] [PASSED] 23 VFs
[23:01:09] [PASSED] 24 VFs
[23:01:09] [PASSED] 25 VFs
[23:01:09] [PASSED] 26 VFs
[23:01:09] [PASSED] 27 VFs
[23:01:09] [PASSED] 28 VFs
[23:01:09] [PASSED] 29 VFs
[23:01:09] [PASSED] 30 VFs
[23:01:09] [PASSED] 31 VFs
[23:01:09] [PASSED] 32 VFs
[23:01:09] [PASSED] 33 VFs
[23:01:09] [PASSED] 34 VFs
[23:01:09] [PASSED] 35 VFs
[23:01:09] [PASSED] 36 VFs
[23:01:09] [PASSED] 37 VFs
[23:01:09] [PASSED] 38 VFs
[23:01:09] [PASSED] 39 VFs
[23:01:09] [PASSED] 40 VFs
[23:01:09] [PASSED] 41 VFs
[23:01:09] [PASSED] 42 VFs
[23:01:09] [PASSED] 43 VFs
[23:01:09] [PASSED] 44 VFs
[23:01:09] [PASSED] 45 VFs
[23:01:09] [PASSED] 46 VFs
[23:01:09] [PASSED] 47 VFs
[23:01:09] [PASSED] 48 VFs
[23:01:09] [PASSED] 49 VFs
[23:01:09] [PASSED] 50 VFs
[23:01:09] [PASSED] 51 VFs
[23:01:09] [PASSED] 52 VFs
[23:01:09] [PASSED] 53 VFs
[23:01:09] [PASSED] 54 VFs
[23:01:09] [PASSED] 55 VFs
[23:01:09] [PASSED] 56 VFs
[23:01:09] [PASSED] 57 VFs
[23:01:09] [PASSED] 58 VFs
[23:01:09] [PASSED] 59 VFs
[23:01:09] [PASSED] 60 VFs
[23:01:09] [PASSED] 61 VFs
[23:01:09] [PASSED] 62 VFs
[23:01:09] [PASSED] 63 VFs
[23:01:09] ==================== [PASSED] fair_ggtt ====================
[23:01:09] ======================== fair_vram  ========================
[23:01:09] [PASSED] 1 VF
[23:01:09] [PASSED] 2 VFs
[23:01:09] [PASSED] 3 VFs
[23:01:09] [PASSED] 4 VFs
[23:01:09] [PASSED] 5 VFs
[23:01:09] [PASSED] 6 VFs
[23:01:09] [PASSED] 7 VFs
[23:01:09] [PASSED] 8 VFs
[23:01:09] [PASSED] 9 VFs
[23:01:09] [PASSED] 10 VFs
[23:01:09] [PASSED] 11 VFs
[23:01:09] [PASSED] 12 VFs
[23:01:09] [PASSED] 13 VFs
[23:01:09] [PASSED] 14 VFs
[23:01:09] [PASSED] 15 VFs
[23:01:09] [PASSED] 16 VFs
[23:01:09] [PASSED] 17 VFs
[23:01:09] [PASSED] 18 VFs
[23:01:09] [PASSED] 19 VFs
[23:01:09] [PASSED] 20 VFs
[23:01:09] [PASSED] 21 VFs
[23:01:09] [PASSED] 22 VFs
[23:01:09] [PASSED] 23 VFs
[23:01:09] [PASSED] 24 VFs
[23:01:09] [PASSED] 25 VFs
[23:01:09] [PASSED] 26 VFs
[23:01:09] [PASSED] 27 VFs
[23:01:09] [PASSED] 28 VFs
[23:01:09] [PASSED] 29 VFs
[23:01:09] [PASSED] 30 VFs
[23:01:09] [PASSED] 31 VFs
[23:01:09] [PASSED] 32 VFs
[23:01:09] [PASSED] 33 VFs
[23:01:09] [PASSED] 34 VFs
[23:01:09] [PASSED] 35 VFs
[23:01:09] [PASSED] 36 VFs
[23:01:09] [PASSED] 37 VFs
[23:01:09] [PASSED] 38 VFs
[23:01:09] [PASSED] 39 VFs
[23:01:09] [PASSED] 40 VFs
[23:01:09] [PASSED] 41 VFs
[23:01:09] [PASSED] 42 VFs
[23:01:09] [PASSED] 43 VFs
[23:01:09] [PASSED] 44 VFs
[23:01:09] [PASSED] 45 VFs
[23:01:09] [PASSED] 46 VFs
[23:01:09] [PASSED] 47 VFs
[23:01:09] [PASSED] 48 VFs
[23:01:09] [PASSED] 49 VFs
[23:01:09] [PASSED] 50 VFs
[23:01:09] [PASSED] 51 VFs
[23:01:09] [PASSED] 52 VFs
[23:01:09] [PASSED] 53 VFs
[23:01:09] [PASSED] 54 VFs
[23:01:09] [PASSED] 55 VFs
[23:01:09] [PASSED] 56 VFs
[23:01:09] [PASSED] 57 VFs
[23:01:09] [PASSED] 58 VFs
[23:01:09] [PASSED] 59 VFs
[23:01:09] [PASSED] 60 VFs
[23:01:09] [PASSED] 61 VFs
[23:01:09] [PASSED] 62 VFs
[23:01:09] [PASSED] 63 VFs
[23:01:09] ==================== [PASSED] fair_vram ====================
[23:01:09] ================== [PASSED] pf_gt_config ===================
[23:01:09] ===================== lmtt (1 subtest) =====================
[23:01:09] ======================== test_ops  =========================
[23:01:09] [PASSED] 2-level
[23:01:09] [PASSED] multi-level
[23:01:09] ==================== [PASSED] test_ops =====================
[23:01:09] ====================== [PASSED] lmtt =======================
[23:01:09] ================= sriov_packet (1 subtest) =================
[23:01:09] [PASSED] test_descriptor_init
[23:01:09] ================== [PASSED] sriov_packet ===================
[23:01:09] ================= pf_service (11 subtests) =================
[23:01:09] [PASSED] pf_negotiate_any
[23:01:09] [PASSED] pf_negotiate_base_match
[23:01:09] [PASSED] pf_negotiate_base_newer
[23:01:09] [PASSED] pf_negotiate_base_next
[23:01:09] [SKIPPED] pf_negotiate_base_older (no older minor)
[23:01:09] [PASSED] pf_negotiate_base_prev
[23:01:09] [PASSED] pf_negotiate_latest_match
[23:01:09] [PASSED] pf_negotiate_latest_newer
[23:01:09] [PASSED] pf_negotiate_latest_next
[23:01:09] [SKIPPED] pf_negotiate_latest_older (no older minor)
[23:01:09] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[23:01:09] =================== [PASSED] pf_service ====================
[23:01:09] ================= xe_guc_g2g (2 subtests) ==================
[23:01:09] ============== xe_live_guc_g2g_kunit_default  ==============
[23:01:09] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[23:01:09] ============== xe_live_guc_g2g_kunit_allmem  ===============
[23:01:09] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[23:01:09] =================== [SKIPPED] xe_guc_g2g ===================
[23:01:09] =================== xe_mocs (2 subtests) ===================
[23:01:09] ================ xe_live_mocs_kernel_kunit  ================
[23:01:09] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[23:01:09] ================ xe_live_mocs_reset_kunit  =================
[23:01:09] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[23:01:09] ==================== [SKIPPED] xe_mocs =====================
[23:01:09] ================= xe_migrate (2 subtests) ==================
[23:01:09] ================= xe_migrate_sanity_kunit  =================
[23:01:09] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[23:01:09] ================== xe_validate_ccs_kunit  ==================
[23:01:09] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[23:01:09] =================== [SKIPPED] xe_migrate ===================
[23:01:09] ================== xe_dma_buf (1 subtest) ==================
[23:01:09] ==================== xe_dma_buf_kunit  =====================
[23:01:09] ================ [SKIPPED] xe_dma_buf_kunit ================
[23:01:09] =================== [SKIPPED] xe_dma_buf ===================
[23:01:09] ================= xe_bo_shrink (1 subtest) =================
[23:01:09] =================== xe_bo_shrink_kunit  ====================
[23:01:09] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[23:01:09] ================== [SKIPPED] xe_bo_shrink ==================
[23:01:09] ==================== xe_bo (2 subtests) ====================
[23:01:09] ================== xe_ccs_migrate_kunit  ===================
[23:01:09] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[23:01:09] ==================== xe_bo_evict_kunit  ====================
[23:01:09] =============== [SKIPPED] xe_bo_evict_kunit ================
[23:01:09] ===================== [SKIPPED] xe_bo ======================
[23:01:09] =================== xe_any (9 subtests) ====================
[23:01:09] [PASSED] test_to_xe
[23:01:09] [PASSED] test_to_dev
[23:01:09] [PASSED] test_to_pdev
[23:01:09] [PASSED] test_to_drm
[23:01:09] [PASSED] test_if_pdev
[23:01:09] [PASSED] test_if_xe
[23:01:09] [PASSED] test_if_tile
[23:01:09] [PASSED] test_if_gt
[23:01:09] [PASSED] test_to_id
[23:01:09] ===================== [PASSED] xe_any ======================
[23:01:09] ==================== args (13 subtests) ====================
[23:01:09] [PASSED] count_args_test
[23:01:09] [PASSED] call_args_example
[23:01:09] [PASSED] call_args_test
[23:01:09] [PASSED] drop_first_arg_example
[23:01:09] [PASSED] drop_first_arg_test
[23:01:09] [PASSED] first_arg_example
[23:01:09] [PASSED] first_arg_test
[23:01:09] [PASSED] last_arg_example
[23:01:09] [PASSED] last_arg_test
[23:01:09] [PASSED] pick_arg_example
[23:01:09] [PASSED] if_args_example
[23:01:09] [PASSED] if_args_test
[23:01:09] [PASSED] sep_comma_example
[23:01:09] ====================== [PASSED] args =======================
[23:01:09] =================== xe_pci (3 subtests) ====================
[23:01:09] ==================== check_graphics_ip  ====================
[23:01:09] [PASSED] 12.00 Xe_LP
[23:01:09] [PASSED] 12.10 Xe_LP+
[23:01:09] [PASSED] 12.55 Xe_HPG
[23:01:09] [PASSED] 12.60 Xe_HPC
[23:01:09] [PASSED] 12.70 Xe_LPG
[23:01:09] [PASSED] 12.71 Xe_LPG
[23:01:09] [PASSED] 12.74 Xe_LPG+
[23:01:09] [PASSED] 20.01 Xe2_HPG
[23:01:09] [PASSED] 20.02 Xe2_HPG
[23:01:09] [PASSED] 20.04 Xe2_LPG
[23:01:09] [PASSED] 30.00 Xe3_LPG
[23:01:09] [PASSED] 30.01 Xe3_LPG
[23:01:09] [PASSED] 30.03 Xe3_LPG
[23:01:09] [PASSED] 30.04 Xe3_LPG
[23:01:09] [PASSED] 30.05 Xe3_LPG
[23:01:09] [PASSED] 35.10 Xe3p_LPG
[23:01:09] [PASSED] 35.11 Xe3p_XPC
[23:01:09] ================ [PASSED] check_graphics_ip ================
[23:01:09] ===================== check_media_ip  ======================
[23:01:09] [PASSED] 12.00 Xe_M
[23:01:09] [PASSED] 12.55 Xe_HPM
[23:01:09] [PASSED] 13.00 Xe_LPM+
[23:01:09] [PASSED] 13.01 Xe2_HPM
[23:01:09] [PASSED] 20.00 Xe2_LPM
[23:01:09] [PASSED] 30.00 Xe3_LPM
[23:01:09] [PASSED] 30.02 Xe3_LPM
[23:01:09] [PASSED] 35.00 Xe3p_LPM
[23:01:09] [PASSED] 35.03 Xe3p_HPM
[23:01:09] ================= [PASSED] check_media_ip ==================
[23:01:09] =================== check_platform_desc  ===================
[23:01:09] [PASSED] 0x9A60 (TIGERLAKE)
[23:01:09] [PASSED] 0x9A68 (TIGERLAKE)
[23:01:09] [PASSED] 0x9A70 (TIGERLAKE)
[23:01:09] [PASSED] 0x9A40 (TIGERLAKE)
[23:01:09] [PASSED] 0x9A49 (TIGERLAKE)
[23:01:09] [PASSED] 0x9A59 (TIGERLAKE)
[23:01:09] [PASSED] 0x9A78 (TIGERLAKE)
[23:01:09] [PASSED] 0x9AC0 (TIGERLAKE)
[23:01:09] [PASSED] 0x9AC9 (TIGERLAKE)
[23:01:09] [PASSED] 0x9AD9 (TIGERLAKE)
[23:01:09] [PASSED] 0x9AF8 (TIGERLAKE)
[23:01:09] [PASSED] 0x4C80 (ROCKETLAKE)
[23:01:09] [PASSED] 0x4C8A (ROCKETLAKE)
[23:01:09] [PASSED] 0x4C8B (ROCKETLAKE)
[23:01:09] [PASSED] 0x4C8C (ROCKETLAKE)
[23:01:09] [PASSED] 0x4C90 (ROCKETLAKE)
[23:01:09] [PASSED] 0x4C9A (ROCKETLAKE)
[23:01:09] [PASSED] 0x4680 (ALDERLAKE_S)
[23:01:09] [PASSED] 0x4682 (ALDERLAKE_S)
[23:01:09] [PASSED] 0x4688 (ALDERLAKE_S)
[23:01:09] [PASSED] 0x468A (ALDERLAKE_S)
[23:01:09] [PASSED] 0x468B (ALDERLAKE_S)
[23:01:09] [PASSED] 0x4690 (ALDERLAKE_S)
[23:01:09] [PASSED] 0x4692 (ALDERLAKE_S)
[23:01:09] [PASSED] 0x4693 (ALDERLAKE_S)
[23:01:09] [PASSED] 0x46A0 (ALDERLAKE_P)
[23:01:09] [PASSED] 0x46A1 (ALDERLAKE_P)
[23:01:09] [PASSED] 0x46A2 (ALDERLAKE_P)
[23:01:09] [PASSED] 0x46A3 (ALDERLAKE_P)
[23:01:09] [PASSED] 0x46A6 (ALDERLAKE_P)
[23:01:09] [PASSED] 0x46A8 (ALDERLAKE_P)
[23:01:09] [PASSED] 0x46AA (ALDERLAKE_P)
[23:01:09] [PASSED] 0x462A (ALDERLAKE_P)
[23:01:09] [PASSED] 0x4626 (ALDERLAKE_P)
[23:01:09] [PASSED] 0x4628 (ALDERLAKE_P)
[23:01:09] [PASSED] 0x46B0 (ALDERLAKE_P)
[23:01:09] [PASSED] 0x46B1 (ALDERLAKE_P)
[23:01:09] [PASSED] 0x46B2 (ALDERLAKE_P)
[23:01:09] [PASSED] 0x46B3 (ALDERLAKE_P)
[23:01:09] [PASSED] 0x46C0 (ALDERLAKE_P)
[23:01:09] [PASSED] 0x46C1 (ALDERLAKE_P)
[23:01:09] [PASSED] 0x46C2 (ALDERLAKE_P)
[23:01:09] [PASSED] 0x46C3 (ALDERLAKE_P)
[23:01:09] [PASSED] 0x46D0 (ALDERLAKE_N)
[23:01:09] [PASSED] 0x46D1 (ALDERLAKE_N)
[23:01:09] [PASSED] 0x46D2 (ALDERLAKE_N)
[23:01:09] [PASSED] 0x46D3 (ALDERLAKE_N)
[23:01:09] [PASSED] 0x46D4 (ALDERLAKE_N)
[23:01:09] [PASSED] 0xA721 (ALDERLAKE_P)
[23:01:09] [PASSED] 0xA7A1 (ALDERLAKE_P)
[23:01:09] [PASSED] 0xA7A9 (ALDERLAKE_P)
[23:01:09] [PASSED] 0xA7AC (ALDERLAKE_P)
[23:01:09] [PASSED] 0xA7AD (ALDERLAKE_P)
[23:01:09] [PASSED] 0xA720 (ALDERLAKE_P)
[23:01:09] [PASSED] 0xA7A0 (ALDERLAKE_P)
[23:01:09] [PASSED] 0xA7A8 (ALDERLAKE_P)
[23:01:09] [PASSED] 0xA7AA (ALDERLAKE_P)
[23:01:09] [PASSED] 0xA7AB (ALDERLAKE_P)
[23:01:09] [PASSED] 0xA780 (ALDERLAKE_S)
[23:01:09] [PASSED] 0xA781 (ALDERLAKE_S)
[23:01:09] [PASSED] 0xA782 (ALDERLAKE_S)
[23:01:09] [PASSED] 0xA783 (ALDERLAKE_S)
[23:01:09] [PASSED] 0xA788 (ALDERLAKE_S)
[23:01:09] [PASSED] 0xA789 (ALDERLAKE_S)
[23:01:09] [PASSED] 0xA78A (ALDERLAKE_S)
[23:01:09] [PASSED] 0xA78B (ALDERLAKE_S)
[23:01:09] [PASSED] 0x4905 (DG1)
[23:01:09] [PASSED] 0x4906 (DG1)
[23:01:09] [PASSED] 0x4907 (DG1)
[23:01:09] [PASSED] 0x4908 (DG1)
[23:01:09] [PASSED] 0x4909 (DG1)
[23:01:09] [PASSED] 0x56C0 (DG2)
[23:01:09] [PASSED] 0x56C2 (DG2)
[23:01:09] [PASSED] 0x56C1 (DG2)
[23:01:09] [PASSED] 0x7D51 (METEORLAKE)
[23:01:09] [PASSED] 0x7DD1 (METEORLAKE)
[23:01:09] [PASSED] 0x7D41 (METEORLAKE)
[23:01:09] [PASSED] 0x7D67 (METEORLAKE)
[23:01:09] [PASSED] 0xB640 (METEORLAKE)
[23:01:09] [PASSED] 0x56A0 (DG2)
[23:01:09] [PASSED] 0x56A1 (DG2)
[23:01:09] [PASSED] 0x56A2 (DG2)
[23:01:09] [PASSED] 0x56BE (DG2)
[23:01:09] [PASSED] 0x56BF (DG2)
[23:01:09] [PASSED] 0x5690 (DG2)
[23:01:09] [PASSED] 0x5691 (DG2)
[23:01:09] [PASSED] 0x5692 (DG2)
[23:01:09] [PASSED] 0x56A5 (DG2)
[23:01:09] [PASSED] 0x56A6 (DG2)
[23:01:09] [PASSED] 0x56B0 (DG2)
[23:01:09] [PASSED] 0x56B1 (DG2)
[23:01:09] [PASSED] 0x56BA (DG2)
[23:01:09] [PASSED] 0x56BB (DG2)
[23:01:09] [PASSED] 0x56BC (DG2)
[23:01:09] [PASSED] 0x56BD (DG2)
[23:01:09] [PASSED] 0x5693 (DG2)
[23:01:09] [PASSED] 0x5694 (DG2)
[23:01:09] [PASSED] 0x5695 (DG2)
[23:01:09] [PASSED] 0x56A3 (DG2)
[23:01:09] [PASSED] 0x56A4 (DG2)
[23:01:09] [PASSED] 0x56B2 (DG2)
[23:01:09] [PASSED] 0x56B3 (DG2)
[23:01:09] [PASSED] 0x5696 (DG2)
[23:01:09] [PASSED] 0x5697 (DG2)
[23:01:09] [PASSED] 0xB69 (PVC)
[23:01:09] [PASSED] 0xB6E (PVC)
[23:01:09] [PASSED] 0xBD4 (PVC)
[23:01:09] [PASSED] 0xBD5 (PVC)
[23:01:09] [PASSED] 0xBD6 (PVC)
[23:01:09] [PASSED] 0xBD7 (PVC)
[23:01:09] [PASSED] 0xBD8 (PVC)
[23:01:09] [PASSED] 0xBD9 (PVC)
[23:01:09] [PASSED] 0xBDA (PVC)
[23:01:09] [PASSED] 0xBDB (PVC)
[23:01:09] [PASSED] 0xBE0 (PVC)
[23:01:09] [PASSED] 0xBE1 (PVC)
[23:01:09] [PASSED] 0xBE5 (PVC)
[23:01:09] [PASSED] 0x7D40 (METEORLAKE)
[23:01:09] [PASSED] 0x7D45 (METEORLAKE)
[23:01:09] [PASSED] 0x7D55 (METEORLAKE)
[23:01:09] [PASSED] 0x7D60 (METEORLAKE)
[23:01:09] [PASSED] 0x7DD5 (METEORLAKE)
[23:01:09] [PASSED] 0x6420 (LUNARLAKE)
[23:01:09] [PASSED] 0x64A0 (LUNARLAKE)
[23:01:09] [PASSED] 0x64B0 (LUNARLAKE)
[23:01:09] [PASSED] 0xE202 (BATTLEMAGE)
[23:01:09] [PASSED] 0xE209 (BATTLEMAGE)
[23:01:09] [PASSED] 0xE20B (BATTLEMAGE)
[23:01:09] [PASSED] 0xE20C (BATTLEMAGE)
[23:01:09] [PASSED] 0xE20D (BATTLEMAGE)
[23:01:09] [PASSED] 0xE210 (BATTLEMAGE)
[23:01:09] [PASSED] 0xE211 (BATTLEMAGE)
[23:01:09] [PASSED] 0xE212 (BATTLEMAGE)
[23:01:09] [PASSED] 0xE216 (BATTLEMAGE)
[23:01:09] [PASSED] 0xE220 (BATTLEMAGE)
[23:01:09] [PASSED] 0xE221 (BATTLEMAGE)
[23:01:09] [PASSED] 0xE222 (BATTLEMAGE)
[23:01:09] [PASSED] 0xE223 (BATTLEMAGE)
[23:01:09] [PASSED] 0xB080 (PANTHERLAKE)
[23:01:09] [PASSED] 0xB081 (PANTHERLAKE)
[23:01:09] [PASSED] 0xB082 (PANTHERLAKE)
[23:01:09] [PASSED] 0xB083 (PANTHERLAKE)
[23:01:09] [PASSED] 0xB084 (PANTHERLAKE)
[23:01:09] [PASSED] 0xB085 (PANTHERLAKE)
[23:01:09] [PASSED] 0xB086 (PANTHERLAKE)
[23:01:09] [PASSED] 0xB087 (PANTHERLAKE)
[23:01:09] [PASSED] 0xB08F (PANTHERLAKE)
[23:01:09] [PASSED] 0xB090 (PANTHERLAKE)
[23:01:09] [PASSED] 0xB0A0 (PANTHERLAKE)
[23:01:09] [PASSED] 0xB0B0 (PANTHERLAKE)
[23:01:09] [PASSED] 0xFD80 (PANTHERLAKE)
[23:01:09] [PASSED] 0xFD81 (PANTHERLAKE)
[23:01:09] [PASSED] 0xD740 (NOVALAKE_S)
[23:01:09] [PASSED] 0xD741 (NOVALAKE_S)
[23:01:09] [PASSED] 0xD742 (NOVALAKE_S)
[23:01:09] [PASSED] 0xD743 (NOVALAKE_S)
[23:01:09] [PASSED] 0xD745 (NOVALAKE_S)
[23:01:09] [PASSED] 0xD74A (NOVALAKE_S)
[23:01:09] [PASSED] 0xD74B (NOVALAKE_S)
[23:01:09] [PASSED] 0x674C (CRESCENTISLAND)
[23:01:09] [PASSED] 0x674D (CRESCENTISLAND)
[23:01:09] [PASSED] 0x674E (CRESCENTISLAND)
[23:01:09] [PASSED] 0x674F (CRESCENTISLAND)
[23:01:09] [PASSED] 0x6750 (CRESCENTISLAND)
[23:01:09] [PASSED] 0xD750 (NOVALAKE_P)
[23:01:09] [PASSED] 0xD751 (NOVALAKE_P)
[23:01:09] [PASSED] 0xD752 (NOVALAKE_P)
[23:01:09] [PASSED] 0xD753 (NOVALAKE_P)
[23:01:09] [PASSED] 0xD754 (NOVALAKE_P)
[23:01:09] [PASSED] 0xD755 (NOVALAKE_P)
[23:01:09] [PASSED] 0xD756 (NOVALAKE_P)
[23:01:09] [PASSED] 0xD757 (NOVALAKE_P)
[23:01:09] [PASSED] 0xD75F (NOVALAKE_P)
[23:01:09] =============== [PASSED] check_platform_desc ===============
[23:01:09] ===================== [PASSED] xe_pci ======================
[23:01:09] ============= xe_rtp_tables_test (5 subtests) ==============
[23:01:09] ================== xe_rtp_table_gt_test  ===================
[23:01:09] [PASSED] gt_was/14011060649
[23:01:09] [PASSED] gt_was/14011059788
[23:01:09] [PASSED] gt_was/14015795083
[23:01:09] [PASSED] gt_was/16021867713
[23:01:09] [PASSED] gt_was/14019449301
[23:01:09] [PASSED] gt_was/16028005424
[23:01:09] [PASSED] gt_was/14026578760
[23:01:09] [PASSED] gt_was/1409420604
[23:01:09] [PASSED] gt_was/1408615072
[23:01:09] [PASSED] gt_was/22010523718
[23:01:09] [PASSED] gt_was/14011006942
[23:01:09] [PASSED] gt_was/14014830051
[23:01:09] [PASSED] gt_was/18018781329
[23:01:09] [PASSED] gt_was/1509235366
[23:01:09] [PASSED] gt_was/18018781329
[23:01:09] [PASSED] gt_was/16016694945
[23:01:09] [PASSED] gt_was/14018575942
[23:01:09] [PASSED] gt_was/22016670082
[23:01:09] [PASSED] gt_was/22016670082
[23:01:09] [PASSED] gt_was/14017421178
[23:01:09] [PASSED] gt_was/16025250150
[23:01:09] [PASSED] gt_was/14021871409
[23:01:09] [PASSED] gt_was/16021865536
[23:01:09] [PASSED] gt_was/14021486841
[23:01:09] [PASSED] gt_was/14025160223
[23:01:09] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[23:01:09] [PASSED] gt_was/14025635424
[23:01:09] [PASSED] gt_was/16028005424
[23:01:09] ============== [PASSED] xe_rtp_table_gt_test ===============
[23:01:09] ================== xe_rtp_table_gt_test  ===================
[23:01:09] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[23:01:09] [PASSED] gt_tunings/Tuning: 32B Access Enable
[23:01:09] [PASSED] gt_tunings/Tuning: L3 cache
[23:01:09] [PASSED] gt_tunings/Tuning: L3 cache - media
[23:01:09] [PASSED] gt_tunings/Tuning: Compression Overfetch
[23:01:09] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[23:01:09] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[23:01:09] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[23:01:09] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[23:01:09] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[23:01:09] [PASSED] gt_tunings/Tuning: Stateless compression control
[23:01:09] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[23:01:09] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[23:01:09] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[23:01:09] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[23:01:09] ============== [PASSED] xe_rtp_table_gt_test ===============
[23:01:09] ================== xe_rtp_table_oob_test  ==================
[23:01:09] [PASSED] oob_was/1607983814
[23:01:09] [PASSED] oob_was/16010904313
[23:01:09] [PASSED] oob_was/18022495364
[23:01:09] [PASSED] oob_was/22012773006
[23:01:09] [PASSED] oob_was/14014475959
[23:01:09] [PASSED] oob_was/22011391025
[23:01:09] [PASSED] oob_was/22012727170
[23:01:09] [PASSED] oob_was/22012727685
[23:01:09] [PASSED] oob_was/22016596838
[23:01:09] [PASSED] oob_was/18020744125
[23:01:09] [PASSED] oob_was/1409600907
[23:01:09] [PASSED] oob_was/22014953428
[23:01:09] [PASSED] oob_was/16017236439
[23:01:09] [PASSED] oob_was/14019821291
[23:01:09] [PASSED] oob_was/14015076503
[23:01:09] [PASSED] oob_was/14018913170
[23:01:09] [PASSED] oob_was/14018094691
[23:01:09] [PASSED] oob_was/18024947630
[23:01:09] [PASSED] oob_was/16022287689
[23:01:09] [PASSED] oob_was/13011645652
[23:01:09] [PASSED] oob_was/14022293748
[23:01:09] [PASSED] oob_was/22019794406
[23:01:09] [PASSED] oob_was/22019338487
[23:01:09] [PASSED] oob_was/16023588340
[23:01:09] [PASSED] oob_was/14019789679
[23:01:09] [PASSED] oob_was/14022866841
[23:01:09] [PASSED] oob_was/16021333562
[23:01:09] [PASSED] oob_was/14016712196
[23:01:09] [PASSED] oob_was/14015568240
[23:01:09] [PASSED] oob_was/18013179988
[23:01:09] [PASSED] oob_was/1508761755
[23:01:09] [PASSED] oob_was/16023105232
[23:01:09] [PASSED] oob_was/16026508708
[23:01:09] [PASSED] oob_was/14020001231
[23:01:09] [PASSED] oob_was/16023683509
[23:01:09] [PASSED] oob_was/14025515070
[23:01:09] [PASSED] oob_was/15015404425_disable
[23:01:09] [PASSED] oob_was/16026007364
[23:01:09] [PASSED] oob_was/14020316580
[23:01:09] [PASSED] oob_was/14025883347
[23:01:09] [PASSED] oob_was/16029380221
[23:01:09] [PASSED] oob_was/22022079272
[23:01:09] [PASSED] oob_was/16029897822
[23:01:09] [PASSED] oob_was/14027054324
[23:01:09] ============== [PASSED] xe_rtp_table_oob_test ==============
[23:01:09] ================ xe_rtp_table_dev_oob_test  ================
[23:01:09] [PASSED] device_oob_was/22010954014
[23:01:09] [PASSED] device_oob_was/15015404425
[23:01:09] [PASSED] device_oob_was/22019338487_display
[23:01:09] [PASSED] device_oob_was/14022085890
[23:01:09] [PASSED] device_oob_was/14026539277
[23:01:09] [PASSED] device_oob_was/14026633728
[23:01:09] [PASSED] device_oob_was/14026746987
[23:01:09] [PASSED] device_oob_was/14026779378
[23:01:09] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[23:01:09] ========== xe_rtp_table_missing_upper_bound_test  ==========
[23:01:09] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[23:01:09] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[23:01:09] [PASSED] register_whitelist/1806527549
[23:01:09] [PASSED] register_whitelist/allow_read_ctx_timestamp
[23:01:09] [PASSED] register_whitelist/allow_read_queue_timestamp
[23:01:09] [PASSED] register_whitelist/16014440446
[23:01:09] [PASSED] register_whitelist/16017236439
[23:01:09] [PASSED] register_whitelist/16020183090
[23:01:09] [PASSED] register_whitelist/14024997852
[23:01:09] [PASSED] register_whitelist/14024997852
[23:01:09] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[23:01:09] =============== [PASSED] xe_rtp_tables_test ================
[23:01:09] =================== xe_rtp (3 subtests) ====================
[23:01:09] =================== xe_rtp_rules_tests  ====================
[23:01:09] [PASSED] no
[23:01:09] [PASSED] yes
[23:01:09] [PASSED] no-and-no
[23:01:09] [PASSED] no-and-yes
[23:01:09] [PASSED] yes-and-no
[23:01:09] [PASSED] yes-and-yes
[23:01:09] [PASSED] no-or-no
[23:01:09] [PASSED] no-or-yes
[23:01:09] [PASSED] yes-or-no
[23:01:09] [PASSED] yes-or-yes
[23:01:09] [PASSED] no-yes-or-yes-no
[23:01:09] [PASSED] no-yes-or-yes-yes
[23:01:09] [PASSED] yes-yes-or-no-yes
[23:01:09] [PASSED] yes-yes-or-yes-yes
[23:01:09] [PASSED] no-no-or-yes-or-no
[23:01:09] [PASSED] or
[23:01:09] [PASSED] or-yes
[23:01:09] [PASSED] or-no
[23:01:09] [PASSED] yes-or
[23:01:09] [PASSED] no-or
[23:01:09] [PASSED] no-or-or-yes
[23:01:09] [PASSED] yes-or-or-no
[23:01:09] [PASSED] no-or-or-no
[23:01:09] [PASSED] missing-context-engine-class
[23:01:09] [PASSED] missing-context-engine-class-or-yes
[23:01:09] [PASSED] missing-context-engine-class-or-or-yes
[23:01:09] =============== [PASSED] xe_rtp_rules_tests ================
[23:01:09] =============== xe_rtp_process_to_sr_tests  ================
[23:01:09] [PASSED] coalesce-same-reg
[23:01:09] [PASSED] coalesce-same-reg-literal-and-func
[23:01:09] [PASSED] no-match-no-add
[23:01:09] [PASSED] two-regs-two-entries
[23:01:09] [PASSED] clr-one-set-other
[23:01:09] [PASSED] set-field
[23:01:09] [PASSED] conflict-duplicate
[23:01:09] [PASSED] conflict-not-disjoint
[23:01:09] [PASSED] conflict-not-disjoint-literal-and-func
[23:01:09] [PASSED] conflict-reg-type
[23:01:09] [PASSED] bad-mcr-reg-forced-to-regular
[23:01:09] [PASSED] bad-regular-reg-forced-to-mcr
[23:01:09] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[23:01:09] ================== xe_rtp_process_tests  ===================
[23:01:09] [PASSED] active1
[23:01:09] [PASSED] active2
[23:01:09] [PASSED] active-inactive
[23:01:09] [PASSED] inactive-active
[23:01:09] [PASSED] inactive-active-inactive
[23:01:09] [PASSED] inactive-inactive-inactive
[23:01:09] ============== [PASSED] xe_rtp_process_tests ===============
[23:01:09] ===================== [PASSED] xe_rtp ======================
[23:01:09] ==================== xe_wa (1 subtest) =====================
[23:01:09] ======================== xe_wa_gt  =========================
[23:01:09] [PASSED] TIGERLAKE B0
[23:01:09] [PASSED] DG1 A0
[23:01:09] [PASSED] DG1 B0
[23:01:09] [PASSED] ALDERLAKE_S A0
[23:01:09] [PASSED] ALDERLAKE_S B0
[23:01:09] [PASSED] ALDERLAKE_S C0
[23:01:09] [PASSED] ALDERLAKE_S D0
[23:01:09] [PASSED] ALDERLAKE_P A0
[23:01:09] [PASSED] ALDERLAKE_P B0
[23:01:09] [PASSED] ALDERLAKE_P C0
[23:01:09] [PASSED] ALDERLAKE_S RPLS D0
[23:01:09] [PASSED] ALDERLAKE_P RPLU E0
[23:01:09] [PASSED] DG2 G10 C0
[23:01:09] [PASSED] DG2 G11 B1
[23:01:09] [PASSED] DG2 G12 A1
[23:01:09] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[23:01:09] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[23:01:09] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[23:01:09] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[23:01:09] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[23:01:09] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[23:01:09] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[23:01:09] ==================== [PASSED] xe_wa_gt =====================
[23:01:09] ====================== [PASSED] xe_wa ======================
[23:01:09] ============================================================
[23:01:09] Testing complete. Ran 789 tests: passed: 761, skipped: 28
[23:01:09] Elapsed time: 36.858s total, 4.367s configuring, 31.774s building, 0.686s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[23:01:09] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:01:11] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:01:36] Starting KUnit Kernel (1/1)...
[23:01:36] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:01:36] ============ drm_test_pick_cmdline (2 subtests) ============
[23:01:36] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[23:01:36] =============== drm_test_pick_cmdline_named  ===============
[23:01:36] [PASSED] NTSC
[23:01:36] [PASSED] NTSC-J
[23:01:36] [PASSED] PAL
[23:01:36] [PASSED] PAL-M
[23:01:36] =========== [PASSED] drm_test_pick_cmdline_named ===========
[23:01:36] ============== [PASSED] drm_test_pick_cmdline ==============
[23:01:36] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[23:01:36] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[23:01:36] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[23:01:36] =========== drm_validate_clone_mode (2 subtests) ===========
[23:01:36] ============== drm_test_check_in_clone_mode  ===============
[23:01:36] [PASSED] in_clone_mode
[23:01:36] [PASSED] not_in_clone_mode
[23:01:36] ========== [PASSED] drm_test_check_in_clone_mode ===========
[23:01:36] =============== drm_test_check_valid_clones  ===============
[23:01:36] [PASSED] not_in_clone_mode
[23:01:36] [PASSED] valid_clone
[23:01:36] [PASSED] invalid_clone
[23:01:36] =========== [PASSED] drm_test_check_valid_clones ===========
[23:01:36] ============= [PASSED] drm_validate_clone_mode =============
[23:01:36] ============= drm_validate_modeset (1 subtest) =============
[23:01:36] [PASSED] drm_test_check_connector_changed_modeset
[23:01:36] ============== [PASSED] drm_validate_modeset ===============
[23:01:36] ====== drm_test_bridge_get_current_state (1 subtest) =======
[23:01:36] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[23:01:36] ======== [PASSED] drm_test_bridge_get_current_state ========
[23:01:36] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[23:01:36] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[23:01:36] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[23:01:36] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[23:01:36] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[23:01:36] ============== drm_bridge_alloc (2 subtests) ===============
[23:01:36] [PASSED] drm_test_drm_bridge_alloc_basic
[23:01:36] [PASSED] drm_test_drm_bridge_alloc_get_put
[23:01:36] ================ [PASSED] drm_bridge_alloc =================
[23:01:36] ============= drm_bridge_bus_fmt (5 subtests) ==============
[23:01:36] [PASSED] drm_test_bridge_rgb_yuv_rgb
[23:01:36] [PASSED] drm_test_bridge_must_convert_to_yuv444
[23:01:36] [PASSED] drm_test_bridge_hdmi_auto_rgb
[23:01:36] [PASSED] drm_test_bridge_auto_first
[23:01:36] [PASSED] drm_test_bridge_rgb_yuv_no_path
[23:01:36] =============== [PASSED] drm_bridge_bus_fmt ================
[23:01:36] ============= drm_cmdline_parser (40 subtests) =============
[23:01:36] [PASSED] drm_test_cmdline_force_d_only
[23:01:36] [PASSED] drm_test_cmdline_force_D_only_dvi
[23:01:36] [PASSED] drm_test_cmdline_force_D_only_hdmi
[23:01:36] [PASSED] drm_test_cmdline_force_D_only_not_digital
[23:01:36] [PASSED] drm_test_cmdline_force_e_only
[23:01:36] [PASSED] drm_test_cmdline_res
[23:01:36] [PASSED] drm_test_cmdline_res_vesa
[23:01:36] [PASSED] drm_test_cmdline_res_vesa_rblank
[23:01:36] [PASSED] drm_test_cmdline_res_rblank
[23:01:36] [PASSED] drm_test_cmdline_res_bpp
[23:01:36] [PASSED] drm_test_cmdline_res_refresh
[23:01:36] [PASSED] drm_test_cmdline_res_bpp_refresh
[23:01:36] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[23:01:36] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[23:01:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[23:01:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[23:01:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[23:01:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[23:01:36] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[23:01:36] [PASSED] drm_test_cmdline_res_margins_force_on
[23:01:36] [PASSED] drm_test_cmdline_res_vesa_margins
[23:01:36] [PASSED] drm_test_cmdline_name
[23:01:36] [PASSED] drm_test_cmdline_name_bpp
[23:01:36] [PASSED] drm_test_cmdline_name_option
[23:01:36] [PASSED] drm_test_cmdline_name_bpp_option
[23:01:36] [PASSED] drm_test_cmdline_rotate_0
[23:01:36] [PASSED] drm_test_cmdline_rotate_90
[23:01:36] [PASSED] drm_test_cmdline_rotate_180
[23:01:36] [PASSED] drm_test_cmdline_rotate_270
[23:01:36] [PASSED] drm_test_cmdline_hmirror
[23:01:36] [PASSED] drm_test_cmdline_vmirror
[23:01:36] [PASSED] drm_test_cmdline_margin_options
[23:01:36] [PASSED] drm_test_cmdline_multiple_options
[23:01:36] [PASSED] drm_test_cmdline_bpp_extra_and_option
[23:01:36] [PASSED] drm_test_cmdline_extra_and_option
[23:01:36] [PASSED] drm_test_cmdline_freestanding_options
[23:01:36] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[23:01:36] [PASSED] drm_test_cmdline_panel_orientation
[23:01:36] ================ drm_test_cmdline_invalid  =================
[23:01:36] [PASSED] margin_only
[23:01:36] [PASSED] interlace_only
[23:01:36] [PASSED] res_missing_x
[23:01:36] [PASSED] res_missing_y
[23:01:36] [PASSED] res_bad_y
[23:01:36] [PASSED] res_missing_y_bpp
[23:01:36] [PASSED] res_bad_bpp
[23:01:36] [PASSED] res_bad_refresh
[23:01:36] [PASSED] res_bpp_refresh_force_on_off
[23:01:36] [PASSED] res_invalid_mode
[23:01:36] [PASSED] res_bpp_wrong_place_mode
[23:01:36] [PASSED] name_bpp_refresh
[23:01:36] [PASSED] name_refresh
[23:01:36] [PASSED] name_refresh_wrong_mode
[23:01:36] [PASSED] name_refresh_invalid_mode
[23:01:36] [PASSED] rotate_multiple
[23:01:36] [PASSED] rotate_invalid_val
[23:01:36] [PASSED] rotate_truncated
[23:01:36] [PASSED] invalid_option
[23:01:36] [PASSED] invalid_tv_option
[23:01:36] [PASSED] truncated_tv_option
[23:01:36] ============ [PASSED] drm_test_cmdline_invalid =============
[23:01:36] =============== drm_test_cmdline_tv_options  ===============
[23:01:36] [PASSED] NTSC
[23:01:36] [PASSED] NTSC_443
[23:01:36] [PASSED] NTSC_J
[23:01:36] [PASSED] PAL
[23:01:36] [PASSED] PAL_M
[23:01:36] [PASSED] PAL_N
[23:01:36] [PASSED] SECAM
[23:01:36] [PASSED] MONO_525
[23:01:36] [PASSED] MONO_625
[23:01:36] =========== [PASSED] drm_test_cmdline_tv_options ===========
[23:01:36] =============== [PASSED] drm_cmdline_parser ================
[23:01:36] ========== drmm_connector_hdmi_init (20 subtests) ==========
[23:01:36] [PASSED] drm_test_connector_hdmi_init_valid
[23:01:36] [PASSED] drm_test_connector_hdmi_init_bpc_8
[23:01:36] [PASSED] drm_test_connector_hdmi_init_bpc_10
[23:01:36] [PASSED] drm_test_connector_hdmi_init_bpc_12
[23:01:36] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[23:01:36] [PASSED] drm_test_connector_hdmi_init_bpc_null
[23:01:36] [PASSED] drm_test_connector_hdmi_init_formats_empty
[23:01:36] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[23:01:36] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[23:01:36] [PASSED] supported_formats=0x9 yuv420_allowed=1
[23:01:36] [PASSED] supported_formats=0x9 yuv420_allowed=0
[23:01:36] [PASSED] supported_formats=0x5 yuv420_allowed=1
[23:01:36] [PASSED] supported_formats=0x5 yuv420_allowed=0
[23:01:36] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[23:01:36] [PASSED] drm_test_connector_hdmi_init_null_ddc
[23:01:36] [PASSED] drm_test_connector_hdmi_init_null_product
[23:01:36] [PASSED] drm_test_connector_hdmi_init_null_vendor
[23:01:36] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[23:01:36] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[23:01:36] [PASSED] drm_test_connector_hdmi_init_product_valid
[23:01:36] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[23:01:36] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[23:01:36] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[23:01:36] ========= drm_test_connector_hdmi_init_type_valid  =========
[23:01:36] [PASSED] HDMI-A
[23:01:36] [PASSED] HDMI-B
[23:01:36] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[23:01:36] ======== drm_test_connector_hdmi_init_type_invalid  ========
[23:01:36] [PASSED] Unknown
[23:01:36] [PASSED] VGA
[23:01:36] [PASSED] DVI-I
[23:01:36] [PASSED] DVI-D
[23:01:36] [PASSED] DVI-A
[23:01:36] [PASSED] Composite
[23:01:36] [PASSED] SVIDEO
[23:01:36] [PASSED] LVDS
[23:01:36] [PASSED] Component
[23:01:36] [PASSED] DIN
[23:01:36] [PASSED] DP
[23:01:36] [PASSED] TV
[23:01:36] [PASSED] eDP
[23:01:36] [PASSED] Virtual
[23:01:36] [PASSED] DSI
[23:01:36] [PASSED] DPI
[23:01:36] [PASSED] Writeback
[23:01:36] [PASSED] SPI
[23:01:36] [PASSED] USB
[23:01:36] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[23:01:36] ============ [PASSED] drmm_connector_hdmi_init =============
[23:01:36] ============= drmm_connector_init (3 subtests) =============
[23:01:36] [PASSED] drm_test_drmm_connector_init
[23:01:36] [PASSED] drm_test_drmm_connector_init_null_ddc
[23:01:36] ========= drm_test_drmm_connector_init_type_valid  =========
[23:01:36] [PASSED] Unknown
[23:01:36] [PASSED] VGA
[23:01:36] [PASSED] DVI-I
[23:01:36] [PASSED] DVI-D
[23:01:36] [PASSED] DVI-A
[23:01:36] [PASSED] Composite
[23:01:36] [PASSED] SVIDEO
[23:01:36] [PASSED] LVDS
[23:01:36] [PASSED] Component
[23:01:36] [PASSED] DIN
[23:01:36] [PASSED] DP
[23:01:36] [PASSED] HDMI-A
[23:01:36] [PASSED] HDMI-B
[23:01:36] [PASSED] TV
[23:01:36] [PASSED] eDP
[23:01:36] [PASSED] Virtual
[23:01:36] [PASSED] DSI
[23:01:36] [PASSED] DPI
[23:01:36] [PASSED] Writeback
[23:01:36] [PASSED] SPI
[23:01:36] [PASSED] USB
[23:01:36] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[23:01:36] =============== [PASSED] drmm_connector_init ===============
[23:01:36] ========= drm_connector_dynamic_init (6 subtests) ==========
[23:01:36] [PASSED] drm_test_drm_connector_dynamic_init
[23:01:36] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[23:01:36] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[23:01:36] [PASSED] drm_test_drm_connector_dynamic_init_properties
[23:01:36] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[23:01:36] [PASSED] Unknown
[23:01:36] [PASSED] VGA
[23:01:36] [PASSED] DVI-I
[23:01:36] [PASSED] DVI-D
[23:01:36] [PASSED] DVI-A
[23:01:36] [PASSED] Composite
[23:01:36] [PASSED] SVIDEO
[23:01:36] [PASSED] LVDS
[23:01:36] [PASSED] Component
[23:01:36] [PASSED] DIN
[23:01:36] [PASSED] DP
[23:01:36] [PASSED] HDMI-A
[23:01:36] [PASSED] HDMI-B
[23:01:36] [PASSED] TV
[23:01:36] [PASSED] eDP
[23:01:36] [PASSED] Virtual
[23:01:36] [PASSED] DSI
[23:01:36] [PASSED] DPI
[23:01:36] [PASSED] Writeback
[23:01:36] [PASSED] SPI
[23:01:36] [PASSED] USB
[23:01:36] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[23:01:36] ======== drm_test_drm_connector_dynamic_init_name  =========
[23:01:36] [PASSED] Unknown
[23:01:36] [PASSED] VGA
[23:01:36] [PASSED] DVI-I
[23:01:36] [PASSED] DVI-D
[23:01:36] [PASSED] DVI-A
[23:01:36] [PASSED] Composite
[23:01:36] [PASSED] SVIDEO
[23:01:36] [PASSED] LVDS
[23:01:36] [PASSED] Component
[23:01:36] [PASSED] DIN
[23:01:36] [PASSED] DP
[23:01:36] [PASSED] HDMI-A
[23:01:36] [PASSED] HDMI-B
[23:01:36] [PASSED] TV
[23:01:36] [PASSED] eDP
[23:01:36] [PASSED] Virtual
[23:01:36] [PASSED] DSI
[23:01:36] [PASSED] DPI
[23:01:36] [PASSED] Writeback
[23:01:36] [PASSED] SPI
[23:01:36] [PASSED] USB
[23:01:36] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[23:01:36] =========== [PASSED] drm_connector_dynamic_init ============
[23:01:36] ==== drm_connector_dynamic_register_early (4 subtests) =====
[23:01:36] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[23:01:36] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[23:01:36] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[23:01:36] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[23:01:36] ====== [PASSED] drm_connector_dynamic_register_early =======
[23:01:36] ======= drm_connector_dynamic_register (7 subtests) ========
[23:01:36] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[23:01:36] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[23:01:36] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[23:01:36] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[23:01:36] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[23:01:36] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[23:01:36] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[23:01:36] ========= [PASSED] drm_connector_dynamic_register ==========
[23:01:36] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[23:01:36] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[23:01:36] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[23:01:36] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[23:01:36] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[23:01:36] ========== drm_test_get_tv_mode_from_name_valid  ===========
[23:01:36] [PASSED] NTSC
[23:01:36] [PASSED] NTSC-443
[23:01:36] [PASSED] NTSC-J
[23:01:36] [PASSED] PAL
[23:01:36] [PASSED] PAL-M
[23:01:36] [PASSED] PAL-N
[23:01:36] [PASSED] SECAM
[23:01:36] [PASSED] Mono
[23:01:36] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[23:01:36] [PASSED] drm_test_get_tv_mode_from_name_truncated
[23:01:36] ============ [PASSED] drm_get_tv_mode_from_name ============
[23:01:36] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[23:01:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[23:01:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[23:01:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[23:01:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[23:01:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[23:01:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[23:01:36] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[23:01:36] [PASSED] VIC 96
[23:01:36] [PASSED] VIC 97
[23:01:36] [PASSED] VIC 101
[23:01:36] [PASSED] VIC 102
[23:01:36] [PASSED] VIC 106
[23:01:36] [PASSED] VIC 107
[23:01:36] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[23:01:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[23:01:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[23:01:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[23:01:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[23:01:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[23:01:36] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[23:01:36] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[23:01:36] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[23:01:36] [PASSED] Automatic
[23:01:36] [PASSED] Full
[23:01:36] [PASSED] Limited 16:235
[23:01:36] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[23:01:36] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[23:01:36] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[23:01:36] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[23:01:36] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[23:01:36] [PASSED] RGB
[23:01:36] [PASSED] YUV 4:2:0
[23:01:36] [PASSED] YUV 4:2:2
[23:01:36] [PASSED] YUV 4:4:4
[23:01:36] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[23:01:36] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[23:01:36] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[23:01:36] ============= drm_damage_helper (21 subtests) ==============
[23:01:36] [PASSED] drm_test_damage_iter_no_damage
[23:01:36] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[23:01:36] [PASSED] drm_test_damage_iter_no_damage_src_moved
[23:01:36] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[23:01:36] [PASSED] drm_test_damage_iter_no_damage_not_visible
[23:01:36] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[23:01:36] [PASSED] drm_test_damage_iter_no_damage_no_fb
[23:01:36] [PASSED] drm_test_damage_iter_simple_damage
[23:01:36] [PASSED] drm_test_damage_iter_single_damage
[23:01:36] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[23:01:36] [PASSED] drm_test_damage_iter_single_damage_outside_src
[23:01:36] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[23:01:36] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[23:01:36] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[23:01:36] [PASSED] drm_test_damage_iter_single_damage_src_moved
[23:01:36] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[23:01:36] [PASSED] drm_test_damage_iter_damage
[23:01:36] [PASSED] drm_test_damage_iter_damage_one_intersect
[23:01:36] [PASSED] drm_test_damage_iter_damage_one_outside
[23:01:36] [PASSED] drm_test_damage_iter_damage_src_moved
[23:01:36] [PASSED] drm_test_damage_iter_damage_not_visible
[23:01:36] ================ [PASSED] drm_damage_helper ================
[23:01:36] ============== drm_dp_mst_helper (3 subtests) ==============
[23:01:36] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[23:01:36] [PASSED] Clock 154000 BPP 30 DSC disabled
[23:01:36] [PASSED] Clock 234000 BPP 30 DSC disabled
[23:01:36] [PASSED] Clock 297000 BPP 24 DSC disabled
[23:01:36] [PASSED] Clock 332880 BPP 24 DSC enabled
[23:01:36] [PASSED] Clock 324540 BPP 24 DSC enabled
[23:01:36] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[23:01:36] ============== drm_test_dp_mst_calc_pbn_div  ===============
[23:01:36] [PASSED] Link rate 2000000 lane count 4
[23:01:36] [PASSED] Link rate 2000000 lane count 2
[23:01:36] [PASSED] Link rate 2000000 lane count 1
[23:01:36] [PASSED] Link rate 1350000 lane count 4
[23:01:36] [PASSED] Link rate 1350000 lane count 2
[23:01:36] [PASSED] Link rate 1350000 lane count 1
[23:01:36] [PASSED] Link rate 1000000 lane count 4
[23:01:36] [PASSED] Link rate 1000000 lane count 2
[23:01:36] [PASSED] Link rate 1000000 lane count 1
[23:01:36] [PASSED] Link rate 810000 lane count 4
[23:01:36] [PASSED] Link rate 810000 lane count 2
[23:01:36] [PASSED] Link rate 810000 lane count 1
[23:01:36] [PASSED] Link rate 540000 lane count 4
[23:01:36] [PASSED] Link rate 540000 lane count 2
[23:01:36] [PASSED] Link rate 540000 lane count 1
[23:01:36] [PASSED] Link rate 270000 lane count 4
[23:01:36] [PASSED] Link rate 270000 lane count 2
[23:01:36] [PASSED] Link rate 270000 lane count 1
[23:01:36] [PASSED] Link rate 162000 lane count 4
[23:01:36] [PASSED] Link rate 162000 lane count 2
[23:01:36] [PASSED] Link rate 162000 lane count 1
[23:01:36] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[23:01:36] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[23:01:36] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[23:01:36] [PASSED] DP_POWER_UP_PHY with port number
[23:01:36] [PASSED] DP_POWER_DOWN_PHY with port number
[23:01:36] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[23:01:36] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[23:01:36] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[23:01:36] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[23:01:36] [PASSED] DP_QUERY_PAYLOAD with port number
[23:01:36] [PASSED] DP_QUERY_PAYLOAD with VCPI
[23:01:36] [PASSED] DP_REMOTE_DPCD_READ with port number
[23:01:36] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[23:01:36] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[23:01:36] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[23:01:36] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[23:01:36] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[23:01:36] [PASSED] DP_REMOTE_I2C_READ with port number
[23:01:36] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[23:01:36] [PASSED] DP_REMOTE_I2C_READ with transactions array
[23:01:36] [PASSED] DP_REMOTE_I2C_WRITE with port number
[23:01:36] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[23:01:36] [PASSED] DP_REMOTE_I2C_WRITE with data array
[23:01:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[23:01:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[23:01:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[23:01:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[23:01:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[23:01:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[23:01:36] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[23:01:36] ================ [PASSED] drm_dp_mst_helper ================
[23:01:36] ================== drm_exec (7 subtests) ===================
[23:01:36] [PASSED] sanitycheck
[23:01:36] [PASSED] test_lock
[23:01:36] [PASSED] test_lock_unlock
[23:01:36] [PASSED] test_duplicates
[23:01:36] [PASSED] test_prepare
[23:01:36] [PASSED] test_prepare_array
[23:01:36] [PASSED] test_multiple_loops
[23:01:36] ==================== [PASSED] drm_exec =====================
[23:01:36] =========== drm_format_helper_test (17 subtests) ===========
[23:01:36] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[23:01:36] [PASSED] single_pixel_source_buffer
[23:01:36] [PASSED] single_pixel_clip_rectangle
[23:01:36] [PASSED] well_known_colors
[23:01:36] [PASSED] destination_pitch
[23:01:36] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[23:01:36] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[23:01:36] [PASSED] single_pixel_source_buffer
[23:01:36] [PASSED] single_pixel_clip_rectangle
[23:01:36] [PASSED] well_known_colors
[23:01:36] [PASSED] destination_pitch
[23:01:36] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[23:01:36] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[23:01:36] [PASSED] single_pixel_source_buffer
[23:01:36] [PASSED] single_pixel_clip_rectangle
[23:01:36] [PASSED] well_known_colors
[23:01:36] [PASSED] destination_pitch
[23:01:36] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[23:01:36] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[23:01:36] [PASSED] single_pixel_source_buffer
[23:01:36] [PASSED] single_pixel_clip_rectangle
[23:01:36] [PASSED] well_known_colors
[23:01:36] [PASSED] destination_pitch
[23:01:36] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[23:01:36] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[23:01:36] [PASSED] single_pixel_source_buffer
[23:01:36] [PASSED] single_pixel_clip_rectangle
[23:01:36] [PASSED] well_known_colors
[23:01:36] [PASSED] destination_pitch
[23:01:36] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[23:01:36] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[23:01:36] [PASSED] single_pixel_source_buffer
[23:01:36] [PASSED] single_pixel_clip_rectangle
[23:01:36] [PASSED] well_known_colors
[23:01:36] [PASSED] destination_pitch
[23:01:36] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[23:01:36] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[23:01:36] [PASSED] single_pixel_source_buffer
[23:01:36] [PASSED] single_pixel_clip_rectangle
[23:01:36] [PASSED] well_known_colors
[23:01:36] [PASSED] destination_pitch
[23:01:36] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[23:01:36] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[23:01:36] [PASSED] single_pixel_source_buffer
[23:01:36] [PASSED] single_pixel_clip_rectangle
[23:01:36] [PASSED] well_known_colors
[23:01:36] [PASSED] destination_pitch
[23:01:36] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[23:01:36] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[23:01:36] [PASSED] single_pixel_source_buffer
[23:01:36] [PASSED] single_pixel_clip_rectangle
[23:01:36] [PASSED] well_known_colors
[23:01:36] [PASSED] destination_pitch
[23:01:36] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[23:01:36] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[23:01:36] [PASSED] single_pixel_source_buffer
[23:01:36] [PASSED] single_pixel_clip_rectangle
[23:01:36] [PASSED] well_known_colors
[23:01:36] [PASSED] destination_pitch
[23:01:36] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[23:01:36] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[23:01:36] [PASSED] single_pixel_source_buffer
[23:01:36] [PASSED] single_pixel_clip_rectangle
[23:01:36] [PASSED] well_known_colors
[23:01:36] [PASSED] destination_pitch
[23:01:36] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[23:01:36] ============== drm_test_fb_xrgb8888_to_mono  ===============
[23:01:36] [PASSED] single_pixel_source_buffer
[23:01:36] [PASSED] single_pixel_clip_rectangle
[23:01:36] [PASSED] well_known_colors
[23:01:36] [PASSED] destination_pitch
[23:01:36] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[23:01:36] ==================== drm_test_fb_swab  =====================
[23:01:36] [PASSED] single_pixel_source_buffer
[23:01:36] [PASSED] single_pixel_clip_rectangle
[23:01:36] [PASSED] well_known_colors
[23:01:36] [PASSED] destination_pitch
[23:01:36] ================ [PASSED] drm_test_fb_swab =================
[23:01:36] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[23:01:36] [PASSED] single_pixel_source_buffer
[23:01:36] [PASSED] single_pixel_clip_rectangle
[23:01:36] [PASSED] well_known_colors
[23:01:36] [PASSED] destination_pitch
[23:01:36] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[23:01:36] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[23:01:36] [PASSED] single_pixel_source_buffer
[23:01:36] [PASSED] single_pixel_clip_rectangle
[23:01:36] [PASSED] well_known_colors
[23:01:36] [PASSED] destination_pitch
[23:01:36] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[23:01:36] ================= drm_test_fb_clip_offset  =================
[23:01:36] [PASSED] pass through
[23:01:36] [PASSED] horizontal offset
[23:01:36] [PASSED] vertical offset
[23:01:36] [PASSED] horizontal and vertical offset
[23:01:36] [PASSED] horizontal offset (custom pitch)
[23:01:36] [PASSED] vertical offset (custom pitch)
[23:01:36] [PASSED] horizontal and vertical offset (custom pitch)
[23:01:36] ============= [PASSED] drm_test_fb_clip_offset =============
[23:01:36] =================== drm_test_fb_memcpy  ====================
[23:01:36] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[23:01:36] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[23:01:36] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[23:01:36] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[23:01:36] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[23:01:36] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[23:01:36] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[23:01:36] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[23:01:36] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[23:01:36] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[23:01:36] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[23:01:36] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[23:01:36] =============== [PASSED] drm_test_fb_memcpy ================
[23:01:36] ============= [PASSED] drm_format_helper_test ==============
[23:01:36] ================= drm_format (18 subtests) =================
[23:01:36] [PASSED] drm_test_format_block_width_invalid
[23:01:36] [PASSED] drm_test_format_block_width_one_plane
[23:01:36] [PASSED] drm_test_format_block_width_two_plane
[23:01:36] [PASSED] drm_test_format_block_width_three_plane
[23:01:36] [PASSED] drm_test_format_block_width_tiled
[23:01:36] [PASSED] drm_test_format_block_height_invalid
[23:01:36] [PASSED] drm_test_format_block_height_one_plane
[23:01:36] [PASSED] drm_test_format_block_height_two_plane
[23:01:36] [PASSED] drm_test_format_block_height_three_plane
[23:01:36] [PASSED] drm_test_format_block_height_tiled
[23:01:36] [PASSED] drm_test_format_min_pitch_invalid
[23:01:36] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[23:01:36] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[23:01:36] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[23:01:36] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[23:01:36] [PASSED] drm_test_format_min_pitch_two_plane
[23:01:36] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[23:01:36] [PASSED] drm_test_format_min_pitch_tiled
[23:01:36] =================== [PASSED] drm_format ====================
[23:01:36] ============== drm_framebuffer (10 subtests) ===============
[23:01:36] ========== drm_test_framebuffer_check_src_coords  ==========
[23:01:36] [PASSED] Success: source fits into fb
[23:01:36] [PASSED] Fail: overflowing fb with x-axis coordinate
[23:01:36] [PASSED] Fail: overflowing fb with y-axis coordinate
[23:01:36] [PASSED] Fail: overflowing fb with source width
[23:01:36] [PASSED] Fail: overflowing fb with source height
[23:01:36] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[23:01:36] [PASSED] drm_test_framebuffer_cleanup
[23:01:36] =============== drm_test_framebuffer_create  ===============
[23:01:36] [PASSED] ABGR8888 normal sizes
[23:01:36] [PASSED] ABGR8888 max sizes
[23:01:36] [PASSED] ABGR8888 pitch greater than min required
[23:01:36] [PASSED] ABGR8888 pitch less than min required
[23:01:36] [PASSED] ABGR8888 Invalid width
[23:01:36] [PASSED] ABGR8888 Invalid buffer handle
[23:01:36] [PASSED] No pixel format
[23:01:36] [PASSED] ABGR8888 Width 0
[23:01:36] [PASSED] ABGR8888 Height 0
[23:01:36] [PASSED] ABGR8888 Out of bound height * pitch combination
[23:01:36] [PASSED] ABGR8888 Large buffer offset
[23:01:36] [PASSED] ABGR8888 Buffer offset for inexistent plane
[23:01:36] [PASSED] ABGR8888 Invalid flag
[23:01:36] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[23:01:36] [PASSED] ABGR8888 Valid buffer modifier
[23:01:36] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[23:01:36] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[23:01:36] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[23:01:36] [PASSED] NV12 Normal sizes
[23:01:36] [PASSED] NV12 Max sizes
[23:01:36] [PASSED] NV12 Invalid pitch
[23:01:36] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[23:01:36] [PASSED] NV12 different  modifier per-plane
[23:01:36] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[23:01:36] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[23:01:36] [PASSED] NV12 Modifier for inexistent plane
[23:01:36] [PASSED] NV12 Handle for inexistent plane
[23:01:36] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[23:01:36] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[23:01:36] [PASSED] YVU420 Normal sizes
[23:01:36] [PASSED] YVU420 Max sizes
[23:01:36] [PASSED] YVU420 Invalid pitch
[23:01:36] [PASSED] YVU420 Different pitches
[23:01:36] [PASSED] YVU420 Different buffer offsets/pitches
[23:01:36] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[23:01:36] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[23:01:36] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[23:01:36] [PASSED] YVU420 Valid modifier
[23:01:36] [PASSED] YVU420 Different modifiers per plane
[23:01:36] [PASSED] YVU420 Modifier for inexistent plane
[23:01:36] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[23:01:36] [PASSED] X0L2 Normal sizes
[23:01:36] [PASSED] X0L2 Max sizes
[23:01:36] [PASSED] X0L2 Invalid pitch
[23:01:36] [PASSED] X0L2 Pitch greater than minimum required
[23:01:36] [PASSED] X0L2 Handle for inexistent plane
[23:01:36] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[23:01:36] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[23:01:36] [PASSED] X0L2 Valid modifier
[23:01:36] [PASSED] X0L2 Modifier for inexistent plane
[23:01:36] =========== [PASSED] drm_test_framebuffer_create ===========
[23:01:36] [PASSED] drm_test_framebuffer_free
[23:01:36] [PASSED] drm_test_framebuffer_init
[23:01:36] [PASSED] drm_test_framebuffer_init_bad_format
[23:01:36] [PASSED] drm_test_framebuffer_init_dev_mismatch
[23:01:36] [PASSED] drm_test_framebuffer_lookup
[23:01:36] [PASSED] drm_test_framebuffer_lookup_inexistent
[23:01:36] [PASSED] drm_test_framebuffer_modifiers_not_supported
[23:01:36] ================= [PASSED] drm_framebuffer =================
[23:01:36] ================ drm_gem_shmem (8 subtests) ================
[23:01:36] [PASSED] drm_gem_shmem_test_obj_create
[23:01:36] [PASSED] drm_gem_shmem_test_obj_create_private
[23:01:36] [PASSED] drm_gem_shmem_test_pin_pages
[23:01:36] [PASSED] drm_gem_shmem_test_vmap
[23:01:36] [PASSED] drm_gem_shmem_test_get_sg_table
[23:01:36] [PASSED] drm_gem_shmem_test_get_pages_sgt
[23:01:36] [PASSED] drm_gem_shmem_test_madvise
[23:01:36] [PASSED] drm_gem_shmem_test_purge
[23:01:36] ================== [PASSED] drm_gem_shmem ==================
[23:01:36] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[23:01:36] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[23:01:36] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[23:01:36] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[23:01:36] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[23:01:36] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[23:01:36] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[23:01:36] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[23:01:36] [PASSED] Automatic
[23:01:36] [PASSED] Full
[23:01:36] [PASSED] Limited 16:235
[23:01:36] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[23:01:36] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[23:01:36] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[23:01:36] [PASSED] drm_test_check_disable_connector
[23:01:36] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[23:01:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[23:01:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[23:01:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[23:01:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[23:01:36] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[23:01:36] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[23:01:36] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[23:01:36] [PASSED] drm_test_check_output_bpc_dvi
[23:01:36] [PASSED] drm_test_check_output_bpc_format_vic_1
[23:01:36] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[23:01:36] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[23:01:36] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[23:01:36] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[23:01:36] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[23:01:36] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[23:01:36] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[23:01:36] ============ drm_test_check_hdmi_color_format  =============
[23:01:36] [PASSED] AUTO -> RGB
[23:01:36] [PASSED] YCBCR422 -> YUV422
[23:01:36] [PASSED] YCBCR420 -> YUV420
[23:01:36] [PASSED] YCBCR444 -> YUV444
[23:01:36] [PASSED] RGB -> RGB
[23:01:36] ======== [PASSED] drm_test_check_hdmi_color_format =========
[23:01:36] ======== drm_test_check_hdmi_color_format_420_only  ========
[23:01:36] [PASSED] RGB should fail
[23:01:36] [PASSED] YUV444 should fail
[23:01:36] [PASSED] YUV422 should fail
[23:01:36] [PASSED] YUV420 should work
[23:01:36] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[23:01:36] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[23:01:36] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[23:01:36] [PASSED] drm_test_check_broadcast_rgb_value
[23:01:36] [PASSED] drm_test_check_bpc_8_value
[23:01:36] [PASSED] drm_test_check_bpc_10_value
[23:01:36] [PASSED] drm_test_check_bpc_12_value
[23:01:36] [PASSED] drm_test_check_format_value
[23:01:36] [PASSED] drm_test_check_tmds_char_value
[23:01:36] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[23:01:36] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[23:01:36] [PASSED] drm_test_check_mode_valid
[23:01:36] [PASSED] drm_test_check_mode_valid_reject
[23:01:36] [PASSED] drm_test_check_mode_valid_reject_rate
[23:01:36] [PASSED] drm_test_check_mode_valid_reject_max_clock
[23:01:36] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[23:01:36] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[23:01:36] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[23:01:36] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[23:01:36] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[23:01:36] [PASSED] drm_test_check_infoframes
[23:01:36] [PASSED] drm_test_check_reject_avi_infoframe
[23:01:36] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[23:01:36] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[23:01:36] [PASSED] drm_test_check_reject_audio_infoframe
[23:01:36] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[23:01:36] ================= drm_managed (2 subtests) =================
[23:01:36] [PASSED] drm_test_managed_release_action
[23:01:36] [PASSED] drm_test_managed_run_action
[23:01:36] =================== [PASSED] drm_managed ===================
[23:01:36] =================== drm_mm (6 subtests) ====================
[23:01:36] [PASSED] drm_test_mm_init
[23:01:36] [PASSED] drm_test_mm_debug
[23:01:36] [PASSED] drm_test_mm_align32
[23:01:36] [PASSED] drm_test_mm_align64
[23:01:36] [PASSED] drm_test_mm_lowest
[23:01:36] [PASSED] drm_test_mm_highest
[23:01:36] ===================== [PASSED] drm_mm ======================
[23:01:36] ============= drm_modes_analog_tv (5 subtests) =============
[23:01:36] [PASSED] drm_test_modes_analog_tv_mono_576i
[23:01:36] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[23:01:36] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[23:01:36] [PASSED] drm_test_modes_analog_tv_pal_576i
[23:01:36] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[23:01:36] =============== [PASSED] drm_modes_analog_tv ===============
[23:01:36] ============== drm_plane_helper (2 subtests) ===============
[23:01:36] =============== drm_test_check_plane_state  ================
[23:01:36] [PASSED] clipping_simple
[23:01:36] [PASSED] clipping_rotate_reflect
[23:01:36] [PASSED] positioning_simple
[23:01:36] [PASSED] upscaling
[23:01:36] [PASSED] downscaling
[23:01:36] [PASSED] rounding1
[23:01:36] [PASSED] rounding2
[23:01:36] [PASSED] rounding3
[23:01:36] [PASSED] rounding4
[23:01:36] =========== [PASSED] drm_test_check_plane_state ============
[23:01:36] =========== drm_test_check_invalid_plane_state  ============
[23:01:36] [PASSED] positioning_invalid
[23:01:36] [PASSED] upscaling_invalid
[23:01:36] [PASSED] downscaling_invalid
[23:01:36] ======= [PASSED] drm_test_check_invalid_plane_state ========
[23:01:36] ================ [PASSED] drm_plane_helper =================
[23:01:36] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[23:01:36] ====== drm_test_connector_helper_tv_get_modes_check  =======
[23:01:36] [PASSED] None
[23:01:36] [PASSED] PAL
[23:01:36] [PASSED] NTSC
[23:01:36] [PASSED] Both, NTSC Default
[23:01:36] [PASSED] Both, PAL Default
[23:01:36] [PASSED] Both, NTSC Default, with PAL on command-line
[23:01:36] [PASSED] Both, PAL Default, with NTSC on command-line
[23:01:36] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[23:01:36] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[23:01:36] ================== drm_rect (9 subtests) ===================
[23:01:36] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[23:01:36] [PASSED] drm_test_rect_clip_scaled_not_clipped
[23:01:36] [PASSED] drm_test_rect_clip_scaled_clipped
[23:01:36] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[23:01:36] ================= drm_test_rect_intersect  =================
[23:01:36] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[23:01:36] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[23:01:36] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[23:01:36] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[23:01:36] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[23:01:36] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[23:01:36] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[23:01:36] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[23:01:36] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[23:01:36] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[23:01:36] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[23:01:36] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[23:01:36] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[23:01:36] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[23:01:36] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[23:01:36] ============= [PASSED] drm_test_rect_intersect =============
[23:01:36] ================ drm_test_rect_calc_hscale  ================
[23:01:36] [PASSED] normal use
[23:01:36] [PASSED] out of max range
[23:01:36] [PASSED] out of min range
[23:01:36] [PASSED] zero dst
[23:01:36] [PASSED] negative src
[23:01:36] [PASSED] negative dst
[23:01:36] ============ [PASSED] drm_test_rect_calc_hscale ============
[23:01:36] ================ drm_test_rect_calc_vscale  ================
[23:01:36] [PASSED] normal use
[23:01:36] [PASSED] out of max range
[23:01:36] [PASSED] out of min range
[23:01:36] [PASSED] zero dst
[23:01:36] [PASSED] negative src
[23:01:36] [PASSED] negative dst
[23:01:36] ============ [PASSED] drm_test_rect_calc_vscale ============
[23:01:36] ================== drm_test_rect_rotate  ===================
[23:01:36] [PASSED] reflect-x
[23:01:36] [PASSED] reflect-y
[23:01:36] [PASSED] rotate-0
[23:01:36] [PASSED] rotate-90
[23:01:36] [PASSED] rotate-180
[23:01:36] [PASSED] rotate-270
[23:01:36] ============== [PASSED] drm_test_rect_rotate ===============
[23:01:36] ================ drm_test_rect_rotate_inv  =================
[23:01:36] [PASSED] reflect-x
[23:01:36] [PASSED] reflect-y
[23:01:36] [PASSED] rotate-0
[23:01:36] [PASSED] rotate-90
[23:01:36] [PASSED] rotate-180
[23:01:36] [PASSED] rotate-270
[23:01:36] ============ [PASSED] drm_test_rect_rotate_inv =============
[23:01:36] ==================== [PASSED] drm_rect =====================
[23:01:36] ============ drm_sysfb_modeset_test (1 subtest) ============
[23:01:36] ============ drm_test_sysfb_build_fourcc_list  =============
[23:01:36] [PASSED] no native formats
[23:01:36] [PASSED] XRGB8888 as native format
[23:01:36] [PASSED] remove duplicates
[23:01:36] [PASSED] convert alpha formats
[23:01:36] [PASSED] random formats
[23:01:36] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[23:01:36] ============= [PASSED] drm_sysfb_modeset_test ==============
[23:01:36] ================== drm_fixp (2 subtests) ===================
[23:01:36] [PASSED] drm_test_int2fixp
[23:01:36] [PASSED] drm_test_sm2fixp
[23:01:36] ==================== [PASSED] drm_fixp =====================
[23:01:36] ============================================================
[23:01:36] Testing complete. Ran 637 tests: passed: 637
[23:01:36] Elapsed time: 26.613s total, 1.831s configuring, 24.613s building, 0.149s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[23:01:36] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:01:38] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:01:48] Starting KUnit Kernel (1/1)...
[23:01:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:01:48] ================= ttm_device (5 subtests) ==================
[23:01:48] [PASSED] ttm_device_init_basic
[23:01:48] [PASSED] ttm_device_init_multiple
[23:01:48] [PASSED] ttm_device_fini_basic
[23:01:48] [PASSED] ttm_device_init_no_vma_man
[23:01:48] ================== ttm_device_init_pools  ==================
[23:01:48] [PASSED] No DMA allocations, no DMA32 required
[23:01:48] [PASSED] DMA allocations, DMA32 required
[23:01:48] [PASSED] No DMA allocations, DMA32 required
[23:01:48] [PASSED] DMA allocations, no DMA32 required
[23:01:48] ============== [PASSED] ttm_device_init_pools ==============
[23:01:48] =================== [PASSED] ttm_device ====================
[23:01:48] ================== ttm_pool (8 subtests) ===================
[23:01:48] ================== ttm_pool_alloc_basic  ===================
[23:01:48] [PASSED] One page
[23:01:48] [PASSED] More than one page
[23:01:48] [PASSED] Above the allocation limit
[23:01:48] [PASSED] One page, with coherent DMA mappings enabled
[23:01:48] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[23:01:48] ============== [PASSED] ttm_pool_alloc_basic ===============
[23:01:48] ============== ttm_pool_alloc_basic_dma_addr  ==============
[23:01:48] [PASSED] One page
[23:01:48] [PASSED] More than one page
[23:01:48] [PASSED] Above the allocation limit
[23:01:48] [PASSED] One page, with coherent DMA mappings enabled
[23:01:48] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[23:01:48] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[23:01:48] [PASSED] ttm_pool_alloc_order_caching_match
[23:01:48] [PASSED] ttm_pool_alloc_caching_mismatch
[23:01:48] [PASSED] ttm_pool_alloc_order_mismatch
[23:01:48] [PASSED] ttm_pool_free_dma_alloc
[23:01:48] [PASSED] ttm_pool_free_no_dma_alloc
[23:01:48] [PASSED] ttm_pool_fini_basic
[23:01:48] ==================== [PASSED] ttm_pool =====================
[23:01:48] ================ ttm_resource (8 subtests) =================
[23:01:48] ================= ttm_resource_init_basic  =================
[23:01:48] [PASSED] Init resource in TTM_PL_SYSTEM
[23:01:48] [PASSED] Init resource in TTM_PL_VRAM
[23:01:48] [PASSED] Init resource in a private placement
[23:01:48] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[23:01:48] ============= [PASSED] ttm_resource_init_basic =============
[23:01:48] [PASSED] ttm_resource_init_pinned
[23:01:48] [PASSED] ttm_resource_fini_basic
[23:01:48] [PASSED] ttm_resource_manager_init_basic
[23:01:48] [PASSED] ttm_resource_manager_usage_basic
[23:01:48] [PASSED] ttm_resource_manager_set_used_basic
[23:01:48] [PASSED] ttm_sys_man_alloc_basic
[23:01:48] [PASSED] ttm_sys_man_free_basic
[23:01:48] ================== [PASSED] ttm_resource ===================
[23:01:48] =================== ttm_tt (15 subtests) ===================
[23:01:48] ==================== ttm_tt_init_basic  ====================
[23:01:48] [PASSED] Page-aligned size
[23:01:48] [PASSED] Extra pages requested
[23:01:48] ================ [PASSED] ttm_tt_init_basic ================
[23:01:48] [PASSED] ttm_tt_init_misaligned
[23:01:48] [PASSED] ttm_tt_fini_basic
[23:01:48] [PASSED] ttm_tt_fini_sg
[23:01:48] [PASSED] ttm_tt_fini_shmem
[23:01:48] [PASSED] ttm_tt_create_basic
[23:01:48] [PASSED] ttm_tt_create_invalid_bo_type
[23:01:48] [PASSED] ttm_tt_create_ttm_exists
[23:01:48] [PASSED] ttm_tt_create_failed
[23:01:48] [PASSED] ttm_tt_destroy_basic
[23:01:48] [PASSED] ttm_tt_populate_null_ttm
[23:01:48] [PASSED] ttm_tt_populate_populated_ttm
[23:01:48] [PASSED] ttm_tt_unpopulate_basic
[23:01:48] [PASSED] ttm_tt_unpopulate_empty_ttm
[23:01:48] [PASSED] ttm_tt_swapin_basic
[23:01:48] ===================== [PASSED] ttm_tt ======================
[23:01:48] =================== ttm_bo (14 subtests) ===================
[23:01:48] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[23:01:48] [PASSED] Cannot be interrupted and sleeps
[23:01:48] [PASSED] Cannot be interrupted, locks straight away
[23:01:48] [PASSED] Can be interrupted, sleeps
[23:01:48] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[23:01:48] [PASSED] ttm_bo_reserve_locked_no_sleep
[23:01:48] [PASSED] ttm_bo_reserve_no_wait_ticket
[23:01:48] [PASSED] ttm_bo_reserve_double_resv
[23:01:48] [PASSED] ttm_bo_reserve_interrupted
[23:01:48] [PASSED] ttm_bo_reserve_deadlock
[23:01:48] [PASSED] ttm_bo_unreserve_basic
[23:01:48] [PASSED] ttm_bo_unreserve_pinned
[23:01:48] [PASSED] ttm_bo_unreserve_bulk
[23:01:48] [PASSED] ttm_bo_fini_basic
[23:01:48] [PASSED] ttm_bo_fini_shared_resv
[23:01:48] [PASSED] ttm_bo_pin_basic
[23:01:48] [PASSED] ttm_bo_pin_unpin_resource
[23:01:48] [PASSED] ttm_bo_multiple_pin_one_unpin
[23:01:48] ===================== [PASSED] ttm_bo ======================
[23:01:48] ============== ttm_bo_validate (22 subtests) ===============
[23:01:48] ============== ttm_bo_init_reserved_sys_man  ===============
[23:01:48] [PASSED] Buffer object for userspace
[23:01:48] [PASSED] Kernel buffer object
[23:01:48] [PASSED] Shared buffer object
[23:01:48] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[23:01:48] ============== ttm_bo_init_reserved_mock_man  ==============
[23:01:48] [PASSED] Buffer object for userspace
[23:01:48] [PASSED] Kernel buffer object
[23:01:48] [PASSED] Shared buffer object
[23:01:48] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[23:01:48] [PASSED] ttm_bo_init_reserved_resv
[23:01:48] ================== ttm_bo_validate_basic  ==================
[23:01:48] [PASSED] Buffer object for userspace
[23:01:48] [PASSED] Kernel buffer object
[23:01:48] [PASSED] Shared buffer object
[23:01:48] ============== [PASSED] ttm_bo_validate_basic ==============
[23:01:48] [PASSED] ttm_bo_validate_invalid_placement
[23:01:48] ============= ttm_bo_validate_same_placement  ==============
[23:01:48] [PASSED] System manager
[23:01:48] [PASSED] VRAM manager
[23:01:48] ========= [PASSED] ttm_bo_validate_same_placement ==========
[23:01:48] [PASSED] ttm_bo_validate_failed_alloc
[23:01:48] [PASSED] ttm_bo_validate_pinned
[23:01:48] [PASSED] ttm_bo_validate_busy_placement
[23:01:48] ================ ttm_bo_validate_multihop  =================
[23:01:48] [PASSED] Buffer object for userspace
[23:01:48] [PASSED] Kernel buffer object
[23:01:48] [PASSED] Shared buffer object
[23:01:48] ============ [PASSED] ttm_bo_validate_multihop =============
[23:01:48] ========== ttm_bo_validate_no_placement_signaled  ==========
[23:01:48] [PASSED] Buffer object in system domain, no page vector
[23:01:48] [PASSED] Buffer object in system domain with an existing page vector
[23:01:48] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[23:01:48] ======== ttm_bo_validate_no_placement_not_signaled  ========
[23:01:48] [PASSED] Buffer object for userspace
[23:01:48] [PASSED] Kernel buffer object
[23:01:48] [PASSED] Shared buffer object
[23:01:48] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[23:01:48] [PASSED] ttm_bo_validate_move_fence_signaled
[23:01:48] ========= ttm_bo_validate_move_fence_not_signaled  =========
[23:01:48] [PASSED] Waits for GPU
[23:01:48] [PASSED] Tries to lock straight away
[23:01:48] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[23:01:48] [PASSED] ttm_bo_validate_swapout
[23:01:48] [PASSED] ttm_bo_validate_happy_evict
[23:01:48] [PASSED] ttm_bo_validate_all_pinned_evict
[23:01:48] [PASSED] ttm_bo_validate_allowed_only_evict
[23:01:48] [PASSED] ttm_bo_validate_deleted_evict
[23:01:48] [PASSED] ttm_bo_validate_busy_domain_evict
[23:01:48] [PASSED] ttm_bo_validate_evict_gutting
[23:01:48] [PASSED] ttm_bo_validate_recrusive_evict
[23:01:48] ================= [PASSED] ttm_bo_validate =================
[23:01:48] ============================================================
[23:01:48] Testing complete. Ran 102 tests: passed: 102
[23:01:48] Elapsed time: 12.197s total, 1.794s configuring, 10.138s building, 0.225s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[23:01:49] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:01:50] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:01:59] Starting KUnit Kernel (1/1)...
[23:01:59] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:01:59] =============== dma-buf-fence (12 subtests) ================
[23:01:59] [PASSED] test_sanitycheck
[23:01:59] [PASSED] test_signaling
[23:01:59] [PASSED] test_add_callback
[23:01:59] [PASSED] test_late_add_callback
[23:01:59] [PASSED] test_rm_callback
[23:01:59] [PASSED] test_late_rm_callback
[23:01:59] [PASSED] test_status
[23:01:59] [PASSED] test_error
[23:01:59] [PASSED] test_wait
[23:01:59] [PASSED] test_wait_timeout
[23:01:59] [PASSED] test_stub
[23:01:59] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[23:01:59] ================== [PASSED] dma-buf-fence ==================
[23:01:59] ============ dma-buf-fence-chain (11 subtests) =============
[23:01:59] [PASSED] test_sanitycheck
[23:01:59] [PASSED] test_find_seqno
[23:01:59] [PASSED] test_find_signaled
[23:01:59] [PASSED] test_find_out_of_order
[23:02:04] [PASSED] test_find_gap
[23:02:04] [PASSED] test_find_race
[23:02:04] [PASSED] test_signal_forward
[23:02:04] [PASSED] test_signal_backward
[23:02:04] [PASSED] test_wait_forward
[23:02:04] [PASSED] test_wait_backward
[23:02:04] [PASSED] test_wait_random
[23:02:04] =============== [PASSED] dma-buf-fence-chain ===============
[23:02:04] ============ dma-buf-fence-unwrap (10 subtests) ============
[23:02:04] [PASSED] test_sanitycheck
[23:02:04] [PASSED] test_unwrap_array
[23:02:04] [PASSED] test_unwrap_chain
[23:02:04] [PASSED] test_unwrap_chain_array
[23:02:04] [PASSED] test_unwrap_merge
[23:02:04] [PASSED] test_unwrap_merge_duplicate
[23:02:04] [PASSED] test_unwrap_merge_seqno
[23:02:04] [PASSED] test_unwrap_merge_order
[23:02:04] [PASSED] test_unwrap_merge_complex
[23:02:04] [PASSED] test_unwrap_merge_complex_seqno
[23:02:04] ============== [PASSED] dma-buf-fence-unwrap ===============
[23:02:04] ================ dma-buf-resv (5 subtests) =================
[23:02:04] [PASSED] test_sanitycheck
[23:02:04] ===================== test_signaling  ======================
[23:02:04] [PASSED] kernel
[23:02:04] [PASSED] write
[23:02:04] [PASSED] read
[23:02:04] [PASSED] bookkeep
[23:02:04] ================= [PASSED] test_signaling ==================
[23:02:04] ====================== test_for_each  ======================
[23:02:04] [PASSED] kernel
[23:02:04] [PASSED] write
[23:02:04] [PASSED] read
[23:02:04] [PASSED] bookkeep
[23:02:04] ================== [PASSED] test_for_each ==================
[23:02:04] ================= test_for_each_unlocked  ==================
[23:02:04] [PASSED] kernel
[23:02:04] [PASSED] write
[23:02:04] [PASSED] read
[23:02:04] [PASSED] bookkeep
[23:02:04] ============= [PASSED] test_for_each_unlocked ==============
[23:02:04] ===================== test_get_fences  =====================
[23:02:04] [PASSED] kernel
[23:02:04] [PASSED] write
[23:02:04] [PASSED] read
[23:02:04] [PASSED] bookkeep
[23:02:04] ================= [PASSED] test_get_fences =================
[23:02:04] ================== [PASSED] dma-buf-resv ===================
[23:02:04] ============================================================
[23:02:04] Testing complete. Ran 50 tests: passed: 49, skipped: 1
[23:02:04] Elapsed time: 15.789s total, 1.822s configuring, 8.645s building, 5.277s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ Xe.CI.BAT: failure for drm/xe/hwmon: Update hwmon thermal mailbox handling

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1712 bytes --]

== Series Details ==

Series: drm/xe/hwmon: Update hwmon thermal mailbox handling
URL   : https://patchwork.freedesktop.org/series/172689/
State : failure

== Summary ==

CI Bug Log - changes from xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad_BAT -> xe-pw-172689v1_BAT
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-172689v1_BAT absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-172689v1_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 12)
------------------------------

  Missing    (1): bat-nvls-1 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-172689v1_BAT:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_module_load@load:
    - bat-atsm-2:         [PASS][1] -> [DMESG-WARN][2] +1 other test dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/bat-atsm-2/igt@xe_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/bat-atsm-2/igt@xe_module_load@load.html

  


Build changes
-------------

  * Linux: xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad -> xe-pw-172689v1

  IGT_9071: 9071
  xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad: 15e2ba2fb6d25c03d89519aec46f8d5be3e118ad
  xe-pw-172689v1: 172689v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/index.html

[-- Attachment #2: Type: text/html, Size: 2297 bytes --]

✓ Xe.CI.FULL: success for drm/xe/hwmon: Update hwmon thermal mailbox handling

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 21843 bytes --]

== Series Details ==

Series: drm/xe/hwmon: Update hwmon thermal mailbox handling
URL   : https://patchwork.freedesktop.org/series/172689/
State : success

== Summary ==

CI Bug Log - changes from xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad_FULL -> xe-pw-172689v1_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-172689v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-bmg:          [PASS][1] -> [FAIL][2] ([Intel XE#3718] / [Intel XE#6078])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-10/igt@kms_async_flips@alternate-sync-async-flip.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-7/igt@kms_async_flips@alternate-sync-async-flip.html
    - shard-lnl:          [PASS][3] -> [FAIL][4] ([Intel XE#3718] / [Intel XE#7265])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-lnl-1/igt@kms_async_flips@alternate-sync-async-flip.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-lnl-7/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-dp-2:
    - shard-bmg:          [PASS][5] -> [FAIL][6] ([Intel XE#6078])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-10/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-dp-2.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-7/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-dp-2.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1:
    - shard-lnl:          [PASS][7] -> [FAIL][8] ([Intel XE#7265])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-lnl-1/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-lnl-7/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1.html

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#2327])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-180:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#1124]) +2 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html

  * igt@kms_bw@linear-tiling-2-displays-target-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#367])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@kms_bw@linear-tiling-2-displays-target-3840x2160p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2887]) +2 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-d-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][13] ([Intel XE#7084] / [Intel XE#8150])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-d-hdmi-a-3.html

  * igt@kms_cdclk@plane-scaling:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#2724] / [Intel XE#7449])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_color@ctm-red-to-blue:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2325] / [Intel XE#7358])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@kms_chamelium_color@ctm-red-to-blue.html

  * igt@kms_cursor_crc@cursor-offscreen-max-size:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#2320]) +2 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@kms_cursor_crc@cursor-offscreen-max-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [PASS][17] -> [FAIL][18] ([Intel XE#7809])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#8265])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_feature_discovery@display-4x:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#1138] / [Intel XE#7344])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@kms_feature_discovery@display-4x.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-dp2:
    - shard-bmg:          [PASS][21] -> [FAIL][22] ([Intel XE#3098]) +1 other test fail
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-8/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-dp2.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-6/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-dp2.html

  * igt@kms_frontbuffer_tracking@drrs-shrfb-scaledprimary:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2311]) +11 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-shrfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#4141]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#7061])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#7061] / [Intel XE#7356]) +2 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#2313]) +14 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2393])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#2763] / [Intel XE#6886]) +4 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#7376] / [Intel XE#7760] / [Intel XE#870])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc5-pageflip-negative:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#6927])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@kms_pm_dc@dc5-pageflip-negative.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#1489])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr@psr-sprite-plane-move:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@kms_psr@psr-sprite-plane-move.html

  * igt@kms_sharpness_filter@filter-scaler-downscale:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#6503])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@kms_sharpness_filter@filter-scaler-downscale.html

  * igt@kms_vrr@flip-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#1499]) +1 other test skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@kms_vrr@flip-suspend.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#2322] / [Intel XE#7372]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_fault_mode@once-multi-queue-userptr-rebind-imm:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#8374]) +2 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@xe_exec_fault_mode@once-multi-queue-userptr-rebind-imm.html

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-basic:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#8364]) +7 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-basic.html

  * igt@xe_exec_threads@threads-multi-queue-cm-fd-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#8378])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-cm-fd-userptr.html

  * igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create:
    - shard-bmg:          [PASS][40] -> [ABORT][41] ([Intel XE#8007])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-6/igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-3/igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create.html

  * igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#2229])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit.html

  * igt@xe_multigpu_svm@mgpu-concurrent-access-basic:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#6964])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@xe_multigpu_svm@mgpu-concurrent-access-basic.html

  * igt@xe_page_reclaim@prl-invalidate-full:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#7793])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@xe_page_reclaim@prl-invalidate-full.html

  * igt@xe_pat@l2-flush-opt-svm-pat-restrict:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#7590])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@xe_pat@l2-flush-opt-svm-pat-restrict.html

  * igt@xe_pat@pat-index-xelp:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#2245] / [Intel XE#7590])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@xe_pat@pat-index-xelp.html

  * igt@xe_pm@d3cold-mocs:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#2284] / [Intel XE#7370])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@xe_pm@d3cold-mocs.html

  * igt@xe_pxp@pxp-stale-bo-exec-post-rpm:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#4733] / [Intel XE#7417])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@xe_pxp@pxp-stale-bo-exec-post-rpm.html

  * igt@xe_query@multigpu-query-hwconfig:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#944])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@xe_query@multigpu-query-hwconfig.html

  
#### Possible fixes ####

  * igt@core_hotunplug@hotrebind-with-load:
    - shard-bmg:          [ABORT][50] ([Intel XE#8007]) -> [PASS][51] +1 other test pass
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-1/igt@core_hotunplug@hotrebind-with-load.html
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-2/igt@core_hotunplug@hotrebind-with-load.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-d-dp-2:
    - shard-bmg:          [INCOMPLETE][52] ([Intel XE#7084] / [Intel XE#8150]) -> [PASS][53]
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-9/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-d-dp-2.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-d-dp-2.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [FAIL][54] ([Intel XE#7571]) -> [PASS][55]
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [FAIL][56] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][57] +1 other test pass
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip@modeset-vs-vblank-race-interruptible:
    - shard-bmg:          [FAIL][58] ([Intel XE#3098]) -> [PASS][59] +1 other test pass
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-2/igt@kms_flip@modeset-vs-vblank-race-interruptible.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-5/igt@kms_flip@modeset-vs-vblank-race-interruptible.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][60] ([Intel XE#1503]) -> [PASS][61]
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-5/igt@kms_hdr@invalid-hdr.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-8/igt@kms_hdr@invalid-hdr.html

  
#### Warnings ####

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][62] ([Intel XE#301] / [Intel XE#3149]) -> [FAIL][63] ([Intel XE#301]) +1 other test fail
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][64] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][65] ([Intel XE#3544])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-6/igt@kms_hdr@brightness-with-hdr.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-3/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][66] ([Intel XE#2509] / [Intel XE#7437]) -> [SKIP][67] ([Intel XE#2426] / [Intel XE#5848])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/shard-bmg-9/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2245]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2245
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6927
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7265
  [Intel XE#7344]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7344
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7449]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7449
  [Intel XE#7571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7571
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7809]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7809
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8150
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad -> xe-pw-172689v1

  IGT_9071: 9071
  xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad: 15e2ba2fb6d25c03d89519aec46f8d5be3e118ad
  xe-pw-172689v1: 172689v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172689v1/index.html

[-- Attachment #2: Type: text/html, Size: 24326 bytes --]

Re: [PATCH 1/3] drm/xe/hwmon: Detect unavailable temperature sensors

[Poosa, Karthik]

On 25-08-2026 00:29, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
> - [High] Incorrect register bitmask `TEMP_MASK` extracts fractional temperature instead of integer, improperly hiding valid VRAM sensors.
> - [Medium] Inverted short-circuit evaluation causes unconditional hardware PCODE reads and excessive log spam during hwmon registration.
> - [Medium] Threshold limit sysfs attributes are exposed for unavailable sensors due to missing validity checks.
> --
>
> --- Patch [1]: [PATCH 1/3] drm/xe/hwmon: Detect unavailable temperature sensors ---
> commit de3d36ad17dd257811068fa1f47a4b3779a65fb1
> Author: Karthik Poosa <karthik.poosa@intel.com>
>
> drm/xe/hwmon: Detect unavailable temperature sensors
>
> Add is_temp_valid() to validate sensor presence.
> A temperature reading of 0xFF on CRI platforms indicates that the
> corresponding sensor is not present and should be treated as unavailable.
>
> Use this check from xe_hwmon_temp_is_visible() callback so that attributes
> for unavailable sensors are not exposed during hwmon device registration.
>
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
>> index de3f2aeffc3fb..c15312b0858ca 100644
>> --- a/drivers/gpu/drm/xe/xe_hwmon.c
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> [ ... ]
>
>> @@ -804,11 +813,25 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>>   		drm_dbg(&hwmon->xe->drm, "thermal data for group %d val 0x%x\n", i, dword[i]);
>>   	}
>>   
>> -	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++)
>> -		average += hwmon->temp.value[i];
>> +	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++) {
>> +		if (is_temp_valid(hwmon, hwmon->temp.value[i])) {
>> +			average += hwmon->temp.value[i];
>> +			count++;
>> +		} else {
>> +			drm_dbg(&hwmon->xe->drm, "mc temp sensor %d not available, val 0x%x\n",
>> +				i, hwmon->temp.value[i]);
>> +		}
>> +	}
>> +
>> +	if (!count) {
>> +		drm_warn(&hwmon->xe->drm, "no memory temp sensors available!\n");
> [Severity: Medium]
> Will this warning be emitted multiple times during device registration?
>
> Because hwmon subsystem core evaluates the is_visible callback multiple times
> per channel, and the logic in xe_hwmon_temp_is_visible() evaluates
> get_mc_temp() first, this warning may trigger excessively if the sensor is
> intentionally absent.

Yes it does.

We can change these messages to |drm_dbg()| to avoid generating 
excessive warnings in such cases.

>> +		return -ENXIO;
>> +	}
>> +
>> +	average /= count;
>> +	if (val)
>> +		*val = average * MILLIDEGREE_PER_DEGREE;
>>   
>> -	average /= (hwmon->temp.count - TEMP_INDEX_MCTRL - 1);
>> -	*val = average * MILLIDEGREE_PER_DEGREE;
>>   	return 0;
>>   }
> [ ... ]
>
>> @@ -932,11 +961,21 @@ static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
>>   	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
>>   	int vram_id = channel - CHANNEL_VRAM_N;
>>   	struct xe_reg vram_reg;
>> +	u32 reg_val;
>> +	u8 temp;
>>   
>>   	vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
>> -	if (!xe_reg_is_valid(vram_reg) || !xe_mmio_read32(mmio, vram_reg))
>> +	if (!xe_reg_is_valid(vram_reg))
>>   		return false;
>>   
>> +	reg_val = xe_mmio_read32(mmio, vram_reg);
>> +	temp = REG_FIELD_GET(TEMP_MASK, reg_val);
> [Severity: High]
> Does this extract the correct bits for the VRAM channel temperature value?
>
> For CHANNEL_VRAM_N, TEMP_MASK extracts bits 7:0, which may represent the
> fractional part of the temperature rather than the integer temperature.
> The integer temperature is typically in bits 31:8 and extracted with
> TEMP_MASK_VRAM_N.
>
> If a valid sensor has a temperature with a 0 fractional part (or 0xFF on newer
> platforms), could it be falsely detected as missing and hidden?
You are right, from VRAM individual channel temperature, we should 
extract with TEMP_MASK_VRAM_N.
>
>> +	if (!is_temp_valid(hwmon, temp)) {
>> +		drm_dbg(&hwmon->xe->drm, "vram channel %d unavailable, val 0x%x\n", vram_id,
>> +			reg_val);
>> +		return false;
>> +	}
>> +
>>   	/* Create label only for available vram channel */
>>   	sprintf(hwmon->temp.vram_label[vram_id], "vram_ch_%d", vram_id);
>>   	return true;
>> @@ -953,8 +992,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>>   		case CHANNEL_VRAM:
>>   			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
> [Severity: Medium]
> Will this expose threshold limit attributes for unavailable sensors?
>
> The input attribute for CHANNEL_PKG and CHANNEL_VRAM is now correctly hidden
> if the sensor returns an unavailable sentinel. However, hwmon_temp_emergency
> and hwmon_temp_crit do not seem to check is_temp_valid() for these channels.
> Could this lead to userspace seeing emergency/crit attributes for sensors
> that don't actually exist?
>
>>   		case CHANNEL_MCTRL:
>> +			return !get_mc_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
Currently, temperature sensor detection is supported only for mailbox 
and per-channel VRAM temperature sensors.
We have requested support from the corresponding team to provide similar 
validity information for package and VRAM temperatures as well.
Once that support becomes available, we can extend the implementation 
accordingly.
> [Severity: Medium]
> Does this execute a synchronous hardware read before checking hwmon->temp.count?
>
> Because this uses !get_mc_temp(hwmon, NULL) && hwmon->temp.count,
> get_mc_temp() is unconditionally executed first due to left-to-right
> evaluation. If temp.count is 0, should the condition short-circuit before
> performing the hardware read by placing the temp.count check first?
>
>>   		case CHANNEL_PCIE:
>> -			return hwmon->temp.count ? 0444 : 0;
>> +			return !get_pcie_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
Agree, I shall change this in next revision.

Re: [PATCH 2/3] drm/xe/hwmon: Use VRAM temperature sensor count from thermal config on CRI

[Poosa, Karthik]

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On 25-08-2026 00:27, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
>
> New issues:
> - [High] VRAM temperature sensors are silently lost on platforms where the thermal mailbox read fails or is unsupported.
> - [High] The dynamic VRAM temperature sensor count feature for CRI is completely non-functional due to missing static attribute definitions and register mappings.
>
> Pre-existing issues:
> - [Medium] The hardware monitoring device is registered directly from the DRM subsystem rather than using an auxiliary device driver.
> --
>
> --- Patch [2]: [PATCH 2/3] drm/xe/hwmon: Use VRAM temperature sensor count from thermal config on CRI ---
> commit ef0f46c26d79ec5ef4b877579a9d69bdbc93ae6c
> Author: Karthik Poosa<karthik.poosa@intel.com>
> Subject: drm/xe/hwmon: Use VRAM temperature sensor count from thermal config on CRI
>
> This patch reads the number of VRAM temperature sensor channels from the
> second byte of READ_THERMAL_CONFIG on CRI platforms. It uses this reported
> count to cap the exposed hwmon attributes for VRAM temperature sensors,
> while retaining the maximum supported channel count for non-CRI platforms.
>
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
>> index c15312b0858ca..8c8a519711230 100644
>> --- a/drivers/gpu/drm/xe/xe_hwmon.c
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> [ ... ]
>
>> @@ -786,6 +790,17 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>>   	drm_dbg(&hwmon->xe->drm, "thermal config count 0x%x\n", config);
>>   	hwmon->temp.count = REG_FIELD_GET(TEMP_MASK, config);
>>   
>> +	if (hwmon->xe->info.platform >= XE_CRESCENTISLAND) {
>> +		hwmon->temp.vram_count = REG_FIELD_GET(VRAM_COUNT_MASK, config);
>> +		if (hwmon->temp.vram_count > MAX_VRAM_CHANNELS && hwmon->temp.vram_count) {
>> +			drm_warn(&hwmon->xe->drm, "VRAM channel count %d exceeds max %d, clamping\n",
>> +				 hwmon->temp.vram_count, MAX_VRAM_CHANNELS);
>> +			hwmon->temp.vram_count = MAX_VRAM_CHANNELS;
>> +		}
> [Severity: High]
> Can the extra sensors on CRI platforms actually be exposed to sysfs?
>
> The HWMON_CHANNEL_INFO(temp, ...) static attribute array doesn't appear
> to be expanded in this patch. Since the static array caps the maximum
> channels visible to sysfs, won't the hwmon core stop querying early
> regardless of the dynamic vram_count value?
Yes, HWMON_CHANNEL_INFO() needs to be increased to accommodate the new 
VRAM channels of CRI.
>
> Also, looking at xe_hwmon_get_reg(), there doesn't seem to be a branch
> for XE_CRESCENTISLAND under the REG_TEMP case. Will is_vram_ch_available()
> receive an invalid register and fail for all VRAM sensors on CRI?
XE_CRESENTISLAND check is there in xe_hwmon_get_reg(), see 
https://gitlab.freedesktop.org/drm/tip/-/blob/drm-tip/drivers/gpu/drm/xe/xe_hwmon.c?ref_type=heads#L269
CRI and BMG share same offsets
>
>> +	} else {
>> +		hwmon->temp.vram_count = 16; /* For older platforms, max is 16 VRAM channels */
>> +	}
>> +
>>   	return ret;
>>   }
> [Severity: High]
> If xe_pcode_read() fails earlier in xe_hwmon_pcode_read_thermal_info(), the
> function returns early. Does this leave hwmon->temp.vram_count uninitialized
> at 0 instead of setting the fallback value of 16?
we shall initialize hwmon->temp.vram_count to 16 before pcode operations 
for this.
>
>> @@ -964,6 +979,9 @@ static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
>>   	u32 reg_val;
>>   	u8 temp;
>>   
>> +	if (vram_id >= hwmon->temp.vram_count)
>> +		return false;
>> +
> [Severity: High]
> If vram_count was left at 0 due to an early return during the pcode read,
> this bounds check will unconditionally return false.
>
> Does this mean a transient pcode error permanently disables all VRAM
> temperature monitoring on older platforms, whereas previously the channels
> were still exposed?
>
> [ ... ]
> same as above
>> @@ -1621,6 +1639,13 @@ int xe_hwmon_register(struct xe_device *xe)
>>   
>>   	xe_hwmon_get_preregistration_info(hwmon);
>>   
>> +	hwmon->temp.vram_label = devm_kcalloc(dev, hwmon->temp.vram_count,
>> +					      MAX_LABEL_SIZE, GFP_KERNEL);
>> +	if (!hwmon->temp.vram_label) {
>> +		xe->hwmon = NULL;
>> +		return -ENOMEM;
>> +	}
>> +
>>   	drm_dbg(&xe->drm, "Register xe hwmon interface\n");
>>   
>>   	/*  hwmon_dev points to device hwmon<i> */
> [Severity: Medium]
> This is a pre-existing issue, but should this hardware monitoring device be
> registered using an auxiliary device driver?
>
> The hwmon subsystem documentation dictates that if the main functionality of
> a chip is not hardware monitoring (such as a DRM controller), its hardware
> monitoring functionality should be implemented as an auxiliary device driver
> in drivers/hwmon/, rather than being registered directly from the DRM
> subsystem.
This is a pre-existing design choice in the Xe driver.
The hwmon device is currently registered directly from the DRM driver,
similar to several other GPU drivers exposing thermal and power 
telemetry through hwmon.

While the hwmon documentation recommends using a separate hwmon driver 
when hardware monitoring is not the primary function of the device,
migrating the existing Xe hwmon implementation to an auxiliary device 
would be a larger architectural change and is outside the scope of this 
series.
This patch set only adds CRI-specific thermal sensor handling on top of 
the existing hwmon infrastructure.


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Re: [PATCH 3/3] drm/xe/hwmon: Correct group selection for memory controller temperature

[Poosa, Karthik]

On 25-08-2026 00:24, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] Out-of-bounds write of 1 byte into `hwmon->temp.value` when reading thermal data from pcode if the sensor count exceeds 252.
> --
>
> --- Patch [3]: [PATCH 3/3] drm/xe/hwmon: Correct group selection for memory controller temperature ---
> commit d6bd40537c53d76ef6df15e33458ad0d982f56b1
> Author: Karthik Poosa <karthik.poosa@intel.com>
>
> drm/xe/hwmon: Correct group selection for memory controller temperature
>      
> This patch corrects the memory controller temperature group selection by
> updating get_mc_temp() to read all necessary groups based on the actual
> sensor count rather than a hardcoded maximum.
>
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
>> --- a/drivers/gpu/drm/xe/xe_hwmon.c
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> [ ... ]
>
>> @@ -820,7 +820,7 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>>   	int ret, i, count = 0;
>>   	s32 average = 0;
>>   
>> -	for (i = 0; i < DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32)); i++) {
>> +	for (i = 0; i < DIV_ROUND_UP(hwmon->temp.count, sizeof(u32)); i++) {
> [Severity: Medium]
> Could this lead to an out-of-bounds write into hwmon->temp.value if the
> hardware returns a sensor count greater than 252?
>
> If hwmon->temp.count is between 253 and 255, the DIV_ROUND_UP calculation
> evaluates to 64. The loop will execute 64 times, reading 4 bytes per
> iteration, resulting in 256 bytes being written to the dword pointer.
>
> Since dword points to hwmon->temp.value, which is sized at 255 bytes, this
> will write past the end of the array by 1 byte.
>
>>   		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
>>   				    (dword + i), NULL);
>>   		if (ret)
> Yes, I shall change the hwmon->temp.value size from U8_MAX to U8_MAX+1 
> @@ -149,7 +149,7 @@ struct xe_hwmon_thermal_info { /** @value: signed 
> value from each sensor */ - s8 value[U8_MAX]; + s8 value[U8_MAX + 1]; };

Re: [PATCH 1/3] drm/xe/hwmon: Detect unavailable temperature sensors

[Nilawar, Badal]

On 25-08-2026 00:11, Karthik Poosa wrote:
> Add is_temp_valid() to validate sensor presence.
> A temperature reading of 0xFF on CRI platforms indicates that the
> corresponding sensor is not present and should be treated as unavailable.
>
> Use this check from xe_hwmon_temp_is_visible() callback so that attributes
> for unavailable sensors are not exposed during hwmon device registration.
>
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_hwmon.c | 79 +++++++++++++++++++++++++++++------
>   1 file changed, 66 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 5284cab6703d..2c4eba4b8f8f 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -813,12 +813,21 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>   	return ret;
>   }
>   
> +static inline bool is_temp_valid(const struct xe_hwmon *hwmon, u8 value)
> +{
> +	/* Value of 0xFF indicates unavailable sensor for platforms from CRI. */
> +	if (hwmon->xe->info.platform >= XE_CRESCENTISLAND)
> +		return value != U8_MAX;
> +	else
> +		return value != 0;

How about returning true here?

> +}
> +
>   static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>   {
>   	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
>   	u32 *dword = (u32 *)hwmon->temp.value;
> +	int ret, i, count = 0;
>   	s32 average = 0;
> -	int ret, i;
>   
>   	for (i = 0; i < DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32)); i++) {
>   		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
> @@ -828,11 +837,25 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>   		drm_dbg(&hwmon->xe->drm, "thermal data for group %d val 0x%x\n", i, dword[i]);
>   	}
>   
> -	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++)
> -		average += hwmon->temp.value[i];
> +	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++) {
> +		if (is_temp_valid(hwmon, hwmon->temp.value[i])) {
> +			average += hwmon->temp.value[i];
> +			count++;
> +		} else {
> +			drm_dbg(&hwmon->xe->drm, "mc temp sensor %d not available, val 0x%x\n",
> +				i, hwmon->temp.value[i]);
Is this required?
> +		}
> +	}
> +
> +	if (!count) {
> +		drm_warn(&hwmon->xe->drm, "no memory temp sensors available!\n");
> +		return -ENXIO;
Why warning? If sensors are not available then its fine. This will any 
way avoid exposing attribute.
> +	}
> +
> +	average /= count;
> +	if (val)
> +		*val = average * MILLIDEGREE_PER_DEGREE;
>   
> -	average /= (hwmon->temp.count - TEMP_INDEX_MCTRL - 1);
> -	*val = average * MILLIDEGREE_PER_DEGREE;
>   	return 0;
>   }
>   
> @@ -852,7 +875,13 @@ static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
>   		data = REG_FIELD_GET(PCIE_SENSOR_MASK, data);
>   
>   	data = REG_FIELD_GET(TEMP_MASK, data);
> -	*val = (s8)data * MILLIDEGREE_PER_DEGREE;
> +	if (!is_temp_valid(hwmon, data)) {
> +		drm_warn(&hwmon->xe->drm, "pcie temp sensor not available, val 0x%x\n", data);
> +		return -ENXIO;
Ditto.
> +	}
> +
> +	if (val)
> +		*val = (s8)data * MILLIDEGREE_PER_DEGREE;
>   
>   	return 0;
>   }
> @@ -956,11 +985,21 @@ static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
>   	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
>   	int vram_id = channel - CHANNEL_VRAM_N;
>   	struct xe_reg vram_reg;
> +	u32 reg_val;
> +	u8 temp;
>   
>   	vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
> -	if (!xe_reg_is_valid(vram_reg) || !xe_mmio_read32(mmio, vram_reg))
> +	if (!xe_reg_is_valid(vram_reg))
>   		return false;
>   
> +	reg_val = xe_mmio_read32(mmio, vram_reg);
> +	temp = REG_FIELD_GET(TEMP_MASK, reg_val);

There is sashiko-bot warning on this. Need to fix.

Thanks,
Badal

> +	if (!is_temp_valid(hwmon, temp)) {
> +		drm_dbg(&hwmon->xe->drm, "vram channel %d unavailable, val 0x%x\n", vram_id,
> +			reg_val);
> +		return false;
> +	}
> +
>   	/* Create label only for available vram channel */
>   	sprintf(hwmon->temp.vram_label[vram_id], "vram_ch_%d", vram_id);
>   	return true;
> @@ -977,8 +1016,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>   		case CHANNEL_VRAM:
>   			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
>   		case CHANNEL_MCTRL:
> +			return !get_mc_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
>   		case CHANNEL_PCIE:
> -			return hwmon->temp.count ? 0444 : 0;
> +			return !get_pcie_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
>   		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
>   			return (is_vram_ch_available(hwmon, channel) &&
>   				hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN]) ? 0444 : 0;
> @@ -992,8 +1032,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>   		case CHANNEL_VRAM:
>   			return hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT] ? 0444 : 0;
>   		case CHANNEL_MCTRL:
> +			return !get_mc_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
>   		case CHANNEL_PCIE:
> -			return hwmon->temp.count ? 0444 : 0;
> +			return !get_pcie_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
>   		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
>   			return (is_vram_ch_available(hwmon, channel) &&
>   				hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT]) ? 0444 : 0;
> @@ -1011,12 +1052,24 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>   	case hwmon_temp_label:
>   		switch (channel) {
>   		case CHANNEL_PKG:
> -		case CHANNEL_VRAM:
> -			return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
> -								channel)) ? 0444 : 0;
> +		case CHANNEL_VRAM: {
> +			struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
> +			struct xe_reg reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
> +			u32 reg_val;
> +			u8 temp;
> +
> +			if (!xe_reg_is_valid(reg))
> +				return 0;
> +
> +			reg_val = xe_mmio_read32(mmio, reg);
> +			temp = REG_FIELD_GET(TEMP_MASK, reg_val);
> +
> +			return is_temp_valid(hwmon, temp) ? 0444 : 0;
> +		}
>   		case CHANNEL_MCTRL:
> +			return !get_mc_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
>   		case CHANNEL_PCIE:
> -			return hwmon->temp.count ? 0444 : 0;
> +			return !get_pcie_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
>   		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
>   			return is_vram_ch_available(hwmon, channel) ? 0444 : 0;
>   		default:

Re: [PATCH 2/3] drm/xe/hwmon: Use VRAM temperature sensor count from thermal config on CRI

[Nilawar, Badal]

On 25-08-2026 00:11, Karthik Poosa wrote:
> Read the number of VRAM temperature sensor channels from the second byte
> of READ_THERMAL_CONFIG on CRI platforms. Use the reported count to avoid
> exposing hwmon attributes for unavailable VRAM temperature sensors, while
> retaining the maximum supported channel count on non-CRI platforms.
>
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_hwmon.c     | 35 ++++++++++++++++++++++++++-----
>   drivers/gpu/drm/xe/xe_pcode_api.h |  1 +
>   2 files changed, 31 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 2c4eba4b8f8f..6e7cb250e628 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -39,7 +39,8 @@ enum xe_hwmon_reg_operation {
>   	REG_READ64,
>   };
>   
> -#define MAX_VRAM_CHANNELS      (16)
> +/* Maximum number of VRAM channels supported by Xe */
> +#define MAX_VRAM_CHANNELS      (80)
>   
>   enum xe_hwmon_channel {
>   	CHANNEL_CARD,
> @@ -48,6 +49,7 @@ enum xe_hwmon_channel {
>   	CHANNEL_MCTRL,
>   	CHANNEL_PCIE,
>   	CHANNEL_VRAM_N,
> +	/* Compile-time upper bound; actual channel count is hwmon->temp.vram_count */
>   	CHANNEL_VRAM_N_MAX = CHANNEL_VRAM_N + MAX_VRAM_CHANNELS - 1,
>   	CHANNEL_MAX,
>   };
> @@ -144,10 +146,12 @@ struct xe_hwmon_thermal_info {
>   	};
>   	/** @count: no of temperature sensors available for the platform */
>   	u8 count;
> +	/** @vram_count: number of VRAM temperature sensors available for the platform */
> +	u8 vram_count;
>   	/** @value: signed value from each sensor */
>   	s8 value[U8_MAX];
> -	/** @vram_label: vram label names */
> -	char vram_label[MAX_VRAM_CHANNELS][MAX_LABEL_SIZE];
> +	/** @vram_label: vram label names, dynamically allocated based on vram_count */
> +	char (*vram_label)[MAX_LABEL_SIZE];
>   };
>   
>   /**
> @@ -271,7 +275,7 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg
>   				return BMG_PACKAGE_TEMPERATURE;
>   			else if (channel == CHANNEL_VRAM)
>   				return BMG_VRAM_TEMPERATURE;
> -			else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
> +			else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count))
>   				return BMG_VRAM_TEMPERATURE_N(channel - CHANNEL_VRAM_N);
>   		} else if (xe->info.platform == XE_DG2) {
>   			if (channel == CHANNEL_PKG)
> @@ -810,6 +814,17 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>   	drm_dbg(&hwmon->xe->drm, "thermal config count 0x%x\n", config);
>   	hwmon->temp.count = REG_FIELD_GET(TEMP_MASK, config);
>   
> +	if (hwmon->xe->info.platform >= XE_CRESCENTISLAND) {
> +		hwmon->temp.vram_count = REG_FIELD_GET(VRAM_COUNT_MASK, config);
> +		if (hwmon->temp.vram_count > MAX_VRAM_CHANNELS && hwmon->temp.vram_count) {
> +			drm_warn(&hwmon->xe->drm, "VRAM channel count %d exceeds max %d, clamping\n",
> +				 hwmon->temp.vram_count, MAX_VRAM_CHANNELS);
> +			hwmon->temp.vram_count = MAX_VRAM_CHANNELS;
> +		}
> +	} else {
> +		hwmon->temp.vram_count = 16; /* For older platforms, max is 16 VRAM channels */

I think better to add #define for this.

Thanks,
Badal

> +	}
> +
>   	return ret;
>   }
>   
> @@ -988,6 +1003,9 @@ static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
>   	u32 reg_val;
>   	u8 temp;
>   
> +	if (vram_id >= hwmon->temp.vram_count)
> +		return false;
> +
>   	vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
>   	if (!xe_reg_is_valid(vram_reg))
>   		return false;
> @@ -1516,7 +1534,7 @@ static int xe_hwmon_read_label(struct device *dev,
>   			*str = "mctrl";
>   		else if (channel == CHANNEL_PCIE)
>   			*str = "pcie";
> -		else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
> +		else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count))
>   			*str = hwmon->temp.vram_label[channel - CHANNEL_VRAM_N];
>   		return 0;
>   	case hwmon_power:
> @@ -1645,6 +1663,13 @@ int xe_hwmon_register(struct xe_device *xe)
>   
>   	xe_hwmon_get_preregistration_info(hwmon);
>   
> +	hwmon->temp.vram_label = devm_kcalloc(dev, hwmon->temp.vram_count,
> +					      MAX_LABEL_SIZE, GFP_KERNEL);
> +	if (!hwmon->temp.vram_label) {
> +		xe->hwmon = NULL;
> +		return -ENOMEM;
> +	}
> +
>   	drm_dbg(&xe->drm, "Register xe hwmon interface\n");
>   
>   	/*  hwmon_dev points to device hwmon<i> */
> diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
> index 94575c476e3d..e1079eff72c6 100644
> --- a/drivers/gpu/drm/xe/xe_pcode_api.h
> +++ b/drivers/gpu/drm/xe/xe_pcode_api.h
> @@ -57,6 +57,7 @@
>   #define   PCODE_THERMAL_INFO			0x25
>   #define     READ_THERMAL_LIMITS			0x0
>   #define     READ_THERMAL_CONFIG			0x1
> +#define       VRAM_COUNT_MASK			REG_GENMASK(15, 8)
>   #define     READ_THERMAL_DATA			0x2
>   #define       PCIE_SENSOR_GROUP_ID		0x2
>   #define       PCIE_SENSOR_MASK			REG_GENMASK(31, 16)

Re: [PATCH 1/3] drm/xe/hwmon: Detect unavailable temperature sensors

[Raag Jadav]

On Tue, Aug 25, 2026 at 12:11:31AM +0530, Karthik Poosa wrote:
> Add is_temp_valid() to validate sensor presence.

Please utilize the full 75 character space where possible.

> A temperature reading of 0xFF on CRI platforms indicates that the
> corresponding sensor is not present and should be treated as unavailable.
> 
> Use this check from xe_hwmon_temp_is_visible() callback so that attributes
> for unavailable sensors are not exposed during hwmon device registration.
> 
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_hwmon.c | 79 +++++++++++++++++++++++++++++------
>  1 file changed, 66 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 5284cab6703d..2c4eba4b8f8f 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -813,12 +813,21 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>  	return ret;
>  }
>  
> +static inline bool is_temp_valid(const struct xe_hwmon *hwmon, u8 value)
> +{
> +	/* Value of 0xFF indicates unavailable sensor for platforms from CRI. */
> +	if (hwmon->xe->info.platform >= XE_CRESCENTISLAND)

Let's not solve a problem that doesn't exist. This kind of checks create
problem in internal repos where the expected platform isn't quite often
the last one. If this is needed for multiple platforms, just add a feature
flag.

> +		return value != U8_MAX;
> +	else

Redundant else.

> +		return value != 0;
> +}
> +
>  static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>  {
>  	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
>  	u32 *dword = (u32 *)hwmon->temp.value;
> +	int ret, i, count = 0;
>  	s32 average = 0;
> -	int ret, i;
>  
>  	for (i = 0; i < DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32)); i++) {
>  		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
> @@ -828,11 +837,25 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>  		drm_dbg(&hwmon->xe->drm, "thermal data for group %d val 0x%x\n", i, dword[i]);
>  	}
>  
> -	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++)
> -		average += hwmon->temp.value[i];
> +	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++) {
> +		if (is_temp_valid(hwmon, hwmon->temp.value[i])) {
> +			average += hwmon->temp.value[i];
> +			count++;
> +		} else {
> +			drm_dbg(&hwmon->xe->drm, "mc temp sensor %d not available, val 0x%x\n",
> +				i, hwmon->temp.value[i]);
> +		}

Rather,

	if (!is_temp_valid())
		continue;
		
	average += ...
	
Tidy? ;)

> +	}
> +
> +	if (!count) {
> +		drm_warn(&hwmon->xe->drm, "no memory temp sensors available!\n");

This is a bit misleading as it is exposed as a single channel to the user.
I'd rephrase this to something like "Memory temperature not available".

> +		return -ENXIO;
> +	}
> +
> +	average /= count;

Blank line please!

> +	if (val)
> +		*val = average * MILLIDEGREE_PER_DEGREE;
>  
> -	average /= (hwmon->temp.count - TEMP_INDEX_MCTRL - 1);
> -	*val = average * MILLIDEGREE_PER_DEGREE;
>  	return 0;
>  }
>  
> @@ -852,7 +875,13 @@ static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
>  		data = REG_FIELD_GET(PCIE_SENSOR_MASK, data);
>  
>  	data = REG_FIELD_GET(TEMP_MASK, data);
> -	*val = (s8)data * MILLIDEGREE_PER_DEGREE;
> +	if (!is_temp_valid(hwmon, data)) {
> +		drm_warn(&hwmon->xe->drm, "pcie temp sensor not available, val 0x%x\n", data);

Same as above, "PCIe temperature not available".
I'm also unsure why do we need to log the value?

> +		return -ENXIO;
> +	}
> +
> +	if (val)
> +		*val = (s8)data * MILLIDEGREE_PER_DEGREE;
>  
>  	return 0;
>  }
> @@ -956,11 +985,21 @@ static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
>  	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
>  	int vram_id = channel - CHANNEL_VRAM_N;
>  	struct xe_reg vram_reg;
> +	u32 reg_val;
> +	u8 temp;
>  
>  	vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
> -	if (!xe_reg_is_valid(vram_reg) || !xe_mmio_read32(mmio, vram_reg))
> +	if (!xe_reg_is_valid(vram_reg))
>  		return false;
>  
> +	reg_val = xe_mmio_read32(mmio, vram_reg);
> +	temp = REG_FIELD_GET(TEMP_MASK, reg_val);
> +	if (!is_temp_valid(hwmon, temp)) {

Hm, see below[1].

> +		drm_dbg(&hwmon->xe->drm, "vram channel %d unavailable, val 0x%x\n", vram_id,
> +			reg_val);
> +		return false;
> +	}
> +
>  	/* Create label only for available vram channel */
>  	sprintf(hwmon->temp.vram_label[vram_id], "vram_ch_%d", vram_id);
>  	return true;
> @@ -977,8 +1016,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  		case CHANNEL_VRAM:
>  			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
>  		case CHANNEL_MCTRL:
> +			return !get_mc_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
>  		case CHANNEL_PCIE:
> -			return hwmon->temp.count ? 0444 : 0;
> +			return !get_pcie_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
>  		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
>  			return (is_vram_ch_available(hwmon, channel) &&
>  				hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN]) ? 0444 : 0;
> @@ -992,8 +1032,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  		case CHANNEL_VRAM:
>  			return hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT] ? 0444 : 0;
>  		case CHANNEL_MCTRL:
> +			return !get_mc_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
>  		case CHANNEL_PCIE:
> -			return hwmon->temp.count ? 0444 : 0;
> +			return !get_pcie_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
>  		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
>  			return (is_vram_ch_available(hwmon, channel) &&
>  				hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT]) ? 0444 : 0;
> @@ -1011,12 +1052,24 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  	case hwmon_temp_label:
>  		switch (channel) {
>  		case CHANNEL_PKG:
> -		case CHANNEL_VRAM:
> -			return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
> -								channel)) ? 0444 : 0;
> +		case CHANNEL_VRAM: {
> +			struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
> +			struct xe_reg reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
> +			u32 reg_val;
> +			u8 temp;
> +
> +			if (!xe_reg_is_valid(reg))
> +				return 0;
> +
> +			reg_val = xe_mmio_read32(mmio, reg);
> +			temp = REG_FIELD_GET(TEMP_MASK, reg_val);
> +
> +			return is_temp_valid(hwmon, temp) ? 0444 : 0;

[1] This looks like something similar to what's happening in
is_vram_ch_available() and can be consolidated into something like
is_vram_temp_valid().

Raag

> +		}
>  		case CHANNEL_MCTRL:
> +			return !get_mc_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
>  		case CHANNEL_PCIE:
> -			return hwmon->temp.count ? 0444 : 0;
> +			return !get_pcie_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
>  		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
>  			return is_vram_ch_available(hwmon, channel) ? 0444 : 0;
>  		default:
> -- 
> 2.25.1
> 

Re: [PATCH 2/3] drm/xe/hwmon: Use VRAM temperature sensor count from thermal config on CRI

[Raag Jadav]

On Tue, Aug 25, 2026 at 12:11:32AM +0530, Karthik Poosa wrote:
> Read the number of VRAM temperature sensor channels from the second byte
> of READ_THERMAL_CONFIG on CRI platforms. Use the reported count to avoid
> exposing hwmon attributes for unavailable VRAM temperature sensors, while
> retaining the maximum supported channel count on non-CRI platforms.
> 
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_hwmon.c     | 35 ++++++++++++++++++++++++++-----
>  drivers/gpu/drm/xe/xe_pcode_api.h |  1 +
>  2 files changed, 31 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 2c4eba4b8f8f..6e7cb250e628 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -39,7 +39,8 @@ enum xe_hwmon_reg_operation {
>  	REG_READ64,
>  };
>  
> -#define MAX_VRAM_CHANNELS      (16)
> +/* Maximum number of VRAM channels supported by Xe */
> +#define MAX_VRAM_CHANNELS      (80)

Why?

>  enum xe_hwmon_channel {
>  	CHANNEL_CARD,
> @@ -48,6 +49,7 @@ enum xe_hwmon_channel {
>  	CHANNEL_MCTRL,
>  	CHANNEL_PCIE,
>  	CHANNEL_VRAM_N,
> +	/* Compile-time upper bound; actual channel count is hwmon->temp.vram_count */
>  	CHANNEL_VRAM_N_MAX = CHANNEL_VRAM_N + MAX_VRAM_CHANNELS - 1,
>  	CHANNEL_MAX,
>  };
> @@ -144,10 +146,12 @@ struct xe_hwmon_thermal_info {
>  	};
>  	/** @count: no of temperature sensors available for the platform */

So now this can be "total number of temperature sensors"?

>  	u8 count;
> +	/** @vram_count: number of VRAM temperature sensors available for the platform */
> +	u8 vram_count;
>  	/** @value: signed value from each sensor */
>  	s8 value[U8_MAX];
> -	/** @vram_label: vram label names */
> -	char vram_label[MAX_VRAM_CHANNELS][MAX_LABEL_SIZE];
> +	/** @vram_label: vram label names, dynamically allocated based on vram_count */
> +	char (*vram_label)[MAX_LABEL_SIZE];
>  };
>  
>  /**
> @@ -271,7 +275,7 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg
>  				return BMG_PACKAGE_TEMPERATURE;
>  			else if (channel == CHANNEL_VRAM)
>  				return BMG_VRAM_TEMPERATURE;
> -			else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
> +			else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count))
>  				return BMG_VRAM_TEMPERATURE_N(channel - CHANNEL_VRAM_N);
>  		} else if (xe->info.platform == XE_DG2) {
>  			if (channel == CHANNEL_PKG)
> @@ -810,6 +814,17 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>  	drm_dbg(&hwmon->xe->drm, "thermal config count 0x%x\n", config);
>  	hwmon->temp.count = REG_FIELD_GET(TEMP_MASK, config);
>  
> +	if (hwmon->xe->info.platform >= XE_CRESCENTISLAND) {

Same as last patch. Don't solve problems that don't exist.

> +		hwmon->temp.vram_count = REG_FIELD_GET(VRAM_COUNT_MASK, config);
> +		if (hwmon->temp.vram_count > MAX_VRAM_CHANNELS && hwmon->temp.vram_count) {

Isn't the first condition sufficient? What am I missing?

> +			drm_warn(&hwmon->xe->drm, "VRAM channel count %d exceeds max %d, clamping\n",

Can this be invalid? i.e. 0xff? And should we clamp it in that case?

> +				 hwmon->temp.vram_count, MAX_VRAM_CHANNELS);
> +			hwmon->temp.vram_count = MAX_VRAM_CHANNELS;

So perhaps CRI_MAX_VRAM_CHANNELS?

> +		}
> +	} else {
> +		hwmon->temp.vram_count = 16; /* For older platforms, max is 16 VRAM channels */

BMG_MAX_VRAM_CHANNELS?

> +	}
> +
>  	return ret;
>  }
>  
> @@ -988,6 +1003,9 @@ static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
>  	u32 reg_val;
>  	u8 temp;
>  
> +	if (vram_id >= hwmon->temp.vram_count)
> +		return false;
> +
>  	vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
>  	if (!xe_reg_is_valid(vram_reg))
>  		return false;
> @@ -1516,7 +1534,7 @@ static int xe_hwmon_read_label(struct device *dev,
>  			*str = "mctrl";
>  		else if (channel == CHANNEL_PCIE)
>  			*str = "pcie";
> -		else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
> +		else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count))
>  			*str = hwmon->temp.vram_label[channel - CHANNEL_VRAM_N];
>  		return 0;
>  	case hwmon_power:
> @@ -1645,6 +1663,13 @@ int xe_hwmon_register(struct xe_device *xe)
>  
>  	xe_hwmon_get_preregistration_info(hwmon);
>  
> +	hwmon->temp.vram_label = devm_kcalloc(dev, hwmon->temp.vram_count,

What if vram_count is 0?

Raag

> +					      MAX_LABEL_SIZE, GFP_KERNEL);
> +	if (!hwmon->temp.vram_label) {
> +		xe->hwmon = NULL;
> +		return -ENOMEM;
> +	}
> +
>  	drm_dbg(&xe->drm, "Register xe hwmon interface\n");
>  
>  	/*  hwmon_dev points to device hwmon<i> */
> diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
> index 94575c476e3d..e1079eff72c6 100644
> --- a/drivers/gpu/drm/xe/xe_pcode_api.h
> +++ b/drivers/gpu/drm/xe/xe_pcode_api.h
> @@ -57,6 +57,7 @@
>  #define   PCODE_THERMAL_INFO			0x25
>  #define     READ_THERMAL_LIMITS			0x0
>  #define     READ_THERMAL_CONFIG			0x1
> +#define       VRAM_COUNT_MASK			REG_GENMASK(15, 8)
>  #define     READ_THERMAL_DATA			0x2
>  #define       PCIE_SENSOR_GROUP_ID		0x2
>  #define       PCIE_SENSOR_MASK			REG_GENMASK(31, 16)
> -- 
> 2.25.1
> 

Re: [PATCH 2/3] drm/xe/hwmon: Use VRAM temperature sensor count from thermal config on CRI

[Rodrigo Vivi]

On Wed, Aug 26, 2026 at 08:19:43PM +0200, Raag Jadav wrote:
> On Tue, Aug 25, 2026 at 12:11:32AM +0530, Karthik Poosa wrote:
> > Read the number of VRAM temperature sensor channels from the second byte
> > of READ_THERMAL_CONFIG on CRI platforms. Use the reported count to avoid
> > exposing hwmon attributes for unavailable VRAM temperature sensors, while
> > retaining the maximum supported channel count on non-CRI platforms.
> > 
> > Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_hwmon.c     | 35 ++++++++++++++++++++++++++-----
> >  drivers/gpu/drm/xe/xe_pcode_api.h |  1 +
> >  2 files changed, 31 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> > index 2c4eba4b8f8f..6e7cb250e628 100644
> > --- a/drivers/gpu/drm/xe/xe_hwmon.c
> > +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> > @@ -39,7 +39,8 @@ enum xe_hwmon_reg_operation {
> >  	REG_READ64,
> >  };
> >  
> > -#define MAX_VRAM_CHANNELS      (16)
> > +/* Maximum number of VRAM channels supported by Xe */
> > +#define MAX_VRAM_CHANNELS      (80)
> 
> Why?

it is used below.

But it should simply be something like this:

#define MAX_VRAM_CHANNELS	16
#define CRI_MAX_VRAM_CHANNELS	80

and both gets used below

> 
> >  enum xe_hwmon_channel {
> >  	CHANNEL_CARD,
> > @@ -48,6 +49,7 @@ enum xe_hwmon_channel {
> >  	CHANNEL_MCTRL,
> >  	CHANNEL_PCIE,
> >  	CHANNEL_VRAM_N,
> > +	/* Compile-time upper bound; actual channel count is hwmon->temp.vram_count */
> >  	CHANNEL_VRAM_N_MAX = CHANNEL_VRAM_N + MAX_VRAM_CHANNELS - 1,
> >  	CHANNEL_MAX,
> >  };
> > @@ -144,10 +146,12 @@ struct xe_hwmon_thermal_info {
> >  	};
> >  	/** @count: no of temperature sensors available for the platform */
> 
> So now this can be "total number of temperature sensors"?
> 
> >  	u8 count;
> > +	/** @vram_count: number of VRAM temperature sensors available for the platform */
> > +	u8 vram_count;
> >  	/** @value: signed value from each sensor */
> >  	s8 value[U8_MAX];
> > -	/** @vram_label: vram label names */
> > -	char vram_label[MAX_VRAM_CHANNELS][MAX_LABEL_SIZE];
> > +	/** @vram_label: vram label names, dynamically allocated based on vram_count */
> > +	char (*vram_label)[MAX_LABEL_SIZE];
> >  };
> >  
> >  /**
> > @@ -271,7 +275,7 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg
> >  				return BMG_PACKAGE_TEMPERATURE;
> >  			else if (channel == CHANNEL_VRAM)
> >  				return BMG_VRAM_TEMPERATURE;
> > -			else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
> > +			else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count))
> >  				return BMG_VRAM_TEMPERATURE_N(channel - CHANNEL_VRAM_N);
> >  		} else if (xe->info.platform == XE_DG2) {
> >  			if (channel == CHANNEL_PKG)
> > @@ -810,6 +814,17 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
> >  	drm_dbg(&hwmon->xe->drm, "thermal config count 0x%x\n", config);
> >  	hwmon->temp.count = REG_FIELD_GET(TEMP_MASK, config);
> >  
> > +	if (hwmon->xe->info.platform >= XE_CRESCENTISLAND) {
> 
> Same as last patch. Don't solve problems that don't exist.
> 
> > +		hwmon->temp.vram_count = REG_FIELD_GET(VRAM_COUNT_MASK, config);
> > +		if (hwmon->temp.vram_count > MAX_VRAM_CHANNELS && hwmon->temp.vram_count) {
> 
> Isn't the first condition sufficient? What am I missing?
> 
> > +			drm_warn(&hwmon->xe->drm, "VRAM channel count %d exceeds max %d, clamping\n",
> 
> Can this be invalid? i.e. 0xff? And should we clamp it in that case?
> 
> > +				 hwmon->temp.vram_count, MAX_VRAM_CHANNELS);
> > +			hwmon->temp.vram_count = MAX_VRAM_CHANNELS;

hwmon->temp.vram_count = CRI_MAX_VRAM_CHANNELS;

> 
> So perhaps CRI_MAX_VRAM_CHANNELS?
> 
> > +		}
> > +	} else {
> > +		hwmon->temp.vram_count = 16; /* For older platforms, max is 16 VRAM channels */
> 
> BMG_MAX_VRAM_CHANNELS?

hwmon->temp.vram_count = MAX_VRAM_CHANNELS;

do not necessarily need to add a prefix to the old one...
just a prefix for the new one...
But if someone's OCD is asking for symmetry then

XE_MAX_VRAM_CHANNELS
or
BMG_MAX_VRAM_CHANNELS

are both accepted options...

> 
> > +	}
> > +
> >  	return ret;
> >  }
> >  
> > @@ -988,6 +1003,9 @@ static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
> >  	u32 reg_val;
> >  	u8 temp;
> >  
> > +	if (vram_id >= hwmon->temp.vram_count)
> > +		return false;
> > +
> >  	vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
> >  	if (!xe_reg_is_valid(vram_reg))
> >  		return false;
> > @@ -1516,7 +1534,7 @@ static int xe_hwmon_read_label(struct device *dev,
> >  			*str = "mctrl";
> >  		else if (channel == CHANNEL_PCIE)
> >  			*str = "pcie";
> > -		else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
> > +		else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count))
> >  			*str = hwmon->temp.vram_label[channel - CHANNEL_VRAM_N];
> >  		return 0;
> >  	case hwmon_power:
> > @@ -1645,6 +1663,13 @@ int xe_hwmon_register(struct xe_device *xe)
> >  
> >  	xe_hwmon_get_preregistration_info(hwmon);
> >  
> > +	hwmon->temp.vram_label = devm_kcalloc(dev, hwmon->temp.vram_count,
> 
> What if vram_count is 0?

then we probably already skipped on the vram_id >= check above no?!
But better to check indeed...

> 
> Raag
> 
> > +					      MAX_LABEL_SIZE, GFP_KERNEL);
> > +	if (!hwmon->temp.vram_label) {
> > +		xe->hwmon = NULL;
> > +		return -ENOMEM;
> > +	}
> > +
> >  	drm_dbg(&xe->drm, "Register xe hwmon interface\n");
> >  
> >  	/*  hwmon_dev points to device hwmon<i> */
> > diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
> > index 94575c476e3d..e1079eff72c6 100644
> > --- a/drivers/gpu/drm/xe/xe_pcode_api.h
> > +++ b/drivers/gpu/drm/xe/xe_pcode_api.h
> > @@ -57,6 +57,7 @@
> >  #define   PCODE_THERMAL_INFO			0x25
> >  #define     READ_THERMAL_LIMITS			0x0
> >  #define     READ_THERMAL_CONFIG			0x1
> > +#define       VRAM_COUNT_MASK			REG_GENMASK(15, 8)
> >  #define     READ_THERMAL_DATA			0x2
> >  #define       PCIE_SENSOR_GROUP_ID		0x2
> >  #define       PCIE_SENSOR_MASK			REG_GENMASK(31, 16)
> > -- 
> > 2.25.1
> > 

Re: [PATCH 1/3] drm/xe/hwmon: Detect unavailable temperature sensors

[Rodrigo Vivi]

On Wed, Aug 26, 2026 at 04:27:15PM +0200, Raag Jadav wrote:
> On Tue, Aug 25, 2026 at 12:11:31AM +0530, Karthik Poosa wrote:
> > Add is_temp_valid() to validate sensor presence.
> 
> Please utilize the full 75 character space where possible.
> 
> > A temperature reading of 0xFF on CRI platforms indicates that the
> > corresponding sensor is not present and should be treated as unavailable.
> > 
> > Use this check from xe_hwmon_temp_is_visible() callback so that attributes
> > for unavailable sensors are not exposed during hwmon device registration.
> > 
> > Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_hwmon.c | 79 +++++++++++++++++++++++++++++------
> >  1 file changed, 66 insertions(+), 13 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> > index 5284cab6703d..2c4eba4b8f8f 100644
> > --- a/drivers/gpu/drm/xe/xe_hwmon.c
> > +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> > @@ -813,12 +813,21 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
> >  	return ret;
> >  }
> >  
> > +static inline bool is_temp_valid(const struct xe_hwmon *hwmon, u8 value)
> > +{
> > +	/* Value of 0xFF indicates unavailable sensor for platforms from CRI. */
> > +	if (hwmon->xe->info.platform >= XE_CRESCENTISLAND)
> 
> Let's not solve a problem that doesn't exist. This kind of checks create
> problem in internal repos where the expected platform isn't quite often
> the last one. If this is needed for multiple platforms, just add a feature
> flag.

Well, I know that sometimes I might be over optimistic about it, but
in general while working with platform enabling I always preferred to
assume that the next platform would be similar and work on the differences
and on the errors than have to hunt all the corner cases that were forgotten
because it was a static if == platform.

We even had a MISSED_CASE macro in i915 for the places that we had a risk
of being different but that would cause trouble later.

That said, I don't have a strong side in here, but it should be easier to
have something like.

> 
> > +		return value != U8_MAX;
> > +	else
> 
> Redundant else.

but on this I agree 100% :)

> 
> > +		return value != 0;
> > +}
> > +
> >  static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
> >  {
> >  	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
> >  	u32 *dword = (u32 *)hwmon->temp.value;
> > +	int ret, i, count = 0;
> >  	s32 average = 0;
> > -	int ret, i;
> >  
> >  	for (i = 0; i < DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32)); i++) {
> >  		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
> > @@ -828,11 +837,25 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
> >  		drm_dbg(&hwmon->xe->drm, "thermal data for group %d val 0x%x\n", i, dword[i]);
> >  	}
> >  
> > -	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++)
> > -		average += hwmon->temp.value[i];
> > +	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++) {
> > +		if (is_temp_valid(hwmon, hwmon->temp.value[i])) {
> > +			average += hwmon->temp.value[i];
> > +			count++;
> > +		} else {
> > +			drm_dbg(&hwmon->xe->drm, "mc temp sensor %d not available, val 0x%x\n",
> > +				i, hwmon->temp.value[i]);
> > +		}
> 
> Rather,
> 
> 	if (!is_temp_valid())
> 		continue;
> 		
> 	average += ...
> 	
> Tidy? ;)
> 
> > +	}
> > +
> > +	if (!count) {
> > +		drm_warn(&hwmon->xe->drm, "no memory temp sensors available!\n");
> 
> This is a bit misleading as it is exposed as a single channel to the user.
> I'd rephrase this to something like "Memory temperature not available".
> 
> > +		return -ENXIO;
> > +	}
> > +
> > +	average /= count;
> 
> Blank line please!
> 
> > +	if (val)
> > +		*val = average * MILLIDEGREE_PER_DEGREE;
> >  
> > -	average /= (hwmon->temp.count - TEMP_INDEX_MCTRL - 1);
> > -	*val = average * MILLIDEGREE_PER_DEGREE;
> >  	return 0;
> >  }
> >  
> > @@ -852,7 +875,13 @@ static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
> >  		data = REG_FIELD_GET(PCIE_SENSOR_MASK, data);
> >  
> >  	data = REG_FIELD_GET(TEMP_MASK, data);
> > -	*val = (s8)data * MILLIDEGREE_PER_DEGREE;
> > +	if (!is_temp_valid(hwmon, data)) {
> > +		drm_warn(&hwmon->xe->drm, "pcie temp sensor not available, val 0x%x\n", data);
> 
> Same as above, "PCIe temperature not available".
> I'm also unsure why do we need to log the value?
> 
> > +		return -ENXIO;
> > +	}
> > +
> > +	if (val)
> > +		*val = (s8)data * MILLIDEGREE_PER_DEGREE;
> >  
> >  	return 0;
> >  }
> > @@ -956,11 +985,21 @@ static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
> >  	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
> >  	int vram_id = channel - CHANNEL_VRAM_N;
> >  	struct xe_reg vram_reg;
> > +	u32 reg_val;
> > +	u8 temp;
> >  
> >  	vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
> > -	if (!xe_reg_is_valid(vram_reg) || !xe_mmio_read32(mmio, vram_reg))
> > +	if (!xe_reg_is_valid(vram_reg))
> >  		return false;
> >  
> > +	reg_val = xe_mmio_read32(mmio, vram_reg);
> > +	temp = REG_FIELD_GET(TEMP_MASK, reg_val);
> > +	if (!is_temp_valid(hwmon, temp)) {
> 
> Hm, see below[1].
> 
> > +		drm_dbg(&hwmon->xe->drm, "vram channel %d unavailable, val 0x%x\n", vram_id,
> > +			reg_val);
> > +		return false;
> > +	}
> > +
> >  	/* Create label only for available vram channel */
> >  	sprintf(hwmon->temp.vram_label[vram_id], "vram_ch_%d", vram_id);
> >  	return true;
> > @@ -977,8 +1016,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
> >  		case CHANNEL_VRAM:
> >  			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
> >  		case CHANNEL_MCTRL:
> > +			return !get_mc_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
> >  		case CHANNEL_PCIE:
> > -			return hwmon->temp.count ? 0444 : 0;
> > +			return !get_pcie_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
> >  		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
> >  			return (is_vram_ch_available(hwmon, channel) &&
> >  				hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN]) ? 0444 : 0;
> > @@ -992,8 +1032,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
> >  		case CHANNEL_VRAM:
> >  			return hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT] ? 0444 : 0;
> >  		case CHANNEL_MCTRL:
> > +			return !get_mc_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
> >  		case CHANNEL_PCIE:
> > -			return hwmon->temp.count ? 0444 : 0;
> > +			return !get_pcie_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
> >  		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
> >  			return (is_vram_ch_available(hwmon, channel) &&
> >  				hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT]) ? 0444 : 0;
> > @@ -1011,12 +1052,24 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
> >  	case hwmon_temp_label:
> >  		switch (channel) {
> >  		case CHANNEL_PKG:
> > -		case CHANNEL_VRAM:
> > -			return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
> > -								channel)) ? 0444 : 0;
> > +		case CHANNEL_VRAM: {
> > +			struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
> > +			struct xe_reg reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
> > +			u32 reg_val;
> > +			u8 temp;
> > +
> > +			if (!xe_reg_is_valid(reg))
> > +				return 0;
> > +
> > +			reg_val = xe_mmio_read32(mmio, reg);
> > +			temp = REG_FIELD_GET(TEMP_MASK, reg_val);
> > +
> > +			return is_temp_valid(hwmon, temp) ? 0444 : 0;
> 
> [1] This looks like something similar to what's happening in
> is_vram_ch_available() and can be consolidated into something like
> is_vram_temp_valid().
> 
> Raag
> 
> > +		}
> >  		case CHANNEL_MCTRL:
> > +			return !get_mc_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
> >  		case CHANNEL_PCIE:
> > -			return hwmon->temp.count ? 0444 : 0;
> > +			return !get_pcie_temp(hwmon, NULL) && hwmon->temp.count ? 0444 : 0;
> >  		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
> >  			return is_vram_ch_available(hwmon, channel) ? 0444 : 0;
> >  		default:
> > -- 
> > 2.25.1
> > 

Re: [PATCH 1/3] drm/xe/hwmon: Detect unavailable temperature sensors

[Poosa, Karthik]

On 26-08-2026 17:20, Nilawar, Badal wrote:
>
> On 25-08-2026 00:11, Karthik Poosa wrote:
>> Add is_temp_valid() to validate sensor presence.
>> A temperature reading of 0xFF on CRI platforms indicates that the
>> corresponding sensor is not present and should be treated as 
>> unavailable.
>>
>> Use this check from xe_hwmon_temp_is_visible() callback so that 
>> attributes
>> for unavailable sensors are not exposed during hwmon device 
>> registration.
>>
>> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
>> ---
>>   drivers/gpu/drm/xe/xe_hwmon.c | 79 +++++++++++++++++++++++++++++------
>>   1 file changed, 66 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c 
>> b/drivers/gpu/drm/xe/xe_hwmon.c
>> index 5284cab6703d..2c4eba4b8f8f 100644
>> --- a/drivers/gpu/drm/xe/xe_hwmon.c
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
>> @@ -813,12 +813,21 @@ static int 
>> xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>>       return ret;
>>   }
>>   +static inline bool is_temp_valid(const struct xe_hwmon *hwmon, u8 
>> value)
>> +{
>> +    /* Value of 0xFF indicates unavailable sensor for platforms from 
>> CRI. */
>> +    if (hwmon->xe->info.platform >= XE_CRESCENTISLAND)
>> +        return value != U8_MAX;
>> +    else
>> +        return value != 0;
>
> How about returning true here?
for BMG value 0 will be there if temperature sensor is not there, which 
is why we are checking this way.
>
>> +}
>> +
>>   static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>>   {
>>       struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
>>       u32 *dword = (u32 *)hwmon->temp.value;
>> +    int ret, i, count = 0;
>>       s32 average = 0;
>> -    int ret, i;
>>         for (i = 0; i < DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32)); 
>> i++) {
>>           ret = xe_pcode_read(root_tile, 
>> PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
>> @@ -828,11 +837,25 @@ static int get_mc_temp(struct xe_hwmon *hwmon, 
>> long *val)
>>           drm_dbg(&hwmon->xe->drm, "thermal data for group %d val 
>> 0x%x\n", i, dword[i]);
>>       }
>>   -    for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++)
>> -        average += hwmon->temp.value[i];
>> +    for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++) {
>> +        if (is_temp_valid(hwmon, hwmon->temp.value[i])) {
>> +            average += hwmon->temp.value[i];
>> +            count++;
>> +        } else {
>> +            drm_dbg(&hwmon->xe->drm, "mc temp sensor %d not 
>> available, val 0x%x\n",
>> +                i, hwmon->temp.value[i]);
> Is this required?
i think we can have this debug log to know which memory controller 
channel is available, of the available count
>> +        }
>> +    }
>> +
>> +    if (!count) {
>> +        drm_warn(&hwmon->xe->drm, "no memory temp sensors 
>> available!\n");
>> +        return -ENXIO;
> Why warning? If sensors are not available then its fine. This will any 
> way avoid exposing attribute.
agree, sashiko also pointed to that, removing this is in next revision
>> +    }
>> +
>> +    average /= count;
>> +    if (val)
>> +        *val = average * MILLIDEGREE_PER_DEGREE;
>>   -    average /= (hwmon->temp.count - TEMP_INDEX_MCTRL - 1);
>> -    *val = average * MILLIDEGREE_PER_DEGREE;
>>       return 0;
>>   }
>>   @@ -852,7 +875,13 @@ static int get_pcie_temp(struct xe_hwmon 
>> *hwmon, long *val)
>>           data = REG_FIELD_GET(PCIE_SENSOR_MASK, data);
>>         data = REG_FIELD_GET(TEMP_MASK, data);
>> -    *val = (s8)data * MILLIDEGREE_PER_DEGREE;
>> +    if (!is_temp_valid(hwmon, data)) {
>> +        drm_warn(&hwmon->xe->drm, "pcie temp sensor not available, 
>> val 0x%x\n", data);
>> +        return -ENXIO;
> Ditto.
I shall remove this.
>> +    }
>> +
>> +    if (val)
>> +        *val = (s8)data * MILLIDEGREE_PER_DEGREE;
>>         return 0;
>>   }
>> @@ -956,11 +985,21 @@ static inline bool is_vram_ch_available(struct 
>> xe_hwmon *hwmon, int channel)
>>       struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
>>       int vram_id = channel - CHANNEL_VRAM_N;
>>       struct xe_reg vram_reg;
>> +    u32 reg_val;
>> +    u8 temp;
>>         vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
>> -    if (!xe_reg_is_valid(vram_reg) || !xe_mmio_read32(mmio, vram_reg))
>> +    if (!xe_reg_is_valid(vram_reg))
>>           return false;
>>   +    reg_val = xe_mmio_read32(mmio, vram_reg);
>> +    temp = REG_FIELD_GET(TEMP_MASK, reg_val);
>
> There is sashiko-bot warning on this. Need to fix.
>
> Thanks,
> Badal
agree, next revision will have the fix.
>
>> +    if (!is_temp_valid(hwmon, temp)) {
>> +        drm_dbg(&hwmon->xe->drm, "vram channel %d unavailable, val 
>> 0x%x\n", vram_id,
>> +            reg_val);
>> +        return false;
>> +    }
>> +
>>       /* Create label only for available vram channel */
>>       sprintf(hwmon->temp.vram_label[vram_id], "vram_ch_%d", vram_id);
>>       return true;
>> @@ -977,8 +1016,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, 
>> u32 attr, int channel)
>>           case CHANNEL_VRAM:
>>               return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 
>> 0444 : 0;
>>           case CHANNEL_MCTRL:
>> +            return !get_mc_temp(hwmon, NULL) && hwmon->temp.count ? 
>> 0444 : 0;
>>           case CHANNEL_PCIE:
>> -            return hwmon->temp.count ? 0444 : 0;
>> +            return !get_pcie_temp(hwmon, NULL) && hwmon->temp.count 
>> ? 0444 : 0;
>>           case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
>>               return (is_vram_ch_available(hwmon, channel) &&
>>                   hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN]) ? 0444 
>> : 0;
>> @@ -992,8 +1032,9 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, 
>> u32 attr, int channel)
>>           case CHANNEL_VRAM:
>>               return hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT] ? 0444 : 0;
>>           case CHANNEL_MCTRL:
>> +            return !get_mc_temp(hwmon, NULL) && hwmon->temp.count ? 
>> 0444 : 0;
>>           case CHANNEL_PCIE:
>> -            return hwmon->temp.count ? 0444 : 0;
>> +            return !get_pcie_temp(hwmon, NULL) && hwmon->temp.count 
>> ? 0444 : 0;
>>           case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
>>               return (is_vram_ch_available(hwmon, channel) &&
>>                   hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT]) ? 0444 : 0;
>> @@ -1011,12 +1052,24 @@ xe_hwmon_temp_is_visible(struct xe_hwmon 
>> *hwmon, u32 attr, int channel)
>>       case hwmon_temp_label:
>>           switch (channel) {
>>           case CHANNEL_PKG:
>> -        case CHANNEL_VRAM:
>> -            return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
>> -                                channel)) ? 0444 : 0;
>> +        case CHANNEL_VRAM: {
>> +            struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
>> +            struct xe_reg reg = xe_hwmon_get_reg(hwmon, REG_TEMP, 
>> channel);
>> +            u32 reg_val;
>> +            u8 temp;
>> +
>> +            if (!xe_reg_is_valid(reg))
>> +                return 0;
>> +
>> +            reg_val = xe_mmio_read32(mmio, reg);
>> +            temp = REG_FIELD_GET(TEMP_MASK, reg_val);
>> +
>> +            return is_temp_valid(hwmon, temp) ? 0444 : 0;
>> +        }
>>           case CHANNEL_MCTRL:
>> +            return !get_mc_temp(hwmon, NULL) && hwmon->temp.count ? 
>> 0444 : 0;
>>           case CHANNEL_PCIE:
>> -            return hwmon->temp.count ? 0444 : 0;
>> +            return !get_pcie_temp(hwmon, NULL) && hwmon->temp.count 
>> ? 0444 : 0;
>>           case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
>>               return is_vram_ch_available(hwmon, channel) ? 0444 : 0;
>>           default: