From: Raag Jadav <raag.jadav@intel.com>
To: Badal Nilawar <badal.nilawar@intel.com>
Cc: intel-xe@lists.freedesktop.org, anshuman.gupta@intel.com,
rodrigo.vivi@intel.com, daniele.ceraolospurio@intel.com,
riana.tauro@intel.com, mallesh.koujalagi@intel.com,
aravind.iddamsetty@intel.com, himal.prasad.ghimiray@intel.com,
arvind.yadav@intel.com, syed.abdul.muqthyar.ahmed@intel.com,
nitin.r.gote@intel.com
Subject: Re: [PATCH v6 09/10] drm/xe/xe_ras: Report soc internal errors using SIGID
Date: Wed, 28 Oct 2026 18:17:10 +0100 [thread overview]
Message-ID: <auIuFsYCyl5m2mrG@black.igk.intel.com> (raw)
In-Reply-To: <20261028095723.734387-21-badal.nilawar@intel.com>
On Wed, Oct 28, 2026 at 03:27:33PM +0530, Badal Nilawar wrote:
> Use xe_log_* helpers to report soc internal errors.
>
> Example:
> xe 0000:03:00.0: [drm] *ERROR* SIGID=205 FATAL
> (020600700000000000000000) [Hardware Error]: SOC_INTERNAL:
> PUNIT error detected: 0x00000002
>
> Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> Cc: Riana Tauro <riana.tauro@intel.com>
> ---
> v6:
> - Print entire xe_ras_soc_error_source for unknown errors (Raag)
> v5:
> - Log unknown soc internal errors
> ---
> drivers/gpu/drm/xe/xe_ras.c | 17 ++++++++++-------
> 1 file changed, 10 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index d7789beb2f6f..5eeccc920d7c 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -609,7 +609,7 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
> {
> struct xe_ras_soc_error *info = (void *)arr->details;
> struct xe_ras_soc_error_source *source = &info->source;
> - struct xe_ras_error_class *counter = &arr->counter;
> + u32 raw_source;
BUILD_BUG_ON(sizeof(raw_source) != sizeof(*source));
> if (source->csc) {
> struct xe_ras_csc_error *csc_error = (void *)info->details;
> @@ -623,9 +623,8 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
> * is required.
> */
> if (csc_error->hec_fw_error) {
> - xe_err(xe, "[RAS]: CSC %s detected: 0x%x\n",
> - sev_to_str(counter->common.severity),
> - csc_error->hec_fw_error);
> + xe_log_comp_fatal(xe, SOC_INTERNAL, &arr->counter, sizeof(arr->counter),
> + "CSC error detected: 0x%08x\n", csc_error->hec_fw_error);
> xe_survivability_mode_runtime_enable(xe);
> return XE_RAS_RECOVERY_ACTION_DISCONNECT;
> }
> @@ -633,15 +632,19 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
> struct xe_ras_ieh_error *ieh_error = (void *)info->details;
>
> if (ieh_error->global_error_status & XE_RAS_SOC_IEH_PUNIT) {
> - xe_err(xe, "[RAS]: PUNIT %s detected: 0x%x\n",
> - sev_to_str(counter->common.severity),
> - ieh_error->global_error_status);
> + xe_log_comp_fatal(xe, SOC_INTERNAL, &arr->counter, sizeof(arr->counter),
> + "PUNIT error detected: 0x%08x\n",
> + ieh_error->global_error_status);
> punit_error_handler(xe);
> return XE_RAS_RECOVERY_ACTION_DISCONNECT;
> }
> }
>
> /* For other SoC internal errors, request a reset as recovery mechanism */
> + memcpy(&raw_source, source, sizeof(raw_source));
> + xe_log_comp(xe, ras_sev_to_cper_sev(arr->counter.common.severity), SOC_INTERNAL,
> + &arr->counter, sizeof(arr->counter),
> + "Unknown error detected (source=0x%08x)\n", raw_source);
The logs are already too busy with all the parentheses. Rather,
make this consistent with CSC and PUNIT error format, i.e.
"Unknown error detected: 0x%08x\n"
Raag
> return XE_RAS_RECOVERY_ACTION_RESET;
> }
>
> --
> 2.56.0
>
next prev parent reply other threads:[~2026-10-28 17:17 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-28 9:57 [PATCH v6 00/10] Add CPER logging support for CRI Badal Nilawar
2026-10-28 9:57 ` [PATCH v6 01/10] drm/xe/cper: Add CPER reporting entry point for xe_log Badal Nilawar
2026-10-28 16:22 ` Raag Jadav
2026-10-28 9:57 ` [PATCH v6 02/10] drm/xe/cper: Retrieve the error counter record for CPER reporting Badal Nilawar
2026-10-28 16:25 ` Raag Jadav
2026-10-28 9:57 ` [PATCH v6 03/10] drm/xe/cper: Initialize Intel-specific CPER header Badal Nilawar
2026-10-28 16:34 ` Raag Jadav
2026-10-28 9:57 ` [PATCH v6 04/10] drm/xe/cper: Construct CPER record for hardware errors Badal Nilawar
2026-10-28 16:52 ` Raag Jadav
2026-10-28 9:57 ` [PATCH v6 05/10] drm/xe/cper: Log CPER records for aggregate counter retrieval Badal Nilawar
2026-10-28 10:30 ` sashiko-bot
2026-10-28 17:05 ` Raag Jadav
2026-10-28 9:57 ` [PATCH v6 06/10] drm/xe/cper: Emit cper record to trace buf Badal Nilawar
2026-10-28 17:06 ` Raag Jadav
2026-10-28 9:57 ` [PATCH v6 07/10] drm/xe/xe_ras: Report device memory errors using SIGID Badal Nilawar
2026-10-28 17:07 ` Raag Jadav
2026-10-28 9:57 ` [PATCH v6 08/10] drm/xe/xe_ras: Report core compute " Badal Nilawar
2026-10-28 9:57 ` [PATCH v6 09/10] drm/xe/xe_ras: Report soc internal " Badal Nilawar
2026-10-28 17:17 ` Raag Jadav [this message]
2026-10-28 9:57 ` [PATCH v6 10/10] drm/xe/xe_ras: Report correctable " Badal Nilawar
2026-10-28 10:05 ` ✗ CI.checkpatch: warning for Add CPER logging support for CRI (rev6) Patchwork
2026-10-28 10:07 ` ✓ CI.KUnit: success " Patchwork
2026-10-28 10:43 ` ✓ Xe.CI.BAT: " Patchwork
2026-10-28 18:37 ` ✓ Xe.CI.FULL: " Patchwork
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