[PATCH v2 0/8] DP-HDMI PCON DSC fixes

[PATCH v2 0/8] DP-HDMI PCON DSC fixes

[Ankit Nautiyal]

The PCON mode_valid path currently does not fully account for the bandwidth
limitations of the PCON <-> HDMI link. The DSC capability between the
PCON and the HDMI sink also needs to be taken into account, which currently
isn't. Furthermore, the compressed bpp chosen needs to fit the
FRL configuration, which is also missing.

This series:
 - reworks the HDMI DSC helpers so they can be reused across the
   mode_valid, compute_config and FRL bandwidth check paths
 - fixes the FRL/TMDS downstream bandwidth checks, and allows
   PCON DSC modes through the FRL check
 - Clamps the programmed DSC bpp to the FRL link bandwidth.

Rev2:
 - Rebase and address comments from Suraj.
 - Drop drm/i915/dp: Use FRL pair check for the DFP dotclock limit as no
   longer required.

Ankit Nautiyal (8):
  drm/i915/hdmi: Split the intel_hdmi_dsc_get_bpp()
  drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP
  drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints
  drm/i915/dp: Use the common downstream bw check in compute_bpc
  drm/i915/hdmi: Expose DSC min/max bpp helpers
  drm/i915/hdmi: Add helper to check if DSC chunksize fits the sink
    limits
  drm/i915/dp: Allow PCON DSC modes through FRL bw check
  drm/i915/dp: Clamp PCON DSC bpp to the FRL link bandwidth

 drivers/gpu/drm/i915/display/intel_dp.c   | 144 ++++++++++++++++++----
 drivers/gpu/drm/i915/display/intel_hdmi.c | 124 ++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_hdmi.h |   7 +-
 3 files changed, 218 insertions(+), 57 deletions(-)

-- 
2.50.1

[PATCH v2 1/8] drm/i915/hdmi: Split the intel_hdmi_dsc_get_bpp()

[Ankit Nautiyal]

Split the intel_hdmi_dsc_get_bpp() into two helper functions
that can be called independently.

While at it, improve the comments in the helper.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 97 ++++++++++++++---------
 1 file changed, 59 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 9b637e38a1a5..df88d7c141f7 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3325,61 +3325,49 @@ intel_hdmi_dsc_get_num_slices(const struct drm_display_mode *mode,
 	return target_slices;
 }
 
-/*
- * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
- * source and sink capabilities.
- *
- * @src_fraction_bpp: fractional bpp supported by the source
- * @slice_width: dsc slice width supported by the source and sink
- * @num_slices: num of slices supported by the source and sink
- * @output_format: video output format
- * @bpc: bits per color
- * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
- * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
- *
- * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
- */
-int
-intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
-		       enum intel_output_format output_format, int bpc,
-		       bool hdmi_all_bpp, int hdmi_max_chunk_bytes)
+static void
+get_dsc_min_max_bpp(enum intel_output_format output_format, u8 bpc,
+		    bool hdmi_all_bpp, int *min_dsc_bpp, int *max_dsc_bpp)
 {
-	int max_dsc_bpp, min_dsc_bpp;
-	int target_bytes;
-	bool bpp_found = false;
-	int bpp_decrement_x16;
-	int bpp_target;
-	int bpp_target_x16;
-
 	/*
-	 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
+	 * Get min bpp and max bpp that can be supported for a
+	 * given bpc and output format.
 	 * Start with the max bpp and keep on decrementing with
-	 * fractional bpp, if supported by PCON DSC encoder
+	 * fractional bpp, if supported by the DSC encoder
 	 *
 	 * for each bpp we check if no of bytes can be supported by HDMI sink
 	 */
 
 	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
-		min_dsc_bpp = 6;
-		max_dsc_bpp = 3 * bpc / 2;
+		*min_dsc_bpp = 6;
+		*max_dsc_bpp = 3 * bpc / 2;
 	} else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
 		   output_format == INTEL_OUTPUT_FORMAT_RGB) {
-		min_dsc_bpp = 8;
-		max_dsc_bpp = 3 * bpc;
+		*min_dsc_bpp = 8;
+		*max_dsc_bpp = 3 * bpc;
 	} else {
 		/* Assuming 4:2:2 encoding */
-		min_dsc_bpp = 7;
-		max_dsc_bpp = 2 * bpc;
+		*min_dsc_bpp = 7;
+		*max_dsc_bpp = 2 * bpc;
 	}
 
 	/*
-	 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
-	 * Section 7.7.34 : Source shall not enable compressed Video
-	 * Transport with bpp_target settings above 12 bpp unless
-	 * DSC_all_bpp is set to 1.
+	 * Don't enable DSC bpp_target settings above 12 bpp,
+	 * unless DSC_all_bpp is set to 1.
 	 */
 	if (!hdmi_all_bpp)
-		max_dsc_bpp = min(max_dsc_bpp, 12);
+		*max_dsc_bpp = min(*max_dsc_bpp, 12);
+}
+
+static int
+get_dsc_compressed_bpp(int num_slices, int slice_width, int hdmi_max_chunk_bytes,
+		       int src_fractional_bpp, int min_dsc_bpp, int max_dsc_bpp)
+{
+	int target_bytes;
+	bool bpp_found = false;
+	int bpp_decrement_x16;
+	int bpp_target;
+	int bpp_target_x16;
 
 	/*
 	 * The Sink has a limit of compressed data in bytes for a scanline,
@@ -3423,6 +3411,39 @@ intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
 	return 0;
 }
 
+/*
+ * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
+ * source and sink capabilities.
+ *
+ * @src_fraction_bpp: fractional bpp supported by the source
+ * @slice_width: dsc slice width supported by the source and sink
+ * @num_slices: num of slices supported by the source and sink
+ * @output_format: video output format
+ * @bpc: bits per color
+ * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
+ * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
+ *
+ * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
+ */
+int
+intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
+		       enum intel_output_format output_format, int bpc,
+		       bool hdmi_all_bpp, int hdmi_max_chunk_bytes)
+{
+	int max_dsc_bpp, min_dsc_bpp;
+	int dsc_bpp_x16;
+
+	get_dsc_min_max_bpp(output_format, bpc, hdmi_all_bpp,
+			    &min_dsc_bpp, &max_dsc_bpp);
+
+	dsc_bpp_x16 = get_dsc_compressed_bpp(num_slices, slice_width,
+					     hdmi_max_chunk_bytes,
+					     src_fractional_bpp,
+					     min_dsc_bpp, max_dsc_bpp);
+
+	return dsc_bpp_x16;
+}
+
 int intel_hdmi_sink_max_frl_rate(struct drm_connector *connector)
 {
 	int max_lanes = connector->display_info.hdmi.max_lanes;
-- 
2.50.1

RE: [PATCH v2 1/8] drm/i915/hdmi: Split the intel_hdmi_dsc_get_bpp()

[Kandpal, Suraj]

> Subject: [PATCH v2 1/8] drm/i915/hdmi: Split the intel_hdmi_dsc_get_bpp()
> 
> Split the intel_hdmi_dsc_get_bpp() into two helper functions that can be called
> independently.
> 
> While at it, improve the comments in the helper.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_hdmi.c | 97 ++++++++++++++---------
>  1 file changed, 59 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 9b637e38a1a5..df88d7c141f7 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -3325,61 +3325,49 @@ intel_hdmi_dsc_get_num_slices(const struct
> drm_display_mode *mode,
>  	return target_slices;
>  }
> 
> -/*
> - * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel
> based on
> - * source and sink capabilities.
> - *
> - * @src_fraction_bpp: fractional bpp supported by the source
> - * @slice_width: dsc slice width supported by the source and sink
> - * @num_slices: num of slices supported by the source and sink
> - * @output_format: video output format
> - * @bpc: bits per color
> - * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
> - * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
> - *
> - * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
> - */
> -int
> -intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
> -		       enum intel_output_format output_format, int bpc,
> -		       bool hdmi_all_bpp, int hdmi_max_chunk_bytes)
> +static void
> +get_dsc_min_max_bpp(enum intel_output_format output_format, u8 bpc,
> +		    bool hdmi_all_bpp, int *min_dsc_bpp, int *max_dsc_bpp)
>  {
> -	int max_dsc_bpp, min_dsc_bpp;
> -	int target_bytes;
> -	bool bpp_found = false;
> -	int bpp_decrement_x16;
> -	int bpp_target;
> -	int bpp_target_x16;
> -
>  	/*
> -	 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
> +	 * Get min bpp and max bpp that can be supported for a
> +	 * given bpc and output format.
>  	 * Start with the max bpp and keep on decrementing with
> -	 * fractional bpp, if supported by PCON DSC encoder
> +	 * fractional bpp, if supported by the DSC encoder
>  	 *
>  	 * for each bpp we check if no of bytes can be supported by HDMI sink
>  	 */
> 
>  	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
> -		min_dsc_bpp = 6;
> -		max_dsc_bpp = 3 * bpc / 2;
> +		*min_dsc_bpp = 6;
> +		*max_dsc_bpp = 3 * bpc / 2;
>  	} else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
>  		   output_format == INTEL_OUTPUT_FORMAT_RGB) {
> -		min_dsc_bpp = 8;
> -		max_dsc_bpp = 3 * bpc;
> +		*min_dsc_bpp = 8;
> +		*max_dsc_bpp = 3 * bpc;
>  	} else {
>  		/* Assuming 4:2:2 encoding */
> -		min_dsc_bpp = 7;
> -		max_dsc_bpp = 2 * bpc;
> +		*min_dsc_bpp = 7;
> +		*max_dsc_bpp = 2 * bpc;
>  	}
> 
>  	/*
> -	 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
> -	 * Section 7.7.34 : Source shall not enable compressed Video
> -	 * Transport with bpp_target settings above 12 bpp unless
> -	 * DSC_all_bpp is set to 1.
> +	 * Don't enable DSC bpp_target settings above 12 bpp,
> +	 * unless DSC_all_bpp is set to 1.
>  	 */
>  	if (!hdmi_all_bpp)
> -		max_dsc_bpp = min(max_dsc_bpp, 12);
> +		*max_dsc_bpp = min(*max_dsc_bpp, 12); }
> +
> +static int
> +get_dsc_compressed_bpp(int num_slices, int slice_width, int
> hdmi_max_chunk_bytes,
> +		       int src_fractional_bpp, int min_dsc_bpp, int max_dsc_bpp)
> {
> +	int target_bytes;
> +	bool bpp_found = false;
> +	int bpp_decrement_x16;
> +	int bpp_target;
> +	int bpp_target_x16;
> 
>  	/*
>  	 * The Sink has a limit of compressed data in bytes for a scanline, @@ -
> 3423,6 +3411,39 @@ intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int
> slice_width, int num_slices,
>  	return 0;
>  }
> 
> +/*
> + * intel_hdmi_dsc_get_bpp - get the appropriate compressed
> +bits_per_pixel based on
> + * source and sink capabilities.
> + *
> + * @src_fraction_bpp: fractional bpp supported by the source
> + * @slice_width: dsc slice width supported by the source and sink
> + * @num_slices: num of slices supported by the source and sink
> + * @output_format: video output format
> + * @bpc: bits per color
> + * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
> + * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by
> +sink
> + *
> + * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
> +*/ int intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width,
> +int num_slices,
> +		       enum intel_output_format output_format, int bpc,
> +		       bool hdmi_all_bpp, int hdmi_max_chunk_bytes) {
> +	int max_dsc_bpp, min_dsc_bpp;
> +	int dsc_bpp_x16;
> +
> +	get_dsc_min_max_bpp(output_format, bpc, hdmi_all_bpp,
> +			    &min_dsc_bpp, &max_dsc_bpp);
> +
> +	dsc_bpp_x16 = get_dsc_compressed_bpp(num_slices, slice_width,
> +					     hdmi_max_chunk_bytes,
> +					     src_fractional_bpp,
> +					     min_dsc_bpp, max_dsc_bpp);
> +
> +	return dsc_bpp_x16;
> +}
> +
>  int intel_hdmi_sink_max_frl_rate(struct drm_connector *connector)  {
>  	int max_lanes = connector->display_info.hdmi.max_lanes;
> --
> 2.50.1

[PATCH v2 2/8] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP

[Ankit Nautiyal]

The FRL bandwidth check considers only the PCON's max FRL rate, ignoring
the HDMI2.1 sink's own max FRL rate. Cap the available bandwidth by the
minimum of the two, similar to the TMDS case.

Move the check into a helper intel_dp_frl_bw_valid() so it can also be
used in the compute_config phase in a subsequent change.

The DSC case, where both the PCON and HDMI sink support DSC, is left
as a FIXME and handled later.

v2: Remove extra braces and re-format comment. (Suraj)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 51 ++++++++++++++++---------
 1 file changed, 34 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 437b9e7bb864..dd706f7de62d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -124,6 +124,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
 }
 
 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
+static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp);
 
 /* Is link rate UHBR and thus 128b/132b? */
 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
@@ -1179,30 +1180,46 @@ static int frl_required_bw(int clock, int bpc,
 }
 
 static enum drm_mode_status
-intel_dp_mode_valid_downstream(struct intel_connector *connector,
-			       const struct drm_display_mode *mode,
-			       int target_clock,
-			       enum intel_output_format sink_format)
+intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock,
+		      int bpc, enum intel_output_format sink_format,
+		      bool respect_downstream_limits)
 {
-	struct intel_dp *intel_dp = intel_attached_dp(connector);
+	int target_bw;
+	int max_frl_bw;
 
-	/* If PCON supports FRL MODE, check FRL bandwidth constraints */
-	if (intel_dp->dfp.pcon_max_frl_bw) {
-		int target_bw, max_frl_bw;
+	if (!respect_downstream_limits)
+		return MODE_OK;
 
-		/* Assume 8bpc for the FRL bandwidth check */
-		target_bw = frl_required_bw(target_clock, 8, sink_format);
+	target_bw = frl_required_bw(target_clock, bpc, sink_format);
 
-		max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
+	/* check for MAX FRL BW for both PCON and HDMI2.1 sink */
+	max_frl_bw = min(intel_dp->dfp.pcon_max_frl_bw,
+			 intel_dp_hdmi_sink_max_frl(intel_dp));
 
-		/* converting bw from Gbps to Kbps*/
-		max_frl_bw = max_frl_bw * 1000000;
+	/* converting bw from Gbps to Kbps*/
+	max_frl_bw = max_frl_bw * 1000000;
 
-		if (target_bw > max_frl_bw)
-			return MODE_CLOCK_HIGH;
+	/* #FIXME check bandwidth with DSC if both PCON and HDMI sink support DSC */
+	if (target_bw > max_frl_bw)
+		return MODE_CLOCK_HIGH;
 
-		return MODE_OK;
-	}
+	return MODE_OK;
+}
+
+static enum drm_mode_status
+intel_dp_mode_valid_downstream(struct intel_connector *connector,
+			       const struct drm_display_mode *mode,
+			       int target_clock,
+			       enum intel_output_format sink_format)
+{
+	struct intel_dp *intel_dp = intel_attached_dp(connector);
+
+	/*
+	 * If PCON supports FRL MODE, check FRL bandwidth constraints.
+	 * Assume 8bpc for the HDMI2.1 FRL BW check
+	 */
+	if (intel_dp->dfp.pcon_max_frl_bw && intel_dp_hdmi_sink_max_frl(intel_dp))
+		return intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format, true);
 
 	if (intel_dp->dfp.max_dotclock &&
 	    target_clock > intel_dp->dfp.max_dotclock)
-- 
2.50.1

RE: [PATCH v2 2/8] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP

[Kandpal, Suraj]

> Subject: [PATCH v2 2/8] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP
> 
> The FRL bandwidth check considers only the PCON's max FRL rate, ignoring the
> HDMI2.1 sink's own max FRL rate. Cap the available bandwidth by the
> minimum of the two, similar to the TMDS case.
> 
> Move the check into a helper intel_dp_frl_bw_valid() so it can also be used in
> the compute_config phase in a subsequent change.
> 
> The DSC case, where both the PCON and HDMI sink support DSC, is left as a
> FIXME and handled later.
> 
> v2: Remove extra braces and re-format comment. (Suraj)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 51 ++++++++++++++++---------
>  1 file changed, 34 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 437b9e7bb864..dd706f7de62d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -124,6 +124,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)  }
> 
>  static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> +static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp);
> 
>  /* Is link rate UHBR and thus 128b/132b? */  bool intel_dp_is_uhbr(const struct
> intel_crtc_state *crtc_state) @@ -1179,30 +1180,46 @@ static int
> frl_required_bw(int clock, int bpc,  }
> 
>  static enum drm_mode_status
> -intel_dp_mode_valid_downstream(struct intel_connector *connector,
> -			       const struct drm_display_mode *mode,
> -			       int target_clock,
> -			       enum intel_output_format sink_format)
> +intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock,
> +		      int bpc, enum intel_output_format sink_format,
> +		      bool respect_downstream_limits)
>  {
> -	struct intel_dp *intel_dp = intel_attached_dp(connector);
> +	int target_bw;
> +	int max_frl_bw;
> 
> -	/* If PCON supports FRL MODE, check FRL bandwidth constraints */
> -	if (intel_dp->dfp.pcon_max_frl_bw) {
> -		int target_bw, max_frl_bw;
> +	if (!respect_downstream_limits)
> +		return MODE_OK;
> 
> -		/* Assume 8bpc for the FRL bandwidth check */
> -		target_bw = frl_required_bw(target_clock, 8, sink_format);
> +	target_bw = frl_required_bw(target_clock, bpc, sink_format);
> 
> -		max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
> +	/* check for MAX FRL BW for both PCON and HDMI2.1 sink */
> +	max_frl_bw = min(intel_dp->dfp.pcon_max_frl_bw,
> +			 intel_dp_hdmi_sink_max_frl(intel_dp));
> 
> -		/* converting bw from Gbps to Kbps*/
> -		max_frl_bw = max_frl_bw * 1000000;
> +	/* converting bw from Gbps to Kbps*/
> +	max_frl_bw = max_frl_bw * 1000000;
> 
> -		if (target_bw > max_frl_bw)
> -			return MODE_CLOCK_HIGH;
> +	/* #FIXME check bandwidth with DSC if both PCON and HDMI sink
> support DSC */
> +	if (target_bw > max_frl_bw)
> +		return MODE_CLOCK_HIGH;
> 
> -		return MODE_OK;
> -	}
> +	return MODE_OK;
> +}
> +
> +static enum drm_mode_status
> +intel_dp_mode_valid_downstream(struct intel_connector *connector,
> +			       const struct drm_display_mode *mode,
> +			       int target_clock,
> +			       enum intel_output_format sink_format) {
> +	struct intel_dp *intel_dp = intel_attached_dp(connector);
> +
> +	/*
> +	 * If PCON supports FRL MODE, check FRL bandwidth constraints.
> +	 * Assume 8bpc for the HDMI2.1 FRL BW check
> +	 */
> +	if (intel_dp->dfp.pcon_max_frl_bw &&
> intel_dp_hdmi_sink_max_frl(intel_dp))
> +		return intel_dp_frl_bw_valid(intel_dp, target_clock, 8,
> sink_format,
> +true);
> 
>  	if (intel_dp->dfp.max_dotclock &&
>  	    target_clock > intel_dp->dfp.max_dotclock)
> --
> 2.50.1

[PATCH v2 3/8] drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints

[Ankit Nautiyal]

Add a wrapper function to check dp_downstream clock/bandwidth
constraints. Based on whether the sink supports FRL/TMDS the wrapper
calls the appropriate FRL/TMDS functions.

v2: Don't modify the dfp.maxdotclock check which deals with VGA.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 34 +++++++++++++++++--------
 1 file changed, 24 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index dd706f7de62d..6296c3d32970 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1206,6 +1206,28 @@ intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock,
 	return MODE_OK;
 }
 
+static bool
+intel_dp_pcon_sink_support_frl(struct intel_dp *intel_dp)
+{
+	return intel_dp->dfp.pcon_max_frl_bw &&
+		intel_dp_hdmi_sink_max_frl(intel_dp);
+}
+
+static enum drm_mode_status
+intel_dp_hdmi_bw_valid(struct intel_dp *intel_dp,
+		       int target_clock, int bpc,
+		       enum intel_output_format sink_format,
+		       bool respect_downstream_limits)
+{
+	if (intel_dp_pcon_sink_support_frl(intel_dp))
+		return intel_dp_frl_bw_valid(intel_dp, target_clock, bpc,
+					     sink_format,
+					     respect_downstream_limits);
+
+	return intel_dp_tmds_clock_valid(intel_dp, target_clock, bpc, sink_format,
+					 respect_downstream_limits);
+}
+
 static enum drm_mode_status
 intel_dp_mode_valid_downstream(struct intel_connector *connector,
 			       const struct drm_display_mode *mode,
@@ -1213,21 +1235,13 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
 			       enum intel_output_format sink_format)
 {
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
-
-	/*
-	 * If PCON supports FRL MODE, check FRL bandwidth constraints.
-	 * Assume 8bpc for the HDMI2.1 FRL BW check
-	 */
-	if (intel_dp->dfp.pcon_max_frl_bw && intel_dp_hdmi_sink_max_frl(intel_dp))
-		return intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format, true);
+	int bpc = 8; /* Assume 8bpc for the DP++/HDMI/DVI TMDS/FRL bw check */
 
 	if (intel_dp->dfp.max_dotclock &&
 	    target_clock > intel_dp->dfp.max_dotclock)
 		return MODE_CLOCK_HIGH;
 
-	/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
-	return intel_dp_tmds_clock_valid(intel_dp, target_clock,
-					 8, sink_format, true);
+	return intel_dp_hdmi_bw_valid(intel_dp, target_clock, bpc, sink_format, true);
 }
 
 static enum drm_mode_status
-- 
2.50.1

RE: [PATCH v2 3/8] drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints

[Kandpal, Suraj]

> Subject: [PATCH v2 3/8] drm/i915/dp: Add a wrapper to check frl/tmds
> downstream constraints
> 

Nit: *FRL/TMDS

Otherwise LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Add a wrapper function to check dp_downstream clock/bandwidth constraints.
> Based on whether the sink supports FRL/TMDS the wrapper calls the
> appropriate FRL/TMDS functions.
> 
> v2: Don't modify the dfp.maxdotclock check which deals with VGA.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 34 +++++++++++++++++--------
>  1 file changed, 24 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index dd706f7de62d..6296c3d32970 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1206,6 +1206,28 @@ intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int
> target_clock,
>  	return MODE_OK;
>  }
> 
> +static bool
> +intel_dp_pcon_sink_support_frl(struct intel_dp *intel_dp) {
> +	return intel_dp->dfp.pcon_max_frl_bw &&
> +		intel_dp_hdmi_sink_max_frl(intel_dp);
> +}
> +
> +static enum drm_mode_status
> +intel_dp_hdmi_bw_valid(struct intel_dp *intel_dp,
> +		       int target_clock, int bpc,
> +		       enum intel_output_format sink_format,
> +		       bool respect_downstream_limits) {
> +	if (intel_dp_pcon_sink_support_frl(intel_dp))
> +		return intel_dp_frl_bw_valid(intel_dp, target_clock, bpc,
> +					     sink_format,
> +					     respect_downstream_limits);
> +
> +	return intel_dp_tmds_clock_valid(intel_dp, target_clock, bpc,
> sink_format,
> +					 respect_downstream_limits);
> +}
> +
>  static enum drm_mode_status
>  intel_dp_mode_valid_downstream(struct intel_connector *connector,
>  			       const struct drm_display_mode *mode, @@ -
> 1213,21 +1235,13 @@ intel_dp_mode_valid_downstream(struct
> intel_connector *connector,
>  			       enum intel_output_format sink_format)  {
>  	struct intel_dp *intel_dp = intel_attached_dp(connector);
> -
> -	/*
> -	 * If PCON supports FRL MODE, check FRL bandwidth constraints.
> -	 * Assume 8bpc for the HDMI2.1 FRL BW check
> -	 */
> -	if (intel_dp->dfp.pcon_max_frl_bw &&
> intel_dp_hdmi_sink_max_frl(intel_dp))
> -		return intel_dp_frl_bw_valid(intel_dp, target_clock, 8,
> sink_format, true);
> +	int bpc = 8; /* Assume 8bpc for the DP++/HDMI/DVI TMDS/FRL bw
> check */
> 
>  	if (intel_dp->dfp.max_dotclock &&
>  	    target_clock > intel_dp->dfp.max_dotclock)
>  		return MODE_CLOCK_HIGH;
> 
> -	/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
> -	return intel_dp_tmds_clock_valid(intel_dp, target_clock,
> -					 8, sink_format, true);
> +	return intel_dp_hdmi_bw_valid(intel_dp, target_clock, bpc,
> +sink_format, true);
>  }
> 
>  static enum drm_mode_status
> --
> 2.50.1

[PATCH v2 4/8] drm/i915/dp: Use the common downstream bw check in compute_bpc

[Ankit Nautiyal]

Currently the FRL bandwidth check is only added for the mode_valid phase.
Add the check in the compute_config phase also, replacing the TMDS-only
check with the common function that checks for both TMDS and FRL.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6296c3d32970..652215fdb1a7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1661,8 +1661,8 @@ static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
 	for (; bpc >= 8; bpc -= 2) {
 		if (intel_hdmi_bpc_possible(crtc_state, bpc,
 					    intel_dp_has_hdmi_sink(intel_dp)) &&
-		    intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
-					      respect_downstream_limits) == MODE_OK)
+		    intel_dp_hdmi_bw_valid(intel_dp, clock, bpc, crtc_state->sink_format,
+					   respect_downstream_limits) == MODE_OK)
 			return bpc;
 	}
 
-- 
2.50.1

[PATCH v2 5/8] drm/i915/hdmi: Expose DSC min/max bpp helpers

[Ankit Nautiyal]

Expose intel_hdmi_dsc_get_min_max_bpp() to query the allowed compressed
bpp range.
This will be used in the subsequent change to compute the compressed bpp
range in mode_valid() for an HDMI with DSC connected to a DP DFP.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 20 +++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_hdmi.h |  2 ++
 2 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index df88d7c141f7..ee6a559762c5 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3325,9 +3325,19 @@ intel_hdmi_dsc_get_num_slices(const struct drm_display_mode *mode,
 	return target_slices;
 }
 
-static void
-get_dsc_min_max_bpp(enum intel_output_format output_format, u8 bpc,
-		    bool hdmi_all_bpp, int *min_dsc_bpp, int *max_dsc_bpp)
+/*
+ * intel_hdmi_dsc_get_min_max_bpp - get the min and max compressed bpp range
+ * allowed for a given output format and bpc.
+ *
+ * @output_format: video output format
+ * @bpc: bits per color
+ * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
+ * @min_dsc_bpp: returns the minimum allowed compressed bpp
+ * @max_dsc_bpp: returns the maximum allowed compressed bpp
+ */
+void
+intel_hdmi_dsc_get_min_max_bpp(enum intel_output_format output_format, u8 bpc,
+			       bool hdmi_all_bpp, int *min_dsc_bpp, int *max_dsc_bpp)
 {
 	/*
 	 * Get min bpp and max bpp that can be supported for a
@@ -3433,8 +3443,8 @@ intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
 	int max_dsc_bpp, min_dsc_bpp;
 	int dsc_bpp_x16;
 
-	get_dsc_min_max_bpp(output_format, bpc, hdmi_all_bpp,
-			    &min_dsc_bpp, &max_dsc_bpp);
+	intel_hdmi_dsc_get_min_max_bpp(output_format, bpc, hdmi_all_bpp,
+				       &min_dsc_bpp, &max_dsc_bpp);
 
 	dsc_bpp_x16 = get_dsc_compressed_bpp(num_slices, slice_width,
 					     hdmi_max_chunk_bytes,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index c95ed37bcc0c..3ab75ef4836e 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -57,6 +57,8 @@ int intel_hdmi_tmds_clock(int clock, int bpc, enum intel_output_format sink_form
 int intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width,
 			   int num_slices, enum intel_output_format output_format,
 			   int bpc, bool hdmi_all_bpp, int hdmi_max_chunk_bytes);
+void intel_hdmi_dsc_get_min_max_bpp(enum intel_output_format output_format, u8 bpc,
+				    bool hdmi_all_bpp, int *min_dsc_bpp, int *max_dsc_bpp);
 int intel_hdmi_dsc_get_num_slices(const struct drm_display_mode *mode,
 				  enum intel_output_format output_format,
 				  int src_max_slices, int src_max_slice_width,
-- 
2.50.1

[PATCH v2 6/8] drm/i915/hdmi: Add helper to check if DSC chunksize fits the sink limits

[Ankit Nautiyal]

Introduce the helper intel_hdmi_dsc_bpp_fits_chunk_bytes() to check
whether the chunksize computed for the given slice configuration is with
in the sink's max chunksize limits.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 25 ++++++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_hdmi.h |  2 ++
 2 files changed, 24 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index ee6a559762c5..6ab62a9e941c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3369,11 +3369,30 @@ intel_hdmi_dsc_get_min_max_bpp(enum intel_output_format output_format, u8 bpc,
 		*max_dsc_bpp = min(*max_dsc_bpp, 12);
 }
 
+/*
+ * intel_hdmi_dsc_bpp_fits_chunk_bytes - check if a given compressed bpp keeps
+ * the per-scanline chunk size within the sink's max_chunk_bytes limit.
+ *
+ * @bpp: compressed bits per pixel to test
+ * @num_slices: num of slices supported by the source and sink
+ * @slice_width: dsc slice width supported by the source and sink
+ * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
+ *
+ * @return: true if the resulting chunk size fits the sink limit
+ */
+bool
+intel_hdmi_dsc_bpp_fits_chunk_bytes(int bpp, int num_slices, int slice_width,
+				    int hdmi_max_chunk_bytes)
+{
+	int target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);
+
+	return target_bytes <= hdmi_max_chunk_bytes;
+}
+
 static int
 get_dsc_compressed_bpp(int num_slices, int slice_width, int hdmi_max_chunk_bytes,
 		       int src_fractional_bpp, int min_dsc_bpp, int max_dsc_bpp)
 {
-	int target_bytes;
 	bool bpp_found = false;
 	int bpp_decrement_x16;
 	int bpp_target;
@@ -3408,8 +3427,8 @@ get_dsc_compressed_bpp(int num_slices, int slice_width, int hdmi_max_chunk_bytes
 		int bpp;
 
 		bpp = DIV_ROUND_UP(bpp_target_x16, 16);
-		target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);
-		if (target_bytes <= hdmi_max_chunk_bytes) {
+		if (intel_hdmi_dsc_bpp_fits_chunk_bytes(bpp, num_slices, slice_width,
+							hdmi_max_chunk_bytes)) {
 			bpp_found = true;
 			break;
 		}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index 3ab75ef4836e..db87656eb27f 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -59,6 +59,8 @@ int intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width,
 			   int bpc, bool hdmi_all_bpp, int hdmi_max_chunk_bytes);
 void intel_hdmi_dsc_get_min_max_bpp(enum intel_output_format output_format, u8 bpc,
 				    bool hdmi_all_bpp, int *min_dsc_bpp, int *max_dsc_bpp);
+bool intel_hdmi_dsc_bpp_fits_chunk_bytes(int bpp, int num_slices, int slice_width,
+					 int hdmi_max_chunk_bytes);
 int intel_hdmi_dsc_get_num_slices(const struct drm_display_mode *mode,
 				  enum intel_output_format output_format,
 				  int src_max_slices, int src_max_slice_width,
-- 
2.50.1

[PATCH v2 7/8] drm/i915/dp: Allow PCON DSC modes through FRL bw check

[Ankit Nautiyal]

intel_dp_frl_bw_valid() rejects any mode whose uncompressed FRL
bandwidth exceeds the PCON/sink max FRL bandwidth, even though we are
capable of enabling PCON DSC encoding at modeset time. As a result,
high-bandwidth HDMI2.1 modes (e.g. 4K120, 8K60) get pruned for sinks
behind a PCON, despite the PCON + sink being able to carry them with
DSC compression.

Now, that the HDMI DSC helpers no longer depend on intel_crtc_state,
reuse them from the FRL bandwidth check. When uncompressed transport does
not fit, compute the lowest compressed bpp allowed for the output format
and verify it:
 - fits the sink's per-scanline chunk-bytes limit and
 - resulets in the required FRL bandwidth within the PCON/sink limits.

This takes care of the existing FIXME in the FRL bandwidth check.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 80 ++++++++++++++++++++++---
 1 file changed, 71 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 652215fdb1a7..938e11bc6a46 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -125,6 +125,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
 
 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp);
+static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp);
 
 /* Is link rate UHBR and thus 128b/132b? */
 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
@@ -1179,8 +1180,58 @@ static int frl_required_bw(int clock, int bpc,
 	return clock * bpc * 3;
 }
 
+static int frl_required_bw_dsc(int target_clock, int comp_bpp_x16)
+{
+	return DIV_ROUND_UP(target_clock * comp_bpp_x16, 16);
+}
+
+static bool
+intel_dp_pcon_dsc_fits_frl_bw(struct intel_dp *intel_dp,
+			      const struct drm_display_mode *mode,
+			      int bpc, enum intel_output_format sink_format,
+			      int max_frl_bw)
+{
+	struct intel_connector *connector = intel_dp->attached_connector;
+	const struct drm_display_info *info = &connector->base.display_info;
+	int min_dsc_bpp, max_dsc_bpp;
+	int num_slices, slice_width;
+	int hdmi_max_chunk_bytes;
+	int pcon_max_slices, pcon_max_slice_width;
+
+	/* PCON and HDMI sink must both support DSC 1.2 */
+	if (!info->hdmi.dsc_cap.v_1p2 ||
+	    !drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd))
+		return false;
+
+	pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
+	pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
+
+	num_slices = intel_hdmi_dsc_get_num_slices(mode, sink_format,
+						   pcon_max_slices,
+						   pcon_max_slice_width,
+						   info->hdmi.dsc_cap.max_slices,
+						   info->hdmi.dsc_cap.clk_per_slice);
+	if (!num_slices)
+		return false;
+
+	slice_width = DIV_ROUND_UP(mode->hdisplay, num_slices);
+
+	intel_hdmi_dsc_get_min_max_bpp(sink_format, bpc, info->hdmi.dsc_cap.all_bpp,
+				       &min_dsc_bpp, &max_dsc_bpp);
+
+	/* Use the lowest allowed compressed bpp for the best-case bandwidth */
+	hdmi_max_chunk_bytes = info->hdmi.dsc_cap.total_chunk_kbytes * 1024;
+	if (!intel_hdmi_dsc_bpp_fits_chunk_bytes(min_dsc_bpp, num_slices, slice_width,
+						 hdmi_max_chunk_bytes))
+		return false;
+
+	return frl_required_bw_dsc(mode->clock, min_dsc_bpp * 16) <= max_frl_bw;
+}
+
 static enum drm_mode_status
-intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock,
+intel_dp_frl_bw_valid(struct intel_dp *intel_dp,
+		      const struct drm_display_mode *mode,
+		      int target_clock,
 		      int bpc, enum intel_output_format sink_format,
 		      bool respect_downstream_limits)
 {
@@ -1199,11 +1250,19 @@ intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock,
 	/* converting bw from Gbps to Kbps*/
 	max_frl_bw = max_frl_bw * 1000000;
 
-	/* #FIXME check bandwidth with DSC if both PCON and HDMI sink support DSC */
-	if (target_bw > max_frl_bw)
-		return MODE_CLOCK_HIGH;
+	if (target_bw <= max_frl_bw)
+		return MODE_OK;
 
-	return MODE_OK;
+	/*
+	 * Uncompressed transport doesn't fit; if both PCON and HDMI sink
+	 * support DSC, check whether DSC compression brings it within limits.
+	 */
+	if (intel_dp_is_hdmi_2_1_sink(intel_dp) &&
+	    intel_dp_pcon_dsc_fits_frl_bw(intel_dp, mode, bpc, sink_format,
+					  max_frl_bw))
+		return MODE_OK;
+
+	return MODE_CLOCK_HIGH;
 }
 
 static bool
@@ -1215,13 +1274,14 @@ intel_dp_pcon_sink_support_frl(struct intel_dp *intel_dp)
 
 static enum drm_mode_status
 intel_dp_hdmi_bw_valid(struct intel_dp *intel_dp,
+		       const struct drm_display_mode *mode,
 		       int target_clock, int bpc,
 		       enum intel_output_format sink_format,
 		       bool respect_downstream_limits)
 {
 	if (intel_dp_pcon_sink_support_frl(intel_dp))
-		return intel_dp_frl_bw_valid(intel_dp, target_clock, bpc,
-					     sink_format,
+		return intel_dp_frl_bw_valid(intel_dp, mode,
+					     target_clock, bpc, sink_format,
 					     respect_downstream_limits);
 
 	return intel_dp_tmds_clock_valid(intel_dp, target_clock, bpc, sink_format,
@@ -1241,7 +1301,8 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
 	    target_clock > intel_dp->dfp.max_dotclock)
 		return MODE_CLOCK_HIGH;
 
-	return intel_dp_hdmi_bw_valid(intel_dp, target_clock, bpc, sink_format, true);
+	return intel_dp_hdmi_bw_valid(intel_dp, mode, target_clock, bpc,
+				      sink_format, true);
 }
 
 static enum drm_mode_status
@@ -1661,7 +1722,8 @@ static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
 	for (; bpc >= 8; bpc -= 2) {
 		if (intel_hdmi_bpc_possible(crtc_state, bpc,
 					    intel_dp_has_hdmi_sink(intel_dp)) &&
-		    intel_dp_hdmi_bw_valid(intel_dp, clock, bpc, crtc_state->sink_format,
+		    intel_dp_hdmi_bw_valid(intel_dp, &crtc_state->hw.adjusted_mode,
+					   clock, bpc, crtc_state->sink_format,
 					   respect_downstream_limits) == MODE_OK)
 			return bpc;
 	}
-- 
2.50.1

RE: [PATCH v2 7/8] drm/i915/dp: Allow PCON DSC modes through FRL bw check

[Kandpal, Suraj]

> Subject: [PATCH v2 7/8] drm/i915/dp: Allow PCON DSC modes through FRL bw
> check
> 
> intel_dp_frl_bw_valid() rejects any mode whose uncompressed FRL bandwidth
> exceeds the PCON/sink max FRL bandwidth, even though we are capable of
> enabling PCON DSC encoding at modeset time. As a result, high-bandwidth
> HDMI2.1 modes (e.g. 4K120, 8K60) get pruned for sinks behind a PCON, despite
> the PCON + sink being able to carry them with DSC compression.
> 
> Now, that the HDMI DSC helpers no longer depend on intel_crtc_state, reuse
> them from the FRL bandwidth check. When uncompressed transport does not
> fit, compute the lowest compressed bpp allowed for the output format and
> verify it:
>  - fits the sink's per-scanline chunk-bytes limit and
>  - resulets in the required FRL bandwidth within the PCON/sink limits.

* results

With this fixed LGTM

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> 
> This takes care of the existing FIXME in the FRL bandwidth check.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 80 ++++++++++++++++++++++---
>  1 file changed, 71 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 652215fdb1a7..938e11bc6a46 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -125,6 +125,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
> 
>  static void intel_dp_unset_edid(struct intel_dp *intel_dp);  static int
> intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp);
> +static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp);
> 
>  /* Is link rate UHBR and thus 128b/132b? */  bool intel_dp_is_uhbr(const struct
> intel_crtc_state *crtc_state) @@ -1179,8 +1180,58 @@ static int
> frl_required_bw(int clock, int bpc,
>  	return clock * bpc * 3;
>  }
> 
> +static int frl_required_bw_dsc(int target_clock, int comp_bpp_x16) {
> +	return DIV_ROUND_UP(target_clock * comp_bpp_x16, 16); }
> +
> +static bool
> +intel_dp_pcon_dsc_fits_frl_bw(struct intel_dp *intel_dp,
> +			      const struct drm_display_mode *mode,
> +			      int bpc, enum intel_output_format sink_format,
> +			      int max_frl_bw)
> +{
> +	struct intel_connector *connector = intel_dp->attached_connector;
> +	const struct drm_display_info *info = &connector->base.display_info;
> +	int min_dsc_bpp, max_dsc_bpp;
> +	int num_slices, slice_width;
> +	int hdmi_max_chunk_bytes;
> +	int pcon_max_slices, pcon_max_slice_width;
> +
> +	/* PCON and HDMI sink must both support DSC 1.2 */
> +	if (!info->hdmi.dsc_cap.v_1p2 ||
> +	    !drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd))
> +		return false;
> +
> +	pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp-
> >pcon_dsc_dpcd);
> +	pcon_max_slice_width =
> +drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
> +
> +	num_slices = intel_hdmi_dsc_get_num_slices(mode, sink_format,
> +						   pcon_max_slices,
> +						   pcon_max_slice_width,
> +						   info-
> >hdmi.dsc_cap.max_slices,
> +						   info-
> >hdmi.dsc_cap.clk_per_slice);
> +	if (!num_slices)
> +		return false;
> +
> +	slice_width = DIV_ROUND_UP(mode->hdisplay, num_slices);
> +
> +	intel_hdmi_dsc_get_min_max_bpp(sink_format, bpc, info-
> >hdmi.dsc_cap.all_bpp,
> +				       &min_dsc_bpp, &max_dsc_bpp);
> +
> +	/* Use the lowest allowed compressed bpp for the best-case bandwidth
> */
> +	hdmi_max_chunk_bytes = info->hdmi.dsc_cap.total_chunk_kbytes *
> 1024;
> +	if (!intel_hdmi_dsc_bpp_fits_chunk_bytes(min_dsc_bpp, num_slices,
> slice_width,
> +						 hdmi_max_chunk_bytes))
> +		return false;
> +
> +	return frl_required_bw_dsc(mode->clock, min_dsc_bpp * 16) <=
> +max_frl_bw; }
> +
>  static enum drm_mode_status
> -intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock,
> +intel_dp_frl_bw_valid(struct intel_dp *intel_dp,
> +		      const struct drm_display_mode *mode,
> +		      int target_clock,
>  		      int bpc, enum intel_output_format sink_format,
>  		      bool respect_downstream_limits)  { @@ -1199,11 +1250,19
> @@ intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock,
>  	/* converting bw from Gbps to Kbps*/
>  	max_frl_bw = max_frl_bw * 1000000;
> 
> -	/* #FIXME check bandwidth with DSC if both PCON and HDMI sink
> support DSC */
> -	if (target_bw > max_frl_bw)
> -		return MODE_CLOCK_HIGH;
> +	if (target_bw <= max_frl_bw)
> +		return MODE_OK;
> 
> -	return MODE_OK;
> +	/*
> +	 * Uncompressed transport doesn't fit; if both PCON and HDMI sink
> +	 * support DSC, check whether DSC compression brings it within limits.
> +	 */
> +	if (intel_dp_is_hdmi_2_1_sink(intel_dp) &&
> +	    intel_dp_pcon_dsc_fits_frl_bw(intel_dp, mode, bpc, sink_format,
> +					  max_frl_bw))
> +		return MODE_OK;
> +
> +	return MODE_CLOCK_HIGH;
>  }
> 
>  static bool
> @@ -1215,13 +1274,14 @@ intel_dp_pcon_sink_support_frl(struct intel_dp
> *intel_dp)
> 
>  static enum drm_mode_status
>  intel_dp_hdmi_bw_valid(struct intel_dp *intel_dp,
> +		       const struct drm_display_mode *mode,
>  		       int target_clock, int bpc,
>  		       enum intel_output_format sink_format,
>  		       bool respect_downstream_limits)  {
>  	if (intel_dp_pcon_sink_support_frl(intel_dp))
> -		return intel_dp_frl_bw_valid(intel_dp, target_clock, bpc,
> -					     sink_format,
> +		return intel_dp_frl_bw_valid(intel_dp, mode,
> +					     target_clock, bpc, sink_format,
>  					     respect_downstream_limits);
> 
>  	return intel_dp_tmds_clock_valid(intel_dp, target_clock, bpc,
> sink_format, @@ -1241,7 +1301,8 @@
> intel_dp_mode_valid_downstream(struct intel_connector *connector,
>  	    target_clock > intel_dp->dfp.max_dotclock)
>  		return MODE_CLOCK_HIGH;
> 
> -	return intel_dp_hdmi_bw_valid(intel_dp, target_clock, bpc,
> sink_format, true);
> +	return intel_dp_hdmi_bw_valid(intel_dp, mode, target_clock, bpc,
> +				      sink_format, true);
>  }
> 
>  static enum drm_mode_status
> @@ -1661,7 +1722,8 @@ static int intel_dp_hdmi_compute_bpc(struct
> intel_dp *intel_dp,
>  	for (; bpc >= 8; bpc -= 2) {
>  		if (intel_hdmi_bpc_possible(crtc_state, bpc,
>  					    intel_dp_has_hdmi_sink(intel_dp))
> &&
> -		    intel_dp_hdmi_bw_valid(intel_dp, clock, bpc, crtc_state-
> >sink_format,
> +		    intel_dp_hdmi_bw_valid(intel_dp, &crtc_state-
> >hw.adjusted_mode,
> +					   clock, bpc, crtc_state->sink_format,
>  					   respect_downstream_limits) ==
> MODE_OK)
>  			return bpc;
>  	}
> --
> 2.50.1

[PATCH v2 8/8] drm/i915/dp: Clamp PCON DSC bpp to the FRL link bandwidth

[Ankit Nautiyal]

While configuring the PCON DSC encoder, intel_hdmi_dsc_get_bpp() picks
the highest compressed bpp that fits the sink's per-scanline chunk-bytes
limit. However it does not account for the FRL link bandwidth, so the
selected bpp can end up exceeding what the trained PCON/sink FRL link can
actually carry.

Compute the maximum compressed bpp that the FRL bandwidth can carry and
pass it down to intel_hdmi_dsc_get_bpp() as an upper bound, so the chosen
DSC bpp stays within both the sink's chunk-bytes limit and the FRL link
budget. The mode_valid/compute phase already guarantees the lowest
compressed bpp fits the FRL bandwidth, so this cap never falls below the
minimum allowed bpp.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c   | 9 ++++++++-
 drivers/gpu/drm/i915/display/intel_hdmi.c | 8 +++++++-
 drivers/gpu/drm/i915/display/intel_hdmi.h | 3 ++-
 3 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 938e11bc6a46..98c3ef1d39fa 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4425,10 +4425,17 @@ intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
 	int hdmi_max_chunk_bytes =
 		info->hdmi.dsc_cap.total_chunk_kbytes * 1024;
 	int bpc = crtc_state->pipe_bpp / 3;
+	int clock = crtc_state->hw.adjusted_mode.clock;
+	int max_frl_bw, max_frl_bpp;
+
+	max_frl_bw = min(intel_dp->dfp.pcon_max_frl_bw,
+			 intel_dp_hdmi_sink_max_frl(intel_dp)) * 1000000;
+
+	max_frl_bpp = clock ? max_frl_bw / clock : 0;
 
 	return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
 				      num_slices, output_format, bpc, hdmi_all_bpp,
-				      hdmi_max_chunk_bytes);
+				      hdmi_max_chunk_bytes, max_frl_bpp);
 }
 
 void
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 6ab62a9e941c..7fcba556bdb1 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3451,13 +3451,15 @@ get_dsc_compressed_bpp(int num_slices, int slice_width, int hdmi_max_chunk_bytes
  * @bpc: bits per color
  * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
  * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
+ * @max_link_dsc_bpp: max compressed bpp the link bandwidth can carry, or 0 if not limited
  *
  * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
  */
 int
 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
 		       enum intel_output_format output_format, int bpc,
-		       bool hdmi_all_bpp, int hdmi_max_chunk_bytes)
+		       bool hdmi_all_bpp, int hdmi_max_chunk_bytes,
+		       int max_link_dsc_bpp)
 {
 	int max_dsc_bpp, min_dsc_bpp;
 	int dsc_bpp_x16;
@@ -3465,6 +3467,10 @@ intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
 	intel_hdmi_dsc_get_min_max_bpp(output_format, bpc, hdmi_all_bpp,
 				       &min_dsc_bpp, &max_dsc_bpp);
 
+	/* Limit the bpp to what the link bandwidth can carry */
+	if (max_link_dsc_bpp)
+		max_dsc_bpp = min(max_dsc_bpp, max_link_dsc_bpp);
+
 	dsc_bpp_x16 = get_dsc_compressed_bpp(num_slices, slice_width,
 					     hdmi_max_chunk_bytes,
 					     src_fractional_bpp,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index db87656eb27f..f7a494df19e6 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -56,7 +56,8 @@ bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
 int intel_hdmi_tmds_clock(int clock, int bpc, enum intel_output_format sink_format);
 int intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width,
 			   int num_slices, enum intel_output_format output_format,
-			   int bpc, bool hdmi_all_bpp, int hdmi_max_chunk_bytes);
+			   int bpc, bool hdmi_all_bpp, int hdmi_max_chunk_bytes,
+			   int max_link_dsc_bpp);
 void intel_hdmi_dsc_get_min_max_bpp(enum intel_output_format output_format, u8 bpc,
 				    bool hdmi_all_bpp, int *min_dsc_bpp, int *max_dsc_bpp);
 bool intel_hdmi_dsc_bpp_fits_chunk_bytes(int bpp, int num_slices, int slice_width,
-- 
2.50.1

RE: [PATCH v2 8/8] drm/i915/dp: Clamp PCON DSC bpp to the FRL link bandwidth

[Kandpal, Suraj]

> Subject: [PATCH v2 8/8] drm/i915/dp: Clamp PCON DSC bpp to the FRL link
> bandwidth
> 
> While configuring the PCON DSC encoder, intel_hdmi_dsc_get_bpp() picks the
> highest compressed bpp that fits the sink's per-scanline chunk-bytes limit.
> However it does not account for the FRL link bandwidth, so the selected bpp can
> end up exceeding what the trained PCON/sink FRL link can actually carry.
> 
> Compute the maximum compressed bpp that the FRL bandwidth can carry and
> pass it down to intel_hdmi_dsc_get_bpp() as an upper bound, so the chosen
> DSC bpp stays within both the sink's chunk-bytes limit and the FRL link budget.
> The mode_valid/compute phase already guarantees the lowest compressed bpp
> fits the FRL bandwidth, so this cap never falls below the minimum allowed bpp.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c   | 9 ++++++++-
>  drivers/gpu/drm/i915/display/intel_hdmi.c | 8 +++++++-
> drivers/gpu/drm/i915/display/intel_hdmi.h | 3 ++-
>  3 files changed, 17 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 938e11bc6a46..98c3ef1d39fa 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4425,10 +4425,17 @@ intel_dp_pcon_dsc_enc_bpp(struct intel_dp
> *intel_dp,
>  	int hdmi_max_chunk_bytes =
>  		info->hdmi.dsc_cap.total_chunk_kbytes * 1024;
>  	int bpc = crtc_state->pipe_bpp / 3;
> +	int clock = crtc_state->hw.adjusted_mode.clock;
> +	int max_frl_bw, max_frl_bpp;
> +
> +	max_frl_bw = min(intel_dp->dfp.pcon_max_frl_bw,
> +			 intel_dp_hdmi_sink_max_frl(intel_dp)) * 1000000;
> +
> +	max_frl_bpp = clock ? max_frl_bw / clock : 0;
> 
>  	return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
>  				      num_slices, output_format, bpc,
> hdmi_all_bpp,
> -				      hdmi_max_chunk_bytes);
> +				      hdmi_max_chunk_bytes, max_frl_bpp);
>  }
> 
>  void
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 6ab62a9e941c..7fcba556bdb1 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -3451,13 +3451,15 @@ get_dsc_compressed_bpp(int num_slices, int
> slice_width, int hdmi_max_chunk_bytes
>   * @bpc: bits per color
>   * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
>   * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
> + * @max_link_dsc_bpp: max compressed bpp the link bandwidth can carry,
> + or 0 if not limited
>   *
>   * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
>   */
>  int
>  intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
>  		       enum intel_output_format output_format, int bpc,
> -		       bool hdmi_all_bpp, int hdmi_max_chunk_bytes)
> +		       bool hdmi_all_bpp, int hdmi_max_chunk_bytes,
> +		       int max_link_dsc_bpp)
>  {
>  	int max_dsc_bpp, min_dsc_bpp;
>  	int dsc_bpp_x16;
> @@ -3465,6 +3467,10 @@ intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int
> slice_width, int num_slices,
>  	intel_hdmi_dsc_get_min_max_bpp(output_format, bpc, hdmi_all_bpp,
>  				       &min_dsc_bpp, &max_dsc_bpp);
> 
> +	/* Limit the bpp to what the link bandwidth can carry */
> +	if (max_link_dsc_bpp)
> +		max_dsc_bpp = min(max_dsc_bpp, max_link_dsc_bpp);
> +
>  	dsc_bpp_x16 = get_dsc_compressed_bpp(num_slices, slice_width,
>  					     hdmi_max_chunk_bytes,
>  					     src_fractional_bpp,
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h
> b/drivers/gpu/drm/i915/display/intel_hdmi.h
> index db87656eb27f..f7a494df19e6 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.h
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
> @@ -56,7 +56,8 @@ bool intel_hdmi_bpc_possible(const struct
> intel_crtc_state *crtc_state,  int intel_hdmi_tmds_clock(int clock, int bpc, enum
> intel_output_format sink_format);  int intel_hdmi_dsc_get_bpp(int
> src_fractional_bpp, int slice_width,
>  			   int num_slices, enum intel_output_format
> output_format,
> -			   int bpc, bool hdmi_all_bpp, int
> hdmi_max_chunk_bytes);
> +			   int bpc, bool hdmi_all_bpp, int
> hdmi_max_chunk_bytes,
> +			   int max_link_dsc_bpp);
>  void intel_hdmi_dsc_get_min_max_bpp(enum intel_output_format
> output_format, u8 bpc,
>  				    bool hdmi_all_bpp, int *min_dsc_bpp, int
> *max_dsc_bpp);  bool intel_hdmi_dsc_bpp_fits_chunk_bytes(int bpp, int
> num_slices, int slice_width,
> --
> 2.50.1

✓ CI.KUnit: success for DP-HDMI PCON DSC fixes (rev2)

[Patchwork]

== Series Details ==

Series: DP-HDMI PCON DSC fixes (rev2)
URL   : https://patchwork.freedesktop.org/series/171346/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[05:06:16] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:06:20] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:06:52] Starting KUnit Kernel (1/1)...
[05:06:52] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:06:53] ================== guc_buf (11 subtests) ===================
[05:06:53] [PASSED] test_smallest
[05:06:53] [PASSED] test_largest
[05:06:53] [PASSED] test_granular
[05:06:53] [PASSED] test_unique
[05:06:53] [PASSED] test_overlap
[05:06:53] [PASSED] test_reusable
[05:06:53] [PASSED] test_too_big
[05:06:53] [PASSED] test_flush
[05:06:53] [PASSED] test_lookup
[05:06:53] [PASSED] test_data
[05:06:53] [PASSED] test_class
[05:06:53] ===================== [PASSED] guc_buf =====================
[05:06:53] =================== guc_dbm (7 subtests) ===================
[05:06:53] [PASSED] test_empty
[05:06:53] [PASSED] test_default
[05:06:53] ======================== test_size  ========================
[05:06:53] [PASSED] 4
[05:06:53] [PASSED] 8
[05:06:53] [PASSED] 32
[05:06:53] [PASSED] 256
[05:06:53] ==================== [PASSED] test_size ====================
[05:06:53] ======================= test_reuse  ========================
[05:06:53] [PASSED] 4
[05:06:53] [PASSED] 8
[05:06:53] [PASSED] 32
[05:06:53] [PASSED] 256
[05:06:53] =================== [PASSED] test_reuse ====================
[05:06:53] =================== test_range_overlap  ====================
[05:06:53] [PASSED] 4
[05:06:53] [PASSED] 8
[05:06:53] [PASSED] 32
[05:06:53] [PASSED] 256
[05:06:53] =============== [PASSED] test_range_overlap ================
[05:06:53] =================== test_range_compact  ====================
[05:06:53] [PASSED] 4
[05:06:53] [PASSED] 8
[05:06:53] [PASSED] 32
[05:06:53] [PASSED] 256
[05:06:53] =============== [PASSED] test_range_compact ================
[05:06:53] ==================== test_range_spare  =====================
[05:06:53] [PASSED] 4
[05:06:53] [PASSED] 8
[05:06:53] [PASSED] 32
[05:06:53] [PASSED] 256
[05:06:53] ================ [PASSED] test_range_spare =================
[05:06:53] ===================== [PASSED] guc_dbm =====================
[05:06:53] =================== guc_idm (6 subtests) ===================
[05:06:53] [PASSED] bad_init
[05:06:53] [PASSED] no_init
[05:06:53] [PASSED] init_fini
[05:06:53] [PASSED] check_used
[05:06:53] [PASSED] check_quota
[05:06:53] [PASSED] check_all
[05:06:53] ===================== [PASSED] guc_idm =====================
[05:06:53] =============== guc_klv_helpers (9 subtests) ===============
[05:06:53] [PASSED] test_count
[05:06:53] [PASSED] test_encode_u32
[05:06:53] [PASSED] test_encode_u64
[05:06:53] [PASSED] test_encode_string
[05:06:53] [PASSED] test_encode_object_raw
[05:06:53] [PASSED] test_encode_object_klv
[05:06:53] [PASSED] test_encode_object_nested
[05:06:53] [PASSED] test_encode_object_basic
[05:06:53] [PASSED] test_print
[05:06:53] ================= [PASSED] guc_klv_helpers =================
[05:06:53] ================== no_relay (3 subtests) ===================
[05:06:53] [PASSED] xe_drops_guc2pf_if_not_ready
[05:06:53] [PASSED] xe_drops_guc2vf_if_not_ready
[05:06:53] [PASSED] xe_rejects_send_if_not_ready
[05:06:53] ==================== [PASSED] no_relay =====================
[05:06:53] ================== pf_relay (14 subtests) ==================
[05:06:53] [PASSED] pf_rejects_guc2pf_too_short
[05:06:53] [PASSED] pf_rejects_guc2pf_too_long
[05:06:53] [PASSED] pf_rejects_guc2pf_no_payload
[05:06:53] [PASSED] pf_fails_no_payload
[05:06:53] [PASSED] pf_fails_bad_origin
[05:06:53] [PASSED] pf_fails_bad_type
[05:06:53] [PASSED] pf_txn_reports_error
[05:06:53] [PASSED] pf_txn_sends_pf2guc
[05:06:53] [PASSED] pf_sends_pf2guc
[05:06:53] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[05:06:53] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[05:06:53] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[05:06:53] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[05:06:53] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[05:06:53] ==================== [PASSED] pf_relay =====================
[05:06:53] ================== vf_relay (3 subtests) ===================
[05:06:53] [PASSED] vf_rejects_guc2vf_too_short
[05:06:53] [PASSED] vf_rejects_guc2vf_too_long
[05:06:53] [PASSED] vf_rejects_guc2vf_no_payload
[05:06:53] ==================== [PASSED] vf_relay =====================
[05:06:53] ================ pf_gt_config (9 subtests) =================
[05:06:53] [PASSED] fair_contexts_1vf
[05:06:53] [PASSED] fair_doorbells_1vf
[05:06:53] [PASSED] fair_ggtt_1vf
[05:06:53] ====================== fair_vram_1vf  ======================
[05:06:53] [PASSED] 3.50 GiB
[05:06:53] [PASSED] 11.5 GiB
[05:06:53] [PASSED] 15.5 GiB
[05:06:53] [PASSED] 31.5 GiB
[05:06:53] [PASSED] 63.5 GiB
[05:06:53] [PASSED] 1.91 GiB
[05:06:53] ================== [PASSED] fair_vram_1vf ==================
[05:06:53] ================ fair_vram_1vf_admin_only  =================
[05:06:53] [PASSED] 3.50 GiB
[05:06:53] [PASSED] 11.5 GiB
[05:06:53] [PASSED] 15.5 GiB
[05:06:53] [PASSED] 31.5 GiB
[05:06:53] [PASSED] 63.5 GiB
[05:06:53] [PASSED] 1.91 GiB
[05:06:53] ============ [PASSED] fair_vram_1vf_admin_only =============
[05:06:53] ====================== fair_contexts  ======================
[05:06:53] [PASSED] 1 VF
[05:06:53] [PASSED] 2 VFs
[05:06:53] [PASSED] 3 VFs
[05:06:53] [PASSED] 4 VFs
[05:06:53] [PASSED] 5 VFs
[05:06:53] [PASSED] 6 VFs
[05:06:53] [PASSED] 7 VFs
[05:06:53] [PASSED] 8 VFs
[05:06:53] [PASSED] 9 VFs
[05:06:53] [PASSED] 10 VFs
[05:06:53] [PASSED] 11 VFs
[05:06:53] [PASSED] 12 VFs
[05:06:53] [PASSED] 13 VFs
[05:06:53] [PASSED] 14 VFs
[05:06:53] [PASSED] 15 VFs
[05:06:53] [PASSED] 16 VFs
[05:06:53] [PASSED] 17 VFs
[05:06:53] [PASSED] 18 VFs
[05:06:53] [PASSED] 19 VFs
[05:06:53] [PASSED] 20 VFs
[05:06:53] [PASSED] 21 VFs
[05:06:53] [PASSED] 22 VFs
[05:06:53] [PASSED] 23 VFs
[05:06:53] [PASSED] 24 VFs
[05:06:53] [PASSED] 25 VFs
[05:06:53] [PASSED] 26 VFs
[05:06:53] [PASSED] 27 VFs
[05:06:53] [PASSED] 28 VFs
[05:06:53] [PASSED] 29 VFs
[05:06:53] [PASSED] 30 VFs
[05:06:53] [PASSED] 31 VFs
[05:06:53] [PASSED] 32 VFs
[05:06:53] [PASSED] 33 VFs
[05:06:53] [PASSED] 34 VFs
[05:06:53] [PASSED] 35 VFs
[05:06:53] [PASSED] 36 VFs
[05:06:53] [PASSED] 37 VFs
[05:06:53] [PASSED] 38 VFs
[05:06:53] [PASSED] 39 VFs
[05:06:53] [PASSED] 40 VFs
[05:06:53] [PASSED] 41 VFs
[05:06:53] [PASSED] 42 VFs
[05:06:53] [PASSED] 43 VFs
[05:06:53] [PASSED] 44 VFs
[05:06:53] [PASSED] 45 VFs
[05:06:53] [PASSED] 46 VFs
[05:06:53] [PASSED] 47 VFs
[05:06:53] [PASSED] 48 VFs
[05:06:53] [PASSED] 49 VFs
[05:06:53] [PASSED] 50 VFs
[05:06:53] [PASSED] 51 VFs
[05:06:53] [PASSED] 52 VFs
[05:06:53] [PASSED] 53 VFs
[05:06:53] [PASSED] 54 VFs
[05:06:53] [PASSED] 55 VFs
[05:06:53] [PASSED] 56 VFs
[05:06:53] [PASSED] 57 VFs
[05:06:53] [PASSED] 58 VFs
[05:06:53] [PASSED] 59 VFs
[05:06:53] [PASSED] 60 VFs
[05:06:53] [PASSED] 61 VFs
[05:06:53] [PASSED] 62 VFs
[05:06:53] [PASSED] 63 VFs
[05:06:53] ================== [PASSED] fair_contexts ==================
[05:06:53] ===================== fair_doorbells  ======================
[05:06:53] [PASSED] 1 VF
[05:06:53] [PASSED] 2 VFs
[05:06:53] [PASSED] 3 VFs
[05:06:53] [PASSED] 4 VFs
[05:06:53] [PASSED] 5 VFs
[05:06:53] [PASSED] 6 VFs
[05:06:53] [PASSED] 7 VFs
[05:06:53] [PASSED] 8 VFs
[05:06:53] [PASSED] 9 VFs
[05:06:53] [PASSED] 10 VFs
[05:06:53] [PASSED] 11 VFs
[05:06:53] [PASSED] 12 VFs
[05:06:53] [PASSED] 13 VFs
[05:06:53] [PASSED] 14 VFs
[05:06:53] [PASSED] 15 VFs
[05:06:53] [PASSED] 16 VFs
[05:06:53] [PASSED] 17 VFs
[05:06:53] [PASSED] 18 VFs
[05:06:53] [PASSED] 19 VFs
[05:06:53] [PASSED] 20 VFs
[05:06:53] [PASSED] 21 VFs
[05:06:53] [PASSED] 22 VFs
[05:06:53] [PASSED] 23 VFs
[05:06:53] [PASSED] 24 VFs
[05:06:53] [PASSED] 25 VFs
[05:06:53] [PASSED] 26 VFs
[05:06:53] [PASSED] 27 VFs
[05:06:53] [PASSED] 28 VFs
[05:06:53] [PASSED] 29 VFs
[05:06:53] [PASSED] 30 VFs
[05:06:53] [PASSED] 31 VFs
[05:06:53] [PASSED] 32 VFs
[05:06:53] [PASSED] 33 VFs
[05:06:53] [PASSED] 34 VFs
[05:06:53] [PASSED] 35 VFs
[05:06:53] [PASSED] 36 VFs
[05:06:53] [PASSED] 37 VFs
[05:06:53] [PASSED] 38 VFs
[05:06:53] [PASSED] 39 VFs
[05:06:53] [PASSED] 40 VFs
[05:06:53] [PASSED] 41 VFs
[05:06:53] [PASSED] 42 VFs
[05:06:53] [PASSED] 43 VFs
[05:06:53] [PASSED] 44 VFs
[05:06:53] [PASSED] 45 VFs
[05:06:53] [PASSED] 46 VFs
[05:06:53] [PASSED] 47 VFs
[05:06:53] [PASSED] 48 VFs
[05:06:53] [PASSED] 49 VFs
[05:06:53] [PASSED] 50 VFs
[05:06:53] [PASSED] 51 VFs
[05:06:53] [PASSED] 52 VFs
[05:06:53] [PASSED] 53 VFs
[05:06:53] [PASSED] 54 VFs
[05:06:53] [PASSED] 55 VFs
[05:06:53] [PASSED] 56 VFs
[05:06:53] [PASSED] 57 VFs
[05:06:53] [PASSED] 58 VFs
[05:06:53] [PASSED] 59 VFs
[05:06:53] [PASSED] 60 VFs
[05:06:53] [PASSED] 61 VFs
[05:06:53] [PASSED] 62 VFs
[05:06:53] [PASSED] 63 VFs
[05:06:53] ================= [PASSED] fair_doorbells ==================
[05:06:53] ======================== fair_ggtt  ========================
[05:06:53] [PASSED] 1 VF
[05:06:53] [PASSED] 2 VFs
[05:06:53] [PASSED] 3 VFs
[05:06:53] [PASSED] 4 VFs
[05:06:53] [PASSED] 5 VFs
[05:06:53] [PASSED] 6 VFs
[05:06:53] [PASSED] 7 VFs
[05:06:53] [PASSED] 8 VFs
[05:06:53] [PASSED] 9 VFs
[05:06:53] [PASSED] 10 VFs
[05:06:53] [PASSED] 11 VFs
[05:06:53] [PASSED] 12 VFs
[05:06:53] [PASSED] 13 VFs
[05:06:53] [PASSED] 14 VFs
[05:06:53] [PASSED] 15 VFs
[05:06:53] [PASSED] 16 VFs
[05:06:53] [PASSED] 17 VFs
[05:06:53] [PASSED] 18 VFs
[05:06:53] [PASSED] 19 VFs
[05:06:53] [PASSED] 20 VFs
[05:06:53] [PASSED] 21 VFs
[05:06:53] [PASSED] 22 VFs
[05:06:53] [PASSED] 23 VFs
[05:06:53] [PASSED] 24 VFs
[05:06:53] [PASSED] 25 VFs
[05:06:53] [PASSED] 26 VFs
[05:06:53] [PASSED] 27 VFs
[05:06:53] [PASSED] 28 VFs
[05:06:53] [PASSED] 29 VFs
[05:06:53] [PASSED] 30 VFs
[05:06:53] [PASSED] 31 VFs
[05:06:53] [PASSED] 32 VFs
[05:06:53] [PASSED] 33 VFs
[05:06:53] [PASSED] 34 VFs
[05:06:53] [PASSED] 35 VFs
[05:06:53] [PASSED] 36 VFs
[05:06:53] [PASSED] 37 VFs
[05:06:53] [PASSED] 38 VFs
[05:06:53] [PASSED] 39 VFs
[05:06:53] [PASSED] 40 VFs
[05:06:53] [PASSED] 41 VFs
[05:06:53] [PASSED] 42 VFs
[05:06:53] [PASSED] 43 VFs
[05:06:53] [PASSED] 44 VFs
[05:06:53] [PASSED] 45 VFs
[05:06:53] [PASSED] 46 VFs
[05:06:53] [PASSED] 47 VFs
[05:06:53] [PASSED] 48 VFs
[05:06:53] [PASSED] 49 VFs
[05:06:53] [PASSED] 50 VFs
[05:06:53] [PASSED] 51 VFs
[05:06:53] [PASSED] 52 VFs
[05:06:53] [PASSED] 53 VFs
[05:06:53] [PASSED] 54 VFs
[05:06:53] [PASSED] 55 VFs
[05:06:53] [PASSED] 56 VFs
[05:06:53] [PASSED] 57 VFs
[05:06:53] [PASSED] 58 VFs
[05:06:53] [PASSED] 59 VFs
[05:06:53] [PASSED] 60 VFs
[05:06:53] [PASSED] 61 VFs
[05:06:53] [PASSED] 62 VFs
[05:06:53] [PASSED] 63 VFs
[05:06:53] ==================== [PASSED] fair_ggtt ====================
[05:06:53] ======================== fair_vram  ========================
[05:06:53] [PASSED] 1 VF
[05:06:53] [PASSED] 2 VFs
[05:06:53] [PASSED] 3 VFs
[05:06:53] [PASSED] 4 VFs
[05:06:53] [PASSED] 5 VFs
[05:06:53] [PASSED] 6 VFs
[05:06:53] [PASSED] 7 VFs
[05:06:53] [PASSED] 8 VFs
[05:06:53] [PASSED] 9 VFs
[05:06:53] [PASSED] 10 VFs
[05:06:53] [PASSED] 11 VFs
[05:06:53] [PASSED] 12 VFs
[05:06:53] [PASSED] 13 VFs
[05:06:53] [PASSED] 14 VFs
[05:06:53] [PASSED] 15 VFs
[05:06:53] [PASSED] 16 VFs
[05:06:53] [PASSED] 17 VFs
[05:06:53] [PASSED] 18 VFs
[05:06:53] [PASSED] 19 VFs
[05:06:53] [PASSED] 20 VFs
[05:06:53] [PASSED] 21 VFs
[05:06:53] [PASSED] 22 VFs
[05:06:53] [PASSED] 23 VFs
[05:06:53] [PASSED] 24 VFs
[05:06:53] [PASSED] 25 VFs
[05:06:53] [PASSED] 26 VFs
[05:06:53] [PASSED] 27 VFs
[05:06:53] [PASSED] 28 VFs
[05:06:53] [PASSED] 29 VFs
[05:06:53] [PASSED] 30 VFs
[05:06:53] [PASSED] 31 VFs
[05:06:53] [PASSED] 32 VFs
[05:06:53] [PASSED] 33 VFs
[05:06:53] [PASSED] 34 VFs
[05:06:53] [PASSED] 35 VFs
[05:06:53] [PASSED] 36 VFs
[05:06:53] [PASSED] 37 VFs
[05:06:53] [PASSED] 38 VFs
[05:06:53] [PASSED] 39 VFs
[05:06:53] [PASSED] 40 VFs
[05:06:53] [PASSED] 41 VFs
[05:06:53] [PASSED] 42 VFs
[05:06:53] [PASSED] 43 VFs
[05:06:53] [PASSED] 44 VFs
[05:06:53] [PASSED] 45 VFs
[05:06:53] [PASSED] 46 VFs
[05:06:53] [PASSED] 47 VFs
[05:06:53] [PASSED] 48 VFs
[05:06:53] [PASSED] 49 VFs
[05:06:53] [PASSED] 50 VFs
[05:06:53] [PASSED] 51 VFs
[05:06:53] [PASSED] 52 VFs
[05:06:53] [PASSED] 53 VFs
[05:06:53] [PASSED] 54 VFs
[05:06:53] [PASSED] 55 VFs
[05:06:53] [PASSED] 56 VFs
[05:06:53] [PASSED] 57 VFs
[05:06:53] [PASSED] 58 VFs
[05:06:53] [PASSED] 59 VFs
[05:06:53] [PASSED] 60 VFs
[05:06:53] [PASSED] 61 VFs
[05:06:53] [PASSED] 62 VFs
[05:06:53] [PASSED] 63 VFs
[05:06:53] ==================== [PASSED] fair_vram ====================
[05:06:53] ================== [PASSED] pf_gt_config ===================
[05:06:53] ===================== lmtt (1 subtest) =====================
[05:06:53] ======================== test_ops  =========================
[05:06:53] [PASSED] 2-level
[05:06:53] [PASSED] multi-level
[05:06:53] ==================== [PASSED] test_ops =====================
[05:06:53] ====================== [PASSED] lmtt =======================
[05:06:53] ================= sriov_packet (1 subtest) =================
[05:06:53] [PASSED] test_descriptor_init
[05:06:53] ================== [PASSED] sriov_packet ===================
[05:06:53] ================= pf_service (11 subtests) =================
[05:06:53] [PASSED] pf_negotiate_any
[05:06:53] [PASSED] pf_negotiate_base_match
[05:06:53] [PASSED] pf_negotiate_base_newer
[05:06:53] [PASSED] pf_negotiate_base_next
[05:06:53] [SKIPPED] pf_negotiate_base_older (no older minor)
[05:06:53] [PASSED] pf_negotiate_base_prev
[05:06:53] [PASSED] pf_negotiate_latest_match
[05:06:53] [PASSED] pf_negotiate_latest_newer
[05:06:53] [PASSED] pf_negotiate_latest_next
[05:06:53] [SKIPPED] pf_negotiate_latest_older (no older minor)
[05:06:53] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[05:06:53] =================== [PASSED] pf_service ====================
[05:06:53] ================= xe_guc_g2g (2 subtests) ==================
[05:06:53] ============== xe_live_guc_g2g_kunit_default  ==============
[05:06:53] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[05:06:53] ============== xe_live_guc_g2g_kunit_allmem  ===============
[05:06:53] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[05:06:53] =================== [SKIPPED] xe_guc_g2g ===================
[05:06:53] =================== xe_mocs (2 subtests) ===================
[05:06:53] ================ xe_live_mocs_kernel_kunit  ================
[05:06:53] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[05:06:53] ================ xe_live_mocs_reset_kunit  =================
[05:06:53] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[05:06:53] ==================== [SKIPPED] xe_mocs =====================
[05:06:53] ================= xe_migrate (2 subtests) ==================
[05:06:53] ================= xe_migrate_sanity_kunit  =================
[05:06:53] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[05:06:53] ================== xe_validate_ccs_kunit  ==================
[05:06:53] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[05:06:53] =================== [SKIPPED] xe_migrate ===================
[05:06:53] ================== xe_dma_buf (1 subtest) ==================
[05:06:53] ==================== xe_dma_buf_kunit  =====================
[05:06:53] ================ [SKIPPED] xe_dma_buf_kunit ================
[05:06:53] =================== [SKIPPED] xe_dma_buf ===================
[05:06:53] ================= xe_bo_shrink (1 subtest) =================
[05:06:53] =================== xe_bo_shrink_kunit  ====================
[05:06:53] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[05:06:53] ================== [SKIPPED] xe_bo_shrink ==================
[05:06:53] ==================== xe_bo (2 subtests) ====================
[05:06:53] ================== xe_ccs_migrate_kunit  ===================
[05:06:53] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[05:06:53] ==================== xe_bo_evict_kunit  ====================
[05:06:53] =============== [SKIPPED] xe_bo_evict_kunit ================
[05:06:53] ===================== [SKIPPED] xe_bo ======================
[05:06:53] ==================== args (13 subtests) ====================
[05:06:53] [PASSED] count_args_test
[05:06:53] [PASSED] call_args_example
[05:06:53] [PASSED] call_args_test
[05:06:53] [PASSED] drop_first_arg_example
[05:06:53] [PASSED] drop_first_arg_test
[05:06:53] [PASSED] first_arg_example
[05:06:53] [PASSED] first_arg_test
[05:06:53] [PASSED] last_arg_example
[05:06:53] [PASSED] last_arg_test
[05:06:53] [PASSED] pick_arg_example
[05:06:53] [PASSED] if_args_example
[05:06:53] [PASSED] if_args_test
[05:06:53] [PASSED] sep_comma_example
[05:06:53] ====================== [PASSED] args =======================
[05:06:53] =================== xe_pci (3 subtests) ====================
[05:06:53] ==================== check_graphics_ip  ====================
[05:06:53] [PASSED] 12.00 Xe_LP
[05:06:53] [PASSED] 12.10 Xe_LP+
[05:06:53] [PASSED] 12.55 Xe_HPG
[05:06:53] [PASSED] 12.60 Xe_HPC
[05:06:53] [PASSED] 12.70 Xe_LPG
[05:06:53] [PASSED] 12.71 Xe_LPG
[05:06:53] [PASSED] 12.74 Xe_LPG+
[05:06:53] [PASSED] 20.01 Xe2_HPG
[05:06:53] [PASSED] 20.02 Xe2_HPG
[05:06:53] [PASSED] 20.04 Xe2_LPG
[05:06:53] [PASSED] 30.00 Xe3_LPG
[05:06:53] [PASSED] 30.01 Xe3_LPG
[05:06:53] [PASSED] 30.03 Xe3_LPG
[05:06:53] [PASSED] 30.04 Xe3_LPG
[05:06:53] [PASSED] 30.05 Xe3_LPG
[05:06:53] [PASSED] 35.10 Xe3p_LPG
[05:06:53] [PASSED] 35.11 Xe3p_XPC
[05:06:53] ================ [PASSED] check_graphics_ip ================
[05:06:53] ===================== check_media_ip  ======================
[05:06:53] [PASSED] 12.00 Xe_M
[05:06:53] [PASSED] 12.55 Xe_HPM
[05:06:53] [PASSED] 13.00 Xe_LPM+
[05:06:53] [PASSED] 13.01 Xe2_HPM
[05:06:53] [PASSED] 20.00 Xe2_LPM
[05:06:53] [PASSED] 30.00 Xe3_LPM
[05:06:53] [PASSED] 30.02 Xe3_LPM
[05:06:53] [PASSED] 35.00 Xe3p_LPM
[05:06:53] [PASSED] 35.03 Xe3p_HPM
[05:06:53] ================= [PASSED] check_media_ip ==================
[05:06:53] =================== check_platform_desc  ===================
[05:06:53] [PASSED] 0x9A60 (TIGERLAKE)
[05:06:53] [PASSED] 0x9A68 (TIGERLAKE)
[05:06:53] [PASSED] 0x9A70 (TIGERLAKE)
[05:06:53] [PASSED] 0x9A40 (TIGERLAKE)
[05:06:53] [PASSED] 0x9A49 (TIGERLAKE)
[05:06:53] [PASSED] 0x9A59 (TIGERLAKE)
[05:06:53] [PASSED] 0x9A78 (TIGERLAKE)
[05:06:53] [PASSED] 0x9AC0 (TIGERLAKE)
[05:06:53] [PASSED] 0x9AC9 (TIGERLAKE)
[05:06:53] [PASSED] 0x9AD9 (TIGERLAKE)
[05:06:53] [PASSED] 0x9AF8 (TIGERLAKE)
[05:06:53] [PASSED] 0x4C80 (ROCKETLAKE)
[05:06:53] [PASSED] 0x4C8A (ROCKETLAKE)
[05:06:53] [PASSED] 0x4C8B (ROCKETLAKE)
[05:06:53] [PASSED] 0x4C8C (ROCKETLAKE)
[05:06:53] [PASSED] 0x4C90 (ROCKETLAKE)
[05:06:53] [PASSED] 0x4C9A (ROCKETLAKE)
[05:06:53] [PASSED] 0x4680 (ALDERLAKE_S)
[05:06:53] [PASSED] 0x4682 (ALDERLAKE_S)
[05:06:53] [PASSED] 0x4688 (ALDERLAKE_S)
[05:06:53] [PASSED] 0x468A (ALDERLAKE_S)
[05:06:53] [PASSED] 0x468B (ALDERLAKE_S)
[05:06:53] [PASSED] 0x4690 (ALDERLAKE_S)
[05:06:53] [PASSED] 0x4692 (ALDERLAKE_S)
[05:06:53] [PASSED] 0x4693 (ALDERLAKE_S)
[05:06:53] [PASSED] 0x46A0 (ALDERLAKE_P)
[05:06:53] [PASSED] 0x46A1 (ALDERLAKE_P)
[05:06:53] [PASSED] 0x46A2 (ALDERLAKE_P)
[05:06:53] [PASSED] 0x46A3 (ALDERLAKE_P)
[05:06:53] [PASSED] 0x46A6 (ALDERLAKE_P)
[05:06:53] [PASSED] 0x46A8 (ALDERLAKE_P)
[05:06:53] [PASSED] 0x46AA (ALDERLAKE_P)
[05:06:53] [PASSED] 0x462A (ALDERLAKE_P)
[05:06:53] [PASSED] 0x4626 (ALDERLAKE_P)
[05:06:53] [PASSED] 0x4628 (ALDERLAKE_P)
[05:06:53] [PASSED] 0x46B0 (ALDERLAKE_P)
[05:06:53] [PASSED] 0x46B1 (ALDERLAKE_P)
[05:06:53] [PASSED] 0x46B2 (ALDERLAKE_P)
[05:06:53] [PASSED] 0x46B3 (ALDERLAKE_P)
[05:06:53] [PASSED] 0x46C0 (ALDERLAKE_P)
[05:06:53] [PASSED] 0x46C1 (ALDERLAKE_P)
[05:06:53] [PASSED] 0x46C2 (ALDERLAKE_P)
[05:06:53] [PASSED] 0x46C3 (ALDERLAKE_P)
[05:06:53] [PASSED] 0x46D0 (ALDERLAKE_N)
[05:06:53] [PASSED] 0x46D1 (ALDERLAKE_N)
[05:06:53] [PASSED] 0x46D2 (ALDERLAKE_N)
[05:06:53] [PASSED] 0x46D3 (ALDERLAKE_N)
[05:06:53] [PASSED] 0x46D4 (ALDERLAKE_N)
[05:06:53] [PASSED] 0xA721 (ALDERLAKE_P)
[05:06:53] [PASSED] 0xA7A1 (ALDERLAKE_P)
[05:06:53] [PASSED] 0xA7A9 (ALDERLAKE_P)
[05:06:53] [PASSED] 0xA7AC (ALDERLAKE_P)
[05:06:53] [PASSED] 0xA7AD (ALDERLAKE_P)
[05:06:53] [PASSED] 0xA720 (ALDERLAKE_P)
[05:06:53] [PASSED] 0xA7A0 (ALDERLAKE_P)
[05:06:53] [PASSED] 0xA7A8 (ALDERLAKE_P)
[05:06:53] [PASSED] 0xA7AA (ALDERLAKE_P)
[05:06:53] [PASSED] 0xA7AB (ALDERLAKE_P)
[05:06:53] [PASSED] 0xA780 (ALDERLAKE_S)
[05:06:53] [PASSED] 0xA781 (ALDERLAKE_S)
[05:06:53] [PASSED] 0xA782 (ALDERLAKE_S)
[05:06:53] [PASSED] 0xA783 (ALDERLAKE_S)
[05:06:53] [PASSED] 0xA788 (ALDERLAKE_S)
[05:06:53] [PASSED] 0xA789 (ALDERLAKE_S)
[05:06:53] [PASSED] 0xA78A (ALDERLAKE_S)
[05:06:53] [PASSED] 0xA78B (ALDERLAKE_S)
[05:06:53] [PASSED] 0x4905 (DG1)
[05:06:53] [PASSED] 0x4906 (DG1)
[05:06:53] [PASSED] 0x4907 (DG1)
[05:06:53] [PASSED] 0x4908 (DG1)
[05:06:53] [PASSED] 0x4909 (DG1)
[05:06:53] [PASSED] 0x56C0 (DG2)
[05:06:53] [PASSED] 0x56C2 (DG2)
[05:06:53] [PASSED] 0x56C1 (DG2)
[05:06:53] [PASSED] 0x7D51 (METEORLAKE)
[05:06:53] [PASSED] 0x7DD1 (METEORLAKE)
[05:06:53] [PASSED] 0x7D41 (METEORLAKE)
[05:06:53] [PASSED] 0x7D67 (METEORLAKE)
[05:06:53] [PASSED] 0xB640 (METEORLAKE)
[05:06:53] [PASSED] 0x56A0 (DG2)
[05:06:53] [PASSED] 0x56A1 (DG2)
[05:06:53] [PASSED] 0x56A2 (DG2)
[05:06:53] [PASSED] 0x56BE (DG2)
[05:06:53] [PASSED] 0x56BF (DG2)
[05:06:53] [PASSED] 0x5690 (DG2)
[05:06:53] [PASSED] 0x5691 (DG2)
[05:06:53] [PASSED] 0x5692 (DG2)
[05:06:53] [PASSED] 0x56A5 (DG2)
[05:06:53] [PASSED] 0x56A6 (DG2)
[05:06:53] [PASSED] 0x56B0 (DG2)
[05:06:53] [PASSED] 0x56B1 (DG2)
[05:06:53] [PASSED] 0x56BA (DG2)
[05:06:53] [PASSED] 0x56BB (DG2)
[05:06:53] [PASSED] 0x56BC (DG2)
[05:06:53] [PASSED] 0x56BD (DG2)
[05:06:53] [PASSED] 0x5693 (DG2)
[05:06:53] [PASSED] 0x5694 (DG2)
[05:06:53] [PASSED] 0x5695 (DG2)
[05:06:53] [PASSED] 0x56A3 (DG2)
[05:06:53] [PASSED] 0x56A4 (DG2)
[05:06:53] [PASSED] 0x56B2 (DG2)
[05:06:53] [PASSED] 0x56B3 (DG2)
[05:06:53] [PASSED] 0x5696 (DG2)
[05:06:53] [PASSED] 0x5697 (DG2)
[05:06:53] [PASSED] 0xB69 (PVC)
[05:06:53] [PASSED] 0xB6E (PVC)
[05:06:53] [PASSED] 0xBD4 (PVC)
[05:06:53] [PASSED] 0xBD5 (PVC)
[05:06:53] [PASSED] 0xBD6 (PVC)
[05:06:53] [PASSED] 0xBD7 (PVC)
[05:06:53] [PASSED] 0xBD8 (PVC)
[05:06:53] [PASSED] 0xBD9 (PVC)
[05:06:53] [PASSED] 0xBDA (PVC)
[05:06:53] [PASSED] 0xBDB (PVC)
[05:06:53] [PASSED] 0xBE0 (PVC)
[05:06:53] [PASSED] 0xBE1 (PVC)
[05:06:53] [PASSED] 0xBE5 (PVC)
[05:06:53] [PASSED] 0x7D40 (METEORLAKE)
[05:06:53] [PASSED] 0x7D45 (METEORLAKE)
[05:06:53] [PASSED] 0x7D55 (METEORLAKE)
[05:06:53] [PASSED] 0x7D60 (METEORLAKE)
[05:06:53] [PASSED] 0x7DD5 (METEORLAKE)
[05:06:53] [PASSED] 0x6420 (LUNARLAKE)
[05:06:53] [PASSED] 0x64A0 (LUNARLAKE)
[05:06:53] [PASSED] 0x64B0 (LUNARLAKE)
[05:06:53] [PASSED] 0xE202 (BATTLEMAGE)
[05:06:53] [PASSED] 0xE209 (BATTLEMAGE)
[05:06:53] [PASSED] 0xE20B (BATTLEMAGE)
[05:06:53] [PASSED] 0xE20C (BATTLEMAGE)
[05:06:53] [PASSED] 0xE20D (BATTLEMAGE)
[05:06:53] [PASSED] 0xE210 (BATTLEMAGE)
[05:06:53] [PASSED] 0xE211 (BATTLEMAGE)
[05:06:53] [PASSED] 0xE212 (BATTLEMAGE)
[05:06:53] [PASSED] 0xE216 (BATTLEMAGE)
[05:06:53] [PASSED] 0xE220 (BATTLEMAGE)
[05:06:53] [PASSED] 0xE221 (BATTLEMAGE)
[05:06:53] [PASSED] 0xE222 (BATTLEMAGE)
[05:06:53] [PASSED] 0xE223 (BATTLEMAGE)
[05:06:53] [PASSED] 0xB080 (PANTHERLAKE)
[05:06:53] [PASSED] 0xB081 (PANTHERLAKE)
[05:06:53] [PASSED] 0xB082 (PANTHERLAKE)
[05:06:53] [PASSED] 0xB083 (PANTHERLAKE)
[05:06:53] [PASSED] 0xB084 (PANTHERLAKE)
[05:06:53] [PASSED] 0xB085 (PANTHERLAKE)
[05:06:53] [PASSED] 0xB086 (PANTHERLAKE)
[05:06:53] [PASSED] 0xB087 (PANTHERLAKE)
[05:06:53] [PASSED] 0xB08F (PANTHERLAKE)
[05:06:53] [PASSED] 0xB090 (PANTHERLAKE)
[05:06:53] [PASSED] 0xB0A0 (PANTHERLAKE)
[05:06:53] [PASSED] 0xB0B0 (PANTHERLAKE)
[05:06:53] [PASSED] 0xFD80 (PANTHERLAKE)
[05:06:53] [PASSED] 0xFD81 (PANTHERLAKE)
[05:06:53] [PASSED] 0xD740 (NOVALAKE_S)
[05:06:53] [PASSED] 0xD741 (NOVALAKE_S)
[05:06:53] [PASSED] 0xD742 (NOVALAKE_S)
[05:06:53] [PASSED] 0xD743 (NOVALAKE_S)
[05:06:53] [PASSED] 0xD745 (NOVALAKE_S)
[05:06:53] [PASSED] 0xD74A (NOVALAKE_S)
[05:06:53] [PASSED] 0xD74B (NOVALAKE_S)
[05:06:53] [PASSED] 0x674C (CRESCENTISLAND)
[05:06:53] [PASSED] 0x674D (CRESCENTISLAND)
[05:06:53] [PASSED] 0x674E (CRESCENTISLAND)
[05:06:53] [PASSED] 0x674F (CRESCENTISLAND)
[05:06:53] [PASSED] 0x6750 (CRESCENTISLAND)
[05:06:53] [PASSED] 0xD750 (NOVALAKE_P)
[05:06:53] [PASSED] 0xD751 (NOVALAKE_P)
[05:06:53] [PASSED] 0xD752 (NOVALAKE_P)
[05:06:53] [PASSED] 0xD753 (NOVALAKE_P)
[05:06:53] [PASSED] 0xD754 (NOVALAKE_P)
[05:06:53] [PASSED] 0xD755 (NOVALAKE_P)
[05:06:53] [PASSED] 0xD756 (NOVALAKE_P)
[05:06:53] [PASSED] 0xD757 (NOVALAKE_P)
[05:06:53] [PASSED] 0xD75F (NOVALAKE_P)
[05:06:53] =============== [PASSED] check_platform_desc ===============
[05:06:53] ===================== [PASSED] xe_pci ======================
[05:06:53] ============= xe_rtp_tables_test (5 subtests) ==============
[05:06:53] ================== xe_rtp_table_gt_test  ===================
[05:06:53] [PASSED] gt_was/14011060649
[05:06:53] [PASSED] gt_was/14011059788
[05:06:53] [PASSED] gt_was/14015795083
[05:06:53] [PASSED] gt_was/16021867713
[05:06:53] [PASSED] gt_was/14019449301
[05:06:53] [PASSED] gt_was/16028005424
[05:06:53] [PASSED] gt_was/14026578760
[05:06:53] [PASSED] gt_was/1409420604
[05:06:53] [PASSED] gt_was/1408615072
[05:06:53] [PASSED] gt_was/22010523718
[05:06:53] [PASSED] gt_was/14011006942
[05:06:53] [PASSED] gt_was/14014830051
[05:06:53] [PASSED] gt_was/18018781329
[05:06:53] [PASSED] gt_was/1509235366
[05:06:53] [PASSED] gt_was/18018781329
[05:06:53] [PASSED] gt_was/16016694945
[05:06:53] [PASSED] gt_was/14018575942
[05:06:53] [PASSED] gt_was/22016670082
[05:06:53] [PASSED] gt_was/22016670082
[05:06:53] [PASSED] gt_was/14017421178
[05:06:53] [PASSED] gt_was/16025250150
[05:06:53] [PASSED] gt_was/14021871409
[05:06:53] [PASSED] gt_was/16021865536
[05:06:53] [PASSED] gt_was/14021486841
[05:06:53] [PASSED] gt_was/14025160223
[05:06:53] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[05:06:53] [PASSED] gt_was/14025635424
[05:06:53] [PASSED] gt_was/16028005424
[05:06:53] ============== [PASSED] xe_rtp_table_gt_test ===============
[05:06:53] ================== xe_rtp_table_gt_test  ===================
[05:06:53] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[05:06:53] [PASSED] gt_tunings/Tuning: 32B Access Enable
[05:06:53] [PASSED] gt_tunings/Tuning: L3 cache
[05:06:53] [PASSED] gt_tunings/Tuning: L3 cache - media
[05:06:53] [PASSED] gt_tunings/Tuning: Compression Overfetch
[05:06:53] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[05:06:53] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[05:06:53] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[05:06:53] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[05:06:53] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[05:06:53] [PASSED] gt_tunings/Tuning: Stateless compression control
[05:06:53] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[05:06:53] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[05:06:53] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[05:06:53] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[05:06:53] ============== [PASSED] xe_rtp_table_gt_test ===============
[05:06:53] ================== xe_rtp_table_oob_test  ==================
[05:06:53] [PASSED] oob_was/1607983814
[05:06:53] [PASSED] oob_was/16010904313
[05:06:53] [PASSED] oob_was/18022495364
[05:06:53] [PASSED] oob_was/22012773006
[05:06:53] [PASSED] oob_was/14014475959
[05:06:53] [PASSED] oob_was/22011391025
[05:06:53] [PASSED] oob_was/22012727170
[05:06:53] [PASSED] oob_was/22012727685
[05:06:53] [PASSED] oob_was/22016596838
[05:06:53] [PASSED] oob_was/18020744125
[05:06:53] [PASSED] oob_was/1409600907
[05:06:53] [PASSED] oob_was/22014953428
[05:06:53] [PASSED] oob_was/16017236439
[05:06:53] [PASSED] oob_was/14019821291
[05:06:53] [PASSED] oob_was/14015076503
[05:06:53] [PASSED] oob_was/14018913170
[05:06:53] [PASSED] oob_was/14018094691
[05:06:53] [PASSED] oob_was/18024947630
[05:06:53] [PASSED] oob_was/16022287689
[05:06:53] [PASSED] oob_was/13011645652
[05:06:53] [PASSED] oob_was/14022293748
[05:06:53] [PASSED] oob_was/22019794406
[05:06:53] [PASSED] oob_was/22019338487
[05:06:53] [PASSED] oob_was/16023588340
[05:06:53] [PASSED] oob_was/14019789679
[05:06:53] [PASSED] oob_was/14022866841
[05:06:53] [PASSED] oob_was/16021333562
[05:06:53] [PASSED] oob_was/14016712196
[05:06:53] [PASSED] oob_was/14015568240
[05:06:53] [PASSED] oob_was/18013179988
[05:06:53] [PASSED] oob_was/1508761755
[05:06:53] [PASSED] oob_was/16023105232
[05:06:53] [PASSED] oob_was/16026508708
[05:06:53] [PASSED] oob_was/14020001231
[05:06:53] [PASSED] oob_was/16023683509
[05:06:53] [PASSED] oob_was/14025515070
[05:06:53] [PASSED] oob_was/15015404425_disable
[05:06:53] [PASSED] oob_was/16026007364
[05:06:53] [PASSED] oob_was/14020316580
[05:06:53] [PASSED] oob_was/14025883347
[05:06:53] [PASSED] oob_was/16029380221
[05:06:53] [PASSED] oob_was/22022079272
[05:06:53] [PASSED] oob_was/16029897822
[05:06:53] [PASSED] oob_was/14027054324
[05:06:53] ============== [PASSED] xe_rtp_table_oob_test ==============
[05:06:53] ================ xe_rtp_table_dev_oob_test  ================
[05:06:53] [PASSED] device_oob_was/22010954014
[05:06:53] [PASSED] device_oob_was/15015404425
[05:06:53] [PASSED] device_oob_was/22019338487_display
[05:06:53] [PASSED] device_oob_was/14022085890
[05:06:53] [PASSED] device_oob_was/14026539277
[05:06:53] [PASSED] device_oob_was/14026633728
[05:06:53] [PASSED] device_oob_was/14026746987
[05:06:53] [PASSED] device_oob_was/14026779378
[05:06:53] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[05:06:53] ========== xe_rtp_table_missing_upper_bound_test  ==========
[05:06:53] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[05:06:53] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[05:06:53] [PASSED] register_whitelist/1806527549
[05:06:53] [PASSED] register_whitelist/allow_read_ctx_timestamp
[05:06:53] [PASSED] register_whitelist/allow_read_queue_timestamp
[05:06:53] [PASSED] register_whitelist/16014440446
[05:06:53] [PASSED] register_whitelist/16017236439
[05:06:53] [PASSED] register_whitelist/16020183090
[05:06:53] [PASSED] register_whitelist/14024997852
[05:06:53] [PASSED] register_whitelist/14024997852
[05:06:53] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[05:06:53] =============== [PASSED] xe_rtp_tables_test ================
[05:06:53] =================== xe_rtp (3 subtests) ====================
[05:06:53] =================== xe_rtp_rules_tests  ====================
[05:06:53] [PASSED] no
[05:06:53] [PASSED] yes
[05:06:53] [PASSED] no-and-no
[05:06:53] [PASSED] no-and-yes
[05:06:53] [PASSED] yes-and-no
[05:06:53] [PASSED] yes-and-yes
[05:06:53] [PASSED] no-or-no
[05:06:53] [PASSED] no-or-yes
[05:06:53] [PASSED] yes-or-no
[05:06:53] [PASSED] yes-or-yes
[05:06:53] [PASSED] no-yes-or-yes-no
[05:06:53] [PASSED] no-yes-or-yes-yes
[05:06:53] [PASSED] yes-yes-or-no-yes
[05:06:53] [PASSED] yes-yes-or-yes-yes
[05:06:53] [PASSED] no-no-or-yes-or-no
[05:06:53] [PASSED] or
[05:06:53] [PASSED] or-yes
[05:06:53] [PASSED] or-no
[05:06:53] [PASSED] yes-or
[05:06:53] [PASSED] no-or
[05:06:53] [PASSED] no-or-or-yes
[05:06:53] [PASSED] yes-or-or-no
[05:06:53] [PASSED] no-or-or-no
[05:06:53] [PASSED] missing-context-engine-class
[05:06:53] [PASSED] missing-context-engine-class-or-yes
[05:06:53] [PASSED] missing-context-engine-class-or-or-yes
[05:06:53] =============== [PASSED] xe_rtp_rules_tests ================
[05:06:53] =============== xe_rtp_process_to_sr_tests  ================
[05:06:53] [PASSED] coalesce-same-reg
[05:06:53] [PASSED] coalesce-same-reg-literal-and-func
[05:06:53] [PASSED] no-match-no-add
[05:06:53] [PASSED] two-regs-two-entries
[05:06:53] [PASSED] clr-one-set-other
[05:06:53] [PASSED] set-field
[05:06:53] [PASSED] conflict-duplicate
[05:06:53] [PASSED] conflict-not-disjoint
[05:06:53] [PASSED] conflict-not-disjoint-literal-and-func
[05:06:53] [PASSED] conflict-reg-type
[05:06:53] [PASSED] bad-mcr-reg-forced-to-regular
[05:06:53] [PASSED] bad-regular-reg-forced-to-mcr
[05:06:53] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[05:06:53] ================== xe_rtp_process_tests  ===================
[05:06:53] [PASSED] active1
[05:06:53] [PASSED] active2
[05:06:53] [PASSED] active-inactive
[05:06:53] [PASSED] inactive-active
[05:06:53] [PASSED] inactive-active-inactive
[05:06:53] [PASSED] inactive-inactive-inactive
[05:06:53] ============== [PASSED] xe_rtp_process_tests ===============
[05:06:53] ===================== [PASSED] xe_rtp ======================
[05:06:53] ==================== xe_wa (1 subtest) =====================
[05:06:53] ======================== xe_wa_gt  =========================
[05:06:53] [PASSED] TIGERLAKE B0
[05:06:53] [PASSED] DG1 A0
[05:06:53] [PASSED] DG1 B0
[05:06:53] [PASSED] ALDERLAKE_S A0
[05:06:53] [PASSED] ALDERLAKE_S B0
[05:06:53] [PASSED] ALDERLAKE_S C0
[05:06:53] [PASSED] ALDERLAKE_S D0
[05:06:53] [PASSED] ALDERLAKE_P A0
[05:06:53] [PASSED] ALDERLAKE_P B0
[05:06:53] [PASSED] ALDERLAKE_P C0
[05:06:53] [PASSED] ALDERLAKE_S RPLS D0
[05:06:53] [PASSED] ALDERLAKE_P RPLU E0
[05:06:53] [PASSED] DG2 G10 C0
[05:06:53] [PASSED] DG2 G11 B1
[05:06:53] [PASSED] DG2 G12 A1
[05:06:53] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[05:06:53] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[05:06:53] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[05:06:53] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[05:06:53] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[05:06:53] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[05:06:53] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[05:06:53] ==================== [PASSED] xe_wa_gt =====================
[05:06:53] ====================== [PASSED] xe_wa ======================
[05:06:53] ============================================================
[05:06:53] Testing complete. Ran 742 tests: passed: 724, skipped: 18
[05:06:53] Elapsed time: 36.942s total, 4.373s configuring, 31.903s building, 0.641s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[05:06:53] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:06:55] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:07:19] Starting KUnit Kernel (1/1)...
[05:07:19] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:07:20] ============ drm_test_pick_cmdline (2 subtests) ============
[05:07:20] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[05:07:20] =============== drm_test_pick_cmdline_named  ===============
[05:07:20] [PASSED] NTSC
[05:07:20] [PASSED] NTSC-J
[05:07:20] [PASSED] PAL
[05:07:20] [PASSED] PAL-M
[05:07:20] =========== [PASSED] drm_test_pick_cmdline_named ===========
[05:07:20] ============== [PASSED] drm_test_pick_cmdline ==============
[05:07:20] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[05:07:20] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[05:07:20] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[05:07:20] =========== drm_validate_clone_mode (2 subtests) ===========
[05:07:20] ============== drm_test_check_in_clone_mode  ===============
[05:07:20] [PASSED] in_clone_mode
[05:07:20] [PASSED] not_in_clone_mode
[05:07:20] ========== [PASSED] drm_test_check_in_clone_mode ===========
[05:07:20] =============== drm_test_check_valid_clones  ===============
[05:07:20] [PASSED] not_in_clone_mode
[05:07:20] [PASSED] valid_clone
[05:07:20] [PASSED] invalid_clone
[05:07:20] =========== [PASSED] drm_test_check_valid_clones ===========
[05:07:20] ============= [PASSED] drm_validate_clone_mode =============
[05:07:20] ============= drm_validate_modeset (1 subtest) =============
[05:07:20] [PASSED] drm_test_check_connector_changed_modeset
[05:07:20] ============== [PASSED] drm_validate_modeset ===============
[05:07:20] ====== drm_test_bridge_get_current_state (1 subtest) =======
[05:07:20] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[05:07:20] ======== [PASSED] drm_test_bridge_get_current_state ========
[05:07:20] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[05:07:20] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[05:07:20] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[05:07:20] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[05:07:20] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[05:07:20] ============== drm_bridge_alloc (2 subtests) ===============
[05:07:20] [PASSED] drm_test_drm_bridge_alloc_basic
[05:07:20] [PASSED] drm_test_drm_bridge_alloc_get_put
[05:07:20] ================ [PASSED] drm_bridge_alloc =================
[05:07:20] ============= drm_bridge_bus_fmt (5 subtests) ==============
[05:07:20] [PASSED] drm_test_bridge_rgb_yuv_rgb
[05:07:20] [PASSED] drm_test_bridge_must_convert_to_yuv444
[05:07:20] [PASSED] drm_test_bridge_hdmi_auto_rgb
[05:07:20] [PASSED] drm_test_bridge_auto_first
[05:07:20] [PASSED] drm_test_bridge_rgb_yuv_no_path
[05:07:20] =============== [PASSED] drm_bridge_bus_fmt ================
[05:07:20] ============= drm_cmdline_parser (40 subtests) =============
[05:07:20] [PASSED] drm_test_cmdline_force_d_only
[05:07:20] [PASSED] drm_test_cmdline_force_D_only_dvi
[05:07:20] [PASSED] drm_test_cmdline_force_D_only_hdmi
[05:07:20] [PASSED] drm_test_cmdline_force_D_only_not_digital
[05:07:20] [PASSED] drm_test_cmdline_force_e_only
[05:07:20] [PASSED] drm_test_cmdline_res
[05:07:20] [PASSED] drm_test_cmdline_res_vesa
[05:07:20] [PASSED] drm_test_cmdline_res_vesa_rblank
[05:07:20] [PASSED] drm_test_cmdline_res_rblank
[05:07:20] [PASSED] drm_test_cmdline_res_bpp
[05:07:20] [PASSED] drm_test_cmdline_res_refresh
[05:07:20] [PASSED] drm_test_cmdline_res_bpp_refresh
[05:07:20] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[05:07:20] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[05:07:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[05:07:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[05:07:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[05:07:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[05:07:20] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[05:07:20] [PASSED] drm_test_cmdline_res_margins_force_on
[05:07:20] [PASSED] drm_test_cmdline_res_vesa_margins
[05:07:20] [PASSED] drm_test_cmdline_name
[05:07:20] [PASSED] drm_test_cmdline_name_bpp
[05:07:20] [PASSED] drm_test_cmdline_name_option
[05:07:20] [PASSED] drm_test_cmdline_name_bpp_option
[05:07:20] [PASSED] drm_test_cmdline_rotate_0
[05:07:20] [PASSED] drm_test_cmdline_rotate_90
[05:07:20] [PASSED] drm_test_cmdline_rotate_180
[05:07:20] [PASSED] drm_test_cmdline_rotate_270
[05:07:20] [PASSED] drm_test_cmdline_hmirror
[05:07:20] [PASSED] drm_test_cmdline_vmirror
[05:07:20] [PASSED] drm_test_cmdline_margin_options
[05:07:20] [PASSED] drm_test_cmdline_multiple_options
[05:07:20] [PASSED] drm_test_cmdline_bpp_extra_and_option
[05:07:20] [PASSED] drm_test_cmdline_extra_and_option
[05:07:20] [PASSED] drm_test_cmdline_freestanding_options
[05:07:20] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[05:07:20] [PASSED] drm_test_cmdline_panel_orientation
[05:07:20] ================ drm_test_cmdline_invalid  =================
[05:07:20] [PASSED] margin_only
[05:07:20] [PASSED] interlace_only
[05:07:20] [PASSED] res_missing_x
[05:07:20] [PASSED] res_missing_y
[05:07:20] [PASSED] res_bad_y
[05:07:20] [PASSED] res_missing_y_bpp
[05:07:20] [PASSED] res_bad_bpp
[05:07:20] [PASSED] res_bad_refresh
[05:07:20] [PASSED] res_bpp_refresh_force_on_off
[05:07:20] [PASSED] res_invalid_mode
[05:07:20] [PASSED] res_bpp_wrong_place_mode
[05:07:20] [PASSED] name_bpp_refresh
[05:07:20] [PASSED] name_refresh
[05:07:20] [PASSED] name_refresh_wrong_mode
[05:07:20] [PASSED] name_refresh_invalid_mode
[05:07:20] [PASSED] rotate_multiple
[05:07:20] [PASSED] rotate_invalid_val
[05:07:20] [PASSED] rotate_truncated
[05:07:20] [PASSED] invalid_option
[05:07:20] [PASSED] invalid_tv_option
[05:07:20] [PASSED] truncated_tv_option
[05:07:20] ============ [PASSED] drm_test_cmdline_invalid =============
[05:07:20] =============== drm_test_cmdline_tv_options  ===============
[05:07:20] [PASSED] NTSC
[05:07:20] [PASSED] NTSC_443
[05:07:20] [PASSED] NTSC_J
[05:07:20] [PASSED] PAL
[05:07:20] [PASSED] PAL_M
[05:07:20] [PASSED] PAL_N
[05:07:20] [PASSED] SECAM
[05:07:20] [PASSED] MONO_525
[05:07:20] [PASSED] MONO_625
[05:07:20] =========== [PASSED] drm_test_cmdline_tv_options ===========
[05:07:20] =============== [PASSED] drm_cmdline_parser ================
[05:07:20] ========== drmm_connector_hdmi_init (20 subtests) ==========
[05:07:20] [PASSED] drm_test_connector_hdmi_init_valid
[05:07:20] [PASSED] drm_test_connector_hdmi_init_bpc_8
[05:07:20] [PASSED] drm_test_connector_hdmi_init_bpc_10
[05:07:20] [PASSED] drm_test_connector_hdmi_init_bpc_12
[05:07:20] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[05:07:20] [PASSED] drm_test_connector_hdmi_init_bpc_null
[05:07:20] [PASSED] drm_test_connector_hdmi_init_formats_empty
[05:07:20] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[05:07:20] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[05:07:20] [PASSED] supported_formats=0x9 yuv420_allowed=1
[05:07:20] [PASSED] supported_formats=0x9 yuv420_allowed=0
[05:07:20] [PASSED] supported_formats=0x5 yuv420_allowed=1
[05:07:20] [PASSED] supported_formats=0x5 yuv420_allowed=0
[05:07:20] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[05:07:20] [PASSED] drm_test_connector_hdmi_init_null_ddc
[05:07:20] [PASSED] drm_test_connector_hdmi_init_null_product
[05:07:20] [PASSED] drm_test_connector_hdmi_init_null_vendor
[05:07:20] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[05:07:20] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[05:07:20] [PASSED] drm_test_connector_hdmi_init_product_valid
[05:07:20] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[05:07:20] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[05:07:20] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[05:07:20] ========= drm_test_connector_hdmi_init_type_valid  =========
[05:07:20] [PASSED] HDMI-A
[05:07:20] [PASSED] HDMI-B
[05:07:20] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[05:07:20] ======== drm_test_connector_hdmi_init_type_invalid  ========
[05:07:20] [PASSED] Unknown
[05:07:20] [PASSED] VGA
[05:07:20] [PASSED] DVI-I
[05:07:20] [PASSED] DVI-D
[05:07:20] [PASSED] DVI-A
[05:07:20] [PASSED] Composite
[05:07:20] [PASSED] SVIDEO
[05:07:20] [PASSED] LVDS
[05:07:20] [PASSED] Component
[05:07:20] [PASSED] DIN
[05:07:20] [PASSED] DP
[05:07:20] [PASSED] TV
[05:07:20] [PASSED] eDP
[05:07:20] [PASSED] Virtual
[05:07:20] [PASSED] DSI
[05:07:20] [PASSED] DPI
[05:07:20] [PASSED] Writeback
[05:07:20] [PASSED] SPI
[05:07:20] [PASSED] USB
[05:07:20] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[05:07:20] ============ [PASSED] drmm_connector_hdmi_init =============
[05:07:20] ============= drmm_connector_init (3 subtests) =============
[05:07:20] [PASSED] drm_test_drmm_connector_init
[05:07:20] [PASSED] drm_test_drmm_connector_init_null_ddc
[05:07:20] ========= drm_test_drmm_connector_init_type_valid  =========
[05:07:20] [PASSED] Unknown
[05:07:20] [PASSED] VGA
[05:07:20] [PASSED] DVI-I
[05:07:20] [PASSED] DVI-D
[05:07:20] [PASSED] DVI-A
[05:07:20] [PASSED] Composite
[05:07:20] [PASSED] SVIDEO
[05:07:20] [PASSED] LVDS
[05:07:20] [PASSED] Component
[05:07:20] [PASSED] DIN
[05:07:20] [PASSED] DP
[05:07:20] [PASSED] HDMI-A
[05:07:20] [PASSED] HDMI-B
[05:07:20] [PASSED] TV
[05:07:20] [PASSED] eDP
[05:07:20] [PASSED] Virtual
[05:07:20] [PASSED] DSI
[05:07:20] [PASSED] DPI
[05:07:20] [PASSED] Writeback
[05:07:20] [PASSED] SPI
[05:07:20] [PASSED] USB
[05:07:20] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[05:07:20] =============== [PASSED] drmm_connector_init ===============
[05:07:20] ========= drm_connector_dynamic_init (6 subtests) ==========
[05:07:20] [PASSED] drm_test_drm_connector_dynamic_init
[05:07:20] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[05:07:20] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[05:07:20] [PASSED] drm_test_drm_connector_dynamic_init_properties
[05:07:20] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[05:07:20] [PASSED] Unknown
[05:07:20] [PASSED] VGA
[05:07:20] [PASSED] DVI-I
[05:07:20] [PASSED] DVI-D
[05:07:20] [PASSED] DVI-A
[05:07:20] [PASSED] Composite
[05:07:20] [PASSED] SVIDEO
[05:07:20] [PASSED] LVDS
[05:07:20] [PASSED] Component
[05:07:20] [PASSED] DIN
[05:07:20] [PASSED] DP
[05:07:20] [PASSED] HDMI-A
[05:07:20] [PASSED] HDMI-B
[05:07:20] [PASSED] TV
[05:07:20] [PASSED] eDP
[05:07:20] [PASSED] Virtual
[05:07:20] [PASSED] DSI
[05:07:20] [PASSED] DPI
[05:07:20] [PASSED] Writeback
[05:07:20] [PASSED] SPI
[05:07:20] [PASSED] USB
[05:07:20] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[05:07:20] ======== drm_test_drm_connector_dynamic_init_name  =========
[05:07:20] [PASSED] Unknown
[05:07:20] [PASSED] VGA
[05:07:20] [PASSED] DVI-I
[05:07:20] [PASSED] DVI-D
[05:07:20] [PASSED] DVI-A
[05:07:20] [PASSED] Composite
[05:07:20] [PASSED] SVIDEO
[05:07:20] [PASSED] LVDS
[05:07:20] [PASSED] Component
[05:07:20] [PASSED] DIN
[05:07:20] [PASSED] DP
[05:07:20] [PASSED] HDMI-A
[05:07:20] [PASSED] HDMI-B
[05:07:20] [PASSED] TV
[05:07:20] [PASSED] eDP
[05:07:20] [PASSED] Virtual
[05:07:20] [PASSED] DSI
[05:07:20] [PASSED] DPI
[05:07:20] [PASSED] Writeback
[05:07:20] [PASSED] SPI
[05:07:20] [PASSED] USB
[05:07:20] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[05:07:20] =========== [PASSED] drm_connector_dynamic_init ============
[05:07:20] ==== drm_connector_dynamic_register_early (4 subtests) =====
[05:07:20] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[05:07:20] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[05:07:20] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[05:07:20] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[05:07:20] ====== [PASSED] drm_connector_dynamic_register_early =======
[05:07:20] ======= drm_connector_dynamic_register (7 subtests) ========
[05:07:20] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[05:07:20] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[05:07:20] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[05:07:20] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[05:07:20] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[05:07:20] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[05:07:20] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[05:07:20] ========= [PASSED] drm_connector_dynamic_register ==========
[05:07:20] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[05:07:20] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[05:07:20] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[05:07:20] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[05:07:20] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[05:07:20] ========== drm_test_get_tv_mode_from_name_valid  ===========
[05:07:20] [PASSED] NTSC
[05:07:20] [PASSED] NTSC-443
[05:07:20] [PASSED] NTSC-J
[05:07:20] [PASSED] PAL
[05:07:20] [PASSED] PAL-M
[05:07:20] [PASSED] PAL-N
[05:07:20] [PASSED] SECAM
[05:07:20] [PASSED] Mono
[05:07:20] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[05:07:20] [PASSED] drm_test_get_tv_mode_from_name_truncated
[05:07:20] ============ [PASSED] drm_get_tv_mode_from_name ============
[05:07:20] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[05:07:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[05:07:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[05:07:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[05:07:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[05:07:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[05:07:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[05:07:20] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[05:07:20] [PASSED] VIC 96
[05:07:20] [PASSED] VIC 97
[05:07:20] [PASSED] VIC 101
[05:07:20] [PASSED] VIC 102
[05:07:20] [PASSED] VIC 106
[05:07:20] [PASSED] VIC 107
[05:07:20] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[05:07:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[05:07:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[05:07:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[05:07:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[05:07:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[05:07:20] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[05:07:20] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[05:07:20] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[05:07:20] [PASSED] Automatic
[05:07:20] [PASSED] Full
[05:07:20] [PASSED] Limited 16:235
[05:07:20] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[05:07:20] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[05:07:20] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[05:07:20] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[05:07:20] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[05:07:20] [PASSED] RGB
[05:07:20] [PASSED] YUV 4:2:0
[05:07:20] [PASSED] YUV 4:2:2
[05:07:20] [PASSED] YUV 4:4:4
[05:07:20] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[05:07:20] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[05:07:20] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[05:07:20] ============= drm_damage_helper (21 subtests) ==============
[05:07:20] [PASSED] drm_test_damage_iter_no_damage
[05:07:20] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[05:07:20] [PASSED] drm_test_damage_iter_no_damage_src_moved
[05:07:20] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[05:07:20] [PASSED] drm_test_damage_iter_no_damage_not_visible
[05:07:20] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[05:07:20] [PASSED] drm_test_damage_iter_no_damage_no_fb
[05:07:20] [PASSED] drm_test_damage_iter_simple_damage
[05:07:20] [PASSED] drm_test_damage_iter_single_damage
[05:07:20] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[05:07:20] [PASSED] drm_test_damage_iter_single_damage_outside_src
[05:07:20] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[05:07:20] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[05:07:20] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[05:07:20] [PASSED] drm_test_damage_iter_single_damage_src_moved
[05:07:20] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[05:07:20] [PASSED] drm_test_damage_iter_damage
[05:07:20] [PASSED] drm_test_damage_iter_damage_one_intersect
[05:07:20] [PASSED] drm_test_damage_iter_damage_one_outside
[05:07:20] [PASSED] drm_test_damage_iter_damage_src_moved
[05:07:20] [PASSED] drm_test_damage_iter_damage_not_visible
[05:07:20] ================ [PASSED] drm_damage_helper ================
[05:07:20] ============== drm_dp_mst_helper (3 subtests) ==============
[05:07:20] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[05:07:20] [PASSED] Clock 154000 BPP 30 DSC disabled
[05:07:20] [PASSED] Clock 234000 BPP 30 DSC disabled
[05:07:20] [PASSED] Clock 297000 BPP 24 DSC disabled
[05:07:20] [PASSED] Clock 332880 BPP 24 DSC enabled
[05:07:20] [PASSED] Clock 324540 BPP 24 DSC enabled
[05:07:20] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[05:07:20] ============== drm_test_dp_mst_calc_pbn_div  ===============
[05:07:20] [PASSED] Link rate 2000000 lane count 4
[05:07:20] [PASSED] Link rate 2000000 lane count 2
[05:07:20] [PASSED] Link rate 2000000 lane count 1
[05:07:20] [PASSED] Link rate 1350000 lane count 4
[05:07:20] [PASSED] Link rate 1350000 lane count 2
[05:07:20] [PASSED] Link rate 1350000 lane count 1
[05:07:20] [PASSED] Link rate 1000000 lane count 4
[05:07:20] [PASSED] Link rate 1000000 lane count 2
[05:07:20] [PASSED] Link rate 1000000 lane count 1
[05:07:20] [PASSED] Link rate 810000 lane count 4
[05:07:20] [PASSED] Link rate 810000 lane count 2
[05:07:20] [PASSED] Link rate 810000 lane count 1
[05:07:20] [PASSED] Link rate 540000 lane count 4
[05:07:20] [PASSED] Link rate 540000 lane count 2
[05:07:20] [PASSED] Link rate 540000 lane count 1
[05:07:20] [PASSED] Link rate 270000 lane count 4
[05:07:20] [PASSED] Link rate 270000 lane count 2
[05:07:20] [PASSED] Link rate 270000 lane count 1
[05:07:20] [PASSED] Link rate 162000 lane count 4
[05:07:20] [PASSED] Link rate 162000 lane count 2
[05:07:20] [PASSED] Link rate 162000 lane count 1
[05:07:20] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[05:07:20] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[05:07:20] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[05:07:20] [PASSED] DP_POWER_UP_PHY with port number
[05:07:20] [PASSED] DP_POWER_DOWN_PHY with port number
[05:07:20] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[05:07:20] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[05:07:20] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[05:07:20] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[05:07:20] [PASSED] DP_QUERY_PAYLOAD with port number
[05:07:20] [PASSED] DP_QUERY_PAYLOAD with VCPI
[05:07:20] [PASSED] DP_REMOTE_DPCD_READ with port number
[05:07:20] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[05:07:20] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[05:07:20] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[05:07:20] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[05:07:20] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[05:07:20] [PASSED] DP_REMOTE_I2C_READ with port number
[05:07:20] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[05:07:20] [PASSED] DP_REMOTE_I2C_READ with transactions array
[05:07:20] [PASSED] DP_REMOTE_I2C_WRITE with port number
[05:07:20] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[05:07:20] [PASSED] DP_REMOTE_I2C_WRITE with data array
[05:07:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[05:07:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[05:07:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[05:07:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[05:07:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[05:07:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[05:07:20] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[05:07:20] ================ [PASSED] drm_dp_mst_helper ================
[05:07:20] ================== drm_exec (7 subtests) ===================
[05:07:20] [PASSED] sanitycheck
[05:07:20] [PASSED] test_lock
[05:07:20] [PASSED] test_lock_unlock
[05:07:20] [PASSED] test_duplicates
[05:07:20] [PASSED] test_prepare
[05:07:20] [PASSED] test_prepare_array
[05:07:20] [PASSED] test_multiple_loops
[05:07:20] ==================== [PASSED] drm_exec =====================
[05:07:20] =========== drm_format_helper_test (17 subtests) ===========
[05:07:20] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[05:07:20] [PASSED] single_pixel_source_buffer
[05:07:20] [PASSED] single_pixel_clip_rectangle
[05:07:20] [PASSED] well_known_colors
[05:07:20] [PASSED] destination_pitch
[05:07:20] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[05:07:20] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[05:07:20] [PASSED] single_pixel_source_buffer
[05:07:20] [PASSED] single_pixel_clip_rectangle
[05:07:20] [PASSED] well_known_colors
[05:07:20] [PASSED] destination_pitch
[05:07:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[05:07:20] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[05:07:20] [PASSED] single_pixel_source_buffer
[05:07:20] [PASSED] single_pixel_clip_rectangle
[05:07:20] [PASSED] well_known_colors
[05:07:20] [PASSED] destination_pitch
[05:07:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[05:07:20] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[05:07:20] [PASSED] single_pixel_source_buffer
[05:07:20] [PASSED] single_pixel_clip_rectangle
[05:07:20] [PASSED] well_known_colors
[05:07:20] [PASSED] destination_pitch
[05:07:20] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[05:07:20] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[05:07:20] [PASSED] single_pixel_source_buffer
[05:07:20] [PASSED] single_pixel_clip_rectangle
[05:07:20] [PASSED] well_known_colors
[05:07:20] [PASSED] destination_pitch
[05:07:20] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[05:07:20] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[05:07:20] [PASSED] single_pixel_source_buffer
[05:07:20] [PASSED] single_pixel_clip_rectangle
[05:07:20] [PASSED] well_known_colors
[05:07:20] [PASSED] destination_pitch
[05:07:20] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[05:07:20] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[05:07:20] [PASSED] single_pixel_source_buffer
[05:07:20] [PASSED] single_pixel_clip_rectangle
[05:07:20] [PASSED] well_known_colors
[05:07:20] [PASSED] destination_pitch
[05:07:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[05:07:20] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[05:07:20] [PASSED] single_pixel_source_buffer
[05:07:20] [PASSED] single_pixel_clip_rectangle
[05:07:20] [PASSED] well_known_colors
[05:07:20] [PASSED] destination_pitch
[05:07:20] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[05:07:20] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[05:07:20] [PASSED] single_pixel_source_buffer
[05:07:20] [PASSED] single_pixel_clip_rectangle
[05:07:20] [PASSED] well_known_colors
[05:07:20] [PASSED] destination_pitch
[05:07:20] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[05:07:20] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[05:07:20] [PASSED] single_pixel_source_buffer
[05:07:20] [PASSED] single_pixel_clip_rectangle
[05:07:20] [PASSED] well_known_colors
[05:07:20] [PASSED] destination_pitch
[05:07:20] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[05:07:20] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[05:07:20] [PASSED] single_pixel_source_buffer
[05:07:20] [PASSED] single_pixel_clip_rectangle
[05:07:20] [PASSED] well_known_colors
[05:07:20] [PASSED] destination_pitch
[05:07:20] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[05:07:20] ============== drm_test_fb_xrgb8888_to_mono  ===============
[05:07:20] [PASSED] single_pixel_source_buffer
[05:07:20] [PASSED] single_pixel_clip_rectangle
[05:07:20] [PASSED] well_known_colors
[05:07:20] [PASSED] destination_pitch
[05:07:20] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[05:07:20] ==================== drm_test_fb_swab  =====================
[05:07:20] [PASSED] single_pixel_source_buffer
[05:07:20] [PASSED] single_pixel_clip_rectangle
[05:07:20] [PASSED] well_known_colors
[05:07:20] [PASSED] destination_pitch
[05:07:20] ================ [PASSED] drm_test_fb_swab =================
[05:07:20] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[05:07:20] [PASSED] single_pixel_source_buffer
[05:07:20] [PASSED] single_pixel_clip_rectangle
[05:07:20] [PASSED] well_known_colors
[05:07:20] [PASSED] destination_pitch
[05:07:20] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[05:07:20] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[05:07:20] [PASSED] single_pixel_source_buffer
[05:07:20] [PASSED] single_pixel_clip_rectangle
[05:07:20] [PASSED] well_known_colors
[05:07:20] [PASSED] destination_pitch
[05:07:20] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[05:07:20] ================= drm_test_fb_clip_offset  =================
[05:07:20] [PASSED] pass through
[05:07:20] [PASSED] horizontal offset
[05:07:20] [PASSED] vertical offset
[05:07:20] [PASSED] horizontal and vertical offset
[05:07:20] [PASSED] horizontal offset (custom pitch)
[05:07:20] [PASSED] vertical offset (custom pitch)
[05:07:20] [PASSED] horizontal and vertical offset (custom pitch)
[05:07:20] ============= [PASSED] drm_test_fb_clip_offset =============
[05:07:20] =================== drm_test_fb_memcpy  ====================
[05:07:20] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[05:07:20] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[05:07:20] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[05:07:20] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[05:07:20] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[05:07:20] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[05:07:20] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[05:07:20] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[05:07:20] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[05:07:20] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[05:07:20] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[05:07:20] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[05:07:20] =============== [PASSED] drm_test_fb_memcpy ================
[05:07:20] ============= [PASSED] drm_format_helper_test ==============
[05:07:20] ================= drm_format (18 subtests) =================
[05:07:20] [PASSED] drm_test_format_block_width_invalid
[05:07:20] [PASSED] drm_test_format_block_width_one_plane
[05:07:20] [PASSED] drm_test_format_block_width_two_plane
[05:07:20] [PASSED] drm_test_format_block_width_three_plane
[05:07:20] [PASSED] drm_test_format_block_width_tiled
[05:07:20] [PASSED] drm_test_format_block_height_invalid
[05:07:20] [PASSED] drm_test_format_block_height_one_plane
[05:07:20] [PASSED] drm_test_format_block_height_two_plane
[05:07:20] [PASSED] drm_test_format_block_height_three_plane
[05:07:20] [PASSED] drm_test_format_block_height_tiled
[05:07:20] [PASSED] drm_test_format_min_pitch_invalid
[05:07:20] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[05:07:20] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[05:07:20] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[05:07:20] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[05:07:20] [PASSED] drm_test_format_min_pitch_two_plane
[05:07:20] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[05:07:20] [PASSED] drm_test_format_min_pitch_tiled
[05:07:20] =================== [PASSED] drm_format ====================
[05:07:20] ============== drm_framebuffer (10 subtests) ===============
[05:07:20] ========== drm_test_framebuffer_check_src_coords  ==========
[05:07:20] [PASSED] Success: source fits into fb
[05:07:20] [PASSED] Fail: overflowing fb with x-axis coordinate
[05:07:20] [PASSED] Fail: overflowing fb with y-axis coordinate
[05:07:20] [PASSED] Fail: overflowing fb with source width
[05:07:20] [PASSED] Fail: overflowing fb with source height
[05:07:20] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[05:07:20] [PASSED] drm_test_framebuffer_cleanup
[05:07:20] =============== drm_test_framebuffer_create  ===============
[05:07:20] [PASSED] ABGR8888 normal sizes
[05:07:20] [PASSED] ABGR8888 max sizes
[05:07:20] [PASSED] ABGR8888 pitch greater than min required
[05:07:20] [PASSED] ABGR8888 pitch less than min required
[05:07:20] [PASSED] ABGR8888 Invalid width
[05:07:20] [PASSED] ABGR8888 Invalid buffer handle
[05:07:20] [PASSED] No pixel format
[05:07:20] [PASSED] ABGR8888 Width 0
[05:07:20] [PASSED] ABGR8888 Height 0
[05:07:20] [PASSED] ABGR8888 Out of bound height * pitch combination
[05:07:20] [PASSED] ABGR8888 Large buffer offset
[05:07:20] [PASSED] ABGR8888 Buffer offset for inexistent plane
[05:07:20] [PASSED] ABGR8888 Invalid flag
[05:07:20] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[05:07:20] [PASSED] ABGR8888 Valid buffer modifier
[05:07:20] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[05:07:20] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[05:07:20] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[05:07:20] [PASSED] NV12 Normal sizes
[05:07:20] [PASSED] NV12 Max sizes
[05:07:20] [PASSED] NV12 Invalid pitch
[05:07:20] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[05:07:20] [PASSED] NV12 different  modifier per-plane
[05:07:20] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[05:07:20] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[05:07:20] [PASSED] NV12 Modifier for inexistent plane
[05:07:20] [PASSED] NV12 Handle for inexistent plane
[05:07:20] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[05:07:20] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[05:07:20] [PASSED] YVU420 Normal sizes
[05:07:20] [PASSED] YVU420 Max sizes
[05:07:20] [PASSED] YVU420 Invalid pitch
[05:07:20] [PASSED] YVU420 Different pitches
[05:07:20] [PASSED] YVU420 Different buffer offsets/pitches
[05:07:20] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[05:07:20] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[05:07:20] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[05:07:20] [PASSED] YVU420 Valid modifier
[05:07:20] [PASSED] YVU420 Different modifiers per plane
[05:07:20] [PASSED] YVU420 Modifier for inexistent plane
[05:07:20] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[05:07:20] [PASSED] X0L2 Normal sizes
[05:07:20] [PASSED] X0L2 Max sizes
[05:07:20] [PASSED] X0L2 Invalid pitch
[05:07:20] [PASSED] X0L2 Pitch greater than minimum required
[05:07:20] [PASSED] X0L2 Handle for inexistent plane
[05:07:20] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[05:07:20] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[05:07:20] [PASSED] X0L2 Valid modifier
[05:07:20] [PASSED] X0L2 Modifier for inexistent plane
[05:07:20] =========== [PASSED] drm_test_framebuffer_create ===========
[05:07:20] [PASSED] drm_test_framebuffer_free
[05:07:20] [PASSED] drm_test_framebuffer_init
[05:07:20] [PASSED] drm_test_framebuffer_init_bad_format
[05:07:20] [PASSED] drm_test_framebuffer_init_dev_mismatch
[05:07:20] [PASSED] drm_test_framebuffer_lookup
[05:07:20] [PASSED] drm_test_framebuffer_lookup_inexistent
[05:07:20] [PASSED] drm_test_framebuffer_modifiers_not_supported
[05:07:20] ================= [PASSED] drm_framebuffer =================
[05:07:20] ================ drm_gem_shmem (8 subtests) ================
[05:07:20] [PASSED] drm_gem_shmem_test_obj_create
[05:07:20] [PASSED] drm_gem_shmem_test_obj_create_private
[05:07:20] [PASSED] drm_gem_shmem_test_pin_pages
[05:07:20] [PASSED] drm_gem_shmem_test_vmap
[05:07:20] [PASSED] drm_gem_shmem_test_get_sg_table
[05:07:20] [PASSED] drm_gem_shmem_test_get_pages_sgt
[05:07:20] [PASSED] drm_gem_shmem_test_madvise
[05:07:20] [PASSED] drm_gem_shmem_test_purge
[05:07:20] ================== [PASSED] drm_gem_shmem ==================
[05:07:20] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[05:07:20] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[05:07:20] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[05:07:20] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[05:07:20] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[05:07:20] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[05:07:20] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[05:07:20] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[05:07:20] [PASSED] Automatic
[05:07:20] [PASSED] Full
[05:07:20] [PASSED] Limited 16:235
[05:07:20] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[05:07:20] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[05:07:20] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[05:07:20] [PASSED] drm_test_check_disable_connector
[05:07:20] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[05:07:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[05:07:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[05:07:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[05:07:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[05:07:20] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[05:07:20] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[05:07:20] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[05:07:20] [PASSED] drm_test_check_output_bpc_dvi
[05:07:20] [PASSED] drm_test_check_output_bpc_format_vic_1
[05:07:20] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[05:07:20] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[05:07:20] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[05:07:20] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[05:07:20] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[05:07:20] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[05:07:20] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[05:07:20] ============ drm_test_check_hdmi_color_format  =============
[05:07:20] [PASSED] AUTO -> RGB
[05:07:20] [PASSED] YCBCR422 -> YUV422
[05:07:20] [PASSED] YCBCR420 -> YUV420
[05:07:20] [PASSED] YCBCR444 -> YUV444
[05:07:20] [PASSED] RGB -> RGB
[05:07:20] ======== [PASSED] drm_test_check_hdmi_color_format =========
[05:07:20] ======== drm_test_check_hdmi_color_format_420_only  ========
[05:07:20] [PASSED] RGB should fail
[05:07:20] [PASSED] YUV444 should fail
[05:07:20] [PASSED] YUV422 should fail
[05:07:20] [PASSED] YUV420 should work
[05:07:20] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[05:07:20] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[05:07:20] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[05:07:20] [PASSED] drm_test_check_broadcast_rgb_value
[05:07:20] [PASSED] drm_test_check_bpc_8_value
[05:07:20] [PASSED] drm_test_check_bpc_10_value
[05:07:20] [PASSED] drm_test_check_bpc_12_value
[05:07:20] [PASSED] drm_test_check_format_value
[05:07:20] [PASSED] drm_test_check_tmds_char_value
[05:07:20] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[05:07:20] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[05:07:20] [PASSED] drm_test_check_mode_valid
[05:07:20] [PASSED] drm_test_check_mode_valid_reject
[05:07:20] [PASSED] drm_test_check_mode_valid_reject_rate
[05:07:20] [PASSED] drm_test_check_mode_valid_reject_max_clock
[05:07:20] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[05:07:20] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[05:07:20] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[05:07:20] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[05:07:20] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[05:07:20] [PASSED] drm_test_check_infoframes
[05:07:20] [PASSED] drm_test_check_reject_avi_infoframe
[05:07:20] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[05:07:20] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[05:07:20] [PASSED] drm_test_check_reject_audio_infoframe
[05:07:20] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[05:07:20] ================= drm_managed (2 subtests) =================
[05:07:20] [PASSED] drm_test_managed_release_action
[05:07:20] [PASSED] drm_test_managed_run_action
[05:07:20] =================== [PASSED] drm_managed ===================
[05:07:20] =================== drm_mm (6 subtests) ====================
[05:07:20] [PASSED] drm_test_mm_init
[05:07:20] [PASSED] drm_test_mm_debug
[05:07:20] [PASSED] drm_test_mm_align32
[05:07:20] [PASSED] drm_test_mm_align64
[05:07:20] [PASSED] drm_test_mm_lowest
[05:07:20] [PASSED] drm_test_mm_highest
[05:07:20] ===================== [PASSED] drm_mm ======================
[05:07:20] ============= drm_modes_analog_tv (5 subtests) =============
[05:07:20] [PASSED] drm_test_modes_analog_tv_mono_576i
[05:07:20] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[05:07:20] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[05:07:20] [PASSED] drm_test_modes_analog_tv_pal_576i
[05:07:20] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[05:07:20] =============== [PASSED] drm_modes_analog_tv ===============
[05:07:20] ============== drm_plane_helper (2 subtests) ===============
[05:07:20] =============== drm_test_check_plane_state  ================
[05:07:20] [PASSED] clipping_simple
[05:07:20] [PASSED] clipping_rotate_reflect
[05:07:20] [PASSED] positioning_simple
[05:07:20] [PASSED] upscaling
[05:07:20] [PASSED] downscaling
[05:07:20] [PASSED] rounding1
[05:07:20] [PASSED] rounding2
[05:07:20] [PASSED] rounding3
[05:07:20] [PASSED] rounding4
[05:07:20] =========== [PASSED] drm_test_check_plane_state ============
[05:07:20] =========== drm_test_check_invalid_plane_state  ============
[05:07:20] [PASSED] positioning_invalid
[05:07:20] [PASSED] upscaling_invalid
[05:07:20] [PASSED] downscaling_invalid
[05:07:20] ======= [PASSED] drm_test_check_invalid_plane_state ========
[05:07:20] ================ [PASSED] drm_plane_helper =================
[05:07:20] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[05:07:20] ====== drm_test_connector_helper_tv_get_modes_check  =======
[05:07:20] [PASSED] None
[05:07:20] [PASSED] PAL
[05:07:20] [PASSED] NTSC
[05:07:20] [PASSED] Both, NTSC Default
[05:07:20] [PASSED] Both, PAL Default
[05:07:20] [PASSED] Both, NTSC Default, with PAL on command-line
[05:07:20] [PASSED] Both, PAL Default, with NTSC on command-line
[05:07:20] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[05:07:20] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[05:07:20] ================== drm_rect (9 subtests) ===================
[05:07:20] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[05:07:20] [PASSED] drm_test_rect_clip_scaled_not_clipped
[05:07:20] [PASSED] drm_test_rect_clip_scaled_clipped
[05:07:20] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[05:07:20] ================= drm_test_rect_intersect  =================
[05:07:20] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[05:07:20] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[05:07:20] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[05:07:20] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[05:07:20] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[05:07:20] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[05:07:20] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[05:07:20] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[05:07:20] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[05:07:20] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[05:07:20] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[05:07:20] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[05:07:20] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[05:07:20] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[05:07:20] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[05:07:20] ============= [PASSED] drm_test_rect_intersect =============
[05:07:20] ================ drm_test_rect_calc_hscale  ================
[05:07:20] [PASSED] normal use
[05:07:20] [PASSED] out of max range
[05:07:20] [PASSED] out of min range
[05:07:20] [PASSED] zero dst
[05:07:20] [PASSED] negative src
[05:07:20] [PASSED] negative dst
[05:07:20] ============ [PASSED] drm_test_rect_calc_hscale ============
[05:07:20] ================ drm_test_rect_calc_vscale  ================
[05:07:20] [PASSED] normal use
[05:07:20] [PASSED] out of max range
[05:07:20] [PASSED] out of min range
[05:07:20] [PASSED] zero dst
[05:07:20] [PASSED] negative src
[05:07:20] [PASSED] negative dst
[05:07:20] ============ [PASSED] drm_test_rect_calc_vscale ============
[05:07:20] ================== drm_test_rect_rotate  ===================
[05:07:20] [PASSED] reflect-x
[05:07:20] [PASSED] reflect-y
[05:07:20] [PASSED] rotate-0
[05:07:20] [PASSED] rotate-90
[05:07:20] [PASSED] rotate-180
[05:07:20] [PASSED] rotate-270
[05:07:20] ============== [PASSED] drm_test_rect_rotate ===============
[05:07:20] ================ drm_test_rect_rotate_inv  =================
[05:07:20] [PASSED] reflect-x
[05:07:20] [PASSED] reflect-y
[05:07:20] [PASSED] rotate-0
[05:07:20] [PASSED] rotate-90
[05:07:20] [PASSED] rotate-180
[05:07:20] [PASSED] rotate-270
[05:07:20] ============ [PASSED] drm_test_rect_rotate_inv =============
[05:07:20] ==================== [PASSED] drm_rect =====================
[05:07:20] ============ drm_sysfb_modeset_test (1 subtest) ============
[05:07:20] ============ drm_test_sysfb_build_fourcc_list  =============
[05:07:20] [PASSED] no native formats
[05:07:20] [PASSED] XRGB8888 as native format
[05:07:20] [PASSED] remove duplicates
[05:07:20] [PASSED] convert alpha formats
[05:07:20] [PASSED] random formats
[05:07:20] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[05:07:20] ============= [PASSED] drm_sysfb_modeset_test ==============
[05:07:20] ================== drm_fixp (2 subtests) ===================
[05:07:20] [PASSED] drm_test_int2fixp
[05:07:20] [PASSED] drm_test_sm2fixp
[05:07:20] ==================== [PASSED] drm_fixp =====================
[05:07:20] ============================================================
[05:07:20] Testing complete. Ran 637 tests: passed: 637
[05:07:20] Elapsed time: 26.510s total, 1.813s configuring, 24.532s building, 0.142s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[05:07:20] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:07:22] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:07:31] Starting KUnit Kernel (1/1)...
[05:07:31] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:07:31] ================= ttm_device (5 subtests) ==================
[05:07:31] [PASSED] ttm_device_init_basic
[05:07:31] [PASSED] ttm_device_init_multiple
[05:07:31] [PASSED] ttm_device_fini_basic
[05:07:31] [PASSED] ttm_device_init_no_vma_man
[05:07:31] ================== ttm_device_init_pools  ==================
[05:07:31] [PASSED] No DMA allocations, no DMA32 required
[05:07:31] [PASSED] DMA allocations, DMA32 required
[05:07:31] [PASSED] No DMA allocations, DMA32 required
[05:07:31] [PASSED] DMA allocations, no DMA32 required
[05:07:31] ============== [PASSED] ttm_device_init_pools ==============
[05:07:31] =================== [PASSED] ttm_device ====================
[05:07:31] ================== ttm_pool (8 subtests) ===================
[05:07:31] ================== ttm_pool_alloc_basic  ===================
[05:07:31] [PASSED] One page
[05:07:31] [PASSED] More than one page
[05:07:31] [PASSED] Above the allocation limit
[05:07:31] [PASSED] One page, with coherent DMA mappings enabled
[05:07:31] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[05:07:31] ============== [PASSED] ttm_pool_alloc_basic ===============
[05:07:31] ============== ttm_pool_alloc_basic_dma_addr  ==============
[05:07:31] [PASSED] One page
[05:07:31] [PASSED] More than one page
[05:07:31] [PASSED] Above the allocation limit
[05:07:31] [PASSED] One page, with coherent DMA mappings enabled
[05:07:31] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[05:07:31] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[05:07:31] [PASSED] ttm_pool_alloc_order_caching_match
[05:07:31] [PASSED] ttm_pool_alloc_caching_mismatch
[05:07:31] [PASSED] ttm_pool_alloc_order_mismatch
[05:07:31] [PASSED] ttm_pool_free_dma_alloc
[05:07:31] [PASSED] ttm_pool_free_no_dma_alloc
[05:07:31] [PASSED] ttm_pool_fini_basic
[05:07:31] ==================== [PASSED] ttm_pool =====================
[05:07:31] ================ ttm_resource (8 subtests) =================
[05:07:31] ================= ttm_resource_init_basic  =================
[05:07:31] [PASSED] Init resource in TTM_PL_SYSTEM
[05:07:31] [PASSED] Init resource in TTM_PL_VRAM
[05:07:31] [PASSED] Init resource in a private placement
[05:07:31] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[05:07:31] ============= [PASSED] ttm_resource_init_basic =============
[05:07:31] [PASSED] ttm_resource_init_pinned
[05:07:31] [PASSED] ttm_resource_fini_basic
[05:07:31] [PASSED] ttm_resource_manager_init_basic
[05:07:31] [PASSED] ttm_resource_manager_usage_basic
[05:07:31] [PASSED] ttm_resource_manager_set_used_basic
[05:07:31] [PASSED] ttm_sys_man_alloc_basic
[05:07:31] [PASSED] ttm_sys_man_free_basic
[05:07:31] ================== [PASSED] ttm_resource ===================
[05:07:31] =================== ttm_tt (15 subtests) ===================
[05:07:31] ==================== ttm_tt_init_basic  ====================
[05:07:31] [PASSED] Page-aligned size
[05:07:31] [PASSED] Extra pages requested
[05:07:31] ================ [PASSED] ttm_tt_init_basic ================
[05:07:31] [PASSED] ttm_tt_init_misaligned
[05:07:31] [PASSED] ttm_tt_fini_basic
[05:07:31] [PASSED] ttm_tt_fini_sg
[05:07:31] [PASSED] ttm_tt_fini_shmem
[05:07:31] [PASSED] ttm_tt_create_basic
[05:07:31] [PASSED] ttm_tt_create_invalid_bo_type
[05:07:31] [PASSED] ttm_tt_create_ttm_exists
[05:07:31] [PASSED] ttm_tt_create_failed
[05:07:31] [PASSED] ttm_tt_destroy_basic
[05:07:31] [PASSED] ttm_tt_populate_null_ttm
[05:07:31] [PASSED] ttm_tt_populate_populated_ttm
[05:07:31] [PASSED] ttm_tt_unpopulate_basic
[05:07:31] [PASSED] ttm_tt_unpopulate_empty_ttm
[05:07:31] [PASSED] ttm_tt_swapin_basic
[05:07:31] ===================== [PASSED] ttm_tt ======================
[05:07:31] =================== ttm_bo (14 subtests) ===================
[05:07:31] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[05:07:31] [PASSED] Cannot be interrupted and sleeps
[05:07:31] [PASSED] Cannot be interrupted, locks straight away
[05:07:31] [PASSED] Can be interrupted, sleeps
[05:07:31] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[05:07:31] [PASSED] ttm_bo_reserve_locked_no_sleep
[05:07:31] [PASSED] ttm_bo_reserve_no_wait_ticket
[05:07:32] [PASSED] ttm_bo_reserve_double_resv
[05:07:32] [PASSED] ttm_bo_reserve_interrupted
[05:07:32] [PASSED] ttm_bo_reserve_deadlock
[05:07:32] [PASSED] ttm_bo_unreserve_basic
[05:07:32] [PASSED] ttm_bo_unreserve_pinned
[05:07:32] [PASSED] ttm_bo_unreserve_bulk
[05:07:32] [PASSED] ttm_bo_fini_basic
[05:07:32] [PASSED] ttm_bo_fini_shared_resv
[05:07:32] [PASSED] ttm_bo_pin_basic
[05:07:32] [PASSED] ttm_bo_pin_unpin_resource
[05:07:32] [PASSED] ttm_bo_multiple_pin_one_unpin
[05:07:32] ===================== [PASSED] ttm_bo ======================
[05:07:32] ============== ttm_bo_validate (22 subtests) ===============
[05:07:32] ============== ttm_bo_init_reserved_sys_man  ===============
[05:07:32] [PASSED] Buffer object for userspace
[05:07:32] [PASSED] Kernel buffer object
[05:07:32] [PASSED] Shared buffer object
[05:07:32] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[05:07:32] ============== ttm_bo_init_reserved_mock_man  ==============
[05:07:32] [PASSED] Buffer object for userspace
[05:07:32] [PASSED] Kernel buffer object
[05:07:32] [PASSED] Shared buffer object
[05:07:32] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[05:07:32] [PASSED] ttm_bo_init_reserved_resv
[05:07:32] ================== ttm_bo_validate_basic  ==================
[05:07:32] [PASSED] Buffer object for userspace
[05:07:32] [PASSED] Kernel buffer object
[05:07:32] [PASSED] Shared buffer object
[05:07:32] ============== [PASSED] ttm_bo_validate_basic ==============
[05:07:32] [PASSED] ttm_bo_validate_invalid_placement
[05:07:32] ============= ttm_bo_validate_same_placement  ==============
[05:07:32] [PASSED] System manager
[05:07:32] [PASSED] VRAM manager
[05:07:32] ========= [PASSED] ttm_bo_validate_same_placement ==========
[05:07:32] [PASSED] ttm_bo_validate_failed_alloc
[05:07:32] [PASSED] ttm_bo_validate_pinned
[05:07:32] [PASSED] ttm_bo_validate_busy_placement
[05:07:32] ================ ttm_bo_validate_multihop  =================
[05:07:32] [PASSED] Buffer object for userspace
[05:07:32] [PASSED] Kernel buffer object
[05:07:32] [PASSED] Shared buffer object
[05:07:32] ============ [PASSED] ttm_bo_validate_multihop =============
[05:07:32] ========== ttm_bo_validate_no_placement_signaled  ==========
[05:07:32] [PASSED] Buffer object in system domain, no page vector
[05:07:32] [PASSED] Buffer object in system domain with an existing page vector
[05:07:32] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[05:07:32] ======== ttm_bo_validate_no_placement_not_signaled  ========
[05:07:32] [PASSED] Buffer object for userspace
[05:07:32] [PASSED] Kernel buffer object
[05:07:32] [PASSED] Shared buffer object
[05:07:32] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[05:07:32] [PASSED] ttm_bo_validate_move_fence_signaled
[05:07:32] ========= ttm_bo_validate_move_fence_not_signaled  =========
[05:07:32] [PASSED] Waits for GPU
[05:07:32] [PASSED] Tries to lock straight away
[05:07:32] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[05:07:32] [PASSED] ttm_bo_validate_swapout
[05:07:32] [PASSED] ttm_bo_validate_happy_evict
[05:07:32] [PASSED] ttm_bo_validate_all_pinned_evict
[05:07:32] [PASSED] ttm_bo_validate_allowed_only_evict
[05:07:32] [PASSED] ttm_bo_validate_deleted_evict
[05:07:32] [PASSED] ttm_bo_validate_busy_domain_evict
[05:07:32] [PASSED] ttm_bo_validate_evict_gutting
[05:07:32] [PASSED] ttm_bo_validate_recrusive_evict
[05:07:32] ================= [PASSED] ttm_bo_validate =================
[05:07:32] ============================================================
[05:07:32] Testing complete. Ran 102 tests: passed: 102
[05:07:32] Elapsed time: 11.865s total, 1.829s configuring, 9.821s building, 0.173s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for DP-HDMI PCON DSC fixes (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 899 bytes --]

== Series Details ==

Series: DP-HDMI PCON DSC fixes (rev2)
URL   : https://patchwork.freedesktop.org/series/171346/
State : success

== Summary ==

CI Bug Log - changes from xe-5575-dc462ab791b686c48545c160ecc81be64f77a846_BAT -> xe-pw-171346v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * IGT: IGT_9049 -> IGT_9050
  * Linux: xe-5575-dc462ab791b686c48545c160ecc81be64f77a846 -> xe-pw-171346v2

  IGT_9049: 9049
  IGT_9050: 9050
  xe-5575-dc462ab791b686c48545c160ecc81be64f77a846: dc462ab791b686c48545c160ecc81be64f77a846
  xe-pw-171346v2: 171346v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/index.html

[-- Attachment #2: Type: text/html, Size: 1461 bytes --]

✓ Xe.CI.FULL: success for DP-HDMI PCON DSC fixes (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 21372 bytes --]

== Series Details ==

Series: DP-HDMI PCON DSC fixes (rev2)
URL   : https://patchwork.freedesktop.org/series/171346/
State : success

== Summary ==

CI Bug Log - changes from xe-5575-dc462ab791b686c48545c160ecc81be64f77a846_FULL -> xe-pw-171346v2_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-171346v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@hotrebind-lateclose:
    - shard-bmg:          [PASS][1] -> [ABORT][2] ([Intel XE#8007]) +2 other tests abort
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5575-dc462ab791b686c48545c160ecc81be64f77a846/shard-bmg-7/igt@core_hotunplug@hotrebind-lateclose.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-2/igt@core_hotunplug@hotrebind-lateclose.html

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#7059] / [Intel XE#7085])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-8/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#1124]) +1 other test skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-4/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#607] / [Intel XE#7361])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-10/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html

  * igt@kms_bw@linear-tiling-3-displays-target-1920x1080p:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#367])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-1/igt@kms_bw@linear-tiling-3-displays-target-1920x1080p.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#3432]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2887]) +3 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-7/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_chamelium_color@ctm-blue-to-red:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#2325] / [Intel XE#7358])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-8/igt@kms_chamelium_color@ctm-blue-to-red.html

  * igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#2252])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-8/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html

  * igt@kms_cursor_crc@cursor-sliding-max-size:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#2320])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-4/igt@kms_cursor_crc@cursor-sliding-max-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [PASS][12] -> [FAIL][13] ([Intel XE#7571])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5575-dc462ab791b686c48545c160ecc81be64f77a846/shard-bmg-4/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-9/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc-ultrajoiner:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#8265])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-9/igt@kms_dsc@dsc-fractional-bpp-with-bpc-ultrajoiner.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-lnl:          [PASS][15] -> [FAIL][16] ([Intel XE#7949])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5575-dc462ab791b686c48545c160ecc81be64f77a846/shard-lnl-5/igt@kms_fbcon_fbt@psr-suspend.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-lnl-3/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3:
    - shard-bmg:          [PASS][17] -> [FAIL][18] ([Intel XE#3321]) +1 other test fail
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5575-dc462ab791b686c48545c160ecc81be64f77a846/shard-bmg-3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-lnl:          [PASS][19] -> [FAIL][20] ([Intel XE#301] / [Intel XE#3149]) +1 other test fail
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5575-dc462ab791b686c48545c160ecc81be64f77a846/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          [PASS][21] -> [FAIL][22] ([Intel XE#301])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5575-dc462ab791b686c48545c160ecc81be64f77a846/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#7178] / [Intel XE#7351])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yuv-linear-to-32bpp-yuv-linear-reflect-x:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#7179])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-1/igt@kms_flip_scaled_crc@flip-32bpp-yuv-linear-to-32bpp-yuv-linear-reflect-x.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#4141]) +4 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-pri-indfb-multidraw:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#2311]) +17 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-argb161616f-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#7061]) +1 other test skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcdrrshdr-argb161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2313]) +15 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#7283]) +2 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-7/igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-lnl:          [PASS][30] -> [FAIL][31] ([Intel XE#8399])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5575-dc462ab791b686c48545c160ecc81be64f77a846/shard-lnl-4/igt@kms_pm_dc@dc6-dpms.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-lnl-4/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#1489]) +2 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-1/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr@pr-sprite-plane-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-8/igt@kms_psr@pr-sprite-plane-onoff.html

  * igt@kms_scaling_modes@scaling-mode-full-aspect:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#2413])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-5/igt@kms_scaling_modes@scaling-mode-full-aspect.html

  * igt@kms_sharpness_filter@invalid-filter-with-plane:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#6503])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-7/igt@kms_sharpness_filter@invalid-filter-with-plane.html

  * igt@kms_vrr@max-min:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#1499])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-1/igt@kms_vrr@max-min.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][37] ([Intel XE#6321] / [Intel XE#8355])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-4/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_evict@evict-threads-small-multi-queue:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#8370])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-5/igt@xe_evict@evict-threads-small-multi-queue.html

  * igt@xe_exec_basic@multigpu-once-null-defer-mmap:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#2322] / [Intel XE#7372]) +2 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-10/igt@xe_exec_basic@multigpu-once-null-defer-mmap.html

  * igt@xe_exec_fault_mode@once-multi-queue-rebind-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#8374]) +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-4/igt@xe_exec_fault_mode@once-multi-queue-rebind-prefetch.html

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-dyn-priority-smem:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#8364]) +12 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-1/igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-dyn-priority-smem.html

  * igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#8378]) +3 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-1/igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr.html

  * igt@xe_multigpu_svm@mgpu-atomic-op-basic:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#6964])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-6/igt@xe_multigpu_svm@mgpu-atomic-op-basic.html

  * igt@xe_page_reclaim@pde-vs-pd:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#7793])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-1/igt@xe_page_reclaim@pde-vs-pd.html

  * igt@xe_pm@d3hot-i2c:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#5742] / [Intel XE#7328] / [Intel XE#7400])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-9/igt@xe_pm@d3hot-i2c.html

  * igt@xe_pxp@pxp-termination-key-update-post-termination-irq:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#4733] / [Intel XE#7417])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-6/igt@xe_pxp@pxp-termination-key-update-post-termination-irq.html

  
#### Possible fixes ####

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-lnl:          [FAIL][47] ([Intel XE#301]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5575-dc462ab791b686c48545c160ecc81be64f77a846/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-bmg:          [SKIP][49] ([Intel XE#7308]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5575-dc462ab791b686c48545c160ecc81be64f77a846/shard-bmg-5/igt@kms_hdmi_inject@inject-audio.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-5/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-lnl:          [SKIP][51] ([Intel XE#8361]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5575-dc462ab791b686c48545c160ecc81be64f77a846/shard-lnl-7/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-lnl-2/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [FAIL][53] ([Intel XE#7397]) -> [PASS][54] +1 other test pass
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5575-dc462ab791b686c48545c160ecc81be64f77a846/shard-lnl-7/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-lnl-1/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_ggtt_init_early:
    - shard-bmg:          [ABORT][55] ([Intel XE#8007]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5575-dc462ab791b686c48545c160ecc81be64f77a846/shard-bmg-9/igt@xe_fault_injection@inject-fault-probe-function-xe_ggtt_init_early.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-1/igt@xe_fault_injection@inject-fault-probe-function-xe_ggtt_init_early.html

  * igt@xe_sriov_scheduling@nonpreempt-engine-resets-normal-priority@numvfs-random-gt0-rcs0:
    - shard-bmg:          [FAIL][57] ([Intel XE#7992]) -> [PASS][58] +2 other tests pass
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5575-dc462ab791b686c48545c160ecc81be64f77a846/shard-bmg-3/igt@xe_sriov_scheduling@nonpreempt-engine-resets-normal-priority@numvfs-random-gt0-rcs0.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-4/igt@xe_sriov_scheduling@nonpreempt-engine-resets-normal-priority@numvfs-random-gt0-rcs0.html

  * igt@xe_sriov_scheduling@nonpreempt-engine-resets-normal-priority@numvfs-random-gt1-vcs0:
    - shard-bmg:          [FAIL][59] ([Intel XE#8340]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5575-dc462ab791b686c48545c160ecc81be64f77a846/shard-bmg-3/igt@xe_sriov_scheduling@nonpreempt-engine-resets-normal-priority@numvfs-random-gt1-vcs0.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-4/igt@xe_sriov_scheduling@nonpreempt-engine-resets-normal-priority@numvfs-random-gt1-vcs0.html

  
#### Warnings ####

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][61] ([Intel XE#3544]) -> [SKIP][62] ([Intel XE#3374] / [Intel XE#3544])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5575-dc462ab791b686c48545c160ecc81be64f77a846/shard-bmg-3/igt@kms_hdr@brightness-with-hdr.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-7/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][63] ([Intel XE#2426] / [Intel XE#5848]) -> [FAIL][64] ([Intel XE#1729] / [Intel XE#7424])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5575-dc462ab791b686c48545c160ecc81be64f77a846/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#5742]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5742
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7308
  [Intel XE#7328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7328
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7361
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7397
  [Intel XE#7400]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7400
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7571
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7949]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7949
  [Intel XE#7992]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7992
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8340
  [Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
  [Intel XE#8361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8361
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8370
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8399


Build changes
-------------

  * IGT: IGT_9049 -> IGT_9050
  * Linux: xe-5575-dc462ab791b686c48545c160ecc81be64f77a846 -> xe-pw-171346v2

  IGT_9049: 9049
  IGT_9050: 9050
  xe-5575-dc462ab791b686c48545c160ecc81be64f77a846: dc462ab791b686c48545c160ecc81be64f77a846
  xe-pw-171346v2: 171346v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171346v2/index.html

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Re: [PATCH v2 0/8] DP-HDMI PCON DSC fixes

[Sharma, Swati2]

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Hi Ankit,

Tested on the NVL platform using the AORUS FO32U2P panel and a BizLink 
(DP to HDMI2.1) dongle.
With your patches, I am now able to achieve 3840x2160 @ 240Hz, which was 
previously being
rejected with a CLOCK_HIGH error without the patches.

Tested-by: Swati Sharma <swati2.sharma@intel.com>

On 11-08-2026 10:12 am, Ankit Nautiyal wrote:
> The PCON mode_valid path currently does not fully account for the bandwidth
> limitations of the PCON <-> HDMI link. The DSC capability between the
> PCON and the HDMI sink also needs to be taken into account, which currently
> isn't. Furthermore, the compressed bpp chosen needs to fit the
> FRL configuration, which is also missing.
>
> This series:
>   - reworks the HDMI DSC helpers so they can be reused across the
>     mode_valid, compute_config and FRL bandwidth check paths
>   - fixes the FRL/TMDS downstream bandwidth checks, and allows
>     PCON DSC modes through the FRL check
>   - Clamps the programmed DSC bpp to the FRL link bandwidth.
>
> Rev2:
>   - Rebase and address comments from Suraj.
>   - Drop drm/i915/dp: Use FRL pair check for the DFP dotclock limit as no
>     longer required.
>
> Ankit Nautiyal (8):
>    drm/i915/hdmi: Split the intel_hdmi_dsc_get_bpp()
>    drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP
>    drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints
>    drm/i915/dp: Use the common downstream bw check in compute_bpc
>    drm/i915/hdmi: Expose DSC min/max bpp helpers
>    drm/i915/hdmi: Add helper to check if DSC chunksize fits the sink
>      limits
>    drm/i915/dp: Allow PCON DSC modes through FRL bw check
>    drm/i915/dp: Clamp PCON DSC bpp to the FRL link bandwidth
>
>   drivers/gpu/drm/i915/display/intel_dp.c   | 144 ++++++++++++++++++----
>   drivers/gpu/drm/i915/display/intel_hdmi.c | 124 ++++++++++++++-----
>   drivers/gpu/drm/i915/display/intel_hdmi.h |   7 +-
>   3 files changed, 218 insertions(+), 57 deletions(-)
>

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Re: [PATCH v2 0/8] DP-HDMI PCON DSC fixes

[Nautiyal, Ankit K]

On 8/21/2026 5:08 PM, Sharma, Swati2 wrote:
>
> Hi Ankit,
>
> Tested on the NVL platform using the AORUS FO32U2P panel and a BizLink 
> (DP to HDMI2.1) dongle.
> With your patches, I am now able to achieve 3840x2160 @ 240Hz, which 
> was previously being
> rejected with a CLOCK_HIGH error without the patches.
>
> Tested-by: Swati Sharma <swati2.sharma@intel.com>
>
Thanks Swati for testing the series and providing your tested-by!


Alex,

Since we discussed converging our work on these paths a while back [1],

I wanted to check if you've had a chance to test this series on your 
Panther Lake / VMM7100 setup, or if you still intend to do so?

Your validation/coverage on the PCON DSC and FRL paths would be great to 
have before we merge.

Thanks,

Ankit


[1] 
https://lore.kernel.org/intel-gfx/20260703232737.4433-1-alexander.kaplan@sms-medipool.de/


> On 11-08-2026 10:12 am, Ankit Nautiyal wrote:
>> The PCON mode_valid path currently does not fully account for the bandwidth
>> limitations of the PCON <-> HDMI link. The DSC capability between the
>> PCON and the HDMI sink also needs to be taken into account, which currently
>> isn't. Furthermore, the compressed bpp chosen needs to fit the
>> FRL configuration, which is also missing.
>>
>> This series:
>>   - reworks the HDMI DSC helpers so they can be reused across the
>>     mode_valid, compute_config and FRL bandwidth check paths
>>   - fixes the FRL/TMDS downstream bandwidth checks, and allows
>>     PCON DSC modes through the FRL check
>>   - Clamps the programmed DSC bpp to the FRL link bandwidth.
>>
>> Rev2:
>>   - Rebase and address comments from Suraj.
>>   - Drop drm/i915/dp: Use FRL pair check for the DFP dotclock limit as no
>>     longer required.
>>
>> Ankit Nautiyal (8):
>>    drm/i915/hdmi: Split the intel_hdmi_dsc_get_bpp()
>>    drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP
>>    drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints
>>    drm/i915/dp: Use the common downstream bw check in compute_bpc
>>    drm/i915/hdmi: Expose DSC min/max bpp helpers
>>    drm/i915/hdmi: Add helper to check if DSC chunksize fits the sink
>>      limits
>>    drm/i915/dp: Allow PCON DSC modes through FRL bw check
>>    drm/i915/dp: Clamp PCON DSC bpp to the FRL link bandwidth
>>
>>   drivers/gpu/drm/i915/display/intel_dp.c   | 144 ++++++++++++++++++----
>>   drivers/gpu/drm/i915/display/intel_hdmi.c | 124 ++++++++++++++-----
>>   drivers/gpu/drm/i915/display/intel_hdmi.h |   7 +-
>>   3 files changed, 218 insertions(+), 57 deletions(-)
>>