Re: [PATCH v7 1/5] drm/xe/ggtt: Assert lower bound of GGTT PTE address

["Lis, Tomasz" <tomasz.lis@intel.com>]

On 2026-10-21 10:57, Piórkowski, Piotr wrote:
> From: Piotr Piórkowski <piotr.piorkowski@intel.com>
>
> Since ggtt->start was introduced, the GGTT range no longer begins at
> address 0, but the PTE accessors still check only the upper bound of
> the address.
>
> Also assert that the address is not below ggtt->start, so that stale or
> miscomputed addresses (e.g. after a VF GGTT shift) are caught as well.
>
> Suggested-by: Tomasz Lis <tomasz.lis@intel.com>
> Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>

Reviewed-by: Tomasz Lis <tomasz.lis@intel.com>

-Tomasz

> ---
>   drivers/gpu/drm/xe/xe_ggtt.c | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> index 773777afc68a2..2d890fe74c1b0 100644
> --- a/drivers/gpu/drm/xe/xe_ggtt.c
> +++ b/drivers/gpu/drm/xe/xe_ggtt.c
> @@ -240,6 +240,7 @@ u64 xe_ggtt_size(struct xe_ggtt *ggtt)
>   static void xe_ggtt_set_pte(struct xe_ggtt *ggtt, u64 addr, u64 pte)
>   {
>   	xe_tile_assert(ggtt->tile, !(addr & XE_PTE_MASK));
> +	xe_tile_assert(ggtt->tile, addr >= ggtt->start);
>   	xe_tile_assert(ggtt->tile, addr < ggtt->start + ggtt->size);
>   
>   	writeq(pte, &ggtt->gsm[addr >> XE_PTE_SHIFT]);
> @@ -254,6 +255,7 @@ static void xe_ggtt_set_pte_and_flush(struct xe_ggtt *ggtt, u64 addr, u64 pte)
>   static u64 xe_ggtt_get_pte(struct xe_ggtt *ggtt, u64 addr)
>   {
>   	xe_tile_assert(ggtt->tile, !(addr & XE_PTE_MASK));
> +	xe_tile_assert(ggtt->tile, addr >= ggtt->start);
>   	xe_tile_assert(ggtt->tile, addr < ggtt->start + ggtt->size);
>   
>   	return readq(&ggtt->gsm[addr >> XE_PTE_SHIFT]);