[PATCH v9 0/8] Use trans push mechanism to generate frame change event

[PATCH v9 0/8] Use trans push mechanism to generate frame change event

[Jouni Högander]

Currently we are using "automatic" frame change event generation. The
event is generated by any access to plane or pipe registers.

We have option to use "PSR PR Frame Change Enable" bit in TRANS_PUSH
register to enable frame change event generation only when doing trans
push. When this bit is set "automatic" frame change event generation
doesn't work anymore. Benfit from this is more controled updates send
by PSR HW.

This patch set is taking trans push mechanism into use.

v9: always do PSR exit on frontbuffer flush for LunarLake and onwards
v8:
  - rebase
  - Wait for idle only after possible send
v7:
  - added bspec references
  - add HAS_PSR_FRAME_CHANGE macro
  - use TRANS_PUSH in instead of TRAN_VRR_CTL
  - "Do not trigger Frame Change events from frontbuffer flush" patch
    already merged
v6: use AND instead of OR in intel_psr_use_trans_push
v5: add missing patch
v4:
  - add intel_psr_use_trans_push to query if TRANS_PUSH is used
  - set DSB_SKIP_WAITS_EN chicken bit when TRANS_PUSH is used
  - Wait for vblank in case of PSR is using trans push
v3:
  - use rmw when enabling disabling transh push for PSR or VRR
  - rely on crtc_state->has_psr/has_vrr to keep trans push enabled
  - modify frontbuffer flush/invalidate to use disable/enable also for
    SU/SF on recent platforms.
  - send push before waiting for vblank
v2: implement intel_vrr_trans_push_enabled_set_clear and use that
    instead of rmw

Jouni Högander (8):
  drm/i915/psr: Add TRANS_PUSH register bit definition for PSR
  drm/i915/psr: Add intel_psr_use_trans_push to query if TRANS_PUSH is
    used
  drm/i915/vrr: Prepare to Use TRANS_PUSH mechanism for PSR frame change
  drm/i915/dsb: Set DSB_SKIP_WAITS_EN chicken bit for LunarLake and
    onwards
  drm/i915/display: Wait for vblank in case of PSR is using trans push
  drm/i915/psr: Wait for idle only after possible send push
  drm/i915/psr: Do PSR exit on frontbuffer flush on LunarLake and
    onwards
  drm/i915/psr: Use TRANS_PUSH to trigger frame change event

 drivers/gpu/drm/i915/display/intel_crtc.c     |  4 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 33 ++++++++++++++--
 drivers/gpu/drm/i915/display/intel_dsb.c      | 15 ++++++--
 drivers/gpu/drm/i915/display/intel_psr.c      | 38 +++++++++++++------
 drivers/gpu/drm/i915/display/intel_psr.h      |  1 +
 drivers/gpu/drm/i915/display/intel_vrr.c      | 29 +++++++++++---
 drivers/gpu/drm/i915/display/intel_vrr.h      |  1 +
 drivers/gpu/drm/i915/display/intel_vrr_regs.h |  1 +
 8 files changed, 96 insertions(+), 26 deletions(-)

-- 
2.43.0

[PATCH v9 1/8] drm/i915/psr: Add TRANS_PUSH register bit definition for PSR

[Jouni Högander]

Add TRANS_PUSH register bit LNL_TRANS_PUSH_PSR_PR_EN definition for PSR
usage.

v2: add bspec reference

Bspec: 69984
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr_regs.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index ba9b9215dc11..a67b2eb125ce 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -97,6 +97,7 @@
 #define TRANS_PUSH(display, trans)		_MMIO_TRANS2((display), (trans), _TRANS_PUSH_A)
 #define   TRANS_PUSH_EN				REG_BIT(31)
 #define   TRANS_PUSH_SEND			REG_BIT(30)
+#define   LNL_TRANS_PUSH_PSR_PR_EN		REG_BIT(16)
 
 #define _TRANS_VRR_VSYNC_A			0x60078
 #define TRANS_VRR_VSYNC(display, trans)		_MMIO_TRANS2((display), (trans), _TRANS_VRR_VSYNC_A)
-- 
2.43.0

[PATCH v9 2/8] drm/i915/psr: Add intel_psr_use_trans_push to query if TRANS_PUSH is used

[Jouni Högander]

This is a preparation to start using trans push as a PSR "Frame Change"
event. It adds intel_psr_use_trans_push placeholder which return false for
now until we have everything in place.

v2:
  - modify commit message
  - add TODO

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++
 drivers/gpu/drm/i915/display/intel_psr.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 91f4ac86c7ad..170d65999ccd 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -4557,3 +4557,9 @@ int intel_psr_min_guardband(struct intel_crtc_state *crtc_state)
 
 	return psr_min_guardband;
 }
+
+bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state)
+{
+	/* TODO: Enable using trans push when everything is in place */
+	return false;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index b41dc4d44ff2..394b641840b3 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -85,5 +85,6 @@ bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
 void intel_psr_compute_config_late(struct intel_dp *intel_dp,
 				   struct intel_crtc_state *crtc_state);
 int intel_psr_min_guardband(struct intel_crtc_state *crtc_state);
+bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_PSR_H__ */
-- 
2.43.0

[PATCH v9 3/8] drm/i915/vrr: Prepare to Use TRANS_PUSH mechanism for PSR frame change

[Jouni Högander]

On Lunarlake and onwards it is possible to generate PSR "frame change"
event using TRANS_PUSH mechanism. Implement function to enable this and
take PSR into account in intel_vrr_send_push.

v6:
  - add HAS_PSR_FRAME_CHANGE macro
  - use TRANS_PUSH in instead of TRAN_VRR_CTL
v5: use intel_psr_use_trans_push for intel_vrr_psr_frame_change_enable
v4:
  - use rmw when enabling/disabling transcoder
  - set TRANS_PUSH_EN conditionally in intel_vrr_send_push
  - do not call intel_vrr_send_push from intel_psr_trigger_frame_change
  - do not enable using TRANS_PUSH mechanism for PSR "Frame Change"
v3:
  - use rmw when enabling/disabling
  - keep LNL_TRANS_PUSH_PSR_PR_EN set always on LunarLake and onwards
v2: use intel_vrr_trans_push_enabled_set_clear instead of rmw

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc.c |  4 +++-
 drivers/gpu/drm/i915/display/intel_psr.c  | 13 +++++++---
 drivers/gpu/drm/i915/display/intel_vrr.c  | 29 ++++++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_vrr.h  |  1 +
 4 files changed, 37 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 778ebc5095c3..ed3c6c4ce025 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -747,7 +747,9 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
 	 * which would cause the next frame to terminate already at vmin
 	 * vblank start instead of vmax vblank start.
 	 */
-	if (!state->base.legacy_cursor_update)
+	if (!state->base.legacy_cursor_update ||
+	    (intel_psr_use_trans_push(new_crtc_state) &&
+	     !new_crtc_state->vrr.enable))
 		intel_vrr_send_push(NULL, new_crtc_state);
 
 	local_irq_enable();
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 170d65999ccd..4336ba188aa7 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -207,6 +207,8 @@
 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
 			   (intel_dp)->psr.source_support)
 
+#define HAS_PSR_FRAME_CHANGE(display)	(DISPLAY_VER(display) >= 20)
+
 bool intel_encoder_can_psr(struct intel_encoder *encoder)
 {
 	if (intel_encoder_is_dp(encoder) || encoder->type == INTEL_OUTPUT_DP_MST)
@@ -2120,6 +2122,9 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 		intel_dmc_block_pkgc(display, intel_dp->psr.pipe, true);
 
 	intel_alpm_configure(intel_dp, crtc_state);
+
+	if (intel_psr_use_trans_push(crtc_state))
+		intel_vrr_psr_frame_change_enable(crtc_state);
 }
 
 static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
@@ -2511,9 +2516,11 @@ void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
 		intel_pre_commit_crtc_state(state, crtc);
 	struct intel_display *display = to_intel_display(crtc);
 
-	if (crtc_state->has_psr)
-		intel_de_write_dsb(display, dsb,
-				   CURSURFLIVE(display, crtc->pipe), 0);
+	if (!crtc_state->has_psr || HAS_PSR_FRAME_CHANGE(display))
+		return;
+
+	intel_de_write_dsb(display, dsb,
+			   CURSURFLIVE(display, crtc->pipe), 0);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index b92c42fde937..aaf0f6cf3cfe 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -584,16 +584,23 @@ void intel_vrr_send_push(struct intel_dsb *dsb,
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 trans_push;
 
-	if (!crtc_state->vrr.enable)
+	if (!crtc_state->vrr.enable && !intel_psr_use_trans_push(crtc_state))
 		return;
 
 	if (dsb)
 		intel_dsb_nonpost_start(dsb);
 
-	intel_de_write_dsb(display, dsb,
-			   TRANS_PUSH(display, cpu_transcoder),
-			   TRANS_PUSH_EN | TRANS_PUSH_SEND);
+	trans_push = TRANS_PUSH_SEND;
+
+	if (crtc_state->vrr.enable)
+		trans_push |= TRANS_PUSH_EN;
+	if (intel_psr_use_trans_push(crtc_state))
+		trans_push |= LNL_TRANS_PUSH_PSR_PR_EN;
+
+	intel_de_write_dsb(display, dsb, TRANS_PUSH(display, cpu_transcoder),
+			   trans_push);
 
 	if (dsb)
 		intel_dsb_nonpost_end(dsb);
@@ -693,7 +700,7 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	u32 vrr_ctl;
 
-	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN);
+	intel_de_rmw(display, TRANS_PUSH(display, cpu_transcoder), 0, TRANS_PUSH_EN);
 
 	vrr_ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
 
@@ -721,7 +728,8 @@ static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
 				       VRR_STATUS_VRR_EN_LIVE, 1000))
 		drm_err(display->drm, "Timed out waiting for VRR live status to clear\n");
 
-	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);
+	intel_de_rmw(display, TRANS_PUSH(display, cpu_transcoder),
+		     TRANS_PUSH_EN, 0);
 }
 
 void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
@@ -737,6 +745,15 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 		intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);
 }
 
+void intel_vrr_psr_frame_change_enable(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	intel_de_rmw(display, TRANS_PUSH(display, cpu_transcoder), 0,
+		     LNL_TRANS_PUSH_PSR_PR_EN);
+}
+
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 {
 	struct intel_display *display = to_intel_display(old_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index bc9044621635..4dc5bb3f6f28 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -30,6 +30,7 @@ void intel_vrr_check_push_sent(struct intel_dsb *dsb,
 			       const struct intel_crtc_state *crtc_state);
 bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state);
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state);
+void intel_vrr_psr_frame_change_enable(const struct intel_crtc_state *crtc_state);
 void intel_vrr_get_config(struct intel_crtc_state *crtc_state);
 int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state);
 int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state);
-- 
2.43.0

[PATCH v9 4/8] drm/i915/dsb: Set DSB_SKIP_WAITS_EN chicken bit for LunarLake and onwards

[Jouni Högander]

On LunarLake we are using TRANS_PUSH mechanism to trigger "Frame Change"
event. This way we have more control on when PSR HW is woken up. I.e. not
every display register write is triggering sending update. This allows us
setting DSB_SKIP_WAITS_EN chicken bit as well.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index ec2a3fb171ab..19a99f82f413 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -17,6 +17,7 @@
 #include "intel_dsb.h"
 #include "intel_dsb_buffer.h"
 #include "intel_dsb_regs.h"
+#include "intel_psr.h"
 #include "intel_vblank.h"
 #include "intel_vrr.h"
 #include "skl_watermark.h"
@@ -166,18 +167,24 @@ static int dsb_scanline_to_hw(struct intel_atomic_state *state,
  * definitely do not want to skip vblank wait. We also have concern what comes
  * to skipping vblank evasion. I.e. arming registers are latched before we have
  * managed writing them. Due to these reasons we are not setting
- * DSB_SKIP_WAITS_EN.
+ * DSB_SKIP_WAITS_EN except when using TRANS_PUSH mechanism to trigger
+ * "frame change" event.
  */
 static u32 dsb_chicken(struct intel_atomic_state *state,
 		       struct intel_crtc *crtc)
 {
+	const struct intel_crtc_state *new_crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	u32 chicken = intel_psr_use_trans_push(new_crtc_state) ?
+		DSB_SKIP_WAITS_EN : 0;
+
 	if (pre_commit_is_vrr_active(state, crtc))
-		return DSB_CTRL_WAIT_SAFE_WINDOW |
+		chicken |= DSB_CTRL_WAIT_SAFE_WINDOW |
 			DSB_CTRL_NO_WAIT_VBLANK |
 			DSB_INST_WAIT_SAFE_WINDOW |
 			DSB_INST_NO_WAIT_VBLANK;
-	else
-		return 0;
+
+	return chicken;
 }
 
 static bool assert_dsb_has_room(struct intel_dsb *dsb)
-- 
2.43.0

[PATCH v9 5/8] drm/i915/display: Wait for vblank in case of PSR is using trans push

[Jouni Högander]

In case PSR uses trans push as a "frame change" event and we need to wait
vblank after triggering PSR "frame change" event. Otherwise we may miss
selective updates.

DSB skips all waits while PSR is active. Check push send is skipped as well
because trans push send bit is not clearn by the HW if VRR is not enabled
-> we may start configuring new selective update while previous is not
complete. Avoid this by waiting for vblank after sending trans push.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1e3c5761fc5e..c7ca4f53b8b8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7366,9 +7366,27 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 				new_crtc_state->dsb_color);
 
 	if (new_crtc_state->use_dsb && !intel_color_uses_chained_dsb(new_crtc_state)) {
-		intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
+		/*
+		 * Dsb wait vblank may or may not skip. Let's remove it for PSR
+		 * trans push case to ensure we are not waiting two vblanks
+		 */
+		if (!intel_psr_use_trans_push(new_crtc_state))
+			intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
 
 		intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
+
+		/*
+		 * In case PSR uses trans push as a "frame change" event and
+		 * VRR is not in use we need to wait vblank. Othervise we may
+		 * miss selective updates. DSB skips all waits while PSR is
+		 * active. Check push send is skipped as well because trans push
+		 * send bit is not clearn by the HW if VRR is not enabled -> we
+		 * may start configuring new selective update while previous is
+		 * not complete.
+		 */
+		if (intel_psr_use_trans_push(new_crtc_state))
+			intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
+
 		intel_dsb_wait_for_delayed_vblank(state, new_crtc_state->dsb_commit);
 		intel_vrr_check_push_sent(new_crtc_state->dsb_commit,
 					  new_crtc_state);
-- 
2.43.0

[PATCH v9 6/8] drm/i915/psr: Wait for idle only after possible send push

[Jouni Högander]

We are planning to move using trans push mechanism to trigger the Frame
Change event. in that case we can't wait PSR to idle before send push
happens. Due to this move wait for idle to be done after possible send push
is done.

This should be ok for Frame Change event triggered by register write as
well. Wait for idle is needed only for corner case where PSR is
transitioning into DEEP_SLEEP when Frame Change event is triggered. It just
has to be before wait for vblank. Otherwise we may have vblank before PSR
enters DEEP_SLEEP and still using old frame buffers for first frame after
wake up.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c7ca4f53b8b8..1aca4802b7d5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7333,9 +7333,6 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 		intel_psr_trigger_frame_change_event(new_crtc_state->dsb_commit,
 						     state, crtc);
 
-		intel_psr_wait_for_idle_dsb(new_crtc_state->dsb_commit,
-					    new_crtc_state);
-
 		if (new_crtc_state->use_dsb)
 			intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);
 
@@ -7375,6 +7372,16 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 
 		intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
 
+		/*
+		 * Wait for idle is needed for corner case where PSR HW
+		 * is transitioning into DEEP_SLEEP/SRDENT_OFF when
+		 * new Frame Change event comes in. It is ok to do it
+		 * here for both Frame Change mecanisms (trans push
+		 * and register write).
+		 */
+		intel_psr_wait_for_idle_dsb(new_crtc_state->dsb_commit,
+					    new_crtc_state);
+
 		/*
 		 * In case PSR uses trans push as a "frame change" event and
 		 * VRR is not in use we need to wait vblank. Othervise we may
-- 
2.43.0

[PATCH v9 7/8] drm/i915/psr: Do PSR exit on frontbuffer flush on LunarLake and onwards

[Jouni Högander]

We need to use intel_psr_exit in frontbuffer flush on LunarLake and
onwardsif we want to move using trans push mechanism to trigger Frame
Change event.

Keep PSR1 and PSR2 HW tracking as it is for older platforms as this was
seen causing problems there.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 4336ba188aa7..ee70d0ceeb5b 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -3559,7 +3559,14 @@ static void _psr_flush_handle(struct intel_dp *intel_dp)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 
-	if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) {
+	if (DISPLAY_VER(display) >= 20) {
+		/*
+		 * We can use PSR exit on LunarLake onwards. Also
+		 * using trans push mechanism to trigger Frame Change
+		 * event requires using PSR exit.
+		 */
+		intel_psr_exit(intel_dp);
+	} else if (intel_dp->psr.psr2_sel_fetch_enabled) {
 		/* Selective fetch prior LNL */
 		if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
 			/* can we turn CFF off? */
@@ -3579,16 +3586,11 @@ static void _psr_flush_handle(struct intel_dp *intel_dp)
 		intel_psr_configure_full_frame_update(intel_dp);
 
 		intel_psr_force_update(intel_dp);
-	} else if (!intel_dp->psr.psr2_sel_fetch_enabled) {
+	} else {
 		/*
-		 * PSR1 on all platforms
-		 * PSR2 HW tracking
-		 * Panel Replay Full frame update
+		 * On older platforms using PSR exit was seen causing problems
 		 */
 		intel_psr_force_update(intel_dp);
-	} else {
-		/* Selective update LNL onwards */
-		intel_psr_exit(intel_dp);
 	}
 
 	if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)
-- 
2.43.0

[PATCH v9 8/8] drm/i915/psr: Use TRANS_PUSH to trigger frame change event

[Jouni Högander]

Now we have everything in place for triggering PSR "frame change" event
using TRANS_PUSH: use TRANS_PUSH for LunarLake and onwards.

v3: use HAS_PSR_FRAME_CHANGE macro
v2: use AND instead of OR in intel_psr_use_trans_push

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index ee70d0ceeb5b..353924f8c975 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -4569,6 +4569,7 @@ int intel_psr_min_guardband(struct intel_crtc_state *crtc_state)
 
 bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state)
 {
-	/* TODO: Enable using trans push when everything is in place */
-	return false;
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	return HAS_PSR_FRAME_CHANGE(display) && crtc_state->has_psr;
 }
-- 
2.43.0

✓ CI.KUnit: success for Use trans push mechanism to generate frame change event (rev9)

[Patchwork]

== Series Details ==

Series: Use trans push mechanism to generate frame change event (rev9)
URL   : https://patchwork.freedesktop.org/series/139831/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[11:40:35] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:40:39] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:41:11] Starting KUnit Kernel (1/1)...
[11:41:11] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:41:11] ================== guc_buf (11 subtests) ===================
[11:41:11] [PASSED] test_smallest
[11:41:11] [PASSED] test_largest
[11:41:11] [PASSED] test_granular
[11:41:11] [PASSED] test_unique
[11:41:11] [PASSED] test_overlap
[11:41:11] [PASSED] test_reusable
[11:41:11] [PASSED] test_too_big
[11:41:11] [PASSED] test_flush
[11:41:11] [PASSED] test_lookup
[11:41:11] [PASSED] test_data
[11:41:11] [PASSED] test_class
[11:41:11] ===================== [PASSED] guc_buf =====================
[11:41:11] =================== guc_dbm (7 subtests) ===================
[11:41:11] [PASSED] test_empty
[11:41:11] [PASSED] test_default
[11:41:11] ======================== test_size  ========================
[11:41:11] [PASSED] 4
[11:41:11] [PASSED] 8
[11:41:11] [PASSED] 32
[11:41:11] [PASSED] 256
[11:41:11] ==================== [PASSED] test_size ====================
[11:41:11] ======================= test_reuse  ========================
[11:41:11] [PASSED] 4
[11:41:11] [PASSED] 8
[11:41:11] [PASSED] 32
[11:41:11] [PASSED] 256
[11:41:11] =================== [PASSED] test_reuse ====================
[11:41:11] =================== test_range_overlap  ====================
[11:41:11] [PASSED] 4
[11:41:11] [PASSED] 8
[11:41:11] [PASSED] 32
[11:41:11] [PASSED] 256
[11:41:11] =============== [PASSED] test_range_overlap ================
[11:41:11] =================== test_range_compact  ====================
[11:41:11] [PASSED] 4
[11:41:11] [PASSED] 8
[11:41:11] [PASSED] 32
[11:41:11] [PASSED] 256
[11:41:11] =============== [PASSED] test_range_compact ================
[11:41:11] ==================== test_range_spare  =====================
[11:41:11] [PASSED] 4
[11:41:11] [PASSED] 8
[11:41:11] [PASSED] 32
[11:41:11] [PASSED] 256
[11:41:11] ================ [PASSED] test_range_spare =================
[11:41:11] ===================== [PASSED] guc_dbm =====================
[11:41:11] =================== guc_idm (6 subtests) ===================
[11:41:11] [PASSED] bad_init
[11:41:11] [PASSED] no_init
[11:41:11] [PASSED] init_fini
[11:41:11] [PASSED] check_used
[11:41:11] [PASSED] check_quota
[11:41:11] [PASSED] check_all
[11:41:11] ===================== [PASSED] guc_idm =====================
[11:41:11] ================== no_relay (3 subtests) ===================
[11:41:11] [PASSED] xe_drops_guc2pf_if_not_ready
[11:41:11] [PASSED] xe_drops_guc2vf_if_not_ready
[11:41:11] [PASSED] xe_rejects_send_if_not_ready
[11:41:11] ==================== [PASSED] no_relay =====================
[11:41:11] ================== pf_relay (14 subtests) ==================
[11:41:11] [PASSED] pf_rejects_guc2pf_too_short
[11:41:11] [PASSED] pf_rejects_guc2pf_too_long
[11:41:11] [PASSED] pf_rejects_guc2pf_no_payload
[11:41:11] [PASSED] pf_fails_no_payload
[11:41:11] [PASSED] pf_fails_bad_origin
[11:41:11] [PASSED] pf_fails_bad_type
[11:41:11] [PASSED] pf_txn_reports_error
[11:41:11] [PASSED] pf_txn_sends_pf2guc
[11:41:11] [PASSED] pf_sends_pf2guc
[11:41:11] [SKIPPED] pf_loopback_nop
[11:41:11] [SKIPPED] pf_loopback_echo
[11:41:11] [SKIPPED] pf_loopback_fail
[11:41:11] [SKIPPED] pf_loopback_busy
[11:41:11] [SKIPPED] pf_loopback_retry
[11:41:11] ==================== [PASSED] pf_relay =====================
[11:41:11] ================== vf_relay (3 subtests) ===================
[11:41:11] [PASSED] vf_rejects_guc2vf_too_short
[11:41:11] [PASSED] vf_rejects_guc2vf_too_long
[11:41:11] [PASSED] vf_rejects_guc2vf_no_payload
[11:41:11] ==================== [PASSED] vf_relay =====================
[11:41:11] ================ pf_gt_config (6 subtests) =================
[11:41:11] [PASSED] fair_contexts_1vf
[11:41:11] [PASSED] fair_doorbells_1vf
[11:41:11] [PASSED] fair_ggtt_1vf
[11:41:11] ====================== fair_contexts  ======================
[11:41:11] [PASSED] 1 VF
[11:41:11] [PASSED] 2 VFs
[11:41:11] [PASSED] 3 VFs
[11:41:11] [PASSED] 4 VFs
[11:41:11] [PASSED] 5 VFs
[11:41:11] [PASSED] 6 VFs
[11:41:11] [PASSED] 7 VFs
[11:41:11] [PASSED] 8 VFs
[11:41:11] [PASSED] 9 VFs
[11:41:11] [PASSED] 10 VFs
[11:41:11] [PASSED] 11 VFs
[11:41:11] [PASSED] 12 VFs
[11:41:11] [PASSED] 13 VFs
[11:41:11] [PASSED] 14 VFs
[11:41:11] [PASSED] 15 VFs
[11:41:11] [PASSED] 16 VFs
[11:41:11] [PASSED] 17 VFs
[11:41:11] [PASSED] 18 VFs
[11:41:11] [PASSED] 19 VFs
[11:41:11] [PASSED] 20 VFs
[11:41:11] [PASSED] 21 VFs
[11:41:11] [PASSED] 22 VFs
[11:41:11] [PASSED] 23 VFs
[11:41:11] [PASSED] 24 VFs
[11:41:11] [PASSED] 25 VFs
[11:41:11] [PASSED] 26 VFs
[11:41:11] [PASSED] 27 VFs
[11:41:11] [PASSED] 28 VFs
[11:41:11] [PASSED] 29 VFs
[11:41:11] [PASSED] 30 VFs
[11:41:11] [PASSED] 31 VFs
[11:41:11] [PASSED] 32 VFs
[11:41:11] [PASSED] 33 VFs
[11:41:11] [PASSED] 34 VFs
[11:41:11] [PASSED] 35 VFs
[11:41:11] [PASSED] 36 VFs
[11:41:11] [PASSED] 37 VFs
[11:41:11] [PASSED] 38 VFs
[11:41:11] [PASSED] 39 VFs
[11:41:11] [PASSED] 40 VFs
[11:41:11] [PASSED] 41 VFs
[11:41:11] [PASSED] 42 VFs
[11:41:11] [PASSED] 43 VFs
[11:41:11] [PASSED] 44 VFs
[11:41:11] [PASSED] 45 VFs
[11:41:11] [PASSED] 46 VFs
[11:41:11] [PASSED] 47 VFs
[11:41:11] [PASSED] 48 VFs
[11:41:11] [PASSED] 49 VFs
[11:41:11] [PASSED] 50 VFs
[11:41:11] [PASSED] 51 VFs
[11:41:11] [PASSED] 52 VFs
[11:41:11] [PASSED] 53 VFs
[11:41:11] [PASSED] 54 VFs
[11:41:11] [PASSED] 55 VFs
[11:41:11] [PASSED] 56 VFs
[11:41:11] [PASSED] 57 VFs
[11:41:11] [PASSED] 58 VFs
[11:41:11] [PASSED] 59 VFs
[11:41:11] [PASSED] 60 VFs
[11:41:11] [PASSED] 61 VFs
[11:41:11] [PASSED] 62 VFs
[11:41:11] [PASSED] 63 VFs
[11:41:11] ================== [PASSED] fair_contexts ==================
[11:41:11] ===================== fair_doorbells  ======================
[11:41:11] [PASSED] 1 VF
[11:41:11] [PASSED] 2 VFs
[11:41:11] [PASSED] 3 VFs
[11:41:11] [PASSED] 4 VFs
[11:41:11] [PASSED] 5 VFs
[11:41:11] [PASSED] 6 VFs
[11:41:11] [PASSED] 7 VFs
[11:41:11] [PASSED] 8 VFs
[11:41:11] [PASSED] 9 VFs
[11:41:11] [PASSED] 10 VFs
[11:41:11] [PASSED] 11 VFs
[11:41:11] [PASSED] 12 VFs
[11:41:11] [PASSED] 13 VFs
[11:41:11] [PASSED] 14 VFs
[11:41:11] [PASSED] 15 VFs
[11:41:11] [PASSED] 16 VFs
[11:41:11] [PASSED] 17 VFs
[11:41:11] [PASSED] 18 VFs
[11:41:11] [PASSED] 19 VFs
[11:41:11] [PASSED] 20 VFs
[11:41:11] [PASSED] 21 VFs
[11:41:11] [PASSED] 22 VFs
[11:41:11] [PASSED] 23 VFs
[11:41:11] [PASSED] 24 VFs
[11:41:11] [PASSED] 25 VFs
[11:41:11] [PASSED] 26 VFs
[11:41:11] [PASSED] 27 VFs
[11:41:11] [PASSED] 28 VFs
[11:41:11] [PASSED] 29 VFs
[11:41:11] [PASSED] 30 VFs
[11:41:11] [PASSED] 31 VFs
[11:41:11] [PASSED] 32 VFs
[11:41:11] [PASSED] 33 VFs
[11:41:11] [PASSED] 34 VFs
[11:41:11] [PASSED] 35 VFs
[11:41:11] [PASSED] 36 VFs
[11:41:11] [PASSED] 37 VFs
[11:41:11] [PASSED] 38 VFs
[11:41:11] [PASSED] 39 VFs
[11:41:11] [PASSED] 40 VFs
[11:41:11] [PASSED] 41 VFs
[11:41:11] [PASSED] 42 VFs
[11:41:11] [PASSED] 43 VFs
[11:41:11] [PASSED] 44 VFs
[11:41:11] [PASSED] 45 VFs
[11:41:11] [PASSED] 46 VFs
[11:41:11] [PASSED] 47 VFs
[11:41:11] [PASSED] 48 VFs
[11:41:11] [PASSED] 49 VFs
[11:41:11] [PASSED] 50 VFs
[11:41:11] [PASSED] 51 VFs
[11:41:11] [PASSED] 52 VFs
[11:41:11] [PASSED] 53 VFs
[11:41:11] [PASSED] 54 VFs
[11:41:11] [PASSED] 55 VFs
[11:41:11] [PASSED] 56 VFs
[11:41:11] [PASSED] 57 VFs
[11:41:11] [PASSED] 58 VFs
[11:41:11] [PASSED] 59 VFs
[11:41:11] [PASSED] 60 VFs
[11:41:11] [PASSED] 61 VFs
[11:41:11] [PASSED] 62 VFs
[11:41:11] [PASSED] 63 VFs
[11:41:11] ================= [PASSED] fair_doorbells ==================
[11:41:11] ======================== fair_ggtt  ========================
[11:41:11] [PASSED] 1 VF
[11:41:11] [PASSED] 2 VFs
[11:41:11] [PASSED] 3 VFs
[11:41:11] [PASSED] 4 VFs
[11:41:11] [PASSED] 5 VFs
[11:41:11] [PASSED] 6 VFs
[11:41:11] [PASSED] 7 VFs
[11:41:11] [PASSED] 8 VFs
[11:41:11] [PASSED] 9 VFs
[11:41:11] [PASSED] 10 VFs
[11:41:11] [PASSED] 11 VFs
[11:41:11] [PASSED] 12 VFs
[11:41:11] [PASSED] 13 VFs
[11:41:11] [PASSED] 14 VFs
[11:41:11] [PASSED] 15 VFs
[11:41:11] [PASSED] 16 VFs
[11:41:11] [PASSED] 17 VFs
[11:41:11] [PASSED] 18 VFs
[11:41:11] [PASSED] 19 VFs
[11:41:11] [PASSED] 20 VFs
[11:41:11] [PASSED] 21 VFs
[11:41:11] [PASSED] 22 VFs
[11:41:11] [PASSED] 23 VFs
[11:41:11] [PASSED] 24 VFs
[11:41:11] [PASSED] 25 VFs
[11:41:11] [PASSED] 26 VFs
[11:41:11] [PASSED] 27 VFs
[11:41:11] [PASSED] 28 VFs
[11:41:11] [PASSED] 29 VFs
[11:41:11] [PASSED] 30 VFs
[11:41:11] [PASSED] 31 VFs
[11:41:11] [PASSED] 32 VFs
[11:41:11] [PASSED] 33 VFs
[11:41:11] [PASSED] 34 VFs
[11:41:11] [PASSED] 35 VFs
[11:41:11] [PASSED] 36 VFs
[11:41:11] [PASSED] 37 VFs
[11:41:11] [PASSED] 38 VFs
[11:41:11] [PASSED] 39 VFs
[11:41:11] [PASSED] 40 VFs
[11:41:11] [PASSED] 41 VFs
[11:41:11] [PASSED] 42 VFs
[11:41:11] [PASSED] 43 VFs
[11:41:11] [PASSED] 44 VFs
[11:41:11] [PASSED] 45 VFs
[11:41:11] [PASSED] 46 VFs
[11:41:11] [PASSED] 47 VFs
[11:41:11] [PASSED] 48 VFs
[11:41:11] [PASSED] 49 VFs
[11:41:11] [PASSED] 50 VFs
[11:41:11] [PASSED] 51 VFs
[11:41:11] [PASSED] 52 VFs
[11:41:11] [PASSED] 53 VFs
[11:41:11] [PASSED] 54 VFs
[11:41:11] [PASSED] 55 VFs
[11:41:11] [PASSED] 56 VFs
[11:41:11] [PASSED] 57 VFs
[11:41:11] [PASSED] 58 VFs
[11:41:11] [PASSED] 59 VFs
[11:41:11] [PASSED] 60 VFs
[11:41:11] [PASSED] 61 VFs
[11:41:11] [PASSED] 62 VFs
[11:41:11] [PASSED] 63 VFs
[11:41:11] ==================== [PASSED] fair_ggtt ====================
[11:41:11] ================== [PASSED] pf_gt_config ===================
[11:41:11] ===================== lmtt (1 subtest) =====================
[11:41:11] ======================== test_ops  =========================
[11:41:11] [PASSED] 2-level
[11:41:11] [PASSED] multi-level
[11:41:11] ==================== [PASSED] test_ops =====================
[11:41:11] ====================== [PASSED] lmtt =======================
[11:41:11] ================= pf_service (11 subtests) =================
[11:41:11] [PASSED] pf_negotiate_any
[11:41:11] [PASSED] pf_negotiate_base_match
[11:41:11] [PASSED] pf_negotiate_base_newer
[11:41:11] [PASSED] pf_negotiate_base_next
[11:41:11] [SKIPPED] pf_negotiate_base_older
[11:41:11] [PASSED] pf_negotiate_base_prev
[11:41:11] [PASSED] pf_negotiate_latest_match
[11:41:11] [PASSED] pf_negotiate_latest_newer
[11:41:11] [PASSED] pf_negotiate_latest_next
[11:41:11] [SKIPPED] pf_negotiate_latest_older
[11:41:11] [SKIPPED] pf_negotiate_latest_prev
[11:41:11] =================== [PASSED] pf_service ====================
[11:41:11] ================= xe_guc_g2g (2 subtests) ==================
[11:41:11] ============== xe_live_guc_g2g_kunit_default  ==============
[11:41:11] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[11:41:11] ============== xe_live_guc_g2g_kunit_allmem  ===============
[11:41:11] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[11:41:11] =================== [SKIPPED] xe_guc_g2g ===================
[11:41:11] =================== xe_mocs (2 subtests) ===================
[11:41:11] ================ xe_live_mocs_kernel_kunit  ================
[11:41:11] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[11:41:11] ================ xe_live_mocs_reset_kunit  =================
[11:41:11] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[11:41:11] ==================== [SKIPPED] xe_mocs =====================
[11:41:11] ================= xe_migrate (2 subtests) ==================
[11:41:11] ================= xe_migrate_sanity_kunit  =================
[11:41:11] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[11:41:11] ================== xe_validate_ccs_kunit  ==================
[11:41:11] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[11:41:11] =================== [SKIPPED] xe_migrate ===================
[11:41:11] ================== xe_dma_buf (1 subtest) ==================
[11:41:11] ==================== xe_dma_buf_kunit  =====================
[11:41:11] ================ [SKIPPED] xe_dma_buf_kunit ================
[11:41:11] =================== [SKIPPED] xe_dma_buf ===================
[11:41:11] ================= xe_bo_shrink (1 subtest) =================
[11:41:11] =================== xe_bo_shrink_kunit  ====================
[11:41:11] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[11:41:11] ================== [SKIPPED] xe_bo_shrink ==================
[11:41:11] ==================== xe_bo (2 subtests) ====================
[11:41:11] ================== xe_ccs_migrate_kunit  ===================
[11:41:11] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[11:41:11] ==================== xe_bo_evict_kunit  ====================
[11:41:11] =============== [SKIPPED] xe_bo_evict_kunit ================
[11:41:11] ===================== [SKIPPED] xe_bo ======================
[11:41:11] ==================== args (13 subtests) ====================
[11:41:11] [PASSED] count_args_test
[11:41:11] [PASSED] call_args_example
[11:41:11] [PASSED] call_args_test
[11:41:11] [PASSED] drop_first_arg_example
[11:41:11] [PASSED] drop_first_arg_test
[11:41:11] [PASSED] first_arg_example
[11:41:11] [PASSED] first_arg_test
[11:41:11] [PASSED] last_arg_example
[11:41:11] [PASSED] last_arg_test
[11:41:11] [PASSED] pick_arg_example
[11:41:11] [PASSED] if_args_example
[11:41:11] [PASSED] if_args_test
[11:41:11] [PASSED] sep_comma_example
[11:41:11] ====================== [PASSED] args =======================
[11:41:11] =================== xe_pci (3 subtests) ====================
[11:41:11] ==================== check_graphics_ip  ====================
[11:41:11] [PASSED] 12.00 Xe_LP
[11:41:11] [PASSED] 12.10 Xe_LP+
[11:41:11] [PASSED] 12.55 Xe_HPG
[11:41:11] [PASSED] 12.60 Xe_HPC
[11:41:11] [PASSED] 12.70 Xe_LPG
[11:41:11] [PASSED] 12.71 Xe_LPG
[11:41:11] [PASSED] 12.74 Xe_LPG+
[11:41:11] [PASSED] 20.01 Xe2_HPG
[11:41:11] [PASSED] 20.02 Xe2_HPG
[11:41:11] [PASSED] 20.04 Xe2_LPG
[11:41:11] [PASSED] 30.00 Xe3_LPG
[11:41:11] [PASSED] 30.01 Xe3_LPG
[11:41:11] [PASSED] 30.03 Xe3_LPG
[11:41:11] [PASSED] 30.04 Xe3_LPG
[11:41:11] [PASSED] 30.05 Xe3_LPG
[11:41:11] [PASSED] 35.11 Xe3p_XPC
[11:41:11] ================ [PASSED] check_graphics_ip ================
[11:41:11] ===================== check_media_ip  ======================
[11:41:11] [PASSED] 12.00 Xe_M
[11:41:11] [PASSED] 12.55 Xe_HPM
[11:41:11] [PASSED] 13.00 Xe_LPM+
[11:41:11] [PASSED] 13.01 Xe2_HPM
[11:41:11] [PASSED] 20.00 Xe2_LPM
[11:41:11] [PASSED] 30.00 Xe3_LPM
[11:41:11] [PASSED] 30.02 Xe3_LPM
[11:41:11] [PASSED] 35.00 Xe3p_LPM
[11:41:11] [PASSED] 35.03 Xe3p_HPM
[11:41:11] ================= [PASSED] check_media_ip ==================
[11:41:11] =================== check_platform_desc  ===================
[11:41:11] [PASSED] 0x9A60 (TIGERLAKE)
[11:41:11] [PASSED] 0x9A68 (TIGERLAKE)
[11:41:11] [PASSED] 0x9A70 (TIGERLAKE)
[11:41:11] [PASSED] 0x9A40 (TIGERLAKE)
[11:41:11] [PASSED] 0x9A49 (TIGERLAKE)
[11:41:11] [PASSED] 0x9A59 (TIGERLAKE)
[11:41:11] [PASSED] 0x9A78 (TIGERLAKE)
[11:41:11] [PASSED] 0x9AC0 (TIGERLAKE)
[11:41:11] [PASSED] 0x9AC9 (TIGERLAKE)
[11:41:11] [PASSED] 0x9AD9 (TIGERLAKE)
[11:41:11] [PASSED] 0x9AF8 (TIGERLAKE)
[11:41:11] [PASSED] 0x4C80 (ROCKETLAKE)
[11:41:11] [PASSED] 0x4C8A (ROCKETLAKE)
[11:41:11] [PASSED] 0x4C8B (ROCKETLAKE)
[11:41:11] [PASSED] 0x4C8C (ROCKETLAKE)
[11:41:11] [PASSED] 0x4C90 (ROCKETLAKE)
[11:41:11] [PASSED] 0x4C9A (ROCKETLAKE)
[11:41:11] [PASSED] 0x4680 (ALDERLAKE_S)
[11:41:11] [PASSED] 0x4682 (ALDERLAKE_S)
[11:41:11] [PASSED] 0x4688 (ALDERLAKE_S)
[11:41:11] [PASSED] 0x468A (ALDERLAKE_S)
[11:41:11] [PASSED] 0x468B (ALDERLAKE_S)
[11:41:11] [PASSED] 0x4690 (ALDERLAKE_S)
[11:41:11] [PASSED] 0x4692 (ALDERLAKE_S)
[11:41:11] [PASSED] 0x4693 (ALDERLAKE_S)
[11:41:11] [PASSED] 0x46A0 (ALDERLAKE_P)
[11:41:11] [PASSED] 0x46A1 (ALDERLAKE_P)
[11:41:11] [PASSED] 0x46A2 (ALDERLAKE_P)
[11:41:11] [PASSED] 0x46A3 (ALDERLAKE_P)
[11:41:11] [PASSED] 0x46A6 (ALDERLAKE_P)
[11:41:11] [PASSED] 0x46A8 (ALDERLAKE_P)
[11:41:11] [PASSED] 0x46AA (ALDERLAKE_P)
[11:41:11] [PASSED] 0x462A (ALDERLAKE_P)
[11:41:11] [PASSED] 0x4626 (ALDERLAKE_P)
[11:41:11] [PASSED] 0x4628 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[11:41:11] [PASSED] 0x46B0 (ALDERLAKE_P)
[11:41:11] [PASSED] 0x46B1 (ALDERLAKE_P)
[11:41:11] [PASSED] 0x46B2 (ALDERLAKE_P)
[11:41:11] [PASSED] 0x46B3 (ALDERLAKE_P)
[11:41:11] [PASSED] 0x46C0 (ALDERLAKE_P)
[11:41:11] [PASSED] 0x46C1 (ALDERLAKE_P)
[11:41:11] [PASSED] 0x46C2 (ALDERLAKE_P)
[11:41:11] [PASSED] 0x46C3 (ALDERLAKE_P)
[11:41:11] [PASSED] 0x46D0 (ALDERLAKE_N)
[11:41:11] [PASSED] 0x46D1 (ALDERLAKE_N)
[11:41:11] [PASSED] 0x46D2 (ALDERLAKE_N)
[11:41:11] [PASSED] 0x46D3 (ALDERLAKE_N)
[11:41:11] [PASSED] 0x46D4 (ALDERLAKE_N)
[11:41:11] [PASSED] 0xA721 (ALDERLAKE_P)
[11:41:11] [PASSED] 0xA7A1 (ALDERLAKE_P)
[11:41:11] [PASSED] 0xA7A9 (ALDERLAKE_P)
[11:41:11] [PASSED] 0xA7AC (ALDERLAKE_P)
[11:41:11] [PASSED] 0xA7AD (ALDERLAKE_P)
[11:41:11] [PASSED] 0xA720 (ALDERLAKE_P)
[11:41:11] [PASSED] 0xA7A0 (ALDERLAKE_P)
[11:41:11] [PASSED] 0xA7A8 (ALDERLAKE_P)
[11:41:11] [PASSED] 0xA7AA (ALDERLAKE_P)
[11:41:11] [PASSED] 0xA7AB (ALDERLAKE_P)
[11:41:11] [PASSED] 0xA780 (ALDERLAKE_S)
[11:41:11] [PASSED] 0xA781 (ALDERLAKE_S)
[11:41:11] [PASSED] 0xA782 (ALDERLAKE_S)
[11:41:11] [PASSED] 0xA783 (ALDERLAKE_S)
[11:41:11] [PASSED] 0xA788 (ALDERLAKE_S)
[11:41:11] [PASSED] 0xA789 (ALDERLAKE_S)
[11:41:11] [PASSED] 0xA78A (ALDERLAKE_S)
[11:41:11] [PASSED] 0xA78B (ALDERLAKE_S)
[11:41:11] [PASSED] 0x4905 (DG1)
[11:41:11] [PASSED] 0x4906 (DG1)
[11:41:11] [PASSED] 0x4907 (DG1)
[11:41:11] [PASSED] 0x4908 (DG1)
[11:41:11] [PASSED] 0x4909 (DG1)
[11:41:11] [PASSED] 0x56C0 (DG2)
[11:41:11] [PASSED] 0x56C2 (DG2)
[11:41:11] [PASSED] 0x56C1 (DG2)
[11:41:11] [PASSED] 0x7D51 (METEORLAKE)
[11:41:11] [PASSED] 0x7DD1 (METEORLAKE)
[11:41:11] [PASSED] 0x7D41 (METEORLAKE)
[11:41:11] [PASSED] 0x7D67 (METEORLAKE)
[11:41:11] [PASSED] 0xB640 (METEORLAKE)
[11:41:11] [PASSED] 0x56A0 (DG2)
[11:41:11] [PASSED] 0x56A1 (DG2)
[11:41:11] [PASSED] 0x56A2 (DG2)
[11:41:11] [PASSED] 0x56BE (DG2)
[11:41:11] [PASSED] 0x56BF (DG2)
[11:41:11] [PASSED] 0x5690 (DG2)
[11:41:11] [PASSED] 0x5691 (DG2)
[11:41:11] [PASSED] 0x5692 (DG2)
[11:41:11] [PASSED] 0x56A5 (DG2)
[11:41:11] [PASSED] 0x56A6 (DG2)
[11:41:11] [PASSED] 0x56B0 (DG2)
[11:41:11] [PASSED] 0x56B1 (DG2)
[11:41:11] [PASSED] 0x56BA (DG2)
[11:41:11] [PASSED] 0x56BB (DG2)
[11:41:11] [PASSED] 0x56BC (DG2)
[11:41:11] [PASSED] 0x56BD (DG2)
[11:41:11] [PASSED] 0x5693 (DG2)
[11:41:11] [PASSED] 0x5694 (DG2)
[11:41:11] [PASSED] 0x5695 (DG2)
[11:41:11] [PASSED] 0x56A3 (DG2)
[11:41:11] [PASSED] 0x56A4 (DG2)
[11:41:11] [PASSED] 0x56B2 (DG2)
[11:41:11] [PASSED] 0x56B3 (DG2)
[11:41:11] [PASSED] 0x5696 (DG2)
[11:41:11] [PASSED] 0x5697 (DG2)
[11:41:11] [PASSED] 0xB69 (PVC)
[11:41:11] [PASSED] 0xB6E (PVC)
[11:41:11] [PASSED] 0xBD4 (PVC)
[11:41:11] [PASSED] 0xBD5 (PVC)
[11:41:11] [PASSED] 0xBD6 (PVC)
[11:41:11] [PASSED] 0xBD7 (PVC)
[11:41:11] [PASSED] 0xBD8 (PVC)
[11:41:11] [PASSED] 0xBD9 (PVC)
[11:41:11] [PASSED] 0xBDA (PVC)
[11:41:11] [PASSED] 0xBDB (PVC)
[11:41:11] [PASSED] 0xBE0 (PVC)
[11:41:11] [PASSED] 0xBE1 (PVC)
[11:41:11] [PASSED] 0xBE5 (PVC)
[11:41:11] [PASSED] 0x7D40 (METEORLAKE)
[11:41:11] [PASSED] 0x7D45 (METEORLAKE)
[11:41:11] [PASSED] 0x7D55 (METEORLAKE)
[11:41:11] [PASSED] 0x7D60 (METEORLAKE)
[11:41:11] [PASSED] 0x7DD5 (METEORLAKE)
[11:41:11] [PASSED] 0x6420 (LUNARLAKE)
[11:41:11] [PASSED] 0x64A0 (LUNARLAKE)
[11:41:11] [PASSED] 0x64B0 (LUNARLAKE)
[11:41:11] [PASSED] 0xE202 (BATTLEMAGE)
[11:41:11] [PASSED] 0xE209 (BATTLEMAGE)
[11:41:11] [PASSED] 0xE20B (BATTLEMAGE)
[11:41:11] [PASSED] 0xE20C (BATTLEMAGE)
[11:41:11] [PASSED] 0xE20D (BATTLEMAGE)
[11:41:11] [PASSED] 0xE210 (BATTLEMAGE)
[11:41:11] [PASSED] 0xE211 (BATTLEMAGE)
[11:41:11] [PASSED] 0xE212 (BATTLEMAGE)
[11:41:11] [PASSED] 0xE216 (BATTLEMAGE)
[11:41:11] [PASSED] 0xE220 (BATTLEMAGE)
[11:41:11] [PASSED] 0xE221 (BATTLEMAGE)
[11:41:11] [PASSED] 0xE222 (BATTLEMAGE)
[11:41:11] [PASSED] 0xE223 (BATTLEMAGE)
[11:41:11] [PASSED] 0xB080 (PANTHERLAKE)
[11:41:11] [PASSED] 0xB081 (PANTHERLAKE)
[11:41:11] [PASSED] 0xB082 (PANTHERLAKE)
[11:41:11] [PASSED] 0xB083 (PANTHERLAKE)
[11:41:11] [PASSED] 0xB084 (PANTHERLAKE)
[11:41:11] [PASSED] 0xB085 (PANTHERLAKE)
[11:41:11] [PASSED] 0xB086 (PANTHERLAKE)
[11:41:11] [PASSED] 0xB087 (PANTHERLAKE)
[11:41:11] [PASSED] 0xB08F (PANTHERLAKE)
[11:41:11] [PASSED] 0xB090 (PANTHERLAKE)
[11:41:11] [PASSED] 0xB0A0 (PANTHERLAKE)
[11:41:11] [PASSED] 0xB0B0 (PANTHERLAKE)
[11:41:11] [PASSED] 0xFD80 (PANTHERLAKE)
[11:41:11] [PASSED] 0xFD81 (PANTHERLAKE)
[11:41:11] [PASSED] 0xD740 (NOVALAKE_S)
[11:41:11] [PASSED] 0xD741 (NOVALAKE_S)
[11:41:11] [PASSED] 0xD742 (NOVALAKE_S)
[11:41:11] [PASSED] 0xD743 (NOVALAKE_S)
[11:41:11] [PASSED] 0xD744 (NOVALAKE_S)
[11:41:11] [PASSED] 0xD745 (NOVALAKE_S)
[11:41:11] [PASSED] 0x674C (CRESCENTISLAND)
[11:41:11] =============== [PASSED] check_platform_desc ===============
[11:41:11] ===================== [PASSED] xe_pci ======================
[11:41:11] =================== xe_rtp (2 subtests) ====================
[11:41:11] =============== xe_rtp_process_to_sr_tests  ================
[11:41:11] [PASSED] coalesce-same-reg
[11:41:11] [PASSED] no-match-no-add
[11:41:11] [PASSED] match-or
[11:41:11] [PASSED] match-or-xfail
[11:41:11] [PASSED] no-match-no-add-multiple-rules
[11:41:11] [PASSED] two-regs-two-entries
[11:41:11] [PASSED] clr-one-set-other
[11:41:11] [PASSED] set-field
[11:41:11] [PASSED] conflict-duplicate
[11:41:11] [PASSED] conflict-not-disjoint
[11:41:11] [PASSED] conflict-reg-type
[11:41:11] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[11:41:11] ================== xe_rtp_process_tests  ===================
[11:41:11] [PASSED] active1
[11:41:11] [PASSED] active2
[11:41:11] [PASSED] active-inactive
[11:41:11] [PASSED] inactive-active
[11:41:11] [PASSED] inactive-1st_or_active-inactive
[11:41:11] [PASSED] inactive-2nd_or_active-inactive
[11:41:11] [PASSED] inactive-last_or_active-inactive
[11:41:11] [PASSED] inactive-no_or_active-inactive
[11:41:11] ============== [PASSED] xe_rtp_process_tests ===============
[11:41:11] ===================== [PASSED] xe_rtp ======================
[11:41:11] ==================== xe_wa (1 subtest) =====================
[11:41:11] ======================== xe_wa_gt  =========================
[11:41:11] [PASSED] TIGERLAKE B0
[11:41:11] [PASSED] DG1 A0
[11:41:11] [PASSED] DG1 B0
[11:41:11] [PASSED] ALDERLAKE_S A0
[11:41:11] [PASSED] ALDERLAKE_S B0
[11:41:11] [PASSED] ALDERLAKE_S C0
[11:41:11] [PASSED] ALDERLAKE_S D0
[11:41:11] [PASSED] ALDERLAKE_P A0
[11:41:11] [PASSED] ALDERLAKE_P B0
[11:41:11] [PASSED] ALDERLAKE_P C0
[11:41:11] [PASSED] ALDERLAKE_S RPLS D0
[11:41:11] [PASSED] ALDERLAKE_P RPLU E0
[11:41:11] [PASSED] DG2 G10 C0
[11:41:11] [PASSED] DG2 G11 B1
[11:41:11] [PASSED] DG2 G12 A1
[11:41:11] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:41:11] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:41:11] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[11:41:11] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[11:41:11] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[11:41:11] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[11:41:11] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[11:41:11] ==================== [PASSED] xe_wa_gt =====================
[11:41:11] ====================== [PASSED] xe_wa ======================
[11:41:11] ============================================================
[11:41:11] Testing complete. Ran 512 tests: passed: 494, skipped: 18
[11:41:11] Elapsed time: 36.036s total, 4.171s configuring, 31.348s building, 0.462s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[11:41:11] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:41:13] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:41:38] Starting KUnit Kernel (1/1)...
[11:41:38] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:41:38] ============ drm_test_pick_cmdline (2 subtests) ============
[11:41:38] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[11:41:38] =============== drm_test_pick_cmdline_named  ===============
[11:41:38] [PASSED] NTSC
[11:41:38] [PASSED] NTSC-J
[11:41:38] [PASSED] PAL
[11:41:38] [PASSED] PAL-M
[11:41:38] =========== [PASSED] drm_test_pick_cmdline_named ===========
[11:41:38] ============== [PASSED] drm_test_pick_cmdline ==============
[11:41:38] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[11:41:38] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[11:41:38] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[11:41:38] =========== drm_validate_clone_mode (2 subtests) ===========
[11:41:38] ============== drm_test_check_in_clone_mode  ===============
[11:41:38] [PASSED] in_clone_mode
[11:41:38] [PASSED] not_in_clone_mode
[11:41:38] ========== [PASSED] drm_test_check_in_clone_mode ===========
[11:41:38] =============== drm_test_check_valid_clones  ===============
[11:41:38] [PASSED] not_in_clone_mode
[11:41:38] [PASSED] valid_clone
[11:41:38] [PASSED] invalid_clone
[11:41:38] =========== [PASSED] drm_test_check_valid_clones ===========
[11:41:38] ============= [PASSED] drm_validate_clone_mode =============
[11:41:38] ============= drm_validate_modeset (1 subtest) =============
[11:41:38] [PASSED] drm_test_check_connector_changed_modeset
[11:41:38] ============== [PASSED] drm_validate_modeset ===============
[11:41:38] ====== drm_test_bridge_get_current_state (2 subtests) ======
[11:41:38] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[11:41:38] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[11:41:38] ======== [PASSED] drm_test_bridge_get_current_state ========
[11:41:38] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[11:41:38] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[11:41:38] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[11:41:38] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[11:41:38] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[11:41:38] ============== drm_bridge_alloc (2 subtests) ===============
[11:41:38] [PASSED] drm_test_drm_bridge_alloc_basic
[11:41:38] [PASSED] drm_test_drm_bridge_alloc_get_put
[11:41:38] ================ [PASSED] drm_bridge_alloc =================
[11:41:38] ================== drm_buddy (8 subtests) ==================
[11:41:38] [PASSED] drm_test_buddy_alloc_limit
[11:41:38] [PASSED] drm_test_buddy_alloc_optimistic
[11:41:38] [PASSED] drm_test_buddy_alloc_pessimistic
[11:41:38] [PASSED] drm_test_buddy_alloc_pathological
[11:41:38] [PASSED] drm_test_buddy_alloc_contiguous
[11:41:38] [PASSED] drm_test_buddy_alloc_clear
[11:41:39] [PASSED] drm_test_buddy_alloc_range_bias
[11:41:39] [PASSED] drm_test_buddy_fragmentation_performance
[11:41:39] ==================== [PASSED] drm_buddy ====================
[11:41:39] ============= drm_cmdline_parser (40 subtests) =============
[11:41:39] [PASSED] drm_test_cmdline_force_d_only
[11:41:39] [PASSED] drm_test_cmdline_force_D_only_dvi
[11:41:39] [PASSED] drm_test_cmdline_force_D_only_hdmi
[11:41:39] [PASSED] drm_test_cmdline_force_D_only_not_digital
[11:41:39] [PASSED] drm_test_cmdline_force_e_only
[11:41:39] [PASSED] drm_test_cmdline_res
[11:41:39] [PASSED] drm_test_cmdline_res_vesa
[11:41:39] [PASSED] drm_test_cmdline_res_vesa_rblank
[11:41:39] [PASSED] drm_test_cmdline_res_rblank
[11:41:39] [PASSED] drm_test_cmdline_res_bpp
[11:41:39] [PASSED] drm_test_cmdline_res_refresh
[11:41:39] [PASSED] drm_test_cmdline_res_bpp_refresh
[11:41:39] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[11:41:39] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[11:41:39] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[11:41:39] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[11:41:39] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[11:41:39] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[11:41:39] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[11:41:39] [PASSED] drm_test_cmdline_res_margins_force_on
[11:41:39] [PASSED] drm_test_cmdline_res_vesa_margins
[11:41:39] [PASSED] drm_test_cmdline_name
[11:41:39] [PASSED] drm_test_cmdline_name_bpp
[11:41:39] [PASSED] drm_test_cmdline_name_option
[11:41:39] [PASSED] drm_test_cmdline_name_bpp_option
[11:41:39] [PASSED] drm_test_cmdline_rotate_0
[11:41:39] [PASSED] drm_test_cmdline_rotate_90
[11:41:39] [PASSED] drm_test_cmdline_rotate_180
[11:41:39] [PASSED] drm_test_cmdline_rotate_270
[11:41:39] [PASSED] drm_test_cmdline_hmirror
[11:41:39] [PASSED] drm_test_cmdline_vmirror
[11:41:39] [PASSED] drm_test_cmdline_margin_options
[11:41:39] [PASSED] drm_test_cmdline_multiple_options
[11:41:39] [PASSED] drm_test_cmdline_bpp_extra_and_option
[11:41:39] [PASSED] drm_test_cmdline_extra_and_option
[11:41:39] [PASSED] drm_test_cmdline_freestanding_options
[11:41:39] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[11:41:39] [PASSED] drm_test_cmdline_panel_orientation
[11:41:39] ================ drm_test_cmdline_invalid  =================
[11:41:39] [PASSED] margin_only
[11:41:39] [PASSED] interlace_only
[11:41:39] [PASSED] res_missing_x
[11:41:39] [PASSED] res_missing_y
[11:41:39] [PASSED] res_bad_y
[11:41:39] [PASSED] res_missing_y_bpp
[11:41:39] [PASSED] res_bad_bpp
[11:41:39] [PASSED] res_bad_refresh
[11:41:39] [PASSED] res_bpp_refresh_force_on_off
[11:41:39] [PASSED] res_invalid_mode
[11:41:39] [PASSED] res_bpp_wrong_place_mode
[11:41:39] [PASSED] name_bpp_refresh
[11:41:39] [PASSED] name_refresh
[11:41:39] [PASSED] name_refresh_wrong_mode
[11:41:39] [PASSED] name_refresh_invalid_mode
[11:41:39] [PASSED] rotate_multiple
[11:41:39] [PASSED] rotate_invalid_val
[11:41:39] [PASSED] rotate_truncated
[11:41:39] [PASSED] invalid_option
[11:41:39] [PASSED] invalid_tv_option
[11:41:39] [PASSED] truncated_tv_option
[11:41:39] ============ [PASSED] drm_test_cmdline_invalid =============
[11:41:39] =============== drm_test_cmdline_tv_options  ===============
[11:41:39] [PASSED] NTSC
[11:41:39] [PASSED] NTSC_443
[11:41:39] [PASSED] NTSC_J
[11:41:39] [PASSED] PAL
[11:41:39] [PASSED] PAL_M
[11:41:39] [PASSED] PAL_N
[11:41:39] [PASSED] SECAM
[11:41:39] [PASSED] MONO_525
[11:41:39] [PASSED] MONO_625
[11:41:39] =========== [PASSED] drm_test_cmdline_tv_options ===========
[11:41:39] =============== [PASSED] drm_cmdline_parser ================
[11:41:39] ========== drmm_connector_hdmi_init (20 subtests) ==========
[11:41:39] [PASSED] drm_test_connector_hdmi_init_valid
[11:41:39] [PASSED] drm_test_connector_hdmi_init_bpc_8
[11:41:39] [PASSED] drm_test_connector_hdmi_init_bpc_10
[11:41:39] [PASSED] drm_test_connector_hdmi_init_bpc_12
[11:41:39] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[11:41:39] [PASSED] drm_test_connector_hdmi_init_bpc_null
[11:41:39] [PASSED] drm_test_connector_hdmi_init_formats_empty
[11:41:39] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[11:41:39] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[11:41:39] [PASSED] supported_formats=0x9 yuv420_allowed=1
[11:41:39] [PASSED] supported_formats=0x9 yuv420_allowed=0
[11:41:39] [PASSED] supported_formats=0x3 yuv420_allowed=1
[11:41:39] [PASSED] supported_formats=0x3 yuv420_allowed=0
[11:41:39] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[11:41:39] [PASSED] drm_test_connector_hdmi_init_null_ddc
[11:41:39] [PASSED] drm_test_connector_hdmi_init_null_product
[11:41:39] [PASSED] drm_test_connector_hdmi_init_null_vendor
[11:41:39] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[11:41:39] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[11:41:39] [PASSED] drm_test_connector_hdmi_init_product_valid
[11:41:39] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[11:41:39] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[11:41:39] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[11:41:39] ========= drm_test_connector_hdmi_init_type_valid  =========
[11:41:39] [PASSED] HDMI-A
[11:41:39] [PASSED] HDMI-B
[11:41:39] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[11:41:39] ======== drm_test_connector_hdmi_init_type_invalid  ========
[11:41:39] [PASSED] Unknown
[11:41:39] [PASSED] VGA
[11:41:39] [PASSED] DVI-I
[11:41:39] [PASSED] DVI-D
[11:41:39] [PASSED] DVI-A
[11:41:39] [PASSED] Composite
[11:41:39] [PASSED] SVIDEO
[11:41:39] [PASSED] LVDS
[11:41:39] [PASSED] Component
[11:41:39] [PASSED] DIN
[11:41:39] [PASSED] DP
[11:41:39] [PASSED] TV
[11:41:39] [PASSED] eDP
[11:41:39] [PASSED] Virtual
[11:41:39] [PASSED] DSI
[11:41:39] [PASSED] DPI
[11:41:39] [PASSED] Writeback
[11:41:39] [PASSED] SPI
[11:41:39] [PASSED] USB
[11:41:39] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[11:41:39] ============ [PASSED] drmm_connector_hdmi_init =============
[11:41:39] ============= drmm_connector_init (3 subtests) =============
[11:41:39] [PASSED] drm_test_drmm_connector_init
[11:41:39] [PASSED] drm_test_drmm_connector_init_null_ddc
[11:41:39] ========= drm_test_drmm_connector_init_type_valid  =========
[11:41:39] [PASSED] Unknown
[11:41:39] [PASSED] VGA
[11:41:39] [PASSED] DVI-I
[11:41:39] [PASSED] DVI-D
[11:41:39] [PASSED] DVI-A
[11:41:39] [PASSED] Composite
[11:41:39] [PASSED] SVIDEO
[11:41:39] [PASSED] LVDS
[11:41:39] [PASSED] Component
[11:41:39] [PASSED] DIN
[11:41:39] [PASSED] DP
[11:41:39] [PASSED] HDMI-A
[11:41:39] [PASSED] HDMI-B
[11:41:39] [PASSED] TV
[11:41:39] [PASSED] eDP
[11:41:39] [PASSED] Virtual
[11:41:39] [PASSED] DSI
[11:41:39] [PASSED] DPI
[11:41:39] [PASSED] Writeback
[11:41:39] [PASSED] SPI
[11:41:39] [PASSED] USB
[11:41:39] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[11:41:39] =============== [PASSED] drmm_connector_init ===============
[11:41:39] ========= drm_connector_dynamic_init (6 subtests) ==========
[11:41:39] [PASSED] drm_test_drm_connector_dynamic_init
[11:41:39] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[11:41:39] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[11:41:39] [PASSED] drm_test_drm_connector_dynamic_init_properties
[11:41:39] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[11:41:39] [PASSED] Unknown
[11:41:39] [PASSED] VGA
[11:41:39] [PASSED] DVI-I
[11:41:39] [PASSED] DVI-D
[11:41:39] [PASSED] DVI-A
[11:41:39] [PASSED] Composite
[11:41:39] [PASSED] SVIDEO
[11:41:39] [PASSED] LVDS
[11:41:39] [PASSED] Component
[11:41:39] [PASSED] DIN
[11:41:39] [PASSED] DP
[11:41:39] [PASSED] HDMI-A
[11:41:39] [PASSED] HDMI-B
[11:41:39] [PASSED] TV
[11:41:39] [PASSED] eDP
[11:41:39] [PASSED] Virtual
[11:41:39] [PASSED] DSI
[11:41:39] [PASSED] DPI
[11:41:39] [PASSED] Writeback
[11:41:39] [PASSED] SPI
[11:41:39] [PASSED] USB
[11:41:39] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[11:41:39] ======== drm_test_drm_connector_dynamic_init_name  =========
[11:41:39] [PASSED] Unknown
[11:41:39] [PASSED] VGA
[11:41:39] [PASSED] DVI-I
[11:41:39] [PASSED] DVI-D
[11:41:39] [PASSED] DVI-A
[11:41:39] [PASSED] Composite
[11:41:39] [PASSED] SVIDEO
[11:41:39] [PASSED] LVDS
[11:41:39] [PASSED] Component
[11:41:39] [PASSED] DIN
[11:41:39] [PASSED] DP
[11:41:39] [PASSED] HDMI-A
[11:41:39] [PASSED] HDMI-B
[11:41:39] [PASSED] TV
[11:41:39] [PASSED] eDP
[11:41:39] [PASSED] Virtual
[11:41:39] [PASSED] DSI
[11:41:39] [PASSED] DPI
[11:41:39] [PASSED] Writeback
[11:41:39] [PASSED] SPI
[11:41:39] [PASSED] USB
[11:41:39] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[11:41:39] =========== [PASSED] drm_connector_dynamic_init ============
[11:41:39] ==== drm_connector_dynamic_register_early (4 subtests) =====
[11:41:39] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[11:41:39] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[11:41:39] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[11:41:39] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[11:41:39] ====== [PASSED] drm_connector_dynamic_register_early =======
[11:41:39] ======= drm_connector_dynamic_register (7 subtests) ========
[11:41:39] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[11:41:39] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[11:41:39] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[11:41:39] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[11:41:39] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[11:41:39] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[11:41:39] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[11:41:39] ========= [PASSED] drm_connector_dynamic_register ==========
[11:41:39] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[11:41:39] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[11:41:39] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[11:41:39] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[11:41:39] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[11:41:39] ========== drm_test_get_tv_mode_from_name_valid  ===========
[11:41:39] [PASSED] NTSC
[11:41:39] [PASSED] NTSC-443
[11:41:39] [PASSED] NTSC-J
[11:41:39] [PASSED] PAL
[11:41:39] [PASSED] PAL-M
[11:41:39] [PASSED] PAL-N
[11:41:39] [PASSED] SECAM
[11:41:39] [PASSED] Mono
[11:41:39] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[11:41:39] [PASSED] drm_test_get_tv_mode_from_name_truncated
[11:41:39] ============ [PASSED] drm_get_tv_mode_from_name ============
[11:41:39] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[11:41:39] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[11:41:39] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[11:41:39] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[11:41:39] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[11:41:39] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[11:41:39] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[11:41:39] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[11:41:39] [PASSED] VIC 96
[11:41:39] [PASSED] VIC 97
[11:41:39] [PASSED] VIC 101
[11:41:39] [PASSED] VIC 102
[11:41:39] [PASSED] VIC 106
[11:41:39] [PASSED] VIC 107
[11:41:39] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[11:41:39] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[11:41:39] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[11:41:39] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[11:41:39] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[11:41:39] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[11:41:39] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[11:41:39] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[11:41:39] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[11:41:39] [PASSED] Automatic
[11:41:39] [PASSED] Full
[11:41:39] [PASSED] Limited 16:235
[11:41:39] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[11:41:39] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[11:41:39] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[11:41:39] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[11:41:39] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[11:41:39] [PASSED] RGB
[11:41:39] [PASSED] YUV 4:2:0
[11:41:39] [PASSED] YUV 4:2:2
[11:41:39] [PASSED] YUV 4:4:4
[11:41:39] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[11:41:39] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[11:41:39] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[11:41:39] ============= drm_damage_helper (21 subtests) ==============
[11:41:39] [PASSED] drm_test_damage_iter_no_damage
[11:41:39] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[11:41:39] [PASSED] drm_test_damage_iter_no_damage_src_moved
[11:41:39] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[11:41:39] [PASSED] drm_test_damage_iter_no_damage_not_visible
[11:41:39] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[11:41:39] [PASSED] drm_test_damage_iter_no_damage_no_fb
[11:41:39] [PASSED] drm_test_damage_iter_simple_damage
[11:41:39] [PASSED] drm_test_damage_iter_single_damage
[11:41:39] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[11:41:39] [PASSED] drm_test_damage_iter_single_damage_outside_src
[11:41:39] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[11:41:39] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[11:41:39] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[11:41:39] [PASSED] drm_test_damage_iter_single_damage_src_moved
[11:41:39] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[11:41:39] [PASSED] drm_test_damage_iter_damage
[11:41:39] [PASSED] drm_test_damage_iter_damage_one_intersect
[11:41:39] [PASSED] drm_test_damage_iter_damage_one_outside
[11:41:39] [PASSED] drm_test_damage_iter_damage_src_moved
[11:41:39] [PASSED] drm_test_damage_iter_damage_not_visible
[11:41:39] ================ [PASSED] drm_damage_helper ================
[11:41:39] ============== drm_dp_mst_helper (3 subtests) ==============
[11:41:39] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[11:41:39] [PASSED] Clock 154000 BPP 30 DSC disabled
[11:41:39] [PASSED] Clock 234000 BPP 30 DSC disabled
[11:41:39] [PASSED] Clock 297000 BPP 24 DSC disabled
[11:41:39] [PASSED] Clock 332880 BPP 24 DSC enabled
[11:41:39] [PASSED] Clock 324540 BPP 24 DSC enabled
[11:41:39] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[11:41:39] ============== drm_test_dp_mst_calc_pbn_div  ===============
[11:41:39] [PASSED] Link rate 2000000 lane count 4
[11:41:39] [PASSED] Link rate 2000000 lane count 2
[11:41:39] [PASSED] Link rate 2000000 lane count 1
[11:41:39] [PASSED] Link rate 1350000 lane count 4
[11:41:39] [PASSED] Link rate 1350000 lane count 2
[11:41:39] [PASSED] Link rate 1350000 lane count 1
[11:41:39] [PASSED] Link rate 1000000 lane count 4
[11:41:39] [PASSED] Link rate 1000000 lane count 2
[11:41:39] [PASSED] Link rate 1000000 lane count 1
[11:41:39] [PASSED] Link rate 810000 lane count 4
[11:41:39] [PASSED] Link rate 810000 lane count 2
[11:41:39] [PASSED] Link rate 810000 lane count 1
[11:41:39] [PASSED] Link rate 540000 lane count 4
[11:41:39] [PASSED] Link rate 540000 lane count 2
[11:41:39] [PASSED] Link rate 540000 lane count 1
[11:41:39] [PASSED] Link rate 270000 lane count 4
[11:41:39] [PASSED] Link rate 270000 lane count 2
[11:41:39] [PASSED] Link rate 270000 lane count 1
[11:41:39] [PASSED] Link rate 162000 lane count 4
[11:41:39] [PASSED] Link rate 162000 lane count 2
[11:41:39] [PASSED] Link rate 162000 lane count 1
[11:41:39] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[11:41:39] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[11:41:39] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[11:41:39] [PASSED] DP_POWER_UP_PHY with port number
[11:41:39] [PASSED] DP_POWER_DOWN_PHY with port number
[11:41:39] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[11:41:39] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[11:41:39] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[11:41:39] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[11:41:39] [PASSED] DP_QUERY_PAYLOAD with port number
[11:41:39] [PASSED] DP_QUERY_PAYLOAD with VCPI
[11:41:39] [PASSED] DP_REMOTE_DPCD_READ with port number
[11:41:39] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[11:41:39] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[11:41:39] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[11:41:39] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[11:41:39] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[11:41:39] [PASSED] DP_REMOTE_I2C_READ with port number
[11:41:39] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[11:41:39] [PASSED] DP_REMOTE_I2C_READ with transactions array
[11:41:39] [PASSED] DP_REMOTE_I2C_WRITE with port number
[11:41:39] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[11:41:39] [PASSED] DP_REMOTE_I2C_WRITE with data array
[11:41:39] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[11:41:39] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[11:41:39] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[11:41:39] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[11:41:39] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[11:41:39] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[11:41:39] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[11:41:39] ================ [PASSED] drm_dp_mst_helper ================
[11:41:39] ================== drm_exec (7 subtests) ===================
[11:41:39] [PASSED] sanitycheck
[11:41:39] [PASSED] test_lock
[11:41:39] [PASSED] test_lock_unlock
[11:41:39] [PASSED] test_duplicates
[11:41:39] [PASSED] test_prepare
[11:41:39] [PASSED] test_prepare_array
[11:41:39] [PASSED] test_multiple_loops
[11:41:39] ==================== [PASSED] drm_exec =====================
[11:41:39] =========== drm_format_helper_test (17 subtests) ===========
[11:41:39] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[11:41:39] [PASSED] single_pixel_source_buffer
[11:41:39] [PASSED] single_pixel_clip_rectangle
[11:41:39] [PASSED] well_known_colors
[11:41:39] [PASSED] destination_pitch
[11:41:39] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[11:41:39] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[11:41:39] [PASSED] single_pixel_source_buffer
[11:41:39] [PASSED] single_pixel_clip_rectangle
[11:41:39] [PASSED] well_known_colors
[11:41:39] [PASSED] destination_pitch
[11:41:39] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[11:41:39] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[11:41:39] [PASSED] single_pixel_source_buffer
[11:41:39] [PASSED] single_pixel_clip_rectangle
[11:41:39] [PASSED] well_known_colors
[11:41:39] [PASSED] destination_pitch
[11:41:39] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[11:41:39] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[11:41:39] [PASSED] single_pixel_source_buffer
[11:41:39] [PASSED] single_pixel_clip_rectangle
[11:41:39] [PASSED] well_known_colors
[11:41:39] [PASSED] destination_pitch
[11:41:39] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[11:41:39] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[11:41:39] [PASSED] single_pixel_source_buffer
[11:41:39] [PASSED] single_pixel_clip_rectangle
[11:41:39] [PASSED] well_known_colors
[11:41:39] [PASSED] destination_pitch
[11:41:39] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[11:41:39] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[11:41:39] [PASSED] single_pixel_source_buffer
[11:41:39] [PASSED] single_pixel_clip_rectangle
[11:41:39] [PASSED] well_known_colors
[11:41:39] [PASSED] destination_pitch
[11:41:39] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[11:41:39] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[11:41:39] [PASSED] single_pixel_source_buffer
[11:41:39] [PASSED] single_pixel_clip_rectangle
[11:41:39] [PASSED] well_known_colors
[11:41:39] [PASSED] destination_pitch
[11:41:39] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[11:41:39] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[11:41:39] [PASSED] single_pixel_source_buffer
[11:41:39] [PASSED] single_pixel_clip_rectangle
[11:41:39] [PASSED] well_known_colors
[11:41:39] [PASSED] destination_pitch
[11:41:39] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[11:41:39] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[11:41:39] [PASSED] single_pixel_source_buffer
[11:41:39] [PASSED] single_pixel_clip_rectangle
[11:41:39] [PASSED] well_known_colors
[11:41:39] [PASSED] destination_pitch
[11:41:39] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[11:41:39] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[11:41:39] [PASSED] single_pixel_source_buffer
[11:41:39] [PASSED] single_pixel_clip_rectangle
[11:41:39] [PASSED] well_known_colors
[11:41:39] [PASSED] destination_pitch
[11:41:39] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[11:41:39] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[11:41:39] [PASSED] single_pixel_source_buffer
[11:41:39] [PASSED] single_pixel_clip_rectangle
[11:41:39] [PASSED] well_known_colors
[11:41:39] [PASSED] destination_pitch
[11:41:39] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[11:41:39] ============== drm_test_fb_xrgb8888_to_mono  ===============
[11:41:39] [PASSED] single_pixel_source_buffer
[11:41:39] [PASSED] single_pixel_clip_rectangle
[11:41:39] [PASSED] well_known_colors
[11:41:39] [PASSED] destination_pitch
[11:41:39] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[11:41:39] ==================== drm_test_fb_swab  =====================
[11:41:39] [PASSED] single_pixel_source_buffer
[11:41:39] [PASSED] single_pixel_clip_rectangle
[11:41:39] [PASSED] well_known_colors
[11:41:39] [PASSED] destination_pitch
[11:41:39] ================ [PASSED] drm_test_fb_swab =================
[11:41:39] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[11:41:39] [PASSED] single_pixel_source_buffer
[11:41:39] [PASSED] single_pixel_clip_rectangle
[11:41:39] [PASSED] well_known_colors
[11:41:39] [PASSED] destination_pitch
[11:41:39] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[11:41:39] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[11:41:39] [PASSED] single_pixel_source_buffer
[11:41:39] [PASSED] single_pixel_clip_rectangle
[11:41:39] [PASSED] well_known_colors
[11:41:39] [PASSED] destination_pitch
[11:41:39] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[11:41:39] ================= drm_test_fb_clip_offset  =================
[11:41:39] [PASSED] pass through
[11:41:39] [PASSED] horizontal offset
[11:41:39] [PASSED] vertical offset
[11:41:39] [PASSED] horizontal and vertical offset
[11:41:39] [PASSED] horizontal offset (custom pitch)
[11:41:39] [PASSED] vertical offset (custom pitch)
[11:41:39] [PASSED] horizontal and vertical offset (custom pitch)
[11:41:39] ============= [PASSED] drm_test_fb_clip_offset =============
[11:41:39] =================== drm_test_fb_memcpy  ====================
[11:41:39] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[11:41:39] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[11:41:39] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[11:41:39] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[11:41:39] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[11:41:39] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[11:41:39] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[11:41:39] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[11:41:39] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[11:41:39] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[11:41:39] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[11:41:39] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[11:41:39] =============== [PASSED] drm_test_fb_memcpy ================
[11:41:39] ============= [PASSED] drm_format_helper_test ==============
[11:41:39] ================= drm_format (18 subtests) =================
[11:41:39] [PASSED] drm_test_format_block_width_invalid
[11:41:39] [PASSED] drm_test_format_block_width_one_plane
[11:41:39] [PASSED] drm_test_format_block_width_two_plane
[11:41:39] [PASSED] drm_test_format_block_width_three_plane
[11:41:39] [PASSED] drm_test_format_block_width_tiled
[11:41:39] [PASSED] drm_test_format_block_height_invalid
[11:41:39] [PASSED] drm_test_format_block_height_one_plane
[11:41:39] [PASSED] drm_test_format_block_height_two_plane
[11:41:39] [PASSED] drm_test_format_block_height_three_plane
[11:41:39] [PASSED] drm_test_format_block_height_tiled
[11:41:39] [PASSED] drm_test_format_min_pitch_invalid
[11:41:39] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[11:41:39] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[11:41:39] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[11:41:39] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[11:41:39] [PASSED] drm_test_format_min_pitch_two_plane
[11:41:39] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[11:41:39] [PASSED] drm_test_format_min_pitch_tiled
[11:41:39] =================== [PASSED] drm_format ====================
[11:41:39] ============== drm_framebuffer (10 subtests) ===============
[11:41:39] ========== drm_test_framebuffer_check_src_coords  ==========
[11:41:39] [PASSED] Success: source fits into fb
[11:41:39] [PASSED] Fail: overflowing fb with x-axis coordinate
[11:41:39] [PASSED] Fail: overflowing fb with y-axis coordinate
[11:41:39] [PASSED] Fail: overflowing fb with source width
[11:41:39] [PASSED] Fail: overflowing fb with source height
[11:41:39] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[11:41:39] [PASSED] drm_test_framebuffer_cleanup
[11:41:39] =============== drm_test_framebuffer_create  ===============
[11:41:39] [PASSED] ABGR8888 normal sizes
[11:41:39] [PASSED] ABGR8888 max sizes
[11:41:39] [PASSED] ABGR8888 pitch greater than min required
[11:41:39] [PASSED] ABGR8888 pitch less than min required
[11:41:39] [PASSED] ABGR8888 Invalid width
[11:41:39] [PASSED] ABGR8888 Invalid buffer handle
[11:41:39] [PASSED] No pixel format
[11:41:39] [PASSED] ABGR8888 Width 0
[11:41:39] [PASSED] ABGR8888 Height 0
[11:41:39] [PASSED] ABGR8888 Out of bound height * pitch combination
[11:41:39] [PASSED] ABGR8888 Large buffer offset
[11:41:39] [PASSED] ABGR8888 Buffer offset for inexistent plane
[11:41:39] [PASSED] ABGR8888 Invalid flag
[11:41:39] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[11:41:39] [PASSED] ABGR8888 Valid buffer modifier
[11:41:39] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[11:41:39] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[11:41:39] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[11:41:39] [PASSED] NV12 Normal sizes
[11:41:39] [PASSED] NV12 Max sizes
[11:41:39] [PASSED] NV12 Invalid pitch
[11:41:39] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[11:41:39] [PASSED] NV12 different  modifier per-plane
[11:41:39] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[11:41:39] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[11:41:39] [PASSED] NV12 Modifier for inexistent plane
[11:41:39] [PASSED] NV12 Handle for inexistent plane
[11:41:39] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[11:41:39] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[11:41:39] [PASSED] YVU420 Normal sizes
[11:41:39] [PASSED] YVU420 Max sizes
[11:41:39] [PASSED] YVU420 Invalid pitch
[11:41:39] [PASSED] YVU420 Different pitches
[11:41:39] [PASSED] YVU420 Different buffer offsets/pitches
[11:41:39] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[11:41:39] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[11:41:39] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[11:41:39] [PASSED] YVU420 Valid modifier
[11:41:39] [PASSED] YVU420 Different modifiers per plane
[11:41:39] [PASSED] YVU420 Modifier for inexistent plane
[11:41:39] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[11:41:39] [PASSED] X0L2 Normal sizes
[11:41:39] [PASSED] X0L2 Max sizes
[11:41:39] [PASSED] X0L2 Invalid pitch
[11:41:39] [PASSED] X0L2 Pitch greater than minimum required
[11:41:39] [PASSED] X0L2 Handle for inexistent plane
[11:41:39] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[11:41:39] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[11:41:39] [PASSED] X0L2 Valid modifier
[11:41:39] [PASSED] X0L2 Modifier for inexistent plane
[11:41:39] =========== [PASSED] drm_test_framebuffer_create ===========
[11:41:39] [PASSED] drm_test_framebuffer_free
[11:41:39] [PASSED] drm_test_framebuffer_init
[11:41:39] [PASSED] drm_test_framebuffer_init_bad_format
[11:41:39] [PASSED] drm_test_framebuffer_init_dev_mismatch
[11:41:39] [PASSED] drm_test_framebuffer_lookup
[11:41:39] [PASSED] drm_test_framebuffer_lookup_inexistent
[11:41:39] [PASSED] drm_test_framebuffer_modifiers_not_supported
[11:41:39] ================= [PASSED] drm_framebuffer =================
[11:41:39] ================ drm_gem_shmem (8 subtests) ================
[11:41:39] [PASSED] drm_gem_shmem_test_obj_create
[11:41:39] [PASSED] drm_gem_shmem_test_obj_create_private
[11:41:39] [PASSED] drm_gem_shmem_test_pin_pages
[11:41:39] [PASSED] drm_gem_shmem_test_vmap
[11:41:39] [PASSED] drm_gem_shmem_test_get_sg_table
[11:41:39] [PASSED] drm_gem_shmem_test_get_pages_sgt
[11:41:39] [PASSED] drm_gem_shmem_test_madvise
[11:41:39] [PASSED] drm_gem_shmem_test_purge
[11:41:39] ================== [PASSED] drm_gem_shmem ==================
[11:41:39] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[11:41:39] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[11:41:39] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[11:41:39] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[11:41:39] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[11:41:39] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[11:41:39] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[11:41:39] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[11:41:39] [PASSED] Automatic
[11:41:39] [PASSED] Full
[11:41:39] [PASSED] Limited 16:235
[11:41:39] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[11:41:39] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[11:41:39] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[11:41:39] [PASSED] drm_test_check_disable_connector
[11:41:39] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[11:41:39] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[11:41:39] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[11:41:39] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[11:41:39] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[11:41:39] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[11:41:39] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[11:41:39] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[11:41:39] [PASSED] drm_test_check_output_bpc_dvi
[11:41:39] [PASSED] drm_test_check_output_bpc_format_vic_1
[11:41:39] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[11:41:39] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[11:41:39] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[11:41:39] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[11:41:39] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[11:41:39] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[11:41:39] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[11:41:39] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[11:41:39] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[11:41:39] [PASSED] drm_test_check_broadcast_rgb_value
[11:41:39] [PASSED] drm_test_check_bpc_8_value
[11:41:39] [PASSED] drm_test_check_bpc_10_value
[11:41:39] [PASSED] drm_test_check_bpc_12_value
[11:41:39] [PASSED] drm_test_check_format_value
[11:41:39] [PASSED] drm_test_check_tmds_char_value
[11:41:39] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[11:41:39] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[11:41:39] [PASSED] drm_test_check_mode_valid
[11:41:39] [PASSED] drm_test_check_mode_valid_reject
[11:41:39] [PASSED] drm_test_check_mode_valid_reject_rate
[11:41:39] [PASSED] drm_test_check_mode_valid_reject_max_clock
[11:41:39] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[11:41:39] ================= drm_managed (2 subtests) =================
[11:41:39] [PASSED] drm_test_managed_release_action
[11:41:39] [PASSED] drm_test_managed_run_action
[11:41:39] =================== [PASSED] drm_managed ===================
[11:41:39] =================== drm_mm (6 subtests) ====================
[11:41:39] [PASSED] drm_test_mm_init
[11:41:39] [PASSED] drm_test_mm_debug
[11:41:39] [PASSED] drm_test_mm_align32
[11:41:39] [PASSED] drm_test_mm_align64
[11:41:39] [PASSED] drm_test_mm_lowest
[11:41:39] [PASSED] drm_test_mm_highest
[11:41:39] ===================== [PASSED] drm_mm ======================
[11:41:39] ============= drm_modes_analog_tv (5 subtests) =============
[11:41:39] [PASSED] drm_test_modes_analog_tv_mono_576i
[11:41:39] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[11:41:39] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[11:41:39] [PASSED] drm_test_modes_analog_tv_pal_576i
[11:41:39] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[11:41:39] =============== [PASSED] drm_modes_analog_tv ===============
[11:41:39] ============== drm_plane_helper (2 subtests) ===============
[11:41:39] =============== drm_test_check_plane_state  ================
[11:41:39] [PASSED] clipping_simple
[11:41:39] [PASSED] clipping_rotate_reflect
[11:41:39] [PASSED] positioning_simple
[11:41:39] [PASSED] upscaling
[11:41:39] [PASSED] downscaling
[11:41:39] [PASSED] rounding1
[11:41:39] [PASSED] rounding2
[11:41:39] [PASSED] rounding3
[11:41:39] [PASSED] rounding4
[11:41:39] =========== [PASSED] drm_test_check_plane_state ============
[11:41:39] =========== drm_test_check_invalid_plane_state  ============
[11:41:39] [PASSED] positioning_invalid
[11:41:39] [PASSED] upscaling_invalid
[11:41:39] [PASSED] downscaling_invalid
[11:41:39] ======= [PASSED] drm_test_check_invalid_plane_state ========
[11:41:39] ================ [PASSED] drm_plane_helper =================
[11:41:39] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[11:41:39] ====== drm_test_connector_helper_tv_get_modes_check  =======
[11:41:39] [PASSED] None
[11:41:39] [PASSED] PAL
[11:41:39] [PASSED] NTSC
[11:41:39] [PASSED] Both, NTSC Default
[11:41:39] [PASSED] Both, PAL Default
[11:41:39] [PASSED] Both, NTSC Default, with PAL on command-line
[11:41:39] [PASSED] Both, PAL Default, with NTSC on command-line
[11:41:39] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[11:41:39] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[11:41:39] ================== drm_rect (9 subtests) ===================
[11:41:39] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[11:41:39] [PASSED] drm_test_rect_clip_scaled_not_clipped
[11:41:39] [PASSED] drm_test_rect_clip_scaled_clipped
[11:41:39] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[11:41:39] ================= drm_test_rect_intersect  =================
[11:41:39] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[11:41:39] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[11:41:39] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[11:41:39] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[11:41:39] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[11:41:39] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[11:41:39] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[11:41:39] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[11:41:39] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[11:41:39] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[11:41:39] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[11:41:39] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[11:41:39] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[11:41:39] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[11:41:39] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[11:41:39] ============= [PASSED] drm_test_rect_intersect =============
[11:41:39] ================ drm_test_rect_calc_hscale  ================
[11:41:39] [PASSED] normal use
[11:41:39] [PASSED] out of max range
[11:41:39] [PASSED] out of min range
[11:41:39] [PASSED] zero dst
[11:41:39] [PASSED] negative src
[11:41:39] [PASSED] negative dst
[11:41:39] ============ [PASSED] drm_test_rect_calc_hscale ============
[11:41:39] ================ drm_test_rect_calc_vscale  ================
[11:41:39] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[11:41:39] [PASSED] out of max range
[11:41:39] [PASSED] out of min range
[11:41:39] [PASSED] zero dst
[11:41:39] [PASSED] negative src
[11:41:39] [PASSED] negative dst
[11:41:39] ============ [PASSED] drm_test_rect_calc_vscale ============
[11:41:39] ================== drm_test_rect_rotate  ===================
[11:41:39] [PASSED] reflect-x
[11:41:39] [PASSED] reflect-y
[11:41:39] [PASSED] rotate-0
[11:41:39] [PASSED] rotate-90
[11:41:39] [PASSED] rotate-180
[11:41:39] [PASSED] rotate-270
[11:41:39] ============== [PASSED] drm_test_rect_rotate ===============
[11:41:39] ================ drm_test_rect_rotate_inv  =================
[11:41:39] [PASSED] reflect-x
[11:41:39] [PASSED] reflect-y
[11:41:39] [PASSED] rotate-0
[11:41:39] [PASSED] rotate-90
[11:41:39] [PASSED] rotate-180
[11:41:39] [PASSED] rotate-270
[11:41:39] ============ [PASSED] drm_test_rect_rotate_inv =============
[11:41:39] ==================== [PASSED] drm_rect =====================
[11:41:39] ============ drm_sysfb_modeset_test (1 subtest) ============
[11:41:39] ============ drm_test_sysfb_build_fourcc_list  =============
[11:41:39] [PASSED] no native formats
[11:41:39] [PASSED] XRGB8888 as native format
[11:41:39] [PASSED] remove duplicates
[11:41:39] [PASSED] convert alpha formats
[11:41:39] [PASSED] random formats
[11:41:39] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[11:41:39] ============= [PASSED] drm_sysfb_modeset_test ==============
[11:41:39] ================== drm_fixp (2 subtests) ===================
[11:41:39] [PASSED] drm_test_int2fixp
[11:41:39] [PASSED] drm_test_sm2fixp
[11:41:39] ==================== [PASSED] drm_fixp =====================
[11:41:39] ============================================================
[11:41:39] Testing complete. Ran 624 tests: passed: 624
[11:41:39] Elapsed time: 27.399s total, 1.655s configuring, 25.323s building, 0.374s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[11:41:39] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:41:41] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:41:50] Starting KUnit Kernel (1/1)...
[11:41:50] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:41:50] ================= ttm_device (5 subtests) ==================
[11:41:50] [PASSED] ttm_device_init_basic
[11:41:50] [PASSED] ttm_device_init_multiple
[11:41:50] [PASSED] ttm_device_fini_basic
[11:41:50] [PASSED] ttm_device_init_no_vma_man
[11:41:50] ================== ttm_device_init_pools  ==================
[11:41:50] [PASSED] No DMA allocations, no DMA32 required
[11:41:50] [PASSED] DMA allocations, DMA32 required
[11:41:50] [PASSED] No DMA allocations, DMA32 required
[11:41:50] [PASSED] DMA allocations, no DMA32 required
[11:41:50] ============== [PASSED] ttm_device_init_pools ==============
[11:41:50] =================== [PASSED] ttm_device ====================
[11:41:50] ================== ttm_pool (8 subtests) ===================
[11:41:50] ================== ttm_pool_alloc_basic  ===================
[11:41:50] [PASSED] One page
[11:41:50] [PASSED] More than one page
[11:41:50] [PASSED] Above the allocation limit
[11:41:50] [PASSED] One page, with coherent DMA mappings enabled
[11:41:50] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:41:50] ============== [PASSED] ttm_pool_alloc_basic ===============
[11:41:50] ============== ttm_pool_alloc_basic_dma_addr  ==============
[11:41:50] [PASSED] One page
[11:41:50] [PASSED] More than one page
[11:41:50] [PASSED] Above the allocation limit
[11:41:50] [PASSED] One page, with coherent DMA mappings enabled
[11:41:50] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:41:50] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[11:41:50] [PASSED] ttm_pool_alloc_order_caching_match
[11:41:50] [PASSED] ttm_pool_alloc_caching_mismatch
[11:41:50] [PASSED] ttm_pool_alloc_order_mismatch
[11:41:50] [PASSED] ttm_pool_free_dma_alloc
[11:41:50] [PASSED] ttm_pool_free_no_dma_alloc
[11:41:50] [PASSED] ttm_pool_fini_basic
[11:41:50] ==================== [PASSED] ttm_pool =====================
[11:41:50] ================ ttm_resource (8 subtests) =================
[11:41:50] ================= ttm_resource_init_basic  =================
[11:41:50] [PASSED] Init resource in TTM_PL_SYSTEM
[11:41:50] [PASSED] Init resource in TTM_PL_VRAM
[11:41:50] [PASSED] Init resource in a private placement
[11:41:50] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[11:41:50] ============= [PASSED] ttm_resource_init_basic =============
[11:41:50] [PASSED] ttm_resource_init_pinned
[11:41:50] [PASSED] ttm_resource_fini_basic
[11:41:50] [PASSED] ttm_resource_manager_init_basic
[11:41:50] [PASSED] ttm_resource_manager_usage_basic
[11:41:50] [PASSED] ttm_resource_manager_set_used_basic
[11:41:50] [PASSED] ttm_sys_man_alloc_basic
[11:41:50] [PASSED] ttm_sys_man_free_basic
[11:41:50] ================== [PASSED] ttm_resource ===================
[11:41:50] =================== ttm_tt (15 subtests) ===================
[11:41:50] ==================== ttm_tt_init_basic  ====================
[11:41:50] [PASSED] Page-aligned size
[11:41:50] [PASSED] Extra pages requested
[11:41:50] ================ [PASSED] ttm_tt_init_basic ================
[11:41:50] [PASSED] ttm_tt_init_misaligned
[11:41:50] [PASSED] ttm_tt_fini_basic
[11:41:50] [PASSED] ttm_tt_fini_sg
[11:41:50] [PASSED] ttm_tt_fini_shmem
[11:41:50] [PASSED] ttm_tt_create_basic
[11:41:50] [PASSED] ttm_tt_create_invalid_bo_type
[11:41:50] [PASSED] ttm_tt_create_ttm_exists
[11:41:50] [PASSED] ttm_tt_create_failed
[11:41:50] [PASSED] ttm_tt_destroy_basic
[11:41:50] [PASSED] ttm_tt_populate_null_ttm
[11:41:50] [PASSED] ttm_tt_populate_populated_ttm
[11:41:50] [PASSED] ttm_tt_unpopulate_basic
[11:41:50] [PASSED] ttm_tt_unpopulate_empty_ttm
[11:41:50] [PASSED] ttm_tt_swapin_basic
[11:41:50] ===================== [PASSED] ttm_tt ======================
[11:41:50] =================== ttm_bo (14 subtests) ===================
[11:41:50] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[11:41:50] [PASSED] Cannot be interrupted and sleeps
[11:41:50] [PASSED] Cannot be interrupted, locks straight away
[11:41:50] [PASSED] Can be interrupted, sleeps
[11:41:50] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[11:41:50] [PASSED] ttm_bo_reserve_locked_no_sleep
[11:41:50] [PASSED] ttm_bo_reserve_no_wait_ticket
[11:41:50] [PASSED] ttm_bo_reserve_double_resv
[11:41:50] [PASSED] ttm_bo_reserve_interrupted
[11:41:50] [PASSED] ttm_bo_reserve_deadlock
[11:41:50] [PASSED] ttm_bo_unreserve_basic
[11:41:50] [PASSED] ttm_bo_unreserve_pinned
[11:41:50] [PASSED] ttm_bo_unreserve_bulk
[11:41:50] [PASSED] ttm_bo_fini_basic
[11:41:50] [PASSED] ttm_bo_fini_shared_resv
[11:41:50] [PASSED] ttm_bo_pin_basic
[11:41:50] [PASSED] ttm_bo_pin_unpin_resource
[11:41:50] [PASSED] ttm_bo_multiple_pin_one_unpin
[11:41:50] ===================== [PASSED] ttm_bo ======================
[11:41:50] ============== ttm_bo_validate (21 subtests) ===============
[11:41:50] ============== ttm_bo_init_reserved_sys_man  ===============
[11:41:50] [PASSED] Buffer object for userspace
[11:41:50] [PASSED] Kernel buffer object
[11:41:50] [PASSED] Shared buffer object
[11:41:50] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[11:41:50] ============== ttm_bo_init_reserved_mock_man  ==============
[11:41:50] [PASSED] Buffer object for userspace
[11:41:50] [PASSED] Kernel buffer object
[11:41:50] [PASSED] Shared buffer object
[11:41:50] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[11:41:50] [PASSED] ttm_bo_init_reserved_resv
[11:41:50] ================== ttm_bo_validate_basic  ==================
[11:41:50] [PASSED] Buffer object for userspace
[11:41:50] [PASSED] Kernel buffer object
[11:41:50] [PASSED] Shared buffer object
[11:41:50] ============== [PASSED] ttm_bo_validate_basic ==============
[11:41:50] [PASSED] ttm_bo_validate_invalid_placement
[11:41:50] ============= ttm_bo_validate_same_placement  ==============
[11:41:50] [PASSED] System manager
[11:41:50] [PASSED] VRAM manager
[11:41:50] ========= [PASSED] ttm_bo_validate_same_placement ==========
[11:41:50] [PASSED] ttm_bo_validate_failed_alloc
[11:41:50] [PASSED] ttm_bo_validate_pinned
[11:41:50] [PASSED] ttm_bo_validate_busy_placement
[11:41:50] ================ ttm_bo_validate_multihop  =================
[11:41:50] [PASSED] Buffer object for userspace
[11:41:50] [PASSED] Kernel buffer object
[11:41:50] [PASSED] Shared buffer object
[11:41:50] ============ [PASSED] ttm_bo_validate_multihop =============
[11:41:50] ========== ttm_bo_validate_no_placement_signaled  ==========
[11:41:50] [PASSED] Buffer object in system domain, no page vector
[11:41:50] [PASSED] Buffer object in system domain with an existing page vector
[11:41:50] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[11:41:50] ======== ttm_bo_validate_no_placement_not_signaled  ========
[11:41:50] [PASSED] Buffer object for userspace
[11:41:50] [PASSED] Kernel buffer object
[11:41:50] [PASSED] Shared buffer object
[11:41:50] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[11:41:50] [PASSED] ttm_bo_validate_move_fence_signaled
[11:41:50] ========= ttm_bo_validate_move_fence_not_signaled  =========
[11:41:50] [PASSED] Waits for GPU
[11:41:50] [PASSED] Tries to lock straight away
[11:41:50] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[11:41:50] [PASSED] ttm_bo_validate_happy_evict
[11:41:50] [PASSED] ttm_bo_validate_all_pinned_evict
[11:41:50] [PASSED] ttm_bo_validate_allowed_only_evict
[11:41:50] [PASSED] ttm_bo_validate_deleted_evict
[11:41:50] [PASSED] ttm_bo_validate_busy_domain_evict
[11:41:50] [PASSED] ttm_bo_validate_evict_gutting
[11:41:50] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[11:41:50] ================= [PASSED] ttm_bo_validate =================
[11:41:50] ============================================================
[11:41:50] Testing complete. Ran 101 tests: passed: 101
[11:41:50] Elapsed time: 11.258s total, 1.692s configuring, 9.349s building, 0.181s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for Use trans push mechanism to generate frame change event (rev9)

[Patchwork]

== Series Details ==

Series: Use trans push mechanism to generate frame change event (rev9)
URL   : https://patchwork.freedesktop.org/series/139831/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast cab246648fd89efbe8d20ed4c86e7fcebd7606da
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_atomic.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_color.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_crtc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_crtc_state_dump.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_cursor.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_cx0_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_debugfs.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_driver.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_irq.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_display_power_well.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_mst.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dsb.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_flipq.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_frontbuffer.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_hdmi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_lt_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_panel.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_plane.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_vblank.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_vrr.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/skl_universal_plane.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Use trans push mechanism to generate frame change event (rev9)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 976 bytes --]

== Series Details ==

Series: Use trans push mechanism to generate frame change event (rev9)
URL   : https://patchwork.freedesktop.org/series/139831/
State : success

== Summary ==

CI Bug Log - changes from xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da_BAT -> xe-pw-139831v9_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da -> xe-pw-139831v9

  IGT_8674: f38f4d8e9c65aff45ac807e646d06e38bc3193a2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da: cab246648fd89efbe8d20ed4c86e7fcebd7606da
  xe-pw-139831v9: 139831v9

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/index.html

[-- Attachment #2: Type: text/html, Size: 1524 bytes --]

✗ Xe.CI.Full: failure for Use trans push mechanism to generate frame change event (rev9)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 55595 bytes --]

== Series Details ==

Series: Use trans push mechanism to generate frame change event (rev9)
URL   : https://patchwork.freedesktop.org/series/139831/
State : failure

== Summary ==

CI Bug Log - changes from xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da_FULL -> xe-pw-139831v9_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-139831v9_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-139831v9_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-139831v9_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_invalid_mode@zero-vdisplay@pipe-d-hdmi-a-3:
    - shard-bmg:          [PASS][1] -> [DMESG-WARN][2] +1 other test dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_invalid_mode@zero-vdisplay@pipe-d-hdmi-a-3.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_invalid_mode@zero-vdisplay@pipe-d-hdmi-a-3.html

  * igt@xe_exec_system_allocator@many-malloc-busy-nomemset:
    - shard-bmg:          [PASS][3] -> [DMESG-FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@xe_exec_system_allocator@many-malloc-busy-nomemset.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@xe_exec_system_allocator@many-malloc-busy-nomemset.html

  
Known issues
------------

  Here are the changes found in xe-pw-139831v9_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#1124]) +2 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html

  * igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
    - shard-bmg:          [PASS][6] -> [SKIP][7] ([Intel XE#2314] / [Intel XE#2894])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html

  * igt@kms_bw@linear-tiling-1-displays-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#367])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_bw@linear-tiling-1-displays-2160x1440p.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#2887]) +2 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#2652] / [Intel XE#787]) +7 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_cdclk@plane-scaling:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#2724])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_hpd@hdmi-hpd-fast:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2252]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_chamelium_hpd@hdmi-hpd-fast.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#2390])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_cursor_crc@cursor-onscreen-max-size:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#2320]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_cursor_crc@cursor-onscreen-max-size.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][15] -> [SKIP][16] ([Intel XE#2291]) +3 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#4354])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#776])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@psr2:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#2374])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop:
    - shard-bmg:          [PASS][20] -> [SKIP][21] ([Intel XE#2316]) +3 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_flip@2x-flip-vs-dpms-on-nop.html

  * igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#2316])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2293] / [Intel XE#2380])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2293]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#2311]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#4141])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#2312]) +9 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2313]) +2 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-2:
    - shard-bmg:          [PASS][29] -> [ABORT][30] ([Intel XE#6740]) +1 other test abort
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-4/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-2.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-3/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-2.html

  * igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [ABORT][31] ([Intel XE#6740])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-1/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3.html

  * igt@kms_plane_lowres@tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#2393])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_plane_lowres@tiling-y.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-bmg:          [PASS][33] -> [SKIP][34] ([Intel XE#4596])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_plane_multiple@2x-tiling-4.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#2938])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_rpm@legacy-planes-dpms:
    - shard-bmg:          [PASS][36] -> [SKIP][37] ([Intel XE#6693])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_pm_rpm@legacy-planes-dpms.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_pm_rpm@legacy-planes-dpms.html

  * igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area-big-fb:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#1406] / [Intel XE#1489])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr@psr-primary-page-flip:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_psr@psr-primary-page-flip.html

  * igt@kms_setmode@invalid-clone-single-crtc-stealing:
    - shard-bmg:          [PASS][40] -> [SKIP][41] ([Intel XE#1435])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-10/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_setmode@invalid-clone-single-crtc-stealing.html

  * igt@kms_sharpness_filter@filter-strength:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#6503])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_sharpness_filter@filter-strength.html

  * igt@xe_create@invalid-pad:
    - shard-bmg:          [PASS][43] -> [SKIP][44] ([Intel XE#6557] / [Intel XE#6703]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@xe_create@invalid-pad.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@xe_create@invalid-pad.html

  * igt@xe_eudebug@basic-vm-access-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#4837]) +2 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@xe_eudebug@basic-vm-access-userptr.html

  * igt@xe_eudebug_online@interrupt-all-set-breakpoint:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#4837] / [Intel XE#6665])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@xe_eudebug_online@interrupt-all-set-breakpoint.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [PASS][47] -> [INCOMPLETE][48] ([Intel XE#6321])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-8/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-9/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#2322]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind.html

  * igt@xe_exec_multi_queue@many-execs-close-fd-smem:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#6874]) +5 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@xe_exec_multi_queue@many-execs-close-fd-smem.html

  * igt@xe_exec_system_allocator@many-execqueues-new-busy:
    - shard-bmg:          [PASS][51] -> [SKIP][52] ([Intel XE#6703]) +134 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@xe_exec_system_allocator@many-execqueues-new-busy.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@xe_exec_system_allocator@many-execqueues-new-busy.html

  * igt@xe_exec_system_allocator@many-large-mmap-huge-nomemset:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#4943]) +4 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@xe_exec_system_allocator@many-large-mmap-huge-nomemset.html

  * igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#6281])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add.html

  * igt@xe_pm@d3hot-i2c:
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#5742])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@xe_pm@d3hot-i2c.html

  * igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_enhance0:
    - shard-lnl:          [PASS][56] -> [FAIL][57] ([Intel XE#6251]) +2 other tests fail
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-lnl-7/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_enhance0.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-lnl-8/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_enhance0.html

  * igt@xe_pxp@pxp-stale-queue-post-termination-irq:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#4733])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@xe_pxp@pxp-stale-queue-post-termination-irq.html

  * igt@xe_query@multigpu-query-uc-fw-version-huc:
    - shard-bmg:          NOTRUN -> [SKIP][59] ([Intel XE#944])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@xe_query@multigpu-query-uc-fw-version-huc.html

  
#### Possible fixes ####

  * igt@intel_hwmon@hwmon-read:
    - shard-bmg:          [SKIP][60] ([Intel XE#5177] / [Intel XE#6703]) -> [PASS][61]
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@intel_hwmon@hwmon-read.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@intel_hwmon@hwmon-read.html

  * igt@kms_atomic_transition@plane-all-transition-fencing:
    - shard-bmg:          [INCOMPLETE][62] ([Intel XE#1727] / [Intel XE#6819]) -> [PASS][63]
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-3/igt@kms_atomic_transition@plane-all-transition-fencing.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_atomic_transition@plane-all-transition-fencing.html

  * igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
    - shard-bmg:          [SKIP][64] ([Intel XE#2314] / [Intel XE#2894]) -> [PASS][65]
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-4/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-10/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-legacy:
    - shard-bmg:          [SKIP][66] ([Intel XE#2291]) -> [PASS][67] +2 other tests pass
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-3/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [FAIL][68] ([Intel XE#6715]) -> [PASS][69]
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-10/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_flip@2x-blocking-absolute-wf_vblank:
    - shard-bmg:          [DMESG-WARN][70] -> [PASS][71] +1 other test pass
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_flip@2x-blocking-absolute-wf_vblank.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_flip@2x-blocking-absolute-wf_vblank.html

  * igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-bmg:          [SKIP][72] ([Intel XE#2316]) -> [PASS][73] +4 other tests pass
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-4/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-10/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][74] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][75] +3 other tests pass
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_pm_rpm@basic-rte:
    - shard-bmg:          [SKIP][76] ([Intel XE#6693]) -> [PASS][77]
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_pm_rpm@basic-rte.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_pm_rpm@basic-rte.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [FAIL][78] ([Intel XE#2142]) -> [PASS][79] +1 other test pass
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-lnl-4/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-lnl-3/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  * igt@xe_exec_balancer@twice-virtual-basic:
    - shard-bmg:          [SKIP][80] ([Intel XE#6557] / [Intel XE#6703]) -> [PASS][81] +2 other tests pass
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@xe_exec_balancer@twice-virtual-basic.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@xe_exec_balancer@twice-virtual-basic.html

  * igt@xe_exec_system_allocator@many-execqueues-mmap-race:
    - shard-bmg:          [SKIP][82] ([Intel XE#6703]) -> [PASS][83] +133 other tests pass
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@xe_exec_system_allocator@many-execqueues-mmap-race.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@xe_exec_system_allocator@many-execqueues-mmap-race.html

  * igt@xe_exec_system_allocator@many-stride-malloc-prefetch:
    - shard-bmg:          [WARN][84] ([Intel XE#5786]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-4/igt@xe_exec_system_allocator@many-stride-malloc-prefetch.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-10/igt@xe_exec_system_allocator@many-stride-malloc-prefetch.html

  * igt@xe_live_ktest@xe_migrate@xe_migrate_sanity_kunit:
    - shard-bmg:          [FAIL][86] ([Intel XE#6558]) -> [PASS][87] +2 other tests pass
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@xe_live_ktest@xe_migrate@xe_migrate_sanity_kunit.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@xe_live_ktest@xe_migrate@xe_migrate_sanity_kunit.html

  
#### Warnings ####

  * igt@kms_big_fb@4-tiled-64bpp-rotate-270:
    - shard-bmg:          [SKIP][88] ([Intel XE#6703]) -> [SKIP][89] ([Intel XE#2327])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-270:
    - shard-bmg:          [SKIP][90] ([Intel XE#2327]) -> [SKIP][91] ([Intel XE#6703])
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-bmg:          [SKIP][92] ([Intel XE#607]) -> [SKIP][93] ([Intel XE#6703])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-bmg:          [SKIP][94] ([Intel XE#6703]) -> [SKIP][95] ([Intel XE#1124]) +2 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
    - shard-bmg:          [SKIP][96] ([Intel XE#1124]) -> [SKIP][97] ([Intel XE#6703]) +1 other test skip
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html

  * igt@kms_bw@linear-tiling-3-displays-2160x1440p:
    - shard-bmg:          [SKIP][98] ([Intel XE#6703]) -> [SKIP][99] ([Intel XE#367])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_bw@linear-tiling-3-displays-2160x1440p.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_bw@linear-tiling-3-displays-2160x1440p.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc:
    - shard-bmg:          [SKIP][100] ([Intel XE#2887]) -> [SKIP][101] ([Intel XE#6703]) +1 other test skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs:
    - shard-bmg:          [SKIP][102] ([Intel XE#6703]) -> [SKIP][103] ([Intel XE#2887]) +3 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
    - shard-bmg:          [SKIP][104] ([Intel XE#6703]) -> [SKIP][105] ([Intel XE#2652] / [Intel XE#787])
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html

  * igt@kms_chamelium_color@ctm-0-75:
    - shard-bmg:          [SKIP][106] ([Intel XE#2325]) -> [SKIP][107] ([Intel XE#6703])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_chamelium_color@ctm-0-75.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_chamelium_color@ctm-0-75.html

  * igt@kms_chamelium_frames@dp-crc-single:
    - shard-bmg:          [SKIP][108] ([Intel XE#2252]) -> [SKIP][109] ([Intel XE#6703]) +2 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_chamelium_frames@dp-crc-single.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_chamelium_frames@dp-crc-single.html

  * igt@kms_chamelium_frames@hdmi-frame-dump:
    - shard-bmg:          [SKIP][110] ([Intel XE#6703]) -> [SKIP][111] ([Intel XE#2252]) +1 other test skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_chamelium_frames@hdmi-frame-dump.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_chamelium_frames@hdmi-frame-dump.html

  * igt@kms_chamelium_sharpness_filter@filter-basic:
    - shard-bmg:          [SKIP][112] ([Intel XE#6703]) -> [SKIP][113] ([Intel XE#6507])
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_chamelium_sharpness_filter@filter-basic.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_chamelium_sharpness_filter@filter-basic.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-bmg:          [SKIP][114] ([Intel XE#2390]) -> [SKIP][115] ([Intel XE#6703])
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_content_protection@dp-mst-lic-type-1.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_cursor_crc@cursor-offscreen-256x85:
    - shard-bmg:          [SKIP][116] ([Intel XE#6703]) -> [SKIP][117] ([Intel XE#2320])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_cursor_crc@cursor-offscreen-256x85.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_cursor_crc@cursor-offscreen-256x85.html

  * igt@kms_cursor_crc@cursor-onscreen-256x85:
    - shard-bmg:          [SKIP][118] ([Intel XE#2320]) -> [SKIP][119] ([Intel XE#6703]) +1 other test skip
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_cursor_crc@cursor-onscreen-256x85.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_cursor_crc@cursor-onscreen-256x85.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
    - shard-bmg:          [SKIP][120] ([Intel XE#6703]) -> [SKIP][121] ([Intel XE#2293] / [Intel XE#2380])
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
    - shard-bmg:          [SKIP][122] ([Intel XE#2293] / [Intel XE#2380]) -> [SKIP][123] ([Intel XE#6703]) +1 other test skip
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][124] ([Intel XE#2311]) -> [SKIP][125] ([Intel XE#2312]) +11 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][126] ([Intel XE#6703]) -> [SKIP][127] ([Intel XE#2311]) +6 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-blt:
    - shard-bmg:          [SKIP][128] ([Intel XE#2312]) -> [SKIP][129] ([Intel XE#2311]) +13 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-blt.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt:
    - shard-bmg:          [SKIP][130] ([Intel XE#6703]) -> [SKIP][131] ([Intel XE#4141]) +2 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
    - shard-bmg:          [SKIP][132] ([Intel XE#4141]) -> [SKIP][133] ([Intel XE#6703]) +3 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-render:
    - shard-bmg:          [SKIP][134] ([Intel XE#4141]) -> [SKIP][135] ([Intel XE#2312]) +4 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-render.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
    - shard-bmg:          [SKIP][136] ([Intel XE#2312]) -> [SKIP][137] ([Intel XE#4141]) +3 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-10/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render:
    - shard-bmg:          [SKIP][138] ([Intel XE#2311]) -> [SKIP][139] ([Intel XE#6703]) +7 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-pgflip-blt:
    - shard-bmg:          [SKIP][140] ([Intel XE#6557] / [Intel XE#6703]) -> [SKIP][141] ([Intel XE#2311])
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-pgflip-blt.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][142] ([Intel XE#6703]) -> [SKIP][143] ([Intel XE#2313]) +6 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-wc.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][144] ([Intel XE#2312]) -> [SKIP][145] ([Intel XE#2313]) +13 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-10/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-msflip-blt:
    - shard-bmg:          [SKIP][146] ([Intel XE#2313]) -> [SKIP][147] ([Intel XE#2312]) +10 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-10/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-msflip-blt.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt:
    - shard-bmg:          [SKIP][148] ([Intel XE#2313]) -> [SKIP][149] ([Intel XE#6703]) +5 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][150] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][151] ([Intel XE#6703])
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_hdr@brightness-with-hdr.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][152] ([Intel XE#1503]) -> [ABORT][153] ([Intel XE#6740])
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-9/igt@kms_hdr@invalid-hdr.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-1/igt@kms_hdr@invalid-hdr.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-bmg:          [SKIP][154] ([Intel XE#6703]) -> [SKIP][155] ([Intel XE#2486])
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_panel_fitting@atomic-fastset.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-bmg:          [SKIP][156] ([Intel XE#4596]) -> [SKIP][157] ([Intel XE#5021])
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-4/igt@kms_plane_multiple@2x-tiling-yf.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_pm_backlight@fade:
    - shard-bmg:          [SKIP][158] ([Intel XE#870]) -> [SKIP][159] ([Intel XE#6703])
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_pm_backlight@fade.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_pm_backlight@fade.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf:
    - shard-bmg:          [SKIP][160] ([Intel XE#1406] / [Intel XE#6703]) -> [SKIP][161] ([Intel XE#1406] / [Intel XE#1489])
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html

  * igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area:
    - shard-bmg:          [SKIP][162] ([Intel XE#1406] / [Intel XE#1489]) -> [SKIP][163] ([Intel XE#1406] / [Intel XE#6703]) +1 other test skip
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr@fbc-psr-sprite-render:
    - shard-bmg:          [SKIP][164] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) -> [SKIP][165] ([Intel XE#1406] / [Intel XE#6703]) +2 other tests skip
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_psr@fbc-psr-sprite-render.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_psr@fbc-psr-sprite-render.html

  * igt@kms_psr@fbc-psr-suspend:
    - shard-bmg:          [SKIP][166] ([Intel XE#1406] / [Intel XE#6703]) -> [SKIP][167] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_psr@fbc-psr-suspend.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_psr@fbc-psr-suspend.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-bmg:          [SKIP][168] ([Intel XE#2330]) -> [SKIP][169] ([Intel XE#6703])
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-bmg:          [SKIP][170] ([Intel XE#6703]) -> [SKIP][171] ([Intel XE#2330])
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_sharpness_filter@filter-basic:
    - shard-bmg:          [SKIP][172] ([Intel XE#6703]) -> [SKIP][173] ([Intel XE#6503])
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_sharpness_filter@filter-basic.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_sharpness_filter@filter-basic.html

  * igt@kms_sharpness_filter@filter-modifiers:
    - shard-bmg:          [SKIP][174] ([Intel XE#6503]) -> [SKIP][175] ([Intel XE#6703])
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_sharpness_filter@filter-modifiers.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_sharpness_filter@filter-modifiers.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][176] ([Intel XE#2509]) -> [SKIP][177] ([Intel XE#2426])
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@cmrr:
    - shard-bmg:          [SKIP][178] ([Intel XE#6703]) -> [SKIP][179] ([Intel XE#2168])
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_vrr@cmrr.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@kms_vrr@cmrr.html

  * igt@kms_vrr@seamless-rr-switch-virtual:
    - shard-bmg:          [SKIP][180] ([Intel XE#1499]) -> [SKIP][181] ([Intel XE#6703])
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_vrr@seamless-rr-switch-virtual.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@kms_vrr@seamless-rr-switch-virtual.html

  * igt@xe_eudebug@basic-connect:
    - shard-bmg:          [SKIP][182] ([Intel XE#4837]) -> [SKIP][183] ([Intel XE#6703]) +1 other test skip
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@xe_eudebug@basic-connect.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@xe_eudebug@basic-connect.html

  * igt@xe_eudebug@basic-vms:
    - shard-bmg:          [SKIP][184] ([Intel XE#6703]) -> [SKIP][185] ([Intel XE#4837])
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@xe_eudebug@basic-vms.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@xe_eudebug@basic-vms.html

  * igt@xe_eudebug_online@interrupt-all:
    - shard-bmg:          [SKIP][186] ([Intel XE#6703]) -> [SKIP][187] ([Intel XE#4837] / [Intel XE#6665])
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@xe_eudebug_online@interrupt-all.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@xe_eudebug_online@interrupt-all.html

  * igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-sram:
    - shard-bmg:          [SKIP][188] ([Intel XE#4837] / [Intel XE#6665]) -> [SKIP][189] ([Intel XE#6703]) +1 other test skip
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-sram.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-sram.html

  * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate-race:
    - shard-bmg:          [SKIP][190] ([Intel XE#2322]) -> [SKIP][191] ([Intel XE#6703])
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate-race.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-dyn-priority:
    - shard-bmg:          [SKIP][192] ([Intel XE#6874]) -> [SKIP][193] ([Intel XE#6703]) +7 other tests skip
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-dyn-priority.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-dyn-priority.html

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-dyn-priority-smem:
    - shard-bmg:          [SKIP][194] ([Intel XE#6703]) -> [SKIP][195] ([Intel XE#6874]) +7 other tests skip
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-dyn-priority-smem.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-dyn-priority-smem.html

  * igt@xe_exec_system_allocator@many-64k-mmap-new-huge:
    - shard-bmg:          [SKIP][196] ([Intel XE#5007]) -> [SKIP][197] ([Intel XE#6703])
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@xe_exec_system_allocator@many-64k-mmap-new-huge.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@xe_exec_system_allocator@many-64k-mmap-new-huge.html

  * igt@xe_exec_system_allocator@process-many-mmap-free-huge:
    - shard-bmg:          [SKIP][198] ([Intel XE#4943]) -> [SKIP][199] ([Intel XE#6703]) +4 other tests skip
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@xe_exec_system_allocator@process-many-mmap-free-huge.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@xe_exec_system_allocator@process-many-mmap-free-huge.html

  * igt@xe_exec_system_allocator@threads-many-large-mmap-huge-nomemset:
    - shard-bmg:          [SKIP][200] ([Intel XE#6703]) -> [SKIP][201] ([Intel XE#4943]) +8 other tests skip
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@xe_exec_system_allocator@threads-many-large-mmap-huge-nomemset.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@xe_exec_system_allocator@threads-many-large-mmap-huge-nomemset.html

  * igt@xe_mmap@small-bar:
    - shard-bmg:          [SKIP][202] ([Intel XE#586]) -> [SKIP][203] ([Intel XE#6703])
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@xe_mmap@small-bar.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@xe_mmap@small-bar.html

  * igt@xe_pm@d3cold-basic-exec:
    - shard-bmg:          [SKIP][204] ([Intel XE#2284]) -> [SKIP][205] ([Intel XE#6703])
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@xe_pm@d3cold-basic-exec.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@xe_pm@d3cold-basic-exec.html

  * igt@xe_query@multigpu-query-hwconfig:
    - shard-bmg:          [SKIP][206] ([Intel XE#944]) -> [SKIP][207] ([Intel XE#6703])
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@xe_query@multigpu-query-hwconfig.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-2/igt@xe_query@multigpu-query-hwconfig.html

  * igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz:
    - shard-bmg:          [SKIP][208] ([Intel XE#6703]) -> [SKIP][209] ([Intel XE#944]) +1 other test skip
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/shard-bmg-8/igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
  [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
  [Intel XE#2374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2374
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2486
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5007
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#5177]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5177
  [Intel XE#5742]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5742
  [Intel XE#5786]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5786
  [Intel XE#586]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/586
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#6251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6251
  [Intel XE#6281]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6281
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6507]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6507
  [Intel XE#6557]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6557
  [Intel XE#6558]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6558
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6693]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6693
  [Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
  [Intel XE#6715]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6715
  [Intel XE#6740]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6740
  [Intel XE#6819]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6819
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da -> xe-pw-139831v9

  IGT_8674: f38f4d8e9c65aff45ac807e646d06e38bc3193a2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da: cab246648fd89efbe8d20ed4c86e7fcebd7606da
  xe-pw-139831v9: 139831v9

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-139831v9/index.html

[-- Attachment #2: Type: text/html, Size: 68270 bytes --]

Re: [PATCH v9 3/8] drm/i915/vrr: Prepare to Use TRANS_PUSH mechanism for PSR frame change

[Nautiyal, Ankit K]

On 12/23/2025 4:21 PM, Jouni Högander wrote:
> On Lunarlake and onwards it is possible to generate PSR "frame change"
> event using TRANS_PUSH mechanism. Implement function to enable this and
> take PSR into account in intel_vrr_send_push.
>
> v6:
>    - add HAS_PSR_FRAME_CHANGE macro
>    - use TRANS_PUSH in instead of TRAN_VRR_CTL
> v5: use intel_psr_use_trans_push for intel_vrr_psr_frame_change_enable
> v4:
>    - use rmw when enabling/disabling transcoder
>    - set TRANS_PUSH_EN conditionally in intel_vrr_send_push
>    - do not call intel_vrr_send_push from intel_psr_trigger_frame_change
>    - do not enable using TRANS_PUSH mechanism for PSR "Frame Change"
> v3:
>    - use rmw when enabling/disabling
>    - keep LNL_TRANS_PUSH_PSR_PR_EN set always on LunarLake and onwards
> v2: use intel_vrr_trans_push_enabled_set_clear instead of rmw
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_crtc.c |  4 +++-
>   drivers/gpu/drm/i915/display/intel_psr.c  | 13 +++++++---
>   drivers/gpu/drm/i915/display/intel_vrr.c  | 29 ++++++++++++++++++-----
>   drivers/gpu/drm/i915/display/intel_vrr.h  |  1 +
>   4 files changed, 37 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 778ebc5095c3..ed3c6c4ce025 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -747,7 +747,9 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
>   	 * which would cause the next frame to terminate already at vmin
>   	 * vblank start instead of vmax vblank start.
>   	 */
> -	if (!state->base.legacy_cursor_update)
> +	if (!state->base.legacy_cursor_update ||
> +	    (intel_psr_use_trans_push(new_crtc_state) &&
> +	     !new_crtc_state->vrr.enable))
>   		intel_vrr_send_push(NULL, new_crtc_state);
>   
>   	local_irq_enable();
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 170d65999ccd..4336ba188aa7 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -207,6 +207,8 @@
>   #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
>   			   (intel_dp)->psr.source_support)
>   
> +#define HAS_PSR_FRAME_CHANGE(display)	(DISPLAY_VER(display) >= 20)
> +
>   bool intel_encoder_can_psr(struct intel_encoder *encoder)
>   {
>   	if (intel_encoder_is_dp(encoder) || encoder->type == INTEL_OUTPUT_DP_MST)
> @@ -2120,6 +2122,9 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>   		intel_dmc_block_pkgc(display, intel_dp->psr.pipe, true);
>   
>   	intel_alpm_configure(intel_dp, crtc_state);
> +
> +	if (intel_psr_use_trans_push(crtc_state))
> +		intel_vrr_psr_frame_change_enable(crtc_state);
>   }
>   
>   static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
> @@ -2511,9 +2516,11 @@ void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
>   		intel_pre_commit_crtc_state(state, crtc);
>   	struct intel_display *display = to_intel_display(crtc);
>   
> -	if (crtc_state->has_psr)
> -		intel_de_write_dsb(display, dsb,
> -				   CURSURFLIVE(display, crtc->pipe), 0);
> +	if (!crtc_state->has_psr || HAS_PSR_FRAME_CHANGE(display))
> +		return;
> +
> +	intel_de_write_dsb(display, dsb,
> +			   CURSURFLIVE(display, crtc->pipe), 0);
>   }
>   
>   /**
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index b92c42fde937..aaf0f6cf3cfe 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -584,16 +584,23 @@ void intel_vrr_send_push(struct intel_dsb *dsb,
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
>   	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 trans_push;
>   
> -	if (!crtc_state->vrr.enable)
> +	if (!crtc_state->vrr.enable && !intel_psr_use_trans_push(crtc_state))
>   		return;
>   
>   	if (dsb)
>   		intel_dsb_nonpost_start(dsb);
>   
> -	intel_de_write_dsb(display, dsb,
> -			   TRANS_PUSH(display, cpu_transcoder),
> -			   TRANS_PUSH_EN | TRANS_PUSH_SEND);
> +	trans_push = TRANS_PUSH_SEND;
> +
> +	if (crtc_state->vrr.enable)
> +		trans_push |= TRANS_PUSH_EN;
> +	if (intel_psr_use_trans_push(crtc_state))
> +		trans_push |= LNL_TRANS_PUSH_PSR_PR_EN;
> +
> +	intel_de_write_dsb(display, dsb, TRANS_PUSH(display, cpu_transcoder),
> +			   trans_push);
>   
>   	if (dsb)
>   		intel_dsb_nonpost_end(dsb);
> @@ -693,7 +700,7 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
>   	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>   	u32 vrr_ctl;
>   
> -	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN);
> +	intel_de_rmw(display, TRANS_PUSH(display, cpu_transcoder), 0, TRANS_PUSH_EN);
>   
>   	vrr_ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
>   
> @@ -721,7 +728,8 @@ static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
>   				       VRR_STATUS_VRR_EN_LIVE, 1000))
>   		drm_err(display->drm, "Timed out waiting for VRR live status to clear\n");
>   
> -	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);
> +	intel_de_rmw(display, TRANS_PUSH(display, cpu_transcoder),
> +		     TRANS_PUSH_EN, 0);
>   }
>   
>   void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
> @@ -737,6 +745,15 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>   		intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);
>   }
>   
> +void intel_vrr_psr_frame_change_enable(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	intel_de_rmw(display, TRANS_PUSH(display, cpu_transcoder), 0,
> +		     LNL_TRANS_PUSH_PSR_PR_EN);
> +}


Can we have a function that tells us what to write in the TRANS_VRR_PUSH 
reg, instead or rmw.

static u32 trans_vrr_push(const struct intel_crtc_state *crtc_state, 
bool send_push)
{
         struct intel_display *display = to_intel_display(crtc_state);
         u32 trans_vrr_push = 0;

         if (intel_vrr_always_use_vrr_tg(display) ||
             crtc_state->vrr.enable)
                 trans_vrr_push |= TRANS_PUSH_EN;

         if (send_push)
                 trans_vrr_push |= TRANS_PUSH_SEND;

         if (intel_psr_use_trans_push(crtc_state))
                 trans_vrr_push |= LNL_TRANS_PUSH_PSR_PR_EN;

         return trans_vrr_push;
}

Then we can just use this in different place.

I think that will make things easier.

We can have first a preparatory patch with changes without the bit 
: LNL_TRANS_PUSH_PSR_PR_EN;

The current patch will then just add the lines to set 
the LNL_TRANS_PUSH_PSR_PR_EN and thats it.


Regards,

Ankit


> +
>   void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(old_crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index bc9044621635..4dc5bb3f6f28 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -30,6 +30,7 @@ void intel_vrr_check_push_sent(struct intel_dsb *dsb,
>   			       const struct intel_crtc_state *crtc_state);
>   bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state);
>   void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state);
> +void intel_vrr_psr_frame_change_enable(const struct intel_crtc_state *crtc_state);
>   void intel_vrr_get_config(struct intel_crtc_state *crtc_state);
>   int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state);
>   int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state);

Re: [PATCH v9 8/8] drm/i915/psr: Use TRANS_PUSH to trigger frame change event

[Nautiyal, Ankit K]

On 12/23/2025 4:21 PM, Jouni Högander wrote:
> Now we have everything in place for triggering PSR "frame change" event
> using TRANS_PUSH: use TRANS_PUSH for LunarLake and onwards.
>
> v3: use HAS_PSR_FRAME_CHANGE macro
> v2: use AND instead of OR in intel_psr_use_trans_push
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_psr.c | 5 +++--
>   1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index ee70d0ceeb5b..353924f8c975 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -4569,6 +4569,7 @@ int intel_psr_min_guardband(struct intel_crtc_state *crtc_state)
>   
>   bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state)
>   {
> -	/* TODO: Enable using trans push when everything is in place */
> -	return false;
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	return HAS_PSR_FRAME_CHANGE(display) && crtc_state->has_psr;


Can we just always enable this bit for LNL+ platforms.

I mean if no PSR/PSR2/Panel Replay are enabled, if we still have this 
bit set, can there be any issue?

The frame change event will be generated but the PSR/PR logic will not 
get activated.


Regards,

Ankit

>   }

Re: [PATCH v9 3/8] drm/i915/vrr: Prepare to Use TRANS_PUSH mechanism for PSR frame change

[Hogander, Jouni]

On Thu, 2026-01-22 at 16:34 +0530, Nautiyal, Ankit K wrote:
> 
> On 12/23/2025 4:21 PM, Jouni Högander wrote:
> > On Lunarlake and onwards it is possible to generate PSR "frame
> > change"
> > event using TRANS_PUSH mechanism. Implement function to enable this
> > and
> > take PSR into account in intel_vrr_send_push.
> > 
> > v6:
> >    - add HAS_PSR_FRAME_CHANGE macro
> >    - use TRANS_PUSH in instead of TRAN_VRR_CTL
> > v5: use intel_psr_use_trans_push for
> > intel_vrr_psr_frame_change_enable
> > v4:
> >    - use rmw when enabling/disabling transcoder
> >    - set TRANS_PUSH_EN conditionally in intel_vrr_send_push
> >    - do not call intel_vrr_send_push from
> > intel_psr_trigger_frame_change
> >    - do not enable using TRANS_PUSH mechanism for PSR "Frame
> > Change"
> > v3:
> >    - use rmw when enabling/disabling
> >    - keep LNL_TRANS_PUSH_PSR_PR_EN set always on LunarLake and
> > onwards
> > v2: use intel_vrr_trans_push_enabled_set_clear instead of rmw
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_crtc.c |  4 +++-
> >   drivers/gpu/drm/i915/display/intel_psr.c  | 13 +++++++---
> >   drivers/gpu/drm/i915/display/intel_vrr.c  | 29
> > ++++++++++++++++++-----
> >   drivers/gpu/drm/i915/display/intel_vrr.h  |  1 +
> >   4 files changed, 37 insertions(+), 10 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> > b/drivers/gpu/drm/i915/display/intel_crtc.c
> > index 778ebc5095c3..ed3c6c4ce025 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > @@ -747,7 +747,9 @@ void intel_pipe_update_end(struct
> > intel_atomic_state *state,
> >   	 * which would cause the next frame to terminate already
> > at vmin
> >   	 * vblank start instead of vmax vblank start.
> >   	 */
> > -	if (!state->base.legacy_cursor_update)
> > +	if (!state->base.legacy_cursor_update ||
> > +	    (intel_psr_use_trans_push(new_crtc_state) &&
> > +	     !new_crtc_state->vrr.enable))
> >   		intel_vrr_send_push(NULL, new_crtc_state);
> >   
> >   	local_irq_enable();
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 170d65999ccd..4336ba188aa7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -207,6 +207,8 @@
> >   #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
> >   			   (intel_dp)->psr.source_support)
> >   
> > +#define HAS_PSR_FRAME_CHANGE(display)	(DISPLAY_VER(display) >=
> > 20)
> > +
> >   bool intel_encoder_can_psr(struct intel_encoder *encoder)
> >   {
> >   	if (intel_encoder_is_dp(encoder) || encoder->type ==
> > INTEL_OUTPUT_DP_MST)
> > @@ -2120,6 +2122,9 @@ static void intel_psr_enable_source(struct
> > intel_dp *intel_dp,
> >   		intel_dmc_block_pkgc(display, intel_dp->psr.pipe,
> > true);
> >   
> >   	intel_alpm_configure(intel_dp, crtc_state);
> > +
> > +	if (intel_psr_use_trans_push(crtc_state))
> > +		intel_vrr_psr_frame_change_enable(crtc_state);
> >   }
> >   
> >   static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
> > @@ -2511,9 +2516,11 @@ void
> > intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
> >   		intel_pre_commit_crtc_state(state, crtc);
> >   	struct intel_display *display = to_intel_display(crtc);
> >   
> > -	if (crtc_state->has_psr)
> > -		intel_de_write_dsb(display, dsb,
> > -				   CURSURFLIVE(display, crtc-
> > >pipe), 0);
> > +	if (!crtc_state->has_psr || HAS_PSR_FRAME_CHANGE(display))
> > +		return;
> > +
> > +	intel_de_write_dsb(display, dsb,
> > +			   CURSURFLIVE(display, crtc->pipe), 0);
> >   }
> >   
> >   /**
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> > b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index b92c42fde937..aaf0f6cf3cfe 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -584,16 +584,23 @@ void intel_vrr_send_push(struct intel_dsb
> > *dsb,
> >   {
> >   	struct intel_display *display =
> > to_intel_display(crtc_state);
> >   	enum transcoder cpu_transcoder = crtc_state-
> > >cpu_transcoder;
> > +	u32 trans_push;
> >   
> > -	if (!crtc_state->vrr.enable)
> > +	if (!crtc_state->vrr.enable &&
> > !intel_psr_use_trans_push(crtc_state))
> >   		return;
> >   
> >   	if (dsb)
> >   		intel_dsb_nonpost_start(dsb);
> >   
> > -	intel_de_write_dsb(display, dsb,
> > -			   TRANS_PUSH(display, cpu_transcoder),
> > -			   TRANS_PUSH_EN | TRANS_PUSH_SEND);
> > +	trans_push = TRANS_PUSH_SEND;
> > +
> > +	if (crtc_state->vrr.enable)
> > +		trans_push |= TRANS_PUSH_EN;
> > +	if (intel_psr_use_trans_push(crtc_state))
> > +		trans_push |= LNL_TRANS_PUSH_PSR_PR_EN;
> > +
> > +	intel_de_write_dsb(display, dsb, TRANS_PUSH(display,
> > cpu_transcoder),
> > +			   trans_push);
> >   
> >   	if (dsb)
> >   		intel_dsb_nonpost_end(dsb);
> > @@ -693,7 +700,7 @@ static void intel_vrr_tg_enable(const struct
> > intel_crtc_state *crtc_state,
> >   	enum transcoder cpu_transcoder = crtc_state-
> > >cpu_transcoder;
> >   	u32 vrr_ctl;
> >   
> > -	intel_de_write(display, TRANS_PUSH(display,
> > cpu_transcoder), TRANS_PUSH_EN);
> > +	intel_de_rmw(display, TRANS_PUSH(display, cpu_transcoder),
> > 0, TRANS_PUSH_EN);
> >   
> >   	vrr_ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
> >   
> > @@ -721,7 +728,8 @@ static void intel_vrr_tg_disable(const struct
> > intel_crtc_state *old_crtc_state)
> >   				       VRR_STATUS_VRR_EN_LIVE,
> > 1000))
> >   		drm_err(display->drm, "Timed out waiting for VRR
> > live status to clear\n");
> >   
> > -	intel_de_write(display, TRANS_PUSH(display,
> > cpu_transcoder), 0);
> > +	intel_de_rmw(display, TRANS_PUSH(display, cpu_transcoder),
> > +		     TRANS_PUSH_EN, 0);
> >   }
> >   
> >   void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
> > @@ -737,6 +745,15 @@ void intel_vrr_enable(const struct
> > intel_crtc_state *crtc_state)
> >   		intel_vrr_tg_enable(crtc_state, crtc_state-
> > >cmrr.enable);
> >   }
> >   
> > +void intel_vrr_psr_frame_change_enable(const struct
> > intel_crtc_state *crtc_state)
> > +{
> > +	struct intel_display *display =
> > to_intel_display(crtc_state);
> > +	enum transcoder cpu_transcoder = crtc_state-
> > >cpu_transcoder;
> > +
> > +	intel_de_rmw(display, TRANS_PUSH(display, cpu_transcoder),
> > 0,
> > +		     LNL_TRANS_PUSH_PSR_PR_EN);
> > +}
> 
> 
> Can we have a function that tells us what to write in the
> TRANS_VRR_PUSH 
> reg, instead or rmw.
> 
> static u32 trans_vrr_push(const struct intel_crtc_state *crtc_state, 
> bool send_push)
> {
>          struct intel_display *display =
> to_intel_display(crtc_state);
>          u32 trans_vrr_push = 0;
> 
>          if (intel_vrr_always_use_vrr_tg(display) ||
>              crtc_state->vrr.enable)
>                  trans_vrr_push |= TRANS_PUSH_EN;
> 
>          if (send_push)
>                  trans_vrr_push |= TRANS_PUSH_SEND;
> 
>          if (intel_psr_use_trans_push(crtc_state))
>                  trans_vrr_push |= LNL_TRANS_PUSH_PSR_PR_EN;
> 
>          return trans_vrr_push;
> }
> 
> Then we can just use this in different place.
> 
> I think that will make things easier.
> 
> We can have first a preparatory patch with changes without the bit 
> : LNL_TRANS_PUSH_PSR_PR_EN;
> 
> The current patch will then just add the lines to set 
> the LNL_TRANS_PUSH_PSR_PR_EN and thats it.

This is good idea. I will try/implement that.

BR,
Jouni Högander

> 
> 
> Regards,
> 
> Ankit
> 
> 
> > +
> >   void intel_vrr_disable(const struct intel_crtc_state
> > *old_crtc_state)
> >   {
> >   	struct intel_display *display =
> > to_intel_display(old_crtc_state);
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h
> > b/drivers/gpu/drm/i915/display/intel_vrr.h
> > index bc9044621635..4dc5bb3f6f28 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> > @@ -30,6 +30,7 @@ void intel_vrr_check_push_sent(struct intel_dsb
> > *dsb,
> >   			       const struct intel_crtc_state
> > *crtc_state);
> >   bool intel_vrr_is_push_sent(const struct intel_crtc_state
> > *crtc_state);
> >   void intel_vrr_disable(const struct intel_crtc_state
> > *old_crtc_state);
> > +void intel_vrr_psr_frame_change_enable(const struct
> > intel_crtc_state *crtc_state);
> >   void intel_vrr_get_config(struct intel_crtc_state *crtc_state);
> >   int intel_vrr_vmax_vtotal(const struct intel_crtc_state
> > *crtc_state);
> >   int intel_vrr_vmin_vtotal(const struct intel_crtc_state
> > *crtc_state);

Re: [PATCH v9 8/8] drm/i915/psr: Use TRANS_PUSH to trigger frame change event

[Hogander, Jouni]

On Thu, 2026-01-22 at 16:34 +0530, Nautiyal, Ankit K wrote:
> 
> On 12/23/2025 4:21 PM, Jouni Högander wrote:
> > Now we have everything in place for triggering PSR "frame change"
> > event
> > using TRANS_PUSH: use TRANS_PUSH for LunarLake and onwards.
> > 
> > v3: use HAS_PSR_FRAME_CHANGE macro
> > v2: use AND instead of OR in intel_psr_use_trans_push
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_psr.c | 5 +++--
> >   1 file changed, 3 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index ee70d0ceeb5b..353924f8c975 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -4569,6 +4569,7 @@ int intel_psr_min_guardband(struct
> > intel_crtc_state *crtc_state)
> >   
> >   bool intel_psr_use_trans_push(const struct intel_crtc_state
> > *crtc_state)
> >   {
> > -	/* TODO: Enable using trans push when everything is in
> > place */
> > -	return false;
> > +	struct intel_display *display =
> > to_intel_display(crtc_state);
> > +
> > +	return HAS_PSR_FRAME_CHANGE(display) && crtc_state-
> > >has_psr;
> 
> 
> Can we just always enable this bit for LNL+ platforms.
> 
> I mean if no PSR/PSR2/Panel Replay are enabled, if we still have this
> bit set, can there be any issue?
> 
> The frame change event will be generated but the PSR/PR logic will
> not 
> get activated.

I think this should be ok. I still need to have this
intel_psr_use_trans_push to have correct sequence in dsb execution.
I'll guess I can use HAS_PSR_FRAME_CHANGE in that trans_vrr_push
discussed on patch 3.

BR,
Jouni Högander

> 
> 
> Regards,
> 
> Ankit
> 
> >   }

Re: [PATCH v9 4/8] drm/i915/dsb: Set DSB_SKIP_WAITS_EN chicken bit for LunarLake and onwards

[Nautiyal, Ankit K]

On 12/23/2025 4:21 PM, Jouni Högander wrote:
> On LunarLake we are using TRANS_PUSH mechanism to trigger "Frame Change"
> event. This way we have more control on when PSR HW is woken up. I.e. not
> every display register write is triggering sending update. This allows us
> setting DSB_SKIP_WAITS_EN chicken bit as well.
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_dsb.c | 15 +++++++++++----
>   1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> index ec2a3fb171ab..19a99f82f413 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -17,6 +17,7 @@
>   #include "intel_dsb.h"
>   #include "intel_dsb_buffer.h"
>   #include "intel_dsb_regs.h"
> +#include "intel_psr.h"
>   #include "intel_vblank.h"
>   #include "intel_vrr.h"
>   #include "skl_watermark.h"
> @@ -166,18 +167,24 @@ static int dsb_scanline_to_hw(struct intel_atomic_state *state,
>    * definitely do not want to skip vblank wait. We also have concern what comes
>    * to skipping vblank evasion. I.e. arming registers are latched before we have
>    * managed writing them. Due to these reasons we are not setting
> - * DSB_SKIP_WAITS_EN.
> + * DSB_SKIP_WAITS_EN except when using TRANS_PUSH mechanism to trigger
> + * "frame change" event.
>    */
>   static u32 dsb_chicken(struct intel_atomic_state *state,
>   		       struct intel_crtc *crtc)
>   {
> +	const struct intel_crtc_state *new_crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	u32 chicken = intel_psr_use_trans_push(new_crtc_state) ?
> +		DSB_SKIP_WAITS_EN : 0;


I have a query regarding Panel Replay. Let's say Panel Replay is enabled.

crtc_state->has_psr will be set for Panel Replay as well so 
DSB_SKIP_WAITS_EN bit gets set.

As per the bspec: "When set, this will enable the DSB to jump from WAIT 
for Vblank, wait for scanline number, in range and out of range states 
to IDLE state when PSR and PSR2 is entered."

When it says "PSR and PSR2 is entered", does this apply to Panel Replay 
as well? Meaning in case of Panel Replay will the wait be skipped?


Regards,

Ankit

> +
>   	if (pre_commit_is_vrr_active(state, crtc))
> -		return DSB_CTRL_WAIT_SAFE_WINDOW |
> +		chicken |= DSB_CTRL_WAIT_SAFE_WINDOW |
>   			DSB_CTRL_NO_WAIT_VBLANK |
>   			DSB_INST_WAIT_SAFE_WINDOW |
>   			DSB_INST_NO_WAIT_VBLANK;
> -	else
> -		return 0;
> +
> +	return chicken;
>   }
>   
>   static bool assert_dsb_has_room(struct intel_dsb *dsb)

Re: [PATCH v9 6/8] drm/i915/psr: Wait for idle only after possible send push

[Nautiyal, Ankit K]

On 12/23/2025 4:21 PM, Jouni Högander wrote:
> We are planning to move using trans push mechanism to trigger the Frame
> Change event. in that case we can't wait PSR to idle before send push
> happens. Due to this move wait for idle to be done after possible send push
> is done.
>
> This should be ok for Frame Change event triggered by register write as
> well. Wait for idle is needed only for corner case where PSR is
> transitioning into DEEP_SLEEP when Frame Change event is triggered. It just
> has to be before wait for vblank. Otherwise we may have vblank before PSR
> enters DEEP_SLEEP and still using old frame buffers for first frame after
> wake up.
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_display.c | 13 ++++++++++---
>   1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index c7ca4f53b8b8..1aca4802b7d5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7333,9 +7333,6 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
>   		intel_psr_trigger_frame_change_event(new_crtc_state->dsb_commit,
>   						     state, crtc);
>   
> -		intel_psr_wait_for_idle_dsb(new_crtc_state->dsb_commit,
> -					    new_crtc_state);
> -
>   		if (new_crtc_state->use_dsb)
>   			intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);
>   
> @@ -7375,6 +7372,16 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
>   
>   		intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
>   
> +		/*
> +		 * Wait for idle is needed for corner case where PSR HW
> +		 * is transitioning into DEEP_SLEEP/SRDENT_OFF when
> +		 * new Frame Change event comes in. It is ok to do it
> +		 * here for both Frame Change mecanisms (trans push
> +		 * and register write).
> +		 */
> +		intel_psr_wait_for_idle_dsb(new_crtc_state->dsb_commit,
> +					    new_crtc_state);
> +

If I understand correctly:

For Fixed RR case:
Suppose we are in PSR:
Skip_wait_en is set.
The portion around the Send Push will be like:


-dsb_wait_vblank will no longer wait for the undelayed vblank (we are in 
PSR and skip_wait_en is set)
-we send push -> to trigger frame change event for PSR HW.

-After this PSR HW is supposed to receive the event and may be in 
transition period so we wait for idle dsb.(which internally makes sure 
that we are out of PSR)

-We are not sure whether we are in active or in vblank region at this 
point of time so we want to use dsb_wait_vblank. The skip_wait_en will 
now not come in picture since we have made sure that we are not in PSR 
in previous step.

Then other steps will be similar to what we have been doing.

Is my understanding correct?

What happens when Panel Replay is in picture, given we can have PR 
enable with Variable Refresh Rate timings.


Regards,

Ankit

>   		/*
>   		 * In case PSR uses trans push as a "frame change" event and
>   		 * VRR is not in use we need to wait vblank. Othervise we may

Re: [PATCH v9 7/8] drm/i915/psr: Do PSR exit on frontbuffer flush on LunarLake and onwards

[Nautiyal, Ankit K]

On 12/23/2025 4:21 PM, Jouni Högander wrote:
> We need to use intel_psr_exit in frontbuffer flush on LunarLake and
> onwardsif we want to move using trans push mechanism to trigger Frame

typo:

s/onwardsif/onwards if/

Patch LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> Change event.
>
> Keep PSR1 and PSR2 HW tracking as it is for older platforms as this was
> seen causing problems there.
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_psr.c | 18 ++++++++++--------
>   1 file changed, 10 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 4336ba188aa7..ee70d0ceeb5b 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -3559,7 +3559,14 @@ static void _psr_flush_handle(struct intel_dp *intel_dp)
>   {
>   	struct intel_display *display = to_intel_display(intel_dp);
>   
> -	if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) {
> +	if (DISPLAY_VER(display) >= 20) {
> +		/*
> +		 * We can use PSR exit on LunarLake onwards. Also
> +		 * using trans push mechanism to trigger Frame Change
> +		 * event requires using PSR exit.
> +		 */
> +		intel_psr_exit(intel_dp);
> +	} else if (intel_dp->psr.psr2_sel_fetch_enabled) {
>   		/* Selective fetch prior LNL */
>   		if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
>   			/* can we turn CFF off? */
> @@ -3579,16 +3586,11 @@ static void _psr_flush_handle(struct intel_dp *intel_dp)
>   		intel_psr_configure_full_frame_update(intel_dp);
>   
>   		intel_psr_force_update(intel_dp);
> -	} else if (!intel_dp->psr.psr2_sel_fetch_enabled) {
> +	} else {
>   		/*
> -		 * PSR1 on all platforms
> -		 * PSR2 HW tracking
> -		 * Panel Replay Full frame update
> +		 * On older platforms using PSR exit was seen causing problems
>   		 */
>   		intel_psr_force_update(intel_dp);
> -	} else {
> -		/* Selective update LNL onwards */
> -		intel_psr_exit(intel_dp);
>   	}
>   
>   	if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)

Re: [PATCH v9 4/8] drm/i915/dsb: Set DSB_SKIP_WAITS_EN chicken bit for LunarLake and onwards

[Hogander, Jouni]

On Fri, 2026-01-23 at 10:11 +0530, Nautiyal, Ankit K wrote:
> 
> On 12/23/2025 4:21 PM, Jouni Högander wrote:
> > On LunarLake we are using TRANS_PUSH mechanism to trigger "Frame
> > Change"
> > event. This way we have more control on when PSR HW is woken up.
> > I.e. not
> > every display register write is triggering sending update. This
> > allows us
> > setting DSB_SKIP_WAITS_EN chicken bit as well.
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_dsb.c | 15 +++++++++++----
> >   1 file changed, 11 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> > b/drivers/gpu/drm/i915/display/intel_dsb.c
> > index ec2a3fb171ab..19a99f82f413 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> > @@ -17,6 +17,7 @@
> >   #include "intel_dsb.h"
> >   #include "intel_dsb_buffer.h"
> >   #include "intel_dsb_regs.h"
> > +#include "intel_psr.h"
> >   #include "intel_vblank.h"
> >   #include "intel_vrr.h"
> >   #include "skl_watermark.h"
> > @@ -166,18 +167,24 @@ static int dsb_scanline_to_hw(struct
> > intel_atomic_state *state,
> >    * definitely do not want to skip vblank wait. We also have
> > concern what comes
> >    * to skipping vblank evasion. I.e. arming registers are latched
> > before we have
> >    * managed writing them. Due to these reasons we are not setting
> > - * DSB_SKIP_WAITS_EN.
> > + * DSB_SKIP_WAITS_EN except when using TRANS_PUSH mechanism to
> > trigger
> > + * "frame change" event.
> >    */
> >   static u32 dsb_chicken(struct intel_atomic_state *state,
> >   		       struct intel_crtc *crtc)
> >   {
> > +	const struct intel_crtc_state *new_crtc_state =
> > +		intel_atomic_get_new_crtc_state(state, crtc);
> > +	u32 chicken = intel_psr_use_trans_push(new_crtc_state) ?
> > +		DSB_SKIP_WAITS_EN : 0;
> 
> 
> I have a query regarding Panel Replay. Let's say Panel Replay is
> enabled.
> 
> crtc_state->has_psr will be set for Panel Replay as well so 
> DSB_SKIP_WAITS_EN bit gets set.
> 
> As per the bspec: "When set, this will enable the DSB to jump from
> WAIT 
> for Vblank, wait for scanline number, in range and out of range
> states 
> to IDLE state when PSR and PSR2 is entered."
> 
> When it says "PSR and PSR2 is entered", does this apply to Panel
> Replay 
> as well? Meaning in case of Panel Replay will the wait be skipped?

Wait will be skipped for PR as we based on my experiments.

BR,

Jouni Högander

> 
> 
> Regards,
> 
> Ankit
> 
> > +
> >   	if (pre_commit_is_vrr_active(state, crtc))
> > -		return DSB_CTRL_WAIT_SAFE_WINDOW |
> > +		chicken |= DSB_CTRL_WAIT_SAFE_WINDOW |
> >   			DSB_CTRL_NO_WAIT_VBLANK |
> >   			DSB_INST_WAIT_SAFE_WINDOW |
> >   			DSB_INST_NO_WAIT_VBLANK;
> > -	else
> > -		return 0;
> > +
> > +	return chicken;
> >   }
> >   
> >   static bool assert_dsb_has_room(struct intel_dsb *dsb)

Re: [PATCH v9 6/8] drm/i915/psr: Wait for idle only after possible send push

[Hogander, Jouni]

On Fri, 2026-01-23 at 10:42 +0530, Nautiyal, Ankit K wrote:
> 
> On 12/23/2025 4:21 PM, Jouni Högander wrote:
> > We are planning to move using trans push mechanism to trigger the
> > Frame
> > Change event. in that case we can't wait PSR to idle before send
> > push
> > happens. Due to this move wait for idle to be done after possible
> > send push
> > is done.
> > 
> > This should be ok for Frame Change event triggered by register
> > write as
> > well. Wait for idle is needed only for corner case where PSR is
> > transitioning into DEEP_SLEEP when Frame Change event is triggered.
> > It just
> > has to be before wait for vblank. Otherwise we may have vblank
> > before PSR
> > enters DEEP_SLEEP and still using old frame buffers for first frame
> > after
> > wake up.
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_display.c | 13 ++++++++++---
> >   1 file changed, 10 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index c7ca4f53b8b8..1aca4802b7d5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -7333,9 +7333,6 @@ static void intel_atomic_dsb_finish(struct
> > intel_atomic_state *state,
> >   		intel_psr_trigger_frame_change_event(new_crtc_stat
> > e->dsb_commit,
> >   						     state, crtc);
> >   
> > -		intel_psr_wait_for_idle_dsb(new_crtc_state-
> > >dsb_commit,
> > -					    new_crtc_state);
> > -
> >   		if (new_crtc_state->use_dsb)
> >   			intel_dsb_vblank_evade(state,
> > new_crtc_state->dsb_commit);
> >   
> > @@ -7375,6 +7372,16 @@ static void intel_atomic_dsb_finish(struct
> > intel_atomic_state *state,
> >   
> >   		intel_vrr_send_push(new_crtc_state->dsb_commit,
> > new_crtc_state);
> >   
> > +		/*
> > +		 * Wait for idle is needed for corner case where
> > PSR HW
> > +		 * is transitioning into DEEP_SLEEP/SRDENT_OFF
> > when
> > +		 * new Frame Change event comes in. It is ok to do
> > it
> > +		 * here for both Frame Change mecanisms (trans
> > push
> > +		 * and register write).
> > +		 */
> > +		intel_psr_wait_for_idle_dsb(new_crtc_state-
> > >dsb_commit,
> > +					    new_crtc_state);
> > +
> 
> If I understand correctly:
> 
> For Fixed RR case:
> Suppose we are in PSR:
> Skip_wait_en is set.
> The portion around the Send Push will be like:
> 
> 
> -dsb_wait_vblank will no longer wait for the undelayed vblank (we are
> in 
> PSR and skip_wait_en is set)
> -we send push -> to trigger frame change event for PSR HW.
> 
> -After this PSR HW is supposed to receive the event and may be in 
> transition period so we wait for idle dsb.(which internally makes
> sure 
> that we are out of PSR)
> 
> -We are not sure whether we are in active or in vblank region at this
> point of time so we want to use dsb_wait_vblank. The skip_wait_en
> will 
> now not come in picture since we have made sure that we are not in
> PSR 
> in previous step.
> 
> Then other steps will be similar to what we have been doing.
> 
> Is my understanding correct?
> 
> What happens when Panel Replay is in picture, given we can have PR 
> enable with Variable Refresh Rate timings.

I don't know how having VRR enabled would impact this sequence? send
push triggers "Frame Change" event -> possible PR active is exited ->
wait for vblank -> wait_for_delayed_vblank -> check push is sent.

Do you have something specific in your mind?

BR,
Jouni Högander

> 
> 
> Regards,
> 
> Ankit
> 
> >   		/*
> >   		 * In case PSR uses trans push as a "frame change"
> > event and
> >   		 * VRR is not in use we need to wait vblank.
> > Othervise we may

Re: [PATCH v9 6/8] drm/i915/psr: Wait for idle only after possible send push

[Nautiyal, Ankit K]

On 1/23/2026 12:07 PM, Hogander, Jouni wrote:
> On Fri, 2026-01-23 at 10:42 +0530, Nautiyal, Ankit K wrote:
>> On 12/23/2025 4:21 PM, Jouni Högander wrote:
>>> We are planning to move using trans push mechanism to trigger the
>>> Frame
>>> Change event. in that case we can't wait PSR to idle before send

Typo: s/in/In


>>> push
>>> happens. Due to this move wait for idle to be done after possible
>>> send push
>>> is done.
>>>
>>> This should be ok for Frame Change event triggered by register
>>> write as
>>> well. Wait for idle is needed only for corner case where PSR is
>>> transitioning into DEEP_SLEEP when Frame Change event is triggered.
>>> It just
>>> has to be before wait for vblank. Otherwise we may have vblank
>>> before PSR
>>> enters DEEP_SLEEP and still using old frame buffers for first frame
>>> after
>>> wake up.
>>>
>>> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/display/intel_display.c | 13 ++++++++++---
>>>    1 file changed, 10 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>>> b/drivers/gpu/drm/i915/display/intel_display.c
>>> index c7ca4f53b8b8..1aca4802b7d5 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>> @@ -7333,9 +7333,6 @@ static void intel_atomic_dsb_finish(struct
>>> intel_atomic_state *state,
>>>    		intel_psr_trigger_frame_change_event(new_crtc_stat
>>> e->dsb_commit,
>>>    						     state, crtc);
>>>    
>>> -		intel_psr_wait_for_idle_dsb(new_crtc_state-
>>>> dsb_commit,
>>> -					    new_crtc_state);
>>> -
>>>    		if (new_crtc_state->use_dsb)
>>>    			intel_dsb_vblank_evade(state,
>>> new_crtc_state->dsb_commit);
>>>    
>>> @@ -7375,6 +7372,16 @@ static void intel_atomic_dsb_finish(struct
>>> intel_atomic_state *state,
>>>    
>>>    		intel_vrr_send_push(new_crtc_state->dsb_commit,
>>> new_crtc_state);
>>>    
>>> +		/*
>>> +		 * Wait for idle is needed for corner case where
>>> PSR HW
>>> +		 * is transitioning into DEEP_SLEEP/SRDENT_OFF
>>> when
>>> +		 * new Frame Change event comes in. It is ok to do
>>> it
>>> +		 * here for both Frame Change mecanisms (trans


s/mecanisms/mechanism


>>> push
>>> +		 * and register write).
>>> +		 */
>>> +		intel_psr_wait_for_idle_dsb(new_crtc_state-
>>>> dsb_commit,
>>> +					    new_crtc_state);
>>> +
>> If I understand correctly:
>>
>> For Fixed RR case:
>> Suppose we are in PSR:
>> Skip_wait_en is set.
>> The portion around the Send Push will be like:
>>
>>
>> -dsb_wait_vblank will no longer wait for the undelayed vblank (we are
>> in
>> PSR and skip_wait_en is set)
>> -we send push -> to trigger frame change event for PSR HW.
>>
>> -After this PSR HW is supposed to receive the event and may be in
>> transition period so we wait for idle dsb.(which internally makes
>> sure
>> that we are out of PSR)
>>
>> -We are not sure whether we are in active or in vblank region at this
>> point of time so we want to use dsb_wait_vblank. The skip_wait_en
>> will
>> now not come in picture since we have made sure that we are not in
>> PSR
>> in previous step.
>>
>> Then other steps will be similar to what we have been doing.
>>
>> Is my understanding correct?
>>
>> What happens when Panel Replay is in picture, given we can have PR
>> enable with Variable Refresh Rate timings.
> I don't know how having VRR enabled would impact this sequence? send
> push triggers "Frame Change" event -> possible PR active is exited ->
> wait for vblank -> wait_for_delayed_vblank -> check push is sent.
>
> Do you have something specific in your mind?


Hmm yes you are right, as you have mentioned with skip_wait_en chicken 
bit will make DSB jump the wait when Panel Replay is enabled.

Lets say we have VRR : ON and Panel Replay enabled.

-dsb_wait_vblank will no longer wait for the undelayed vblank (we are in PR and skip_wait_en is set)

-we send push with send push bit and the frame change bit set.
  This will now happen earlier than the case where Panel Replay was not in picture, perhaps can be in active region.
  This will also result in frame change event for PSR/PR HW.

-we then call intel_psr_wait_for_idle_dsb() that will make sure PR is out from deep sleep state.

-We now wait for undelayed vblank which DSB will not jump because HW is not in Panel Replay active mode.

-Then wait for delayed vblank, and check push sent etc should work as before.

Only thing to check now is DC balance thing done by DMC FW, but I guess since HW is not in Panel Replay active state, it would not expect anything different than the non Panel Replay situation.

In all, theoretically sequence looks alright to me.


There are a few nitpicks in commit message and comment.
Otherwise the patch LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

>
> BR,
> Jouni Högander
>
>>
>> Regards,
>>
>> Ankit
>>
>>>    		/*
>>>    		 * In case PSR uses trans push as a "frame change"
>>> event and
>>>    		 * VRR is not in use we need to wait vblank.
>>> Othervise we may