Re: [PATCH v3 1/1] drm/xe/xe2: Introduce performance changes

["Jahagirdar, Akshata" <akshata.jahagirdar@intel.com>]

On 8/1/2024 2:36 PM, Matt Roper wrote:
> On Fri, Aug 02, 2024 at 02:39:29AM -0700, Akshata Jahagirdar wrote:
>> Add Compression Performance Improvement Changes in Xe2
>>
>> v2: Rebase
>>
>> v3: Rebase, updated as per latest changes on bspec,
>>      Removed unnecessary default actions (Matt)
>>      formatting nits (Tejas)
>>
>> Bspec: 72161
>> Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com>
>> ---
>>   drivers/gpu/drm/xe/regs/xe_gt_regs.h | 4 ++++
>>   drivers/gpu/drm/xe/xe_tuning.c       | 6 ++++++
>>   2 files changed, 10 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> index 3b87f95f9ecf..0d6a73a3c8c7 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> @@ -367,6 +367,10 @@
>>   #define XEHP_L3NODEARBCFG			XE_REG_MCR(0xb0b4)
>>   #define   XEHP_LNESPARE				REG_BIT(19)
>>   
>> +#define L3SQCREG2				XE_REG_MCR(0xb104)
>> +#define   COMPMEMRD256BOVRFETCHEN		REG_BIT(20)
>> +#define	  MEMRD256BOVRFETCHEN			REG_BIT(14)
> Looks like we still have an tab character here where we wanted a space.
Will fix this in next one.
>
>> +
>>   #define L3SQCREG3				XE_REG_MCR(0xb108)
>>   #define   COMPPWOVERFETCHEN			REG_BIT(28)
>>   
>> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
>> index 77d4eec0118d..b41fdb350411 100644
>> --- a/drivers/gpu/drm/xe/xe_tuning.c
>> +++ b/drivers/gpu/drm/xe/xe_tuning.c
>> @@ -45,6 +45,12 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>>   	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
>>   	  XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN))
>>   	},
>> +	{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
>> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
>> +	  XE_RTP_ACTIONS(SET(L3SQCREG2,
>> +	  		     COMPMEMRD256BOVRFETCHEN |
>> +	  		     MEMRD256BOVRFETCHEN))
> Bit 14 = 1 here is also the hardware default, so we don't need to
> specify this one explicitly.
>
>
> Matt
Ah yes, Missed this one. WIll update in next revision.
thank you for your review! :)

Akshata
>> +	},
>>   	{}
>>   };
>>   
>> -- 
>> 2.34.1
>>