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From: "Chauhan, Shekhar" <shekhar.chauhan@intel.com>
To: Akshata Jahagirdar <akshata.jahagirdar@intel.com>,
	<intel-xe@lists.freedesktop.org>
Cc: <tejas.upadhyay@intel.com>
Subject: Re: [PATCH v3 1/1] drm/xe/xe2: Introduce performance changes
Date: Mon, 5 Aug 2024 09:47:15 +0530	[thread overview]
Message-ID: <e194709e-5237-48d8-8dec-7e280992142c@intel.com> (raw)
In-Reply-To: <c2dd753fdc55df6a6432026f2df9c2684a0d25c1.1722607628.git.akshata.jahagirdar@intel.com>


On 8/2/2024 19:42, Akshata Jahagirdar wrote:
> Add Compression Performance Improvement Changes in Xe2
>
> v2: Rebase
>
> v3: Rebase, updated as per latest changes on bspec,
>      Removed unnecessary default actions (Matt)
>      formatting nits (Tejas)
>
> v4: Formatting nits, removed default set action for bit 14 (Matt)
>
> Bspec: 72161
> Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com>
> ---
>   drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 +++
>   drivers/gpu/drm/xe/xe_tuning.c       | 5 +++++
>   2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 3b87f95f9ecf..c50643ab4c84 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -367,6 +367,9 @@
>   #define XEHP_L3NODEARBCFG			XE_REG_MCR(0xb0b4)
>   #define   XEHP_LNESPARE				REG_BIT(19)
>   
> +#define L3SQCREG2				XE_REG_MCR(0xb104)
> +#define   COMPMEMRD256BOVRFETCHEN		REG_BIT(20)
> +
>   #define L3SQCREG3				XE_REG_MCR(0xb108)
>   #define   COMPPWOVERFETCHEN			REG_BIT(28)
>   
> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
> index 77d4eec0118d..3817b7743b0c 100644
> --- a/drivers/gpu/drm/xe/xe_tuning.c
> +++ b/drivers/gpu/drm/xe/xe_tuning.c
> @@ -45,6 +45,11 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>   	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
>   	  XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN))
>   	},
> +	{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
> +	  XE_RTP_ACTIONS(SET(L3SQCREG2,
> +			     COMPMEMRD256BOVRFETCHEN))
Can we merge this into the same line, or any particular reason for 
adding a line break?
> +	},
>   	{}
>   };
>   

-- 
-shekhar


  parent reply	other threads:[~2024-08-05  4:17 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-02 14:12 [PATCH v3 0/1] drm/xe/xe2: Introduce performance changes Akshata Jahagirdar
2024-08-02  2:06 ` ✓ CI.Patch_applied: success for " Patchwork
2024-08-02  2:07 ` ✓ CI.checkpatch: " Patchwork
2024-08-02  2:08 ` ✓ CI.KUnit: " Patchwork
2024-08-02  2:20 ` ✓ CI.Build: " Patchwork
2024-08-02  2:22 ` ✓ CI.Hooks: " Patchwork
2024-08-02  2:23 ` ✓ CI.checksparse: " Patchwork
2024-08-02  2:42 ` ✓ CI.BAT: " Patchwork
2024-08-02  4:48 ` ✗ CI.FULL: failure " Patchwork
2024-08-02 14:12 ` [PATCH v3 1/1] " Akshata Jahagirdar
2024-08-02 21:28   ` Matt Roper
2024-08-02 21:38     ` Matt Roper
2024-08-05  4:17   ` Chauhan, Shekhar [this message]
  -- strict thread matches above, loose matches on Subject: below --
2024-08-02  9:39 [PATCH v3 0/1] " Akshata Jahagirdar
2024-08-02  9:39 ` [PATCH v3 1/1] " Akshata Jahagirdar
2024-08-01 21:36   ` Matt Roper
2024-08-02  1:59     ` Jahagirdar, Akshata

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