[PATCH v3 0/4] PSR/PR Selective Fetch Early Transport fixes

[PATCH v3 0/4] PSR/PR Selective Fetch Early Transport fixes

[Jouni Högander]

This patch set contains fixes for Selective Fetch Early Transport configuration:

  - add necessary DSC Early Transport configuration
  - corner case fix for Selective Update area when Early Transport is
    in use and cursor plane is included into SU are due to alignment.

v3:
  - add WARN_ON_ONCE if vdsc instances per pipe > 2
  - instead of checking vdsc instances per pipe being > 1 check == 2
  - move psr2_su_area under skip_sel_fetch_set_loop label
v2:
  - optimize alignment loop
  - move register definitions to intel_vdsc_regs.h
  - replace patches 3 and 4 with new patches
  - drop patch 5

Jouni Högander (4):
  drm/i915/psr: Repeat Selective Update area alignment
  drm/i915/dsc: Add Selective Update register definitions
  drm/i915/dsc: Add helper for writing DSC Selective Update ET
    parameters
  drm/i915/psr: Write DSC parameters on Selective Update in ET mode

 drivers/gpu/drm/i915/display/intel_psr.c      | 60 +++++++++++++++----
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 23 +++++++
 drivers/gpu/drm/i915/display/intel_vdsc.h     |  3 +
 .../gpu/drm/i915/display/intel_vdsc_regs.h    | 12 ++++
 4 files changed, 86 insertions(+), 12 deletions(-)

-- 
2.43.0

[PATCH v3 1/4] drm/i915/psr: Repeat Selective Update area alignment

[Jouni Högander]

Currently we are aligning Selective Update area to cover cursor fully if
needed only once. It may happen that cursor is in Selective Update area
after pipe alignment and after that covering cursor plane only
partially. Fix this by looping alignment as long as alignment isn't needed
anymore.

v2:
  - do not unecessarily loop if cursor was already fully covered
  - rename aligned as su_area_changed

Fixes: 1bff93b8bc27 ("drm/i915/psr: Extend SU area to cover cursor fully if needed")
Cc: <stable@vger.kernel.org> # v6.9+
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 50 ++++++++++++++++++------
 1 file changed, 38 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 5bea2eda744b..7b197e84e77d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2688,11 +2688,12 @@ static void clip_area_update(struct drm_rect *overlap_damage_area,
 		overlap_damage_area->y2 = damage_area->y2;
 }
 
-static void intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_state)
+static bool intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
 	u16 y_alignment;
+	bool su_area_changed = false;
 
 	/* ADLP aligns the SU region to vdsc slice height in case dsc is enabled */
 	if (crtc_state->dsc.compression_enable &&
@@ -2701,10 +2702,18 @@ static void intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_st
 	else
 		y_alignment = crtc_state->su_y_granularity;
 
-	crtc_state->psr2_su_area.y1 -= crtc_state->psr2_su_area.y1 % y_alignment;
-	if (crtc_state->psr2_su_area.y2 % y_alignment)
+	if (crtc_state->psr2_su_area.y1 % y_alignment) {
+		crtc_state->psr2_su_area.y1 -= crtc_state->psr2_su_area.y1 % y_alignment;
+		su_area_changed = true;
+	}
+
+	if (crtc_state->psr2_su_area.y2 % y_alignment) {
 		crtc_state->psr2_su_area.y2 = ((crtc_state->psr2_su_area.y2 /
 						y_alignment) + 1) * y_alignment;
+		su_area_changed = true;
+	}
+
+	return su_area_changed;
 }
 
 /*
@@ -2838,7 +2847,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 	struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
 	struct intel_plane_state *new_plane_state, *old_plane_state;
 	struct intel_plane *plane;
-	bool full_update = false, cursor_in_su_area = false;
+	bool full_update = false, su_area_changed;
 	int i, ret;
 
 	if (!crtc_state->enable_psr2_sel_fetch)
@@ -2945,15 +2954,32 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 	if (ret)
 		return ret;
 
-	/*
-	 * Adjust su area to cover cursor fully as necessary (early
-	 * transport). This needs to be done after
-	 * drm_atomic_add_affected_planes to ensure visible cursor is added into
-	 * affected planes even when cursor is not updated by itself.
-	 */
-	intel_psr2_sel_fetch_et_alignment(state, crtc, &cursor_in_su_area);
+	do {
+		bool cursor_in_su_area;
 
-	intel_psr2_sel_fetch_pipe_alignment(crtc_state);
+		/*
+		 * Adjust su area to cover cursor fully as necessary
+		 * (early transport). This needs to be done after
+		 * drm_atomic_add_affected_planes to ensure visible
+		 * cursor is added into affected planes even when
+		 * cursor is not updated by itself.
+		 */
+		intel_psr2_sel_fetch_et_alignment(state, crtc, &cursor_in_su_area);
+
+		su_area_changed = intel_psr2_sel_fetch_pipe_alignment(crtc_state);
+
+		/*
+		 * If the cursor was outside the SU area before
+		 * alignment, the alignment step (which only expands
+		 * SU) may pull the cursor partially inside, so we
+		 * must run ET alignment again to fully cover it. But
+		 * if the cursor was already fully inside before
+		 * alignment, expanding the SU area won't change that,
+		 * so no further work is needed.
+		 */
+		if (cursor_in_su_area)
+			break;
+	} while (su_area_changed);
 
 	/*
 	 * Now that we have the pipe damaged area check if it intersect with
-- 
2.43.0

[PATCH v3 2/4] drm/i915/dsc: Add Selective Update register definitions

[Jouni Högander]

Add definitions for DSC_SU_PARAMETER_SET_0_DSC0 and
DSC_SU_PARAMETER_SET_0_DSC1 registers. These are for Selective Update Early
Transport configuration.

Bspec: 71709
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
index 2d478a84b07c..2b2e3c1b8138 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -196,6 +196,18 @@
 #define   DSC_PPS18_NSL_BPG_OFFSET(offset)	REG_FIELD_PREP(DSC_PPS18_NSL_BPG_OFFSET_MASK, offset)
 #define   DSC_PPS18_SL_OFFSET_ADJ(offset)	REG_FIELD_PREP(DSC_PPS18_SL_OFFSET_ADJ_MASK, offset)
 
+#define _LNL_DSC0_SU_PARAMETER_SET_0_PA		0x78064
+#define _LNL_DSC1_SU_PARAMETER_SET_0_PA		0x78164
+#define _LNL_DSC0_SU_PARAMETER_SET_0_PB		0x78264
+#define _LNL_DSC1_SU_PARAMETER_SET_0_PB		0x78364
+#define LNL_DSC0_SU_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe), _LNL_DSC0_SU_PARAMETER_SET_0_PA, _LNL_DSC0_SU_PARAMETER_SET_0_PB)
+#define LNL_DSC1_SU_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe), _LNL_DSC1_SU_PARAMETER_SET_0_PA, _LNL_DSC1_SU_PARAMETER_SET_0_PB)
+
+#define   DSC_SUPS0_SU_SLICE_ROW_PER_FRAME_MASK		REG_GENMASK(31, 20)
+#define   DSC_SUPS0_SU_SLICE_ROW_PER_FRAME(rows)	REG_FIELD_PREP(DSC_SUPS0_SU_SLICE_ROW_PER_FRAME_MASK, (rows))
+#define   DSC_SUPS0_SU_PIC_HEIGHT_MASK			REG_GENMASK(15, 0)
+#define   DSC_SUPS0_SU_PIC_HEIGHT(h)			REG_FIELD_PREP(DSC_SUPS0_SU_PIC_HEIGHT_MASK, (h))
+
 /* Icelake Rate Control Buffer Threshold Registers */
 #define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)
 #define DSCA_RC_BUF_THRESH_0_UDW		_MMIO(0x6B230 + 4)
-- 
2.43.0

[PATCH v3 3/4] drm/i915/dsc: Add helper for writing DSC Selective Update ET parameters

[Jouni Högander]

There are slice row per frame and pic height configuration in DSC Selective
Update Parameter Set 1 register. Add helper for configuring these.

v2:
  - Add WARN_ON_ONCE if vdsc instances per pipe > 2
  - instead of checking vdsc instances per pipe being > 1 check == 2

Bspec: 71709
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 23 +++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vdsc.h |  3 +++
 2 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 7e53201b3cb1..6c09c6d99ffe 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -820,6 +820,29 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
 				  sizeof(dp_dsc_pps_sdp));
 }
 
+void intel_dsc_su_et_parameters_configure(struct intel_dsb *dsb, struct intel_encoder *encoder,
+					  const struct intel_crtc_state *crtc_state, int su_lines)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
+	enum pipe pipe = crtc->pipe;
+	int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
+	int slice_row_per_frame = su_lines / vdsc_cfg->slice_height;
+	u32 val;
+
+	drm_WARN_ON_ONCE(display->drm, su_lines % vdsc_cfg->slice_height);
+	drm_WARN_ON_ONCE(display->drm, vdsc_instances_per_pipe > 2);
+
+	val = DSC_SUPS0_SU_SLICE_ROW_PER_FRAME(slice_row_per_frame);
+	val |= DSC_SUPS0_SU_PIC_HEIGHT(su_lines);
+
+	intel_de_write_dsb(display, dsb, LNL_DSC0_SU_PARAMETER_SET_0(pipe), val);
+
+	if (vdsc_instances_per_pipe == 2)
+		intel_de_write_dsb(display, dsb, LNL_DSC1_SU_PARAMETER_SET_0(pipe), val);
+}
+
 static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
 {
 	return is_pipe_dsc(crtc, cpu_transcoder) ?
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index f4d5b37293cf..3372f8694054 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -14,6 +14,7 @@ enum transcoder;
 struct intel_crtc;
 struct intel_crtc_state;
 struct intel_display;
+struct intel_dsb;
 struct intel_dsc_slice_config;
 struct intel_encoder;
 
@@ -37,6 +38,8 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
 			     const struct intel_crtc_state *crtc_state);
 void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
 			    const struct intel_crtc_state *crtc_state);
+void intel_dsc_su_et_parameters_configure(struct intel_dsb *dsb, struct intel_encoder *encoder,
+					  const struct intel_crtc_state *crtc_state, int su_lines);
 void intel_vdsc_state_dump(struct drm_printer *p, int indent,
 			   const struct intel_crtc_state *crtc_state);
 int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state);
-- 
2.43.0

[PATCH v3 4/4] drm/i915/psr: Write DSC parameters on Selective Update in ET mode

[Jouni Högander]

There are slice row per frame and pic height parameters in DSC that needs
to be configured on every Selective Update in Early Transport mode. Use
helper provided by DSC code to configure these on Selective Update when in
Early Transport mode. Also fill crtc_state->psr2_su_area with full frame
area on full frame update for DSC calculation.

v2: move psr2_su_area under skip_sel_fetch_set_loop label

Bspec: 68927, 71709
Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as possible")
Cc: <stable@vger.kernel.org> # v6.9+
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 7b197e84e77d..cb3df2611515 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2618,6 +2618,12 @@ void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb,
 
 	intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
 			   crtc_state->pipe_srcsz_early_tpt);
+
+	if (!crtc_state->dsc.compression_enable)
+		return;
+
+	intel_dsc_su_et_parameters_configure(dsb, encoder, crtc_state,
+					     drm_rect_height(&crtc_state->psr2_su_area));
 }
 
 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
@@ -3039,6 +3045,10 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 	}
 
 skip_sel_fetch_set_loop:
+	if (full_update)
+		clip_area_update(&crtc_state->psr2_su_area, &crtc_state->pipe_src,
+				 &crtc_state->pipe_src);
+
 	psr2_man_trk_ctl_calc(crtc_state, full_update);
 	crtc_state->pipe_srcsz_early_tpt =
 		psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update);
-- 
2.43.0

Re: [PATCH v3 3/4] drm/i915/dsc: Add helper for writing DSC Selective Update ET parameters

[Nautiyal, Ankit K]

On 3/4/2026 5:00 PM, Jouni Högander wrote:
> There are slice row per frame and pic height configuration in DSC Selective
> Update Parameter Set 1 register. Add helper for configuring these.
>
> v2:
>    - Add WARN_ON_ONCE if vdsc instances per pipe > 2
>    - instead of checking vdsc instances per pipe being > 1 check == 2
>
> Bspec: 71709
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_vdsc.c | 23 +++++++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_vdsc.h |  3 +++
>   2 files changed, 26 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 7e53201b3cb1..6c09c6d99ffe 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -820,6 +820,29 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
>   				  sizeof(dp_dsc_pps_sdp));
>   }
>   
> +void intel_dsc_su_et_parameters_configure(struct intel_dsb *dsb, struct intel_encoder *encoder,
> +					  const struct intel_crtc_state *crtc_state, int su_lines)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> +	enum pipe pipe = crtc->pipe;
> +	int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
> +	int slice_row_per_frame = su_lines / vdsc_cfg->slice_height;
> +	u32 val;
> +
> +	drm_WARN_ON_ONCE(display->drm, su_lines % vdsc_cfg->slice_height);
> +	drm_WARN_ON_ONCE(display->drm, vdsc_instances_per_pipe > 2);
> +
> +	val = DSC_SUPS0_SU_SLICE_ROW_PER_FRAME(slice_row_per_frame);
> +	val |= DSC_SUPS0_SU_PIC_HEIGHT(su_lines);
> +
> +	intel_de_write_dsb(display, dsb, LNL_DSC0_SU_PARAMETER_SET_0(pipe), val);
> +
> +	if (vdsc_instances_per_pipe == 2)
> +		intel_de_write_dsb(display, dsb, LNL_DSC1_SU_PARAMETER_SET_0(pipe), val);
> +}
> +
>   static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
>   {
>   	return is_pipe_dsc(crtc, cpu_transcoder) ?
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
> index f4d5b37293cf..3372f8694054 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> @@ -14,6 +14,7 @@ enum transcoder;
>   struct intel_crtc;
>   struct intel_crtc_state;
>   struct intel_display;
> +struct intel_dsb;
>   struct intel_dsc_slice_config;
>   struct intel_encoder;
>   
> @@ -37,6 +38,8 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
>   			     const struct intel_crtc_state *crtc_state);
>   void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
>   			    const struct intel_crtc_state *crtc_state);
> +void intel_dsc_su_et_parameters_configure(struct intel_dsb *dsb, struct intel_encoder *encoder,
> +					  const struct intel_crtc_state *crtc_state, int su_lines);
>   void intel_vdsc_state_dump(struct drm_printer *p, int indent,
>   			   const struct intel_crtc_state *crtc_state);
>   int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state);

Re: [PATCH v3 4/4] drm/i915/psr: Write DSC parameters on Selective Update in ET mode

[Nautiyal, Ankit K]

On 3/4/2026 5:00 PM, Jouni Högander wrote:
> There are slice row per frame and pic height parameters in DSC that needs
> to be configured on every Selective Update in Early Transport mode. Use
> helper provided by DSC code to configure these on Selective Update when in
> Early Transport mode. Also fill crtc_state->psr2_su_area with full frame
> area on full frame update for DSC calculation.
>
> v2: move psr2_su_area under skip_sel_fetch_set_loop label
>
> Bspec: 68927, 71709
> Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as possible")
> Cc: <stable@vger.kernel.org> # v6.9+
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

Makes sense to, make the su area full at the end, if full_frame update 
is needed.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

> ---
>   drivers/gpu/drm/i915/display/intel_psr.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 7b197e84e77d..cb3df2611515 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2618,6 +2618,12 @@ void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb,
>   
>   	intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
>   			   crtc_state->pipe_srcsz_early_tpt);
> +
> +	if (!crtc_state->dsc.compression_enable)
> +		return;
> +
> +	intel_dsc_su_et_parameters_configure(dsb, encoder, crtc_state,
> +					     drm_rect_height(&crtc_state->psr2_su_area));
>   }
>   
>   static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
> @@ -3039,6 +3045,10 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>   	}
>   
>   skip_sel_fetch_set_loop:
> +	if (full_update)
> +		clip_area_update(&crtc_state->psr2_su_area, &crtc_state->pipe_src,
> +				 &crtc_state->pipe_src);
> +
>   	psr2_man_trk_ctl_calc(crtc_state, full_update);
>   	crtc_state->pipe_srcsz_early_tpt =
>   		psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update);

✗ CI.checkpatch: warning for PSR/PR Selective Fetch Early Transport fixes (rev3)

[Patchwork]

== Series Details ==

Series: PSR/PR Selective Fetch Early Transport fixes (rev3)
URL   : https://patchwork.freedesktop.org/series/161835/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 7e89092c8d497a030e60fb4b0a5bd4dced222466
Author: Jouni Högander <jouni.hogander@intel.com>
Date:   Wed Mar 4 13:30:11 2026 +0200

    drm/i915/psr: Write DSC parameters on Selective Update in ET mode
    
    There are slice row per frame and pic height parameters in DSC that needs
    to be configured on every Selective Update in Early Transport mode. Use
    helper provided by DSC code to configure these on Selective Update when in
    Early Transport mode. Also fill crtc_state->psr2_su_area with full frame
    area on full frame update for DSC calculation.
    
    v2: move psr2_su_area under skip_sel_fetch_set_loop label
    
    Bspec: 68927, 71709
    Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as possible")
    Cc: <stable@vger.kernel.org> # v6.9+
    Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
    Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
+ /mt/dim checkpatch 704ff20b65b8a8037c10332bad4ecabbfeab7cdc drm-intel
18e2bdffb067 drm/i915/psr: Repeat Selective Update area alignment
72d284d1e33b drm/i915/dsc: Add Selective Update register definitions
-:29: WARNING:LONG_LINE: line length of 132 exceeds 100 columns
#29: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:203:
+#define LNL_DSC0_SU_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe), _LNL_DSC0_SU_PARAMETER_SET_0_PA, _LNL_DSC0_SU_PARAMETER_SET_0_PB)

-:30: WARNING:LONG_LINE: line length of 132 exceeds 100 columns
#30: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:204:
+#define LNL_DSC1_SU_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe), _LNL_DSC1_SU_PARAMETER_SET_0_PA, _LNL_DSC1_SU_PARAMETER_SET_0_PB)

-:33: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#33: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:207:
+#define   DSC_SUPS0_SU_SLICE_ROW_PER_FRAME(rows)	REG_FIELD_PREP(DSC_SUPS0_SU_SLICE_ROW_PER_FRAME_MASK, (rows))

-:35: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#35: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:209:
+#define   DSC_SUPS0_SU_PIC_HEIGHT(h)			REG_FIELD_PREP(DSC_SUPS0_SU_PIC_HEIGHT_MASK, (h))

total: 0 errors, 4 warnings, 0 checks, 18 lines checked
2fb13c2d1a9c drm/i915/dsc: Add helper for writing DSC Selective Update ET parameters
7e89092c8d49 drm/i915/psr: Write DSC parameters on Selective Update in ET mode

✓ CI.KUnit: success for PSR/PR Selective Fetch Early Transport fixes (rev3)

[Patchwork]

== Series Details ==

Series: PSR/PR Selective Fetch Early Transport fixes (rev3)
URL   : https://patchwork.freedesktop.org/series/161835/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[10:27:54] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:27:59] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[10:28:36] Starting KUnit Kernel (1/1)...
[10:28:36] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:28:36] ================== guc_buf (11 subtests) ===================
[10:28:36] [PASSED] test_smallest
[10:28:36] [PASSED] test_largest
[10:28:36] [PASSED] test_granular
[10:28:36] [PASSED] test_unique
[10:28:36] [PASSED] test_overlap
[10:28:36] [PASSED] test_reusable
[10:28:36] [PASSED] test_too_big
[10:28:36] [PASSED] test_flush
[10:28:36] [PASSED] test_lookup
[10:28:36] [PASSED] test_data
[10:28:36] [PASSED] test_class
[10:28:36] ===================== [PASSED] guc_buf =====================
[10:28:36] =================== guc_dbm (7 subtests) ===================
[10:28:36] [PASSED] test_empty
[10:28:36] [PASSED] test_default
[10:28:36] ======================== test_size  ========================
[10:28:36] [PASSED] 4
[10:28:36] [PASSED] 8
[10:28:36] [PASSED] 32
[10:28:36] [PASSED] 256
[10:28:36] ==================== [PASSED] test_size ====================
[10:28:36] ======================= test_reuse  ========================
[10:28:36] [PASSED] 4
[10:28:36] [PASSED] 8
[10:28:36] [PASSED] 32
[10:28:36] [PASSED] 256
[10:28:36] =================== [PASSED] test_reuse ====================
[10:28:36] =================== test_range_overlap  ====================
[10:28:36] [PASSED] 4
[10:28:36] [PASSED] 8
[10:28:36] [PASSED] 32
[10:28:36] [PASSED] 256
[10:28:36] =============== [PASSED] test_range_overlap ================
[10:28:36] =================== test_range_compact  ====================
[10:28:36] [PASSED] 4
[10:28:36] [PASSED] 8
[10:28:36] [PASSED] 32
[10:28:36] [PASSED] 256
[10:28:36] =============== [PASSED] test_range_compact ================
[10:28:36] ==================== test_range_spare  =====================
[10:28:36] [PASSED] 4
[10:28:36] [PASSED] 8
[10:28:36] [PASSED] 32
[10:28:36] [PASSED] 256
[10:28:36] ================ [PASSED] test_range_spare =================
[10:28:36] ===================== [PASSED] guc_dbm =====================
[10:28:36] =================== guc_idm (6 subtests) ===================
[10:28:36] [PASSED] bad_init
[10:28:36] [PASSED] no_init
[10:28:36] [PASSED] init_fini
[10:28:36] [PASSED] check_used
[10:28:36] [PASSED] check_quota
[10:28:36] [PASSED] check_all
[10:28:36] ===================== [PASSED] guc_idm =====================
[10:28:36] ================== no_relay (3 subtests) ===================
[10:28:36] [PASSED] xe_drops_guc2pf_if_not_ready
[10:28:36] [PASSED] xe_drops_guc2vf_if_not_ready
[10:28:36] [PASSED] xe_rejects_send_if_not_ready
[10:28:36] ==================== [PASSED] no_relay =====================
[10:28:36] ================== pf_relay (14 subtests) ==================
[10:28:36] [PASSED] pf_rejects_guc2pf_too_short
[10:28:36] [PASSED] pf_rejects_guc2pf_too_long
[10:28:36] [PASSED] pf_rejects_guc2pf_no_payload
[10:28:36] [PASSED] pf_fails_no_payload
[10:28:36] [PASSED] pf_fails_bad_origin
[10:28:36] [PASSED] pf_fails_bad_type
[10:28:36] [PASSED] pf_txn_reports_error
[10:28:36] [PASSED] pf_txn_sends_pf2guc
[10:28:36] [PASSED] pf_sends_pf2guc
[10:28:36] [SKIPPED] pf_loopback_nop
[10:28:36] [SKIPPED] pf_loopback_echo
[10:28:36] [SKIPPED] pf_loopback_fail
[10:28:36] [SKIPPED] pf_loopback_busy
[10:28:36] [SKIPPED] pf_loopback_retry
[10:28:36] ==================== [PASSED] pf_relay =====================
[10:28:36] ================== vf_relay (3 subtests) ===================
[10:28:36] [PASSED] vf_rejects_guc2vf_too_short
[10:28:36] [PASSED] vf_rejects_guc2vf_too_long
[10:28:36] [PASSED] vf_rejects_guc2vf_no_payload
[10:28:36] ==================== [PASSED] vf_relay =====================
[10:28:36] ================ pf_gt_config (9 subtests) =================
[10:28:36] [PASSED] fair_contexts_1vf
[10:28:36] [PASSED] fair_doorbells_1vf
[10:28:36] [PASSED] fair_ggtt_1vf
[10:28:36] ====================== fair_vram_1vf  ======================
[10:28:36] [PASSED] 3.50 GiB
[10:28:36] [PASSED] 11.5 GiB
[10:28:36] [PASSED] 15.5 GiB
[10:28:36] [PASSED] 31.5 GiB
[10:28:36] [PASSED] 63.5 GiB
[10:28:36] [PASSED] 1.91 GiB
[10:28:36] ================== [PASSED] fair_vram_1vf ==================
[10:28:36] ================ fair_vram_1vf_admin_only  =================
[10:28:36] [PASSED] 3.50 GiB
[10:28:36] [PASSED] 11.5 GiB
[10:28:36] [PASSED] 15.5 GiB
[10:28:36] [PASSED] 31.5 GiB
[10:28:36] [PASSED] 63.5 GiB
[10:28:36] [PASSED] 1.91 GiB
[10:28:36] ============ [PASSED] fair_vram_1vf_admin_only =============
[10:28:36] ====================== fair_contexts  ======================
[10:28:36] [PASSED] 1 VF
[10:28:36] [PASSED] 2 VFs
[10:28:36] [PASSED] 3 VFs
[10:28:36] [PASSED] 4 VFs
[10:28:36] [PASSED] 5 VFs
[10:28:36] [PASSED] 6 VFs
[10:28:36] [PASSED] 7 VFs
[10:28:36] [PASSED] 8 VFs
[10:28:36] [PASSED] 9 VFs
[10:28:36] [PASSED] 10 VFs
[10:28:36] [PASSED] 11 VFs
[10:28:36] [PASSED] 12 VFs
[10:28:36] [PASSED] 13 VFs
[10:28:36] [PASSED] 14 VFs
[10:28:36] [PASSED] 15 VFs
[10:28:36] [PASSED] 16 VFs
[10:28:36] [PASSED] 17 VFs
[10:28:36] [PASSED] 18 VFs
[10:28:36] [PASSED] 19 VFs
[10:28:36] [PASSED] 20 VFs
[10:28:36] [PASSED] 21 VFs
[10:28:36] [PASSED] 22 VFs
[10:28:36] [PASSED] 23 VFs
[10:28:36] [PASSED] 24 VFs
[10:28:36] [PASSED] 25 VFs
[10:28:36] [PASSED] 26 VFs
[10:28:36] [PASSED] 27 VFs
[10:28:36] [PASSED] 28 VFs
[10:28:36] [PASSED] 29 VFs
[10:28:36] [PASSED] 30 VFs
[10:28:36] [PASSED] 31 VFs
[10:28:36] [PASSED] 32 VFs
[10:28:36] [PASSED] 33 VFs
[10:28:36] [PASSED] 34 VFs
[10:28:36] [PASSED] 35 VFs
[10:28:36] [PASSED] 36 VFs
[10:28:36] [PASSED] 37 VFs
[10:28:36] [PASSED] 38 VFs
[10:28:36] [PASSED] 39 VFs
[10:28:36] [PASSED] 40 VFs
[10:28:36] [PASSED] 41 VFs
[10:28:36] [PASSED] 42 VFs
[10:28:36] [PASSED] 43 VFs
[10:28:36] [PASSED] 44 VFs
[10:28:36] [PASSED] 45 VFs
[10:28:36] [PASSED] 46 VFs
[10:28:36] [PASSED] 47 VFs
[10:28:36] [PASSED] 48 VFs
[10:28:36] [PASSED] 49 VFs
[10:28:36] [PASSED] 50 VFs
[10:28:36] [PASSED] 51 VFs
[10:28:36] [PASSED] 52 VFs
[10:28:36] [PASSED] 53 VFs
[10:28:36] [PASSED] 54 VFs
[10:28:36] [PASSED] 55 VFs
[10:28:36] [PASSED] 56 VFs
[10:28:36] [PASSED] 57 VFs
[10:28:36] [PASSED] 58 VFs
[10:28:36] [PASSED] 59 VFs
[10:28:36] [PASSED] 60 VFs
[10:28:36] [PASSED] 61 VFs
[10:28:36] [PASSED] 62 VFs
[10:28:36] [PASSED] 63 VFs
[10:28:36] ================== [PASSED] fair_contexts ==================
[10:28:36] ===================== fair_doorbells  ======================
[10:28:36] [PASSED] 1 VF
[10:28:36] [PASSED] 2 VFs
[10:28:36] [PASSED] 3 VFs
[10:28:36] [PASSED] 4 VFs
[10:28:36] [PASSED] 5 VFs
[10:28:36] [PASSED] 6 VFs
[10:28:36] [PASSED] 7 VFs
[10:28:36] [PASSED] 8 VFs
[10:28:36] [PASSED] 9 VFs
[10:28:36] [PASSED] 10 VFs
[10:28:36] [PASSED] 11 VFs
[10:28:36] [PASSED] 12 VFs
[10:28:36] [PASSED] 13 VFs
[10:28:36] [PASSED] 14 VFs
[10:28:36] [PASSED] 15 VFs
[10:28:36] [PASSED] 16 VFs
[10:28:36] [PASSED] 17 VFs
[10:28:36] [PASSED] 18 VFs
[10:28:36] [PASSED] 19 VFs
[10:28:36] [PASSED] 20 VFs
[10:28:36] [PASSED] 21 VFs
[10:28:36] [PASSED] 22 VFs
[10:28:36] [PASSED] 23 VFs
[10:28:36] [PASSED] 24 VFs
[10:28:36] [PASSED] 25 VFs
[10:28:36] [PASSED] 26 VFs
[10:28:36] [PASSED] 27 VFs
[10:28:36] [PASSED] 28 VFs
[10:28:36] [PASSED] 29 VFs
[10:28:36] [PASSED] 30 VFs
[10:28:36] [PASSED] 31 VFs
[10:28:36] [PASSED] 32 VFs
[10:28:36] [PASSED] 33 VFs
[10:28:36] [PASSED] 34 VFs
[10:28:36] [PASSED] 35 VFs
[10:28:36] [PASSED] 36 VFs
[10:28:36] [PASSED] 37 VFs
[10:28:36] [PASSED] 38 VFs
[10:28:36] [PASSED] 39 VFs
[10:28:36] [PASSED] 40 VFs
[10:28:36] [PASSED] 41 VFs
[10:28:36] [PASSED] 42 VFs
[10:28:36] [PASSED] 43 VFs
[10:28:36] [PASSED] 44 VFs
[10:28:36] [PASSED] 45 VFs
[10:28:36] [PASSED] 46 VFs
[10:28:36] [PASSED] 47 VFs
[10:28:36] [PASSED] 48 VFs
[10:28:36] [PASSED] 49 VFs
[10:28:36] [PASSED] 50 VFs
[10:28:36] [PASSED] 51 VFs
[10:28:36] [PASSED] 52 VFs
[10:28:36] [PASSED] 53 VFs
[10:28:36] [PASSED] 54 VFs
[10:28:36] [PASSED] 55 VFs
[10:28:36] [PASSED] 56 VFs
[10:28:36] [PASSED] 57 VFs
[10:28:36] [PASSED] 58 VFs
[10:28:36] [PASSED] 59 VFs
[10:28:36] [PASSED] 60 VFs
[10:28:36] [PASSED] 61 VFs
[10:28:36] [PASSED] 62 VFs
[10:28:36] [PASSED] 63 VFs
[10:28:36] ================= [PASSED] fair_doorbells ==================
[10:28:36] ======================== fair_ggtt  ========================
[10:28:36] [PASSED] 1 VF
[10:28:36] [PASSED] 2 VFs
[10:28:36] [PASSED] 3 VFs
[10:28:36] [PASSED] 4 VFs
[10:28:36] [PASSED] 5 VFs
[10:28:36] [PASSED] 6 VFs
[10:28:36] [PASSED] 7 VFs
[10:28:36] [PASSED] 8 VFs
[10:28:36] [PASSED] 9 VFs
[10:28:36] [PASSED] 10 VFs
[10:28:36] [PASSED] 11 VFs
[10:28:36] [PASSED] 12 VFs
[10:28:36] [PASSED] 13 VFs
[10:28:36] [PASSED] 14 VFs
[10:28:36] [PASSED] 15 VFs
[10:28:36] [PASSED] 16 VFs
[10:28:36] [PASSED] 17 VFs
[10:28:36] [PASSED] 18 VFs
[10:28:36] [PASSED] 19 VFs
[10:28:36] [PASSED] 20 VFs
[10:28:36] [PASSED] 21 VFs
[10:28:36] [PASSED] 22 VFs
[10:28:36] [PASSED] 23 VFs
[10:28:36] [PASSED] 24 VFs
[10:28:36] [PASSED] 25 VFs
[10:28:36] [PASSED] 26 VFs
[10:28:36] [PASSED] 27 VFs
[10:28:36] [PASSED] 28 VFs
[10:28:36] [PASSED] 29 VFs
[10:28:36] [PASSED] 30 VFs
[10:28:36] [PASSED] 31 VFs
[10:28:36] [PASSED] 32 VFs
[10:28:36] [PASSED] 33 VFs
[10:28:36] [PASSED] 34 VFs
[10:28:36] [PASSED] 35 VFs
[10:28:36] [PASSED] 36 VFs
[10:28:36] [PASSED] 37 VFs
[10:28:36] [PASSED] 38 VFs
[10:28:36] [PASSED] 39 VFs
[10:28:36] [PASSED] 40 VFs
[10:28:36] [PASSED] 41 VFs
[10:28:36] [PASSED] 42 VFs
[10:28:36] [PASSED] 43 VFs
[10:28:36] [PASSED] 44 VFs
[10:28:36] [PASSED] 45 VFs
[10:28:36] [PASSED] 46 VFs
[10:28:36] [PASSED] 47 VFs
[10:28:36] [PASSED] 48 VFs
[10:28:36] [PASSED] 49 VFs
[10:28:36] [PASSED] 50 VFs
[10:28:36] [PASSED] 51 VFs
[10:28:36] [PASSED] 52 VFs
[10:28:36] [PASSED] 53 VFs
[10:28:36] [PASSED] 54 VFs
[10:28:36] [PASSED] 55 VFs
[10:28:36] [PASSED] 56 VFs
[10:28:36] [PASSED] 57 VFs
[10:28:36] [PASSED] 58 VFs
[10:28:36] [PASSED] 59 VFs
[10:28:36] [PASSED] 60 VFs
[10:28:36] [PASSED] 61 VFs
[10:28:36] [PASSED] 62 VFs
[10:28:36] [PASSED] 63 VFs
[10:28:36] ==================== [PASSED] fair_ggtt ====================
[10:28:36] ======================== fair_vram  ========================
[10:28:36] [PASSED] 1 VF
[10:28:36] [PASSED] 2 VFs
[10:28:36] [PASSED] 3 VFs
[10:28:36] [PASSED] 4 VFs
[10:28:36] [PASSED] 5 VFs
[10:28:36] [PASSED] 6 VFs
[10:28:36] [PASSED] 7 VFs
[10:28:36] [PASSED] 8 VFs
[10:28:36] [PASSED] 9 VFs
[10:28:36] [PASSED] 10 VFs
[10:28:36] [PASSED] 11 VFs
[10:28:36] [PASSED] 12 VFs
[10:28:36] [PASSED] 13 VFs
[10:28:36] [PASSED] 14 VFs
[10:28:36] [PASSED] 15 VFs
[10:28:36] [PASSED] 16 VFs
[10:28:36] [PASSED] 17 VFs
[10:28:36] [PASSED] 18 VFs
[10:28:36] [PASSED] 19 VFs
[10:28:36] [PASSED] 20 VFs
[10:28:36] [PASSED] 21 VFs
[10:28:36] [PASSED] 22 VFs
[10:28:36] [PASSED] 23 VFs
[10:28:36] [PASSED] 24 VFs
[10:28:36] [PASSED] 25 VFs
[10:28:36] [PASSED] 26 VFs
[10:28:36] [PASSED] 27 VFs
[10:28:36] [PASSED] 28 VFs
[10:28:36] [PASSED] 29 VFs
[10:28:37] [PASSED] 30 VFs
[10:28:37] [PASSED] 31 VFs
[10:28:37] [PASSED] 32 VFs
[10:28:37] [PASSED] 33 VFs
[10:28:37] [PASSED] 34 VFs
[10:28:37] [PASSED] 35 VFs
[10:28:37] [PASSED] 36 VFs
[10:28:37] [PASSED] 37 VFs
[10:28:37] [PASSED] 38 VFs
[10:28:37] [PASSED] 39 VFs
[10:28:37] [PASSED] 40 VFs
[10:28:37] [PASSED] 41 VFs
[10:28:37] [PASSED] 42 VFs
[10:28:37] [PASSED] 43 VFs
[10:28:37] [PASSED] 44 VFs
[10:28:37] [PASSED] 45 VFs
[10:28:37] [PASSED] 46 VFs
[10:28:37] [PASSED] 47 VFs
[10:28:37] [PASSED] 48 VFs
[10:28:37] [PASSED] 49 VFs
[10:28:37] [PASSED] 50 VFs
[10:28:37] [PASSED] 51 VFs
[10:28:37] [PASSED] 52 VFs
[10:28:37] [PASSED] 53 VFs
[10:28:37] [PASSED] 54 VFs
[10:28:37] [PASSED] 55 VFs
[10:28:37] [PASSED] 56 VFs
[10:28:37] [PASSED] 57 VFs
[10:28:37] [PASSED] 58 VFs
[10:28:37] [PASSED] 59 VFs
[10:28:37] [PASSED] 60 VFs
[10:28:37] [PASSED] 61 VFs
[10:28:37] [PASSED] 62 VFs
[10:28:37] [PASSED] 63 VFs
[10:28:37] ==================== [PASSED] fair_vram ====================
[10:28:37] ================== [PASSED] pf_gt_config ===================
[10:28:37] ===================== lmtt (1 subtest) =====================
[10:28:37] ======================== test_ops  =========================
[10:28:37] [PASSED] 2-level
[10:28:37] [PASSED] multi-level
[10:28:37] ==================== [PASSED] test_ops =====================
[10:28:37] ====================== [PASSED] lmtt =======================
[10:28:37] ================= pf_service (11 subtests) =================
[10:28:37] [PASSED] pf_negotiate_any
[10:28:37] [PASSED] pf_negotiate_base_match
[10:28:37] [PASSED] pf_negotiate_base_newer
[10:28:37] [PASSED] pf_negotiate_base_next
[10:28:37] [SKIPPED] pf_negotiate_base_older
[10:28:37] [PASSED] pf_negotiate_base_prev
[10:28:37] [PASSED] pf_negotiate_latest_match
[10:28:37] [PASSED] pf_negotiate_latest_newer
[10:28:37] [PASSED] pf_negotiate_latest_next
[10:28:37] [SKIPPED] pf_negotiate_latest_older
[10:28:37] [SKIPPED] pf_negotiate_latest_prev
[10:28:37] =================== [PASSED] pf_service ====================
[10:28:37] ================= xe_guc_g2g (2 subtests) ==================
[10:28:37] ============== xe_live_guc_g2g_kunit_default  ==============
[10:28:37] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[10:28:37] ============== xe_live_guc_g2g_kunit_allmem  ===============
[10:28:37] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[10:28:37] =================== [SKIPPED] xe_guc_g2g ===================
[10:28:37] =================== xe_mocs (2 subtests) ===================
[10:28:37] ================ xe_live_mocs_kernel_kunit  ================
[10:28:37] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[10:28:37] ================ xe_live_mocs_reset_kunit  =================
[10:28:37] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[10:28:37] ==================== [SKIPPED] xe_mocs =====================
[10:28:37] ================= xe_migrate (2 subtests) ==================
[10:28:37] ================= xe_migrate_sanity_kunit  =================
[10:28:37] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[10:28:37] ================== xe_validate_ccs_kunit  ==================
[10:28:37] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[10:28:37] =================== [SKIPPED] xe_migrate ===================
[10:28:37] ================== xe_dma_buf (1 subtest) ==================
[10:28:37] ==================== xe_dma_buf_kunit  =====================
[10:28:37] ================ [SKIPPED] xe_dma_buf_kunit ================
[10:28:37] =================== [SKIPPED] xe_dma_buf ===================
[10:28:37] ================= xe_bo_shrink (1 subtest) =================
[10:28:37] =================== xe_bo_shrink_kunit  ====================
[10:28:37] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[10:28:37] ================== [SKIPPED] xe_bo_shrink ==================
[10:28:37] ==================== xe_bo (2 subtests) ====================
[10:28:37] ================== xe_ccs_migrate_kunit  ===================
[10:28:37] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[10:28:37] ==================== xe_bo_evict_kunit  ====================
[10:28:37] =============== [SKIPPED] xe_bo_evict_kunit ================
[10:28:37] ===================== [SKIPPED] xe_bo ======================
[10:28:37] ==================== args (13 subtests) ====================
[10:28:37] [PASSED] count_args_test
[10:28:37] [PASSED] call_args_example
[10:28:37] [PASSED] call_args_test
[10:28:37] [PASSED] drop_first_arg_example
[10:28:37] [PASSED] drop_first_arg_test
[10:28:37] [PASSED] first_arg_example
[10:28:37] [PASSED] first_arg_test
[10:28:37] [PASSED] last_arg_example
[10:28:37] [PASSED] last_arg_test
[10:28:37] [PASSED] pick_arg_example
[10:28:37] [PASSED] if_args_example
[10:28:37] [PASSED] if_args_test
[10:28:37] [PASSED] sep_comma_example
[10:28:37] ====================== [PASSED] args =======================
[10:28:37] =================== xe_pci (3 subtests) ====================
[10:28:37] ==================== check_graphics_ip  ====================
[10:28:37] [PASSED] 12.00 Xe_LP
[10:28:37] [PASSED] 12.10 Xe_LP+
[10:28:37] [PASSED] 12.55 Xe_HPG
[10:28:37] [PASSED] 12.60 Xe_HPC
[10:28:37] [PASSED] 12.70 Xe_LPG
[10:28:37] [PASSED] 12.71 Xe_LPG
[10:28:37] [PASSED] 12.74 Xe_LPG+
[10:28:37] [PASSED] 20.01 Xe2_HPG
[10:28:37] [PASSED] 20.02 Xe2_HPG
[10:28:37] [PASSED] 20.04 Xe2_LPG
[10:28:37] [PASSED] 30.00 Xe3_LPG
[10:28:37] [PASSED] 30.01 Xe3_LPG
[10:28:37] [PASSED] 30.03 Xe3_LPG
[10:28:37] [PASSED] 30.04 Xe3_LPG
[10:28:37] [PASSED] 30.05 Xe3_LPG
[10:28:37] [PASSED] 35.10 Xe3p_LPG
[10:28:37] [PASSED] 35.11 Xe3p_XPC
[10:28:37] ================ [PASSED] check_graphics_ip ================
[10:28:37] ===================== check_media_ip  ======================
[10:28:37] [PASSED] 12.00 Xe_M
[10:28:37] [PASSED] 12.55 Xe_HPM
[10:28:37] [PASSED] 13.00 Xe_LPM+
[10:28:37] [PASSED] 13.01 Xe2_HPM
[10:28:37] [PASSED] 20.00 Xe2_LPM
[10:28:37] [PASSED] 30.00 Xe3_LPM
[10:28:37] [PASSED] 30.02 Xe3_LPM
[10:28:37] [PASSED] 35.00 Xe3p_LPM
[10:28:37] [PASSED] 35.03 Xe3p_HPM
[10:28:37] ================= [PASSED] check_media_ip ==================
[10:28:37] =================== check_platform_desc  ===================
[10:28:37] [PASSED] 0x9A60 (TIGERLAKE)
[10:28:37] [PASSED] 0x9A68 (TIGERLAKE)
[10:28:37] [PASSED] 0x9A70 (TIGERLAKE)
[10:28:37] [PASSED] 0x9A40 (TIGERLAKE)
[10:28:37] [PASSED] 0x9A49 (TIGERLAKE)
[10:28:37] [PASSED] 0x9A59 (TIGERLAKE)
[10:28:37] [PASSED] 0x9A78 (TIGERLAKE)
[10:28:37] [PASSED] 0x9AC0 (TIGERLAKE)
[10:28:37] [PASSED] 0x9AC9 (TIGERLAKE)
[10:28:37] [PASSED] 0x9AD9 (TIGERLAKE)
[10:28:37] [PASSED] 0x9AF8 (TIGERLAKE)
[10:28:37] [PASSED] 0x4C80 (ROCKETLAKE)
[10:28:37] [PASSED] 0x4C8A (ROCKETLAKE)
[10:28:37] [PASSED] 0x4C8B (ROCKETLAKE)
[10:28:37] [PASSED] 0x4C8C (ROCKETLAKE)
[10:28:37] [PASSED] 0x4C90 (ROCKETLAKE)
[10:28:37] [PASSED] 0x4C9A (ROCKETLAKE)
[10:28:37] [PASSED] 0x4680 (ALDERLAKE_S)
[10:28:37] [PASSED] 0x4682 (ALDERLAKE_S)
[10:28:37] [PASSED] 0x4688 (ALDERLAKE_S)
[10:28:37] [PASSED] 0x468A (ALDERLAKE_S)
[10:28:37] [PASSED] 0x468B (ALDERLAKE_S)
[10:28:37] [PASSED] 0x4690 (ALDERLAKE_S)
[10:28:37] [PASSED] 0x4692 (ALDERLAKE_S)
[10:28:37] [PASSED] 0x4693 (ALDERLAKE_S)
[10:28:37] [PASSED] 0x46A0 (ALDERLAKE_P)
[10:28:37] [PASSED] 0x46A1 (ALDERLAKE_P)
[10:28:37] [PASSED] 0x46A2 (ALDERLAKE_P)
[10:28:37] [PASSED] 0x46A3 (ALDERLAKE_P)
[10:28:37] [PASSED] 0x46A6 (ALDERLAKE_P)
[10:28:37] [PASSED] 0x46A8 (ALDERLAKE_P)
[10:28:37] [PASSED] 0x46AA (ALDERLAKE_P)
[10:28:37] [PASSED] 0x462A (ALDERLAKE_P)
[10:28:37] [PASSED] 0x4626 (ALDERLAKE_P)
[10:28:37] [PASSED] 0x4628 (ALDERLAKE_P)
[10:28:37] [PASSED] 0x46B0 (ALDERLAKE_P)
[10:28:37] [PASSED] 0x46B1 (ALDERLAKE_P)
[10:28:37] [PASSED] 0x46B2 (ALDERLAKE_P)
[10:28:37] [PASSED] 0x46B3 (ALDERLAKE_P)
[10:28:37] [PASSED] 0x46C0 (ALDERLAKE_P)
[10:28:37] [PASSED] 0x46C1 (ALDERLAKE_P)
[10:28:37] [PASSED] 0x46C2 (ALDERLAKE_P)
[10:28:37] [PASSED] 0x46C3 (ALDERLAKE_P)
[10:28:37] [PASSED] 0x46D0 (ALDERLAKE_N)
[10:28:37] [PASSED] 0x46D1 (ALDERLAKE_N)
[10:28:37] [PASSED] 0x46D2 (ALDERLAKE_N)
[10:28:37] [PASSED] 0x46D3 (ALDERLAKE_N)
[10:28:37] [PASSED] 0x46D4 (ALDERLAKE_N)
[10:28:37] [PASSED] 0xA721 (ALDERLAKE_P)
[10:28:37] [PASSED] 0xA7A1 (ALDERLAKE_P)
[10:28:37] [PASSED] 0xA7A9 (ALDERLAKE_P)
[10:28:37] [PASSED] 0xA7AC (ALDERLAKE_P)
[10:28:37] [PASSED] 0xA7AD (ALDERLAKE_P)
[10:28:37] [PASSED] 0xA720 (ALDERLAKE_P)
[10:28:37] [PASSED] 0xA7A0 (ALDERLAKE_P)
[10:28:37] [PASSED] 0xA7A8 (ALDERLAKE_P)
[10:28:37] [PASSED] 0xA7AA (ALDERLAKE_P)
[10:28:37] [PASSED] 0xA7AB (ALDERLAKE_P)
[10:28:37] [PASSED] 0xA780 (ALDERLAKE_S)
[10:28:37] [PASSED] 0xA781 (ALDERLAKE_S)
[10:28:37] [PASSED] 0xA782 (ALDERLAKE_S)
[10:28:37] [PASSED] 0xA783 (ALDERLAKE_S)
[10:28:37] [PASSED] 0xA788 (ALDERLAKE_S)
[10:28:37] [PASSED] 0xA789 (ALDERLAKE_S)
[10:28:37] [PASSED] 0xA78A (ALDERLAKE_S)
[10:28:37] [PASSED] 0xA78B (ALDERLAKE_S)
[10:28:37] [PASSED] 0x4905 (DG1)
[10:28:37] [PASSED] 0x4906 (DG1)
[10:28:37] [PASSED] 0x4907 (DG1)
[10:28:37] [PASSED] 0x4908 (DG1)
[10:28:37] [PASSED] 0x4909 (DG1)
[10:28:37] [PASSED] 0x56C0 (DG2)
[10:28:37] [PASSED] 0x56C2 (DG2)
[10:28:37] [PASSED] 0x56C1 (DG2)
[10:28:37] [PASSED] 0x7D51 (METEORLAKE)
[10:28:37] [PASSED] 0x7DD1 (METEORLAKE)
[10:28:37] [PASSED] 0x7D41 (METEORLAKE)
[10:28:37] [PASSED] 0x7D67 (METEORLAKE)
[10:28:37] [PASSED] 0xB640 (METEORLAKE)
[10:28:37] [PASSED] 0x56A0 (DG2)
[10:28:37] [PASSED] 0x56A1 (DG2)
[10:28:37] [PASSED] 0x56A2 (DG2)
[10:28:37] [PASSED] 0x56BE (DG2)
[10:28:37] [PASSED] 0x56BF (DG2)
[10:28:37] [PASSED] 0x5690 (DG2)
[10:28:37] [PASSED] 0x5691 (DG2)
[10:28:37] [PASSED] 0x5692 (DG2)
[10:28:37] [PASSED] 0x56A5 (DG2)
[10:28:37] [PASSED] 0x56A6 (DG2)
[10:28:37] [PASSED] 0x56B0 (DG2)
[10:28:37] [PASSED] 0x56B1 (DG2)
[10:28:37] [PASSED] 0x56BA (DG2)
[10:28:37] [PASSED] 0x56BB (DG2)
[10:28:37] [PASSED] 0x56BC (DG2)
[10:28:37] [PASSED] 0x56BD (DG2)
[10:28:37] [PASSED] 0x5693 (DG2)
[10:28:37] [PASSED] 0x5694 (DG2)
[10:28:37] [PASSED] 0x5695 (DG2)
[10:28:37] [PASSED] 0x56A3 (DG2)
[10:28:37] [PASSED] 0x56A4 (DG2)
[10:28:37] [PASSED] 0x56B2 (DG2)
[10:28:37] [PASSED] 0x56B3 (DG2)
[10:28:37] [PASSED] 0x5696 (DG2)
[10:28:37] [PASSED] 0x5697 (DG2)
[10:28:37] [PASSED] 0xB69 (PVC)
[10:28:37] [PASSED] 0xB6E (PVC)
[10:28:37] [PASSED] 0xBD4 (PVC)
[10:28:37] [PASSED] 0xBD5 (PVC)
[10:28:37] [PASSED] 0xBD6 (PVC)
[10:28:37] [PASSED] 0xBD7 (PVC)
[10:28:37] [PASSED] 0xBD8 (PVC)
[10:28:37] [PASSED] 0xBD9 (PVC)
[10:28:37] [PASSED] 0xBDA (PVC)
[10:28:37] [PASSED] 0xBDB (PVC)
[10:28:37] [PASSED] 0xBE0 (PVC)
[10:28:37] [PASSED] 0xBE1 (PVC)
[10:28:37] [PASSED] 0xBE5 (PVC)
[10:28:37] [PASSED] 0x7D40 (METEORLAKE)
[10:28:37] [PASSED] 0x7D45 (METEORLAKE)
[10:28:37] [PASSED] 0x7D55 (METEORLAKE)
[10:28:37] [PASSED] 0x7D60 (METEORLAKE)
[10:28:37] [PASSED] 0x7DD5 (METEORLAKE)
[10:28:37] [PASSED] 0x6420 (LUNARLAKE)
[10:28:37] [PASSED] 0x64A0 (LUNARLAKE)
[10:28:37] [PASSED] 0x64B0 (LUNARLAKE)
[10:28:37] [PASSED] 0xE202 (BATTLEMAGE)
[10:28:37] [PASSED] 0xE209 (BATTLEMAGE)
[10:28:37] [PASSED] 0xE20B (BATTLEMAGE)
[10:28:37] [PASSED] 0xE20C (BATTLEMAGE)
[10:28:37] [PASSED] 0xE20D (BATTLEMAGE)
[10:28:37] [PASSED] 0xE210 (BATTLEMAGE)
[10:28:37] [PASSED] 0xE211 (BATTLEMAGE)
[10:28:37] [PASSED] 0xE212 (BATTLEMAGE)
[10:28:37] [PASSED] 0xE216 (BATTLEMAGE)
[10:28:37] [PASSED] 0xE220 (BATTLEMAGE)
[10:28:37] [PASSED] 0xE221 (BATTLEMAGE)
[10:28:37] [PASSED] 0xE222 (BATTLEMAGE)
[10:28:37] [PASSED] 0xE223 (BATTLEMAGE)
[10:28:37] [PASSED] 0xB080 (PANTHERLAKE)
[10:28:37] [PASSED] 0xB081 (PANTHERLAKE)
[10:28:37] [PASSED] 0xB082 (PANTHERLAKE)
[10:28:37] [PASSED] 0xB083 (PANTHERLAKE)
[10:28:37] [PASSED] 0xB084 (PANTHERLAKE)
[10:28:37] [PASSED] 0xB085 (PANTHERLAKE)
[10:28:37] [PASSED] 0xB086 (PANTHERLAKE)
[10:28:37] [PASSED] 0xB087 (PANTHERLAKE)
[10:28:37] [PASSED] 0xB08F (PANTHERLAKE)
[10:28:37] [PASSED] 0xB090 (PANTHERLAKE)
[10:28:37] [PASSED] 0xB0A0 (PANTHERLAKE)
[10:28:37] [PASSED] 0xB0B0 (PANTHERLAKE)
[10:28:37] [PASSED] 0xFD80 (PANTHERLAKE)
[10:28:37] [PASSED] 0xFD81 (PANTHERLAKE)
[10:28:37] [PASSED] 0xD740 (NOVALAKE_S)
[10:28:37] [PASSED] 0xD741 (NOVALAKE_S)
[10:28:37] [PASSED] 0xD742 (NOVALAKE_S)
[10:28:37] [PASSED] 0xD743 (NOVALAKE_S)
[10:28:37] [PASSED] 0xD744 (NOVALAKE_S)
[10:28:37] [PASSED] 0xD745 (NOVALAKE_S)
[10:28:37] [PASSED] 0x674C (CRESCENTISLAND)
[10:28:37] [PASSED] 0xD750 (NOVALAKE_P)
[10:28:37] [PASSED] 0xD751 (NOVALAKE_P)
[10:28:37] [PASSED] 0xD752 (NOVALAKE_P)
[10:28:37] [PASSED] 0xD753 (NOVALAKE_P)
[10:28:37] [PASSED] 0xD754 (NOVALAKE_P)
[10:28:37] [PASSED] 0xD755 (NOVALAKE_P)
[10:28:37] [PASSED] 0xD756 (NOVALAKE_P)
[10:28:37] [PASSED] 0xD757 (NOVALAKE_P)
[10:28:37] [PASSED] 0xD75F (NOVALAKE_P)
[10:28:37] =============== [PASSED] check_platform_desc ===============
[10:28:37] ===================== [PASSED] xe_pci ======================
[10:28:37] =================== xe_rtp (2 subtests) ====================
[10:28:37] =============== xe_rtp_process_to_sr_tests  ================
[10:28:37] [PASSED] coalesce-same-reg
[10:28:37] [PASSED] no-match-no-add
[10:28:37] [PASSED] match-or
[10:28:37] [PASSED] match-or-xfail
[10:28:37] [PASSED] no-match-no-add-multiple-rules
[10:28:37] [PASSED] two-regs-two-entries
[10:28:37] [PASSED] clr-one-set-other
[10:28:37] [PASSED] set-field
[10:28:37] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[10:28:37] [PASSED] conflict-not-disjoint
[10:28:37] [PASSED] conflict-reg-type
[10:28:37] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[10:28:37] ================== xe_rtp_process_tests  ===================
[10:28:37] [PASSED] active1
[10:28:37] [PASSED] active2
[10:28:37] [PASSED] active-inactive
[10:28:37] [PASSED] inactive-active
[10:28:37] [PASSED] inactive-1st_or_active-inactive
[10:28:37] [PASSED] inactive-2nd_or_active-inactive
[10:28:37] [PASSED] inactive-last_or_active-inactive
[10:28:37] [PASSED] inactive-no_or_active-inactive
[10:28:37] ============== [PASSED] xe_rtp_process_tests ===============
[10:28:37] ===================== [PASSED] xe_rtp ======================
[10:28:37] ==================== xe_wa (1 subtest) =====================
[10:28:37] ======================== xe_wa_gt  =========================
[10:28:37] [PASSED] TIGERLAKE B0
[10:28:37] [PASSED] DG1 A0
[10:28:37] [PASSED] DG1 B0
[10:28:37] [PASSED] ALDERLAKE_S A0
[10:28:37] [PASSED] ALDERLAKE_S B0
[10:28:37] [PASSED] ALDERLAKE_S C0
[10:28:37] [PASSED] ALDERLAKE_S D0
[10:28:37] [PASSED] ALDERLAKE_P A0
[10:28:37] [PASSED] ALDERLAKE_P B0
[10:28:37] [PASSED] ALDERLAKE_P C0
[10:28:37] [PASSED] ALDERLAKE_S RPLS D0
[10:28:37] [PASSED] ALDERLAKE_P RPLU E0
[10:28:37] [PASSED] DG2 G10 C0
[10:28:37] [PASSED] DG2 G11 B1
[10:28:37] [PASSED] DG2 G12 A1
[10:28:37] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:28:37] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:28:37] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[10:28:37] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[10:28:37] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[10:28:37] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[10:28:37] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[10:28:37] ==================== [PASSED] xe_wa_gt =====================
[10:28:37] ====================== [PASSED] xe_wa ======================
[10:28:37] ============================================================
[10:28:37] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[10:28:37] Elapsed time: 42.560s total, 4.615s configuring, 37.277s building, 0.622s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[10:28:37] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:28:38] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[10:29:07] Starting KUnit Kernel (1/1)...
[10:29:07] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:29:07] ============ drm_test_pick_cmdline (2 subtests) ============
[10:29:07] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[10:29:07] =============== drm_test_pick_cmdline_named  ===============
[10:29:07] [PASSED] NTSC
[10:29:07] [PASSED] NTSC-J
[10:29:07] [PASSED] PAL
[10:29:07] [PASSED] PAL-M
[10:29:07] =========== [PASSED] drm_test_pick_cmdline_named ===========
[10:29:07] ============== [PASSED] drm_test_pick_cmdline ==============
[10:29:07] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[10:29:07] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[10:29:07] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[10:29:07] =========== drm_validate_clone_mode (2 subtests) ===========
[10:29:07] ============== drm_test_check_in_clone_mode  ===============
[10:29:07] [PASSED] in_clone_mode
[10:29:07] [PASSED] not_in_clone_mode
[10:29:07] ========== [PASSED] drm_test_check_in_clone_mode ===========
[10:29:07] =============== drm_test_check_valid_clones  ===============
[10:29:07] [PASSED] not_in_clone_mode
[10:29:07] [PASSED] valid_clone
[10:29:07] [PASSED] invalid_clone
[10:29:07] =========== [PASSED] drm_test_check_valid_clones ===========
[10:29:07] ============= [PASSED] drm_validate_clone_mode =============
[10:29:07] ============= drm_validate_modeset (1 subtest) =============
[10:29:07] [PASSED] drm_test_check_connector_changed_modeset
[10:29:07] ============== [PASSED] drm_validate_modeset ===============
[10:29:07] ====== drm_test_bridge_get_current_state (2 subtests) ======
[10:29:07] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[10:29:07] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[10:29:07] ======== [PASSED] drm_test_bridge_get_current_state ========
[10:29:07] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[10:29:07] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[10:29:07] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[10:29:07] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[10:29:07] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[10:29:07] ============== drm_bridge_alloc (2 subtests) ===============
[10:29:07] [PASSED] drm_test_drm_bridge_alloc_basic
[10:29:07] [PASSED] drm_test_drm_bridge_alloc_get_put
[10:29:07] ================ [PASSED] drm_bridge_alloc =================
[10:29:07] ============= drm_cmdline_parser (40 subtests) =============
[10:29:07] [PASSED] drm_test_cmdline_force_d_only
[10:29:07] [PASSED] drm_test_cmdline_force_D_only_dvi
[10:29:07] [PASSED] drm_test_cmdline_force_D_only_hdmi
[10:29:07] [PASSED] drm_test_cmdline_force_D_only_not_digital
[10:29:07] [PASSED] drm_test_cmdline_force_e_only
[10:29:07] [PASSED] drm_test_cmdline_res
[10:29:07] [PASSED] drm_test_cmdline_res_vesa
[10:29:07] [PASSED] drm_test_cmdline_res_vesa_rblank
[10:29:07] [PASSED] drm_test_cmdline_res_rblank
[10:29:07] [PASSED] drm_test_cmdline_res_bpp
[10:29:07] [PASSED] drm_test_cmdline_res_refresh
[10:29:07] [PASSED] drm_test_cmdline_res_bpp_refresh
[10:29:07] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[10:29:07] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[10:29:07] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[10:29:07] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[10:29:07] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[10:29:07] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[10:29:07] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[10:29:07] [PASSED] drm_test_cmdline_res_margins_force_on
[10:29:07] [PASSED] drm_test_cmdline_res_vesa_margins
[10:29:07] [PASSED] drm_test_cmdline_name
[10:29:07] [PASSED] drm_test_cmdline_name_bpp
[10:29:07] [PASSED] drm_test_cmdline_name_option
[10:29:07] [PASSED] drm_test_cmdline_name_bpp_option
[10:29:07] [PASSED] drm_test_cmdline_rotate_0
[10:29:07] [PASSED] drm_test_cmdline_rotate_90
[10:29:07] [PASSED] drm_test_cmdline_rotate_180
[10:29:07] [PASSED] drm_test_cmdline_rotate_270
[10:29:07] [PASSED] drm_test_cmdline_hmirror
[10:29:07] [PASSED] drm_test_cmdline_vmirror
[10:29:07] [PASSED] drm_test_cmdline_margin_options
[10:29:07] [PASSED] drm_test_cmdline_multiple_options
[10:29:07] [PASSED] drm_test_cmdline_bpp_extra_and_option
[10:29:07] [PASSED] drm_test_cmdline_extra_and_option
[10:29:07] [PASSED] drm_test_cmdline_freestanding_options
[10:29:07] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[10:29:07] [PASSED] drm_test_cmdline_panel_orientation
[10:29:07] ================ drm_test_cmdline_invalid  =================
[10:29:07] [PASSED] margin_only
[10:29:07] [PASSED] interlace_only
[10:29:07] [PASSED] res_missing_x
[10:29:07] [PASSED] res_missing_y
[10:29:07] [PASSED] res_bad_y
[10:29:07] [PASSED] res_missing_y_bpp
[10:29:07] [PASSED] res_bad_bpp
[10:29:07] [PASSED] res_bad_refresh
[10:29:07] [PASSED] res_bpp_refresh_force_on_off
[10:29:07] [PASSED] res_invalid_mode
[10:29:07] [PASSED] res_bpp_wrong_place_mode
[10:29:07] [PASSED] name_bpp_refresh
[10:29:07] [PASSED] name_refresh
[10:29:07] [PASSED] name_refresh_wrong_mode
[10:29:07] [PASSED] name_refresh_invalid_mode
[10:29:07] [PASSED] rotate_multiple
[10:29:07] [PASSED] rotate_invalid_val
[10:29:07] [PASSED] rotate_truncated
[10:29:07] [PASSED] invalid_option
[10:29:07] [PASSED] invalid_tv_option
[10:29:07] [PASSED] truncated_tv_option
[10:29:07] ============ [PASSED] drm_test_cmdline_invalid =============
[10:29:07] =============== drm_test_cmdline_tv_options  ===============
[10:29:07] [PASSED] NTSC
[10:29:07] [PASSED] NTSC_443
[10:29:07] [PASSED] NTSC_J
[10:29:07] [PASSED] PAL
[10:29:07] [PASSED] PAL_M
[10:29:07] [PASSED] PAL_N
[10:29:07] [PASSED] SECAM
[10:29:07] [PASSED] MONO_525
[10:29:07] [PASSED] MONO_625
[10:29:07] =========== [PASSED] drm_test_cmdline_tv_options ===========
[10:29:07] =============== [PASSED] drm_cmdline_parser ================
[10:29:07] ========== drmm_connector_hdmi_init (20 subtests) ==========
[10:29:07] [PASSED] drm_test_connector_hdmi_init_valid
[10:29:07] [PASSED] drm_test_connector_hdmi_init_bpc_8
[10:29:07] [PASSED] drm_test_connector_hdmi_init_bpc_10
[10:29:07] [PASSED] drm_test_connector_hdmi_init_bpc_12
[10:29:07] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[10:29:07] [PASSED] drm_test_connector_hdmi_init_bpc_null
[10:29:07] [PASSED] drm_test_connector_hdmi_init_formats_empty
[10:29:07] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[10:29:07] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[10:29:07] [PASSED] supported_formats=0x9 yuv420_allowed=1
[10:29:07] [PASSED] supported_formats=0x9 yuv420_allowed=0
[10:29:07] [PASSED] supported_formats=0x3 yuv420_allowed=1
[10:29:07] [PASSED] supported_formats=0x3 yuv420_allowed=0
[10:29:07] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[10:29:07] [PASSED] drm_test_connector_hdmi_init_null_ddc
[10:29:07] [PASSED] drm_test_connector_hdmi_init_null_product
[10:29:07] [PASSED] drm_test_connector_hdmi_init_null_vendor
[10:29:07] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[10:29:07] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[10:29:07] [PASSED] drm_test_connector_hdmi_init_product_valid
[10:29:07] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[10:29:07] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[10:29:07] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[10:29:07] ========= drm_test_connector_hdmi_init_type_valid  =========
[10:29:07] [PASSED] HDMI-A
[10:29:07] [PASSED] HDMI-B
[10:29:07] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[10:29:07] ======== drm_test_connector_hdmi_init_type_invalid  ========
[10:29:07] [PASSED] Unknown
[10:29:07] [PASSED] VGA
[10:29:07] [PASSED] DVI-I
[10:29:07] [PASSED] DVI-D
[10:29:07] [PASSED] DVI-A
[10:29:07] [PASSED] Composite
[10:29:07] [PASSED] SVIDEO
[10:29:07] [PASSED] LVDS
[10:29:07] [PASSED] Component
[10:29:07] [PASSED] DIN
[10:29:07] [PASSED] DP
[10:29:07] [PASSED] TV
[10:29:07] [PASSED] eDP
[10:29:07] [PASSED] Virtual
[10:29:07] [PASSED] DSI
[10:29:07] [PASSED] DPI
[10:29:07] [PASSED] Writeback
[10:29:07] [PASSED] SPI
[10:29:07] [PASSED] USB
[10:29:07] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[10:29:07] ============ [PASSED] drmm_connector_hdmi_init =============
[10:29:07] ============= drmm_connector_init (3 subtests) =============
[10:29:07] [PASSED] drm_test_drmm_connector_init
[10:29:07] [PASSED] drm_test_drmm_connector_init_null_ddc
[10:29:07] ========= drm_test_drmm_connector_init_type_valid  =========
[10:29:07] [PASSED] Unknown
[10:29:07] [PASSED] VGA
[10:29:07] [PASSED] DVI-I
[10:29:07] [PASSED] DVI-D
[10:29:07] [PASSED] DVI-A
[10:29:07] [PASSED] Composite
[10:29:07] [PASSED] SVIDEO
[10:29:07] [PASSED] LVDS
[10:29:07] [PASSED] Component
[10:29:07] [PASSED] DIN
[10:29:07] [PASSED] DP
[10:29:07] [PASSED] HDMI-A
[10:29:07] [PASSED] HDMI-B
[10:29:07] [PASSED] TV
[10:29:07] [PASSED] eDP
[10:29:07] [PASSED] Virtual
[10:29:07] [PASSED] DSI
[10:29:07] [PASSED] DPI
[10:29:07] [PASSED] Writeback
[10:29:07] [PASSED] SPI
[10:29:07] [PASSED] USB
[10:29:07] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[10:29:07] =============== [PASSED] drmm_connector_init ===============
[10:29:07] ========= drm_connector_dynamic_init (6 subtests) ==========
[10:29:07] [PASSED] drm_test_drm_connector_dynamic_init
[10:29:07] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[10:29:07] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[10:29:07] [PASSED] drm_test_drm_connector_dynamic_init_properties
[10:29:07] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[10:29:07] [PASSED] Unknown
[10:29:07] [PASSED] VGA
[10:29:07] [PASSED] DVI-I
[10:29:07] [PASSED] DVI-D
[10:29:07] [PASSED] DVI-A
[10:29:07] [PASSED] Composite
[10:29:07] [PASSED] SVIDEO
[10:29:07] [PASSED] LVDS
[10:29:07] [PASSED] Component
[10:29:07] [PASSED] DIN
[10:29:07] [PASSED] DP
[10:29:07] [PASSED] HDMI-A
[10:29:07] [PASSED] HDMI-B
[10:29:07] [PASSED] TV
[10:29:07] [PASSED] eDP
[10:29:07] [PASSED] Virtual
[10:29:07] [PASSED] DSI
[10:29:07] [PASSED] DPI
[10:29:07] [PASSED] Writeback
[10:29:07] [PASSED] SPI
[10:29:07] [PASSED] USB
[10:29:07] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[10:29:07] ======== drm_test_drm_connector_dynamic_init_name  =========
[10:29:07] [PASSED] Unknown
[10:29:07] [PASSED] VGA
[10:29:07] [PASSED] DVI-I
[10:29:07] [PASSED] DVI-D
[10:29:07] [PASSED] DVI-A
[10:29:07] [PASSED] Composite
[10:29:07] [PASSED] SVIDEO
[10:29:07] [PASSED] LVDS
[10:29:07] [PASSED] Component
[10:29:07] [PASSED] DIN
[10:29:07] [PASSED] DP
[10:29:07] [PASSED] HDMI-A
[10:29:07] [PASSED] HDMI-B
[10:29:07] [PASSED] TV
[10:29:07] [PASSED] eDP
[10:29:07] [PASSED] Virtual
[10:29:07] [PASSED] DSI
[10:29:07] [PASSED] DPI
[10:29:07] [PASSED] Writeback
[10:29:07] [PASSED] SPI
[10:29:07] [PASSED] USB
[10:29:07] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[10:29:07] =========== [PASSED] drm_connector_dynamic_init ============
[10:29:07] ==== drm_connector_dynamic_register_early (4 subtests) =====
[10:29:07] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[10:29:07] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[10:29:07] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[10:29:07] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[10:29:07] ====== [PASSED] drm_connector_dynamic_register_early =======
[10:29:07] ======= drm_connector_dynamic_register (7 subtests) ========
[10:29:07] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[10:29:07] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[10:29:07] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[10:29:07] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[10:29:07] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[10:29:07] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[10:29:07] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[10:29:07] ========= [PASSED] drm_connector_dynamic_register ==========
[10:29:07] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[10:29:07] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[10:29:07] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[10:29:07] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[10:29:07] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[10:29:07] ========== drm_test_get_tv_mode_from_name_valid  ===========
[10:29:07] [PASSED] NTSC
[10:29:07] [PASSED] NTSC-443
[10:29:07] [PASSED] NTSC-J
[10:29:07] [PASSED] PAL
[10:29:07] [PASSED] PAL-M
[10:29:07] [PASSED] PAL-N
[10:29:07] [PASSED] SECAM
[10:29:07] [PASSED] Mono
[10:29:07] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[10:29:07] [PASSED] drm_test_get_tv_mode_from_name_truncated
[10:29:07] ============ [PASSED] drm_get_tv_mode_from_name ============
[10:29:07] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[10:29:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[10:29:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[10:29:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[10:29:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[10:29:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[10:29:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[10:29:07] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[10:29:07] [PASSED] VIC 96
[10:29:07] [PASSED] VIC 97
[10:29:07] [PASSED] VIC 101
[10:29:07] [PASSED] VIC 102
[10:29:07] [PASSED] VIC 106
[10:29:07] [PASSED] VIC 107
[10:29:07] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[10:29:07] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[10:29:07] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[10:29:07] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[10:29:07] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[10:29:07] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[10:29:07] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[10:29:07] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[10:29:07] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[10:29:07] [PASSED] Automatic
[10:29:07] [PASSED] Full
[10:29:07] [PASSED] Limited 16:235
[10:29:07] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[10:29:07] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[10:29:07] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[10:29:07] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[10:29:07] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[10:29:07] [PASSED] RGB
[10:29:07] [PASSED] YUV 4:2:0
[10:29:07] [PASSED] YUV 4:2:2
[10:29:07] [PASSED] YUV 4:4:4
[10:29:07] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[10:29:07] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[10:29:07] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[10:29:07] ============= drm_damage_helper (21 subtests) ==============
[10:29:07] [PASSED] drm_test_damage_iter_no_damage
[10:29:07] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[10:29:07] [PASSED] drm_test_damage_iter_no_damage_src_moved
[10:29:07] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[10:29:07] [PASSED] drm_test_damage_iter_no_damage_not_visible
[10:29:07] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[10:29:07] [PASSED] drm_test_damage_iter_no_damage_no_fb
[10:29:07] [PASSED] drm_test_damage_iter_simple_damage
[10:29:07] [PASSED] drm_test_damage_iter_single_damage
[10:29:07] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[10:29:07] [PASSED] drm_test_damage_iter_single_damage_outside_src
[10:29:07] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[10:29:07] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[10:29:07] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[10:29:07] [PASSED] drm_test_damage_iter_single_damage_src_moved
[10:29:07] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[10:29:07] [PASSED] drm_test_damage_iter_damage
[10:29:07] [PASSED] drm_test_damage_iter_damage_one_intersect
[10:29:07] [PASSED] drm_test_damage_iter_damage_one_outside
[10:29:07] [PASSED] drm_test_damage_iter_damage_src_moved
[10:29:07] [PASSED] drm_test_damage_iter_damage_not_visible
[10:29:07] ================ [PASSED] drm_damage_helper ================
[10:29:07] ============== drm_dp_mst_helper (3 subtests) ==============
[10:29:07] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[10:29:07] [PASSED] Clock 154000 BPP 30 DSC disabled
[10:29:07] [PASSED] Clock 234000 BPP 30 DSC disabled
[10:29:07] [PASSED] Clock 297000 BPP 24 DSC disabled
[10:29:07] [PASSED] Clock 332880 BPP 24 DSC enabled
[10:29:07] [PASSED] Clock 324540 BPP 24 DSC enabled
[10:29:07] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[10:29:07] ============== drm_test_dp_mst_calc_pbn_div  ===============
[10:29:07] [PASSED] Link rate 2000000 lane count 4
[10:29:07] [PASSED] Link rate 2000000 lane count 2
[10:29:07] [PASSED] Link rate 2000000 lane count 1
[10:29:07] [PASSED] Link rate 1350000 lane count 4
[10:29:07] [PASSED] Link rate 1350000 lane count 2
[10:29:07] [PASSED] Link rate 1350000 lane count 1
[10:29:07] [PASSED] Link rate 1000000 lane count 4
[10:29:07] [PASSED] Link rate 1000000 lane count 2
[10:29:07] [PASSED] Link rate 1000000 lane count 1
[10:29:07] [PASSED] Link rate 810000 lane count 4
[10:29:07] [PASSED] Link rate 810000 lane count 2
[10:29:07] [PASSED] Link rate 810000 lane count 1
[10:29:07] [PASSED] Link rate 540000 lane count 4
[10:29:07] [PASSED] Link rate 540000 lane count 2
[10:29:07] [PASSED] Link rate 540000 lane count 1
[10:29:07] [PASSED] Link rate 270000 lane count 4
[10:29:07] [PASSED] Link rate 270000 lane count 2
[10:29:07] [PASSED] Link rate 270000 lane count 1
[10:29:07] [PASSED] Link rate 162000 lane count 4
[10:29:07] [PASSED] Link rate 162000 lane count 2
[10:29:07] [PASSED] Link rate 162000 lane count 1
[10:29:07] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[10:29:07] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[10:29:07] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[10:29:07] [PASSED] DP_POWER_UP_PHY with port number
[10:29:07] [PASSED] DP_POWER_DOWN_PHY with port number
[10:29:07] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[10:29:07] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[10:29:07] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[10:29:07] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[10:29:07] [PASSED] DP_QUERY_PAYLOAD with port number
[10:29:07] [PASSED] DP_QUERY_PAYLOAD with VCPI
[10:29:07] [PASSED] DP_REMOTE_DPCD_READ with port number
[10:29:07] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[10:29:07] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[10:29:07] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[10:29:07] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[10:29:07] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[10:29:07] [PASSED] DP_REMOTE_I2C_READ with port number
[10:29:07] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[10:29:07] [PASSED] DP_REMOTE_I2C_READ with transactions array
[10:29:07] [PASSED] DP_REMOTE_I2C_WRITE with port number
[10:29:07] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[10:29:07] [PASSED] DP_REMOTE_I2C_WRITE with data array
[10:29:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[10:29:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[10:29:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[10:29:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[10:29:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[10:29:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[10:29:07] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[10:29:07] ================ [PASSED] drm_dp_mst_helper ================
[10:29:07] ================== drm_exec (7 subtests) ===================
[10:29:07] [PASSED] sanitycheck
[10:29:07] [PASSED] test_lock
[10:29:07] [PASSED] test_lock_unlock
[10:29:07] [PASSED] test_duplicates
[10:29:07] [PASSED] test_prepare
[10:29:07] [PASSED] test_prepare_array
[10:29:07] [PASSED] test_multiple_loops
[10:29:07] ==================== [PASSED] drm_exec =====================
[10:29:07] =========== drm_format_helper_test (17 subtests) ===========
[10:29:07] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[10:29:07] [PASSED] single_pixel_source_buffer
[10:29:07] [PASSED] single_pixel_clip_rectangle
[10:29:07] [PASSED] well_known_colors
[10:29:07] [PASSED] destination_pitch
[10:29:07] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[10:29:07] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[10:29:07] [PASSED] single_pixel_source_buffer
[10:29:07] [PASSED] single_pixel_clip_rectangle
[10:29:07] [PASSED] well_known_colors
[10:29:07] [PASSED] destination_pitch
[10:29:07] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[10:29:07] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[10:29:07] [PASSED] single_pixel_source_buffer
[10:29:07] [PASSED] single_pixel_clip_rectangle
[10:29:07] [PASSED] well_known_colors
[10:29:07] [PASSED] destination_pitch
[10:29:07] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[10:29:07] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[10:29:07] [PASSED] single_pixel_source_buffer
[10:29:07] [PASSED] single_pixel_clip_rectangle
[10:29:07] [PASSED] well_known_colors
[10:29:07] [PASSED] destination_pitch
[10:29:07] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[10:29:07] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[10:29:07] [PASSED] single_pixel_source_buffer
[10:29:07] [PASSED] single_pixel_clip_rectangle
[10:29:07] [PASSED] well_known_colors
[10:29:07] [PASSED] destination_pitch
[10:29:07] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[10:29:07] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[10:29:07] [PASSED] single_pixel_source_buffer
[10:29:07] [PASSED] single_pixel_clip_rectangle
[10:29:07] [PASSED] well_known_colors
[10:29:07] [PASSED] destination_pitch
[10:29:07] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[10:29:07] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[10:29:07] [PASSED] single_pixel_source_buffer
[10:29:07] [PASSED] single_pixel_clip_rectangle
[10:29:07] [PASSED] well_known_colors
[10:29:07] [PASSED] destination_pitch
[10:29:07] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[10:29:07] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[10:29:07] [PASSED] single_pixel_source_buffer
[10:29:07] [PASSED] single_pixel_clip_rectangle
[10:29:07] [PASSED] well_known_colors
[10:29:07] [PASSED] destination_pitch
[10:29:07] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[10:29:07] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[10:29:07] [PASSED] single_pixel_source_buffer
[10:29:07] [PASSED] single_pixel_clip_rectangle
[10:29:07] [PASSED] well_known_colors
[10:29:07] [PASSED] destination_pitch
[10:29:07] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[10:29:07] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[10:29:07] [PASSED] single_pixel_source_buffer
[10:29:07] [PASSED] single_pixel_clip_rectangle
[10:29:07] [PASSED] well_known_colors
[10:29:07] [PASSED] destination_pitch
[10:29:07] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[10:29:07] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[10:29:07] [PASSED] single_pixel_source_buffer
[10:29:07] [PASSED] single_pixel_clip_rectangle
[10:29:07] [PASSED] well_known_colors
[10:29:07] [PASSED] destination_pitch
[10:29:07] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[10:29:07] ============== drm_test_fb_xrgb8888_to_mono  ===============
[10:29:07] [PASSED] single_pixel_source_buffer
[10:29:07] [PASSED] single_pixel_clip_rectangle
[10:29:07] [PASSED] well_known_colors
[10:29:07] [PASSED] destination_pitch
[10:29:07] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[10:29:07] ==================== drm_test_fb_swab  =====================
[10:29:07] [PASSED] single_pixel_source_buffer
[10:29:07] [PASSED] single_pixel_clip_rectangle
[10:29:07] [PASSED] well_known_colors
[10:29:07] [PASSED] destination_pitch
[10:29:07] ================ [PASSED] drm_test_fb_swab =================
[10:29:07] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[10:29:07] [PASSED] single_pixel_source_buffer
[10:29:07] [PASSED] single_pixel_clip_rectangle
[10:29:07] [PASSED] well_known_colors
[10:29:07] [PASSED] destination_pitch
[10:29:07] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[10:29:07] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[10:29:07] [PASSED] single_pixel_source_buffer
[10:29:07] [PASSED] single_pixel_clip_rectangle
[10:29:07] [PASSED] well_known_colors
[10:29:07] [PASSED] destination_pitch
[10:29:07] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[10:29:07] ================= drm_test_fb_clip_offset  =================
[10:29:07] [PASSED] pass through
[10:29:07] [PASSED] horizontal offset
[10:29:07] [PASSED] vertical offset
[10:29:07] [PASSED] horizontal and vertical offset
[10:29:07] [PASSED] horizontal offset (custom pitch)
[10:29:07] [PASSED] vertical offset (custom pitch)
[10:29:07] [PASSED] horizontal and vertical offset (custom pitch)
[10:29:07] ============= [PASSED] drm_test_fb_clip_offset =============
[10:29:07] =================== drm_test_fb_memcpy  ====================
[10:29:07] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[10:29:07] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[10:29:07] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[10:29:07] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[10:29:07] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[10:29:07] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[10:29:07] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[10:29:07] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[10:29:07] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[10:29:07] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[10:29:07] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[10:29:07] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[10:29:07] =============== [PASSED] drm_test_fb_memcpy ================
[10:29:07] ============= [PASSED] drm_format_helper_test ==============
[10:29:07] ================= drm_format (18 subtests) =================
[10:29:07] [PASSED] drm_test_format_block_width_invalid
[10:29:07] [PASSED] drm_test_format_block_width_one_plane
[10:29:07] [PASSED] drm_test_format_block_width_two_plane
[10:29:07] [PASSED] drm_test_format_block_width_three_plane
[10:29:07] [PASSED] drm_test_format_block_width_tiled
[10:29:07] [PASSED] drm_test_format_block_height_invalid
[10:29:07] [PASSED] drm_test_format_block_height_one_plane
[10:29:07] [PASSED] drm_test_format_block_height_two_plane
[10:29:07] [PASSED] drm_test_format_block_height_three_plane
[10:29:07] [PASSED] drm_test_format_block_height_tiled
[10:29:07] [PASSED] drm_test_format_min_pitch_invalid
[10:29:07] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[10:29:07] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[10:29:07] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[10:29:07] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[10:29:07] [PASSED] drm_test_format_min_pitch_two_plane
[10:29:07] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[10:29:07] [PASSED] drm_test_format_min_pitch_tiled
[10:29:07] =================== [PASSED] drm_format ====================
[10:29:07] ============== drm_framebuffer (10 subtests) ===============
[10:29:07] ========== drm_test_framebuffer_check_src_coords  ==========
[10:29:07] [PASSED] Success: source fits into fb
[10:29:07] [PASSED] Fail: overflowing fb with x-axis coordinate
[10:29:07] [PASSED] Fail: overflowing fb with y-axis coordinate
[10:29:07] [PASSED] Fail: overflowing fb with source width
[10:29:07] [PASSED] Fail: overflowing fb with source height
[10:29:07] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[10:29:07] [PASSED] drm_test_framebuffer_cleanup
[10:29:07] =============== drm_test_framebuffer_create  ===============
[10:29:07] [PASSED] ABGR8888 normal sizes
[10:29:07] [PASSED] ABGR8888 max sizes
[10:29:07] [PASSED] ABGR8888 pitch greater than min required
[10:29:07] [PASSED] ABGR8888 pitch less than min required
[10:29:07] [PASSED] ABGR8888 Invalid width
[10:29:07] [PASSED] ABGR8888 Invalid buffer handle
[10:29:07] [PASSED] No pixel format
[10:29:07] [PASSED] ABGR8888 Width 0
[10:29:07] [PASSED] ABGR8888 Height 0
[10:29:07] [PASSED] ABGR8888 Out of bound height * pitch combination
[10:29:07] [PASSED] ABGR8888 Large buffer offset
[10:29:07] [PASSED] ABGR8888 Buffer offset for inexistent plane
[10:29:07] [PASSED] ABGR8888 Invalid flag
[10:29:07] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[10:29:07] [PASSED] ABGR8888 Valid buffer modifier
[10:29:07] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[10:29:07] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[10:29:07] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[10:29:07] [PASSED] NV12 Normal sizes
[10:29:07] [PASSED] NV12 Max sizes
[10:29:07] [PASSED] NV12 Invalid pitch
[10:29:07] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[10:29:07] [PASSED] NV12 different  modifier per-plane
[10:29:07] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[10:29:07] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[10:29:07] [PASSED] NV12 Modifier for inexistent plane
[10:29:07] [PASSED] NV12 Handle for inexistent plane
[10:29:07] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[10:29:07] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[10:29:07] [PASSED] YVU420 Normal sizes
[10:29:07] [PASSED] YVU420 Max sizes
[10:29:07] [PASSED] YVU420 Invalid pitch
[10:29:07] [PASSED] YVU420 Different pitches
[10:29:07] [PASSED] YVU420 Different buffer offsets/pitches
[10:29:07] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[10:29:07] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[10:29:07] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[10:29:07] [PASSED] YVU420 Valid modifier
[10:29:07] [PASSED] YVU420 Different modifiers per plane
[10:29:07] [PASSED] YVU420 Modifier for inexistent plane
[10:29:07] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[10:29:07] [PASSED] X0L2 Normal sizes
[10:29:07] [PASSED] X0L2 Max sizes
[10:29:07] [PASSED] X0L2 Invalid pitch
[10:29:07] [PASSED] X0L2 Pitch greater than minimum required
[10:29:07] [PASSED] X0L2 Handle for inexistent plane
[10:29:07] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[10:29:07] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[10:29:07] [PASSED] X0L2 Valid modifier
[10:29:07] [PASSED] X0L2 Modifier for inexistent plane
[10:29:07] =========== [PASSED] drm_test_framebuffer_create ===========
[10:29:07] [PASSED] drm_test_framebuffer_free
[10:29:07] [PASSED] drm_test_framebuffer_init
[10:29:07] [PASSED] drm_test_framebuffer_init_bad_format
[10:29:07] [PASSED] drm_test_framebuffer_init_dev_mismatch
[10:29:07] [PASSED] drm_test_framebuffer_lookup
[10:29:07] [PASSED] drm_test_framebuffer_lookup_inexistent
[10:29:07] [PASSED] drm_test_framebuffer_modifiers_not_supported
[10:29:07] ================= [PASSED] drm_framebuffer =================
[10:29:07] ================ drm_gem_shmem (8 subtests) ================
[10:29:07] [PASSED] drm_gem_shmem_test_obj_create
[10:29:07] [PASSED] drm_gem_shmem_test_obj_create_private
[10:29:07] [PASSED] drm_gem_shmem_test_pin_pages
[10:29:07] [PASSED] drm_gem_shmem_test_vmap
[10:29:07] [PASSED] drm_gem_shmem_test_get_sg_table
[10:29:07] [PASSED] drm_gem_shmem_test_get_pages_sgt
[10:29:07] [PASSED] drm_gem_shmem_test_madvise
[10:29:07] [PASSED] drm_gem_shmem_test_purge
[10:29:07] ================== [PASSED] drm_gem_shmem ==================
[10:29:07] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[10:29:07] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[10:29:07] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[10:29:07] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[10:29:07] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[10:29:07] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[10:29:07] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[10:29:07] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[10:29:07] [PASSED] Automatic
[10:29:07] [PASSED] Full
[10:29:07] [PASSED] Limited 16:235
[10:29:07] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[10:29:07] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[10:29:07] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[10:29:07] [PASSED] drm_test_check_disable_connector
[10:29:07] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[10:29:07] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[10:29:07] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[10:29:07] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[10:29:07] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[10:29:07] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[10:29:07] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[10:29:07] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[10:29:07] [PASSED] drm_test_check_output_bpc_dvi
[10:29:07] [PASSED] drm_test_check_output_bpc_format_vic_1
[10:29:07] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[10:29:07] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[10:29:07] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[10:29:07] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[10:29:07] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[10:29:07] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[10:29:07] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[10:29:07] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[10:29:07] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[10:29:07] [PASSED] drm_test_check_broadcast_rgb_value
[10:29:07] [PASSED] drm_test_check_bpc_8_value
[10:29:07] [PASSED] drm_test_check_bpc_10_value
[10:29:07] [PASSED] drm_test_check_bpc_12_value
[10:29:07] [PASSED] drm_test_check_format_value
[10:29:07] [PASSED] drm_test_check_tmds_char_value
[10:29:07] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[10:29:07] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[10:29:07] [PASSED] drm_test_check_mode_valid
[10:29:07] [PASSED] drm_test_check_mode_valid_reject
[10:29:07] [PASSED] drm_test_check_mode_valid_reject_rate
[10:29:07] [PASSED] drm_test_check_mode_valid_reject_max_clock
[10:29:07] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[10:29:07] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[10:29:07] [PASSED] drm_test_check_infoframes
[10:29:07] [PASSED] drm_test_check_reject_avi_infoframe
[10:29:07] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[10:29:07] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[10:29:07] [PASSED] drm_test_check_reject_audio_infoframe
[10:29:07] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[10:29:07] ================= drm_managed (2 subtests) =================
[10:29:07] [PASSED] drm_test_managed_release_action
[10:29:07] [PASSED] drm_test_managed_run_action
[10:29:07] =================== [PASSED] drm_managed ===================
[10:29:07] =================== drm_mm (6 subtests) ====================
[10:29:07] [PASSED] drm_test_mm_init
[10:29:07] [PASSED] drm_test_mm_debug
[10:29:07] [PASSED] drm_test_mm_align32
[10:29:07] [PASSED] drm_test_mm_align64
[10:29:07] [PASSED] drm_test_mm_lowest
[10:29:07] [PASSED] drm_test_mm_highest
[10:29:07] ===================== [PASSED] drm_mm ======================
[10:29:07] ============= drm_modes_analog_tv (5 subtests) =============
[10:29:07] [PASSED] drm_test_modes_analog_tv_mono_576i
[10:29:07] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[10:29:07] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[10:29:07] [PASSED] drm_test_modes_analog_tv_pal_576i
[10:29:07] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[10:29:07] =============== [PASSED] drm_modes_analog_tv ===============
[10:29:07] ============== drm_plane_helper (2 subtests) ===============
[10:29:07] =============== drm_test_check_plane_state  ================
[10:29:07] [PASSED] clipping_simple
[10:29:07] [PASSED] clipping_rotate_reflect
[10:29:07] [PASSED] positioning_simple
[10:29:07] [PASSED] upscaling
[10:29:07] [PASSED] downscaling
[10:29:07] [PASSED] rounding1
[10:29:07] [PASSED] rounding2
[10:29:07] [PASSED] rounding3
[10:29:07] [PASSED] rounding4
[10:29:07] =========== [PASSED] drm_test_check_plane_state ============
[10:29:07] =========== drm_test_check_invalid_plane_state  ============
[10:29:07] [PASSED] positioning_invalid
[10:29:07] [PASSED] upscaling_invalid
[10:29:07] [PASSED] downscaling_invalid
[10:29:07] ======= [PASSED] drm_test_check_invalid_plane_state ========
[10:29:07] ================ [PASSED] drm_plane_helper =================
[10:29:07] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[10:29:07] ====== drm_test_connector_helper_tv_get_modes_check  =======
[10:29:07] [PASSED] None
[10:29:07] [PASSED] PAL
[10:29:07] [PASSED] NTSC
[10:29:07] [PASSED] Both, NTSC Default
[10:29:07] [PASSED] Both, PAL Default
[10:29:07] [PASSED] Both, NTSC Default, with PAL on command-line
[10:29:07] [PASSED] Both, PAL Default, with NTSC on command-line
[10:29:07] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[10:29:07] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[10:29:07] ================== drm_rect (9 subtests) ===================
[10:29:07] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[10:29:07] [PASSED] drm_test_rect_clip_scaled_not_clipped
[10:29:07] [PASSED] drm_test_rect_clip_scaled_clipped
[10:29:07] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[10:29:07] ================= drm_test_rect_intersect  =================
[10:29:07] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[10:29:07] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[10:29:07] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[10:29:07] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[10:29:07] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[10:29:07] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[10:29:07] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[10:29:07] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[10:29:07] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[10:29:07] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[10:29:07] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[10:29:07] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[10:29:07] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[10:29:07] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[10:29:07] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[10:29:07] ============= [PASSED] drm_test_rect_intersect =============
[10:29:07] ================ drm_test_rect_calc_hscale  ================
[10:29:07] [PASSED] normal use
[10:29:07] [PASSED] out of max range
[10:29:07] [PASSED] out of min range
[10:29:07] [PASSED] zero dst
[10:29:07] [PASSED] negative src
[10:29:07] [PASSED] negative dst
[10:29:07] ============ [PASSED] drm_test_rect_calc_hscale ============
[10:29:07] ================ drm_test_rect_calc_vscale  ================
[10:29:07] [PASSED] normal use
[10:29:07] [PASSED] out of max range
[10:29:07] [PASSED] out of min range
[10:29:07] [PASSED] zero dst
[10:29:07] [PASSED] negative src
[10:29:07] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[10:29:07] ============ [PASSED] drm_test_rect_calc_vscale ============
[10:29:07] ================== drm_test_rect_rotate  ===================
[10:29:07] [PASSED] reflect-x
[10:29:07] [PASSED] reflect-y
[10:29:07] [PASSED] rotate-0
[10:29:07] [PASSED] rotate-90
[10:29:07] [PASSED] rotate-180
[10:29:07] [PASSED] rotate-270
[10:29:07] ============== [PASSED] drm_test_rect_rotate ===============
[10:29:07] ================ drm_test_rect_rotate_inv  =================
[10:29:07] [PASSED] reflect-x
[10:29:07] [PASSED] reflect-y
[10:29:07] [PASSED] rotate-0
[10:29:07] [PASSED] rotate-90
[10:29:07] [PASSED] rotate-180
[10:29:07] [PASSED] rotate-270
[10:29:07] ============ [PASSED] drm_test_rect_rotate_inv =============
[10:29:07] ==================== [PASSED] drm_rect =====================
[10:29:07] ============ drm_sysfb_modeset_test (1 subtest) ============
[10:29:07] ============ drm_test_sysfb_build_fourcc_list  =============
[10:29:07] [PASSED] no native formats
[10:29:07] [PASSED] XRGB8888 as native format
[10:29:07] [PASSED] remove duplicates
[10:29:07] [PASSED] convert alpha formats
[10:29:07] [PASSED] random formats
[10:29:07] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[10:29:07] ============= [PASSED] drm_sysfb_modeset_test ==============
[10:29:07] ================== drm_fixp (2 subtests) ===================
[10:29:07] [PASSED] drm_test_int2fixp
[10:29:07] [PASSED] drm_test_sm2fixp
[10:29:07] ==================== [PASSED] drm_fixp =====================
[10:29:07] ============================================================
[10:29:07] Testing complete. Ran 621 tests: passed: 621
[10:29:07] Elapsed time: 30.598s total, 1.653s configuring, 28.778s building, 0.121s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[10:29:07] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:29:09] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[10:29:19] Starting KUnit Kernel (1/1)...
[10:29:19] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:29:19] ================= ttm_device (5 subtests) ==================
[10:29:19] [PASSED] ttm_device_init_basic
[10:29:19] [PASSED] ttm_device_init_multiple
[10:29:19] [PASSED] ttm_device_fini_basic
[10:29:19] [PASSED] ttm_device_init_no_vma_man
[10:29:19] ================== ttm_device_init_pools  ==================
[10:29:19] [PASSED] No DMA allocations, no DMA32 required
[10:29:19] [PASSED] DMA allocations, DMA32 required
[10:29:19] [PASSED] No DMA allocations, DMA32 required
[10:29:19] [PASSED] DMA allocations, no DMA32 required
[10:29:19] ============== [PASSED] ttm_device_init_pools ==============
[10:29:19] =================== [PASSED] ttm_device ====================
[10:29:19] ================== ttm_pool (8 subtests) ===================
[10:29:19] ================== ttm_pool_alloc_basic  ===================
[10:29:19] [PASSED] One page
[10:29:19] [PASSED] More than one page
[10:29:19] [PASSED] Above the allocation limit
[10:29:19] [PASSED] One page, with coherent DMA mappings enabled
[10:29:19] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:29:19] ============== [PASSED] ttm_pool_alloc_basic ===============
[10:29:19] ============== ttm_pool_alloc_basic_dma_addr  ==============
[10:29:19] [PASSED] One page
[10:29:19] [PASSED] More than one page
[10:29:19] [PASSED] Above the allocation limit
[10:29:19] [PASSED] One page, with coherent DMA mappings enabled
[10:29:19] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:29:19] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[10:29:19] [PASSED] ttm_pool_alloc_order_caching_match
[10:29:19] [PASSED] ttm_pool_alloc_caching_mismatch
[10:29:19] [PASSED] ttm_pool_alloc_order_mismatch
[10:29:19] [PASSED] ttm_pool_free_dma_alloc
[10:29:19] [PASSED] ttm_pool_free_no_dma_alloc
[10:29:19] [PASSED] ttm_pool_fini_basic
[10:29:19] ==================== [PASSED] ttm_pool =====================
[10:29:19] ================ ttm_resource (8 subtests) =================
[10:29:19] ================= ttm_resource_init_basic  =================
[10:29:19] [PASSED] Init resource in TTM_PL_SYSTEM
[10:29:19] [PASSED] Init resource in TTM_PL_VRAM
[10:29:19] [PASSED] Init resource in a private placement
[10:29:19] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[10:29:19] ============= [PASSED] ttm_resource_init_basic =============
[10:29:19] [PASSED] ttm_resource_init_pinned
[10:29:19] [PASSED] ttm_resource_fini_basic
[10:29:19] [PASSED] ttm_resource_manager_init_basic
[10:29:19] [PASSED] ttm_resource_manager_usage_basic
[10:29:19] [PASSED] ttm_resource_manager_set_used_basic
[10:29:19] [PASSED] ttm_sys_man_alloc_basic
[10:29:19] [PASSED] ttm_sys_man_free_basic
[10:29:19] ================== [PASSED] ttm_resource ===================
[10:29:19] =================== ttm_tt (15 subtests) ===================
[10:29:19] ==================== ttm_tt_init_basic  ====================
[10:29:19] [PASSED] Page-aligned size
[10:29:19] [PASSED] Extra pages requested
[10:29:19] ================ [PASSED] ttm_tt_init_basic ================
[10:29:19] [PASSED] ttm_tt_init_misaligned
[10:29:19] [PASSED] ttm_tt_fini_basic
[10:29:19] [PASSED] ttm_tt_fini_sg
[10:29:19] [PASSED] ttm_tt_fini_shmem
[10:29:19] [PASSED] ttm_tt_create_basic
[10:29:19] [PASSED] ttm_tt_create_invalid_bo_type
[10:29:19] [PASSED] ttm_tt_create_ttm_exists
[10:29:19] [PASSED] ttm_tt_create_failed
[10:29:19] [PASSED] ttm_tt_destroy_basic
[10:29:19] [PASSED] ttm_tt_populate_null_ttm
[10:29:19] [PASSED] ttm_tt_populate_populated_ttm
[10:29:19] [PASSED] ttm_tt_unpopulate_basic
[10:29:19] [PASSED] ttm_tt_unpopulate_empty_ttm
[10:29:19] [PASSED] ttm_tt_swapin_basic
[10:29:19] ===================== [PASSED] ttm_tt ======================
[10:29:19] =================== ttm_bo (14 subtests) ===================
[10:29:19] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[10:29:19] [PASSED] Cannot be interrupted and sleeps
[10:29:19] [PASSED] Cannot be interrupted, locks straight away
[10:29:19] [PASSED] Can be interrupted, sleeps
[10:29:19] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[10:29:19] [PASSED] ttm_bo_reserve_locked_no_sleep
[10:29:19] [PASSED] ttm_bo_reserve_no_wait_ticket
[10:29:19] [PASSED] ttm_bo_reserve_double_resv
[10:29:19] [PASSED] ttm_bo_reserve_interrupted
[10:29:19] [PASSED] ttm_bo_reserve_deadlock
[10:29:19] [PASSED] ttm_bo_unreserve_basic
[10:29:19] [PASSED] ttm_bo_unreserve_pinned
[10:29:19] [PASSED] ttm_bo_unreserve_bulk
[10:29:19] [PASSED] ttm_bo_fini_basic
[10:29:19] [PASSED] ttm_bo_fini_shared_resv
[10:29:19] [PASSED] ttm_bo_pin_basic
[10:29:19] [PASSED] ttm_bo_pin_unpin_resource
[10:29:19] [PASSED] ttm_bo_multiple_pin_one_unpin
[10:29:19] ===================== [PASSED] ttm_bo ======================
[10:29:19] ============== ttm_bo_validate (21 subtests) ===============
[10:29:19] ============== ttm_bo_init_reserved_sys_man  ===============
[10:29:19] [PASSED] Buffer object for userspace
[10:29:19] [PASSED] Kernel buffer object
[10:29:19] [PASSED] Shared buffer object
[10:29:19] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[10:29:19] ============== ttm_bo_init_reserved_mock_man  ==============
[10:29:19] [PASSED] Buffer object for userspace
[10:29:19] [PASSED] Kernel buffer object
[10:29:19] [PASSED] Shared buffer object
[10:29:19] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[10:29:19] [PASSED] ttm_bo_init_reserved_resv
[10:29:19] ================== ttm_bo_validate_basic  ==================
[10:29:19] [PASSED] Buffer object for userspace
[10:29:19] [PASSED] Kernel buffer object
[10:29:19] [PASSED] Shared buffer object
[10:29:19] ============== [PASSED] ttm_bo_validate_basic ==============
[10:29:19] [PASSED] ttm_bo_validate_invalid_placement
[10:29:19] ============= ttm_bo_validate_same_placement  ==============
[10:29:19] [PASSED] System manager
[10:29:19] [PASSED] VRAM manager
[10:29:19] ========= [PASSED] ttm_bo_validate_same_placement ==========
[10:29:19] [PASSED] ttm_bo_validate_failed_alloc
[10:29:19] [PASSED] ttm_bo_validate_pinned
[10:29:19] [PASSED] ttm_bo_validate_busy_placement
[10:29:19] ================ ttm_bo_validate_multihop  =================
[10:29:19] [PASSED] Buffer object for userspace
[10:29:19] [PASSED] Kernel buffer object
[10:29:19] [PASSED] Shared buffer object
[10:29:19] ============ [PASSED] ttm_bo_validate_multihop =============
[10:29:19] ========== ttm_bo_validate_no_placement_signaled  ==========
[10:29:19] [PASSED] Buffer object in system domain, no page vector
[10:29:19] [PASSED] Buffer object in system domain with an existing page vector
[10:29:19] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[10:29:19] ======== ttm_bo_validate_no_placement_not_signaled  ========
[10:29:19] [PASSED] Buffer object for userspace
[10:29:19] [PASSED] Kernel buffer object
[10:29:19] [PASSED] Shared buffer object
[10:29:19] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[10:29:19] [PASSED] ttm_bo_validate_move_fence_signaled
[10:29:19] ========= ttm_bo_validate_move_fence_not_signaled  =========
[10:29:19] [PASSED] Waits for GPU
[10:29:19] [PASSED] Tries to lock straight away
[10:29:19] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[10:29:19] [PASSED] ttm_bo_validate_happy_evict
[10:29:19] [PASSED] ttm_bo_validate_all_pinned_evict
[10:29:19] [PASSED] ttm_bo_validate_allowed_only_evict
[10:29:19] [PASSED] ttm_bo_validate_deleted_evict
[10:29:19] [PASSED] ttm_bo_validate_busy_domain_evict
[10:29:19] [PASSED] ttm_bo_validate_evict_gutting
[10:29:19] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[10:29:19] ================= [PASSED] ttm_bo_validate =================
[10:29:19] ============================================================
[10:29:19] Testing complete. Ran 101 tests: passed: 101
[10:29:19] Elapsed time: 11.428s total, 1.644s configuring, 9.518s building, 0.225s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for PSR/PR Selective Fetch Early Transport fixes (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2001 bytes --]

== Series Details ==

Series: PSR/PR Selective Fetch Early Transport fixes (rev3)
URL   : https://patchwork.freedesktop.org/series/161835/
State : success

== Summary ==

CI Bug Log - changes from xe-4658-d17c843163eeb774261fd8b0ea9e278c0e57db50_BAT -> xe-pw-161835v3_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (14 -> 14)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-161835v3_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
    - bat-adlp-7:         [PASS][1] -> [DMESG-WARN][2] ([Intel XE#7483])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4658-d17c843163eeb774261fd8b0ea9e278c0e57db50/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161835v3/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html

  
#### Possible fixes ####

  * igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1:
    - bat-adlp-7:         [DMESG-WARN][3] ([Intel XE#7483]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4658-d17c843163eeb774261fd8b0ea9e278c0e57db50/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161835v3/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1.html

  
  [Intel XE#7483]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7483


Build changes
-------------

  * Linux: xe-4658-d17c843163eeb774261fd8b0ea9e278c0e57db50 -> xe-pw-161835v3

  IGT_8777: a50285a68dbef0fe11140adef4016a756f57b324 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4658-d17c843163eeb774261fd8b0ea9e278c0e57db50: d17c843163eeb774261fd8b0ea9e278c0e57db50
  xe-pw-161835v3: 161835v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161835v3/index.html

[-- Attachment #2: Type: text/html, Size: 2664 bytes --]

✓ Xe.CI.FULL: success for PSR/PR Selective Fetch Early Transport fixes (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 8171 bytes --]

== Series Details ==

Series: PSR/PR Selective Fetch Early Transport fixes (rev3)
URL   : https://patchwork.freedesktop.org/series/161835/
State : success

== Summary ==

CI Bug Log - changes from xe-4658-d17c843163eeb774261fd8b0ea9e278c0e57db50_FULL -> xe-pw-161835v3_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-161835v3_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][1] ([Intel XE#2652]) +7 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161835v3/shard-bmg-8/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [PASS][2] -> [INCOMPLETE][3] ([Intel XE#7084]) +1 other test incomplete
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4658-d17c843163eeb774261fd8b0ea9e278c0e57db50/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161835v3/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_content_protection@atomic@pipe-a-dp-1:
    - shard-bmg:          NOTRUN -> [FAIL][4] ([Intel XE#3304])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161835v3/shard-bmg-5/igt@kms_content_protection@atomic@pipe-a-dp-1.html

  * igt@kms_content_protection@suspend-resume@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][5] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161835v3/shard-bmg-9/igt@kms_content_protection@suspend-resume@pipe-a-dp-2.html

  * igt@kms_content_protection@uevent-hdcp14@pipe-a-dp-1:
    - shard-bmg:          NOTRUN -> [FAIL][6] ([Intel XE#6707] / [Intel XE#7439])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161835v3/shard-bmg-5/igt@kms_content_protection@uevent-hdcp14@pipe-a-dp-1.html

  * igt@kms_cursor_edge_walk@256x256-right-edge:
    - shard-bmg:          [PASS][7] -> [FAIL][8] ([Intel XE#6841]) +1 other test fail
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4658-d17c843163eeb774261fd8b0ea9e278c0e57db50/shard-bmg-7/igt@kms_cursor_edge_walk@256x256-right-edge.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161835v3/shard-bmg-2/igt@kms_cursor_edge_walk@256x256-right-edge.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [PASS][9] -> [FAIL][10] ([Intel XE#2142]) +1 other test fail
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4658-d17c843163eeb774261fd8b0ea9e278c0e57db50/shard-lnl-2/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161835v3/shard-lnl-6/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  
#### Possible fixes ####

  * igt@kms_async_flips@crc-atomic@pipe-a-dp-2:
    - shard-bmg:          [ABORT][11] ([Intel XE#5545] / [Intel XE#6652]) -> [PASS][12] +1 other test pass
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4658-d17c843163eeb774261fd8b0ea9e278c0e57db50/shard-bmg-2/igt@kms_async_flips@crc-atomic@pipe-a-dp-2.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161835v3/shard-bmg-6/igt@kms_async_flips@crc-atomic@pipe-a-dp-2.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-bmg:          [DMESG-WARN][13] ([Intel XE#5208]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4658-d17c843163eeb774261fd8b0ea9e278c0e57db50/shard-bmg-2/igt@kms_flip@2x-flip-vs-suspend.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161835v3/shard-bmg-6/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@2x-flip-vs-suspend@cd-dp2-hdmi-a3:
    - shard-bmg:          [DMESG-WARN][15] -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4658-d17c843163eeb774261fd8b0ea9e278c0e57db50/shard-bmg-2/igt@kms_flip@2x-flip-vs-suspend@cd-dp2-hdmi-a3.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161835v3/shard-bmg-6/igt@kms_flip@2x-flip-vs-suspend@cd-dp2-hdmi-a3.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][17] ([Intel XE#6321]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4658-d17c843163eeb774261fd8b0ea9e278c0e57db50/shard-bmg-5/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161835v3/shard-bmg-9/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma:
    - shard-lnl:          [FAIL][19] ([Intel XE#5625]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4658-d17c843163eeb774261fd8b0ea9e278c0e57db50/shard-lnl-7/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161835v3/shard-lnl-2/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html

  
#### Warnings ####

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [FAIL][21] ([Intel XE#1729] / [Intel XE#7424]) -> [SKIP][22] ([Intel XE#2426] / [Intel XE#5848])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4658-d17c843163eeb774261fd8b0ea9e278c0e57db50/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161835v3/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][23] ([Intel XE#2509] / [Intel XE#7437]) -> [SKIP][24] ([Intel XE#2426] / [Intel XE#5848])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4658-d17c843163eeb774261fd8b0ea9e278c0e57db50/shard-bmg-6/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161835v3/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
  [Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6652
  [Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707
  [Intel XE#6841]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6841
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7439


Build changes
-------------

  * Linux: xe-4658-d17c843163eeb774261fd8b0ea9e278c0e57db50 -> xe-pw-161835v3

  IGT_8777: a50285a68dbef0fe11140adef4016a756f57b324 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4658-d17c843163eeb774261fd8b0ea9e278c0e57db50: d17c843163eeb774261fd8b0ea9e278c0e57db50
  xe-pw-161835v3: 161835v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161835v3/index.html

[-- Attachment #2: Type: text/html, Size: 9213 bytes --]

Re: [PATCH v3 4/4] drm/i915/psr: Write DSC parameters on Selective Update in ET mode

[Hogander, Jouni]

On Wed, 2026-03-04 at 17:33 +0530, Nautiyal, Ankit K wrote:
> 
> On 3/4/2026 5:00 PM, Jouni Högander wrote:
> > There are slice row per frame and pic height parameters in DSC that
> > needs
> > to be configured on every Selective Update in Early Transport mode.
> > Use
> > helper provided by DSC code to configure these on Selective Update
> > when in
> > Early Transport mode. Also fill crtc_state->psr2_su_area with full
> > frame
> > area on full frame update for DSC calculation.
> > 
> > v2: move psr2_su_area under skip_sel_fetch_set_loop label
> > 
> > Bspec: 68927, 71709
> > Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as
> > possible")
> > Cc: <stable@vger.kernel.org> # v6.9+
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> 
> Makes sense to, make the su area full at the end, if full_frame
> update 
> is needed.
> 
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Thank you Ankit for the review. These are now pushed to drm-intel-next.

BR,
Jouni Högander

> 
> > ---
> >   drivers/gpu/drm/i915/display/intel_psr.c | 10 ++++++++++
> >   1 file changed, 10 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 7b197e84e77d..cb3df2611515 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -2618,6 +2618,12 @@ void
> > intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb,
> >   
> >   	intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc-
> > >pipe),
> >   			   crtc_state->pipe_srcsz_early_tpt);
> > +
> > +	if (!crtc_state->dsc.compression_enable)
> > +		return;
> > +
> > +	intel_dsc_su_et_parameters_configure(dsb, encoder,
> > crtc_state,
> > +					    
> > drm_rect_height(&crtc_state->psr2_su_area));
> >   }
> >   
> >   static void psr2_man_trk_ctl_calc(struct intel_crtc_state
> > *crtc_state,
> > @@ -3039,6 +3045,10 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >   	}
> >   
> >   skip_sel_fetch_set_loop:
> > +	if (full_update)
> > +		clip_area_update(&crtc_state->psr2_su_area,
> > &crtc_state->pipe_src,
> > +				 &crtc_state->pipe_src);
> > +
> >   	psr2_man_trk_ctl_calc(crtc_state, full_update);
> >   	crtc_state->pipe_srcsz_early_tpt =
> >   		psr2_pipe_srcsz_early_tpt_calc(crtc_state,
> > full_update);