* ✗ CI.checkpatch: warning for drm/i915/display: Enable AS SDP Skip Frames (rev2)
2026-08-03 18:53 [PATCH 0/2] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
@ 2026-08-03 18:39 ` Patchwork
2026-08-03 18:40 ` ✓ CI.KUnit: success " Patchwork
` (10 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2026-08-03 18:39 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-xe
== Series Details ==
Series: drm/i915/display: Enable AS SDP Skip Frames (rev2)
URL : https://patchwork.freedesktop.org/series/162015/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
061140b9bc586ae7f40abc1249c97e1cc72d1b9d
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit d17891e8740a94e19ea1b177e4b1f92febf33d66
Author: Uma Shankar <uma.shankar@intel.com>
Date: Tue Aug 4 00:23:05 2026 +0530
drm/i915/display: Keep AS SDP flowing when skip frames is enabled
The AS SDP skip-frame mechanism relies on the AS SDP still being
transmitted (just less often) while Panel Replay is active, so the source
must not stop sending it in the PR active state, nor enter the DC3CO idle
protocol which would suppress it entirely.
When a non-zero skip-frame count is programmed, leave both
PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE and
PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL cleared. The previous behaviour
(honouring disable_as_sdp_when_pr_active and the DC3CO idle protocol) is
retained for the non skip-frame case.
Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Naladala Ramanaidu <ramanaidu.naladala@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
+ /mt/dim checkpatch f8d080b47819f01011c1b9c3c875badbb67ec955 drm-intel
e4844cdfb19e drm/i915/display: Enable AS SDP Skip Frames
-:90: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#90: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:455:
+ pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(
-:105: WARNING:LONG_LINE: line length of 125 exceeds 100 columns
#105: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:280:
+#define PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(frames) REG_FIELD_PREP(PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK, (frames))
total: 0 errors, 1 warnings, 1 checks, 65 lines checked
d17891e8740a drm/i915/display: Keep AS SDP flowing when skip frames is enabled
-:55: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#55: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:462:
+ pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
total: 0 errors, 1 warnings, 0 checks, 40 lines checked
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✓ CI.KUnit: success for drm/i915/display: Enable AS SDP Skip Frames (rev2)
2026-08-03 18:53 [PATCH 0/2] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
2026-08-03 18:39 ` ✗ CI.checkpatch: warning for drm/i915/display: Enable AS SDP Skip Frames (rev2) Patchwork
@ 2026-08-03 18:40 ` Patchwork
2026-08-03 18:53 ` [PATCH 1/2] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
` (9 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2026-08-03 18:40 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-xe
== Series Details ==
Series: drm/i915/display: Enable AS SDP Skip Frames (rev2)
URL : https://patchwork.freedesktop.org/series/162015/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[18:39:09] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[18:39:13] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[18:39:45] Starting KUnit Kernel (1/1)...
[18:39:45] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[18:39:45] ================== guc_buf (11 subtests) ===================
[18:39:45] [PASSED] test_smallest
[18:39:45] [PASSED] test_largest
[18:39:45] [PASSED] test_granular
[18:39:45] [PASSED] test_unique
[18:39:45] [PASSED] test_overlap
[18:39:45] [PASSED] test_reusable
[18:39:45] [PASSED] test_too_big
[18:39:45] [PASSED] test_flush
[18:39:45] [PASSED] test_lookup
[18:39:45] [PASSED] test_data
[18:39:45] [PASSED] test_class
[18:39:45] ===================== [PASSED] guc_buf =====================
[18:39:45] =================== guc_dbm (7 subtests) ===================
[18:39:45] [PASSED] test_empty
[18:39:45] [PASSED] test_default
[18:39:45] ======================== test_size ========================
[18:39:45] [PASSED] 4
[18:39:45] [PASSED] 8
[18:39:45] [PASSED] 32
[18:39:45] [PASSED] 256
[18:39:45] ==================== [PASSED] test_size ====================
[18:39:45] ======================= test_reuse ========================
[18:39:45] [PASSED] 4
[18:39:45] [PASSED] 8
[18:39:45] [PASSED] 32
[18:39:45] [PASSED] 256
[18:39:45] =================== [PASSED] test_reuse ====================
[18:39:45] =================== test_range_overlap ====================
[18:39:45] [PASSED] 4
[18:39:45] [PASSED] 8
[18:39:45] [PASSED] 32
[18:39:45] [PASSED] 256
[18:39:45] =============== [PASSED] test_range_overlap ================
[18:39:45] =================== test_range_compact ====================
[18:39:45] [PASSED] 4
[18:39:45] [PASSED] 8
[18:39:45] [PASSED] 32
[18:39:45] [PASSED] 256
[18:39:45] =============== [PASSED] test_range_compact ================
[18:39:45] ==================== test_range_spare =====================
[18:39:45] [PASSED] 4
[18:39:45] [PASSED] 8
[18:39:45] [PASSED] 32
[18:39:45] [PASSED] 256
[18:39:45] ================ [PASSED] test_range_spare =================
[18:39:45] ===================== [PASSED] guc_dbm =====================
[18:39:45] =================== guc_idm (6 subtests) ===================
[18:39:45] [PASSED] bad_init
[18:39:45] [PASSED] no_init
[18:39:45] [PASSED] init_fini
[18:39:45] [PASSED] check_used
[18:39:45] [PASSED] check_quota
[18:39:45] [PASSED] check_all
[18:39:45] ===================== [PASSED] guc_idm =====================
[18:39:45] =============== guc_klv_helpers (9 subtests) ===============
[18:39:45] [PASSED] test_count
[18:39:45] [PASSED] test_encode_u32
[18:39:45] [PASSED] test_encode_u64
[18:39:45] [PASSED] test_encode_string
[18:39:45] [PASSED] test_encode_object_raw
[18:39:45] [PASSED] test_encode_object_klv
[18:39:45] [PASSED] test_encode_object_nested
[18:39:45] [PASSED] test_encode_object_basic
[18:39:45] [PASSED] test_print
[18:39:45] ================= [PASSED] guc_klv_helpers =================
[18:39:45] ================== no_relay (3 subtests) ===================
[18:39:45] [PASSED] xe_drops_guc2pf_if_not_ready
[18:39:45] [PASSED] xe_drops_guc2vf_if_not_ready
[18:39:45] [PASSED] xe_rejects_send_if_not_ready
[18:39:45] ==================== [PASSED] no_relay =====================
[18:39:45] ================== pf_relay (14 subtests) ==================
[18:39:45] [PASSED] pf_rejects_guc2pf_too_short
[18:39:45] [PASSED] pf_rejects_guc2pf_too_long
[18:39:45] [PASSED] pf_rejects_guc2pf_no_payload
[18:39:45] [PASSED] pf_fails_no_payload
[18:39:45] [PASSED] pf_fails_bad_origin
[18:39:45] [PASSED] pf_fails_bad_type
[18:39:45] [PASSED] pf_txn_reports_error
[18:39:45] [PASSED] pf_txn_sends_pf2guc
[18:39:45] [PASSED] pf_sends_pf2guc
[18:39:45] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[18:39:45] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[18:39:45] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[18:39:45] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[18:39:45] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[18:39:45] ==================== [PASSED] pf_relay =====================
[18:39:45] ================== vf_relay (3 subtests) ===================
[18:39:45] [PASSED] vf_rejects_guc2vf_too_short
[18:39:45] [PASSED] vf_rejects_guc2vf_too_long
[18:39:45] [PASSED] vf_rejects_guc2vf_no_payload
[18:39:45] ==================== [PASSED] vf_relay =====================
[18:39:45] ================ pf_gt_config (9 subtests) =================
[18:39:45] [PASSED] fair_contexts_1vf
[18:39:45] [PASSED] fair_doorbells_1vf
[18:39:45] [PASSED] fair_ggtt_1vf
[18:39:45] ====================== fair_vram_1vf ======================
[18:39:45] [PASSED] 3.50 GiB
[18:39:45] [PASSED] 11.5 GiB
[18:39:45] [PASSED] 15.5 GiB
[18:39:45] [PASSED] 31.5 GiB
[18:39:45] [PASSED] 63.5 GiB
[18:39:45] [PASSED] 1.91 GiB
[18:39:45] ================== [PASSED] fair_vram_1vf ==================
[18:39:45] ================ fair_vram_1vf_admin_only =================
[18:39:45] [PASSED] 3.50 GiB
[18:39:45] [PASSED] 11.5 GiB
[18:39:45] [PASSED] 15.5 GiB
[18:39:45] [PASSED] 31.5 GiB
[18:39:45] [PASSED] 63.5 GiB
[18:39:45] [PASSED] 1.91 GiB
[18:39:45] ============ [PASSED] fair_vram_1vf_admin_only =============
[18:39:45] ====================== fair_contexts ======================
[18:39:45] [PASSED] 1 VF
[18:39:45] [PASSED] 2 VFs
[18:39:45] [PASSED] 3 VFs
[18:39:45] [PASSED] 4 VFs
[18:39:45] [PASSED] 5 VFs
[18:39:45] [PASSED] 6 VFs
[18:39:45] [PASSED] 7 VFs
[18:39:45] [PASSED] 8 VFs
[18:39:45] [PASSED] 9 VFs
[18:39:45] [PASSED] 10 VFs
[18:39:45] [PASSED] 11 VFs
[18:39:45] [PASSED] 12 VFs
[18:39:45] [PASSED] 13 VFs
[18:39:45] [PASSED] 14 VFs
[18:39:45] [PASSED] 15 VFs
[18:39:45] [PASSED] 16 VFs
[18:39:45] [PASSED] 17 VFs
[18:39:45] [PASSED] 18 VFs
[18:39:45] [PASSED] 19 VFs
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[18:39:45] [PASSED] 27 VFs
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[18:39:45] [PASSED] 31 VFs
[18:39:45] [PASSED] 32 VFs
[18:39:45] [PASSED] 33 VFs
[18:39:45] [PASSED] 34 VFs
[18:39:45] [PASSED] 35 VFs
[18:39:45] [PASSED] 36 VFs
[18:39:45] [PASSED] 37 VFs
[18:39:45] [PASSED] 38 VFs
[18:39:45] [PASSED] 39 VFs
[18:39:45] [PASSED] 40 VFs
[18:39:45] [PASSED] 41 VFs
[18:39:45] [PASSED] 42 VFs
[18:39:45] [PASSED] 43 VFs
[18:39:45] [PASSED] 44 VFs
[18:39:45] [PASSED] 45 VFs
[18:39:45] [PASSED] 46 VFs
[18:39:45] [PASSED] 47 VFs
[18:39:45] [PASSED] 48 VFs
[18:39:45] [PASSED] 49 VFs
[18:39:45] [PASSED] 50 VFs
[18:39:45] [PASSED] 51 VFs
[18:39:45] [PASSED] 52 VFs
[18:39:45] [PASSED] 53 VFs
[18:39:45] [PASSED] 54 VFs
[18:39:45] [PASSED] 55 VFs
[18:39:45] [PASSED] 56 VFs
[18:39:45] [PASSED] 57 VFs
[18:39:45] [PASSED] 58 VFs
[18:39:45] [PASSED] 59 VFs
[18:39:45] [PASSED] 60 VFs
[18:39:45] [PASSED] 61 VFs
[18:39:45] [PASSED] 62 VFs
[18:39:45] [PASSED] 63 VFs
[18:39:45] ================== [PASSED] fair_contexts ==================
[18:39:45] ===================== fair_doorbells ======================
[18:39:45] [PASSED] 1 VF
[18:39:45] [PASSED] 2 VFs
[18:39:45] [PASSED] 3 VFs
[18:39:45] [PASSED] 4 VFs
[18:39:45] [PASSED] 5 VFs
[18:39:45] [PASSED] 6 VFs
[18:39:45] [PASSED] 7 VFs
[18:39:45] [PASSED] 8 VFs
[18:39:45] [PASSED] 9 VFs
[18:39:45] [PASSED] 10 VFs
[18:39:45] [PASSED] 11 VFs
[18:39:45] [PASSED] 12 VFs
[18:39:45] [PASSED] 13 VFs
[18:39:45] [PASSED] 14 VFs
[18:39:45] [PASSED] 15 VFs
[18:39:45] [PASSED] 16 VFs
[18:39:45] [PASSED] 17 VFs
[18:39:45] [PASSED] 18 VFs
[18:39:45] [PASSED] 19 VFs
[18:39:45] [PASSED] 20 VFs
[18:39:45] [PASSED] 21 VFs
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[18:39:45] [PASSED] 24 VFs
[18:39:45] [PASSED] 25 VFs
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[18:39:45] [PASSED] 27 VFs
[18:39:45] [PASSED] 28 VFs
[18:39:45] [PASSED] 29 VFs
[18:39:45] [PASSED] 30 VFs
[18:39:45] [PASSED] 31 VFs
[18:39:46] [PASSED] 32 VFs
[18:39:46] [PASSED] 33 VFs
[18:39:46] [PASSED] 34 VFs
[18:39:46] [PASSED] 35 VFs
[18:39:46] [PASSED] 36 VFs
[18:39:46] [PASSED] 37 VFs
[18:39:46] [PASSED] 38 VFs
[18:39:46] [PASSED] 39 VFs
[18:39:46] [PASSED] 40 VFs
[18:39:46] [PASSED] 41 VFs
[18:39:46] [PASSED] 42 VFs
[18:39:46] [PASSED] 43 VFs
[18:39:46] [PASSED] 44 VFs
[18:39:46] [PASSED] 45 VFs
[18:39:46] [PASSED] 46 VFs
[18:39:46] [PASSED] 47 VFs
[18:39:46] [PASSED] 48 VFs
[18:39:46] [PASSED] 49 VFs
[18:39:46] [PASSED] 50 VFs
[18:39:46] [PASSED] 51 VFs
[18:39:46] [PASSED] 52 VFs
[18:39:46] [PASSED] 53 VFs
[18:39:46] [PASSED] 54 VFs
[18:39:46] [PASSED] 55 VFs
[18:39:46] [PASSED] 56 VFs
[18:39:46] [PASSED] 57 VFs
[18:39:46] [PASSED] 58 VFs
[18:39:46] [PASSED] 59 VFs
[18:39:46] [PASSED] 60 VFs
[18:39:46] [PASSED] 61 VFs
[18:39:46] [PASSED] 62 VFs
[18:39:46] [PASSED] 63 VFs
[18:39:46] ================= [PASSED] fair_doorbells ==================
[18:39:46] ======================== fair_ggtt ========================
[18:39:46] [PASSED] 1 VF
[18:39:46] [PASSED] 2 VFs
[18:39:46] [PASSED] 3 VFs
[18:39:46] [PASSED] 4 VFs
[18:39:46] [PASSED] 5 VFs
[18:39:46] [PASSED] 6 VFs
[18:39:46] [PASSED] 7 VFs
[18:39:46] [PASSED] 8 VFs
[18:39:46] [PASSED] 9 VFs
[18:39:46] [PASSED] 10 VFs
[18:39:46] [PASSED] 11 VFs
[18:39:46] [PASSED] 12 VFs
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[18:39:46] [PASSED] 14 VFs
[18:39:46] [PASSED] 15 VFs
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[18:39:46] [PASSED] 19 VFs
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[18:39:46] [PASSED] 22 VFs
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[18:39:46] [PASSED] 26 VFs
[18:39:46] [PASSED] 27 VFs
[18:39:46] [PASSED] 28 VFs
[18:39:46] [PASSED] 29 VFs
[18:39:46] [PASSED] 30 VFs
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[18:39:46] [PASSED] 33 VFs
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[18:39:46] [PASSED] 35 VFs
[18:39:46] [PASSED] 36 VFs
[18:39:46] [PASSED] 37 VFs
[18:39:46] [PASSED] 38 VFs
[18:39:46] [PASSED] 39 VFs
[18:39:46] [PASSED] 40 VFs
[18:39:46] [PASSED] 41 VFs
[18:39:46] [PASSED] 42 VFs
[18:39:46] [PASSED] 43 VFs
[18:39:46] [PASSED] 44 VFs
[18:39:46] [PASSED] 45 VFs
[18:39:46] [PASSED] 46 VFs
[18:39:46] [PASSED] 47 VFs
[18:39:46] [PASSED] 48 VFs
[18:39:46] [PASSED] 49 VFs
[18:39:46] [PASSED] 50 VFs
[18:39:46] [PASSED] 51 VFs
[18:39:46] [PASSED] 52 VFs
[18:39:46] [PASSED] 53 VFs
[18:39:46] [PASSED] 54 VFs
[18:39:46] [PASSED] 55 VFs
[18:39:46] [PASSED] 56 VFs
[18:39:46] [PASSED] 57 VFs
[18:39:46] [PASSED] 58 VFs
[18:39:46] [PASSED] 59 VFs
[18:39:46] [PASSED] 60 VFs
[18:39:46] [PASSED] 61 VFs
[18:39:46] [PASSED] 62 VFs
[18:39:46] [PASSED] 63 VFs
[18:39:46] ==================== [PASSED] fair_ggtt ====================
[18:39:46] ======================== fair_vram ========================
[18:39:46] [PASSED] 1 VF
[18:39:46] [PASSED] 2 VFs
[18:39:46] [PASSED] 3 VFs
[18:39:46] [PASSED] 4 VFs
[18:39:46] [PASSED] 5 VFs
[18:39:46] [PASSED] 6 VFs
[18:39:46] [PASSED] 7 VFs
[18:39:46] [PASSED] 8 VFs
[18:39:46] [PASSED] 9 VFs
[18:39:46] [PASSED] 10 VFs
[18:39:46] [PASSED] 11 VFs
[18:39:46] [PASSED] 12 VFs
[18:39:46] [PASSED] 13 VFs
[18:39:46] [PASSED] 14 VFs
[18:39:46] [PASSED] 15 VFs
[18:39:46] [PASSED] 16 VFs
[18:39:46] [PASSED] 17 VFs
[18:39:46] [PASSED] 18 VFs
[18:39:46] [PASSED] 19 VFs
[18:39:46] [PASSED] 20 VFs
[18:39:46] [PASSED] 21 VFs
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[18:39:46] [PASSED] 24 VFs
[18:39:46] [PASSED] 25 VFs
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[18:39:46] [PASSED] 27 VFs
[18:39:46] [PASSED] 28 VFs
[18:39:46] [PASSED] 29 VFs
[18:39:46] [PASSED] 30 VFs
[18:39:46] [PASSED] 31 VFs
[18:39:46] [PASSED] 32 VFs
[18:39:46] [PASSED] 33 VFs
[18:39:46] [PASSED] 34 VFs
[18:39:46] [PASSED] 35 VFs
[18:39:46] [PASSED] 36 VFs
[18:39:46] [PASSED] 37 VFs
[18:39:46] [PASSED] 38 VFs
[18:39:46] [PASSED] 39 VFs
[18:39:46] [PASSED] 40 VFs
[18:39:46] [PASSED] 41 VFs
[18:39:46] [PASSED] 42 VFs
[18:39:46] [PASSED] 43 VFs
[18:39:46] [PASSED] 44 VFs
[18:39:46] [PASSED] 45 VFs
[18:39:46] [PASSED] 46 VFs
[18:39:46] [PASSED] 47 VFs
[18:39:46] [PASSED] 48 VFs
[18:39:46] [PASSED] 49 VFs
[18:39:46] [PASSED] 50 VFs
[18:39:46] [PASSED] 51 VFs
[18:39:46] [PASSED] 52 VFs
[18:39:46] [PASSED] 53 VFs
[18:39:46] [PASSED] 54 VFs
[18:39:46] [PASSED] 55 VFs
[18:39:46] [PASSED] 56 VFs
[18:39:46] [PASSED] 57 VFs
[18:39:46] [PASSED] 58 VFs
[18:39:46] [PASSED] 59 VFs
[18:39:46] [PASSED] 60 VFs
[18:39:46] [PASSED] 61 VFs
[18:39:46] [PASSED] 62 VFs
[18:39:46] [PASSED] 63 VFs
[18:39:46] ==================== [PASSED] fair_vram ====================
[18:39:46] ================== [PASSED] pf_gt_config ===================
[18:39:46] ===================== lmtt (1 subtest) =====================
[18:39:46] ======================== test_ops =========================
[18:39:46] [PASSED] 2-level
[18:39:46] [PASSED] multi-level
[18:39:46] ==================== [PASSED] test_ops =====================
[18:39:46] ====================== [PASSED] lmtt =======================
[18:39:46] ================= sriov_packet (1 subtest) =================
[18:39:46] [PASSED] test_descriptor_init
[18:39:46] ================== [PASSED] sriov_packet ===================
[18:39:46] ================= pf_service (11 subtests) =================
[18:39:46] [PASSED] pf_negotiate_any
[18:39:46] [PASSED] pf_negotiate_base_match
[18:39:46] [PASSED] pf_negotiate_base_newer
[18:39:46] [PASSED] pf_negotiate_base_next
[18:39:46] [SKIPPED] pf_negotiate_base_older (no older minor)
[18:39:46] [PASSED] pf_negotiate_base_prev
[18:39:46] [PASSED] pf_negotiate_latest_match
[18:39:46] [PASSED] pf_negotiate_latest_newer
[18:39:46] [PASSED] pf_negotiate_latest_next
[18:39:46] [SKIPPED] pf_negotiate_latest_older (no older minor)
[18:39:46] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[18:39:46] =================== [PASSED] pf_service ====================
[18:39:46] ================= xe_guc_g2g (2 subtests) ==================
[18:39:46] ============== xe_live_guc_g2g_kunit_default ==============
[18:39:46] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[18:39:46] ============== xe_live_guc_g2g_kunit_allmem ===============
[18:39:46] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[18:39:46] =================== [SKIPPED] xe_guc_g2g ===================
[18:39:46] =================== xe_mocs (2 subtests) ===================
[18:39:46] ================ xe_live_mocs_kernel_kunit ================
[18:39:46] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[18:39:46] ================ xe_live_mocs_reset_kunit =================
[18:39:46] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[18:39:46] ==================== [SKIPPED] xe_mocs =====================
[18:39:46] ================= xe_migrate (2 subtests) ==================
[18:39:46] ================= xe_migrate_sanity_kunit =================
[18:39:46] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[18:39:46] ================== xe_validate_ccs_kunit ==================
[18:39:46] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[18:39:46] =================== [SKIPPED] xe_migrate ===================
[18:39:46] ================== xe_dma_buf (1 subtest) ==================
[18:39:46] ==================== xe_dma_buf_kunit =====================
[18:39:46] ================ [SKIPPED] xe_dma_buf_kunit ================
[18:39:46] =================== [SKIPPED] xe_dma_buf ===================
[18:39:46] ================= xe_bo_shrink (1 subtest) =================
[18:39:46] =================== xe_bo_shrink_kunit ====================
[18:39:46] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[18:39:46] ================== [SKIPPED] xe_bo_shrink ==================
[18:39:46] ==================== xe_bo (2 subtests) ====================
[18:39:46] ================== xe_ccs_migrate_kunit ===================
[18:39:46] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[18:39:46] ==================== xe_bo_evict_kunit ====================
[18:39:46] =============== [SKIPPED] xe_bo_evict_kunit ================
[18:39:46] ===================== [SKIPPED] xe_bo ======================
[18:39:46] ==================== args (13 subtests) ====================
[18:39:46] [PASSED] count_args_test
[18:39:46] [PASSED] call_args_example
[18:39:46] [PASSED] call_args_test
[18:39:46] [PASSED] drop_first_arg_example
[18:39:46] [PASSED] drop_first_arg_test
[18:39:46] [PASSED] first_arg_example
[18:39:46] [PASSED] first_arg_test
[18:39:46] [PASSED] last_arg_example
[18:39:46] [PASSED] last_arg_test
[18:39:46] [PASSED] pick_arg_example
[18:39:46] [PASSED] if_args_example
[18:39:46] [PASSED] if_args_test
[18:39:46] [PASSED] sep_comma_example
[18:39:46] ====================== [PASSED] args =======================
[18:39:46] =================== xe_pci (3 subtests) ====================
[18:39:46] ==================== check_graphics_ip ====================
[18:39:46] [PASSED] 12.00 Xe_LP
[18:39:46] [PASSED] 12.10 Xe_LP+
[18:39:46] [PASSED] 12.55 Xe_HPG
[18:39:46] [PASSED] 12.60 Xe_HPC
[18:39:46] [PASSED] 12.70 Xe_LPG
[18:39:46] [PASSED] 12.71 Xe_LPG
[18:39:46] [PASSED] 12.74 Xe_LPG+
[18:39:46] [PASSED] 20.01 Xe2_HPG
[18:39:46] [PASSED] 20.02 Xe2_HPG
[18:39:46] [PASSED] 20.04 Xe2_LPG
[18:39:46] [PASSED] 30.00 Xe3_LPG
[18:39:46] [PASSED] 30.01 Xe3_LPG
[18:39:46] [PASSED] 30.03 Xe3_LPG
[18:39:46] [PASSED] 30.04 Xe3_LPG
[18:39:46] [PASSED] 30.05 Xe3_LPG
[18:39:46] [PASSED] 35.10 Xe3p_LPG
[18:39:46] [PASSED] 35.11 Xe3p_XPC
[18:39:46] ================ [PASSED] check_graphics_ip ================
[18:39:46] ===================== check_media_ip ======================
[18:39:46] [PASSED] 12.00 Xe_M
[18:39:46] [PASSED] 12.55 Xe_HPM
[18:39:46] [PASSED] 13.00 Xe_LPM+
[18:39:46] [PASSED] 13.01 Xe2_HPM
[18:39:46] [PASSED] 20.00 Xe2_LPM
[18:39:46] [PASSED] 30.00 Xe3_LPM
[18:39:46] [PASSED] 30.02 Xe3_LPM
[18:39:46] [PASSED] 35.00 Xe3p_LPM
[18:39:46] [PASSED] 35.03 Xe3p_HPM
[18:39:46] ================= [PASSED] check_media_ip ==================
[18:39:46] =================== check_platform_desc ===================
[18:39:46] [PASSED] 0x9A60 (TIGERLAKE)
[18:39:46] [PASSED] 0x9A68 (TIGERLAKE)
[18:39:46] [PASSED] 0x9A70 (TIGERLAKE)
[18:39:46] [PASSED] 0x9A40 (TIGERLAKE)
[18:39:46] [PASSED] 0x9A49 (TIGERLAKE)
[18:39:46] [PASSED] 0x9A59 (TIGERLAKE)
[18:39:46] [PASSED] 0x9A78 (TIGERLAKE)
[18:39:46] [PASSED] 0x9AC0 (TIGERLAKE)
[18:39:46] [PASSED] 0x9AC9 (TIGERLAKE)
[18:39:46] [PASSED] 0x9AD9 (TIGERLAKE)
[18:39:46] [PASSED] 0x9AF8 (TIGERLAKE)
[18:39:46] [PASSED] 0x4C80 (ROCKETLAKE)
[18:39:46] [PASSED] 0x4C8A (ROCKETLAKE)
[18:39:46] [PASSED] 0x4C8B (ROCKETLAKE)
[18:39:46] [PASSED] 0x4C8C (ROCKETLAKE)
[18:39:46] [PASSED] 0x4C90 (ROCKETLAKE)
[18:39:46] [PASSED] 0x4C9A (ROCKETLAKE)
[18:39:46] [PASSED] 0x4680 (ALDERLAKE_S)
[18:39:46] [PASSED] 0x4682 (ALDERLAKE_S)
[18:39:46] [PASSED] 0x4688 (ALDERLAKE_S)
[18:39:46] [PASSED] 0x468A (ALDERLAKE_S)
[18:39:46] [PASSED] 0x468B (ALDERLAKE_S)
[18:39:46] [PASSED] 0x4690 (ALDERLAKE_S)
[18:39:46] [PASSED] 0x4692 (ALDERLAKE_S)
[18:39:46] [PASSED] 0x4693 (ALDERLAKE_S)
[18:39:46] [PASSED] 0x46A0 (ALDERLAKE_P)
[18:39:46] [PASSED] 0x46A1 (ALDERLAKE_P)
[18:39:46] [PASSED] 0x46A2 (ALDERLAKE_P)
[18:39:46] [PASSED] 0x46A3 (ALDERLAKE_P)
[18:39:46] [PASSED] 0x46A6 (ALDERLAKE_P)
[18:39:46] [PASSED] 0x46A8 (ALDERLAKE_P)
[18:39:46] [PASSED] 0x46AA (ALDERLAKE_P)
[18:39:46] [PASSED] 0x462A (ALDERLAKE_P)
[18:39:46] [PASSED] 0x4626 (ALDERLAKE_P)
[18:39:46] [PASSED] 0x4628 (ALDERLAKE_P)
[18:39:46] [PASSED] 0x46B0 (ALDERLAKE_P)
[18:39:46] [PASSED] 0x46B1 (ALDERLAKE_P)
[18:39:46] [PASSED] 0x46B2 (ALDERLAKE_P)
[18:39:46] [PASSED] 0x46B3 (ALDERLAKE_P)
[18:39:46] [PASSED] 0x46C0 (ALDERLAKE_P)
[18:39:46] [PASSED] 0x46C1 (ALDERLAKE_P)
[18:39:46] [PASSED] 0x46C2 (ALDERLAKE_P)
[18:39:46] [PASSED] 0x46C3 (ALDERLAKE_P)
[18:39:46] [PASSED] 0x46D0 (ALDERLAKE_N)
[18:39:46] [PASSED] 0x46D1 (ALDERLAKE_N)
[18:39:46] [PASSED] 0x46D2 (ALDERLAKE_N)
[18:39:46] [PASSED] 0x46D3 (ALDERLAKE_N)
[18:39:46] [PASSED] 0x46D4 (ALDERLAKE_N)
[18:39:46] [PASSED] 0xA721 (ALDERLAKE_P)
[18:39:46] [PASSED] 0xA7A1 (ALDERLAKE_P)
[18:39:46] [PASSED] 0xA7A9 (ALDERLAKE_P)
[18:39:46] [PASSED] 0xA7AC (ALDERLAKE_P)
[18:39:46] [PASSED] 0xA7AD (ALDERLAKE_P)
[18:39:46] [PASSED] 0xA720 (ALDERLAKE_P)
[18:39:46] [PASSED] 0xA7A0 (ALDERLAKE_P)
[18:39:46] [PASSED] 0xA7A8 (ALDERLAKE_P)
[18:39:46] [PASSED] 0xA7AA (ALDERLAKE_P)
[18:39:46] [PASSED] 0xA7AB (ALDERLAKE_P)
[18:39:46] [PASSED] 0xA780 (ALDERLAKE_S)
[18:39:46] [PASSED] 0xA781 (ALDERLAKE_S)
[18:39:46] [PASSED] 0xA782 (ALDERLAKE_S)
[18:39:46] [PASSED] 0xA783 (ALDERLAKE_S)
[18:39:46] [PASSED] 0xA788 (ALDERLAKE_S)
[18:39:46] [PASSED] 0xA789 (ALDERLAKE_S)
[18:39:46] [PASSED] 0xA78A (ALDERLAKE_S)
[18:39:46] [PASSED] 0xA78B (ALDERLAKE_S)
[18:39:46] [PASSED] 0x4905 (DG1)
[18:39:46] [PASSED] 0x4906 (DG1)
[18:39:46] [PASSED] 0x4907 (DG1)
[18:39:46] [PASSED] 0x4908 (DG1)
[18:39:46] [PASSED] 0x4909 (DG1)
[18:39:46] [PASSED] 0x56C0 (DG2)
[18:39:46] [PASSED] 0x56C2 (DG2)
[18:39:46] [PASSED] 0x56C1 (DG2)
[18:39:46] [PASSED] 0x7D51 (METEORLAKE)
[18:39:46] [PASSED] 0x7DD1 (METEORLAKE)
[18:39:46] [PASSED] 0x7D41 (METEORLAKE)
[18:39:46] [PASSED] 0x7D67 (METEORLAKE)
[18:39:46] [PASSED] 0xB640 (METEORLAKE)
[18:39:46] [PASSED] 0x56A0 (DG2)
[18:39:46] [PASSED] 0x56A1 (DG2)
[18:39:46] [PASSED] 0x56A2 (DG2)
[18:39:46] [PASSED] 0x56BE (DG2)
[18:39:46] [PASSED] 0x56BF (DG2)
[18:39:46] [PASSED] 0x5690 (DG2)
[18:39:46] [PASSED] 0x5691 (DG2)
[18:39:46] [PASSED] 0x5692 (DG2)
[18:39:46] [PASSED] 0x56A5 (DG2)
[18:39:46] [PASSED] 0x56A6 (DG2)
[18:39:46] [PASSED] 0x56B0 (DG2)
[18:39:46] [PASSED] 0x56B1 (DG2)
[18:39:46] [PASSED] 0x56BA (DG2)
[18:39:46] [PASSED] 0x56BB (DG2)
[18:39:46] [PASSED] 0x56BC (DG2)
[18:39:46] [PASSED] 0x56BD (DG2)
[18:39:46] [PASSED] 0x5693 (DG2)
[18:39:46] [PASSED] 0x5694 (DG2)
[18:39:46] [PASSED] 0x5695 (DG2)
[18:39:46] [PASSED] 0x56A3 (DG2)
[18:39:46] [PASSED] 0x56A4 (DG2)
[18:39:46] [PASSED] 0x56B2 (DG2)
[18:39:46] [PASSED] 0x56B3 (DG2)
[18:39:46] [PASSED] 0x5696 (DG2)
[18:39:46] [PASSED] 0x5697 (DG2)
[18:39:46] [PASSED] 0xB69 (PVC)
[18:39:46] [PASSED] 0xB6E (PVC)
[18:39:46] [PASSED] 0xBD4 (PVC)
[18:39:46] [PASSED] 0xBD5 (PVC)
[18:39:46] [PASSED] 0xBD6 (PVC)
[18:39:46] [PASSED] 0xBD7 (PVC)
[18:39:46] [PASSED] 0xBD8 (PVC)
[18:39:46] [PASSED] 0xBD9 (PVC)
[18:39:46] [PASSED] 0xBDA (PVC)
[18:39:46] [PASSED] 0xBDB (PVC)
[18:39:46] [PASSED] 0xBE0 (PVC)
[18:39:46] [PASSED] 0xBE1 (PVC)
[18:39:46] [PASSED] 0xBE5 (PVC)
[18:39:46] [PASSED] 0x7D40 (METEORLAKE)
[18:39:46] [PASSED] 0x7D45 (METEORLAKE)
[18:39:46] [PASSED] 0x7D55 (METEORLAKE)
[18:39:46] [PASSED] 0x7D60 (METEORLAKE)
[18:39:46] [PASSED] 0x7DD5 (METEORLAKE)
[18:39:46] [PASSED] 0x6420 (LUNARLAKE)
[18:39:46] [PASSED] 0x64A0 (LUNARLAKE)
[18:39:46] [PASSED] 0x64B0 (LUNARLAKE)
[18:39:46] [PASSED] 0xE202 (BATTLEMAGE)
[18:39:46] [PASSED] 0xE209 (BATTLEMAGE)
[18:39:46] [PASSED] 0xE20B (BATTLEMAGE)
[18:39:46] [PASSED] 0xE20C (BATTLEMAGE)
[18:39:46] [PASSED] 0xE20D (BATTLEMAGE)
[18:39:46] [PASSED] 0xE210 (BATTLEMAGE)
[18:39:46] [PASSED] 0xE211 (BATTLEMAGE)
[18:39:46] [PASSED] 0xE212 (BATTLEMAGE)
[18:39:46] [PASSED] 0xE216 (BATTLEMAGE)
[18:39:46] [PASSED] 0xE220 (BATTLEMAGE)
[18:39:46] [PASSED] 0xE221 (BATTLEMAGE)
[18:39:46] [PASSED] 0xE222 (BATTLEMAGE)
[18:39:46] [PASSED] 0xE223 (BATTLEMAGE)
[18:39:46] [PASSED] 0xB080 (PANTHERLAKE)
[18:39:46] [PASSED] 0xB081 (PANTHERLAKE)
[18:39:46] [PASSED] 0xB082 (PANTHERLAKE)
[18:39:46] [PASSED] 0xB083 (PANTHERLAKE)
[18:39:46] [PASSED] 0xB084 (PANTHERLAKE)
[18:39:46] [PASSED] 0xB085 (PANTHERLAKE)
[18:39:46] [PASSED] 0xB086 (PANTHERLAKE)
[18:39:46] [PASSED] 0xB087 (PANTHERLAKE)
[18:39:46] [PASSED] 0xB08F (PANTHERLAKE)
[18:39:46] [PASSED] 0xB090 (PANTHERLAKE)
[18:39:46] [PASSED] 0xB0A0 (PANTHERLAKE)
[18:39:46] [PASSED] 0xB0B0 (PANTHERLAKE)
[18:39:46] [PASSED] 0xFD80 (PANTHERLAKE)
[18:39:46] [PASSED] 0xFD81 (PANTHERLAKE)
[18:39:46] [PASSED] 0xD740 (NOVALAKE_S)
[18:39:46] [PASSED] 0xD741 (NOVALAKE_S)
[18:39:46] [PASSED] 0xD742 (NOVALAKE_S)
[18:39:46] [PASSED] 0xD743 (NOVALAKE_S)
[18:39:46] [PASSED] 0xD745 (NOVALAKE_S)
[18:39:46] [PASSED] 0xD74A (NOVALAKE_S)
[18:39:46] [PASSED] 0xD74B (NOVALAKE_S)
[18:39:46] [PASSED] 0x674C (CRESCENTISLAND)
[18:39:46] [PASSED] 0x674D (CRESCENTISLAND)
[18:39:46] [PASSED] 0x674E (CRESCENTISLAND)
[18:39:46] [PASSED] 0x674F (CRESCENTISLAND)
[18:39:46] [PASSED] 0x6750 (CRESCENTISLAND)
[18:39:46] [PASSED] 0xD750 (NOVALAKE_P)
[18:39:46] [PASSED] 0xD751 (NOVALAKE_P)
[18:39:46] [PASSED] 0xD752 (NOVALAKE_P)
[18:39:46] [PASSED] 0xD753 (NOVALAKE_P)
[18:39:46] [PASSED] 0xD754 (NOVALAKE_P)
[18:39:46] [PASSED] 0xD755 (NOVALAKE_P)
[18:39:46] [PASSED] 0xD756 (NOVALAKE_P)
[18:39:46] [PASSED] 0xD757 (NOVALAKE_P)
[18:39:46] [PASSED] 0xD75F (NOVALAKE_P)
[18:39:46] =============== [PASSED] check_platform_desc ===============
[18:39:46] ===================== [PASSED] xe_pci ======================
[18:39:46] ============= xe_rtp_tables_test (5 subtests) ==============
[18:39:46] ================== xe_rtp_table_gt_test ===================
[18:39:46] [PASSED] gt_was/14011060649
[18:39:46] [PASSED] gt_was/14011059788
[18:39:46] [PASSED] gt_was/14015795083
[18:39:46] [PASSED] gt_was/16021867713
[18:39:46] [PASSED] gt_was/14019449301
[18:39:46] [PASSED] gt_was/16028005424
[18:39:46] [PASSED] gt_was/14026578760
[18:39:46] [PASSED] gt_was/1409420604
[18:39:46] [PASSED] gt_was/1408615072
[18:39:46] [PASSED] gt_was/22010523718
[18:39:46] [PASSED] gt_was/14011006942
[18:39:46] [PASSED] gt_was/14014830051
[18:39:46] [PASSED] gt_was/18018781329
[18:39:46] [PASSED] gt_was/1509235366
[18:39:46] [PASSED] gt_was/18018781329
[18:39:46] [PASSED] gt_was/16016694945
[18:39:46] [PASSED] gt_was/14018575942
[18:39:46] [PASSED] gt_was/22016670082
[18:39:46] [PASSED] gt_was/22016670082
[18:39:46] [PASSED] gt_was/14017421178
[18:39:46] [PASSED] gt_was/16025250150
[18:39:46] [PASSED] gt_was/14021871409
[18:39:46] [PASSED] gt_was/16021865536
[18:39:46] [PASSED] gt_was/14021486841
[18:39:46] [PASSED] gt_was/14025160223
[18:39:46] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[18:39:46] [PASSED] gt_was/14025635424
[18:39:46] [PASSED] gt_was/16028005424
[18:39:46] ============== [PASSED] xe_rtp_table_gt_test ===============
[18:39:46] ================== xe_rtp_table_gt_test ===================
[18:39:46] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[18:39:46] [PASSED] gt_tunings/Tuning: 32B Access Enable
[18:39:46] [PASSED] gt_tunings/Tuning: L3 cache
[18:39:46] [PASSED] gt_tunings/Tuning: L3 cache - media
[18:39:46] [PASSED] gt_tunings/Tuning: Compression Overfetch
[18:39:46] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[18:39:46] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[18:39:46] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[18:39:46] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[18:39:46] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[18:39:46] [PASSED] gt_tunings/Tuning: Stateless compression control
[18:39:46] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[18:39:46] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[18:39:46] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[18:39:46] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[18:39:46] ============== [PASSED] xe_rtp_table_gt_test ===============
[18:39:46] ================== xe_rtp_table_oob_test ==================
[18:39:46] [PASSED] oob_was/1607983814
[18:39:46] [PASSED] oob_was/16010904313
[18:39:46] [PASSED] oob_was/18022495364
[18:39:46] [PASSED] oob_was/22012773006
[18:39:46] [PASSED] oob_was/14014475959
[18:39:46] [PASSED] oob_was/22011391025
[18:39:46] [PASSED] oob_was/22012727170
[18:39:46] [PASSED] oob_was/22012727685
[18:39:46] [PASSED] oob_was/22016596838
[18:39:46] [PASSED] oob_was/18020744125
[18:39:46] [PASSED] oob_was/1409600907
[18:39:46] [PASSED] oob_was/22014953428
[18:39:46] [PASSED] oob_was/16017236439
[18:39:46] [PASSED] oob_was/14019821291
[18:39:46] [PASSED] oob_was/14015076503
[18:39:46] [PASSED] oob_was/14018913170
[18:39:46] [PASSED] oob_was/14018094691
[18:39:46] [PASSED] oob_was/18024947630
[18:39:46] [PASSED] oob_was/16022287689
[18:39:46] [PASSED] oob_was/13011645652
[18:39:46] [PASSED] oob_was/14022293748
[18:39:46] [PASSED] oob_was/22019794406
[18:39:46] [PASSED] oob_was/22019338487
[18:39:46] [PASSED] oob_was/16023588340
[18:39:46] [PASSED] oob_was/14019789679
[18:39:46] [PASSED] oob_was/14022866841
[18:39:46] [PASSED] oob_was/16021333562
[18:39:46] [PASSED] oob_was/14016712196
[18:39:46] [PASSED] oob_was/14015568240
[18:39:46] [PASSED] oob_was/18013179988
[18:39:46] [PASSED] oob_was/1508761755
[18:39:46] [PASSED] oob_was/16023105232
[18:39:46] [PASSED] oob_was/16026508708
[18:39:46] [PASSED] oob_was/14020001231
[18:39:46] [PASSED] oob_was/16023683509
[18:39:46] [PASSED] oob_was/14025515070
[18:39:46] [PASSED] oob_was/15015404425_disable
[18:39:46] [PASSED] oob_was/16026007364
[18:39:46] [PASSED] oob_was/14020316580
[18:39:46] [PASSED] oob_was/14025883347
[18:39:46] [PASSED] oob_was/16029380221
[18:39:46] [PASSED] oob_was/22022079272
[18:39:46] [PASSED] oob_was/16029897822
[18:39:46] [PASSED] oob_was/14027054324
[18:39:46] ============== [PASSED] xe_rtp_table_oob_test ==============
[18:39:46] ================ xe_rtp_table_dev_oob_test ================
[18:39:46] [PASSED] device_oob_was/22010954014
[18:39:46] [PASSED] device_oob_was/15015404425
[18:39:46] [PASSED] device_oob_was/22019338487_display
[18:39:46] [PASSED] device_oob_was/14022085890
[18:39:46] [PASSED] device_oob_was/14026539277
[18:39:46] [PASSED] device_oob_was/14026633728
[18:39:46] [PASSED] device_oob_was/14026746987
[18:39:46] [PASSED] device_oob_was/14026779378
[18:39:46] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[18:39:46] ========== xe_rtp_table_missing_upper_bound_test ==========
[18:39:46] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[18:39:46] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[18:39:46] [PASSED] register_whitelist/1806527549
[18:39:46] [PASSED] register_whitelist/allow_read_ctx_timestamp
[18:39:46] [PASSED] register_whitelist/allow_read_queue_timestamp
[18:39:46] [PASSED] register_whitelist/16014440446
[18:39:46] [PASSED] register_whitelist/16017236439
[18:39:46] [PASSED] register_whitelist/16020183090
[18:39:46] [PASSED] register_whitelist/14024997852
[18:39:46] [PASSED] register_whitelist/14024997852
[18:39:46] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[18:39:46] =============== [PASSED] xe_rtp_tables_test ================
[18:39:46] =================== xe_rtp (3 subtests) ====================
[18:39:46] =================== xe_rtp_rules_tests ====================
[18:39:46] [PASSED] no
[18:39:46] [PASSED] yes
[18:39:46] [PASSED] no-and-no
[18:39:46] [PASSED] no-and-yes
[18:39:46] [PASSED] yes-and-no
[18:39:46] [PASSED] yes-and-yes
[18:39:46] [PASSED] no-or-no
[18:39:46] [PASSED] no-or-yes
[18:39:46] [PASSED] yes-or-no
[18:39:46] [PASSED] yes-or-yes
[18:39:46] [PASSED] no-yes-or-yes-no
[18:39:46] [PASSED] no-yes-or-yes-yes
[18:39:46] [PASSED] yes-yes-or-no-yes
[18:39:46] [PASSED] yes-yes-or-yes-yes
[18:39:46] [PASSED] no-no-or-yes-or-no
[18:39:46] [PASSED] or
[18:39:46] [PASSED] or-yes
[18:39:46] [PASSED] or-no
[18:39:46] [PASSED] yes-or
[18:39:46] [PASSED] no-or
[18:39:46] [PASSED] no-or-or-yes
[18:39:46] [PASSED] yes-or-or-no
[18:39:46] [PASSED] no-or-or-no
[18:39:46] [PASSED] missing-context-engine-class
[18:39:46] [PASSED] missing-context-engine-class-or-yes
[18:39:46] [PASSED] missing-context-engine-class-or-or-yes
[18:39:46] =============== [PASSED] xe_rtp_rules_tests ================
[18:39:46] =============== xe_rtp_process_to_sr_tests ================
[18:39:46] [PASSED] coalesce-same-reg
[18:39:46] [PASSED] coalesce-same-reg-literal-and-func
[18:39:46] [PASSED] no-match-no-add
[18:39:46] [PASSED] two-regs-two-entries
[18:39:46] [PASSED] clr-one-set-other
[18:39:46] [PASSED] set-field
[18:39:46] [PASSED] conflict-duplicate
[18:39:46] [PASSED] conflict-not-disjoint
[18:39:46] [PASSED] conflict-not-disjoint-literal-and-func
[18:39:46] [PASSED] conflict-reg-type
[18:39:46] [PASSED] bad-mcr-reg-forced-to-regular
[18:39:46] [PASSED] bad-regular-reg-forced-to-mcr
[18:39:46] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[18:39:46] ================== xe_rtp_process_tests ===================
[18:39:46] [PASSED] active1
[18:39:46] [PASSED] active2
[18:39:46] [PASSED] active-inactive
[18:39:46] [PASSED] inactive-active
[18:39:46] [PASSED] inactive-active-inactive
[18:39:46] [PASSED] inactive-inactive-inactive
[18:39:46] ============== [PASSED] xe_rtp_process_tests ===============
[18:39:46] ===================== [PASSED] xe_rtp ======================
[18:39:46] ==================== xe_wa (1 subtest) =====================
[18:39:46] ======================== xe_wa_gt =========================
[18:39:46] [PASSED] TIGERLAKE B0
[18:39:46] [PASSED] DG1 A0
[18:39:46] [PASSED] DG1 B0
[18:39:46] [PASSED] ALDERLAKE_S A0
[18:39:46] [PASSED] ALDERLAKE_S B0
[18:39:46] [PASSED] ALDERLAKE_S C0
[18:39:46] [PASSED] ALDERLAKE_S D0
[18:39:46] [PASSED] ALDERLAKE_P A0
[18:39:46] [PASSED] ALDERLAKE_P B0
[18:39:46] [PASSED] ALDERLAKE_P C0
[18:39:46] [PASSED] ALDERLAKE_S RPLS D0
[18:39:46] [PASSED] ALDERLAKE_P RPLU E0
[18:39:46] [PASSED] DG2 G10 C0
[18:39:46] [PASSED] DG2 G11 B1
[18:39:46] [PASSED] DG2 G12 A1
[18:39:46] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[18:39:46] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[18:39:46] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[18:39:46] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[18:39:46] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[18:39:46] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[18:39:46] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[18:39:46] ==================== [PASSED] xe_wa_gt =====================
[18:39:46] ====================== [PASSED] xe_wa ======================
[18:39:46] ============================================================
[18:39:46] Testing complete. Ran 742 tests: passed: 724, skipped: 18
[18:39:46] Elapsed time: 36.755s total, 4.392s configuring, 31.697s building, 0.637s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[18:39:46] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[18:39:48] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[18:40:13] Starting KUnit Kernel (1/1)...
[18:40:13] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[18:40:13] ============ drm_test_pick_cmdline (2 subtests) ============
[18:40:13] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[18:40:13] =============== drm_test_pick_cmdline_named ===============
[18:40:13] [PASSED] NTSC
[18:40:13] [PASSED] NTSC-J
[18:40:13] [PASSED] PAL
[18:40:13] [PASSED] PAL-M
[18:40:13] =========== [PASSED] drm_test_pick_cmdline_named ===========
[18:40:13] ============== [PASSED] drm_test_pick_cmdline ==============
[18:40:13] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[18:40:13] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[18:40:13] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[18:40:13] =========== drm_validate_clone_mode (2 subtests) ===========
[18:40:13] ============== drm_test_check_in_clone_mode ===============
[18:40:13] [PASSED] in_clone_mode
[18:40:13] [PASSED] not_in_clone_mode
[18:40:13] ========== [PASSED] drm_test_check_in_clone_mode ===========
[18:40:13] =============== drm_test_check_valid_clones ===============
[18:40:13] [PASSED] not_in_clone_mode
[18:40:13] [PASSED] valid_clone
[18:40:13] [PASSED] invalid_clone
[18:40:13] =========== [PASSED] drm_test_check_valid_clones ===========
[18:40:13] ============= [PASSED] drm_validate_clone_mode =============
[18:40:13] ============= drm_validate_modeset (1 subtest) =============
[18:40:13] [PASSED] drm_test_check_connector_changed_modeset
[18:40:13] ============== [PASSED] drm_validate_modeset ===============
[18:40:13] ====== drm_test_bridge_get_current_state (1 subtest) =======
[18:40:13] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[18:40:13] ======== [PASSED] drm_test_bridge_get_current_state ========
[18:40:13] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[18:40:13] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[18:40:13] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[18:40:13] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[18:40:13] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[18:40:13] ============== drm_bridge_alloc (2 subtests) ===============
[18:40:13] [PASSED] drm_test_drm_bridge_alloc_basic
[18:40:13] [PASSED] drm_test_drm_bridge_alloc_get_put
[18:40:13] ================ [PASSED] drm_bridge_alloc =================
[18:40:13] ============= drm_bridge_bus_fmt (5 subtests) ==============
[18:40:13] [PASSED] drm_test_bridge_rgb_yuv_rgb
[18:40:13] [PASSED] drm_test_bridge_must_convert_to_yuv444
[18:40:13] [PASSED] drm_test_bridge_hdmi_auto_rgb
[18:40:13] [PASSED] drm_test_bridge_auto_first
[18:40:13] [PASSED] drm_test_bridge_rgb_yuv_no_path
[18:40:13] =============== [PASSED] drm_bridge_bus_fmt ================
[18:40:13] ============= drm_cmdline_parser (40 subtests) =============
[18:40:13] [PASSED] drm_test_cmdline_force_d_only
[18:40:13] [PASSED] drm_test_cmdline_force_D_only_dvi
[18:40:13] [PASSED] drm_test_cmdline_force_D_only_hdmi
[18:40:13] [PASSED] drm_test_cmdline_force_D_only_not_digital
[18:40:13] [PASSED] drm_test_cmdline_force_e_only
[18:40:13] [PASSED] drm_test_cmdline_res
[18:40:13] [PASSED] drm_test_cmdline_res_vesa
[18:40:13] [PASSED] drm_test_cmdline_res_vesa_rblank
[18:40:13] [PASSED] drm_test_cmdline_res_rblank
[18:40:13] [PASSED] drm_test_cmdline_res_bpp
[18:40:13] [PASSED] drm_test_cmdline_res_refresh
[18:40:13] [PASSED] drm_test_cmdline_res_bpp_refresh
[18:40:13] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[18:40:13] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[18:40:13] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[18:40:13] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[18:40:13] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[18:40:13] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[18:40:13] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[18:40:13] [PASSED] drm_test_cmdline_res_margins_force_on
[18:40:13] [PASSED] drm_test_cmdline_res_vesa_margins
[18:40:13] [PASSED] drm_test_cmdline_name
[18:40:13] [PASSED] drm_test_cmdline_name_bpp
[18:40:13] [PASSED] drm_test_cmdline_name_option
[18:40:13] [PASSED] drm_test_cmdline_name_bpp_option
[18:40:13] [PASSED] drm_test_cmdline_rotate_0
[18:40:13] [PASSED] drm_test_cmdline_rotate_90
[18:40:13] [PASSED] drm_test_cmdline_rotate_180
[18:40:13] [PASSED] drm_test_cmdline_rotate_270
[18:40:13] [PASSED] drm_test_cmdline_hmirror
[18:40:13] [PASSED] drm_test_cmdline_vmirror
[18:40:13] [PASSED] drm_test_cmdline_margin_options
[18:40:13] [PASSED] drm_test_cmdline_multiple_options
[18:40:13] [PASSED] drm_test_cmdline_bpp_extra_and_option
[18:40:13] [PASSED] drm_test_cmdline_extra_and_option
[18:40:13] [PASSED] drm_test_cmdline_freestanding_options
[18:40:13] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[18:40:13] [PASSED] drm_test_cmdline_panel_orientation
[18:40:13] ================ drm_test_cmdline_invalid =================
[18:40:13] [PASSED] margin_only
[18:40:13] [PASSED] interlace_only
[18:40:13] [PASSED] res_missing_x
[18:40:13] [PASSED] res_missing_y
[18:40:13] [PASSED] res_bad_y
[18:40:13] [PASSED] res_missing_y_bpp
[18:40:13] [PASSED] res_bad_bpp
[18:40:13] [PASSED] res_bad_refresh
[18:40:13] [PASSED] res_bpp_refresh_force_on_off
[18:40:13] [PASSED] res_invalid_mode
[18:40:13] [PASSED] res_bpp_wrong_place_mode
[18:40:13] [PASSED] name_bpp_refresh
[18:40:13] [PASSED] name_refresh
[18:40:13] [PASSED] name_refresh_wrong_mode
[18:40:13] [PASSED] name_refresh_invalid_mode
[18:40:13] [PASSED] rotate_multiple
[18:40:13] [PASSED] rotate_invalid_val
[18:40:13] [PASSED] rotate_truncated
[18:40:13] [PASSED] invalid_option
[18:40:13] [PASSED] invalid_tv_option
[18:40:13] [PASSED] truncated_tv_option
[18:40:13] ============ [PASSED] drm_test_cmdline_invalid =============
[18:40:13] =============== drm_test_cmdline_tv_options ===============
[18:40:13] [PASSED] NTSC
[18:40:13] [PASSED] NTSC_443
[18:40:13] [PASSED] NTSC_J
[18:40:13] [PASSED] PAL
[18:40:13] [PASSED] PAL_M
[18:40:13] [PASSED] PAL_N
[18:40:13] [PASSED] SECAM
[18:40:13] [PASSED] MONO_525
[18:40:13] [PASSED] MONO_625
[18:40:13] =========== [PASSED] drm_test_cmdline_tv_options ===========
[18:40:13] =============== [PASSED] drm_cmdline_parser ================
[18:40:13] ========== drmm_connector_hdmi_init (20 subtests) ==========
[18:40:13] [PASSED] drm_test_connector_hdmi_init_valid
[18:40:13] [PASSED] drm_test_connector_hdmi_init_bpc_8
[18:40:13] [PASSED] drm_test_connector_hdmi_init_bpc_10
[18:40:13] [PASSED] drm_test_connector_hdmi_init_bpc_12
[18:40:13] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[18:40:13] [PASSED] drm_test_connector_hdmi_init_bpc_null
[18:40:13] [PASSED] drm_test_connector_hdmi_init_formats_empty
[18:40:13] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[18:40:13] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[18:40:13] [PASSED] supported_formats=0x9 yuv420_allowed=1
[18:40:13] [PASSED] supported_formats=0x9 yuv420_allowed=0
[18:40:13] [PASSED] supported_formats=0x5 yuv420_allowed=1
[18:40:13] [PASSED] supported_formats=0x5 yuv420_allowed=0
[18:40:13] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[18:40:13] [PASSED] drm_test_connector_hdmi_init_null_ddc
[18:40:13] [PASSED] drm_test_connector_hdmi_init_null_product
[18:40:13] [PASSED] drm_test_connector_hdmi_init_null_vendor
[18:40:13] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[18:40:13] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[18:40:13] [PASSED] drm_test_connector_hdmi_init_product_valid
[18:40:13] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[18:40:13] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[18:40:13] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[18:40:13] ========= drm_test_connector_hdmi_init_type_valid =========
[18:40:13] [PASSED] HDMI-A
[18:40:13] [PASSED] HDMI-B
[18:40:13] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[18:40:13] ======== drm_test_connector_hdmi_init_type_invalid ========
[18:40:13] [PASSED] Unknown
[18:40:13] [PASSED] VGA
[18:40:13] [PASSED] DVI-I
[18:40:13] [PASSED] DVI-D
[18:40:13] [PASSED] DVI-A
[18:40:13] [PASSED] Composite
[18:40:13] [PASSED] SVIDEO
[18:40:13] [PASSED] LVDS
[18:40:13] [PASSED] Component
[18:40:13] [PASSED] DIN
[18:40:13] [PASSED] DP
[18:40:13] [PASSED] TV
[18:40:13] [PASSED] eDP
[18:40:13] [PASSED] Virtual
[18:40:13] [PASSED] DSI
[18:40:13] [PASSED] DPI
[18:40:13] [PASSED] Writeback
[18:40:13] [PASSED] SPI
[18:40:13] [PASSED] USB
[18:40:13] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[18:40:13] ============ [PASSED] drmm_connector_hdmi_init =============
[18:40:13] ============= drmm_connector_init (3 subtests) =============
[18:40:13] [PASSED] drm_test_drmm_connector_init
[18:40:13] [PASSED] drm_test_drmm_connector_init_null_ddc
[18:40:13] ========= drm_test_drmm_connector_init_type_valid =========
[18:40:13] [PASSED] Unknown
[18:40:13] [PASSED] VGA
[18:40:13] [PASSED] DVI-I
[18:40:13] [PASSED] DVI-D
[18:40:13] [PASSED] DVI-A
[18:40:13] [PASSED] Composite
[18:40:13] [PASSED] SVIDEO
[18:40:13] [PASSED] LVDS
[18:40:13] [PASSED] Component
[18:40:13] [PASSED] DIN
[18:40:13] [PASSED] DP
[18:40:13] [PASSED] HDMI-A
[18:40:13] [PASSED] HDMI-B
[18:40:13] [PASSED] TV
[18:40:13] [PASSED] eDP
[18:40:13] [PASSED] Virtual
[18:40:13] [PASSED] DSI
[18:40:13] [PASSED] DPI
[18:40:13] [PASSED] Writeback
[18:40:13] [PASSED] SPI
[18:40:13] [PASSED] USB
[18:40:13] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[18:40:13] =============== [PASSED] drmm_connector_init ===============
[18:40:13] ========= drm_connector_dynamic_init (6 subtests) ==========
[18:40:13] [PASSED] drm_test_drm_connector_dynamic_init
[18:40:13] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[18:40:13] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[18:40:13] [PASSED] drm_test_drm_connector_dynamic_init_properties
[18:40:13] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[18:40:13] [PASSED] Unknown
[18:40:13] [PASSED] VGA
[18:40:13] [PASSED] DVI-I
[18:40:13] [PASSED] DVI-D
[18:40:13] [PASSED] DVI-A
[18:40:13] [PASSED] Composite
[18:40:13] [PASSED] SVIDEO
[18:40:13] [PASSED] LVDS
[18:40:13] [PASSED] Component
[18:40:13] [PASSED] DIN
[18:40:13] [PASSED] DP
[18:40:13] [PASSED] HDMI-A
[18:40:13] [PASSED] HDMI-B
[18:40:13] [PASSED] TV
[18:40:13] [PASSED] eDP
[18:40:13] [PASSED] Virtual
[18:40:13] [PASSED] DSI
[18:40:13] [PASSED] DPI
[18:40:13] [PASSED] Writeback
[18:40:13] [PASSED] SPI
[18:40:13] [PASSED] USB
[18:40:13] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[18:40:13] ======== drm_test_drm_connector_dynamic_init_name =========
[18:40:13] [PASSED] Unknown
[18:40:13] [PASSED] VGA
[18:40:13] [PASSED] DVI-I
[18:40:13] [PASSED] DVI-D
[18:40:13] [PASSED] DVI-A
[18:40:13] [PASSED] Composite
[18:40:13] [PASSED] SVIDEO
[18:40:13] [PASSED] LVDS
[18:40:13] [PASSED] Component
[18:40:13] [PASSED] DIN
[18:40:13] [PASSED] DP
[18:40:13] [PASSED] HDMI-A
[18:40:13] [PASSED] HDMI-B
[18:40:13] [PASSED] TV
[18:40:13] [PASSED] eDP
[18:40:13] [PASSED] Virtual
[18:40:13] [PASSED] DSI
[18:40:13] [PASSED] DPI
[18:40:13] [PASSED] Writeback
[18:40:13] [PASSED] SPI
[18:40:13] [PASSED] USB
[18:40:13] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[18:40:13] =========== [PASSED] drm_connector_dynamic_init ============
[18:40:13] ==== drm_connector_dynamic_register_early (4 subtests) =====
[18:40:13] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[18:40:13] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[18:40:13] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[18:40:13] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[18:40:13] ====== [PASSED] drm_connector_dynamic_register_early =======
[18:40:13] ======= drm_connector_dynamic_register (7 subtests) ========
[18:40:13] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[18:40:13] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[18:40:13] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[18:40:13] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[18:40:13] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[18:40:13] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[18:40:13] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[18:40:13] ========= [PASSED] drm_connector_dynamic_register ==========
[18:40:13] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[18:40:13] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[18:40:13] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[18:40:13] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[18:40:13] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[18:40:13] ========== drm_test_get_tv_mode_from_name_valid ===========
[18:40:13] [PASSED] NTSC
[18:40:13] [PASSED] NTSC-443
[18:40:13] [PASSED] NTSC-J
[18:40:13] [PASSED] PAL
[18:40:13] [PASSED] PAL-M
[18:40:13] [PASSED] PAL-N
[18:40:13] [PASSED] SECAM
[18:40:13] [PASSED] Mono
[18:40:13] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[18:40:13] [PASSED] drm_test_get_tv_mode_from_name_truncated
[18:40:13] ============ [PASSED] drm_get_tv_mode_from_name ============
[18:40:13] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[18:40:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[18:40:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[18:40:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[18:40:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[18:40:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[18:40:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[18:40:13] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[18:40:13] [PASSED] VIC 96
[18:40:13] [PASSED] VIC 97
[18:40:13] [PASSED] VIC 101
[18:40:13] [PASSED] VIC 102
[18:40:13] [PASSED] VIC 106
[18:40:13] [PASSED] VIC 107
[18:40:13] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[18:40:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[18:40:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[18:40:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[18:40:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[18:40:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[18:40:13] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[18:40:13] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[18:40:13] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[18:40:13] [PASSED] Automatic
[18:40:13] [PASSED] Full
[18:40:13] [PASSED] Limited 16:235
[18:40:13] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[18:40:13] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[18:40:13] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[18:40:13] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[18:40:13] === drm_test_drm_hdmi_connector_get_output_format_name ====
[18:40:13] [PASSED] RGB
[18:40:13] [PASSED] YUV 4:2:0
[18:40:13] [PASSED] YUV 4:2:2
[18:40:13] [PASSED] YUV 4:4:4
[18:40:13] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[18:40:13] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[18:40:13] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[18:40:13] ============= drm_damage_helper (21 subtests) ==============
[18:40:13] [PASSED] drm_test_damage_iter_no_damage
[18:40:13] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[18:40:13] [PASSED] drm_test_damage_iter_no_damage_src_moved
[18:40:13] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[18:40:13] [PASSED] drm_test_damage_iter_no_damage_not_visible
[18:40:13] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[18:40:13] [PASSED] drm_test_damage_iter_no_damage_no_fb
[18:40:13] [PASSED] drm_test_damage_iter_simple_damage
[18:40:13] [PASSED] drm_test_damage_iter_single_damage
[18:40:13] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[18:40:13] [PASSED] drm_test_damage_iter_single_damage_outside_src
[18:40:13] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[18:40:13] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[18:40:13] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[18:40:13] [PASSED] drm_test_damage_iter_single_damage_src_moved
[18:40:13] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[18:40:13] [PASSED] drm_test_damage_iter_damage
[18:40:13] [PASSED] drm_test_damage_iter_damage_one_intersect
[18:40:13] [PASSED] drm_test_damage_iter_damage_one_outside
[18:40:13] [PASSED] drm_test_damage_iter_damage_src_moved
[18:40:13] [PASSED] drm_test_damage_iter_damage_not_visible
[18:40:13] ================ [PASSED] drm_damage_helper ================
[18:40:13] ============== drm_dp_mst_helper (3 subtests) ==============
[18:40:13] ============== drm_test_dp_mst_calc_pbn_mode ==============
[18:40:13] [PASSED] Clock 154000 BPP 30 DSC disabled
[18:40:13] [PASSED] Clock 234000 BPP 30 DSC disabled
[18:40:13] [PASSED] Clock 297000 BPP 24 DSC disabled
[18:40:13] [PASSED] Clock 332880 BPP 24 DSC enabled
[18:40:13] [PASSED] Clock 324540 BPP 24 DSC enabled
[18:40:13] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[18:40:13] ============== drm_test_dp_mst_calc_pbn_div ===============
[18:40:13] [PASSED] Link rate 2000000 lane count 4
[18:40:13] [PASSED] Link rate 2000000 lane count 2
[18:40:13] [PASSED] Link rate 2000000 lane count 1
[18:40:13] [PASSED] Link rate 1350000 lane count 4
[18:40:13] [PASSED] Link rate 1350000 lane count 2
[18:40:13] [PASSED] Link rate 1350000 lane count 1
[18:40:13] [PASSED] Link rate 1000000 lane count 4
[18:40:13] [PASSED] Link rate 1000000 lane count 2
[18:40:13] [PASSED] Link rate 1000000 lane count 1
[18:40:13] [PASSED] Link rate 810000 lane count 4
[18:40:13] [PASSED] Link rate 810000 lane count 2
[18:40:13] [PASSED] Link rate 810000 lane count 1
[18:40:13] [PASSED] Link rate 540000 lane count 4
[18:40:13] [PASSED] Link rate 540000 lane count 2
[18:40:13] [PASSED] Link rate 540000 lane count 1
[18:40:13] [PASSED] Link rate 270000 lane count 4
[18:40:13] [PASSED] Link rate 270000 lane count 2
[18:40:13] [PASSED] Link rate 270000 lane count 1
[18:40:13] [PASSED] Link rate 162000 lane count 4
[18:40:13] [PASSED] Link rate 162000 lane count 2
[18:40:13] [PASSED] Link rate 162000 lane count 1
[18:40:13] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[18:40:13] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[18:40:13] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[18:40:13] [PASSED] DP_POWER_UP_PHY with port number
[18:40:13] [PASSED] DP_POWER_DOWN_PHY with port number
[18:40:13] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[18:40:13] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[18:40:13] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[18:40:13] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[18:40:13] [PASSED] DP_QUERY_PAYLOAD with port number
[18:40:13] [PASSED] DP_QUERY_PAYLOAD with VCPI
[18:40:13] [PASSED] DP_REMOTE_DPCD_READ with port number
[18:40:13] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[18:40:13] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[18:40:13] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[18:40:13] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[18:40:13] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[18:40:13] [PASSED] DP_REMOTE_I2C_READ with port number
[18:40:13] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[18:40:13] [PASSED] DP_REMOTE_I2C_READ with transactions array
[18:40:13] [PASSED] DP_REMOTE_I2C_WRITE with port number
[18:40:13] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[18:40:13] [PASSED] DP_REMOTE_I2C_WRITE with data array
[18:40:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[18:40:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[18:40:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[18:40:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[18:40:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[18:40:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[18:40:13] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[18:40:13] ================ [PASSED] drm_dp_mst_helper ================
[18:40:13] ================== drm_exec (7 subtests) ===================
[18:40:13] [PASSED] sanitycheck
[18:40:13] [PASSED] test_lock
[18:40:13] [PASSED] test_lock_unlock
[18:40:13] [PASSED] test_duplicates
[18:40:13] [PASSED] test_prepare
[18:40:13] [PASSED] test_prepare_array
[18:40:13] [PASSED] test_multiple_loops
[18:40:13] ==================== [PASSED] drm_exec =====================
[18:40:13] =========== drm_format_helper_test (17 subtests) ===========
[18:40:13] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[18:40:13] [PASSED] single_pixel_source_buffer
[18:40:13] [PASSED] single_pixel_clip_rectangle
[18:40:13] [PASSED] well_known_colors
[18:40:13] [PASSED] destination_pitch
[18:40:13] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[18:40:13] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[18:40:13] [PASSED] single_pixel_source_buffer
[18:40:13] [PASSED] single_pixel_clip_rectangle
[18:40:13] [PASSED] well_known_colors
[18:40:13] [PASSED] destination_pitch
[18:40:13] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[18:40:13] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[18:40:13] [PASSED] single_pixel_source_buffer
[18:40:13] [PASSED] single_pixel_clip_rectangle
[18:40:13] [PASSED] well_known_colors
[18:40:13] [PASSED] destination_pitch
[18:40:13] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[18:40:13] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[18:40:13] [PASSED] single_pixel_source_buffer
[18:40:13] [PASSED] single_pixel_clip_rectangle
[18:40:13] [PASSED] well_known_colors
[18:40:13] [PASSED] destination_pitch
[18:40:13] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[18:40:13] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[18:40:13] [PASSED] single_pixel_source_buffer
[18:40:13] [PASSED] single_pixel_clip_rectangle
[18:40:13] [PASSED] well_known_colors
[18:40:13] [PASSED] destination_pitch
[18:40:13] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[18:40:13] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[18:40:13] [PASSED] single_pixel_source_buffer
[18:40:13] [PASSED] single_pixel_clip_rectangle
[18:40:13] [PASSED] well_known_colors
[18:40:13] [PASSED] destination_pitch
[18:40:13] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[18:40:13] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[18:40:13] [PASSED] single_pixel_source_buffer
[18:40:13] [PASSED] single_pixel_clip_rectangle
[18:40:13] [PASSED] well_known_colors
[18:40:13] [PASSED] destination_pitch
[18:40:13] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[18:40:13] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[18:40:13] [PASSED] single_pixel_source_buffer
[18:40:13] [PASSED] single_pixel_clip_rectangle
[18:40:13] [PASSED] well_known_colors
[18:40:13] [PASSED] destination_pitch
[18:40:13] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[18:40:13] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[18:40:13] [PASSED] single_pixel_source_buffer
[18:40:13] [PASSED] single_pixel_clip_rectangle
[18:40:13] [PASSED] well_known_colors
[18:40:13] [PASSED] destination_pitch
[18:40:13] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[18:40:13] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[18:40:13] [PASSED] single_pixel_source_buffer
[18:40:13] [PASSED] single_pixel_clip_rectangle
[18:40:13] [PASSED] well_known_colors
[18:40:13] [PASSED] destination_pitch
[18:40:13] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[18:40:13] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[18:40:13] [PASSED] single_pixel_source_buffer
[18:40:13] [PASSED] single_pixel_clip_rectangle
[18:40:13] [PASSED] well_known_colors
[18:40:13] [PASSED] destination_pitch
[18:40:13] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[18:40:13] ============== drm_test_fb_xrgb8888_to_mono ===============
[18:40:13] [PASSED] single_pixel_source_buffer
[18:40:13] [PASSED] single_pixel_clip_rectangle
[18:40:13] [PASSED] well_known_colors
[18:40:13] [PASSED] destination_pitch
[18:40:13] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[18:40:13] ==================== drm_test_fb_swab =====================
[18:40:13] [PASSED] single_pixel_source_buffer
[18:40:13] [PASSED] single_pixel_clip_rectangle
[18:40:13] [PASSED] well_known_colors
[18:40:13] [PASSED] destination_pitch
[18:40:13] ================ [PASSED] drm_test_fb_swab =================
[18:40:13] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[18:40:13] [PASSED] single_pixel_source_buffer
[18:40:13] [PASSED] single_pixel_clip_rectangle
[18:40:13] [PASSED] well_known_colors
[18:40:13] [PASSED] destination_pitch
[18:40:13] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[18:40:13] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[18:40:13] [PASSED] single_pixel_source_buffer
[18:40:13] [PASSED] single_pixel_clip_rectangle
[18:40:13] [PASSED] well_known_colors
[18:40:13] [PASSED] destination_pitch
[18:40:13] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[18:40:13] ================= drm_test_fb_clip_offset =================
[18:40:13] [PASSED] pass through
[18:40:13] [PASSED] horizontal offset
[18:40:13] [PASSED] vertical offset
[18:40:13] [PASSED] horizontal and vertical offset
[18:40:13] [PASSED] horizontal offset (custom pitch)
[18:40:13] [PASSED] vertical offset (custom pitch)
[18:40:13] [PASSED] horizontal and vertical offset (custom pitch)
[18:40:13] ============= [PASSED] drm_test_fb_clip_offset =============
[18:40:13] =================== drm_test_fb_memcpy ====================
[18:40:13] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[18:40:13] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[18:40:13] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[18:40:13] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[18:40:13] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[18:40:13] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[18:40:13] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[18:40:13] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[18:40:13] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[18:40:13] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[18:40:13] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[18:40:13] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[18:40:13] =============== [PASSED] drm_test_fb_memcpy ================
[18:40:13] ============= [PASSED] drm_format_helper_test ==============
[18:40:13] ================= drm_format (18 subtests) =================
[18:40:13] [PASSED] drm_test_format_block_width_invalid
[18:40:13] [PASSED] drm_test_format_block_width_one_plane
[18:40:13] [PASSED] drm_test_format_block_width_two_plane
[18:40:13] [PASSED] drm_test_format_block_width_three_plane
[18:40:13] [PASSED] drm_test_format_block_width_tiled
[18:40:13] [PASSED] drm_test_format_block_height_invalid
[18:40:13] [PASSED] drm_test_format_block_height_one_plane
[18:40:13] [PASSED] drm_test_format_block_height_two_plane
[18:40:13] [PASSED] drm_test_format_block_height_three_plane
[18:40:13] [PASSED] drm_test_format_block_height_tiled
[18:40:13] [PASSED] drm_test_format_min_pitch_invalid
[18:40:13] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[18:40:13] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[18:40:13] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[18:40:13] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[18:40:13] [PASSED] drm_test_format_min_pitch_two_plane
[18:40:13] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[18:40:13] [PASSED] drm_test_format_min_pitch_tiled
[18:40:13] =================== [PASSED] drm_format ====================
[18:40:13] ============== drm_framebuffer (10 subtests) ===============
[18:40:13] ========== drm_test_framebuffer_check_src_coords ==========
[18:40:13] [PASSED] Success: source fits into fb
[18:40:13] [PASSED] Fail: overflowing fb with x-axis coordinate
[18:40:13] [PASSED] Fail: overflowing fb with y-axis coordinate
[18:40:13] [PASSED] Fail: overflowing fb with source width
[18:40:13] [PASSED] Fail: overflowing fb with source height
[18:40:13] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[18:40:13] [PASSED] drm_test_framebuffer_cleanup
[18:40:13] =============== drm_test_framebuffer_create ===============
[18:40:13] [PASSED] ABGR8888 normal sizes
[18:40:13] [PASSED] ABGR8888 max sizes
[18:40:13] [PASSED] ABGR8888 pitch greater than min required
[18:40:13] [PASSED] ABGR8888 pitch less than min required
[18:40:13] [PASSED] ABGR8888 Invalid width
[18:40:13] [PASSED] ABGR8888 Invalid buffer handle
[18:40:13] [PASSED] No pixel format
[18:40:13] [PASSED] ABGR8888 Width 0
[18:40:13] [PASSED] ABGR8888 Height 0
[18:40:13] [PASSED] ABGR8888 Out of bound height * pitch combination
[18:40:13] [PASSED] ABGR8888 Large buffer offset
[18:40:13] [PASSED] ABGR8888 Buffer offset for inexistent plane
[18:40:13] [PASSED] ABGR8888 Invalid flag
[18:40:13] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[18:40:13] [PASSED] ABGR8888 Valid buffer modifier
[18:40:13] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[18:40:13] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[18:40:13] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[18:40:13] [PASSED] NV12 Normal sizes
[18:40:13] [PASSED] NV12 Max sizes
[18:40:13] [PASSED] NV12 Invalid pitch
[18:40:13] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[18:40:13] [PASSED] NV12 different modifier per-plane
[18:40:13] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[18:40:13] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[18:40:13] [PASSED] NV12 Modifier for inexistent plane
[18:40:13] [PASSED] NV12 Handle for inexistent plane
[18:40:13] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[18:40:13] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[18:40:13] [PASSED] YVU420 Normal sizes
[18:40:13] [PASSED] YVU420 Max sizes
[18:40:13] [PASSED] YVU420 Invalid pitch
[18:40:13] [PASSED] YVU420 Different pitches
[18:40:13] [PASSED] YVU420 Different buffer offsets/pitches
[18:40:13] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[18:40:13] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[18:40:13] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[18:40:13] [PASSED] YVU420 Valid modifier
[18:40:13] [PASSED] YVU420 Different modifiers per plane
[18:40:13] [PASSED] YVU420 Modifier for inexistent plane
[18:40:13] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[18:40:13] [PASSED] X0L2 Normal sizes
[18:40:13] [PASSED] X0L2 Max sizes
[18:40:13] [PASSED] X0L2 Invalid pitch
[18:40:13] [PASSED] X0L2 Pitch greater than minimum required
[18:40:13] [PASSED] X0L2 Handle for inexistent plane
[18:40:13] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[18:40:13] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[18:40:13] [PASSED] X0L2 Valid modifier
[18:40:13] [PASSED] X0L2 Modifier for inexistent plane
[18:40:13] =========== [PASSED] drm_test_framebuffer_create ===========
[18:40:13] [PASSED] drm_test_framebuffer_free
[18:40:13] [PASSED] drm_test_framebuffer_init
[18:40:13] [PASSED] drm_test_framebuffer_init_bad_format
[18:40:13] [PASSED] drm_test_framebuffer_init_dev_mismatch
[18:40:13] [PASSED] drm_test_framebuffer_lookup
[18:40:13] [PASSED] drm_test_framebuffer_lookup_inexistent
[18:40:13] [PASSED] drm_test_framebuffer_modifiers_not_supported
[18:40:13] ================= [PASSED] drm_framebuffer =================
[18:40:13] ================ drm_gem_shmem (8 subtests) ================
[18:40:13] [PASSED] drm_gem_shmem_test_obj_create
[18:40:13] [PASSED] drm_gem_shmem_test_obj_create_private
[18:40:13] [PASSED] drm_gem_shmem_test_pin_pages
[18:40:13] [PASSED] drm_gem_shmem_test_vmap
[18:40:13] [PASSED] drm_gem_shmem_test_get_sg_table
[18:40:13] [PASSED] drm_gem_shmem_test_get_pages_sgt
[18:40:13] [PASSED] drm_gem_shmem_test_madvise
[18:40:13] [PASSED] drm_gem_shmem_test_purge
[18:40:13] ================== [PASSED] drm_gem_shmem ==================
[18:40:13] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[18:40:13] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[18:40:13] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[18:40:13] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[18:40:13] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[18:40:13] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[18:40:13] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[18:40:13] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[18:40:13] [PASSED] Automatic
[18:40:13] [PASSED] Full
[18:40:13] [PASSED] Limited 16:235
[18:40:13] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[18:40:13] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[18:40:13] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[18:40:13] [PASSED] drm_test_check_disable_connector
[18:40:13] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[18:40:13] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[18:40:13] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[18:40:13] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[18:40:13] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[18:40:13] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[18:40:13] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[18:40:13] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[18:40:13] [PASSED] drm_test_check_output_bpc_dvi
[18:40:13] [PASSED] drm_test_check_output_bpc_format_vic_1
[18:40:13] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[18:40:13] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[18:40:13] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[18:40:13] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[18:40:13] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[18:40:13] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[18:40:13] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[18:40:13] ============ drm_test_check_hdmi_color_format =============
[18:40:13] [PASSED] AUTO -> RGB
[18:40:13] [PASSED] YCBCR422 -> YUV422
[18:40:13] [PASSED] YCBCR420 -> YUV420
[18:40:13] [PASSED] YCBCR444 -> YUV444
[18:40:13] [PASSED] RGB -> RGB
[18:40:13] ======== [PASSED] drm_test_check_hdmi_color_format =========
[18:40:13] ======== drm_test_check_hdmi_color_format_420_only ========
[18:40:13] [PASSED] RGB should fail
[18:40:13] [PASSED] YUV444 should fail
[18:40:13] [PASSED] YUV422 should fail
[18:40:13] [PASSED] YUV420 should work
[18:40:13] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[18:40:13] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[18:40:13] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[18:40:13] [PASSED] drm_test_check_broadcast_rgb_value
[18:40:13] [PASSED] drm_test_check_bpc_8_value
[18:40:13] [PASSED] drm_test_check_bpc_10_value
[18:40:13] [PASSED] drm_test_check_bpc_12_value
[18:40:13] [PASSED] drm_test_check_format_value
[18:40:13] [PASSED] drm_test_check_tmds_char_value
[18:40:13] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[18:40:13] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[18:40:13] [PASSED] drm_test_check_mode_valid
[18:40:13] [PASSED] drm_test_check_mode_valid_reject
[18:40:13] [PASSED] drm_test_check_mode_valid_reject_rate
[18:40:13] [PASSED] drm_test_check_mode_valid_reject_max_clock
[18:40:13] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[18:40:13] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[18:40:13] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[18:40:13] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[18:40:13] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[18:40:13] [PASSED] drm_test_check_infoframes
[18:40:13] [PASSED] drm_test_check_reject_avi_infoframe
[18:40:13] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[18:40:13] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[18:40:13] [PASSED] drm_test_check_reject_audio_infoframe
[18:40:13] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[18:40:13] ================= drm_managed (2 subtests) =================
[18:40:13] [PASSED] drm_test_managed_release_action
[18:40:13] [PASSED] drm_test_managed_run_action
[18:40:13] =================== [PASSED] drm_managed ===================
[18:40:13] =================== drm_mm (6 subtests) ====================
[18:40:13] [PASSED] drm_test_mm_init
[18:40:13] [PASSED] drm_test_mm_debug
[18:40:13] [PASSED] drm_test_mm_align32
[18:40:13] [PASSED] drm_test_mm_align64
[18:40:13] [PASSED] drm_test_mm_lowest
[18:40:13] [PASSED] drm_test_mm_highest
[18:40:13] ===================== [PASSED] drm_mm ======================
[18:40:13] ============= drm_modes_analog_tv (5 subtests) =============
[18:40:13] [PASSED] drm_test_modes_analog_tv_mono_576i
[18:40:13] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[18:40:13] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[18:40:13] [PASSED] drm_test_modes_analog_tv_pal_576i
[18:40:13] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[18:40:13] =============== [PASSED] drm_modes_analog_tv ===============
[18:40:13] ============== drm_plane_helper (2 subtests) ===============
[18:40:13] =============== drm_test_check_plane_state ================
[18:40:13] [PASSED] clipping_simple
[18:40:13] [PASSED] clipping_rotate_reflect
[18:40:13] [PASSED] positioning_simple
[18:40:13] [PASSED] upscaling
[18:40:13] [PASSED] downscaling
[18:40:13] [PASSED] rounding1
[18:40:13] [PASSED] rounding2
[18:40:13] [PASSED] rounding3
[18:40:13] [PASSED] rounding4
[18:40:13] =========== [PASSED] drm_test_check_plane_state ============
[18:40:13] =========== drm_test_check_invalid_plane_state ============
[18:40:13] [PASSED] positioning_invalid
[18:40:13] [PASSED] upscaling_invalid
[18:40:13] [PASSED] downscaling_invalid
[18:40:13] ======= [PASSED] drm_test_check_invalid_plane_state ========
[18:40:13] ================ [PASSED] drm_plane_helper =================
[18:40:13] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[18:40:13] ====== drm_test_connector_helper_tv_get_modes_check =======
[18:40:13] [PASSED] None
[18:40:13] [PASSED] PAL
[18:40:13] [PASSED] NTSC
[18:40:13] [PASSED] Both, NTSC Default
[18:40:13] [PASSED] Both, PAL Default
[18:40:13] [PASSED] Both, NTSC Default, with PAL on command-line
[18:40:13] [PASSED] Both, PAL Default, with NTSC on command-line
[18:40:13] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[18:40:13] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[18:40:13] ================== drm_rect (9 subtests) ===================
[18:40:13] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[18:40:13] [PASSED] drm_test_rect_clip_scaled_not_clipped
[18:40:13] [PASSED] drm_test_rect_clip_scaled_clipped
[18:40:13] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[18:40:13] ================= drm_test_rect_intersect =================
[18:40:13] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[18:40:13] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[18:40:13] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[18:40:13] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[18:40:13] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[18:40:13] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[18:40:13] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[18:40:13] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[18:40:13] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[18:40:13] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[18:40:13] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[18:40:13] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[18:40:13] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[18:40:13] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[18:40:13] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[18:40:13] ============= [PASSED] drm_test_rect_intersect =============
[18:40:13] ================ drm_test_rect_calc_hscale ================
[18:40:13] [PASSED] normal use
[18:40:13] [PASSED] out of max range
[18:40:13] [PASSED] out of min range
[18:40:13] [PASSED] zero dst
[18:40:13] [PASSED] negative src
[18:40:13] [PASSED] negative dst
[18:40:13] ============ [PASSED] drm_test_rect_calc_hscale ============
[18:40:13] ================ drm_test_rect_calc_vscale ================
[18:40:13] [PASSED] normal use
[18:40:13] [PASSED] out of max range
[18:40:13] [PASSED] out of min range
[18:40:13] [PASSED] zero dst
[18:40:13] [PASSED] negative src
[18:40:13] [PASSED] negative dst
[18:40:13] ============ [PASSED] drm_test_rect_calc_vscale ============
[18:40:13] ================== drm_test_rect_rotate ===================
[18:40:13] [PASSED] reflect-x
[18:40:13] [PASSED] reflect-y
[18:40:13] [PASSED] rotate-0
[18:40:13] [PASSED] rotate-90
[18:40:13] [PASSED] rotate-180
[18:40:13] [PASSED] rotate-270
[18:40:13] ============== [PASSED] drm_test_rect_rotate ===============
[18:40:13] ================ drm_test_rect_rotate_inv =================
[18:40:13] [PASSED] reflect-x
[18:40:13] [PASSED] reflect-y
[18:40:13] [PASSED] rotate-0
[18:40:13] [PASSED] rotate-90
[18:40:13] [PASSED] rotate-180
[18:40:13] [PASSED] rotate-270
[18:40:13] ============ [PASSED] drm_test_rect_rotate_inv =============
[18:40:13] ==================== [PASSED] drm_rect =====================
[18:40:13] ============ drm_sysfb_modeset_test (1 subtest) ============
[18:40:13] ============ drm_test_sysfb_build_fourcc_list =============
[18:40:13] [PASSED] no native formats
[18:40:13] [PASSED] XRGB8888 as native format
[18:40:13] [PASSED] remove duplicates
[18:40:13] [PASSED] convert alpha formats
[18:40:13] [PASSED] random formats
[18:40:13] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[18:40:13] ============= [PASSED] drm_sysfb_modeset_test ==============
[18:40:13] ================== drm_fixp (2 subtests) ===================
[18:40:13] [PASSED] drm_test_int2fixp
[18:40:13] [PASSED] drm_test_sm2fixp
[18:40:13] ==================== [PASSED] drm_fixp =====================
[18:40:13] ============================================================
[18:40:13] Testing complete. Ran 637 tests: passed: 637
[18:40:13] Elapsed time: 26.812s total, 1.811s configuring, 24.833s building, 0.148s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[18:40:13] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[18:40:15] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[18:40:25] Starting KUnit Kernel (1/1)...
[18:40:25] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[18:40:25] ================= ttm_device (5 subtests) ==================
[18:40:25] [PASSED] ttm_device_init_basic
[18:40:25] [PASSED] ttm_device_init_multiple
[18:40:25] [PASSED] ttm_device_fini_basic
[18:40:25] [PASSED] ttm_device_init_no_vma_man
[18:40:25] ================== ttm_device_init_pools ==================
[18:40:25] [PASSED] No DMA allocations, no DMA32 required
[18:40:25] [PASSED] DMA allocations, DMA32 required
[18:40:25] [PASSED] No DMA allocations, DMA32 required
[18:40:25] [PASSED] DMA allocations, no DMA32 required
[18:40:25] ============== [PASSED] ttm_device_init_pools ==============
[18:40:25] =================== [PASSED] ttm_device ====================
[18:40:25] ================== ttm_pool (8 subtests) ===================
[18:40:25] ================== ttm_pool_alloc_basic ===================
[18:40:25] [PASSED] One page
[18:40:25] [PASSED] More than one page
[18:40:25] [PASSED] Above the allocation limit
[18:40:25] [PASSED] One page, with coherent DMA mappings enabled
[18:40:25] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[18:40:25] ============== [PASSED] ttm_pool_alloc_basic ===============
[18:40:25] ============== ttm_pool_alloc_basic_dma_addr ==============
[18:40:25] [PASSED] One page
[18:40:25] [PASSED] More than one page
[18:40:25] [PASSED] Above the allocation limit
[18:40:25] [PASSED] One page, with coherent DMA mappings enabled
[18:40:25] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[18:40:25] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[18:40:25] [PASSED] ttm_pool_alloc_order_caching_match
[18:40:25] [PASSED] ttm_pool_alloc_caching_mismatch
[18:40:25] [PASSED] ttm_pool_alloc_order_mismatch
[18:40:25] [PASSED] ttm_pool_free_dma_alloc
[18:40:25] [PASSED] ttm_pool_free_no_dma_alloc
[18:40:25] [PASSED] ttm_pool_fini_basic
[18:40:25] ==================== [PASSED] ttm_pool =====================
[18:40:25] ================ ttm_resource (8 subtests) =================
[18:40:25] ================= ttm_resource_init_basic =================
[18:40:25] [PASSED] Init resource in TTM_PL_SYSTEM
[18:40:25] [PASSED] Init resource in TTM_PL_VRAM
[18:40:25] [PASSED] Init resource in a private placement
[18:40:25] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[18:40:25] ============= [PASSED] ttm_resource_init_basic =============
[18:40:25] [PASSED] ttm_resource_init_pinned
[18:40:25] [PASSED] ttm_resource_fini_basic
[18:40:25] [PASSED] ttm_resource_manager_init_basic
[18:40:25] [PASSED] ttm_resource_manager_usage_basic
[18:40:25] [PASSED] ttm_resource_manager_set_used_basic
[18:40:25] [PASSED] ttm_sys_man_alloc_basic
[18:40:25] [PASSED] ttm_sys_man_free_basic
[18:40:25] ================== [PASSED] ttm_resource ===================
[18:40:25] =================== ttm_tt (15 subtests) ===================
[18:40:25] ==================== ttm_tt_init_basic ====================
[18:40:25] [PASSED] Page-aligned size
[18:40:25] [PASSED] Extra pages requested
[18:40:25] ================ [PASSED] ttm_tt_init_basic ================
[18:40:25] [PASSED] ttm_tt_init_misaligned
[18:40:25] [PASSED] ttm_tt_fini_basic
[18:40:25] [PASSED] ttm_tt_fini_sg
[18:40:25] [PASSED] ttm_tt_fini_shmem
[18:40:25] [PASSED] ttm_tt_create_basic
[18:40:25] [PASSED] ttm_tt_create_invalid_bo_type
[18:40:25] [PASSED] ttm_tt_create_ttm_exists
[18:40:25] [PASSED] ttm_tt_create_failed
[18:40:25] [PASSED] ttm_tt_destroy_basic
[18:40:25] [PASSED] ttm_tt_populate_null_ttm
[18:40:25] [PASSED] ttm_tt_populate_populated_ttm
[18:40:25] [PASSED] ttm_tt_unpopulate_basic
[18:40:25] [PASSED] ttm_tt_unpopulate_empty_ttm
[18:40:25] [PASSED] ttm_tt_swapin_basic
[18:40:25] ===================== [PASSED] ttm_tt ======================
[18:40:25] =================== ttm_bo (14 subtests) ===================
[18:40:25] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[18:40:25] [PASSED] Cannot be interrupted and sleeps
[18:40:25] [PASSED] Cannot be interrupted, locks straight away
[18:40:25] [PASSED] Can be interrupted, sleeps
[18:40:25] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[18:40:25] [PASSED] ttm_bo_reserve_locked_no_sleep
[18:40:25] [PASSED] ttm_bo_reserve_no_wait_ticket
[18:40:25] [PASSED] ttm_bo_reserve_double_resv
[18:40:25] [PASSED] ttm_bo_reserve_interrupted
[18:40:25] [PASSED] ttm_bo_reserve_deadlock
[18:40:25] [PASSED] ttm_bo_unreserve_basic
[18:40:25] [PASSED] ttm_bo_unreserve_pinned
[18:40:25] [PASSED] ttm_bo_unreserve_bulk
[18:40:25] [PASSED] ttm_bo_fini_basic
[18:40:25] [PASSED] ttm_bo_fini_shared_resv
[18:40:25] [PASSED] ttm_bo_pin_basic
[18:40:25] [PASSED] ttm_bo_pin_unpin_resource
[18:40:25] [PASSED] ttm_bo_multiple_pin_one_unpin
[18:40:25] ===================== [PASSED] ttm_bo ======================
[18:40:25] ============== ttm_bo_validate (22 subtests) ===============
[18:40:25] ============== ttm_bo_init_reserved_sys_man ===============
[18:40:25] [PASSED] Buffer object for userspace
[18:40:25] [PASSED] Kernel buffer object
[18:40:25] [PASSED] Shared buffer object
[18:40:25] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[18:40:25] ============== ttm_bo_init_reserved_mock_man ==============
[18:40:25] [PASSED] Buffer object for userspace
[18:40:25] [PASSED] Kernel buffer object
[18:40:25] [PASSED] Shared buffer object
[18:40:25] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[18:40:25] [PASSED] ttm_bo_init_reserved_resv
[18:40:25] ================== ttm_bo_validate_basic ==================
[18:40:25] [PASSED] Buffer object for userspace
[18:40:25] [PASSED] Kernel buffer object
[18:40:25] [PASSED] Shared buffer object
[18:40:25] ============== [PASSED] ttm_bo_validate_basic ==============
[18:40:25] [PASSED] ttm_bo_validate_invalid_placement
[18:40:25] ============= ttm_bo_validate_same_placement ==============
[18:40:25] [PASSED] System manager
[18:40:25] [PASSED] VRAM manager
[18:40:25] ========= [PASSED] ttm_bo_validate_same_placement ==========
[18:40:25] [PASSED] ttm_bo_validate_failed_alloc
[18:40:25] [PASSED] ttm_bo_validate_pinned
[18:40:25] [PASSED] ttm_bo_validate_busy_placement
[18:40:25] ================ ttm_bo_validate_multihop =================
[18:40:25] [PASSED] Buffer object for userspace
[18:40:25] [PASSED] Kernel buffer object
[18:40:25] [PASSED] Shared buffer object
[18:40:25] ============ [PASSED] ttm_bo_validate_multihop =============
[18:40:25] ========== ttm_bo_validate_no_placement_signaled ==========
[18:40:25] [PASSED] Buffer object in system domain, no page vector
[18:40:25] [PASSED] Buffer object in system domain with an existing page vector
[18:40:25] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[18:40:25] ======== ttm_bo_validate_no_placement_not_signaled ========
[18:40:25] [PASSED] Buffer object for userspace
[18:40:25] [PASSED] Kernel buffer object
[18:40:25] [PASSED] Shared buffer object
[18:40:25] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[18:40:25] [PASSED] ttm_bo_validate_move_fence_signaled
[18:40:25] ========= ttm_bo_validate_move_fence_not_signaled =========
[18:40:25] [PASSED] Waits for GPU
[18:40:25] [PASSED] Tries to lock straight away
[18:40:25] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[18:40:25] [PASSED] ttm_bo_validate_swapout
[18:40:25] [PASSED] ttm_bo_validate_happy_evict
[18:40:25] [PASSED] ttm_bo_validate_all_pinned_evict
[18:40:25] [PASSED] ttm_bo_validate_allowed_only_evict
[18:40:25] [PASSED] ttm_bo_validate_deleted_evict
[18:40:25] [PASSED] ttm_bo_validate_busy_domain_evict
[18:40:25] [PASSED] ttm_bo_validate_evict_gutting
[18:40:25] [PASSED] ttm_bo_validate_recrusive_evict
[18:40:25] ================= [PASSED] ttm_bo_validate =================
[18:40:25] ============================================================
[18:40:25] Testing complete. Ran 102 tests: passed: 102
[18:40:25] Elapsed time: 12.087s total, 1.792s configuring, 10.080s building, 0.181s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 0/2] drm/i915/display: Enable AS SDP Skip Frames
@ 2026-08-03 18:53 Uma Shankar
2026-08-03 18:39 ` ✗ CI.checkpatch: warning for drm/i915/display: Enable AS SDP Skip Frames (rev2) Patchwork
` (11 more replies)
0 siblings, 12 replies; 16+ messages in thread
From: Uma Shankar @ 2026-08-03 18:53 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: animesh.manna, dibin.moolakadan.subrahmanian, Uma Shankar
When Panel Replay is active the transcoder timing generator runs at the
panel's maximum refresh rate, but content is often presented at a lower
rate. In that case the Adaptive-Sync SDP (AS SDP) only needs to reach the
panel often enough to satisfy its maximum frame time, so transmitting it
on every frame is redundant and shows up as repeated SDPs on the link.
Xe3LPD adds a HW skip-frame counter in PR_ALPM_CTL that lets the source
send a single AS SDP and then suppress it for a programmed number of
frames. Program this counter so that one AS SDP is followed by
(max_vrefresh / flip_rate - 1) idle frames, matching the effective
content rate and allowing the link to be driven down to as low as 1Hz
when the hardware supports it.
ToDo: Currently using CMRR debugfs as an interface to get the flip rate
from userspace, this will be extended to a property interface to receive
actual content fps as follow up.
Uma Shankar (2):
drm/i915/display: Enable AS SDP Skip Frames
drm/i915/display: Keep AS SDP flowing when skip frames is enabled
drivers/gpu/drm/i915/display/intel_alpm.c | 65 +++++++++++++++++--
drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +
2 files changed, 62 insertions(+), 5 deletions(-)
--
2.50.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/2] drm/i915/display: Enable AS SDP Skip Frames
2026-08-03 18:53 [PATCH 0/2] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
2026-08-03 18:39 ` ✗ CI.checkpatch: warning for drm/i915/display: Enable AS SDP Skip Frames (rev2) Patchwork
2026-08-03 18:40 ` ✓ CI.KUnit: success " Patchwork
@ 2026-08-03 18:53 ` Uma Shankar
2026-08-04 16:15 ` Dibin Moolakadan Subrahmanian
2026-08-03 18:53 ` [PATCH 2/2] drm/i915/display: Keep AS SDP flowing when skip frames is enabled Uma Shankar
` (8 subsequent siblings)
11 siblings, 1 reply; 16+ messages in thread
From: Uma Shankar @ 2026-08-03 18:53 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: animesh.manna, dibin.moolakadan.subrahmanian, Uma Shankar
When Panel Replay is active the transcoder timing generator runs at the
panel's maximum refresh rate, but content is often presented at a lower
rate. In that case the Adaptive-Sync SDP (AS SDP) only needs to reach the
panel often enough to satisfy its maximum frame time, so transmitting it
on every frame is redundant and shows up as repeated SDPs on the link.
Xe3LPD adds a HW skip-frame counter in PR_ALPM_CTL that lets the source
send a single AS SDP and then suppress it for a programmed number of
frames. Program this counter so that one AS SDP is followed by
(max_vrefresh / flip_rate - 1) idle frames, matching the effective
content rate and allowing the link to be driven down to as low as 1Hz
when the hardware supports it.
The maximum refresh rate is taken from the current mode's vertical
refresh (adjusted_mode), while the actual flip/content rate is derived
from the CMRR target (force_cmrr numerator in milli-Hz over the 1000 or
1001 denominator). If no CMRR target is programmed the skip counter is
left at zero, i.e. the feature is a no-op and AS SDP continues to be sent
on every frame.
ToDo: Currently using CMRR debugfs as an interface to get the flip rate
from userspace, this will be extended to a property interface to receive
actual content fps as follow up.
Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_alpm.c | 45 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +
2 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index f1383764b702..0f98f02a1848 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -375,6 +375,46 @@ static u32 get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *c
}
}
+/*
+ * Periodic Adaptive-Sync SDP skip frames.
+ *
+ * While Panel Replay is active the transcoder timing generator runs at the
+ * panel's maximum refresh rate, but content may be presented at a lower rate.
+ * The Adaptive-Sync SDP only needs to reach the panel often enough to satisfy
+ * its maximum frame time, so transmitting it on every frame is unnecessary and
+ * shows up as repeated SDPs on the link. Program the HW skip counter so that a
+ * single AS SDP is followed by (max_vrefresh / flip_vrefresh - 1) idle frames,
+ * matching the effective content rate.
+ *
+ * ToDo: Actual flip rate is currently passed on by userspace through debugfs
+ * create for CMRRR, but will be extended later as a property interface.
+ */
+static u32 intel_pr_as_sdp_skip_frames(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ int max_vrefresh = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
+ int flip_vrefresh;
+ u32 skip_frames;
+
+ /*
+ * Actual (flip) refresh rate comes from the CMRR target: numerator is
+ * in milli-Hz, denominator is 1000 (1:1) or 1001 (1000/1001 timing).
+ */
+ if (!crtc->force_cmrr.numerator || !crtc->force_cmrr.denominator)
+ return 0;
+
+ flip_vrefresh = DIV_ROUND_CLOSEST(crtc->force_cmrr.numerator,
+ crtc->force_cmrr.denominator);
+
+ if (max_vrefresh <= 0 || flip_vrefresh <= 0 || max_vrefresh <= flip_vrefresh)
+ return 0;
+
+ skip_frames = max_vrefresh / flip_vrefresh - 1;
+
+ return min_t(u32, skip_frames,
+ REG_FIELD_MAX(PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK));
+}
+
static void lnl_alpm_configure(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
@@ -410,6 +450,11 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
else
pr_alpm_ctl &= ~PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
+ /* AS SDP skip frames field only exists on Xe3LPD+ */
+ if (DISPLAY_VER(display) >= 35)
+ pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(
+ intel_pr_as_sdp_skip_frames(crtc_state));
+
intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
pr_alpm_ctl);
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 16a9e3af198d..bb577e7e3bbd 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -276,6 +276,8 @@
#define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2 REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 0)
#define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1 REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 1)
#define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2 REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 2)
+#define PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK REG_GENMASK(27, 16)
+#define PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(frames) REG_FIELD_PREP(PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK, (frames))
#define _ALPM_CTL_A 0x60950
#define ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A)
--
2.50.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/2] drm/i915/display: Keep AS SDP flowing when skip frames is enabled
2026-08-03 18:53 [PATCH 0/2] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
` (2 preceding siblings ...)
2026-08-03 18:53 ` [PATCH 1/2] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
@ 2026-08-03 18:53 ` Uma Shankar
2026-08-04 7:21 ` Dibin Moolakadan Subrahmanian
2026-08-03 21:25 ` ✓ Xe.CI.FULL: success for drm/i915/display: Enable AS SDP Skip Frames (rev2) Patchwork
` (7 subsequent siblings)
11 siblings, 1 reply; 16+ messages in thread
From: Uma Shankar @ 2026-08-03 18:53 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: animesh.manna, dibin.moolakadan.subrahmanian, Uma Shankar
The AS SDP skip-frame mechanism relies on the AS SDP still being
transmitted (just less often) while Panel Replay is active, so the source
must not stop sending it in the PR active state, nor enter the DC3CO idle
protocol which would suppress it entirely.
When a non-zero skip-frame count is programmed, leave both
PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE and
PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL cleared. The previous behaviour
(honouring disable_as_sdp_when_pr_active and the DC3CO idle protocol) is
retained for the non skip-frame case.
Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Naladala Ramanaidu <ramanaidu.naladala@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_alpm.c | 28 +++++++++++++++--------
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 0f98f02a1848..7e2292f93e1e 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -439,21 +439,31 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
if (intel_dp->as_sdp_supported) {
u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
+ u32 skip_frames = 0;
+
+ /* AS SDP skip frames field only exists on Xe3LPD+ */
+ if (DISPLAY_VER(display) >= 35)
+ skip_frames = intel_pr_as_sdp_skip_frames(crtc_state);
if (crtc_state->link_off_after_as_sdp_when_pr_active)
pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
- if (crtc_state->disable_as_sdp_when_pr_active)
- pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
- if (intel_display_power_dc3co_allowed(display))
- pr_alpm_ctl |= PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
- else
+ /*
+ * Skip frames needs the AS SDP to keep flowing during PR
+ * active, so it is mutually exclusive with disabling AS SDP
+ * transmission in active and with the DC3CO idle protocol.
+ */
+ if (skip_frames) {
+ pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(skip_frames);
+ pr_alpm_ctl &= ~PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
pr_alpm_ctl &= ~PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
+ } else {
+ if (crtc_state->disable_as_sdp_when_pr_active)
+ pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
- /* AS SDP skip frames field only exists on Xe3LPD+ */
- if (DISPLAY_VER(display) >= 35)
- pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(
- intel_pr_as_sdp_skip_frames(crtc_state));
+ if (intel_display_power_dc3co_allowed(display))
+ pr_alpm_ctl |= PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
+ }
intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
pr_alpm_ctl);
--
2.50.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* ✓ Xe.CI.FULL: success for drm/i915/display: Enable AS SDP Skip Frames (rev2)
2026-08-03 18:53 [PATCH 0/2] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
` (3 preceding siblings ...)
2026-08-03 18:53 ` [PATCH 2/2] drm/i915/display: Keep AS SDP flowing when skip frames is enabled Uma Shankar
@ 2026-08-03 21:25 ` Patchwork
2026-08-04 12:03 ` ✗ CI.checkpatch: warning " Patchwork
` (6 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2026-08-03 21:25 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 873 bytes --]
== Series Details ==
Series: drm/i915/display: Enable AS SDP Skip Frames (rev2)
URL : https://patchwork.freedesktop.org/series/162015/
State : success
== Summary ==
CI Bug Log - changes from xe-5521-f8d080b47819f01011c1b9c3c875badbb67ec955_FULL -> xe-pw-162015v2_FULL
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (0 -> 0)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-5521-f8d080b47819f01011c1b9c3c875badbb67ec955 -> xe-pw-162015v2
IGT_9036: 9036
xe-5521-f8d080b47819f01011c1b9c3c875badbb67ec955: f8d080b47819f01011c1b9c3c875badbb67ec955
xe-pw-162015v2: 162015v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v2/index.html
[-- Attachment #2: Type: text/html, Size: 1421 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/2] drm/i915/display: Keep AS SDP flowing when skip frames is enabled
2026-08-03 18:53 ` [PATCH 2/2] drm/i915/display: Keep AS SDP flowing when skip frames is enabled Uma Shankar
@ 2026-08-04 7:21 ` Dibin Moolakadan Subrahmanian
2026-08-04 7:50 ` Shankar, Uma
0 siblings, 1 reply; 16+ messages in thread
From: Dibin Moolakadan Subrahmanian @ 2026-08-04 7:21 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe; +Cc: animesh.manna
On 8/4/2026 12:23 AM, Uma Shankar wrote:
> The AS SDP skip-frame mechanism relies on the AS SDP still being
> transmitted (just less often) while Panel Replay is active, so the source
> must not stop sending it in the PR active state, nor enter the DC3CO idle
> protocol which would suppress it entirely.
>
> When a non-zero skip-frame count is programmed, leave both
> PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE and
> PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL cleared. The previous behaviour
> (honouring disable_as_sdp_when_pr_active and the DC3CO idle protocol) is
> retained for the non skip-frame case.
>
> Assisted-by: Claude:claude-opus-4-8
> Signed-off-by: Naladala Ramanaidu <ramanaidu.naladala@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_alpm.c | 28 +++++++++++++++--------
> 1 file changed, 19 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 0f98f02a1848..7e2292f93e1e 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -439,21 +439,31 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>
> if (intel_dp->as_sdp_supported) {
> u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
> + u32 skip_frames = 0;
> +
> + /* AS SDP skip frames field only exists on Xe3LPD+ */
> + if (DISPLAY_VER(display) >= 35)
> + skip_frames = intel_pr_as_sdp_skip_frames(crtc_state);
>
> if (crtc_state->link_off_after_as_sdp_when_pr_active)
> pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
> - if (crtc_state->disable_as_sdp_when_pr_active)
> - pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
>
> - if (intel_display_power_dc3co_allowed(display))
> - pr_alpm_ctl |= PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
> - else
> + /*
> + * Skip frames needs the AS SDP to keep flowing during PR
> + * active, so it is mutually exclusive with disabling AS SDP
> + * transmission in active and with the DC3CO idle protocol.
> + */
> + if (skip_frames) {
> + pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(skip_frames);
> + pr_alpm_ctl &= ~PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
> pr_alpm_ctl &= ~PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
> + } else {
> + if (crtc_state->disable_as_sdp_when_pr_active)
> + pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
>
> - /* AS SDP skip frames field only exists on Xe3LPD+ */
> - if (DISPLAY_VER(display) >= 35)
> - pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(
> - intel_pr_as_sdp_skip_frames(crtc_state));
> + if (intel_display_power_dc3co_allowed(display))
> + pr_alpm_ctl |= PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
Do we also need to clear the AS SDP skip frame bits here?
Otherwise, LGTM.
Regards,
Dibin
> + }
>
> intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
> pr_alpm_ctl);
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH 2/2] drm/i915/display: Keep AS SDP flowing when skip frames is enabled
2026-08-04 7:21 ` Dibin Moolakadan Subrahmanian
@ 2026-08-04 7:50 ` Shankar, Uma
0 siblings, 0 replies; 16+ messages in thread
From: Shankar, Uma @ 2026-08-04 7:50 UTC (permalink / raw)
To: Dibin Moolakadan Subrahmanian, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Manna, Animesh
> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Tuesday, August 4, 2026 12:52 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>
> Subject: Re: [PATCH 2/2] drm/i915/display: Keep AS SDP flowing when skip
> frames is enabled
>
> On 8/4/2026 12:23 AM, Uma Shankar wrote:
> > The AS SDP skip-frame mechanism relies on the AS SDP still being
> > transmitted (just less often) while Panel Replay is active, so the
> > source must not stop sending it in the PR active state, nor enter the
> > DC3CO idle protocol which would suppress it entirely.
> >
> > When a non-zero skip-frame count is programmed, leave both
> > PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE and
> > PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL cleared. The previous
> behaviour
> > (honouring disable_as_sdp_when_pr_active and the DC3CO idle protocol)
> > is retained for the non skip-frame case.
> >
> > Assisted-by: Claude:claude-opus-4-8
> > Signed-off-by: Naladala Ramanaidu <ramanaidu.naladala@intel.com>
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_alpm.c | 28 +++++++++++++++--------
> > 1 file changed, 19 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index 0f98f02a1848..7e2292f93e1e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -439,21 +439,31 @@ static void lnl_alpm_configure(struct intel_dp
> > *intel_dp,
> >
> > if (intel_dp->as_sdp_supported) {
> > u32 pr_alpm_ctl =
> > get_pr_alpm_as_sdp_transmission_time(crtc_state);
> > + u32 skip_frames = 0;
> > +
> > + /* AS SDP skip frames field only exists on Xe3LPD+ */
> > + if (DISPLAY_VER(display) >= 35)
> > + skip_frames =
> intel_pr_as_sdp_skip_frames(crtc_state);
> >
> > if (crtc_state->link_off_after_as_sdp_when_pr_active)
> > pr_alpm_ctl |=
> PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
> > - if (crtc_state->disable_as_sdp_when_pr_active)
> > - pr_alpm_ctl |=
> PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
> >
> > - if (intel_display_power_dc3co_allowed(display))
> > - pr_alpm_ctl |=
> PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
> > - else
> > + /*
> > + * Skip frames needs the AS SDP to keep flowing during
> PR
> > + * active, so it is mutually exclusive with disabling AS
> SDP
> > + * transmission in active and with the DC3CO idle
> protocol.
> > + */
> > + if (skip_frames) {
> > + pr_alpm_ctl |=
> PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(skip_frames);
> > + pr_alpm_ctl &=
> > +~PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
> > pr_alpm_ctl &=
> ~PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
> > + } else {
> > + if (crtc_state->disable_as_sdp_when_pr_active)
> > + pr_alpm_ctl |=
> > +PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
> >
> > - /* AS SDP skip frames field only exists on Xe3LPD+ */
> > - if (DISPLAY_VER(display) >= 35)
> > - pr_alpm_ctl |=
> PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(
> > - intel_pr_as_sdp_skip_frames(crtc_state));
> > + if (intel_display_power_dc3co_allowed(display))
> > + pr_alpm_ctl |=
> PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
> Do we also need to clear the AS SDP skip frame bits here?
Yeah we should explicitly clear it to 0 here. Will update the same.
Thanks Dibin for the review.
Regards,
Uma Shankar
> Otherwise, LGTM.
>
> Regards,
> Dibin
>
> > + }
> >
> > intel_de_write(display, PR_ALPM_CTL(display,
> cpu_transcoder),
> > pr_alpm_ctl);
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✗ CI.checkpatch: warning for drm/i915/display: Enable AS SDP Skip Frames (rev2)
2026-08-03 18:53 [PATCH 0/2] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
` (4 preceding siblings ...)
2026-08-03 21:25 ` ✓ Xe.CI.FULL: success for drm/i915/display: Enable AS SDP Skip Frames (rev2) Patchwork
@ 2026-08-04 12:03 ` Patchwork
2026-08-04 12:05 ` ✓ CI.KUnit: success " Patchwork
` (5 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2026-08-04 12:03 UTC (permalink / raw)
To: Shankar, Uma; +Cc: intel-xe
== Series Details ==
Series: drm/i915/display: Enable AS SDP Skip Frames (rev2)
URL : https://patchwork.freedesktop.org/series/162015/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
061140b9bc586ae7f40abc1249c97e1cc72d1b9d
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 2cd2b523be724cc092cb2ee575164da497a5d54b
Author: Uma Shankar <uma.shankar@intel.com>
Date: Tue Aug 4 00:23:05 2026 +0530
drm/i915/display: Keep AS SDP flowing when skip frames is enabled
The AS SDP skip-frame mechanism relies on the AS SDP still being
transmitted (just less often) while Panel Replay is active, so the source
must not stop sending it in the PR active state, nor enter the DC3CO idle
protocol which would suppress it entirely.
When a non-zero skip-frame count is programmed, leave both
PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE and
PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL cleared. The previous behaviour
(honouring disable_as_sdp_when_pr_active and the DC3CO idle protocol) is
retained for the non skip-frame case.
Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Naladala Ramanaidu <ramanaidu.naladala@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
+ /mt/dim checkpatch 11c46820ac5b8e1451b8d0c0b82d2b9b0b0f9e1e drm-intel
686d87e5b8c8 drm/i915/display: Enable AS SDP Skip Frames
-:90: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#90: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:455:
+ pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(
-:105: WARNING:LONG_LINE: line length of 125 exceeds 100 columns
#105: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:280:
+#define PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(frames) REG_FIELD_PREP(PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK, (frames))
total: 0 errors, 1 warnings, 1 checks, 65 lines checked
2cd2b523be72 drm/i915/display: Keep AS SDP flowing when skip frames is enabled
-:55: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#55: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:462:
+ pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
total: 0 errors, 1 warnings, 0 checks, 40 lines checked
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✓ CI.KUnit: success for drm/i915/display: Enable AS SDP Skip Frames (rev2)
2026-08-03 18:53 [PATCH 0/2] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
` (5 preceding siblings ...)
2026-08-04 12:03 ` ✗ CI.checkpatch: warning " Patchwork
@ 2026-08-04 12:05 ` Patchwork
2026-08-05 6:03 ` ✗ Xe.CI.BAT: failure " Patchwork
` (4 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2026-08-04 12:05 UTC (permalink / raw)
To: Shankar, Uma; +Cc: intel-xe
== Series Details ==
Series: drm/i915/display: Enable AS SDP Skip Frames (rev2)
URL : https://patchwork.freedesktop.org/series/162015/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[12:03:44] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:03:49] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:04:20] Starting KUnit Kernel (1/1)...
[12:04:20] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:04:21] ================== guc_buf (11 subtests) ===================
[12:04:21] [PASSED] test_smallest
[12:04:21] [PASSED] test_largest
[12:04:21] [PASSED] test_granular
[12:04:21] [PASSED] test_unique
[12:04:21] [PASSED] test_overlap
[12:04:21] [PASSED] test_reusable
[12:04:21] [PASSED] test_too_big
[12:04:21] [PASSED] test_flush
[12:04:21] [PASSED] test_lookup
[12:04:21] [PASSED] test_data
[12:04:21] [PASSED] test_class
[12:04:21] ===================== [PASSED] guc_buf =====================
[12:04:21] =================== guc_dbm (7 subtests) ===================
[12:04:21] [PASSED] test_empty
[12:04:21] [PASSED] test_default
[12:04:21] ======================== test_size ========================
[12:04:21] [PASSED] 4
[12:04:21] [PASSED] 8
[12:04:21] [PASSED] 32
[12:04:21] [PASSED] 256
[12:04:21] ==================== [PASSED] test_size ====================
[12:04:21] ======================= test_reuse ========================
[12:04:21] [PASSED] 4
[12:04:21] [PASSED] 8
[12:04:21] [PASSED] 32
[12:04:21] [PASSED] 256
[12:04:21] =================== [PASSED] test_reuse ====================
[12:04:21] =================== test_range_overlap ====================
[12:04:21] [PASSED] 4
[12:04:21] [PASSED] 8
[12:04:21] [PASSED] 32
[12:04:21] [PASSED] 256
[12:04:21] =============== [PASSED] test_range_overlap ================
[12:04:21] =================== test_range_compact ====================
[12:04:21] [PASSED] 4
[12:04:21] [PASSED] 8
[12:04:21] [PASSED] 32
[12:04:21] [PASSED] 256
[12:04:21] =============== [PASSED] test_range_compact ================
[12:04:21] ==================== test_range_spare =====================
[12:04:21] [PASSED] 4
[12:04:21] [PASSED] 8
[12:04:21] [PASSED] 32
[12:04:21] [PASSED] 256
[12:04:21] ================ [PASSED] test_range_spare =================
[12:04:21] ===================== [PASSED] guc_dbm =====================
[12:04:21] =================== guc_idm (6 subtests) ===================
[12:04:21] [PASSED] bad_init
[12:04:21] [PASSED] no_init
[12:04:21] [PASSED] init_fini
[12:04:21] [PASSED] check_used
[12:04:21] [PASSED] check_quota
[12:04:21] [PASSED] check_all
[12:04:21] ===================== [PASSED] guc_idm =====================
[12:04:21] =============== guc_klv_helpers (9 subtests) ===============
[12:04:21] [PASSED] test_count
[12:04:21] [PASSED] test_encode_u32
[12:04:21] [PASSED] test_encode_u64
[12:04:21] [PASSED] test_encode_string
[12:04:21] [PASSED] test_encode_object_raw
[12:04:21] [PASSED] test_encode_object_klv
[12:04:21] [PASSED] test_encode_object_nested
[12:04:21] [PASSED] test_encode_object_basic
[12:04:21] [PASSED] test_print
[12:04:21] ================= [PASSED] guc_klv_helpers =================
[12:04:21] ================== no_relay (3 subtests) ===================
[12:04:21] [PASSED] xe_drops_guc2pf_if_not_ready
[12:04:21] [PASSED] xe_drops_guc2vf_if_not_ready
[12:04:21] [PASSED] xe_rejects_send_if_not_ready
[12:04:21] ==================== [PASSED] no_relay =====================
[12:04:21] ================== pf_relay (14 subtests) ==================
[12:04:21] [PASSED] pf_rejects_guc2pf_too_short
[12:04:21] [PASSED] pf_rejects_guc2pf_too_long
[12:04:21] [PASSED] pf_rejects_guc2pf_no_payload
[12:04:21] [PASSED] pf_fails_no_payload
[12:04:21] [PASSED] pf_fails_bad_origin
[12:04:21] [PASSED] pf_fails_bad_type
[12:04:21] [PASSED] pf_txn_reports_error
[12:04:21] [PASSED] pf_txn_sends_pf2guc
[12:04:21] [PASSED] pf_sends_pf2guc
[12:04:21] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[12:04:21] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[12:04:21] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[12:04:21] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[12:04:21] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[12:04:21] ==================== [PASSED] pf_relay =====================
[12:04:21] ================== vf_relay (3 subtests) ===================
[12:04:21] [PASSED] vf_rejects_guc2vf_too_short
[12:04:21] [PASSED] vf_rejects_guc2vf_too_long
[12:04:21] [PASSED] vf_rejects_guc2vf_no_payload
[12:04:21] ==================== [PASSED] vf_relay =====================
[12:04:21] ================ pf_gt_config (9 subtests) =================
[12:04:21] [PASSED] fair_contexts_1vf
[12:04:21] [PASSED] fair_doorbells_1vf
[12:04:21] [PASSED] fair_ggtt_1vf
[12:04:21] ====================== fair_vram_1vf ======================
[12:04:21] [PASSED] 3.50 GiB
[12:04:21] [PASSED] 11.5 GiB
[12:04:21] [PASSED] 15.5 GiB
[12:04:21] [PASSED] 31.5 GiB
[12:04:21] [PASSED] 63.5 GiB
[12:04:21] [PASSED] 1.91 GiB
[12:04:21] ================== [PASSED] fair_vram_1vf ==================
[12:04:21] ================ fair_vram_1vf_admin_only =================
[12:04:21] [PASSED] 3.50 GiB
[12:04:21] [PASSED] 11.5 GiB
[12:04:21] [PASSED] 15.5 GiB
[12:04:21] [PASSED] 31.5 GiB
[12:04:21] [PASSED] 63.5 GiB
[12:04:21] [PASSED] 1.91 GiB
[12:04:21] ============ [PASSED] fair_vram_1vf_admin_only =============
[12:04:21] ====================== fair_contexts ======================
[12:04:21] [PASSED] 1 VF
[12:04:21] [PASSED] 2 VFs
[12:04:21] [PASSED] 3 VFs
[12:04:21] [PASSED] 4 VFs
[12:04:21] [PASSED] 5 VFs
[12:04:21] [PASSED] 6 VFs
[12:04:21] [PASSED] 7 VFs
[12:04:21] [PASSED] 8 VFs
[12:04:21] [PASSED] 9 VFs
[12:04:21] [PASSED] 10 VFs
[12:04:21] [PASSED] 11 VFs
[12:04:21] [PASSED] 12 VFs
[12:04:21] [PASSED] 13 VFs
[12:04:21] [PASSED] 14 VFs
[12:04:21] [PASSED] 15 VFs
[12:04:21] [PASSED] 16 VFs
[12:04:21] [PASSED] 17 VFs
[12:04:21] [PASSED] 18 VFs
[12:04:21] [PASSED] 19 VFs
[12:04:21] [PASSED] 20 VFs
[12:04:21] [PASSED] 21 VFs
[12:04:21] [PASSED] 22 VFs
[12:04:21] [PASSED] 23 VFs
[12:04:21] [PASSED] 24 VFs
[12:04:21] [PASSED] 25 VFs
[12:04:21] [PASSED] 26 VFs
[12:04:21] [PASSED] 27 VFs
[12:04:21] [PASSED] 28 VFs
[12:04:21] [PASSED] 29 VFs
[12:04:21] [PASSED] 30 VFs
[12:04:21] [PASSED] 31 VFs
[12:04:21] [PASSED] 32 VFs
[12:04:21] [PASSED] 33 VFs
[12:04:21] [PASSED] 34 VFs
[12:04:21] [PASSED] 35 VFs
[12:04:21] [PASSED] 36 VFs
[12:04:21] [PASSED] 37 VFs
[12:04:21] [PASSED] 38 VFs
[12:04:21] [PASSED] 39 VFs
[12:04:21] [PASSED] 40 VFs
[12:04:21] [PASSED] 41 VFs
[12:04:21] [PASSED] 42 VFs
[12:04:21] [PASSED] 43 VFs
[12:04:21] [PASSED] 44 VFs
[12:04:21] [PASSED] 45 VFs
[12:04:21] [PASSED] 46 VFs
[12:04:21] [PASSED] 47 VFs
[12:04:21] [PASSED] 48 VFs
[12:04:21] [PASSED] 49 VFs
[12:04:21] [PASSED] 50 VFs
[12:04:21] [PASSED] 51 VFs
[12:04:21] [PASSED] 52 VFs
[12:04:21] [PASSED] 53 VFs
[12:04:21] [PASSED] 54 VFs
[12:04:21] [PASSED] 55 VFs
[12:04:21] [PASSED] 56 VFs
[12:04:21] [PASSED] 57 VFs
[12:04:21] [PASSED] 58 VFs
[12:04:21] [PASSED] 59 VFs
[12:04:21] [PASSED] 60 VFs
[12:04:21] [PASSED] 61 VFs
[12:04:21] [PASSED] 62 VFs
[12:04:21] [PASSED] 63 VFs
[12:04:21] ================== [PASSED] fair_contexts ==================
[12:04:21] ===================== fair_doorbells ======================
[12:04:21] [PASSED] 1 VF
[12:04:21] [PASSED] 2 VFs
[12:04:21] [PASSED] 3 VFs
[12:04:21] [PASSED] 4 VFs
[12:04:21] [PASSED] 5 VFs
[12:04:21] [PASSED] 6 VFs
[12:04:21] [PASSED] 7 VFs
[12:04:21] [PASSED] 8 VFs
[12:04:21] [PASSED] 9 VFs
[12:04:21] [PASSED] 10 VFs
[12:04:21] [PASSED] 11 VFs
[12:04:21] [PASSED] 12 VFs
[12:04:21] [PASSED] 13 VFs
[12:04:21] [PASSED] 14 VFs
[12:04:21] [PASSED] 15 VFs
[12:04:21] [PASSED] 16 VFs
[12:04:21] [PASSED] 17 VFs
[12:04:21] [PASSED] 18 VFs
[12:04:21] [PASSED] 19 VFs
[12:04:21] [PASSED] 20 VFs
[12:04:21] [PASSED] 21 VFs
[12:04:21] [PASSED] 22 VFs
[12:04:21] [PASSED] 23 VFs
[12:04:21] [PASSED] 24 VFs
[12:04:21] [PASSED] 25 VFs
[12:04:21] [PASSED] 26 VFs
[12:04:21] [PASSED] 27 VFs
[12:04:21] [PASSED] 28 VFs
[12:04:21] [PASSED] 29 VFs
[12:04:21] [PASSED] 30 VFs
[12:04:21] [PASSED] 31 VFs
[12:04:21] [PASSED] 32 VFs
[12:04:21] [PASSED] 33 VFs
[12:04:21] [PASSED] 34 VFs
[12:04:21] [PASSED] 35 VFs
[12:04:21] [PASSED] 36 VFs
[12:04:21] [PASSED] 37 VFs
[12:04:21] [PASSED] 38 VFs
[12:04:21] [PASSED] 39 VFs
[12:04:21] [PASSED] 40 VFs
[12:04:21] [PASSED] 41 VFs
[12:04:21] [PASSED] 42 VFs
[12:04:21] [PASSED] 43 VFs
[12:04:21] [PASSED] 44 VFs
[12:04:21] [PASSED] 45 VFs
[12:04:21] [PASSED] 46 VFs
[12:04:21] [PASSED] 47 VFs
[12:04:21] [PASSED] 48 VFs
[12:04:21] [PASSED] 49 VFs
[12:04:21] [PASSED] 50 VFs
[12:04:21] [PASSED] 51 VFs
[12:04:21] [PASSED] 52 VFs
[12:04:21] [PASSED] 53 VFs
[12:04:21] [PASSED] 54 VFs
[12:04:21] [PASSED] 55 VFs
[12:04:21] [PASSED] 56 VFs
[12:04:21] [PASSED] 57 VFs
[12:04:21] [PASSED] 58 VFs
[12:04:21] [PASSED] 59 VFs
[12:04:21] [PASSED] 60 VFs
[12:04:21] [PASSED] 61 VFs
[12:04:21] [PASSED] 62 VFs
[12:04:21] [PASSED] 63 VFs
[12:04:21] ================= [PASSED] fair_doorbells ==================
[12:04:21] ======================== fair_ggtt ========================
[12:04:21] [PASSED] 1 VF
[12:04:21] [PASSED] 2 VFs
[12:04:21] [PASSED] 3 VFs
[12:04:21] [PASSED] 4 VFs
[12:04:21] [PASSED] 5 VFs
[12:04:21] [PASSED] 6 VFs
[12:04:21] [PASSED] 7 VFs
[12:04:21] [PASSED] 8 VFs
[12:04:21] [PASSED] 9 VFs
[12:04:21] [PASSED] 10 VFs
[12:04:21] [PASSED] 11 VFs
[12:04:21] [PASSED] 12 VFs
[12:04:21] [PASSED] 13 VFs
[12:04:21] [PASSED] 14 VFs
[12:04:21] [PASSED] 15 VFs
[12:04:21] [PASSED] 16 VFs
[12:04:21] [PASSED] 17 VFs
[12:04:21] [PASSED] 18 VFs
[12:04:21] [PASSED] 19 VFs
[12:04:21] [PASSED] 20 VFs
[12:04:21] [PASSED] 21 VFs
[12:04:21] [PASSED] 22 VFs
[12:04:21] [PASSED] 23 VFs
[12:04:21] [PASSED] 24 VFs
[12:04:21] [PASSED] 25 VFs
[12:04:21] [PASSED] 26 VFs
[12:04:21] [PASSED] 27 VFs
[12:04:21] [PASSED] 28 VFs
[12:04:21] [PASSED] 29 VFs
[12:04:21] [PASSED] 30 VFs
[12:04:21] [PASSED] 31 VFs
[12:04:21] [PASSED] 32 VFs
[12:04:21] [PASSED] 33 VFs
[12:04:21] [PASSED] 34 VFs
[12:04:21] [PASSED] 35 VFs
[12:04:21] [PASSED] 36 VFs
[12:04:21] [PASSED] 37 VFs
[12:04:21] [PASSED] 38 VFs
[12:04:21] [PASSED] 39 VFs
[12:04:21] [PASSED] 40 VFs
[12:04:21] [PASSED] 41 VFs
[12:04:21] [PASSED] 42 VFs
[12:04:21] [PASSED] 43 VFs
[12:04:21] [PASSED] 44 VFs
[12:04:21] [PASSED] 45 VFs
[12:04:21] [PASSED] 46 VFs
[12:04:21] [PASSED] 47 VFs
[12:04:21] [PASSED] 48 VFs
[12:04:21] [PASSED] 49 VFs
[12:04:21] [PASSED] 50 VFs
[12:04:21] [PASSED] 51 VFs
[12:04:21] [PASSED] 52 VFs
[12:04:21] [PASSED] 53 VFs
[12:04:21] [PASSED] 54 VFs
[12:04:21] [PASSED] 55 VFs
[12:04:21] [PASSED] 56 VFs
[12:04:21] [PASSED] 57 VFs
[12:04:21] [PASSED] 58 VFs
[12:04:21] [PASSED] 59 VFs
[12:04:21] [PASSED] 60 VFs
[12:04:21] [PASSED] 61 VFs
[12:04:21] [PASSED] 62 VFs
[12:04:21] [PASSED] 63 VFs
[12:04:21] ==================== [PASSED] fair_ggtt ====================
[12:04:21] ======================== fair_vram ========================
[12:04:21] [PASSED] 1 VF
[12:04:21] [PASSED] 2 VFs
[12:04:21] [PASSED] 3 VFs
[12:04:21] [PASSED] 4 VFs
[12:04:21] [PASSED] 5 VFs
[12:04:21] [PASSED] 6 VFs
[12:04:21] [PASSED] 7 VFs
[12:04:21] [PASSED] 8 VFs
[12:04:21] [PASSED] 9 VFs
[12:04:21] [PASSED] 10 VFs
[12:04:21] [PASSED] 11 VFs
[12:04:21] [PASSED] 12 VFs
[12:04:21] [PASSED] 13 VFs
[12:04:21] [PASSED] 14 VFs
[12:04:21] [PASSED] 15 VFs
[12:04:21] [PASSED] 16 VFs
[12:04:21] [PASSED] 17 VFs
[12:04:21] [PASSED] 18 VFs
[12:04:21] [PASSED] 19 VFs
[12:04:21] [PASSED] 20 VFs
[12:04:21] [PASSED] 21 VFs
[12:04:21] [PASSED] 22 VFs
[12:04:21] [PASSED] 23 VFs
[12:04:21] [PASSED] 24 VFs
[12:04:21] [PASSED] 25 VFs
[12:04:21] [PASSED] 26 VFs
[12:04:21] [PASSED] 27 VFs
[12:04:21] [PASSED] 28 VFs
[12:04:21] [PASSED] 29 VFs
[12:04:21] [PASSED] 30 VFs
[12:04:21] [PASSED] 31 VFs
[12:04:21] [PASSED] 32 VFs
[12:04:21] [PASSED] 33 VFs
[12:04:21] [PASSED] 34 VFs
[12:04:21] [PASSED] 35 VFs
[12:04:21] [PASSED] 36 VFs
[12:04:21] [PASSED] 37 VFs
[12:04:21] [PASSED] 38 VFs
[12:04:21] [PASSED] 39 VFs
[12:04:21] [PASSED] 40 VFs
[12:04:21] [PASSED] 41 VFs
[12:04:21] [PASSED] 42 VFs
[12:04:21] [PASSED] 43 VFs
[12:04:21] [PASSED] 44 VFs
[12:04:21] [PASSED] 45 VFs
[12:04:21] [PASSED] 46 VFs
[12:04:21] [PASSED] 47 VFs
[12:04:21] [PASSED] 48 VFs
[12:04:21] [PASSED] 49 VFs
[12:04:21] [PASSED] 50 VFs
[12:04:21] [PASSED] 51 VFs
[12:04:21] [PASSED] 52 VFs
[12:04:21] [PASSED] 53 VFs
[12:04:21] [PASSED] 54 VFs
[12:04:21] [PASSED] 55 VFs
[12:04:21] [PASSED] 56 VFs
[12:04:21] [PASSED] 57 VFs
[12:04:21] [PASSED] 58 VFs
[12:04:21] [PASSED] 59 VFs
[12:04:21] [PASSED] 60 VFs
[12:04:21] [PASSED] 61 VFs
[12:04:21] [PASSED] 62 VFs
[12:04:21] [PASSED] 63 VFs
[12:04:21] ==================== [PASSED] fair_vram ====================
[12:04:21] ================== [PASSED] pf_gt_config ===================
[12:04:21] ===================== lmtt (1 subtest) =====================
[12:04:21] ======================== test_ops =========================
[12:04:21] [PASSED] 2-level
[12:04:21] [PASSED] multi-level
[12:04:21] ==================== [PASSED] test_ops =====================
[12:04:21] ====================== [PASSED] lmtt =======================
[12:04:21] ================= sriov_packet (1 subtest) =================
[12:04:21] [PASSED] test_descriptor_init
[12:04:21] ================== [PASSED] sriov_packet ===================
[12:04:21] ================= pf_service (11 subtests) =================
[12:04:21] [PASSED] pf_negotiate_any
[12:04:21] [PASSED] pf_negotiate_base_match
[12:04:21] [PASSED] pf_negotiate_base_newer
[12:04:21] [PASSED] pf_negotiate_base_next
[12:04:21] [SKIPPED] pf_negotiate_base_older (no older minor)
[12:04:21] [PASSED] pf_negotiate_base_prev
[12:04:21] [PASSED] pf_negotiate_latest_match
[12:04:21] [PASSED] pf_negotiate_latest_newer
[12:04:21] [PASSED] pf_negotiate_latest_next
[12:04:21] [SKIPPED] pf_negotiate_latest_older (no older minor)
[12:04:21] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[12:04:21] =================== [PASSED] pf_service ====================
[12:04:21] ================= xe_guc_g2g (2 subtests) ==================
[12:04:21] ============== xe_live_guc_g2g_kunit_default ==============
[12:04:21] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[12:04:21] ============== xe_live_guc_g2g_kunit_allmem ===============
[12:04:21] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[12:04:21] =================== [SKIPPED] xe_guc_g2g ===================
[12:04:21] =================== xe_mocs (2 subtests) ===================
[12:04:21] ================ xe_live_mocs_kernel_kunit ================
[12:04:21] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[12:04:21] ================ xe_live_mocs_reset_kunit =================
[12:04:21] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[12:04:21] ==================== [SKIPPED] xe_mocs =====================
[12:04:21] ================= xe_migrate (2 subtests) ==================
[12:04:21] ================= xe_migrate_sanity_kunit =================
[12:04:21] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[12:04:21] ================== xe_validate_ccs_kunit ==================
[12:04:21] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[12:04:21] =================== [SKIPPED] xe_migrate ===================
[12:04:21] ================== xe_dma_buf (1 subtest) ==================
[12:04:21] ==================== xe_dma_buf_kunit =====================
[12:04:21] ================ [SKIPPED] xe_dma_buf_kunit ================
[12:04:21] =================== [SKIPPED] xe_dma_buf ===================
[12:04:21] ================= xe_bo_shrink (1 subtest) =================
[12:04:21] =================== xe_bo_shrink_kunit ====================
[12:04:21] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[12:04:21] ================== [SKIPPED] xe_bo_shrink ==================
[12:04:21] ==================== xe_bo (2 subtests) ====================
[12:04:21] ================== xe_ccs_migrate_kunit ===================
[12:04:21] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[12:04:21] ==================== xe_bo_evict_kunit ====================
[12:04:21] =============== [SKIPPED] xe_bo_evict_kunit ================
[12:04:21] ===================== [SKIPPED] xe_bo ======================
[12:04:21] ==================== args (13 subtests) ====================
[12:04:21] [PASSED] count_args_test
[12:04:21] [PASSED] call_args_example
[12:04:21] [PASSED] call_args_test
[12:04:21] [PASSED] drop_first_arg_example
[12:04:21] [PASSED] drop_first_arg_test
[12:04:21] [PASSED] first_arg_example
[12:04:21] [PASSED] first_arg_test
[12:04:21] [PASSED] last_arg_example
[12:04:21] [PASSED] last_arg_test
[12:04:21] [PASSED] pick_arg_example
[12:04:21] [PASSED] if_args_example
[12:04:21] [PASSED] if_args_test
[12:04:21] [PASSED] sep_comma_example
[12:04:21] ====================== [PASSED] args =======================
[12:04:21] =================== xe_pci (3 subtests) ====================
[12:04:21] ==================== check_graphics_ip ====================
[12:04:21] [PASSED] 12.00 Xe_LP
[12:04:21] [PASSED] 12.10 Xe_LP+
[12:04:21] [PASSED] 12.55 Xe_HPG
[12:04:21] [PASSED] 12.60 Xe_HPC
[12:04:21] [PASSED] 12.70 Xe_LPG
[12:04:21] [PASSED] 12.71 Xe_LPG
[12:04:21] [PASSED] 12.74 Xe_LPG+
[12:04:21] [PASSED] 20.01 Xe2_HPG
[12:04:21] [PASSED] 20.02 Xe2_HPG
[12:04:21] [PASSED] 20.04 Xe2_LPG
[12:04:21] [PASSED] 30.00 Xe3_LPG
[12:04:21] [PASSED] 30.01 Xe3_LPG
[12:04:21] [PASSED] 30.03 Xe3_LPG
[12:04:21] [PASSED] 30.04 Xe3_LPG
[12:04:21] [PASSED] 30.05 Xe3_LPG
[12:04:21] [PASSED] 35.10 Xe3p_LPG
[12:04:21] [PASSED] 35.11 Xe3p_XPC
[12:04:21] ================ [PASSED] check_graphics_ip ================
[12:04:21] ===================== check_media_ip ======================
[12:04:21] [PASSED] 12.00 Xe_M
[12:04:21] [PASSED] 12.55 Xe_HPM
[12:04:21] [PASSED] 13.00 Xe_LPM+
[12:04:21] [PASSED] 13.01 Xe2_HPM
[12:04:21] [PASSED] 20.00 Xe2_LPM
[12:04:21] [PASSED] 30.00 Xe3_LPM
[12:04:21] [PASSED] 30.02 Xe3_LPM
[12:04:21] [PASSED] 35.00 Xe3p_LPM
[12:04:21] [PASSED] 35.03 Xe3p_HPM
[12:04:21] ================= [PASSED] check_media_ip ==================
[12:04:21] =================== check_platform_desc ===================
[12:04:21] [PASSED] 0x9A60 (TIGERLAKE)
[12:04:21] [PASSED] 0x9A68 (TIGERLAKE)
[12:04:21] [PASSED] 0x9A70 (TIGERLAKE)
[12:04:21] [PASSED] 0x9A40 (TIGERLAKE)
[12:04:21] [PASSED] 0x9A49 (TIGERLAKE)
[12:04:21] [PASSED] 0x9A59 (TIGERLAKE)
[12:04:21] [PASSED] 0x9A78 (TIGERLAKE)
[12:04:21] [PASSED] 0x9AC0 (TIGERLAKE)
[12:04:21] [PASSED] 0x9AC9 (TIGERLAKE)
[12:04:21] [PASSED] 0x9AD9 (TIGERLAKE)
[12:04:21] [PASSED] 0x9AF8 (TIGERLAKE)
[12:04:21] [PASSED] 0x4C80 (ROCKETLAKE)
[12:04:21] [PASSED] 0x4C8A (ROCKETLAKE)
[12:04:21] [PASSED] 0x4C8B (ROCKETLAKE)
[12:04:21] [PASSED] 0x4C8C (ROCKETLAKE)
[12:04:21] [PASSED] 0x4C90 (ROCKETLAKE)
[12:04:21] [PASSED] 0x4C9A (ROCKETLAKE)
[12:04:21] [PASSED] 0x4680 (ALDERLAKE_S)
[12:04:21] [PASSED] 0x4682 (ALDERLAKE_S)
[12:04:21] [PASSED] 0x4688 (ALDERLAKE_S)
[12:04:21] [PASSED] 0x468A (ALDERLAKE_S)
[12:04:21] [PASSED] 0x468B (ALDERLAKE_S)
[12:04:21] [PASSED] 0x4690 (ALDERLAKE_S)
[12:04:21] [PASSED] 0x4692 (ALDERLAKE_S)
[12:04:21] [PASSED] 0x4693 (ALDERLAKE_S)
[12:04:21] [PASSED] 0x46A0 (ALDERLAKE_P)
[12:04:21] [PASSED] 0x46A1 (ALDERLAKE_P)
[12:04:21] [PASSED] 0x46A2 (ALDERLAKE_P)
[12:04:21] [PASSED] 0x46A3 (ALDERLAKE_P)
[12:04:21] [PASSED] 0x46A6 (ALDERLAKE_P)
[12:04:21] [PASSED] 0x46A8 (ALDERLAKE_P)
[12:04:21] [PASSED] 0x46AA (ALDERLAKE_P)
[12:04:21] [PASSED] 0x462A (ALDERLAKE_P)
[12:04:21] [PASSED] 0x4626 (ALDERLAKE_P)
[12:04:21] [PASSED] 0x4628 (ALDERLAKE_P)
[12:04:21] [PASSED] 0x46B0 (ALDERLAKE_P)
[12:04:21] [PASSED] 0x46B1 (ALDERLAKE_P)
[12:04:21] [PASSED] 0x46B2 (ALDERLAKE_P)
[12:04:21] [PASSED] 0x46B3 (ALDERLAKE_P)
[12:04:21] [PASSED] 0x46C0 (ALDERLAKE_P)
[12:04:21] [PASSED] 0x46C1 (ALDERLAKE_P)
[12:04:21] [PASSED] 0x46C2 (ALDERLAKE_P)
[12:04:21] [PASSED] 0x46C3 (ALDERLAKE_P)
[12:04:21] [PASSED] 0x46D0 (ALDERLAKE_N)
[12:04:21] [PASSED] 0x46D1 (ALDERLAKE_N)
[12:04:21] [PASSED] 0x46D2 (ALDERLAKE_N)
[12:04:21] [PASSED] 0x46D3 (ALDERLAKE_N)
[12:04:21] [PASSED] 0x46D4 (ALDERLAKE_N)
[12:04:21] [PASSED] 0xA721 (ALDERLAKE_P)
[12:04:21] [PASSED] 0xA7A1 (ALDERLAKE_P)
[12:04:21] [PASSED] 0xA7A9 (ALDERLAKE_P)
[12:04:21] [PASSED] 0xA7AC (ALDERLAKE_P)
[12:04:21] [PASSED] 0xA7AD (ALDERLAKE_P)
[12:04:21] [PASSED] 0xA720 (ALDERLAKE_P)
[12:04:21] [PASSED] 0xA7A0 (ALDERLAKE_P)
[12:04:21] [PASSED] 0xA7A8 (ALDERLAKE_P)
[12:04:21] [PASSED] 0xA7AA (ALDERLAKE_P)
[12:04:21] [PASSED] 0xA7AB (ALDERLAKE_P)
[12:04:21] [PASSED] 0xA780 (ALDERLAKE_S)
[12:04:21] [PASSED] 0xA781 (ALDERLAKE_S)
[12:04:21] [PASSED] 0xA782 (ALDERLAKE_S)
[12:04:21] [PASSED] 0xA783 (ALDERLAKE_S)
[12:04:21] [PASSED] 0xA788 (ALDERLAKE_S)
[12:04:21] [PASSED] 0xA789 (ALDERLAKE_S)
[12:04:21] [PASSED] 0xA78A (ALDERLAKE_S)
[12:04:21] [PASSED] 0xA78B (ALDERLAKE_S)
[12:04:21] [PASSED] 0x4905 (DG1)
[12:04:21] [PASSED] 0x4906 (DG1)
[12:04:21] [PASSED] 0x4907 (DG1)
[12:04:21] [PASSED] 0x4908 (DG1)
[12:04:21] [PASSED] 0x4909 (DG1)
[12:04:21] [PASSED] 0x56C0 (DG2)
[12:04:21] [PASSED] 0x56C2 (DG2)
[12:04:21] [PASSED] 0x56C1 (DG2)
[12:04:21] [PASSED] 0x7D51 (METEORLAKE)
[12:04:21] [PASSED] 0x7DD1 (METEORLAKE)
[12:04:21] [PASSED] 0x7D41 (METEORLAKE)
[12:04:21] [PASSED] 0x7D67 (METEORLAKE)
[12:04:21] [PASSED] 0xB640 (METEORLAKE)
[12:04:21] [PASSED] 0x56A0 (DG2)
[12:04:21] [PASSED] 0x56A1 (DG2)
[12:04:21] [PASSED] 0x56A2 (DG2)
[12:04:21] [PASSED] 0x56BE (DG2)
[12:04:21] [PASSED] 0x56BF (DG2)
[12:04:21] [PASSED] 0x5690 (DG2)
[12:04:21] [PASSED] 0x5691 (DG2)
[12:04:21] [PASSED] 0x5692 (DG2)
[12:04:21] [PASSED] 0x56A5 (DG2)
[12:04:21] [PASSED] 0x56A6 (DG2)
[12:04:21] [PASSED] 0x56B0 (DG2)
[12:04:21] [PASSED] 0x56B1 (DG2)
[12:04:21] [PASSED] 0x56BA (DG2)
[12:04:21] [PASSED] 0x56BB (DG2)
[12:04:21] [PASSED] 0x56BC (DG2)
[12:04:21] [PASSED] 0x56BD (DG2)
[12:04:21] [PASSED] 0x5693 (DG2)
[12:04:21] [PASSED] 0x5694 (DG2)
[12:04:21] [PASSED] 0x5695 (DG2)
[12:04:21] [PASSED] 0x56A3 (DG2)
[12:04:21] [PASSED] 0x56A4 (DG2)
[12:04:21] [PASSED] 0x56B2 (DG2)
[12:04:21] [PASSED] 0x56B3 (DG2)
[12:04:21] [PASSED] 0x5696 (DG2)
[12:04:21] [PASSED] 0x5697 (DG2)
[12:04:21] [PASSED] 0xB69 (PVC)
[12:04:21] [PASSED] 0xB6E (PVC)
[12:04:21] [PASSED] 0xBD4 (PVC)
[12:04:21] [PASSED] 0xBD5 (PVC)
[12:04:21] [PASSED] 0xBD6 (PVC)
[12:04:21] [PASSED] 0xBD7 (PVC)
[12:04:21] [PASSED] 0xBD8 (PVC)
[12:04:21] [PASSED] 0xBD9 (PVC)
[12:04:21] [PASSED] 0xBDA (PVC)
[12:04:21] [PASSED] 0xBDB (PVC)
[12:04:21] [PASSED] 0xBE0 (PVC)
[12:04:21] [PASSED] 0xBE1 (PVC)
[12:04:21] [PASSED] 0xBE5 (PVC)
[12:04:21] [PASSED] 0x7D40 (METEORLAKE)
[12:04:21] [PASSED] 0x7D45 (METEORLAKE)
[12:04:21] [PASSED] 0x7D55 (METEORLAKE)
[12:04:21] [PASSED] 0x7D60 (METEORLAKE)
[12:04:21] [PASSED] 0x7DD5 (METEORLAKE)
[12:04:21] [PASSED] 0x6420 (LUNARLAKE)
[12:04:21] [PASSED] 0x64A0 (LUNARLAKE)
[12:04:21] [PASSED] 0x64B0 (LUNARLAKE)
[12:04:21] [PASSED] 0xE202 (BATTLEMAGE)
[12:04:21] [PASSED] 0xE209 (BATTLEMAGE)
[12:04:21] [PASSED] 0xE20B (BATTLEMAGE)
[12:04:21] [PASSED] 0xE20C (BATTLEMAGE)
[12:04:21] [PASSED] 0xE20D (BATTLEMAGE)
[12:04:21] [PASSED] 0xE210 (BATTLEMAGE)
[12:04:21] [PASSED] 0xE211 (BATTLEMAGE)
[12:04:21] [PASSED] 0xE212 (BATTLEMAGE)
[12:04:21] [PASSED] 0xE216 (BATTLEMAGE)
[12:04:21] [PASSED] 0xE220 (BATTLEMAGE)
[12:04:21] [PASSED] 0xE221 (BATTLEMAGE)
[12:04:21] [PASSED] 0xE222 (BATTLEMAGE)
[12:04:21] [PASSED] 0xE223 (BATTLEMAGE)
[12:04:21] [PASSED] 0xB080 (PANTHERLAKE)
[12:04:21] [PASSED] 0xB081 (PANTHERLAKE)
[12:04:21] [PASSED] 0xB082 (PANTHERLAKE)
[12:04:21] [PASSED] 0xB083 (PANTHERLAKE)
[12:04:21] [PASSED] 0xB084 (PANTHERLAKE)
[12:04:21] [PASSED] 0xB085 (PANTHERLAKE)
[12:04:21] [PASSED] 0xB086 (PANTHERLAKE)
[12:04:21] [PASSED] 0xB087 (PANTHERLAKE)
[12:04:21] [PASSED] 0xB08F (PANTHERLAKE)
[12:04:21] [PASSED] 0xB090 (PANTHERLAKE)
[12:04:21] [PASSED] 0xB0A0 (PANTHERLAKE)
[12:04:21] [PASSED] 0xB0B0 (PANTHERLAKE)
[12:04:21] [PASSED] 0xFD80 (PANTHERLAKE)
[12:04:21] [PASSED] 0xFD81 (PANTHERLAKE)
[12:04:21] [PASSED] 0xD740 (NOVALAKE_S)
[12:04:21] [PASSED] 0xD741 (NOVALAKE_S)
[12:04:21] [PASSED] 0xD742 (NOVALAKE_S)
[12:04:21] [PASSED] 0xD743 (NOVALAKE_S)
[12:04:21] [PASSED] 0xD745 (NOVALAKE_S)
[12:04:21] [PASSED] 0xD74A (NOVALAKE_S)
[12:04:21] [PASSED] 0xD74B (NOVALAKE_S)
[12:04:21] [PASSED] 0x674C (CRESCENTISLAND)
[12:04:21] [PASSED] 0x674D (CRESCENTISLAND)
[12:04:21] [PASSED] 0x674E (CRESCENTISLAND)
[12:04:21] [PASSED] 0x674F (CRESCENTISLAND)
[12:04:21] [PASSED] 0x6750 (CRESCENTISLAND)
[12:04:21] [PASSED] 0xD750 (NOVALAKE_P)
[12:04:21] [PASSED] 0xD751 (NOVALAKE_P)
[12:04:21] [PASSED] 0xD752 (NOVALAKE_P)
[12:04:21] [PASSED] 0xD753 (NOVALAKE_P)
[12:04:21] [PASSED] 0xD754 (NOVALAKE_P)
[12:04:21] [PASSED] 0xD755 (NOVALAKE_P)
[12:04:21] [PASSED] 0xD756 (NOVALAKE_P)
[12:04:21] [PASSED] 0xD757 (NOVALAKE_P)
[12:04:21] [PASSED] 0xD75F (NOVALAKE_P)
[12:04:21] =============== [PASSED] check_platform_desc ===============
[12:04:21] ===================== [PASSED] xe_pci ======================
[12:04:21] ============= xe_rtp_tables_test (5 subtests) ==============
[12:04:21] ================== xe_rtp_table_gt_test ===================
[12:04:21] [PASSED] gt_was/14011060649
[12:04:21] [PASSED] gt_was/14011059788
[12:04:21] [PASSED] gt_was/14015795083
[12:04:21] [PASSED] gt_was/16021867713
[12:04:21] [PASSED] gt_was/14019449301
[12:04:21] [PASSED] gt_was/16028005424
[12:04:21] [PASSED] gt_was/14026578760
[12:04:21] [PASSED] gt_was/1409420604
[12:04:21] [PASSED] gt_was/1408615072
[12:04:21] [PASSED] gt_was/22010523718
[12:04:21] [PASSED] gt_was/14011006942
[12:04:21] [PASSED] gt_was/14014830051
[12:04:21] [PASSED] gt_was/18018781329
[12:04:21] [PASSED] gt_was/1509235366
[12:04:21] [PASSED] gt_was/18018781329
[12:04:21] [PASSED] gt_was/16016694945
[12:04:21] [PASSED] gt_was/14018575942
[12:04:21] [PASSED] gt_was/22016670082
[12:04:21] [PASSED] gt_was/22016670082
[12:04:21] [PASSED] gt_was/14017421178
[12:04:21] [PASSED] gt_was/16025250150
[12:04:21] [PASSED] gt_was/14021871409
[12:04:21] [PASSED] gt_was/16021865536
[12:04:21] [PASSED] gt_was/14021486841
[12:04:21] [PASSED] gt_was/14025160223
[12:04:21] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[12:04:21] [PASSED] gt_was/14025635424
[12:04:21] [PASSED] gt_was/16028005424
[12:04:21] ============== [PASSED] xe_rtp_table_gt_test ===============
[12:04:21] ================== xe_rtp_table_gt_test ===================
[12:04:21] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[12:04:21] [PASSED] gt_tunings/Tuning: 32B Access Enable
[12:04:21] [PASSED] gt_tunings/Tuning: L3 cache
[12:04:21] [PASSED] gt_tunings/Tuning: L3 cache - media
[12:04:21] [PASSED] gt_tunings/Tuning: Compression Overfetch
[12:04:21] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[12:04:21] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[12:04:21] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[12:04:21] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[12:04:21] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[12:04:21] [PASSED] gt_tunings/Tuning: Stateless compression control
[12:04:21] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[12:04:21] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[12:04:21] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[12:04:21] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[12:04:21] ============== [PASSED] xe_rtp_table_gt_test ===============
[12:04:21] ================== xe_rtp_table_oob_test ==================
[12:04:21] [PASSED] oob_was/1607983814
[12:04:21] [PASSED] oob_was/16010904313
[12:04:21] [PASSED] oob_was/18022495364
[12:04:21] [PASSED] oob_was/22012773006
[12:04:21] [PASSED] oob_was/14014475959
[12:04:21] [PASSED] oob_was/22011391025
[12:04:21] [PASSED] oob_was/22012727170
[12:04:21] [PASSED] oob_was/22012727685
[12:04:21] [PASSED] oob_was/22016596838
[12:04:21] [PASSED] oob_was/18020744125
[12:04:21] [PASSED] oob_was/1409600907
[12:04:21] [PASSED] oob_was/22014953428
[12:04:21] [PASSED] oob_was/16017236439
[12:04:21] [PASSED] oob_was/14019821291
[12:04:21] [PASSED] oob_was/14015076503
[12:04:21] [PASSED] oob_was/14018913170
[12:04:21] [PASSED] oob_was/14018094691
[12:04:21] [PASSED] oob_was/18024947630
[12:04:21] [PASSED] oob_was/16022287689
[12:04:21] [PASSED] oob_was/13011645652
[12:04:21] [PASSED] oob_was/14022293748
[12:04:21] [PASSED] oob_was/22019794406
[12:04:21] [PASSED] oob_was/22019338487
[12:04:21] [PASSED] oob_was/16023588340
[12:04:21] [PASSED] oob_was/14019789679
[12:04:21] [PASSED] oob_was/14022866841
[12:04:21] [PASSED] oob_was/16021333562
[12:04:21] [PASSED] oob_was/14016712196
[12:04:21] [PASSED] oob_was/14015568240
[12:04:21] [PASSED] oob_was/18013179988
[12:04:21] [PASSED] oob_was/1508761755
[12:04:21] [PASSED] oob_was/16023105232
[12:04:21] [PASSED] oob_was/16026508708
[12:04:21] [PASSED] oob_was/14020001231
[12:04:21] [PASSED] oob_was/16023683509
[12:04:21] [PASSED] oob_was/14025515070
[12:04:21] [PASSED] oob_was/15015404425_disable
[12:04:21] [PASSED] oob_was/16026007364
[12:04:21] [PASSED] oob_was/14020316580
[12:04:21] [PASSED] oob_was/14025883347
[12:04:21] [PASSED] oob_was/16029380221
[12:04:21] [PASSED] oob_was/22022079272
[12:04:21] [PASSED] oob_was/16029897822
[12:04:21] [PASSED] oob_was/14027054324
[12:04:21] ============== [PASSED] xe_rtp_table_oob_test ==============
[12:04:21] ================ xe_rtp_table_dev_oob_test ================
[12:04:21] [PASSED] device_oob_was/22010954014
[12:04:21] [PASSED] device_oob_was/15015404425
[12:04:21] [PASSED] device_oob_was/22019338487_display
[12:04:21] [PASSED] device_oob_was/14022085890
[12:04:21] [PASSED] device_oob_was/14026539277
[12:04:21] [PASSED] device_oob_was/14026633728
[12:04:21] [PASSED] device_oob_was/14026746987
[12:04:21] [PASSED] device_oob_was/14026779378
[12:04:21] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[12:04:21] ========== xe_rtp_table_missing_upper_bound_test ==========
[12:04:21] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[12:04:21] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[12:04:21] [PASSED] register_whitelist/1806527549
[12:04:21] [PASSED] register_whitelist/allow_read_ctx_timestamp
[12:04:21] [PASSED] register_whitelist/allow_read_queue_timestamp
[12:04:21] [PASSED] register_whitelist/16014440446
[12:04:21] [PASSED] register_whitelist/16017236439
[12:04:21] [PASSED] register_whitelist/16020183090
[12:04:21] [PASSED] register_whitelist/14024997852
[12:04:21] [PASSED] register_whitelist/14024997852
[12:04:21] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[12:04:21] =============== [PASSED] xe_rtp_tables_test ================
[12:04:21] =================== xe_rtp (3 subtests) ====================
[12:04:21] =================== xe_rtp_rules_tests ====================
[12:04:21] [PASSED] no
[12:04:21] [PASSED] yes
[12:04:21] [PASSED] no-and-no
[12:04:21] [PASSED] no-and-yes
[12:04:21] [PASSED] yes-and-no
[12:04:21] [PASSED] yes-and-yes
[12:04:21] [PASSED] no-or-no
[12:04:21] [PASSED] no-or-yes
[12:04:21] [PASSED] yes-or-no
[12:04:21] [PASSED] yes-or-yes
[12:04:21] [PASSED] no-yes-or-yes-no
[12:04:21] [PASSED] no-yes-or-yes-yes
[12:04:21] [PASSED] yes-yes-or-no-yes
[12:04:21] [PASSED] yes-yes-or-yes-yes
[12:04:21] [PASSED] no-no-or-yes-or-no
[12:04:21] [PASSED] or
[12:04:21] [PASSED] or-yes
[12:04:21] [PASSED] or-no
[12:04:21] [PASSED] yes-or
[12:04:21] [PASSED] no-or
[12:04:21] [PASSED] no-or-or-yes
[12:04:21] [PASSED] yes-or-or-no
[12:04:21] [PASSED] no-or-or-no
[12:04:21] [PASSED] missing-context-engine-class
[12:04:21] [PASSED] missing-context-engine-class-or-yes
[12:04:21] [PASSED] missing-context-engine-class-or-or-yes
[12:04:21] =============== [PASSED] xe_rtp_rules_tests ================
[12:04:21] =============== xe_rtp_process_to_sr_tests ================
[12:04:21] [PASSED] coalesce-same-reg
[12:04:21] [PASSED] coalesce-same-reg-literal-and-func
[12:04:21] [PASSED] no-match-no-add
[12:04:21] [PASSED] two-regs-two-entries
[12:04:21] [PASSED] clr-one-set-other
[12:04:21] [PASSED] set-field
[12:04:21] [PASSED] conflict-duplicate
[12:04:21] [PASSED] conflict-not-disjoint
[12:04:21] [PASSED] conflict-not-disjoint-literal-and-func
[12:04:21] [PASSED] conflict-reg-type
[12:04:21] [PASSED] bad-mcr-reg-forced-to-regular
[12:04:21] [PASSED] bad-regular-reg-forced-to-mcr
[12:04:21] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[12:04:21] ================== xe_rtp_process_tests ===================
[12:04:21] [PASSED] active1
[12:04:21] [PASSED] active2
[12:04:21] [PASSED] active-inactive
[12:04:21] [PASSED] inactive-active
[12:04:21] [PASSED] inactive-active-inactive
[12:04:21] [PASSED] inactive-inactive-inactive
[12:04:21] ============== [PASSED] xe_rtp_process_tests ===============
[12:04:21] ===================== [PASSED] xe_rtp ======================
[12:04:21] ==================== xe_wa (1 subtest) =====================
[12:04:21] ======================== xe_wa_gt =========================
[12:04:21] [PASSED] TIGERLAKE B0
[12:04:21] [PASSED] DG1 A0
[12:04:21] [PASSED] DG1 B0
[12:04:21] [PASSED] ALDERLAKE_S A0
[12:04:21] [PASSED] ALDERLAKE_S B0
[12:04:21] [PASSED] ALDERLAKE_S C0
[12:04:21] [PASSED] ALDERLAKE_S D0
[12:04:21] [PASSED] ALDERLAKE_P A0
[12:04:21] [PASSED] ALDERLAKE_P B0
[12:04:21] [PASSED] ALDERLAKE_P C0
[12:04:21] [PASSED] ALDERLAKE_S RPLS D0
[12:04:21] [PASSED] ALDERLAKE_P RPLU E0
[12:04:21] [PASSED] DG2 G10 C0
[12:04:21] [PASSED] DG2 G11 B1
[12:04:21] [PASSED] DG2 G12 A1
[12:04:21] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:04:21] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:04:21] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[12:04:21] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[12:04:21] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[12:04:21] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[12:04:21] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[12:04:21] ==================== [PASSED] xe_wa_gt =====================
[12:04:21] ====================== [PASSED] xe_wa ======================
[12:04:21] ============================================================
[12:04:21] Testing complete. Ran 742 tests: passed: 724, skipped: 18
[12:04:21] Elapsed time: 36.785s total, 4.333s configuring, 31.785s building, 0.625s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[12:04:21] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:04:23] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:04:48] Starting KUnit Kernel (1/1)...
[12:04:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:04:48] ============ drm_test_pick_cmdline (2 subtests) ============
[12:04:48] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[12:04:48] =============== drm_test_pick_cmdline_named ===============
[12:04:48] [PASSED] NTSC
[12:04:48] [PASSED] NTSC-J
[12:04:48] [PASSED] PAL
[12:04:48] [PASSED] PAL-M
[12:04:48] =========== [PASSED] drm_test_pick_cmdline_named ===========
[12:04:48] ============== [PASSED] drm_test_pick_cmdline ==============
[12:04:48] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[12:04:48] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[12:04:48] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[12:04:48] =========== drm_validate_clone_mode (2 subtests) ===========
[12:04:48] ============== drm_test_check_in_clone_mode ===============
[12:04:48] [PASSED] in_clone_mode
[12:04:48] [PASSED] not_in_clone_mode
[12:04:48] ========== [PASSED] drm_test_check_in_clone_mode ===========
[12:04:48] =============== drm_test_check_valid_clones ===============
[12:04:48] [PASSED] not_in_clone_mode
[12:04:48] [PASSED] valid_clone
[12:04:48] [PASSED] invalid_clone
[12:04:48] =========== [PASSED] drm_test_check_valid_clones ===========
[12:04:48] ============= [PASSED] drm_validate_clone_mode =============
[12:04:48] ============= drm_validate_modeset (1 subtest) =============
[12:04:48] [PASSED] drm_test_check_connector_changed_modeset
[12:04:48] ============== [PASSED] drm_validate_modeset ===============
[12:04:48] ====== drm_test_bridge_get_current_state (1 subtest) =======
[12:04:48] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[12:04:48] ======== [PASSED] drm_test_bridge_get_current_state ========
[12:04:48] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[12:04:48] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[12:04:48] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[12:04:48] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[12:04:48] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[12:04:48] ============== drm_bridge_alloc (2 subtests) ===============
[12:04:48] [PASSED] drm_test_drm_bridge_alloc_basic
[12:04:48] [PASSED] drm_test_drm_bridge_alloc_get_put
[12:04:48] ================ [PASSED] drm_bridge_alloc =================
[12:04:48] ============= drm_bridge_bus_fmt (5 subtests) ==============
[12:04:48] [PASSED] drm_test_bridge_rgb_yuv_rgb
[12:04:48] [PASSED] drm_test_bridge_must_convert_to_yuv444
[12:04:48] [PASSED] drm_test_bridge_hdmi_auto_rgb
[12:04:48] [PASSED] drm_test_bridge_auto_first
[12:04:48] [PASSED] drm_test_bridge_rgb_yuv_no_path
[12:04:48] =============== [PASSED] drm_bridge_bus_fmt ================
[12:04:48] ============= drm_cmdline_parser (40 subtests) =============
[12:04:48] [PASSED] drm_test_cmdline_force_d_only
[12:04:48] [PASSED] drm_test_cmdline_force_D_only_dvi
[12:04:48] [PASSED] drm_test_cmdline_force_D_only_hdmi
[12:04:48] [PASSED] drm_test_cmdline_force_D_only_not_digital
[12:04:48] [PASSED] drm_test_cmdline_force_e_only
[12:04:48] [PASSED] drm_test_cmdline_res
[12:04:48] [PASSED] drm_test_cmdline_res_vesa
[12:04:48] [PASSED] drm_test_cmdline_res_vesa_rblank
[12:04:48] [PASSED] drm_test_cmdline_res_rblank
[12:04:48] [PASSED] drm_test_cmdline_res_bpp
[12:04:48] [PASSED] drm_test_cmdline_res_refresh
[12:04:48] [PASSED] drm_test_cmdline_res_bpp_refresh
[12:04:48] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[12:04:48] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[12:04:48] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[12:04:48] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[12:04:48] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[12:04:48] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[12:04:48] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[12:04:48] [PASSED] drm_test_cmdline_res_margins_force_on
[12:04:48] [PASSED] drm_test_cmdline_res_vesa_margins
[12:04:48] [PASSED] drm_test_cmdline_name
[12:04:48] [PASSED] drm_test_cmdline_name_bpp
[12:04:48] [PASSED] drm_test_cmdline_name_option
[12:04:48] [PASSED] drm_test_cmdline_name_bpp_option
[12:04:48] [PASSED] drm_test_cmdline_rotate_0
[12:04:48] [PASSED] drm_test_cmdline_rotate_90
[12:04:48] [PASSED] drm_test_cmdline_rotate_180
[12:04:48] [PASSED] drm_test_cmdline_rotate_270
[12:04:48] [PASSED] drm_test_cmdline_hmirror
[12:04:48] [PASSED] drm_test_cmdline_vmirror
[12:04:48] [PASSED] drm_test_cmdline_margin_options
[12:04:48] [PASSED] drm_test_cmdline_multiple_options
[12:04:48] [PASSED] drm_test_cmdline_bpp_extra_and_option
[12:04:48] [PASSED] drm_test_cmdline_extra_and_option
[12:04:48] [PASSED] drm_test_cmdline_freestanding_options
[12:04:48] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[12:04:48] [PASSED] drm_test_cmdline_panel_orientation
[12:04:48] ================ drm_test_cmdline_invalid =================
[12:04:48] [PASSED] margin_only
[12:04:48] [PASSED] interlace_only
[12:04:48] [PASSED] res_missing_x
[12:04:48] [PASSED] res_missing_y
[12:04:48] [PASSED] res_bad_y
[12:04:48] [PASSED] res_missing_y_bpp
[12:04:48] [PASSED] res_bad_bpp
[12:04:48] [PASSED] res_bad_refresh
[12:04:48] [PASSED] res_bpp_refresh_force_on_off
[12:04:48] [PASSED] res_invalid_mode
[12:04:48] [PASSED] res_bpp_wrong_place_mode
[12:04:48] [PASSED] name_bpp_refresh
[12:04:48] [PASSED] name_refresh
[12:04:48] [PASSED] name_refresh_wrong_mode
[12:04:48] [PASSED] name_refresh_invalid_mode
[12:04:48] [PASSED] rotate_multiple
[12:04:48] [PASSED] rotate_invalid_val
[12:04:48] [PASSED] rotate_truncated
[12:04:48] [PASSED] invalid_option
[12:04:48] [PASSED] invalid_tv_option
[12:04:48] [PASSED] truncated_tv_option
[12:04:48] ============ [PASSED] drm_test_cmdline_invalid =============
[12:04:48] =============== drm_test_cmdline_tv_options ===============
[12:04:48] [PASSED] NTSC
[12:04:48] [PASSED] NTSC_443
[12:04:48] [PASSED] NTSC_J
[12:04:48] [PASSED] PAL
[12:04:48] [PASSED] PAL_M
[12:04:48] [PASSED] PAL_N
[12:04:48] [PASSED] SECAM
[12:04:48] [PASSED] MONO_525
[12:04:48] [PASSED] MONO_625
[12:04:48] =========== [PASSED] drm_test_cmdline_tv_options ===========
[12:04:48] =============== [PASSED] drm_cmdline_parser ================
[12:04:48] ========== drmm_connector_hdmi_init (20 subtests) ==========
[12:04:48] [PASSED] drm_test_connector_hdmi_init_valid
[12:04:48] [PASSED] drm_test_connector_hdmi_init_bpc_8
[12:04:48] [PASSED] drm_test_connector_hdmi_init_bpc_10
[12:04:48] [PASSED] drm_test_connector_hdmi_init_bpc_12
[12:04:48] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[12:04:48] [PASSED] drm_test_connector_hdmi_init_bpc_null
[12:04:48] [PASSED] drm_test_connector_hdmi_init_formats_empty
[12:04:48] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[12:04:48] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[12:04:48] [PASSED] supported_formats=0x9 yuv420_allowed=1
[12:04:48] [PASSED] supported_formats=0x9 yuv420_allowed=0
[12:04:48] [PASSED] supported_formats=0x5 yuv420_allowed=1
[12:04:48] [PASSED] supported_formats=0x5 yuv420_allowed=0
[12:04:48] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[12:04:48] [PASSED] drm_test_connector_hdmi_init_null_ddc
[12:04:48] [PASSED] drm_test_connector_hdmi_init_null_product
[12:04:48] [PASSED] drm_test_connector_hdmi_init_null_vendor
[12:04:48] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[12:04:48] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[12:04:48] [PASSED] drm_test_connector_hdmi_init_product_valid
[12:04:48] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[12:04:48] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[12:04:48] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[12:04:48] ========= drm_test_connector_hdmi_init_type_valid =========
[12:04:48] [PASSED] HDMI-A
[12:04:48] [PASSED] HDMI-B
[12:04:48] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[12:04:48] ======== drm_test_connector_hdmi_init_type_invalid ========
[12:04:48] [PASSED] Unknown
[12:04:48] [PASSED] VGA
[12:04:48] [PASSED] DVI-I
[12:04:48] [PASSED] DVI-D
[12:04:48] [PASSED] DVI-A
[12:04:48] [PASSED] Composite
[12:04:48] [PASSED] SVIDEO
[12:04:48] [PASSED] LVDS
[12:04:48] [PASSED] Component
[12:04:48] [PASSED] DIN
[12:04:48] [PASSED] DP
[12:04:48] [PASSED] TV
[12:04:48] [PASSED] eDP
[12:04:48] [PASSED] Virtual
[12:04:48] [PASSED] DSI
[12:04:48] [PASSED] DPI
[12:04:48] [PASSED] Writeback
[12:04:48] [PASSED] SPI
[12:04:48] [PASSED] USB
[12:04:48] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[12:04:48] ============ [PASSED] drmm_connector_hdmi_init =============
[12:04:48] ============= drmm_connector_init (3 subtests) =============
[12:04:48] [PASSED] drm_test_drmm_connector_init
[12:04:48] [PASSED] drm_test_drmm_connector_init_null_ddc
[12:04:48] ========= drm_test_drmm_connector_init_type_valid =========
[12:04:48] [PASSED] Unknown
[12:04:48] [PASSED] VGA
[12:04:48] [PASSED] DVI-I
[12:04:48] [PASSED] DVI-D
[12:04:48] [PASSED] DVI-A
[12:04:48] [PASSED] Composite
[12:04:48] [PASSED] SVIDEO
[12:04:48] [PASSED] LVDS
[12:04:48] [PASSED] Component
[12:04:48] [PASSED] DIN
[12:04:48] [PASSED] DP
[12:04:48] [PASSED] HDMI-A
[12:04:48] [PASSED] HDMI-B
[12:04:48] [PASSED] TV
[12:04:48] [PASSED] eDP
[12:04:48] [PASSED] Virtual
[12:04:48] [PASSED] DSI
[12:04:48] [PASSED] DPI
[12:04:48] [PASSED] Writeback
[12:04:48] [PASSED] SPI
[12:04:48] [PASSED] USB
[12:04:48] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[12:04:48] =============== [PASSED] drmm_connector_init ===============
[12:04:48] ========= drm_connector_dynamic_init (6 subtests) ==========
[12:04:48] [PASSED] drm_test_drm_connector_dynamic_init
[12:04:48] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[12:04:48] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[12:04:48] [PASSED] drm_test_drm_connector_dynamic_init_properties
[12:04:48] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[12:04:48] [PASSED] Unknown
[12:04:48] [PASSED] VGA
[12:04:48] [PASSED] DVI-I
[12:04:48] [PASSED] DVI-D
[12:04:48] [PASSED] DVI-A
[12:04:48] [PASSED] Composite
[12:04:48] [PASSED] SVIDEO
[12:04:48] [PASSED] LVDS
[12:04:48] [PASSED] Component
[12:04:48] [PASSED] DIN
[12:04:48] [PASSED] DP
[12:04:48] [PASSED] HDMI-A
[12:04:48] [PASSED] HDMI-B
[12:04:48] [PASSED] TV
[12:04:48] [PASSED] eDP
[12:04:48] [PASSED] Virtual
[12:04:48] [PASSED] DSI
[12:04:48] [PASSED] DPI
[12:04:48] [PASSED] Writeback
[12:04:48] [PASSED] SPI
[12:04:48] [PASSED] USB
[12:04:48] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[12:04:48] ======== drm_test_drm_connector_dynamic_init_name =========
[12:04:48] [PASSED] Unknown
[12:04:48] [PASSED] VGA
[12:04:48] [PASSED] DVI-I
[12:04:48] [PASSED] DVI-D
[12:04:48] [PASSED] DVI-A
[12:04:48] [PASSED] Composite
[12:04:48] [PASSED] SVIDEO
[12:04:48] [PASSED] LVDS
[12:04:48] [PASSED] Component
[12:04:48] [PASSED] DIN
[12:04:48] [PASSED] DP
[12:04:48] [PASSED] HDMI-A
[12:04:48] [PASSED] HDMI-B
[12:04:48] [PASSED] TV
[12:04:48] [PASSED] eDP
[12:04:48] [PASSED] Virtual
[12:04:48] [PASSED] DSI
[12:04:48] [PASSED] DPI
[12:04:48] [PASSED] Writeback
[12:04:48] [PASSED] SPI
[12:04:48] [PASSED] USB
[12:04:48] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[12:04:48] =========== [PASSED] drm_connector_dynamic_init ============
[12:04:48] ==== drm_connector_dynamic_register_early (4 subtests) =====
[12:04:48] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[12:04:48] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[12:04:48] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[12:04:48] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[12:04:48] ====== [PASSED] drm_connector_dynamic_register_early =======
[12:04:48] ======= drm_connector_dynamic_register (7 subtests) ========
[12:04:48] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[12:04:48] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[12:04:48] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[12:04:48] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[12:04:48] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[12:04:48] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[12:04:48] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[12:04:48] ========= [PASSED] drm_connector_dynamic_register ==========
[12:04:48] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[12:04:48] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[12:04:48] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[12:04:48] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[12:04:48] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[12:04:48] ========== drm_test_get_tv_mode_from_name_valid ===========
[12:04:48] [PASSED] NTSC
[12:04:48] [PASSED] NTSC-443
[12:04:48] [PASSED] NTSC-J
[12:04:48] [PASSED] PAL
[12:04:48] [PASSED] PAL-M
[12:04:48] [PASSED] PAL-N
[12:04:48] [PASSED] SECAM
[12:04:48] [PASSED] Mono
[12:04:48] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[12:04:48] [PASSED] drm_test_get_tv_mode_from_name_truncated
[12:04:48] ============ [PASSED] drm_get_tv_mode_from_name ============
[12:04:48] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[12:04:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[12:04:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[12:04:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[12:04:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[12:04:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[12:04:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[12:04:48] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[12:04:48] [PASSED] VIC 96
[12:04:48] [PASSED] VIC 97
[12:04:48] [PASSED] VIC 101
[12:04:48] [PASSED] VIC 102
[12:04:48] [PASSED] VIC 106
[12:04:48] [PASSED] VIC 107
[12:04:48] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[12:04:48] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[12:04:48] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[12:04:48] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[12:04:48] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[12:04:48] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[12:04:48] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[12:04:48] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[12:04:48] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[12:04:48] [PASSED] Automatic
[12:04:48] [PASSED] Full
[12:04:48] [PASSED] Limited 16:235
[12:04:48] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[12:04:48] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[12:04:48] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[12:04:48] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[12:04:48] === drm_test_drm_hdmi_connector_get_output_format_name ====
[12:04:48] [PASSED] RGB
[12:04:48] [PASSED] YUV 4:2:0
[12:04:48] [PASSED] YUV 4:2:2
[12:04:48] [PASSED] YUV 4:4:4
[12:04:48] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[12:04:48] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[12:04:48] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[12:04:48] ============= drm_damage_helper (21 subtests) ==============
[12:04:48] [PASSED] drm_test_damage_iter_no_damage
[12:04:48] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[12:04:48] [PASSED] drm_test_damage_iter_no_damage_src_moved
[12:04:48] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[12:04:48] [PASSED] drm_test_damage_iter_no_damage_not_visible
[12:04:48] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[12:04:48] [PASSED] drm_test_damage_iter_no_damage_no_fb
[12:04:48] [PASSED] drm_test_damage_iter_simple_damage
[12:04:48] [PASSED] drm_test_damage_iter_single_damage
[12:04:48] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[12:04:48] [PASSED] drm_test_damage_iter_single_damage_outside_src
[12:04:48] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[12:04:48] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[12:04:48] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[12:04:48] [PASSED] drm_test_damage_iter_single_damage_src_moved
[12:04:48] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[12:04:48] [PASSED] drm_test_damage_iter_damage
[12:04:48] [PASSED] drm_test_damage_iter_damage_one_intersect
[12:04:48] [PASSED] drm_test_damage_iter_damage_one_outside
[12:04:48] [PASSED] drm_test_damage_iter_damage_src_moved
[12:04:48] [PASSED] drm_test_damage_iter_damage_not_visible
[12:04:48] ================ [PASSED] drm_damage_helper ================
[12:04:48] ============== drm_dp_mst_helper (3 subtests) ==============
[12:04:48] ============== drm_test_dp_mst_calc_pbn_mode ==============
[12:04:48] [PASSED] Clock 154000 BPP 30 DSC disabled
[12:04:48] [PASSED] Clock 234000 BPP 30 DSC disabled
[12:04:48] [PASSED] Clock 297000 BPP 24 DSC disabled
[12:04:48] [PASSED] Clock 332880 BPP 24 DSC enabled
[12:04:48] [PASSED] Clock 324540 BPP 24 DSC enabled
[12:04:48] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[12:04:48] ============== drm_test_dp_mst_calc_pbn_div ===============
[12:04:48] [PASSED] Link rate 2000000 lane count 4
[12:04:48] [PASSED] Link rate 2000000 lane count 2
[12:04:48] [PASSED] Link rate 2000000 lane count 1
[12:04:48] [PASSED] Link rate 1350000 lane count 4
[12:04:48] [PASSED] Link rate 1350000 lane count 2
[12:04:48] [PASSED] Link rate 1350000 lane count 1
[12:04:48] [PASSED] Link rate 1000000 lane count 4
[12:04:48] [PASSED] Link rate 1000000 lane count 2
[12:04:48] [PASSED] Link rate 1000000 lane count 1
[12:04:48] [PASSED] Link rate 810000 lane count 4
[12:04:48] [PASSED] Link rate 810000 lane count 2
[12:04:48] [PASSED] Link rate 810000 lane count 1
[12:04:48] [PASSED] Link rate 540000 lane count 4
[12:04:48] [PASSED] Link rate 540000 lane count 2
[12:04:48] [PASSED] Link rate 540000 lane count 1
[12:04:48] [PASSED] Link rate 270000 lane count 4
[12:04:48] [PASSED] Link rate 270000 lane count 2
[12:04:48] [PASSED] Link rate 270000 lane count 1
[12:04:48] [PASSED] Link rate 162000 lane count 4
[12:04:48] [PASSED] Link rate 162000 lane count 2
[12:04:48] [PASSED] Link rate 162000 lane count 1
[12:04:48] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[12:04:48] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[12:04:48] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[12:04:48] [PASSED] DP_POWER_UP_PHY with port number
[12:04:48] [PASSED] DP_POWER_DOWN_PHY with port number
[12:04:48] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[12:04:48] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[12:04:48] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[12:04:48] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[12:04:48] [PASSED] DP_QUERY_PAYLOAD with port number
[12:04:48] [PASSED] DP_QUERY_PAYLOAD with VCPI
[12:04:48] [PASSED] DP_REMOTE_DPCD_READ with port number
[12:04:48] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[12:04:48] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[12:04:48] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[12:04:48] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[12:04:48] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[12:04:48] [PASSED] DP_REMOTE_I2C_READ with port number
[12:04:48] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[12:04:48] [PASSED] DP_REMOTE_I2C_READ with transactions array
[12:04:48] [PASSED] DP_REMOTE_I2C_WRITE with port number
[12:04:48] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[12:04:48] [PASSED] DP_REMOTE_I2C_WRITE with data array
[12:04:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[12:04:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[12:04:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[12:04:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[12:04:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[12:04:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[12:04:48] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[12:04:48] ================ [PASSED] drm_dp_mst_helper ================
[12:04:48] ================== drm_exec (7 subtests) ===================
[12:04:48] [PASSED] sanitycheck
[12:04:48] [PASSED] test_lock
[12:04:48] [PASSED] test_lock_unlock
[12:04:48] [PASSED] test_duplicates
[12:04:48] [PASSED] test_prepare
[12:04:48] [PASSED] test_prepare_array
[12:04:48] [PASSED] test_multiple_loops
[12:04:48] ==================== [PASSED] drm_exec =====================
[12:04:48] =========== drm_format_helper_test (17 subtests) ===========
[12:04:48] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[12:04:48] [PASSED] single_pixel_source_buffer
[12:04:48] [PASSED] single_pixel_clip_rectangle
[12:04:48] [PASSED] well_known_colors
[12:04:48] [PASSED] destination_pitch
[12:04:48] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[12:04:48] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[12:04:48] [PASSED] single_pixel_source_buffer
[12:04:48] [PASSED] single_pixel_clip_rectangle
[12:04:48] [PASSED] well_known_colors
[12:04:48] [PASSED] destination_pitch
[12:04:48] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[12:04:48] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[12:04:48] [PASSED] single_pixel_source_buffer
[12:04:48] [PASSED] single_pixel_clip_rectangle
[12:04:48] [PASSED] well_known_colors
[12:04:48] [PASSED] destination_pitch
[12:04:48] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[12:04:48] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[12:04:48] [PASSED] single_pixel_source_buffer
[12:04:48] [PASSED] single_pixel_clip_rectangle
[12:04:48] [PASSED] well_known_colors
[12:04:48] [PASSED] destination_pitch
[12:04:48] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[12:04:48] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[12:04:48] [PASSED] single_pixel_source_buffer
[12:04:48] [PASSED] single_pixel_clip_rectangle
[12:04:48] [PASSED] well_known_colors
[12:04:48] [PASSED] destination_pitch
[12:04:48] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[12:04:48] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[12:04:48] [PASSED] single_pixel_source_buffer
[12:04:48] [PASSED] single_pixel_clip_rectangle
[12:04:48] [PASSED] well_known_colors
[12:04:48] [PASSED] destination_pitch
[12:04:48] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[12:04:48] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[12:04:48] [PASSED] single_pixel_source_buffer
[12:04:48] [PASSED] single_pixel_clip_rectangle
[12:04:48] [PASSED] well_known_colors
[12:04:48] [PASSED] destination_pitch
[12:04:48] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[12:04:48] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[12:04:48] [PASSED] single_pixel_source_buffer
[12:04:48] [PASSED] single_pixel_clip_rectangle
[12:04:48] [PASSED] well_known_colors
[12:04:48] [PASSED] destination_pitch
[12:04:48] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[12:04:48] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[12:04:48] [PASSED] single_pixel_source_buffer
[12:04:48] [PASSED] single_pixel_clip_rectangle
[12:04:48] [PASSED] well_known_colors
[12:04:48] [PASSED] destination_pitch
[12:04:48] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[12:04:48] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[12:04:48] [PASSED] single_pixel_source_buffer
[12:04:48] [PASSED] single_pixel_clip_rectangle
[12:04:48] [PASSED] well_known_colors
[12:04:48] [PASSED] destination_pitch
[12:04:48] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[12:04:48] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[12:04:48] [PASSED] single_pixel_source_buffer
[12:04:48] [PASSED] single_pixel_clip_rectangle
[12:04:48] [PASSED] well_known_colors
[12:04:48] [PASSED] destination_pitch
[12:04:48] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[12:04:48] ============== drm_test_fb_xrgb8888_to_mono ===============
[12:04:48] [PASSED] single_pixel_source_buffer
[12:04:48] [PASSED] single_pixel_clip_rectangle
[12:04:48] [PASSED] well_known_colors
[12:04:48] [PASSED] destination_pitch
[12:04:48] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[12:04:48] ==================== drm_test_fb_swab =====================
[12:04:48] [PASSED] single_pixel_source_buffer
[12:04:48] [PASSED] single_pixel_clip_rectangle
[12:04:48] [PASSED] well_known_colors
[12:04:48] [PASSED] destination_pitch
[12:04:48] ================ [PASSED] drm_test_fb_swab =================
[12:04:48] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[12:04:48] [PASSED] single_pixel_source_buffer
[12:04:48] [PASSED] single_pixel_clip_rectangle
[12:04:48] [PASSED] well_known_colors
[12:04:48] [PASSED] destination_pitch
[12:04:48] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[12:04:48] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[12:04:48] [PASSED] single_pixel_source_buffer
[12:04:48] [PASSED] single_pixel_clip_rectangle
[12:04:48] [PASSED] well_known_colors
[12:04:48] [PASSED] destination_pitch
[12:04:48] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[12:04:48] ================= drm_test_fb_clip_offset =================
[12:04:48] [PASSED] pass through
[12:04:48] [PASSED] horizontal offset
[12:04:48] [PASSED] vertical offset
[12:04:48] [PASSED] horizontal and vertical offset
[12:04:48] [PASSED] horizontal offset (custom pitch)
[12:04:48] [PASSED] vertical offset (custom pitch)
[12:04:48] [PASSED] horizontal and vertical offset (custom pitch)
[12:04:48] ============= [PASSED] drm_test_fb_clip_offset =============
[12:04:48] =================== drm_test_fb_memcpy ====================
[12:04:48] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[12:04:48] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[12:04:48] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[12:04:48] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[12:04:48] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[12:04:48] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[12:04:48] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[12:04:48] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[12:04:48] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[12:04:48] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[12:04:48] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[12:04:48] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[12:04:48] =============== [PASSED] drm_test_fb_memcpy ================
[12:04:48] ============= [PASSED] drm_format_helper_test ==============
[12:04:48] ================= drm_format (18 subtests) =================
[12:04:48] [PASSED] drm_test_format_block_width_invalid
[12:04:48] [PASSED] drm_test_format_block_width_one_plane
[12:04:48] [PASSED] drm_test_format_block_width_two_plane
[12:04:48] [PASSED] drm_test_format_block_width_three_plane
[12:04:48] [PASSED] drm_test_format_block_width_tiled
[12:04:48] [PASSED] drm_test_format_block_height_invalid
[12:04:48] [PASSED] drm_test_format_block_height_one_plane
[12:04:48] [PASSED] drm_test_format_block_height_two_plane
[12:04:48] [PASSED] drm_test_format_block_height_three_plane
[12:04:48] [PASSED] drm_test_format_block_height_tiled
[12:04:48] [PASSED] drm_test_format_min_pitch_invalid
[12:04:48] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[12:04:48] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[12:04:48] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[12:04:48] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[12:04:48] [PASSED] drm_test_format_min_pitch_two_plane
[12:04:48] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[12:04:48] [PASSED] drm_test_format_min_pitch_tiled
[12:04:48] =================== [PASSED] drm_format ====================
[12:04:48] ============== drm_framebuffer (10 subtests) ===============
[12:04:48] ========== drm_test_framebuffer_check_src_coords ==========
[12:04:48] [PASSED] Success: source fits into fb
[12:04:48] [PASSED] Fail: overflowing fb with x-axis coordinate
[12:04:48] [PASSED] Fail: overflowing fb with y-axis coordinate
[12:04:48] [PASSED] Fail: overflowing fb with source width
[12:04:48] [PASSED] Fail: overflowing fb with source height
[12:04:48] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[12:04:48] [PASSED] drm_test_framebuffer_cleanup
[12:04:48] =============== drm_test_framebuffer_create ===============
[12:04:48] [PASSED] ABGR8888 normal sizes
[12:04:48] [PASSED] ABGR8888 max sizes
[12:04:48] [PASSED] ABGR8888 pitch greater than min required
[12:04:48] [PASSED] ABGR8888 pitch less than min required
[12:04:48] [PASSED] ABGR8888 Invalid width
[12:04:48] [PASSED] ABGR8888 Invalid buffer handle
[12:04:48] [PASSED] No pixel format
[12:04:48] [PASSED] ABGR8888 Width 0
[12:04:48] [PASSED] ABGR8888 Height 0
[12:04:48] [PASSED] ABGR8888 Out of bound height * pitch combination
[12:04:48] [PASSED] ABGR8888 Large buffer offset
[12:04:48] [PASSED] ABGR8888 Buffer offset for inexistent plane
[12:04:48] [PASSED] ABGR8888 Invalid flag
[12:04:48] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[12:04:48] [PASSED] ABGR8888 Valid buffer modifier
[12:04:48] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[12:04:48] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[12:04:48] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[12:04:48] [PASSED] NV12 Normal sizes
[12:04:48] [PASSED] NV12 Max sizes
[12:04:48] [PASSED] NV12 Invalid pitch
[12:04:48] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[12:04:48] [PASSED] NV12 different modifier per-plane
[12:04:48] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[12:04:48] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[12:04:48] [PASSED] NV12 Modifier for inexistent plane
[12:04:48] [PASSED] NV12 Handle for inexistent plane
[12:04:48] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[12:04:48] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[12:04:48] [PASSED] YVU420 Normal sizes
[12:04:48] [PASSED] YVU420 Max sizes
[12:04:48] [PASSED] YVU420 Invalid pitch
[12:04:48] [PASSED] YVU420 Different pitches
[12:04:48] [PASSED] YVU420 Different buffer offsets/pitches
[12:04:48] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[12:04:48] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[12:04:48] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[12:04:48] [PASSED] YVU420 Valid modifier
[12:04:48] [PASSED] YVU420 Different modifiers per plane
[12:04:48] [PASSED] YVU420 Modifier for inexistent plane
[12:04:48] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[12:04:48] [PASSED] X0L2 Normal sizes
[12:04:48] [PASSED] X0L2 Max sizes
[12:04:48] [PASSED] X0L2 Invalid pitch
[12:04:48] [PASSED] X0L2 Pitch greater than minimum required
[12:04:48] [PASSED] X0L2 Handle for inexistent plane
[12:04:48] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[12:04:48] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[12:04:48] [PASSED] X0L2 Valid modifier
[12:04:48] [PASSED] X0L2 Modifier for inexistent plane
[12:04:48] =========== [PASSED] drm_test_framebuffer_create ===========
[12:04:48] [PASSED] drm_test_framebuffer_free
[12:04:48] [PASSED] drm_test_framebuffer_init
[12:04:48] [PASSED] drm_test_framebuffer_init_bad_format
[12:04:48] [PASSED] drm_test_framebuffer_init_dev_mismatch
[12:04:48] [PASSED] drm_test_framebuffer_lookup
[12:04:48] [PASSED] drm_test_framebuffer_lookup_inexistent
[12:04:48] [PASSED] drm_test_framebuffer_modifiers_not_supported
[12:04:48] ================= [PASSED] drm_framebuffer =================
[12:04:48] ================ drm_gem_shmem (8 subtests) ================
[12:04:48] [PASSED] drm_gem_shmem_test_obj_create
[12:04:48] [PASSED] drm_gem_shmem_test_obj_create_private
[12:04:48] [PASSED] drm_gem_shmem_test_pin_pages
[12:04:48] [PASSED] drm_gem_shmem_test_vmap
[12:04:48] [PASSED] drm_gem_shmem_test_get_sg_table
[12:04:48] [PASSED] drm_gem_shmem_test_get_pages_sgt
[12:04:48] [PASSED] drm_gem_shmem_test_madvise
[12:04:48] [PASSED] drm_gem_shmem_test_purge
[12:04:48] ================== [PASSED] drm_gem_shmem ==================
[12:04:48] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[12:04:48] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[12:04:48] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[12:04:48] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[12:04:48] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[12:04:48] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[12:04:48] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[12:04:48] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[12:04:48] [PASSED] Automatic
[12:04:48] [PASSED] Full
[12:04:48] [PASSED] Limited 16:235
[12:04:48] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[12:04:48] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[12:04:48] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[12:04:48] [PASSED] drm_test_check_disable_connector
[12:04:48] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[12:04:48] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[12:04:48] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[12:04:48] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[12:04:48] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[12:04:48] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[12:04:48] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[12:04:48] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[12:04:48] [PASSED] drm_test_check_output_bpc_dvi
[12:04:48] [PASSED] drm_test_check_output_bpc_format_vic_1
[12:04:48] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[12:04:48] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[12:04:48] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[12:04:48] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[12:04:48] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[12:04:48] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[12:04:48] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[12:04:48] ============ drm_test_check_hdmi_color_format =============
[12:04:48] [PASSED] AUTO -> RGB
[12:04:48] [PASSED] YCBCR422 -> YUV422
[12:04:48] [PASSED] YCBCR420 -> YUV420
[12:04:48] [PASSED] YCBCR444 -> YUV444
[12:04:48] [PASSED] RGB -> RGB
[12:04:48] ======== [PASSED] drm_test_check_hdmi_color_format =========
[12:04:48] ======== drm_test_check_hdmi_color_format_420_only ========
[12:04:48] [PASSED] RGB should fail
[12:04:48] [PASSED] YUV444 should fail
[12:04:48] [PASSED] YUV422 should fail
[12:04:48] [PASSED] YUV420 should work
[12:04:48] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[12:04:48] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[12:04:48] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[12:04:48] [PASSED] drm_test_check_broadcast_rgb_value
[12:04:48] [PASSED] drm_test_check_bpc_8_value
[12:04:48] [PASSED] drm_test_check_bpc_10_value
[12:04:48] [PASSED] drm_test_check_bpc_12_value
[12:04:48] [PASSED] drm_test_check_format_value
[12:04:48] [PASSED] drm_test_check_tmds_char_value
[12:04:48] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[12:04:48] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[12:04:48] [PASSED] drm_test_check_mode_valid
[12:04:48] [PASSED] drm_test_check_mode_valid_reject
[12:04:48] [PASSED] drm_test_check_mode_valid_reject_rate
[12:04:48] [PASSED] drm_test_check_mode_valid_reject_max_clock
[12:04:48] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[12:04:48] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[12:04:48] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[12:04:48] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[12:04:48] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[12:04:48] [PASSED] drm_test_check_infoframes
[12:04:48] [PASSED] drm_test_check_reject_avi_infoframe
[12:04:48] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[12:04:48] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[12:04:48] [PASSED] drm_test_check_reject_audio_infoframe
[12:04:48] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[12:04:48] ================= drm_managed (2 subtests) =================
[12:04:48] [PASSED] drm_test_managed_release_action
[12:04:48] [PASSED] drm_test_managed_run_action
[12:04:48] =================== [PASSED] drm_managed ===================
[12:04:48] =================== drm_mm (6 subtests) ====================
[12:04:48] [PASSED] drm_test_mm_init
[12:04:48] [PASSED] drm_test_mm_debug
[12:04:48] [PASSED] drm_test_mm_align32
[12:04:48] [PASSED] drm_test_mm_align64
[12:04:48] [PASSED] drm_test_mm_lowest
[12:04:48] [PASSED] drm_test_mm_highest
[12:04:48] ===================== [PASSED] drm_mm ======================
[12:04:48] ============= drm_modes_analog_tv (5 subtests) =============
[12:04:48] [PASSED] drm_test_modes_analog_tv_mono_576i
[12:04:48] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[12:04:48] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[12:04:48] [PASSED] drm_test_modes_analog_tv_pal_576i
[12:04:48] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[12:04:48] =============== [PASSED] drm_modes_analog_tv ===============
[12:04:48] ============== drm_plane_helper (2 subtests) ===============
[12:04:48] =============== drm_test_check_plane_state ================
[12:04:48] [PASSED] clipping_simple
[12:04:48] [PASSED] clipping_rotate_reflect
[12:04:48] [PASSED] positioning_simple
[12:04:48] [PASSED] upscaling
[12:04:48] [PASSED] downscaling
[12:04:48] [PASSED] rounding1
[12:04:48] [PASSED] rounding2
[12:04:48] [PASSED] rounding3
[12:04:48] [PASSED] rounding4
[12:04:48] =========== [PASSED] drm_test_check_plane_state ============
[12:04:48] =========== drm_test_check_invalid_plane_state ============
[12:04:48] [PASSED] positioning_invalid
[12:04:48] [PASSED] upscaling_invalid
[12:04:48] [PASSED] downscaling_invalid
[12:04:48] ======= [PASSED] drm_test_check_invalid_plane_state ========
[12:04:48] ================ [PASSED] drm_plane_helper =================
[12:04:48] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[12:04:48] ====== drm_test_connector_helper_tv_get_modes_check =======
[12:04:48] [PASSED] None
[12:04:48] [PASSED] PAL
[12:04:48] [PASSED] NTSC
[12:04:48] [PASSED] Both, NTSC Default
[12:04:48] [PASSED] Both, PAL Default
[12:04:48] [PASSED] Both, NTSC Default, with PAL on command-line
[12:04:48] [PASSED] Both, PAL Default, with NTSC on command-line
[12:04:48] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[12:04:48] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[12:04:48] ================== drm_rect (9 subtests) ===================
[12:04:48] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[12:04:48] [PASSED] drm_test_rect_clip_scaled_not_clipped
[12:04:48] [PASSED] drm_test_rect_clip_scaled_clipped
[12:04:48] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[12:04:48] ================= drm_test_rect_intersect =================
[12:04:48] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[12:04:48] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[12:04:48] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[12:04:48] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[12:04:48] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[12:04:48] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[12:04:48] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[12:04:48] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[12:04:48] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[12:04:48] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[12:04:48] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[12:04:48] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[12:04:48] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[12:04:48] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[12:04:48] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[12:04:48] ============= [PASSED] drm_test_rect_intersect =============
[12:04:48] ================ drm_test_rect_calc_hscale ================
[12:04:48] [PASSED] normal use
[12:04:48] [PASSED] out of max range
[12:04:48] [PASSED] out of min range
[12:04:48] [PASSED] zero dst
[12:04:48] [PASSED] negative src
[12:04:48] [PASSED] negative dst
[12:04:48] ============ [PASSED] drm_test_rect_calc_hscale ============
[12:04:48] ================ drm_test_rect_calc_vscale ================
[12:04:48] [PASSED] normal use
[12:04:48] [PASSED] out of max range
[12:04:48] [PASSED] out of min range
[12:04:48] [PASSED] zero dst
[12:04:48] [PASSED] negative src
[12:04:48] [PASSED] negative dst
[12:04:48] ============ [PASSED] drm_test_rect_calc_vscale ============
[12:04:48] ================== drm_test_rect_rotate ===================
[12:04:48] [PASSED] reflect-x
[12:04:48] [PASSED] reflect-y
[12:04:48] [PASSED] rotate-0
[12:04:48] [PASSED] rotate-90
[12:04:48] [PASSED] rotate-180
[12:04:48] [PASSED] rotate-270
[12:04:48] ============== [PASSED] drm_test_rect_rotate ===============
[12:04:48] ================ drm_test_rect_rotate_inv =================
[12:04:48] [PASSED] reflect-x
[12:04:48] [PASSED] reflect-y
[12:04:48] [PASSED] rotate-0
[12:04:48] [PASSED] rotate-90
[12:04:48] [PASSED] rotate-180
[12:04:48] [PASSED] rotate-270
[12:04:48] ============ [PASSED] drm_test_rect_rotate_inv =============
[12:04:48] ==================== [PASSED] drm_rect =====================
[12:04:48] ============ drm_sysfb_modeset_test (1 subtest) ============
[12:04:48] ============ drm_test_sysfb_build_fourcc_list =============
[12:04:48] [PASSED] no native formats
[12:04:48] [PASSED] XRGB8888 as native format
[12:04:48] [PASSED] remove duplicates
[12:04:48] [PASSED] convert alpha formats
[12:04:48] [PASSED] random formats
[12:04:48] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[12:04:48] ============= [PASSED] drm_sysfb_modeset_test ==============
[12:04:48] ================== drm_fixp (2 subtests) ===================
[12:04:48] [PASSED] drm_test_int2fixp
[12:04:48] [PASSED] drm_test_sm2fixp
[12:04:48] ==================== [PASSED] drm_fixp =====================
[12:04:48] ============================================================
[12:04:48] Testing complete. Ran 637 tests: passed: 637
[12:04:48] Elapsed time: 26.775s total, 1.746s configuring, 24.864s building, 0.134s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[12:04:48] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:04:50] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:05:00] Starting KUnit Kernel (1/1)...
[12:05:00] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:05:00] ================= ttm_device (5 subtests) ==================
[12:05:00] [PASSED] ttm_device_init_basic
[12:05:00] [PASSED] ttm_device_init_multiple
[12:05:00] [PASSED] ttm_device_fini_basic
[12:05:00] [PASSED] ttm_device_init_no_vma_man
[12:05:00] ================== ttm_device_init_pools ==================
[12:05:00] [PASSED] No DMA allocations, no DMA32 required
[12:05:00] [PASSED] DMA allocations, DMA32 required
[12:05:00] [PASSED] No DMA allocations, DMA32 required
[12:05:00] [PASSED] DMA allocations, no DMA32 required
[12:05:00] ============== [PASSED] ttm_device_init_pools ==============
[12:05:00] =================== [PASSED] ttm_device ====================
[12:05:00] ================== ttm_pool (8 subtests) ===================
[12:05:00] ================== ttm_pool_alloc_basic ===================
[12:05:00] [PASSED] One page
[12:05:00] [PASSED] More than one page
[12:05:00] [PASSED] Above the allocation limit
[12:05:00] [PASSED] One page, with coherent DMA mappings enabled
[12:05:00] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:05:00] ============== [PASSED] ttm_pool_alloc_basic ===============
[12:05:00] ============== ttm_pool_alloc_basic_dma_addr ==============
[12:05:00] [PASSED] One page
[12:05:00] [PASSED] More than one page
[12:05:00] [PASSED] Above the allocation limit
[12:05:00] [PASSED] One page, with coherent DMA mappings enabled
[12:05:00] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:05:00] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[12:05:00] [PASSED] ttm_pool_alloc_order_caching_match
[12:05:00] [PASSED] ttm_pool_alloc_caching_mismatch
[12:05:00] [PASSED] ttm_pool_alloc_order_mismatch
[12:05:00] [PASSED] ttm_pool_free_dma_alloc
[12:05:00] [PASSED] ttm_pool_free_no_dma_alloc
[12:05:00] [PASSED] ttm_pool_fini_basic
[12:05:00] ==================== [PASSED] ttm_pool =====================
[12:05:00] ================ ttm_resource (8 subtests) =================
[12:05:00] ================= ttm_resource_init_basic =================
[12:05:00] [PASSED] Init resource in TTM_PL_SYSTEM
[12:05:00] [PASSED] Init resource in TTM_PL_VRAM
[12:05:00] [PASSED] Init resource in a private placement
[12:05:00] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[12:05:00] ============= [PASSED] ttm_resource_init_basic =============
[12:05:00] [PASSED] ttm_resource_init_pinned
[12:05:00] [PASSED] ttm_resource_fini_basic
[12:05:00] [PASSED] ttm_resource_manager_init_basic
[12:05:00] [PASSED] ttm_resource_manager_usage_basic
[12:05:00] [PASSED] ttm_resource_manager_set_used_basic
[12:05:00] [PASSED] ttm_sys_man_alloc_basic
[12:05:00] [PASSED] ttm_sys_man_free_basic
[12:05:00] ================== [PASSED] ttm_resource ===================
[12:05:00] =================== ttm_tt (15 subtests) ===================
[12:05:00] ==================== ttm_tt_init_basic ====================
[12:05:00] [PASSED] Page-aligned size
[12:05:00] [PASSED] Extra pages requested
[12:05:00] ================ [PASSED] ttm_tt_init_basic ================
[12:05:00] [PASSED] ttm_tt_init_misaligned
[12:05:00] [PASSED] ttm_tt_fini_basic
[12:05:00] [PASSED] ttm_tt_fini_sg
[12:05:00] [PASSED] ttm_tt_fini_shmem
[12:05:00] [PASSED] ttm_tt_create_basic
[12:05:00] [PASSED] ttm_tt_create_invalid_bo_type
[12:05:00] [PASSED] ttm_tt_create_ttm_exists
[12:05:00] [PASSED] ttm_tt_create_failed
[12:05:00] [PASSED] ttm_tt_destroy_basic
[12:05:00] [PASSED] ttm_tt_populate_null_ttm
[12:05:00] [PASSED] ttm_tt_populate_populated_ttm
[12:05:00] [PASSED] ttm_tt_unpopulate_basic
[12:05:00] [PASSED] ttm_tt_unpopulate_empty_ttm
[12:05:00] [PASSED] ttm_tt_swapin_basic
[12:05:00] ===================== [PASSED] ttm_tt ======================
[12:05:00] =================== ttm_bo (14 subtests) ===================
[12:05:00] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[12:05:00] [PASSED] Cannot be interrupted and sleeps
[12:05:00] [PASSED] Cannot be interrupted, locks straight away
[12:05:00] [PASSED] Can be interrupted, sleeps
[12:05:00] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[12:05:00] [PASSED] ttm_bo_reserve_locked_no_sleep
[12:05:00] [PASSED] ttm_bo_reserve_no_wait_ticket
[12:05:00] [PASSED] ttm_bo_reserve_double_resv
[12:05:00] [PASSED] ttm_bo_reserve_interrupted
[12:05:00] [PASSED] ttm_bo_reserve_deadlock
[12:05:00] [PASSED] ttm_bo_unreserve_basic
[12:05:00] [PASSED] ttm_bo_unreserve_pinned
[12:05:00] [PASSED] ttm_bo_unreserve_bulk
[12:05:00] [PASSED] ttm_bo_fini_basic
[12:05:00] [PASSED] ttm_bo_fini_shared_resv
[12:05:00] [PASSED] ttm_bo_pin_basic
[12:05:00] [PASSED] ttm_bo_pin_unpin_resource
[12:05:00] [PASSED] ttm_bo_multiple_pin_one_unpin
[12:05:00] ===================== [PASSED] ttm_bo ======================
[12:05:00] ============== ttm_bo_validate (22 subtests) ===============
[12:05:00] ============== ttm_bo_init_reserved_sys_man ===============
[12:05:00] [PASSED] Buffer object for userspace
[12:05:00] [PASSED] Kernel buffer object
[12:05:00] [PASSED] Shared buffer object
[12:05:00] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[12:05:00] ============== ttm_bo_init_reserved_mock_man ==============
[12:05:00] [PASSED] Buffer object for userspace
[12:05:00] [PASSED] Kernel buffer object
[12:05:00] [PASSED] Shared buffer object
[12:05:00] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[12:05:00] [PASSED] ttm_bo_init_reserved_resv
[12:05:00] ================== ttm_bo_validate_basic ==================
[12:05:00] [PASSED] Buffer object for userspace
[12:05:00] [PASSED] Kernel buffer object
[12:05:00] [PASSED] Shared buffer object
[12:05:00] ============== [PASSED] ttm_bo_validate_basic ==============
[12:05:00] [PASSED] ttm_bo_validate_invalid_placement
[12:05:00] ============= ttm_bo_validate_same_placement ==============
[12:05:00] [PASSED] System manager
[12:05:00] [PASSED] VRAM manager
[12:05:00] ========= [PASSED] ttm_bo_validate_same_placement ==========
[12:05:00] [PASSED] ttm_bo_validate_failed_alloc
[12:05:00] [PASSED] ttm_bo_validate_pinned
[12:05:00] [PASSED] ttm_bo_validate_busy_placement
[12:05:00] ================ ttm_bo_validate_multihop =================
[12:05:00] [PASSED] Buffer object for userspace
[12:05:00] [PASSED] Kernel buffer object
[12:05:00] [PASSED] Shared buffer object
[12:05:00] ============ [PASSED] ttm_bo_validate_multihop =============
[12:05:00] ========== ttm_bo_validate_no_placement_signaled ==========
[12:05:00] [PASSED] Buffer object in system domain, no page vector
[12:05:00] [PASSED] Buffer object in system domain with an existing page vector
[12:05:00] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[12:05:00] ======== ttm_bo_validate_no_placement_not_signaled ========
[12:05:00] [PASSED] Buffer object for userspace
[12:05:00] [PASSED] Kernel buffer object
[12:05:00] [PASSED] Shared buffer object
[12:05:00] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[12:05:00] [PASSED] ttm_bo_validate_move_fence_signaled
[12:05:00] ========= ttm_bo_validate_move_fence_not_signaled =========
[12:05:00] [PASSED] Waits for GPU
[12:05:00] [PASSED] Tries to lock straight away
[12:05:00] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[12:05:00] [PASSED] ttm_bo_validate_swapout
[12:05:00] [PASSED] ttm_bo_validate_happy_evict
[12:05:00] [PASSED] ttm_bo_validate_all_pinned_evict
[12:05:00] [PASSED] ttm_bo_validate_allowed_only_evict
[12:05:00] [PASSED] ttm_bo_validate_deleted_evict
[12:05:00] [PASSED] ttm_bo_validate_busy_domain_evict
[12:05:00] [PASSED] ttm_bo_validate_evict_gutting
[12:05:00] [PASSED] ttm_bo_validate_recrusive_evict
[12:05:00] ================= [PASSED] ttm_bo_validate =================
[12:05:00] ============================================================
[12:05:00] Testing complete. Ran 102 tests: passed: 102
[12:05:00] Elapsed time: 11.776s total, 1.756s configuring, 9.805s building, 0.180s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] drm/i915/display: Enable AS SDP Skip Frames
2026-08-03 18:53 ` [PATCH 1/2] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
@ 2026-08-04 16:15 ` Dibin Moolakadan Subrahmanian
0 siblings, 0 replies; 16+ messages in thread
From: Dibin Moolakadan Subrahmanian @ 2026-08-04 16:15 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe; +Cc: animesh.manna
On 8/4/2026 12:23 AM, Uma Shankar wrote:
> When Panel Replay is active the transcoder timing generator runs at the
> panel's maximum refresh rate, but content is often presented at a lower
> rate. In that case the Adaptive-Sync SDP (AS SDP) only needs to reach the
> panel often enough to satisfy its maximum frame time, so transmitting it
> on every frame is redundant and shows up as repeated SDPs on the link.
>
> Xe3LPD adds a HW skip-frame counter in PR_ALPM_CTL that lets the source
> send a single AS SDP and then suppress it for a programmed number of
> frames. Program this counter so that one AS SDP is followed by
> (max_vrefresh / flip_rate - 1) idle frames, matching the effective
> content rate and allowing the link to be driven down to as low as 1Hz
> when the hardware supports it.
>
> The maximum refresh rate is taken from the current mode's vertical
> refresh (adjusted_mode), while the actual flip/content rate is derived
> from the CMRR target (force_cmrr numerator in milli-Hz over the 1000 or
> 1001 denominator). If no CMRR target is programmed the skip counter is
> left at zero, i.e. the feature is a no-op and AS SDP continues to be sent
> on every frame.
>
> ToDo: Currently using CMRR debugfs as an interface to get the flip rate
> from userspace, this will be extended to a property interface to receive
> actual content fps as follow up.
>
> Assisted-by: Claude:claude-opus-4-8
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_alpm.c | 45 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +
> 2 files changed, 47 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index f1383764b702..0f98f02a1848 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -375,6 +375,46 @@ static u32 get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *c
> }
> }
>
> +/*
> + * Periodic Adaptive-Sync SDP skip frames.
> + *
> + * While Panel Replay is active the transcoder timing generator runs at the
> + * panel's maximum refresh rate, but content may be presented at a lower rate.
> + * The Adaptive-Sync SDP only needs to reach the panel often enough to satisfy
> + * its maximum frame time, so transmitting it on every frame is unnecessary and
> + * shows up as repeated SDPs on the link. Program the HW skip counter so that a
> + * single AS SDP is followed by (max_vrefresh / flip_vrefresh - 1) idle frames,
> + * matching the effective content rate.
> + *
> + * ToDo: Actual flip rate is currently passed on by userspace through debugfs
> + * create for CMRRR, but will be extended later as a property interface.
> + */
> +static u32 intel_pr_as_sdp_skip_frames(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + int max_vrefresh = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
> + int flip_vrefresh;
> + u32 skip_frames;
> +
> + /*
> + * Actual (flip) refresh rate comes from the CMRR target: numerator is
> + * in milli-Hz, denominator is 1000 (1:1) or 1001 (1000/1001 timing).
> + */
> + if (!crtc->force_cmrr.numerator || !crtc->force_cmrr.denominator)
> + return 0;
I assume skip frames are valid only when crtc_state->vrr.cmrr.enable is true.
As intel_vrr_cmrr_compute_config() already validates the CMRR parameters before setting this flag,
I think checking crtc_state->vrr.cmrr.enable here should cover all the validations.
> +
> + flip_vrefresh = DIV_ROUND_CLOSEST(crtc->force_cmrr.numerator,
> + crtc->force_cmrr.denominator);
> +
> + if (max_vrefresh <= 0 || flip_vrefresh <= 0 || max_vrefresh <= flip_vrefresh)
> + return 0;
> +
> + skip_frames = max_vrefresh / flip_vrefresh - 1;
> +
> + return min_t(u32, skip_frames,
> + REG_FIELD_MAX(PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK));
> +}
> +
> static void lnl_alpm_configure(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state)
> {
> @@ -410,6 +450,11 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
> else
> pr_alpm_ctl &= ~PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
>
> + /* AS SDP skip frames field only exists on Xe3LPD+ */
> + if (DISPLAY_VER(display) >= 35)
> + pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(
> + intel_pr_as_sdp_skip_frames(crtc_state));
> +
> intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
> pr_alpm_ctl);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 16a9e3af198d..bb577e7e3bbd 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -276,6 +276,8 @@
> #define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2 REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 0)
> #define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1 REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 1)
> #define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2 REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 2)
> +#define PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK REG_GENMASK(27, 16)
> +#define PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(frames) REG_FIELD_PREP(PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK, (frames))
>
> #define _ALPM_CTL_A 0x60950
> #define ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A)
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✗ Xe.CI.BAT: failure for drm/i915/display: Enable AS SDP Skip Frames (rev2)
2026-08-03 18:53 [PATCH 0/2] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
` (6 preceding siblings ...)
2026-08-04 12:05 ` ✓ CI.KUnit: success " Patchwork
@ 2026-08-05 6:03 ` Patchwork
2026-08-05 10:21 ` ✗ CI.checkpatch: warning for drm/i915/display: Enable AS SDP Skip Frames (rev3) Patchwork
` (3 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2026-08-05 6:03 UTC (permalink / raw)
To: Shankar, Uma; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 380 bytes --]
== Series Details ==
Series: drm/i915/display: Enable AS SDP Skip Frames (rev2)
URL : https://patchwork.freedesktop.org/series/162015/
State : failure
== Summary ==
ERROR: The runconfig 'xe-5521-f8d080b47819f01011c1b9c3c875badbb67ec955_BAT' does not exist in the database
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v2/index.html
[-- Attachment #2: Type: text/html, Size: 945 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✗ CI.checkpatch: warning for drm/i915/display: Enable AS SDP Skip Frames (rev3)
2026-08-03 18:53 [PATCH 0/2] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
` (7 preceding siblings ...)
2026-08-05 6:03 ` ✗ Xe.CI.BAT: failure " Patchwork
@ 2026-08-05 10:21 ` Patchwork
2026-08-05 10:23 ` ✓ CI.KUnit: success " Patchwork
` (2 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2026-08-05 10:21 UTC (permalink / raw)
To: Shankar, Uma; +Cc: intel-xe
== Series Details ==
Series: drm/i915/display: Enable AS SDP Skip Frames (rev3)
URL : https://patchwork.freedesktop.org/series/162015/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
061140b9bc586ae7f40abc1249c97e1cc72d1b9d
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 0ef50e0de27f0438fb05fd9b5014a2a8c42469bd
Author: Uma Shankar <uma.shankar@intel.com>
Date: Tue Aug 4 00:23:05 2026 +0530
drm/i915/display: Keep AS SDP flowing when skip frames is enabled
The AS SDP skip-frame mechanism relies on the AS SDP still being
transmitted (just less often) while Panel Replay is active, so the source
must not stop sending it in the PR active state, nor enter the DC3CO idle
protocol which would suppress it entirely.
When a non-zero skip-frame count is programmed, leave both
PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE and
PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL cleared. The previous behaviour
(honouring disable_as_sdp_when_pr_active and the DC3CO idle protocol) is
retained for the non skip-frame case.
Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Naladala Ramanaidu <ramanaidu.naladala@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
+ /mt/dim checkpatch 4c13a67db118ee0019231dbc1362bcb8115ac660 drm-intel
7be27ce4e242 drm/i915/display: Enable AS SDP Skip Frames
-:90: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#90: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:455:
+ pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(
-:105: WARNING:LONG_LINE: line length of 125 exceeds 100 columns
#105: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:280:
+#define PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(frames) REG_FIELD_PREP(PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK, (frames))
total: 0 errors, 1 warnings, 1 checks, 65 lines checked
0ef50e0de27f drm/i915/display: Keep AS SDP flowing when skip frames is enabled
-:55: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#55: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:462:
+ pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
total: 0 errors, 1 warnings, 0 checks, 40 lines checked
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✓ CI.KUnit: success for drm/i915/display: Enable AS SDP Skip Frames (rev3)
2026-08-03 18:53 [PATCH 0/2] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
` (8 preceding siblings ...)
2026-08-05 10:21 ` ✗ CI.checkpatch: warning for drm/i915/display: Enable AS SDP Skip Frames (rev3) Patchwork
@ 2026-08-05 10:23 ` Patchwork
2026-08-05 11:05 ` ✓ Xe.CI.BAT: " Patchwork
2026-08-05 20:52 ` ✗ Xe.CI.FULL: failure " Patchwork
11 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2026-08-05 10:23 UTC (permalink / raw)
To: Shankar, Uma; +Cc: intel-xe
== Series Details ==
Series: drm/i915/display: Enable AS SDP Skip Frames (rev3)
URL : https://patchwork.freedesktop.org/series/162015/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[10:21:58] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:22:03] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:22:35] Starting KUnit Kernel (1/1)...
[10:22:35] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:22:35] ================== guc_buf (11 subtests) ===================
[10:22:35] [PASSED] test_smallest
[10:22:35] [PASSED] test_largest
[10:22:35] [PASSED] test_granular
[10:22:35] [PASSED] test_unique
[10:22:35] [PASSED] test_overlap
[10:22:35] [PASSED] test_reusable
[10:22:35] [PASSED] test_too_big
[10:22:35] [PASSED] test_flush
[10:22:35] [PASSED] test_lookup
[10:22:35] [PASSED] test_data
[10:22:35] [PASSED] test_class
[10:22:35] ===================== [PASSED] guc_buf =====================
[10:22:35] =================== guc_dbm (7 subtests) ===================
[10:22:35] [PASSED] test_empty
[10:22:35] [PASSED] test_default
[10:22:35] ======================== test_size ========================
[10:22:35] [PASSED] 4
[10:22:35] [PASSED] 8
[10:22:35] [PASSED] 32
[10:22:35] [PASSED] 256
[10:22:35] ==================== [PASSED] test_size ====================
[10:22:35] ======================= test_reuse ========================
[10:22:35] [PASSED] 4
[10:22:35] [PASSED] 8
[10:22:35] [PASSED] 32
[10:22:35] [PASSED] 256
[10:22:35] =================== [PASSED] test_reuse ====================
[10:22:35] =================== test_range_overlap ====================
[10:22:35] [PASSED] 4
[10:22:35] [PASSED] 8
[10:22:35] [PASSED] 32
[10:22:35] [PASSED] 256
[10:22:35] =============== [PASSED] test_range_overlap ================
[10:22:35] =================== test_range_compact ====================
[10:22:35] [PASSED] 4
[10:22:35] [PASSED] 8
[10:22:35] [PASSED] 32
[10:22:35] [PASSED] 256
[10:22:35] =============== [PASSED] test_range_compact ================
[10:22:35] ==================== test_range_spare =====================
[10:22:35] [PASSED] 4
[10:22:35] [PASSED] 8
[10:22:35] [PASSED] 32
[10:22:35] [PASSED] 256
[10:22:35] ================ [PASSED] test_range_spare =================
[10:22:35] ===================== [PASSED] guc_dbm =====================
[10:22:35] =================== guc_idm (6 subtests) ===================
[10:22:35] [PASSED] bad_init
[10:22:35] [PASSED] no_init
[10:22:35] [PASSED] init_fini
[10:22:35] [PASSED] check_used
[10:22:35] [PASSED] check_quota
[10:22:35] [PASSED] check_all
[10:22:35] ===================== [PASSED] guc_idm =====================
[10:22:35] =============== guc_klv_helpers (9 subtests) ===============
[10:22:35] [PASSED] test_count
[10:22:35] [PASSED] test_encode_u32
[10:22:35] [PASSED] test_encode_u64
[10:22:35] [PASSED] test_encode_string
[10:22:35] [PASSED] test_encode_object_raw
[10:22:35] [PASSED] test_encode_object_klv
[10:22:35] [PASSED] test_encode_object_nested
[10:22:35] [PASSED] test_encode_object_basic
[10:22:35] [PASSED] test_print
[10:22:35] ================= [PASSED] guc_klv_helpers =================
[10:22:35] ================== no_relay (3 subtests) ===================
[10:22:35] [PASSED] xe_drops_guc2pf_if_not_ready
[10:22:35] [PASSED] xe_drops_guc2vf_if_not_ready
[10:22:35] [PASSED] xe_rejects_send_if_not_ready
[10:22:35] ==================== [PASSED] no_relay =====================
[10:22:35] ================== pf_relay (14 subtests) ==================
[10:22:35] [PASSED] pf_rejects_guc2pf_too_short
[10:22:35] [PASSED] pf_rejects_guc2pf_too_long
[10:22:35] [PASSED] pf_rejects_guc2pf_no_payload
[10:22:35] [PASSED] pf_fails_no_payload
[10:22:35] [PASSED] pf_fails_bad_origin
[10:22:35] [PASSED] pf_fails_bad_type
[10:22:35] [PASSED] pf_txn_reports_error
[10:22:35] [PASSED] pf_txn_sends_pf2guc
[10:22:35] [PASSED] pf_sends_pf2guc
[10:22:35] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[10:22:35] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[10:22:35] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[10:22:35] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[10:22:35] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[10:22:35] ==================== [PASSED] pf_relay =====================
[10:22:35] ================== vf_relay (3 subtests) ===================
[10:22:35] [PASSED] vf_rejects_guc2vf_too_short
[10:22:35] [PASSED] vf_rejects_guc2vf_too_long
[10:22:35] [PASSED] vf_rejects_guc2vf_no_payload
[10:22:35] ==================== [PASSED] vf_relay =====================
[10:22:35] ================ pf_gt_config (9 subtests) =================
[10:22:35] [PASSED] fair_contexts_1vf
[10:22:35] [PASSED] fair_doorbells_1vf
[10:22:35] [PASSED] fair_ggtt_1vf
[10:22:35] ====================== fair_vram_1vf ======================
[10:22:35] [PASSED] 3.50 GiB
[10:22:35] [PASSED] 11.5 GiB
[10:22:35] [PASSED] 15.5 GiB
[10:22:35] [PASSED] 31.5 GiB
[10:22:35] [PASSED] 63.5 GiB
[10:22:35] [PASSED] 1.91 GiB
[10:22:35] ================== [PASSED] fair_vram_1vf ==================
[10:22:35] ================ fair_vram_1vf_admin_only =================
[10:22:35] [PASSED] 3.50 GiB
[10:22:35] [PASSED] 11.5 GiB
[10:22:35] [PASSED] 15.5 GiB
[10:22:35] [PASSED] 31.5 GiB
[10:22:35] [PASSED] 63.5 GiB
[10:22:35] [PASSED] 1.91 GiB
[10:22:35] ============ [PASSED] fair_vram_1vf_admin_only =============
[10:22:35] ====================== fair_contexts ======================
[10:22:35] [PASSED] 1 VF
[10:22:35] [PASSED] 2 VFs
[10:22:35] [PASSED] 3 VFs
[10:22:35] [PASSED] 4 VFs
[10:22:35] [PASSED] 5 VFs
[10:22:35] [PASSED] 6 VFs
[10:22:35] [PASSED] 7 VFs
[10:22:35] [PASSED] 8 VFs
[10:22:35] [PASSED] 9 VFs
[10:22:35] [PASSED] 10 VFs
[10:22:35] [PASSED] 11 VFs
[10:22:35] [PASSED] 12 VFs
[10:22:35] [PASSED] 13 VFs
[10:22:35] [PASSED] 14 VFs
[10:22:35] [PASSED] 15 VFs
[10:22:35] [PASSED] 16 VFs
[10:22:35] [PASSED] 17 VFs
[10:22:35] [PASSED] 18 VFs
[10:22:35] [PASSED] 19 VFs
[10:22:35] [PASSED] 20 VFs
[10:22:35] [PASSED] 21 VFs
[10:22:35] [PASSED] 22 VFs
[10:22:35] [PASSED] 23 VFs
[10:22:35] [PASSED] 24 VFs
[10:22:35] [PASSED] 25 VFs
[10:22:35] [PASSED] 26 VFs
[10:22:35] [PASSED] 27 VFs
[10:22:35] [PASSED] 28 VFs
[10:22:35] [PASSED] 29 VFs
[10:22:35] [PASSED] 30 VFs
[10:22:35] [PASSED] 31 VFs
[10:22:35] [PASSED] 32 VFs
[10:22:35] [PASSED] 33 VFs
[10:22:35] [PASSED] 34 VFs
[10:22:35] [PASSED] 35 VFs
[10:22:35] [PASSED] 36 VFs
[10:22:35] [PASSED] 37 VFs
[10:22:35] [PASSED] 38 VFs
[10:22:35] [PASSED] 39 VFs
[10:22:35] [PASSED] 40 VFs
[10:22:35] [PASSED] 41 VFs
[10:22:35] [PASSED] 42 VFs
[10:22:35] [PASSED] 43 VFs
[10:22:35] [PASSED] 44 VFs
[10:22:35] [PASSED] 45 VFs
[10:22:35] [PASSED] 46 VFs
[10:22:35] [PASSED] 47 VFs
[10:22:35] [PASSED] 48 VFs
[10:22:35] [PASSED] 49 VFs
[10:22:35] [PASSED] 50 VFs
[10:22:35] [PASSED] 51 VFs
[10:22:35] [PASSED] 52 VFs
[10:22:35] [PASSED] 53 VFs
[10:22:35] [PASSED] 54 VFs
[10:22:35] [PASSED] 55 VFs
[10:22:35] [PASSED] 56 VFs
[10:22:35] [PASSED] 57 VFs
[10:22:35] [PASSED] 58 VFs
[10:22:35] [PASSED] 59 VFs
[10:22:35] [PASSED] 60 VFs
[10:22:35] [PASSED] 61 VFs
[10:22:35] [PASSED] 62 VFs
[10:22:35] [PASSED] 63 VFs
[10:22:35] ================== [PASSED] fair_contexts ==================
[10:22:35] ===================== fair_doorbells ======================
[10:22:35] [PASSED] 1 VF
[10:22:35] [PASSED] 2 VFs
[10:22:35] [PASSED] 3 VFs
[10:22:35] [PASSED] 4 VFs
[10:22:35] [PASSED] 5 VFs
[10:22:35] [PASSED] 6 VFs
[10:22:35] [PASSED] 7 VFs
[10:22:35] [PASSED] 8 VFs
[10:22:35] [PASSED] 9 VFs
[10:22:35] [PASSED] 10 VFs
[10:22:35] [PASSED] 11 VFs
[10:22:35] [PASSED] 12 VFs
[10:22:35] [PASSED] 13 VFs
[10:22:35] [PASSED] 14 VFs
[10:22:35] [PASSED] 15 VFs
[10:22:35] [PASSED] 16 VFs
[10:22:35] [PASSED] 17 VFs
[10:22:35] [PASSED] 18 VFs
[10:22:35] [PASSED] 19 VFs
[10:22:35] [PASSED] 20 VFs
[10:22:35] [PASSED] 21 VFs
[10:22:35] [PASSED] 22 VFs
[10:22:35] [PASSED] 23 VFs
[10:22:35] [PASSED] 24 VFs
[10:22:35] [PASSED] 25 VFs
[10:22:35] [PASSED] 26 VFs
[10:22:35] [PASSED] 27 VFs
[10:22:35] [PASSED] 28 VFs
[10:22:35] [PASSED] 29 VFs
[10:22:35] [PASSED] 30 VFs
[10:22:35] [PASSED] 31 VFs
[10:22:35] [PASSED] 32 VFs
[10:22:35] [PASSED] 33 VFs
[10:22:35] [PASSED] 34 VFs
[10:22:35] [PASSED] 35 VFs
[10:22:35] [PASSED] 36 VFs
[10:22:35] [PASSED] 37 VFs
[10:22:35] [PASSED] 38 VFs
[10:22:35] [PASSED] 39 VFs
[10:22:35] [PASSED] 40 VFs
[10:22:35] [PASSED] 41 VFs
[10:22:35] [PASSED] 42 VFs
[10:22:35] [PASSED] 43 VFs
[10:22:35] [PASSED] 44 VFs
[10:22:35] [PASSED] 45 VFs
[10:22:35] [PASSED] 46 VFs
[10:22:35] [PASSED] 47 VFs
[10:22:35] [PASSED] 48 VFs
[10:22:35] [PASSED] 49 VFs
[10:22:35] [PASSED] 50 VFs
[10:22:35] [PASSED] 51 VFs
[10:22:35] [PASSED] 52 VFs
[10:22:35] [PASSED] 53 VFs
[10:22:35] [PASSED] 54 VFs
[10:22:35] [PASSED] 55 VFs
[10:22:35] [PASSED] 56 VFs
[10:22:35] [PASSED] 57 VFs
[10:22:35] [PASSED] 58 VFs
[10:22:35] [PASSED] 59 VFs
[10:22:35] [PASSED] 60 VFs
[10:22:35] [PASSED] 61 VFs
[10:22:35] [PASSED] 62 VFs
[10:22:35] [PASSED] 63 VFs
[10:22:35] ================= [PASSED] fair_doorbells ==================
[10:22:35] ======================== fair_ggtt ========================
[10:22:35] [PASSED] 1 VF
[10:22:35] [PASSED] 2 VFs
[10:22:35] [PASSED] 3 VFs
[10:22:35] [PASSED] 4 VFs
[10:22:35] [PASSED] 5 VFs
[10:22:35] [PASSED] 6 VFs
[10:22:35] [PASSED] 7 VFs
[10:22:35] [PASSED] 8 VFs
[10:22:35] [PASSED] 9 VFs
[10:22:35] [PASSED] 10 VFs
[10:22:35] [PASSED] 11 VFs
[10:22:35] [PASSED] 12 VFs
[10:22:35] [PASSED] 13 VFs
[10:22:35] [PASSED] 14 VFs
[10:22:35] [PASSED] 15 VFs
[10:22:35] [PASSED] 16 VFs
[10:22:35] [PASSED] 17 VFs
[10:22:35] [PASSED] 18 VFs
[10:22:35] [PASSED] 19 VFs
[10:22:35] [PASSED] 20 VFs
[10:22:35] [PASSED] 21 VFs
[10:22:35] [PASSED] 22 VFs
[10:22:35] [PASSED] 23 VFs
[10:22:35] [PASSED] 24 VFs
[10:22:35] [PASSED] 25 VFs
[10:22:35] [PASSED] 26 VFs
[10:22:35] [PASSED] 27 VFs
[10:22:35] [PASSED] 28 VFs
[10:22:35] [PASSED] 29 VFs
[10:22:35] [PASSED] 30 VFs
[10:22:35] [PASSED] 31 VFs
[10:22:35] [PASSED] 32 VFs
[10:22:35] [PASSED] 33 VFs
[10:22:35] [PASSED] 34 VFs
[10:22:35] [PASSED] 35 VFs
[10:22:35] [PASSED] 36 VFs
[10:22:35] [PASSED] 37 VFs
[10:22:35] [PASSED] 38 VFs
[10:22:35] [PASSED] 39 VFs
[10:22:35] [PASSED] 40 VFs
[10:22:35] [PASSED] 41 VFs
[10:22:35] [PASSED] 42 VFs
[10:22:35] [PASSED] 43 VFs
[10:22:35] [PASSED] 44 VFs
[10:22:35] [PASSED] 45 VFs
[10:22:35] [PASSED] 46 VFs
[10:22:35] [PASSED] 47 VFs
[10:22:35] [PASSED] 48 VFs
[10:22:35] [PASSED] 49 VFs
[10:22:35] [PASSED] 50 VFs
[10:22:35] [PASSED] 51 VFs
[10:22:35] [PASSED] 52 VFs
[10:22:35] [PASSED] 53 VFs
[10:22:35] [PASSED] 54 VFs
[10:22:35] [PASSED] 55 VFs
[10:22:35] [PASSED] 56 VFs
[10:22:35] [PASSED] 57 VFs
[10:22:35] [PASSED] 58 VFs
[10:22:35] [PASSED] 59 VFs
[10:22:35] [PASSED] 60 VFs
[10:22:35] [PASSED] 61 VFs
[10:22:35] [PASSED] 62 VFs
[10:22:35] [PASSED] 63 VFs
[10:22:35] ==================== [PASSED] fair_ggtt ====================
[10:22:35] ======================== fair_vram ========================
[10:22:35] [PASSED] 1 VF
[10:22:35] [PASSED] 2 VFs
[10:22:35] [PASSED] 3 VFs
[10:22:35] [PASSED] 4 VFs
[10:22:35] [PASSED] 5 VFs
[10:22:35] [PASSED] 6 VFs
[10:22:35] [PASSED] 7 VFs
[10:22:35] [PASSED] 8 VFs
[10:22:35] [PASSED] 9 VFs
[10:22:35] [PASSED] 10 VFs
[10:22:35] [PASSED] 11 VFs
[10:22:35] [PASSED] 12 VFs
[10:22:35] [PASSED] 13 VFs
[10:22:35] [PASSED] 14 VFs
[10:22:35] [PASSED] 15 VFs
[10:22:35] [PASSED] 16 VFs
[10:22:35] [PASSED] 17 VFs
[10:22:35] [PASSED] 18 VFs
[10:22:35] [PASSED] 19 VFs
[10:22:35] [PASSED] 20 VFs
[10:22:35] [PASSED] 21 VFs
[10:22:35] [PASSED] 22 VFs
[10:22:35] [PASSED] 23 VFs
[10:22:35] [PASSED] 24 VFs
[10:22:35] [PASSED] 25 VFs
[10:22:35] [PASSED] 26 VFs
[10:22:35] [PASSED] 27 VFs
[10:22:35] [PASSED] 28 VFs
[10:22:35] [PASSED] 29 VFs
[10:22:35] [PASSED] 30 VFs
[10:22:35] [PASSED] 31 VFs
[10:22:35] [PASSED] 32 VFs
[10:22:35] [PASSED] 33 VFs
[10:22:35] [PASSED] 34 VFs
[10:22:35] [PASSED] 35 VFs
[10:22:35] [PASSED] 36 VFs
[10:22:35] [PASSED] 37 VFs
[10:22:35] [PASSED] 38 VFs
[10:22:35] [PASSED] 39 VFs
[10:22:35] [PASSED] 40 VFs
[10:22:35] [PASSED] 41 VFs
[10:22:35] [PASSED] 42 VFs
[10:22:35] [PASSED] 43 VFs
[10:22:35] [PASSED] 44 VFs
[10:22:35] [PASSED] 45 VFs
[10:22:35] [PASSED] 46 VFs
[10:22:35] [PASSED] 47 VFs
[10:22:35] [PASSED] 48 VFs
[10:22:35] [PASSED] 49 VFs
[10:22:35] [PASSED] 50 VFs
[10:22:35] [PASSED] 51 VFs
[10:22:35] [PASSED] 52 VFs
[10:22:35] [PASSED] 53 VFs
[10:22:35] [PASSED] 54 VFs
[10:22:35] [PASSED] 55 VFs
[10:22:35] [PASSED] 56 VFs
[10:22:35] [PASSED] 57 VFs
[10:22:35] [PASSED] 58 VFs
[10:22:35] [PASSED] 59 VFs
[10:22:35] [PASSED] 60 VFs
[10:22:35] [PASSED] 61 VFs
[10:22:35] [PASSED] 62 VFs
[10:22:35] [PASSED] 63 VFs
[10:22:35] ==================== [PASSED] fair_vram ====================
[10:22:35] ================== [PASSED] pf_gt_config ===================
[10:22:35] ===================== lmtt (1 subtest) =====================
[10:22:35] ======================== test_ops =========================
[10:22:35] [PASSED] 2-level
[10:22:35] [PASSED] multi-level
[10:22:35] ==================== [PASSED] test_ops =====================
[10:22:35] ====================== [PASSED] lmtt =======================
[10:22:35] ================= sriov_packet (1 subtest) =================
[10:22:35] [PASSED] test_descriptor_init
[10:22:35] ================== [PASSED] sriov_packet ===================
[10:22:35] ================= pf_service (11 subtests) =================
[10:22:35] [PASSED] pf_negotiate_any
[10:22:35] [PASSED] pf_negotiate_base_match
[10:22:35] [PASSED] pf_negotiate_base_newer
[10:22:35] [PASSED] pf_negotiate_base_next
[10:22:35] [SKIPPED] pf_negotiate_base_older (no older minor)
[10:22:35] [PASSED] pf_negotiate_base_prev
[10:22:35] [PASSED] pf_negotiate_latest_match
[10:22:35] [PASSED] pf_negotiate_latest_newer
[10:22:35] [PASSED] pf_negotiate_latest_next
[10:22:35] [SKIPPED] pf_negotiate_latest_older (no older minor)
[10:22:35] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[10:22:35] =================== [PASSED] pf_service ====================
[10:22:35] ================= xe_guc_g2g (2 subtests) ==================
[10:22:35] ============== xe_live_guc_g2g_kunit_default ==============
[10:22:35] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[10:22:35] ============== xe_live_guc_g2g_kunit_allmem ===============
[10:22:35] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[10:22:35] =================== [SKIPPED] xe_guc_g2g ===================
[10:22:35] =================== xe_mocs (2 subtests) ===================
[10:22:35] ================ xe_live_mocs_kernel_kunit ================
[10:22:35] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[10:22:35] ================ xe_live_mocs_reset_kunit =================
[10:22:35] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[10:22:35] ==================== [SKIPPED] xe_mocs =====================
[10:22:35] ================= xe_migrate (2 subtests) ==================
[10:22:35] ================= xe_migrate_sanity_kunit =================
[10:22:35] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[10:22:35] ================== xe_validate_ccs_kunit ==================
[10:22:35] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[10:22:35] =================== [SKIPPED] xe_migrate ===================
[10:22:35] ================== xe_dma_buf (1 subtest) ==================
[10:22:35] ==================== xe_dma_buf_kunit =====================
[10:22:35] ================ [SKIPPED] xe_dma_buf_kunit ================
[10:22:35] =================== [SKIPPED] xe_dma_buf ===================
[10:22:35] ================= xe_bo_shrink (1 subtest) =================
[10:22:35] =================== xe_bo_shrink_kunit ====================
[10:22:35] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[10:22:35] ================== [SKIPPED] xe_bo_shrink ==================
[10:22:35] ==================== xe_bo (2 subtests) ====================
[10:22:35] ================== xe_ccs_migrate_kunit ===================
[10:22:35] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[10:22:35] ==================== xe_bo_evict_kunit ====================
[10:22:35] =============== [SKIPPED] xe_bo_evict_kunit ================
[10:22:35] ===================== [SKIPPED] xe_bo ======================
[10:22:35] ==================== args (13 subtests) ====================
[10:22:35] [PASSED] count_args_test
[10:22:35] [PASSED] call_args_example
[10:22:35] [PASSED] call_args_test
[10:22:35] [PASSED] drop_first_arg_example
[10:22:35] [PASSED] drop_first_arg_test
[10:22:35] [PASSED] first_arg_example
[10:22:35] [PASSED] first_arg_test
[10:22:35] [PASSED] last_arg_example
[10:22:35] [PASSED] last_arg_test
[10:22:35] [PASSED] pick_arg_example
[10:22:35] [PASSED] if_args_example
[10:22:35] [PASSED] if_args_test
[10:22:35] [PASSED] sep_comma_example
[10:22:35] ====================== [PASSED] args =======================
[10:22:35] =================== xe_pci (3 subtests) ====================
[10:22:35] ==================== check_graphics_ip ====================
[10:22:35] [PASSED] 12.00 Xe_LP
[10:22:35] [PASSED] 12.10 Xe_LP+
[10:22:35] [PASSED] 12.55 Xe_HPG
[10:22:35] [PASSED] 12.60 Xe_HPC
[10:22:35] [PASSED] 12.70 Xe_LPG
[10:22:35] [PASSED] 12.71 Xe_LPG
[10:22:35] [PASSED] 12.74 Xe_LPG+
[10:22:35] [PASSED] 20.01 Xe2_HPG
[10:22:35] [PASSED] 20.02 Xe2_HPG
[10:22:35] [PASSED] 20.04 Xe2_LPG
[10:22:35] [PASSED] 30.00 Xe3_LPG
[10:22:35] [PASSED] 30.01 Xe3_LPG
[10:22:35] [PASSED] 30.03 Xe3_LPG
[10:22:35] [PASSED] 30.04 Xe3_LPG
[10:22:35] [PASSED] 30.05 Xe3_LPG
[10:22:35] [PASSED] 35.10 Xe3p_LPG
[10:22:35] [PASSED] 35.11 Xe3p_XPC
[10:22:35] ================ [PASSED] check_graphics_ip ================
[10:22:35] ===================== check_media_ip ======================
[10:22:35] [PASSED] 12.00 Xe_M
[10:22:35] [PASSED] 12.55 Xe_HPM
[10:22:35] [PASSED] 13.00 Xe_LPM+
[10:22:35] [PASSED] 13.01 Xe2_HPM
[10:22:35] [PASSED] 20.00 Xe2_LPM
[10:22:35] [PASSED] 30.00 Xe3_LPM
[10:22:35] [PASSED] 30.02 Xe3_LPM
[10:22:35] [PASSED] 35.00 Xe3p_LPM
[10:22:35] [PASSED] 35.03 Xe3p_HPM
[10:22:35] ================= [PASSED] check_media_ip ==================
[10:22:35] =================== check_platform_desc ===================
[10:22:35] [PASSED] 0x9A60 (TIGERLAKE)
[10:22:35] [PASSED] 0x9A68 (TIGERLAKE)
[10:22:35] [PASSED] 0x9A70 (TIGERLAKE)
[10:22:35] [PASSED] 0x9A40 (TIGERLAKE)
[10:22:35] [PASSED] 0x9A49 (TIGERLAKE)
[10:22:35] [PASSED] 0x9A59 (TIGERLAKE)
[10:22:35] [PASSED] 0x9A78 (TIGERLAKE)
[10:22:35] [PASSED] 0x9AC0 (TIGERLAKE)
[10:22:35] [PASSED] 0x9AC9 (TIGERLAKE)
[10:22:35] [PASSED] 0x9AD9 (TIGERLAKE)
[10:22:35] [PASSED] 0x9AF8 (TIGERLAKE)
[10:22:35] [PASSED] 0x4C80 (ROCKETLAKE)
[10:22:35] [PASSED] 0x4C8A (ROCKETLAKE)
[10:22:35] [PASSED] 0x4C8B (ROCKETLAKE)
[10:22:35] [PASSED] 0x4C8C (ROCKETLAKE)
[10:22:35] [PASSED] 0x4C90 (ROCKETLAKE)
[10:22:35] [PASSED] 0x4C9A (ROCKETLAKE)
[10:22:35] [PASSED] 0x4680 (ALDERLAKE_S)
[10:22:35] [PASSED] 0x4682 (ALDERLAKE_S)
[10:22:35] [PASSED] 0x4688 (ALDERLAKE_S)
[10:22:35] [PASSED] 0x468A (ALDERLAKE_S)
[10:22:35] [PASSED] 0x468B (ALDERLAKE_S)
[10:22:35] [PASSED] 0x4690 (ALDERLAKE_S)
[10:22:35] [PASSED] 0x4692 (ALDERLAKE_S)
[10:22:35] [PASSED] 0x4693 (ALDERLAKE_S)
[10:22:35] [PASSED] 0x46A0 (ALDERLAKE_P)
[10:22:35] [PASSED] 0x46A1 (ALDERLAKE_P)
[10:22:35] [PASSED] 0x46A2 (ALDERLAKE_P)
[10:22:35] [PASSED] 0x46A3 (ALDERLAKE_P)
[10:22:35] [PASSED] 0x46A6 (ALDERLAKE_P)
[10:22:35] [PASSED] 0x46A8 (ALDERLAKE_P)
[10:22:35] [PASSED] 0x46AA (ALDERLAKE_P)
[10:22:35] [PASSED] 0x462A (ALDERLAKE_P)
[10:22:35] [PASSED] 0x4626 (ALDERLAKE_P)
[10:22:35] [PASSED] 0x4628 (ALDERLAKE_P)
[10:22:35] [PASSED] 0x46B0 (ALDERLAKE_P)
[10:22:35] [PASSED] 0x46B1 (ALDERLAKE_P)
[10:22:35] [PASSED] 0x46B2 (ALDERLAKE_P)
[10:22:35] [PASSED] 0x46B3 (ALDERLAKE_P)
[10:22:35] [PASSED] 0x46C0 (ALDERLAKE_P)
[10:22:35] [PASSED] 0x46C1 (ALDERLAKE_P)
[10:22:35] [PASSED] 0x46C2 (ALDERLAKE_P)
[10:22:35] [PASSED] 0x46C3 (ALDERLAKE_P)
[10:22:35] [PASSED] 0x46D0 (ALDERLAKE_N)
[10:22:35] [PASSED] 0x46D1 (ALDERLAKE_N)
[10:22:35] [PASSED] 0x46D2 (ALDERLAKE_N)
[10:22:35] [PASSED] 0x46D3 (ALDERLAKE_N)
[10:22:35] [PASSED] 0x46D4 (ALDERLAKE_N)
[10:22:35] [PASSED] 0xA721 (ALDERLAKE_P)
[10:22:35] [PASSED] 0xA7A1 (ALDERLAKE_P)
[10:22:35] [PASSED] 0xA7A9 (ALDERLAKE_P)
[10:22:35] [PASSED] 0xA7AC (ALDERLAKE_P)
[10:22:35] [PASSED] 0xA7AD (ALDERLAKE_P)
[10:22:35] [PASSED] 0xA720 (ALDERLAKE_P)
[10:22:35] [PASSED] 0xA7A0 (ALDERLAKE_P)
[10:22:35] [PASSED] 0xA7A8 (ALDERLAKE_P)
[10:22:35] [PASSED] 0xA7AA (ALDERLAKE_P)
[10:22:35] [PASSED] 0xA7AB (ALDERLAKE_P)
[10:22:35] [PASSED] 0xA780 (ALDERLAKE_S)
[10:22:35] [PASSED] 0xA781 (ALDERLAKE_S)
[10:22:35] [PASSED] 0xA782 (ALDERLAKE_S)
[10:22:35] [PASSED] 0xA783 (ALDERLAKE_S)
[10:22:35] [PASSED] 0xA788 (ALDERLAKE_S)
[10:22:35] [PASSED] 0xA789 (ALDERLAKE_S)
[10:22:35] [PASSED] 0xA78A (ALDERLAKE_S)
[10:22:35] [PASSED] 0xA78B (ALDERLAKE_S)
[10:22:35] [PASSED] 0x4905 (DG1)
[10:22:35] [PASSED] 0x4906 (DG1)
[10:22:35] [PASSED] 0x4907 (DG1)
[10:22:35] [PASSED] 0x4908 (DG1)
[10:22:35] [PASSED] 0x4909 (DG1)
[10:22:35] [PASSED] 0x56C0 (DG2)
[10:22:35] [PASSED] 0x56C2 (DG2)
[10:22:35] [PASSED] 0x56C1 (DG2)
[10:22:35] [PASSED] 0x7D51 (METEORLAKE)
[10:22:35] [PASSED] 0x7DD1 (METEORLAKE)
[10:22:35] [PASSED] 0x7D41 (METEORLAKE)
[10:22:35] [PASSED] 0x7D67 (METEORLAKE)
[10:22:35] [PASSED] 0xB640 (METEORLAKE)
[10:22:35] [PASSED] 0x56A0 (DG2)
[10:22:35] [PASSED] 0x56A1 (DG2)
[10:22:35] [PASSED] 0x56A2 (DG2)
[10:22:35] [PASSED] 0x56BE (DG2)
[10:22:35] [PASSED] 0x56BF (DG2)
[10:22:35] [PASSED] 0x5690 (DG2)
[10:22:35] [PASSED] 0x5691 (DG2)
[10:22:35] [PASSED] 0x5692 (DG2)
[10:22:35] [PASSED] 0x56A5 (DG2)
[10:22:35] [PASSED] 0x56A6 (DG2)
[10:22:35] [PASSED] 0x56B0 (DG2)
[10:22:35] [PASSED] 0x56B1 (DG2)
[10:22:35] [PASSED] 0x56BA (DG2)
[10:22:35] [PASSED] 0x56BB (DG2)
[10:22:35] [PASSED] 0x56BC (DG2)
[10:22:35] [PASSED] 0x56BD (DG2)
[10:22:35] [PASSED] 0x5693 (DG2)
[10:22:35] [PASSED] 0x5694 (DG2)
[10:22:35] [PASSED] 0x5695 (DG2)
[10:22:35] [PASSED] 0x56A3 (DG2)
[10:22:35] [PASSED] 0x56A4 (DG2)
[10:22:35] [PASSED] 0x56B2 (DG2)
[10:22:35] [PASSED] 0x56B3 (DG2)
[10:22:35] [PASSED] 0x5696 (DG2)
[10:22:35] [PASSED] 0x5697 (DG2)
[10:22:35] [PASSED] 0xB69 (PVC)
[10:22:35] [PASSED] 0xB6E (PVC)
[10:22:35] [PASSED] 0xBD4 (PVC)
[10:22:35] [PASSED] 0xBD5 (PVC)
[10:22:35] [PASSED] 0xBD6 (PVC)
[10:22:35] [PASSED] 0xBD7 (PVC)
[10:22:35] [PASSED] 0xBD8 (PVC)
[10:22:35] [PASSED] 0xBD9 (PVC)
[10:22:35] [PASSED] 0xBDA (PVC)
[10:22:35] [PASSED] 0xBDB (PVC)
[10:22:35] [PASSED] 0xBE0 (PVC)
[10:22:35] [PASSED] 0xBE1 (PVC)
[10:22:35] [PASSED] 0xBE5 (PVC)
[10:22:35] [PASSED] 0x7D40 (METEORLAKE)
[10:22:35] [PASSED] 0x7D45 (METEORLAKE)
[10:22:35] [PASSED] 0x7D55 (METEORLAKE)
[10:22:35] [PASSED] 0x7D60 (METEORLAKE)
[10:22:35] [PASSED] 0x7DD5 (METEORLAKE)
[10:22:35] [PASSED] 0x6420 (LUNARLAKE)
[10:22:35] [PASSED] 0x64A0 (LUNARLAKE)
[10:22:35] [PASSED] 0x64B0 (LUNARLAKE)
[10:22:35] [PASSED] 0xE202 (BATTLEMAGE)
[10:22:35] [PASSED] 0xE209 (BATTLEMAGE)
[10:22:35] [PASSED] 0xE20B (BATTLEMAGE)
[10:22:35] [PASSED] 0xE20C (BATTLEMAGE)
[10:22:35] [PASSED] 0xE20D (BATTLEMAGE)
[10:22:35] [PASSED] 0xE210 (BATTLEMAGE)
[10:22:35] [PASSED] 0xE211 (BATTLEMAGE)
[10:22:35] [PASSED] 0xE212 (BATTLEMAGE)
[10:22:35] [PASSED] 0xE216 (BATTLEMAGE)
[10:22:35] [PASSED] 0xE220 (BATTLEMAGE)
[10:22:35] [PASSED] 0xE221 (BATTLEMAGE)
[10:22:35] [PASSED] 0xE222 (BATTLEMAGE)
[10:22:35] [PASSED] 0xE223 (BATTLEMAGE)
[10:22:35] [PASSED] 0xB080 (PANTHERLAKE)
[10:22:35] [PASSED] 0xB081 (PANTHERLAKE)
[10:22:35] [PASSED] 0xB082 (PANTHERLAKE)
[10:22:35] [PASSED] 0xB083 (PANTHERLAKE)
[10:22:35] [PASSED] 0xB084 (PANTHERLAKE)
[10:22:35] [PASSED] 0xB085 (PANTHERLAKE)
[10:22:35] [PASSED] 0xB086 (PANTHERLAKE)
[10:22:35] [PASSED] 0xB087 (PANTHERLAKE)
[10:22:35] [PASSED] 0xB08F (PANTHERLAKE)
[10:22:35] [PASSED] 0xB090 (PANTHERLAKE)
[10:22:35] [PASSED] 0xB0A0 (PANTHERLAKE)
[10:22:35] [PASSED] 0xB0B0 (PANTHERLAKE)
[10:22:35] [PASSED] 0xFD80 (PANTHERLAKE)
[10:22:35] [PASSED] 0xFD81 (PANTHERLAKE)
[10:22:35] [PASSED] 0xD740 (NOVALAKE_S)
[10:22:35] [PASSED] 0xD741 (NOVALAKE_S)
[10:22:35] [PASSED] 0xD742 (NOVALAKE_S)
[10:22:35] [PASSED] 0xD743 (NOVALAKE_S)
[10:22:35] [PASSED] 0xD745 (NOVALAKE_S)
[10:22:35] [PASSED] 0xD74A (NOVALAKE_S)
[10:22:35] [PASSED] 0xD74B (NOVALAKE_S)
[10:22:35] [PASSED] 0x674C (CRESCENTISLAND)
[10:22:35] [PASSED] 0x674D (CRESCENTISLAND)
[10:22:35] [PASSED] 0x674E (CRESCENTISLAND)
[10:22:35] [PASSED] 0x674F (CRESCENTISLAND)
[10:22:35] [PASSED] 0x6750 (CRESCENTISLAND)
[10:22:35] [PASSED] 0xD750 (NOVALAKE_P)
[10:22:35] [PASSED] 0xD751 (NOVALAKE_P)
[10:22:35] [PASSED] 0xD752 (NOVALAKE_P)
[10:22:35] [PASSED] 0xD753 (NOVALAKE_P)
[10:22:35] [PASSED] 0xD754 (NOVALAKE_P)
[10:22:35] [PASSED] 0xD755 (NOVALAKE_P)
[10:22:35] [PASSED] 0xD756 (NOVALAKE_P)
[10:22:35] [PASSED] 0xD757 (NOVALAKE_P)
[10:22:35] [PASSED] 0xD75F (NOVALAKE_P)
[10:22:35] =============== [PASSED] check_platform_desc ===============
[10:22:35] ===================== [PASSED] xe_pci ======================
[10:22:35] ============= xe_rtp_tables_test (5 subtests) ==============
[10:22:35] ================== xe_rtp_table_gt_test ===================
[10:22:35] [PASSED] gt_was/14011060649
[10:22:35] [PASSED] gt_was/14011059788
[10:22:35] [PASSED] gt_was/14015795083
[10:22:35] [PASSED] gt_was/16021867713
[10:22:35] [PASSED] gt_was/14019449301
[10:22:35] [PASSED] gt_was/16028005424
[10:22:35] [PASSED] gt_was/14026578760
[10:22:35] [PASSED] gt_was/1409420604
[10:22:35] [PASSED] gt_was/1408615072
[10:22:35] [PASSED] gt_was/22010523718
[10:22:35] [PASSED] gt_was/14011006942
[10:22:35] [PASSED] gt_was/14014830051
[10:22:35] [PASSED] gt_was/18018781329
[10:22:35] [PASSED] gt_was/1509235366
[10:22:35] [PASSED] gt_was/18018781329
[10:22:35] [PASSED] gt_was/16016694945
[10:22:35] [PASSED] gt_was/14018575942
[10:22:35] [PASSED] gt_was/22016670082
[10:22:35] [PASSED] gt_was/22016670082
[10:22:35] [PASSED] gt_was/14017421178
[10:22:35] [PASSED] gt_was/16025250150
[10:22:35] [PASSED] gt_was/14021871409
[10:22:35] [PASSED] gt_was/16021865536
[10:22:35] [PASSED] gt_was/14021486841
[10:22:35] [PASSED] gt_was/14025160223
[10:22:35] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[10:22:35] [PASSED] gt_was/14025635424
[10:22:35] [PASSED] gt_was/16028005424
[10:22:35] ============== [PASSED] xe_rtp_table_gt_test ===============
[10:22:35] ================== xe_rtp_table_gt_test ===================
[10:22:35] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[10:22:35] [PASSED] gt_tunings/Tuning: 32B Access Enable
[10:22:35] [PASSED] gt_tunings/Tuning: L3 cache
[10:22:35] [PASSED] gt_tunings/Tuning: L3 cache - media
[10:22:35] [PASSED] gt_tunings/Tuning: Compression Overfetch
[10:22:35] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[10:22:35] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[10:22:35] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[10:22:35] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[10:22:35] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[10:22:35] [PASSED] gt_tunings/Tuning: Stateless compression control
[10:22:35] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[10:22:35] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[10:22:35] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[10:22:35] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[10:22:35] ============== [PASSED] xe_rtp_table_gt_test ===============
[10:22:35] ================== xe_rtp_table_oob_test ==================
[10:22:35] [PASSED] oob_was/1607983814
[10:22:35] [PASSED] oob_was/16010904313
[10:22:35] [PASSED] oob_was/18022495364
[10:22:35] [PASSED] oob_was/22012773006
[10:22:35] [PASSED] oob_was/14014475959
[10:22:35] [PASSED] oob_was/22011391025
[10:22:35] [PASSED] oob_was/22012727170
[10:22:35] [PASSED] oob_was/22012727685
[10:22:35] [PASSED] oob_was/22016596838
[10:22:35] [PASSED] oob_was/18020744125
[10:22:35] [PASSED] oob_was/1409600907
[10:22:35] [PASSED] oob_was/22014953428
[10:22:35] [PASSED] oob_was/16017236439
[10:22:35] [PASSED] oob_was/14019821291
[10:22:35] [PASSED] oob_was/14015076503
[10:22:35] [PASSED] oob_was/14018913170
[10:22:35] [PASSED] oob_was/14018094691
[10:22:35] [PASSED] oob_was/18024947630
[10:22:35] [PASSED] oob_was/16022287689
[10:22:35] [PASSED] oob_was/13011645652
[10:22:35] [PASSED] oob_was/14022293748
[10:22:35] [PASSED] oob_was/22019794406
[10:22:35] [PASSED] oob_was/22019338487
[10:22:35] [PASSED] oob_was/16023588340
[10:22:35] [PASSED] oob_was/14019789679
[10:22:35] [PASSED] oob_was/14022866841
[10:22:35] [PASSED] oob_was/16021333562
[10:22:35] [PASSED] oob_was/14016712196
[10:22:35] [PASSED] oob_was/14015568240
[10:22:35] [PASSED] oob_was/18013179988
[10:22:35] [PASSED] oob_was/1508761755
[10:22:35] [PASSED] oob_was/16023105232
[10:22:35] [PASSED] oob_was/16026508708
[10:22:35] [PASSED] oob_was/14020001231
[10:22:35] [PASSED] oob_was/16023683509
[10:22:35] [PASSED] oob_was/14025515070
[10:22:35] [PASSED] oob_was/15015404425_disable
[10:22:35] [PASSED] oob_was/16026007364
[10:22:35] [PASSED] oob_was/14020316580
[10:22:35] [PASSED] oob_was/14025883347
[10:22:35] [PASSED] oob_was/16029380221
[10:22:35] [PASSED] oob_was/22022079272
[10:22:35] [PASSED] oob_was/16029897822
[10:22:35] [PASSED] oob_was/14027054324
[10:22:35] ============== [PASSED] xe_rtp_table_oob_test ==============
[10:22:35] ================ xe_rtp_table_dev_oob_test ================
[10:22:35] [PASSED] device_oob_was/22010954014
[10:22:35] [PASSED] device_oob_was/15015404425
[10:22:35] [PASSED] device_oob_was/22019338487_display
[10:22:35] [PASSED] device_oob_was/14022085890
[10:22:35] [PASSED] device_oob_was/14026539277
[10:22:35] [PASSED] device_oob_was/14026633728
[10:22:35] [PASSED] device_oob_was/14026746987
[10:22:35] [PASSED] device_oob_was/14026779378
[10:22:35] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[10:22:35] ========== xe_rtp_table_missing_upper_bound_test ==========
[10:22:35] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[10:22:35] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[10:22:35] [PASSED] register_whitelist/1806527549
[10:22:35] [PASSED] register_whitelist/allow_read_ctx_timestamp
[10:22:35] [PASSED] register_whitelist/allow_read_queue_timestamp
[10:22:35] [PASSED] register_whitelist/16014440446
[10:22:35] [PASSED] register_whitelist/16017236439
[10:22:35] [PASSED] register_whitelist/16020183090
[10:22:35] [PASSED] register_whitelist/14024997852
[10:22:35] [PASSED] register_whitelist/14024997852
[10:22:35] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[10:22:35] =============== [PASSED] xe_rtp_tables_test ================
[10:22:35] =================== xe_rtp (3 subtests) ====================
[10:22:35] =================== xe_rtp_rules_tests ====================
[10:22:35] [PASSED] no
[10:22:35] [PASSED] yes
[10:22:35] [PASSED] no-and-no
[10:22:35] [PASSED] no-and-yes
[10:22:35] [PASSED] yes-and-no
[10:22:35] [PASSED] yes-and-yes
[10:22:35] [PASSED] no-or-no
[10:22:35] [PASSED] no-or-yes
[10:22:35] [PASSED] yes-or-no
[10:22:35] [PASSED] yes-or-yes
[10:22:35] [PASSED] no-yes-or-yes-no
[10:22:35] [PASSED] no-yes-or-yes-yes
[10:22:35] [PASSED] yes-yes-or-no-yes
[10:22:35] [PASSED] yes-yes-or-yes-yes
[10:22:35] [PASSED] no-no-or-yes-or-no
[10:22:35] [PASSED] or
[10:22:35] [PASSED] or-yes
[10:22:35] [PASSED] or-no
[10:22:35] [PASSED] yes-or
[10:22:35] [PASSED] no-or
[10:22:35] [PASSED] no-or-or-yes
[10:22:35] [PASSED] yes-or-or-no
[10:22:35] [PASSED] no-or-or-no
[10:22:35] [PASSED] missing-context-engine-class
[10:22:35] [PASSED] missing-context-engine-class-or-yes
[10:22:35] [PASSED] missing-context-engine-class-or-or-yes
[10:22:35] =============== [PASSED] xe_rtp_rules_tests ================
[10:22:35] =============== xe_rtp_process_to_sr_tests ================
[10:22:35] [PASSED] coalesce-same-reg
[10:22:35] [PASSED] coalesce-same-reg-literal-and-func
[10:22:35] [PASSED] no-match-no-add
[10:22:35] [PASSED] two-regs-two-entries
[10:22:35] [PASSED] clr-one-set-other
[10:22:35] [PASSED] set-field
[10:22:35] [PASSED] conflict-duplicate
[10:22:35] [PASSED] conflict-not-disjoint
[10:22:35] [PASSED] conflict-not-disjoint-literal-and-func
[10:22:35] [PASSED] conflict-reg-type
[10:22:35] [PASSED] bad-mcr-reg-forced-to-regular
[10:22:35] [PASSED] bad-regular-reg-forced-to-mcr
[10:22:35] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[10:22:35] ================== xe_rtp_process_tests ===================
[10:22:35] [PASSED] active1
[10:22:35] [PASSED] active2
[10:22:35] [PASSED] active-inactive
[10:22:35] [PASSED] inactive-active
[10:22:35] [PASSED] inactive-active-inactive
[10:22:35] [PASSED] inactive-inactive-inactive
[10:22:35] ============== [PASSED] xe_rtp_process_tests ===============
[10:22:35] ===================== [PASSED] xe_rtp ======================
[10:22:35] ==================== xe_wa (1 subtest) =====================
[10:22:35] ======================== xe_wa_gt =========================
[10:22:35] [PASSED] TIGERLAKE B0
[10:22:35] [PASSED] DG1 A0
[10:22:35] [PASSED] DG1 B0
[10:22:35] [PASSED] ALDERLAKE_S A0
[10:22:35] [PASSED] ALDERLAKE_S B0
[10:22:35] [PASSED] ALDERLAKE_S C0
[10:22:35] [PASSED] ALDERLAKE_S D0
[10:22:35] [PASSED] ALDERLAKE_P A0
[10:22:35] [PASSED] ALDERLAKE_P B0
[10:22:35] [PASSED] ALDERLAKE_P C0
[10:22:35] [PASSED] ALDERLAKE_S RPLS D0
[10:22:35] [PASSED] ALDERLAKE_P RPLU E0
[10:22:35] [PASSED] DG2 G10 C0
[10:22:35] [PASSED] DG2 G11 B1
[10:22:35] [PASSED] DG2 G12 A1
[10:22:35] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:22:35] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:22:35] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[10:22:35] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[10:22:35] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[10:22:35] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[10:22:35] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[10:22:35] ==================== [PASSED] xe_wa_gt =====================
[10:22:35] ====================== [PASSED] xe_wa ======================
[10:22:35] ============================================================
[10:22:35] Testing complete. Ran 742 tests: passed: 724, skipped: 18
[10:22:35] Elapsed time: 36.854s total, 4.307s configuring, 31.881s building, 0.642s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[10:22:35] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:22:37] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:23:02] Starting KUnit Kernel (1/1)...
[10:23:02] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:23:02] ============ drm_test_pick_cmdline (2 subtests) ============
[10:23:02] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[10:23:02] =============== drm_test_pick_cmdline_named ===============
[10:23:02] [PASSED] NTSC
[10:23:02] [PASSED] NTSC-J
[10:23:02] [PASSED] PAL
[10:23:02] [PASSED] PAL-M
[10:23:02] =========== [PASSED] drm_test_pick_cmdline_named ===========
[10:23:02] ============== [PASSED] drm_test_pick_cmdline ==============
[10:23:02] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[10:23:02] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[10:23:02] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[10:23:02] =========== drm_validate_clone_mode (2 subtests) ===========
[10:23:02] ============== drm_test_check_in_clone_mode ===============
[10:23:02] [PASSED] in_clone_mode
[10:23:02] [PASSED] not_in_clone_mode
[10:23:02] ========== [PASSED] drm_test_check_in_clone_mode ===========
[10:23:02] =============== drm_test_check_valid_clones ===============
[10:23:02] [PASSED] not_in_clone_mode
[10:23:02] [PASSED] valid_clone
[10:23:02] [PASSED] invalid_clone
[10:23:02] =========== [PASSED] drm_test_check_valid_clones ===========
[10:23:02] ============= [PASSED] drm_validate_clone_mode =============
[10:23:02] ============= drm_validate_modeset (1 subtest) =============
[10:23:02] [PASSED] drm_test_check_connector_changed_modeset
[10:23:02] ============== [PASSED] drm_validate_modeset ===============
[10:23:02] ====== drm_test_bridge_get_current_state (1 subtest) =======
[10:23:02] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[10:23:02] ======== [PASSED] drm_test_bridge_get_current_state ========
[10:23:02] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[10:23:02] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[10:23:02] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[10:23:02] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[10:23:02] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[10:23:02] ============== drm_bridge_alloc (2 subtests) ===============
[10:23:02] [PASSED] drm_test_drm_bridge_alloc_basic
[10:23:02] [PASSED] drm_test_drm_bridge_alloc_get_put
[10:23:02] ================ [PASSED] drm_bridge_alloc =================
[10:23:02] ============= drm_bridge_bus_fmt (5 subtests) ==============
[10:23:02] [PASSED] drm_test_bridge_rgb_yuv_rgb
[10:23:02] [PASSED] drm_test_bridge_must_convert_to_yuv444
[10:23:02] [PASSED] drm_test_bridge_hdmi_auto_rgb
[10:23:02] [PASSED] drm_test_bridge_auto_first
[10:23:02] [PASSED] drm_test_bridge_rgb_yuv_no_path
[10:23:02] =============== [PASSED] drm_bridge_bus_fmt ================
[10:23:02] ============= drm_cmdline_parser (40 subtests) =============
[10:23:02] [PASSED] drm_test_cmdline_force_d_only
[10:23:02] [PASSED] drm_test_cmdline_force_D_only_dvi
[10:23:02] [PASSED] drm_test_cmdline_force_D_only_hdmi
[10:23:02] [PASSED] drm_test_cmdline_force_D_only_not_digital
[10:23:02] [PASSED] drm_test_cmdline_force_e_only
[10:23:02] [PASSED] drm_test_cmdline_res
[10:23:02] [PASSED] drm_test_cmdline_res_vesa
[10:23:02] [PASSED] drm_test_cmdline_res_vesa_rblank
[10:23:02] [PASSED] drm_test_cmdline_res_rblank
[10:23:02] [PASSED] drm_test_cmdline_res_bpp
[10:23:02] [PASSED] drm_test_cmdline_res_refresh
[10:23:02] [PASSED] drm_test_cmdline_res_bpp_refresh
[10:23:02] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[10:23:02] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[10:23:02] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[10:23:02] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[10:23:02] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[10:23:02] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[10:23:02] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[10:23:02] [PASSED] drm_test_cmdline_res_margins_force_on
[10:23:02] [PASSED] drm_test_cmdline_res_vesa_margins
[10:23:02] [PASSED] drm_test_cmdline_name
[10:23:02] [PASSED] drm_test_cmdline_name_bpp
[10:23:02] [PASSED] drm_test_cmdline_name_option
[10:23:02] [PASSED] drm_test_cmdline_name_bpp_option
[10:23:02] [PASSED] drm_test_cmdline_rotate_0
[10:23:02] [PASSED] drm_test_cmdline_rotate_90
[10:23:02] [PASSED] drm_test_cmdline_rotate_180
[10:23:02] [PASSED] drm_test_cmdline_rotate_270
[10:23:02] [PASSED] drm_test_cmdline_hmirror
[10:23:02] [PASSED] drm_test_cmdline_vmirror
[10:23:02] [PASSED] drm_test_cmdline_margin_options
[10:23:02] [PASSED] drm_test_cmdline_multiple_options
[10:23:02] [PASSED] drm_test_cmdline_bpp_extra_and_option
[10:23:02] [PASSED] drm_test_cmdline_extra_and_option
[10:23:02] [PASSED] drm_test_cmdline_freestanding_options
[10:23:02] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[10:23:02] [PASSED] drm_test_cmdline_panel_orientation
[10:23:02] ================ drm_test_cmdline_invalid =================
[10:23:02] [PASSED] margin_only
[10:23:02] [PASSED] interlace_only
[10:23:02] [PASSED] res_missing_x
[10:23:02] [PASSED] res_missing_y
[10:23:02] [PASSED] res_bad_y
[10:23:02] [PASSED] res_missing_y_bpp
[10:23:02] [PASSED] res_bad_bpp
[10:23:02] [PASSED] res_bad_refresh
[10:23:02] [PASSED] res_bpp_refresh_force_on_off
[10:23:02] [PASSED] res_invalid_mode
[10:23:02] [PASSED] res_bpp_wrong_place_mode
[10:23:02] [PASSED] name_bpp_refresh
[10:23:02] [PASSED] name_refresh
[10:23:02] [PASSED] name_refresh_wrong_mode
[10:23:02] [PASSED] name_refresh_invalid_mode
[10:23:02] [PASSED] rotate_multiple
[10:23:02] [PASSED] rotate_invalid_val
[10:23:02] [PASSED] rotate_truncated
[10:23:02] [PASSED] invalid_option
[10:23:02] [PASSED] invalid_tv_option
[10:23:02] [PASSED] truncated_tv_option
[10:23:02] ============ [PASSED] drm_test_cmdline_invalid =============
[10:23:02] =============== drm_test_cmdline_tv_options ===============
[10:23:02] [PASSED] NTSC
[10:23:02] [PASSED] NTSC_443
[10:23:02] [PASSED] NTSC_J
[10:23:02] [PASSED] PAL
[10:23:02] [PASSED] PAL_M
[10:23:02] [PASSED] PAL_N
[10:23:02] [PASSED] SECAM
[10:23:02] [PASSED] MONO_525
[10:23:02] [PASSED] MONO_625
[10:23:02] =========== [PASSED] drm_test_cmdline_tv_options ===========
[10:23:02] =============== [PASSED] drm_cmdline_parser ================
[10:23:02] ========== drmm_connector_hdmi_init (20 subtests) ==========
[10:23:02] [PASSED] drm_test_connector_hdmi_init_valid
[10:23:02] [PASSED] drm_test_connector_hdmi_init_bpc_8
[10:23:02] [PASSED] drm_test_connector_hdmi_init_bpc_10
[10:23:02] [PASSED] drm_test_connector_hdmi_init_bpc_12
[10:23:02] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[10:23:02] [PASSED] drm_test_connector_hdmi_init_bpc_null
[10:23:02] [PASSED] drm_test_connector_hdmi_init_formats_empty
[10:23:02] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[10:23:02] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[10:23:02] [PASSED] supported_formats=0x9 yuv420_allowed=1
[10:23:02] [PASSED] supported_formats=0x9 yuv420_allowed=0
[10:23:02] [PASSED] supported_formats=0x5 yuv420_allowed=1
[10:23:02] [PASSED] supported_formats=0x5 yuv420_allowed=0
[10:23:02] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[10:23:02] [PASSED] drm_test_connector_hdmi_init_null_ddc
[10:23:02] [PASSED] drm_test_connector_hdmi_init_null_product
[10:23:02] [PASSED] drm_test_connector_hdmi_init_null_vendor
[10:23:02] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[10:23:02] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[10:23:02] [PASSED] drm_test_connector_hdmi_init_product_valid
[10:23:02] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[10:23:02] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[10:23:02] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[10:23:02] ========= drm_test_connector_hdmi_init_type_valid =========
[10:23:02] [PASSED] HDMI-A
[10:23:02] [PASSED] HDMI-B
[10:23:02] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[10:23:02] ======== drm_test_connector_hdmi_init_type_invalid ========
[10:23:02] [PASSED] Unknown
[10:23:02] [PASSED] VGA
[10:23:02] [PASSED] DVI-I
[10:23:02] [PASSED] DVI-D
[10:23:02] [PASSED] DVI-A
[10:23:02] [PASSED] Composite
[10:23:02] [PASSED] SVIDEO
[10:23:02] [PASSED] LVDS
[10:23:02] [PASSED] Component
[10:23:02] [PASSED] DIN
[10:23:02] [PASSED] DP
[10:23:02] [PASSED] TV
[10:23:02] [PASSED] eDP
[10:23:02] [PASSED] Virtual
[10:23:02] [PASSED] DSI
[10:23:02] [PASSED] DPI
[10:23:02] [PASSED] Writeback
[10:23:02] [PASSED] SPI
[10:23:02] [PASSED] USB
[10:23:02] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[10:23:02] ============ [PASSED] drmm_connector_hdmi_init =============
[10:23:02] ============= drmm_connector_init (3 subtests) =============
[10:23:02] [PASSED] drm_test_drmm_connector_init
[10:23:02] [PASSED] drm_test_drmm_connector_init_null_ddc
[10:23:02] ========= drm_test_drmm_connector_init_type_valid =========
[10:23:02] [PASSED] Unknown
[10:23:02] [PASSED] VGA
[10:23:02] [PASSED] DVI-I
[10:23:02] [PASSED] DVI-D
[10:23:02] [PASSED] DVI-A
[10:23:02] [PASSED] Composite
[10:23:02] [PASSED] SVIDEO
[10:23:02] [PASSED] LVDS
[10:23:02] [PASSED] Component
[10:23:02] [PASSED] DIN
[10:23:02] [PASSED] DP
[10:23:02] [PASSED] HDMI-A
[10:23:02] [PASSED] HDMI-B
[10:23:02] [PASSED] TV
[10:23:02] [PASSED] eDP
[10:23:02] [PASSED] Virtual
[10:23:02] [PASSED] DSI
[10:23:02] [PASSED] DPI
[10:23:02] [PASSED] Writeback
[10:23:02] [PASSED] SPI
[10:23:02] [PASSED] USB
[10:23:02] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[10:23:02] =============== [PASSED] drmm_connector_init ===============
[10:23:02] ========= drm_connector_dynamic_init (6 subtests) ==========
[10:23:02] [PASSED] drm_test_drm_connector_dynamic_init
[10:23:02] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[10:23:02] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[10:23:02] [PASSED] drm_test_drm_connector_dynamic_init_properties
[10:23:02] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[10:23:02] [PASSED] Unknown
[10:23:02] [PASSED] VGA
[10:23:02] [PASSED] DVI-I
[10:23:02] [PASSED] DVI-D
[10:23:02] [PASSED] DVI-A
[10:23:02] [PASSED] Composite
[10:23:02] [PASSED] SVIDEO
[10:23:02] [PASSED] LVDS
[10:23:02] [PASSED] Component
[10:23:02] [PASSED] DIN
[10:23:02] [PASSED] DP
[10:23:02] [PASSED] HDMI-A
[10:23:02] [PASSED] HDMI-B
[10:23:02] [PASSED] TV
[10:23:02] [PASSED] eDP
[10:23:02] [PASSED] Virtual
[10:23:02] [PASSED] DSI
[10:23:02] [PASSED] DPI
[10:23:02] [PASSED] Writeback
[10:23:02] [PASSED] SPI
[10:23:02] [PASSED] USB
[10:23:02] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[10:23:02] ======== drm_test_drm_connector_dynamic_init_name =========
[10:23:02] [PASSED] Unknown
[10:23:02] [PASSED] VGA
[10:23:02] [PASSED] DVI-I
[10:23:02] [PASSED] DVI-D
[10:23:02] [PASSED] DVI-A
[10:23:02] [PASSED] Composite
[10:23:02] [PASSED] SVIDEO
[10:23:02] [PASSED] LVDS
[10:23:02] [PASSED] Component
[10:23:02] [PASSED] DIN
[10:23:02] [PASSED] DP
[10:23:02] [PASSED] HDMI-A
[10:23:02] [PASSED] HDMI-B
[10:23:02] [PASSED] TV
[10:23:02] [PASSED] eDP
[10:23:02] [PASSED] Virtual
[10:23:02] [PASSED] DSI
[10:23:02] [PASSED] DPI
[10:23:02] [PASSED] Writeback
[10:23:02] [PASSED] SPI
[10:23:02] [PASSED] USB
[10:23:02] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[10:23:02] =========== [PASSED] drm_connector_dynamic_init ============
[10:23:02] ==== drm_connector_dynamic_register_early (4 subtests) =====
[10:23:02] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[10:23:02] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[10:23:02] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[10:23:02] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[10:23:02] ====== [PASSED] drm_connector_dynamic_register_early =======
[10:23:02] ======= drm_connector_dynamic_register (7 subtests) ========
[10:23:02] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[10:23:02] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[10:23:02] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[10:23:02] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[10:23:02] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[10:23:02] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[10:23:02] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[10:23:02] ========= [PASSED] drm_connector_dynamic_register ==========
[10:23:02] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[10:23:02] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[10:23:02] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[10:23:02] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[10:23:02] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[10:23:02] ========== drm_test_get_tv_mode_from_name_valid ===========
[10:23:02] [PASSED] NTSC
[10:23:02] [PASSED] NTSC-443
[10:23:02] [PASSED] NTSC-J
[10:23:02] [PASSED] PAL
[10:23:02] [PASSED] PAL-M
[10:23:02] [PASSED] PAL-N
[10:23:02] [PASSED] SECAM
[10:23:02] [PASSED] Mono
[10:23:02] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[10:23:02] [PASSED] drm_test_get_tv_mode_from_name_truncated
[10:23:02] ============ [PASSED] drm_get_tv_mode_from_name ============
[10:23:02] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[10:23:02] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[10:23:02] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[10:23:02] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[10:23:02] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[10:23:02] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[10:23:02] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[10:23:02] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[10:23:02] [PASSED] VIC 96
[10:23:02] [PASSED] VIC 97
[10:23:02] [PASSED] VIC 101
[10:23:02] [PASSED] VIC 102
[10:23:02] [PASSED] VIC 106
[10:23:02] [PASSED] VIC 107
[10:23:02] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[10:23:02] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[10:23:02] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[10:23:02] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[10:23:02] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[10:23:02] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[10:23:02] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[10:23:02] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[10:23:02] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[10:23:02] [PASSED] Automatic
[10:23:02] [PASSED] Full
[10:23:02] [PASSED] Limited 16:235
[10:23:02] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[10:23:02] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[10:23:02] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[10:23:02] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[10:23:02] === drm_test_drm_hdmi_connector_get_output_format_name ====
[10:23:02] [PASSED] RGB
[10:23:02] [PASSED] YUV 4:2:0
[10:23:02] [PASSED] YUV 4:2:2
[10:23:02] [PASSED] YUV 4:4:4
[10:23:02] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[10:23:02] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[10:23:02] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[10:23:02] ============= drm_damage_helper (21 subtests) ==============
[10:23:02] [PASSED] drm_test_damage_iter_no_damage
[10:23:02] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[10:23:02] [PASSED] drm_test_damage_iter_no_damage_src_moved
[10:23:02] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[10:23:02] [PASSED] drm_test_damage_iter_no_damage_not_visible
[10:23:02] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[10:23:02] [PASSED] drm_test_damage_iter_no_damage_no_fb
[10:23:02] [PASSED] drm_test_damage_iter_simple_damage
[10:23:02] [PASSED] drm_test_damage_iter_single_damage
[10:23:02] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[10:23:02] [PASSED] drm_test_damage_iter_single_damage_outside_src
[10:23:02] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[10:23:02] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[10:23:02] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[10:23:02] [PASSED] drm_test_damage_iter_single_damage_src_moved
[10:23:02] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[10:23:02] [PASSED] drm_test_damage_iter_damage
[10:23:02] [PASSED] drm_test_damage_iter_damage_one_intersect
[10:23:02] [PASSED] drm_test_damage_iter_damage_one_outside
[10:23:02] [PASSED] drm_test_damage_iter_damage_src_moved
[10:23:02] [PASSED] drm_test_damage_iter_damage_not_visible
[10:23:02] ================ [PASSED] drm_damage_helper ================
[10:23:02] ============== drm_dp_mst_helper (3 subtests) ==============
[10:23:02] ============== drm_test_dp_mst_calc_pbn_mode ==============
[10:23:02] [PASSED] Clock 154000 BPP 30 DSC disabled
[10:23:02] [PASSED] Clock 234000 BPP 30 DSC disabled
[10:23:02] [PASSED] Clock 297000 BPP 24 DSC disabled
[10:23:02] [PASSED] Clock 332880 BPP 24 DSC enabled
[10:23:02] [PASSED] Clock 324540 BPP 24 DSC enabled
[10:23:02] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[10:23:02] ============== drm_test_dp_mst_calc_pbn_div ===============
[10:23:02] [PASSED] Link rate 2000000 lane count 4
[10:23:02] [PASSED] Link rate 2000000 lane count 2
[10:23:02] [PASSED] Link rate 2000000 lane count 1
[10:23:02] [PASSED] Link rate 1350000 lane count 4
[10:23:02] [PASSED] Link rate 1350000 lane count 2
[10:23:02] [PASSED] Link rate 1350000 lane count 1
[10:23:02] [PASSED] Link rate 1000000 lane count 4
[10:23:02] [PASSED] Link rate 1000000 lane count 2
[10:23:02] [PASSED] Link rate 1000000 lane count 1
[10:23:02] [PASSED] Link rate 810000 lane count 4
[10:23:02] [PASSED] Link rate 810000 lane count 2
[10:23:02] [PASSED] Link rate 810000 lane count 1
[10:23:02] [PASSED] Link rate 540000 lane count 4
[10:23:02] [PASSED] Link rate 540000 lane count 2
[10:23:02] [PASSED] Link rate 540000 lane count 1
[10:23:02] [PASSED] Link rate 270000 lane count 4
[10:23:02] [PASSED] Link rate 270000 lane count 2
[10:23:02] [PASSED] Link rate 270000 lane count 1
[10:23:02] [PASSED] Link rate 162000 lane count 4
[10:23:02] [PASSED] Link rate 162000 lane count 2
[10:23:02] [PASSED] Link rate 162000 lane count 1
[10:23:02] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[10:23:02] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[10:23:02] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[10:23:02] [PASSED] DP_POWER_UP_PHY with port number
[10:23:02] [PASSED] DP_POWER_DOWN_PHY with port number
[10:23:02] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[10:23:02] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[10:23:02] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[10:23:02] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[10:23:02] [PASSED] DP_QUERY_PAYLOAD with port number
[10:23:02] [PASSED] DP_QUERY_PAYLOAD with VCPI
[10:23:02] [PASSED] DP_REMOTE_DPCD_READ with port number
[10:23:02] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[10:23:02] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[10:23:02] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[10:23:02] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[10:23:02] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[10:23:02] [PASSED] DP_REMOTE_I2C_READ with port number
[10:23:02] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[10:23:02] [PASSED] DP_REMOTE_I2C_READ with transactions array
[10:23:02] [PASSED] DP_REMOTE_I2C_WRITE with port number
[10:23:02] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[10:23:02] [PASSED] DP_REMOTE_I2C_WRITE with data array
[10:23:02] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[10:23:02] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[10:23:02] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[10:23:02] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[10:23:02] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[10:23:02] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[10:23:02] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[10:23:02] ================ [PASSED] drm_dp_mst_helper ================
[10:23:02] ================== drm_exec (7 subtests) ===================
[10:23:02] [PASSED] sanitycheck
[10:23:02] [PASSED] test_lock
[10:23:02] [PASSED] test_lock_unlock
[10:23:02] [PASSED] test_duplicates
[10:23:02] [PASSED] test_prepare
[10:23:02] [PASSED] test_prepare_array
[10:23:02] [PASSED] test_multiple_loops
[10:23:02] ==================== [PASSED] drm_exec =====================
[10:23:02] =========== drm_format_helper_test (17 subtests) ===========
[10:23:02] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[10:23:02] [PASSED] single_pixel_source_buffer
[10:23:02] [PASSED] single_pixel_clip_rectangle
[10:23:02] [PASSED] well_known_colors
[10:23:02] [PASSED] destination_pitch
[10:23:02] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[10:23:02] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[10:23:02] [PASSED] single_pixel_source_buffer
[10:23:02] [PASSED] single_pixel_clip_rectangle
[10:23:02] [PASSED] well_known_colors
[10:23:02] [PASSED] destination_pitch
[10:23:02] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[10:23:02] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[10:23:02] [PASSED] single_pixel_source_buffer
[10:23:02] [PASSED] single_pixel_clip_rectangle
[10:23:02] [PASSED] well_known_colors
[10:23:02] [PASSED] destination_pitch
[10:23:02] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[10:23:02] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[10:23:02] [PASSED] single_pixel_source_buffer
[10:23:02] [PASSED] single_pixel_clip_rectangle
[10:23:02] [PASSED] well_known_colors
[10:23:02] [PASSED] destination_pitch
[10:23:02] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[10:23:02] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[10:23:02] [PASSED] single_pixel_source_buffer
[10:23:02] [PASSED] single_pixel_clip_rectangle
[10:23:02] [PASSED] well_known_colors
[10:23:02] [PASSED] destination_pitch
[10:23:02] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[10:23:02] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[10:23:02] [PASSED] single_pixel_source_buffer
[10:23:02] [PASSED] single_pixel_clip_rectangle
[10:23:02] [PASSED] well_known_colors
[10:23:02] [PASSED] destination_pitch
[10:23:02] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[10:23:02] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[10:23:02] [PASSED] single_pixel_source_buffer
[10:23:02] [PASSED] single_pixel_clip_rectangle
[10:23:02] [PASSED] well_known_colors
[10:23:02] [PASSED] destination_pitch
[10:23:02] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[10:23:02] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[10:23:02] [PASSED] single_pixel_source_buffer
[10:23:02] [PASSED] single_pixel_clip_rectangle
[10:23:02] [PASSED] well_known_colors
[10:23:02] [PASSED] destination_pitch
[10:23:02] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[10:23:02] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[10:23:02] [PASSED] single_pixel_source_buffer
[10:23:02] [PASSED] single_pixel_clip_rectangle
[10:23:02] [PASSED] well_known_colors
[10:23:02] [PASSED] destination_pitch
[10:23:02] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[10:23:02] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[10:23:02] [PASSED] single_pixel_source_buffer
[10:23:02] [PASSED] single_pixel_clip_rectangle
[10:23:02] [PASSED] well_known_colors
[10:23:02] [PASSED] destination_pitch
[10:23:02] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[10:23:02] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[10:23:02] [PASSED] single_pixel_source_buffer
[10:23:02] [PASSED] single_pixel_clip_rectangle
[10:23:02] [PASSED] well_known_colors
[10:23:02] [PASSED] destination_pitch
[10:23:02] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[10:23:02] ============== drm_test_fb_xrgb8888_to_mono ===============
[10:23:02] [PASSED] single_pixel_source_buffer
[10:23:02] [PASSED] single_pixel_clip_rectangle
[10:23:02] [PASSED] well_known_colors
[10:23:02] [PASSED] destination_pitch
[10:23:02] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[10:23:02] ==================== drm_test_fb_swab =====================
[10:23:02] [PASSED] single_pixel_source_buffer
[10:23:02] [PASSED] single_pixel_clip_rectangle
[10:23:02] [PASSED] well_known_colors
[10:23:02] [PASSED] destination_pitch
[10:23:02] ================ [PASSED] drm_test_fb_swab =================
[10:23:02] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[10:23:02] [PASSED] single_pixel_source_buffer
[10:23:02] [PASSED] single_pixel_clip_rectangle
[10:23:02] [PASSED] well_known_colors
[10:23:02] [PASSED] destination_pitch
[10:23:02] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[10:23:02] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[10:23:02] [PASSED] single_pixel_source_buffer
[10:23:02] [PASSED] single_pixel_clip_rectangle
[10:23:02] [PASSED] well_known_colors
[10:23:02] [PASSED] destination_pitch
[10:23:02] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[10:23:02] ================= drm_test_fb_clip_offset =================
[10:23:02] [PASSED] pass through
[10:23:02] [PASSED] horizontal offset
[10:23:02] [PASSED] vertical offset
[10:23:02] [PASSED] horizontal and vertical offset
[10:23:02] [PASSED] horizontal offset (custom pitch)
[10:23:02] [PASSED] vertical offset (custom pitch)
[10:23:02] [PASSED] horizontal and vertical offset (custom pitch)
[10:23:02] ============= [PASSED] drm_test_fb_clip_offset =============
[10:23:02] =================== drm_test_fb_memcpy ====================
[10:23:02] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[10:23:02] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[10:23:02] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[10:23:02] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[10:23:02] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[10:23:02] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[10:23:02] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[10:23:02] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[10:23:02] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[10:23:02] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[10:23:02] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[10:23:02] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[10:23:02] =============== [PASSED] drm_test_fb_memcpy ================
[10:23:02] ============= [PASSED] drm_format_helper_test ==============
[10:23:02] ================= drm_format (18 subtests) =================
[10:23:02] [PASSED] drm_test_format_block_width_invalid
[10:23:02] [PASSED] drm_test_format_block_width_one_plane
[10:23:02] [PASSED] drm_test_format_block_width_two_plane
[10:23:02] [PASSED] drm_test_format_block_width_three_plane
[10:23:02] [PASSED] drm_test_format_block_width_tiled
[10:23:02] [PASSED] drm_test_format_block_height_invalid
[10:23:02] [PASSED] drm_test_format_block_height_one_plane
[10:23:02] [PASSED] drm_test_format_block_height_two_plane
[10:23:02] [PASSED] drm_test_format_block_height_three_plane
[10:23:02] [PASSED] drm_test_format_block_height_tiled
[10:23:02] [PASSED] drm_test_format_min_pitch_invalid
[10:23:02] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[10:23:02] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[10:23:02] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[10:23:02] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[10:23:02] [PASSED] drm_test_format_min_pitch_two_plane
[10:23:02] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[10:23:02] [PASSED] drm_test_format_min_pitch_tiled
[10:23:02] =================== [PASSED] drm_format ====================
[10:23:02] ============== drm_framebuffer (10 subtests) ===============
[10:23:02] ========== drm_test_framebuffer_check_src_coords ==========
[10:23:02] [PASSED] Success: source fits into fb
[10:23:02] [PASSED] Fail: overflowing fb with x-axis coordinate
[10:23:02] [PASSED] Fail: overflowing fb with y-axis coordinate
[10:23:02] [PASSED] Fail: overflowing fb with source width
[10:23:02] [PASSED] Fail: overflowing fb with source height
[10:23:02] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[10:23:02] [PASSED] drm_test_framebuffer_cleanup
[10:23:02] =============== drm_test_framebuffer_create ===============
[10:23:02] [PASSED] ABGR8888 normal sizes
[10:23:02] [PASSED] ABGR8888 max sizes
[10:23:02] [PASSED] ABGR8888 pitch greater than min required
[10:23:02] [PASSED] ABGR8888 pitch less than min required
[10:23:02] [PASSED] ABGR8888 Invalid width
[10:23:02] [PASSED] ABGR8888 Invalid buffer handle
[10:23:02] [PASSED] No pixel format
[10:23:02] [PASSED] ABGR8888 Width 0
[10:23:02] [PASSED] ABGR8888 Height 0
[10:23:02] [PASSED] ABGR8888 Out of bound height * pitch combination
[10:23:02] [PASSED] ABGR8888 Large buffer offset
[10:23:02] [PASSED] ABGR8888 Buffer offset for inexistent plane
[10:23:02] [PASSED] ABGR8888 Invalid flag
[10:23:02] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[10:23:02] [PASSED] ABGR8888 Valid buffer modifier
[10:23:02] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[10:23:02] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[10:23:02] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[10:23:02] [PASSED] NV12 Normal sizes
[10:23:02] [PASSED] NV12 Max sizes
[10:23:02] [PASSED] NV12 Invalid pitch
[10:23:02] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[10:23:02] [PASSED] NV12 different modifier per-plane
[10:23:02] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[10:23:02] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[10:23:02] [PASSED] NV12 Modifier for inexistent plane
[10:23:02] [PASSED] NV12 Handle for inexistent plane
[10:23:02] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[10:23:02] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[10:23:02] [PASSED] YVU420 Normal sizes
[10:23:02] [PASSED] YVU420 Max sizes
[10:23:02] [PASSED] YVU420 Invalid pitch
[10:23:02] [PASSED] YVU420 Different pitches
[10:23:02] [PASSED] YVU420 Different buffer offsets/pitches
[10:23:02] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[10:23:02] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[10:23:02] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[10:23:02] [PASSED] YVU420 Valid modifier
[10:23:02] [PASSED] YVU420 Different modifiers per plane
[10:23:02] [PASSED] YVU420 Modifier for inexistent plane
[10:23:02] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[10:23:02] [PASSED] X0L2 Normal sizes
[10:23:02] [PASSED] X0L2 Max sizes
[10:23:02] [PASSED] X0L2 Invalid pitch
[10:23:02] [PASSED] X0L2 Pitch greater than minimum required
[10:23:02] [PASSED] X0L2 Handle for inexistent plane
[10:23:02] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[10:23:02] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[10:23:02] [PASSED] X0L2 Valid modifier
[10:23:02] [PASSED] X0L2 Modifier for inexistent plane
[10:23:02] =========== [PASSED] drm_test_framebuffer_create ===========
[10:23:02] [PASSED] drm_test_framebuffer_free
[10:23:02] [PASSED] drm_test_framebuffer_init
[10:23:02] [PASSED] drm_test_framebuffer_init_bad_format
[10:23:02] [PASSED] drm_test_framebuffer_init_dev_mismatch
[10:23:02] [PASSED] drm_test_framebuffer_lookup
[10:23:02] [PASSED] drm_test_framebuffer_lookup_inexistent
[10:23:02] [PASSED] drm_test_framebuffer_modifiers_not_supported
[10:23:02] ================= [PASSED] drm_framebuffer =================
[10:23:02] ================ drm_gem_shmem (8 subtests) ================
[10:23:02] [PASSED] drm_gem_shmem_test_obj_create
[10:23:02] [PASSED] drm_gem_shmem_test_obj_create_private
[10:23:02] [PASSED] drm_gem_shmem_test_pin_pages
[10:23:02] [PASSED] drm_gem_shmem_test_vmap
[10:23:02] [PASSED] drm_gem_shmem_test_get_sg_table
[10:23:02] [PASSED] drm_gem_shmem_test_get_pages_sgt
[10:23:02] [PASSED] drm_gem_shmem_test_madvise
[10:23:02] [PASSED] drm_gem_shmem_test_purge
[10:23:02] ================== [PASSED] drm_gem_shmem ==================
[10:23:02] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[10:23:02] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[10:23:02] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[10:23:02] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[10:23:02] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[10:23:02] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[10:23:02] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[10:23:02] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[10:23:02] [PASSED] Automatic
[10:23:02] [PASSED] Full
[10:23:02] [PASSED] Limited 16:235
[10:23:02] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[10:23:02] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[10:23:02] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[10:23:02] [PASSED] drm_test_check_disable_connector
[10:23:02] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[10:23:02] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[10:23:02] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[10:23:02] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[10:23:02] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[10:23:02] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[10:23:02] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[10:23:02] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[10:23:02] [PASSED] drm_test_check_output_bpc_dvi
[10:23:02] [PASSED] drm_test_check_output_bpc_format_vic_1
[10:23:02] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[10:23:02] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[10:23:02] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[10:23:02] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[10:23:02] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[10:23:02] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[10:23:02] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[10:23:02] ============ drm_test_check_hdmi_color_format =============
[10:23:02] [PASSED] AUTO -> RGB
[10:23:02] [PASSED] YCBCR422 -> YUV422
[10:23:02] [PASSED] YCBCR420 -> YUV420
[10:23:02] [PASSED] YCBCR444 -> YUV444
[10:23:02] [PASSED] RGB -> RGB
[10:23:02] ======== [PASSED] drm_test_check_hdmi_color_format =========
[10:23:02] ======== drm_test_check_hdmi_color_format_420_only ========
[10:23:02] [PASSED] RGB should fail
[10:23:02] [PASSED] YUV444 should fail
[10:23:02] [PASSED] YUV422 should fail
[10:23:02] [PASSED] YUV420 should work
[10:23:02] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[10:23:02] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[10:23:02] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[10:23:02] [PASSED] drm_test_check_broadcast_rgb_value
[10:23:02] [PASSED] drm_test_check_bpc_8_value
[10:23:02] [PASSED] drm_test_check_bpc_10_value
[10:23:02] [PASSED] drm_test_check_bpc_12_value
[10:23:02] [PASSED] drm_test_check_format_value
[10:23:02] [PASSED] drm_test_check_tmds_char_value
[10:23:02] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[10:23:02] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[10:23:02] [PASSED] drm_test_check_mode_valid
[10:23:02] [PASSED] drm_test_check_mode_valid_reject
[10:23:02] [PASSED] drm_test_check_mode_valid_reject_rate
[10:23:02] [PASSED] drm_test_check_mode_valid_reject_max_clock
[10:23:02] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[10:23:02] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[10:23:02] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[10:23:02] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[10:23:02] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[10:23:02] [PASSED] drm_test_check_infoframes
[10:23:02] [PASSED] drm_test_check_reject_avi_infoframe
[10:23:02] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[10:23:02] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[10:23:02] [PASSED] drm_test_check_reject_audio_infoframe
[10:23:02] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[10:23:02] ================= drm_managed (2 subtests) =================
[10:23:02] [PASSED] drm_test_managed_release_action
[10:23:02] [PASSED] drm_test_managed_run_action
[10:23:02] =================== [PASSED] drm_managed ===================
[10:23:02] =================== drm_mm (6 subtests) ====================
[10:23:02] [PASSED] drm_test_mm_init
[10:23:02] [PASSED] drm_test_mm_debug
[10:23:02] [PASSED] drm_test_mm_align32
[10:23:02] [PASSED] drm_test_mm_align64
[10:23:02] [PASSED] drm_test_mm_lowest
[10:23:02] [PASSED] drm_test_mm_highest
[10:23:02] ===================== [PASSED] drm_mm ======================
[10:23:02] ============= drm_modes_analog_tv (5 subtests) =============
[10:23:02] [PASSED] drm_test_modes_analog_tv_mono_576i
[10:23:02] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[10:23:02] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[10:23:02] [PASSED] drm_test_modes_analog_tv_pal_576i
[10:23:02] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[10:23:02] =============== [PASSED] drm_modes_analog_tv ===============
[10:23:02] ============== drm_plane_helper (2 subtests) ===============
[10:23:02] =============== drm_test_check_plane_state ================
[10:23:02] [PASSED] clipping_simple
[10:23:02] [PASSED] clipping_rotate_reflect
[10:23:02] [PASSED] positioning_simple
[10:23:02] [PASSED] upscaling
[10:23:02] [PASSED] downscaling
[10:23:02] [PASSED] rounding1
[10:23:02] [PASSED] rounding2
[10:23:02] [PASSED] rounding3
[10:23:02] [PASSED] rounding4
[10:23:02] =========== [PASSED] drm_test_check_plane_state ============
[10:23:02] =========== drm_test_check_invalid_plane_state ============
[10:23:02] [PASSED] positioning_invalid
[10:23:02] [PASSED] upscaling_invalid
[10:23:02] [PASSED] downscaling_invalid
[10:23:02] ======= [PASSED] drm_test_check_invalid_plane_state ========
[10:23:02] ================ [PASSED] drm_plane_helper =================
[10:23:02] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[10:23:02] ====== drm_test_connector_helper_tv_get_modes_check =======
[10:23:02] [PASSED] None
[10:23:02] [PASSED] PAL
[10:23:02] [PASSED] NTSC
[10:23:02] [PASSED] Both, NTSC Default
[10:23:02] [PASSED] Both, PAL Default
[10:23:02] [PASSED] Both, NTSC Default, with PAL on command-line
[10:23:02] [PASSED] Both, PAL Default, with NTSC on command-line
[10:23:02] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[10:23:02] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[10:23:02] ================== drm_rect (9 subtests) ===================
[10:23:02] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[10:23:02] [PASSED] drm_test_rect_clip_scaled_not_clipped
[10:23:02] [PASSED] drm_test_rect_clip_scaled_clipped
[10:23:02] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[10:23:02] ================= drm_test_rect_intersect =================
[10:23:02] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[10:23:02] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[10:23:02] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[10:23:02] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[10:23:02] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[10:23:02] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[10:23:02] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[10:23:02] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[10:23:02] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[10:23:02] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[10:23:02] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[10:23:02] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[10:23:02] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[10:23:02] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[10:23:02] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[10:23:02] ============= [PASSED] drm_test_rect_intersect =============
[10:23:02] ================ drm_test_rect_calc_hscale ================
[10:23:02] [PASSED] normal use
[10:23:02] [PASSED] out of max range
[10:23:02] [PASSED] out of min range
[10:23:02] [PASSED] zero dst
[10:23:02] [PASSED] negative src
[10:23:02] [PASSED] negative dst
[10:23:02] ============ [PASSED] drm_test_rect_calc_hscale ============
[10:23:02] ================ drm_test_rect_calc_vscale ================
[10:23:02] [PASSED] normal use
[10:23:02] [PASSED] out of max range
[10:23:02] [PASSED] out of min range
[10:23:02] [PASSED] zero dst
[10:23:02] [PASSED] negative src
[10:23:02] [PASSED] negative dst
[10:23:02] ============ [PASSED] drm_test_rect_calc_vscale ============
[10:23:02] ================== drm_test_rect_rotate ===================
[10:23:02] [PASSED] reflect-x
[10:23:02] [PASSED] reflect-y
[10:23:02] [PASSED] rotate-0
[10:23:02] [PASSED] rotate-90
[10:23:02] [PASSED] rotate-180
[10:23:02] [PASSED] rotate-270
[10:23:02] ============== [PASSED] drm_test_rect_rotate ===============
[10:23:02] ================ drm_test_rect_rotate_inv =================
[10:23:02] [PASSED] reflect-x
[10:23:02] [PASSED] reflect-y
[10:23:02] [PASSED] rotate-0
[10:23:02] [PASSED] rotate-90
[10:23:02] [PASSED] rotate-180
[10:23:02] [PASSED] rotate-270
[10:23:02] ============ [PASSED] drm_test_rect_rotate_inv =============
[10:23:02] ==================== [PASSED] drm_rect =====================
[10:23:02] ============ drm_sysfb_modeset_test (1 subtest) ============
[10:23:02] ============ drm_test_sysfb_build_fourcc_list =============
[10:23:02] [PASSED] no native formats
[10:23:02] [PASSED] XRGB8888 as native format
[10:23:02] [PASSED] remove duplicates
[10:23:02] [PASSED] convert alpha formats
[10:23:02] [PASSED] random formats
[10:23:02] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[10:23:02] ============= [PASSED] drm_sysfb_modeset_test ==============
[10:23:02] ================== drm_fixp (2 subtests) ===================
[10:23:02] [PASSED] drm_test_int2fixp
[10:23:02] [PASSED] drm_test_sm2fixp
[10:23:02] ==================== [PASSED] drm_fixp =====================
[10:23:02] ============================================================
[10:23:02] Testing complete. Ran 637 tests: passed: 637
[10:23:02] Elapsed time: 26.800s total, 1.822s configuring, 24.814s building, 0.145s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[10:23:02] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:23:04] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:23:14] Starting KUnit Kernel (1/1)...
[10:23:14] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:23:14] ================= ttm_device (5 subtests) ==================
[10:23:14] [PASSED] ttm_device_init_basic
[10:23:14] [PASSED] ttm_device_init_multiple
[10:23:14] [PASSED] ttm_device_fini_basic
[10:23:14] [PASSED] ttm_device_init_no_vma_man
[10:23:14] ================== ttm_device_init_pools ==================
[10:23:14] [PASSED] No DMA allocations, no DMA32 required
[10:23:14] [PASSED] DMA allocations, DMA32 required
[10:23:14] [PASSED] No DMA allocations, DMA32 required
[10:23:14] [PASSED] DMA allocations, no DMA32 required
[10:23:14] ============== [PASSED] ttm_device_init_pools ==============
[10:23:14] =================== [PASSED] ttm_device ====================
[10:23:14] ================== ttm_pool (8 subtests) ===================
[10:23:14] ================== ttm_pool_alloc_basic ===================
[10:23:14] [PASSED] One page
[10:23:14] [PASSED] More than one page
[10:23:14] [PASSED] Above the allocation limit
[10:23:14] [PASSED] One page, with coherent DMA mappings enabled
[10:23:14] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:23:14] ============== [PASSED] ttm_pool_alloc_basic ===============
[10:23:14] ============== ttm_pool_alloc_basic_dma_addr ==============
[10:23:14] [PASSED] One page
[10:23:14] [PASSED] More than one page
[10:23:14] [PASSED] Above the allocation limit
[10:23:14] [PASSED] One page, with coherent DMA mappings enabled
[10:23:14] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:23:14] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[10:23:14] [PASSED] ttm_pool_alloc_order_caching_match
[10:23:14] [PASSED] ttm_pool_alloc_caching_mismatch
[10:23:14] [PASSED] ttm_pool_alloc_order_mismatch
[10:23:14] [PASSED] ttm_pool_free_dma_alloc
[10:23:14] [PASSED] ttm_pool_free_no_dma_alloc
[10:23:14] [PASSED] ttm_pool_fini_basic
[10:23:14] ==================== [PASSED] ttm_pool =====================
[10:23:14] ================ ttm_resource (8 subtests) =================
[10:23:14] ================= ttm_resource_init_basic =================
[10:23:14] [PASSED] Init resource in TTM_PL_SYSTEM
[10:23:14] [PASSED] Init resource in TTM_PL_VRAM
[10:23:14] [PASSED] Init resource in a private placement
[10:23:14] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[10:23:14] ============= [PASSED] ttm_resource_init_basic =============
[10:23:14] [PASSED] ttm_resource_init_pinned
[10:23:14] [PASSED] ttm_resource_fini_basic
[10:23:14] [PASSED] ttm_resource_manager_init_basic
[10:23:14] [PASSED] ttm_resource_manager_usage_basic
[10:23:14] [PASSED] ttm_resource_manager_set_used_basic
[10:23:14] [PASSED] ttm_sys_man_alloc_basic
[10:23:14] [PASSED] ttm_sys_man_free_basic
[10:23:14] ================== [PASSED] ttm_resource ===================
[10:23:14] =================== ttm_tt (15 subtests) ===================
[10:23:14] ==================== ttm_tt_init_basic ====================
[10:23:14] [PASSED] Page-aligned size
[10:23:14] [PASSED] Extra pages requested
[10:23:14] ================ [PASSED] ttm_tt_init_basic ================
[10:23:14] [PASSED] ttm_tt_init_misaligned
[10:23:14] [PASSED] ttm_tt_fini_basic
[10:23:14] [PASSED] ttm_tt_fini_sg
[10:23:14] [PASSED] ttm_tt_fini_shmem
[10:23:14] [PASSED] ttm_tt_create_basic
[10:23:14] [PASSED] ttm_tt_create_invalid_bo_type
[10:23:14] [PASSED] ttm_tt_create_ttm_exists
[10:23:14] [PASSED] ttm_tt_create_failed
[10:23:14] [PASSED] ttm_tt_destroy_basic
[10:23:14] [PASSED] ttm_tt_populate_null_ttm
[10:23:14] [PASSED] ttm_tt_populate_populated_ttm
[10:23:14] [PASSED] ttm_tt_unpopulate_basic
[10:23:14] [PASSED] ttm_tt_unpopulate_empty_ttm
[10:23:14] [PASSED] ttm_tt_swapin_basic
[10:23:14] ===================== [PASSED] ttm_tt ======================
[10:23:14] =================== ttm_bo (14 subtests) ===================
[10:23:14] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[10:23:14] [PASSED] Cannot be interrupted and sleeps
[10:23:14] [PASSED] Cannot be interrupted, locks straight away
[10:23:14] [PASSED] Can be interrupted, sleeps
[10:23:14] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[10:23:14] [PASSED] ttm_bo_reserve_locked_no_sleep
[10:23:14] [PASSED] ttm_bo_reserve_no_wait_ticket
[10:23:14] [PASSED] ttm_bo_reserve_double_resv
[10:23:14] [PASSED] ttm_bo_reserve_interrupted
[10:23:14] [PASSED] ttm_bo_reserve_deadlock
[10:23:14] [PASSED] ttm_bo_unreserve_basic
[10:23:14] [PASSED] ttm_bo_unreserve_pinned
[10:23:14] [PASSED] ttm_bo_unreserve_bulk
[10:23:14] [PASSED] ttm_bo_fini_basic
[10:23:14] [PASSED] ttm_bo_fini_shared_resv
[10:23:14] [PASSED] ttm_bo_pin_basic
[10:23:14] [PASSED] ttm_bo_pin_unpin_resource
[10:23:14] [PASSED] ttm_bo_multiple_pin_one_unpin
[10:23:14] ===================== [PASSED] ttm_bo ======================
[10:23:14] ============== ttm_bo_validate (22 subtests) ===============
[10:23:14] ============== ttm_bo_init_reserved_sys_man ===============
[10:23:14] [PASSED] Buffer object for userspace
[10:23:14] [PASSED] Kernel buffer object
[10:23:14] [PASSED] Shared buffer object
[10:23:14] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[10:23:14] ============== ttm_bo_init_reserved_mock_man ==============
[10:23:14] [PASSED] Buffer object for userspace
[10:23:14] [PASSED] Kernel buffer object
[10:23:14] [PASSED] Shared buffer object
[10:23:14] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[10:23:14] [PASSED] ttm_bo_init_reserved_resv
[10:23:14] ================== ttm_bo_validate_basic ==================
[10:23:14] [PASSED] Buffer object for userspace
[10:23:14] [PASSED] Kernel buffer object
[10:23:14] [PASSED] Shared buffer object
[10:23:14] ============== [PASSED] ttm_bo_validate_basic ==============
[10:23:14] [PASSED] ttm_bo_validate_invalid_placement
[10:23:14] ============= ttm_bo_validate_same_placement ==============
[10:23:14] [PASSED] System manager
[10:23:14] [PASSED] VRAM manager
[10:23:14] ========= [PASSED] ttm_bo_validate_same_placement ==========
[10:23:14] [PASSED] ttm_bo_validate_failed_alloc
[10:23:14] [PASSED] ttm_bo_validate_pinned
[10:23:14] [PASSED] ttm_bo_validate_busy_placement
[10:23:14] ================ ttm_bo_validate_multihop =================
[10:23:14] [PASSED] Buffer object for userspace
[10:23:14] [PASSED] Kernel buffer object
[10:23:14] [PASSED] Shared buffer object
[10:23:14] ============ [PASSED] ttm_bo_validate_multihop =============
[10:23:14] ========== ttm_bo_validate_no_placement_signaled ==========
[10:23:14] [PASSED] Buffer object in system domain, no page vector
[10:23:14] [PASSED] Buffer object in system domain with an existing page vector
[10:23:14] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[10:23:14] ======== ttm_bo_validate_no_placement_not_signaled ========
[10:23:14] [PASSED] Buffer object for userspace
[10:23:14] [PASSED] Kernel buffer object
[10:23:14] [PASSED] Shared buffer object
[10:23:14] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[10:23:14] [PASSED] ttm_bo_validate_move_fence_signaled
[10:23:14] ========= ttm_bo_validate_move_fence_not_signaled =========
[10:23:14] [PASSED] Waits for GPU
[10:23:14] [PASSED] Tries to lock straight away
[10:23:14] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[10:23:14] [PASSED] ttm_bo_validate_swapout
[10:23:14] [PASSED] ttm_bo_validate_happy_evict
[10:23:14] [PASSED] ttm_bo_validate_all_pinned_evict
[10:23:14] [PASSED] ttm_bo_validate_allowed_only_evict
[10:23:14] [PASSED] ttm_bo_validate_deleted_evict
[10:23:14] [PASSED] ttm_bo_validate_busy_domain_evict
[10:23:14] [PASSED] ttm_bo_validate_evict_gutting
[10:23:14] [PASSED] ttm_bo_validate_recrusive_evict
[10:23:14] ================= [PASSED] ttm_bo_validate =================
[10:23:14] ============================================================
[10:23:14] Testing complete. Ran 102 tests: passed: 102
[10:23:14] Elapsed time: 11.977s total, 1.814s configuring, 9.949s building, 0.181s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✓ Xe.CI.BAT: success for drm/i915/display: Enable AS SDP Skip Frames (rev3)
2026-08-03 18:53 [PATCH 0/2] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
` (9 preceding siblings ...)
2026-08-05 10:23 ` ✓ CI.KUnit: success " Patchwork
@ 2026-08-05 11:05 ` Patchwork
2026-08-05 20:52 ` ✗ Xe.CI.FULL: failure " Patchwork
11 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2026-08-05 11:05 UTC (permalink / raw)
To: Shankar, Uma; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 873 bytes --]
== Series Details ==
Series: drm/i915/display: Enable AS SDP Skip Frames (rev3)
URL : https://patchwork.freedesktop.org/series/162015/
State : success
== Summary ==
CI Bug Log - changes from xe-5545-4c13a67db118ee0019231dbc1362bcb8115ac660_BAT -> xe-pw-162015v3_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (14 -> 14)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-5545-4c13a67db118ee0019231dbc1362bcb8115ac660 -> xe-pw-162015v3
IGT_9038: 9038
xe-5545-4c13a67db118ee0019231dbc1362bcb8115ac660: 4c13a67db118ee0019231dbc1362bcb8115ac660
xe-pw-162015v3: 162015v3
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v3/index.html
[-- Attachment #2: Type: text/html, Size: 1421 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✗ Xe.CI.FULL: failure for drm/i915/display: Enable AS SDP Skip Frames (rev3)
2026-08-03 18:53 [PATCH 0/2] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
` (10 preceding siblings ...)
2026-08-05 11:05 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-08-05 20:52 ` Patchwork
11 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2026-08-05 20:52 UTC (permalink / raw)
To: Shankar, Uma; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 381 bytes --]
== Series Details ==
Series: drm/i915/display: Enable AS SDP Skip Frames (rev3)
URL : https://patchwork.freedesktop.org/series/162015/
State : failure
== Summary ==
ERROR: The runconfig 'xe-5545-4c13a67db118ee0019231dbc1362bcb8115ac660_FULL' does not exist in the database
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v3/index.html
[-- Attachment #2: Type: text/html, Size: 946 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2026-08-05 20:52 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-08-03 18:53 [PATCH 0/2] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
2026-08-03 18:39 ` ✗ CI.checkpatch: warning for drm/i915/display: Enable AS SDP Skip Frames (rev2) Patchwork
2026-08-03 18:40 ` ✓ CI.KUnit: success " Patchwork
2026-08-03 18:53 ` [PATCH 1/2] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
2026-08-04 16:15 ` Dibin Moolakadan Subrahmanian
2026-08-03 18:53 ` [PATCH 2/2] drm/i915/display: Keep AS SDP flowing when skip frames is enabled Uma Shankar
2026-08-04 7:21 ` Dibin Moolakadan Subrahmanian
2026-08-04 7:50 ` Shankar, Uma
2026-08-03 21:25 ` ✓ Xe.CI.FULL: success for drm/i915/display: Enable AS SDP Skip Frames (rev2) Patchwork
2026-08-04 12:03 ` ✗ CI.checkpatch: warning " Patchwork
2026-08-04 12:05 ` ✓ CI.KUnit: success " Patchwork
2026-08-05 6:03 ` ✗ Xe.CI.BAT: failure " Patchwork
2026-08-05 10:21 ` ✗ CI.checkpatch: warning for drm/i915/display: Enable AS SDP Skip Frames (rev3) Patchwork
2026-08-05 10:23 ` ✓ CI.KUnit: success " Patchwork
2026-08-05 11:05 ` ✓ Xe.CI.BAT: " Patchwork
2026-08-05 20:52 ` ✗ Xe.CI.FULL: failure " Patchwork
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