[PATCH 0/5] VF: Setup VRAM based on received config data

[PATCH 0/5] VF: Setup VRAM based on received config data

[Michal Wajdeczko]

VF drivers will obtain VRAM configuration from the GuC as part of
the VF self config. Use that configuration instead of trying to
read inaccessible registers.

But before doing that, do some cleanup of the VRAM probe code.

Michal Wajdeczko (5):
  drm/xe: Move XEHP_MTCFG_ADDR register definition to xe_regs.h
  drm/xe: Move BAR definitions to dedicated file
  drm/xe: Promote VRAM initialization function to own file
  drm/xe: Rename internal vram helper function
  drm/xe/vf: Setup VRAM based on received config data

 drivers/gpu/drm/xe/Makefile            |   1 +
 drivers/gpu/drm/xe/regs/xe_bars.h      |  11 +
 drivers/gpu/drm/xe/regs/xe_regs.h      |   3 +
 drivers/gpu/drm/xe/xe_device.c         |   3 +-
 drivers/gpu/drm/xe/xe_gt_sriov_vf.c    |  17 ++
 drivers/gpu/drm/xe/xe_gt_sriov_vf.h    |   1 +
 drivers/gpu/drm/xe/xe_mmio.c           | 339 +----------------------
 drivers/gpu/drm/xe/xe_mmio.h           |   2 -
 drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c |   1 +
 drivers/gpu/drm/xe/xe_vram.c           | 368 +++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_vram.h           |  13 +
 11 files changed, 421 insertions(+), 338 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/regs/xe_bars.h
 create mode 100644 drivers/gpu/drm/xe/xe_vram.c
 create mode 100644 drivers/gpu/drm/xe/xe_vram.h

-- 
2.43.0

[PATCH 1/5] drm/xe: Move XEHP_MTCFG_ADDR register definition to xe_regs.h

[Michal Wajdeczko]

We should not define registers directly in the code while we have
dedicated files for all register definitions. Move XEHP_MTCFG_ADDR
to regs/xe_regs.h

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_regs.h | 3 +++
 drivers/gpu/drm/xe/xe_mmio.c      | 3 ---
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
index 722fb6dbb72e..23e33ec84902 100644
--- a/drivers/gpu/drm/xe/regs/xe_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
@@ -30,6 +30,9 @@
 #define XEHP_CLOCK_GATE_DIS			XE_REG(0x101014)
 #define   SGSI_SIDECLK_DIS			REG_BIT(17)
 
+#define XEHP_MTCFG_ADDR				XE_REG(0x101800)
+#define   TILE_COUNT				REG_GENMASK(15, 8)
+
 #define GGC					XE_REG(0x108040)
 #define   GMS_MASK				REG_GENMASK(15, 8)
 #define   GGMS_MASK				REG_GENMASK(7, 6)
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 248e93ec6df7..44bff104c011 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -28,9 +28,6 @@
 #include "xe_sriov.h"
 #include "xe_tile.h"
 
-#define XEHP_MTCFG_ADDR		XE_REG(0x101800)
-#define TILE_COUNT		REG_GENMASK(15, 8)
-
 #define BAR_SIZE_SHIFT 20
 
 static void
-- 
2.43.0

[PATCH 2/5] drm/xe: Move BAR definitions to dedicated file

[Michal Wajdeczko]

We should keep all hardware definitions separated from the driver
code. Move LMEM_BAR definition to new regs/xe_bars.h file and also
add there GTTMMADR_BAR definition to avoid using magic 0 resource.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_bars.h      | 11 +++++++++++
 drivers/gpu/drm/xe/xe_mmio.c           |  3 ++-
 drivers/gpu/drm/xe/xe_mmio.h           |  2 --
 drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c |  1 +
 4 files changed, 14 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/regs/xe_bars.h

diff --git a/drivers/gpu/drm/xe/regs/xe_bars.h b/drivers/gpu/drm/xe/regs/xe_bars.h
new file mode 100644
index 000000000000..ce05b6ae832f
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_bars.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+#ifndef _XE_BARS_H_
+#define _XE_BARS_H_
+
+#define GTTMMADR_BAR			0 /* MMIO + GTT */
+#define LMEM_BAR			2 /* VRAM */
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 44bff104c011..1272246dd8a3 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -12,6 +12,7 @@
 #include <drm/drm_managed.h>
 #include <drm/xe_drm.h>
 
+#include "regs/xe_bars.h"
 #include "regs/xe_engine_regs.h"
 #include "regs/xe_gt_regs.h"
 #include "regs/xe_regs.h"
@@ -435,7 +436,7 @@ int xe_mmio_init(struct xe_device *xe)
 	 * registers (0-4MB), reserved space (4MB-8MB) and GGTT (8MB-16MB).
 	 */
 	xe->mmio.size = pci_resource_len(pdev, mmio_bar);
-	xe->mmio.regs = pci_iomap(pdev, mmio_bar, 0);
+	xe->mmio.regs = pci_iomap(pdev, mmio_bar, GTTMMADR_BAR);
 	if (xe->mmio.regs == NULL) {
 		drm_err(&xe->drm, "failed to map registers\n");
 		return -EIO;
diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
index 1d578fd6ffc2..6ae0cc32c651 100644
--- a/drivers/gpu/drm/xe/xe_mmio.h
+++ b/drivers/gpu/drm/xe/xe_mmio.h
@@ -11,8 +11,6 @@
 struct xe_device;
 struct xe_reg;
 
-#define LMEM_BAR		2
-
 int xe_mmio_init(struct xe_device *xe);
 int xe_mmio_probe_tiles(struct xe_device *xe);
 
diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
index 64592a8e527b..f46fd2df84de 100644
--- a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
+++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
@@ -13,6 +13,7 @@
 
 #include <generated/xe_wa_oob.h>
 
+#include "regs/xe_bars.h"
 #include "regs/xe_gt_regs.h"
 #include "regs/xe_regs.h"
 #include "xe_bo.h"
-- 
2.43.0

[PATCH 3/5] drm/xe: Promote VRAM initialization function to own file

[Michal Wajdeczko]

There is no point in mixing MMIO and VRAM code in the same file.
Move and rename the VRAM probe function to a new file (there are
no other changes other then simple kernel-doc).

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/Makefile    |   1 +
 drivers/gpu/drm/xe/xe_device.c |   3 +-
 drivers/gpu/drm/xe/xe_mmio.c   | 333 +------------------------------
 drivers/gpu/drm/xe/xe_vram.c   | 350 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_vram.h   |  13 ++
 5 files changed, 368 insertions(+), 332 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/xe_vram.c
 create mode 100644 drivers/gpu/drm/xe/xe_vram.h

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index d5b137e762ed..74bd64d9e8ab 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -143,6 +143,7 @@ xe-y += xe_bb.o \
 	xe_uc_debugfs.o \
 	xe_uc_fw.o \
 	xe_vm.o \
+	xe_vram.o \
 	xe_vram_freq.o \
 	xe_wait_user_fence.o \
 	xe_wa.o \
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index f04b11e45c2d..61ec15f2034b 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -51,6 +51,7 @@
 #include "xe_ttm_stolen_mgr.h"
 #include "xe_ttm_sys_mgr.h"
 #include "xe_vm.h"
+#include "xe_vram.h"
 #include "xe_wait_user_fence.h"
 
 static int xe_file_open(struct drm_device *dev, struct drm_file *file)
@@ -615,7 +616,7 @@ int xe_device_probe(struct xe_device *xe)
 	if (err)
 		goto err_irq_shutdown;
 
-	err = xe_mmio_probe_vram(xe);
+	err = xe_vram_probe(xe);
 	if (err)
 		goto err_irq_shutdown;
 
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 1272246dd8a3..7962eeb9adb7 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -8,348 +8,19 @@
 #include <linux/delay.h>
 #include <linux/io-64-nonatomic-lo-hi.h>
 #include <linux/minmax.h>
+#include <linux/pci.h>
 
 #include <drm/drm_managed.h>
-#include <drm/xe_drm.h>
+#include <drm/drm_print.h>
 
 #include "regs/xe_bars.h"
-#include "regs/xe_engine_regs.h"
-#include "regs/xe_gt_regs.h"
 #include "regs/xe_regs.h"
-#include "xe_bo.h"
 #include "xe_device.h"
-#include "xe_force_wake.h"
-#include "xe_ggtt.h"
 #include "xe_gt.h"
-#include "xe_gt_mcr.h"
 #include "xe_gt_printk.h"
 #include "xe_gt_sriov_vf.h"
 #include "xe_macros.h"
-#include "xe_module.h"
 #include "xe_sriov.h"
-#include "xe_tile.h"
-
-#define BAR_SIZE_SHIFT 20
-
-static void
-_resize_bar(struct xe_device *xe, int resno, resource_size_t size)
-{
-	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
-	int bar_size = pci_rebar_bytes_to_size(size);
-	int ret;
-
-	if (pci_resource_len(pdev, resno))
-		pci_release_resource(pdev, resno);
-
-	ret = pci_resize_resource(pdev, resno, bar_size);
-	if (ret) {
-		drm_info(&xe->drm, "Failed to resize BAR%d to %dM (%pe). Consider enabling 'Resizable BAR' support in your BIOS\n",
-			 resno, 1 << bar_size, ERR_PTR(ret));
-		return;
-	}
-
-	drm_info(&xe->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
-}
-
-/*
- * if force_vram_bar_size is set, attempt to set to the requested size
- * else set to maximum possible size
- */
-static void xe_resize_vram_bar(struct xe_device *xe)
-{
-	u64 force_vram_bar_size = xe_modparam.force_vram_bar_size;
-	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
-	struct pci_bus *root = pdev->bus;
-	resource_size_t current_size;
-	resource_size_t rebar_size;
-	struct resource *root_res;
-	u32 bar_size_mask;
-	u32 pci_cmd;
-	int i;
-
-	/* gather some relevant info */
-	current_size = pci_resource_len(pdev, LMEM_BAR);
-	bar_size_mask = pci_rebar_get_possible_sizes(pdev, LMEM_BAR);
-
-	if (!bar_size_mask)
-		return;
-
-	/* set to a specific size? */
-	if (force_vram_bar_size) {
-		u32 bar_size_bit;
-
-		rebar_size = force_vram_bar_size * (resource_size_t)SZ_1M;
-
-		bar_size_bit = bar_size_mask & BIT(pci_rebar_bytes_to_size(rebar_size));
-
-		if (!bar_size_bit) {
-			drm_info(&xe->drm,
-				 "Requested size: %lluMiB is not supported by rebar sizes: 0x%x. Leaving default: %lluMiB\n",
-				 (u64)rebar_size >> 20, bar_size_mask, (u64)current_size >> 20);
-			return;
-		}
-
-		rebar_size = 1ULL << (__fls(bar_size_bit) + BAR_SIZE_SHIFT);
-
-		if (rebar_size == current_size)
-			return;
-	} else {
-		rebar_size = 1ULL << (__fls(bar_size_mask) + BAR_SIZE_SHIFT);
-
-		/* only resize if larger than current */
-		if (rebar_size <= current_size)
-			return;
-	}
-
-	drm_info(&xe->drm, "Attempting to resize bar from %lluMiB -> %lluMiB\n",
-		 (u64)current_size >> 20, (u64)rebar_size >> 20);
-
-	while (root->parent)
-		root = root->parent;
-
-	pci_bus_for_each_resource(root, root_res, i) {
-		if (root_res && root_res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
-		    (u64)root_res->start > 0x100000000ul)
-			break;
-	}
-
-	if (!root_res) {
-		drm_info(&xe->drm, "Can't resize VRAM BAR - platform support is missing. Consider enabling 'Resizable BAR' support in your BIOS\n");
-		return;
-	}
-
-	pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
-	pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd & ~PCI_COMMAND_MEMORY);
-
-	_resize_bar(xe, LMEM_BAR, rebar_size);
-
-	pci_assign_unassigned_bus_resources(pdev->bus);
-	pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
-}
-
-static bool xe_pci_resource_valid(struct pci_dev *pdev, int bar)
-{
-	if (!pci_resource_flags(pdev, bar))
-		return false;
-
-	if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET)
-		return false;
-
-	if (!pci_resource_len(pdev, bar))
-		return false;
-
-	return true;
-}
-
-static int xe_determine_lmem_bar_size(struct xe_device *xe)
-{
-	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
-
-	if (!xe_pci_resource_valid(pdev, LMEM_BAR)) {
-		drm_err(&xe->drm, "pci resource is not valid\n");
-		return -ENXIO;
-	}
-
-	xe_resize_vram_bar(xe);
-
-	xe->mem.vram.io_start = pci_resource_start(pdev, LMEM_BAR);
-	xe->mem.vram.io_size = pci_resource_len(pdev, LMEM_BAR);
-	if (!xe->mem.vram.io_size)
-		return -EIO;
-
-	/* XXX: Need to change when xe link code is ready */
-	xe->mem.vram.dpa_base = 0;
-
-	/* set up a map to the total memory area. */
-	xe->mem.vram.mapping = ioremap_wc(xe->mem.vram.io_start, xe->mem.vram.io_size);
-
-	return 0;
-}
-
-static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
-{
-	struct xe_device *xe = gt_to_xe(gt);
-	u64 offset;
-	u32 reg;
-
-	if (GRAPHICS_VER(xe) >= 20) {
-		u64 ccs_size = tile_size / 512;
-		u64 offset_hi, offset_lo;
-		u32 nodes, num_enabled;
-
-		reg = xe_mmio_read32(gt, MIRROR_FUSE3);
-		nodes = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, reg);
-		num_enabled = hweight32(nodes); /* Number of enabled l3 nodes */
-
-		reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_LOWER);
-		offset_lo = REG_FIELD_GET(XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK, reg);
-
-		reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_UPPER);
-		offset_hi = REG_FIELD_GET(XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK, reg);
-
-		offset = offset_hi << 32; /* HW view bits 39:32 */
-		offset |= offset_lo << 6; /* HW view bits 31:6 */
-		offset *= num_enabled; /* convert to SW view */
-
-		/* We don't expect any holes */
-		xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(gt, GSMBASE) - ccs_size),
-			      "Hole between CCS and GSM.\n");
-	} else {
-		reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
-		offset = (u64)REG_FIELD_GET(XEHP_FLAT_CCS_PTR, reg) * SZ_64K;
-	}
-
-	return offset;
-}
-
-/**
- * xe_mmio_tile_vram_size() - Collect vram size and offset information
- * @tile: tile to get info for
- * @vram_size: available vram (size - device reserved portions)
- * @tile_size: actual vram size
- * @tile_offset: physical start point in the vram address space
- *
- * There are 4 places for size information:
- * - io size (from pci_resource_len of LMEM bar) (only used for small bar and DG1)
- * - TILEx size (actual vram size)
- * - GSMBASE offset (TILEx - "stolen")
- * - CSSBASE offset (TILEx - CSS space necessary)
- *
- * CSSBASE is always a lower/smaller offset then GSMBASE.
- *
- * The actual available size of memory is to the CCS or GSM base.
- * NOTE: multi-tile bases will include the tile offset.
- *
- */
-static int xe_mmio_tile_vram_size(struct xe_tile *tile, u64 *vram_size,
-				  u64 *tile_size, u64 *tile_offset)
-{
-	struct xe_device *xe = tile_to_xe(tile);
-	struct xe_gt *gt = tile->primary_gt;
-	u64 offset;
-	int err;
-	u32 reg;
-
-	err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
-	if (err)
-		return err;
-
-	/* actual size */
-	if (unlikely(xe->info.platform == XE_DG1)) {
-		*tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), LMEM_BAR);
-		*tile_offset = 0;
-	} else {
-		reg = xe_gt_mcr_unicast_read_any(gt, XEHP_TILE_ADDR_RANGE(gt->info.id));
-		*tile_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G;
-		*tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G;
-	}
-
-	/* minus device usage */
-	if (xe->info.has_flat_ccs) {
-		offset = get_flat_ccs_offset(gt, *tile_size);
-	} else {
-		offset = xe_mmio_read64_2x32(gt, GSMBASE);
-	}
-
-	/* remove the tile offset so we have just the available size */
-	*vram_size = offset - *tile_offset;
-
-	return xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
-}
-
-static void vram_fini(void *arg)
-{
-	struct xe_device *xe = arg;
-	struct xe_tile *tile;
-	int id;
-
-	if (xe->mem.vram.mapping)
-		iounmap(xe->mem.vram.mapping);
-
-	xe->mem.vram.mapping = NULL;
-
-	for_each_tile(tile, xe, id)
-		tile->mem.vram.mapping = NULL;
-}
-
-int xe_mmio_probe_vram(struct xe_device *xe)
-{
-	struct xe_tile *tile;
-	resource_size_t io_size;
-	u64 available_size = 0;
-	u64 total_size = 0;
-	u64 tile_offset;
-	u64 tile_size;
-	u64 vram_size;
-	int err;
-	u8 id;
-
-	if (!IS_DGFX(xe))
-		return 0;
-
-	/* Get the size of the root tile's vram for later accessibility comparison */
-	tile = xe_device_get_root_tile(xe);
-	err = xe_mmio_tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
-	if (err)
-		return err;
-
-	err = xe_determine_lmem_bar_size(xe);
-	if (err)
-		return err;
-
-	drm_info(&xe->drm, "VISIBLE VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
-		 &xe->mem.vram.io_size);
-
-	io_size = xe->mem.vram.io_size;
-
-	/* tile specific ranges */
-	for_each_tile(tile, xe, id) {
-		err = xe_mmio_tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
-		if (err)
-			return err;
-
-		tile->mem.vram.actual_physical_size = tile_size;
-		tile->mem.vram.io_start = xe->mem.vram.io_start + tile_offset;
-		tile->mem.vram.io_size = min_t(u64, vram_size, io_size);
-
-		if (!tile->mem.vram.io_size) {
-			drm_err(&xe->drm, "Tile without any CPU visible VRAM. Aborting.\n");
-			return -ENODEV;
-		}
-
-		tile->mem.vram.dpa_base = xe->mem.vram.dpa_base + tile_offset;
-		tile->mem.vram.usable_size = vram_size;
-		tile->mem.vram.mapping = xe->mem.vram.mapping + tile_offset;
-
-		if (tile->mem.vram.io_size < tile->mem.vram.usable_size)
-			drm_info(&xe->drm, "Small BAR device\n");
-		drm_info(&xe->drm, "VRAM[%u, %u]: Actual physical size %pa, usable size exclude stolen %pa, CPU accessible size %pa\n", id,
-			 tile->id, &tile->mem.vram.actual_physical_size, &tile->mem.vram.usable_size, &tile->mem.vram.io_size);
-		drm_info(&xe->drm, "VRAM[%u, %u]: DPA range: [%pa-%llx], io range: [%pa-%llx]\n", id, tile->id,
-			 &tile->mem.vram.dpa_base, tile->mem.vram.dpa_base + (u64)tile->mem.vram.actual_physical_size,
-			 &tile->mem.vram.io_start, tile->mem.vram.io_start + (u64)tile->mem.vram.io_size);
-
-		/* calculate total size using tile size to get the correct HW sizing */
-		total_size += tile_size;
-		available_size += vram_size;
-
-		if (total_size > xe->mem.vram.io_size) {
-			drm_info(&xe->drm, "VRAM: %pa is larger than resource %pa\n",
-				 &total_size, &xe->mem.vram.io_size);
-		}
-
-		io_size -= min_t(u64, tile_size, io_size);
-	}
-
-	xe->mem.vram.actual_physical_size = total_size;
-
-	drm_info(&xe->drm, "Total VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
-		 &xe->mem.vram.actual_physical_size);
-	drm_info(&xe->drm, "Available VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
-		 &available_size);
-
-	return devm_add_action_or_reset(xe->drm.dev, vram_fini, xe);
-}
 
 static void tiles_fini(void *arg)
 {
diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
new file mode 100644
index 000000000000..d8b81e4e050c
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_vram.c
@@ -0,0 +1,350 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021-2024 Intel Corporation
+ */
+
+#include <linux/pci.h>
+
+#include <drm/drm_managed.h>
+#include <drm/drm_print.h>
+
+#include "regs/xe_bars.h"
+#include "regs/xe_gt_regs.h"
+#include "regs/xe_regs.h"
+#include "xe_assert.h"
+#include "xe_device.h"
+#include "xe_force_wake.h"
+#include "xe_gt_mcr.h"
+#include "xe_mmio.h"
+#include "xe_module.h"
+#include "xe_vram.h"
+
+#define BAR_SIZE_SHIFT 20
+
+static void
+_resize_bar(struct xe_device *xe, int resno, resource_size_t size)
+{
+	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+	int bar_size = pci_rebar_bytes_to_size(size);
+	int ret;
+
+	if (pci_resource_len(pdev, resno))
+		pci_release_resource(pdev, resno);
+
+	ret = pci_resize_resource(pdev, resno, bar_size);
+	if (ret) {
+		drm_info(&xe->drm, "Failed to resize BAR%d to %dM (%pe). Consider enabling 'Resizable BAR' support in your BIOS\n",
+			 resno, 1 << bar_size, ERR_PTR(ret));
+		return;
+	}
+
+	drm_info(&xe->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
+}
+
+/*
+ * if force_vram_bar_size is set, attempt to set to the requested size
+ * else set to maximum possible size
+ */
+static void xe_resize_vram_bar(struct xe_device *xe)
+{
+	u64 force_vram_bar_size = xe_modparam.force_vram_bar_size;
+	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+	struct pci_bus *root = pdev->bus;
+	resource_size_t current_size;
+	resource_size_t rebar_size;
+	struct resource *root_res;
+	u32 bar_size_mask;
+	u32 pci_cmd;
+	int i;
+
+	/* gather some relevant info */
+	current_size = pci_resource_len(pdev, LMEM_BAR);
+	bar_size_mask = pci_rebar_get_possible_sizes(pdev, LMEM_BAR);
+
+	if (!bar_size_mask)
+		return;
+
+	/* set to a specific size? */
+	if (force_vram_bar_size) {
+		u32 bar_size_bit;
+
+		rebar_size = force_vram_bar_size * (resource_size_t)SZ_1M;
+
+		bar_size_bit = bar_size_mask & BIT(pci_rebar_bytes_to_size(rebar_size));
+
+		if (!bar_size_bit) {
+			drm_info(&xe->drm,
+				 "Requested size: %lluMiB is not supported by rebar sizes: 0x%x. Leaving default: %lluMiB\n",
+				 (u64)rebar_size >> 20, bar_size_mask, (u64)current_size >> 20);
+			return;
+		}
+
+		rebar_size = 1ULL << (__fls(bar_size_bit) + BAR_SIZE_SHIFT);
+
+		if (rebar_size == current_size)
+			return;
+	} else {
+		rebar_size = 1ULL << (__fls(bar_size_mask) + BAR_SIZE_SHIFT);
+
+		/* only resize if larger than current */
+		if (rebar_size <= current_size)
+			return;
+	}
+
+	drm_info(&xe->drm, "Attempting to resize bar from %lluMiB -> %lluMiB\n",
+		 (u64)current_size >> 20, (u64)rebar_size >> 20);
+
+	while (root->parent)
+		root = root->parent;
+
+	pci_bus_for_each_resource(root, root_res, i) {
+		if (root_res && root_res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
+		    (u64)root_res->start > 0x100000000ul)
+			break;
+	}
+
+	if (!root_res) {
+		drm_info(&xe->drm, "Can't resize VRAM BAR - platform support is missing. Consider enabling 'Resizable BAR' support in your BIOS\n");
+		return;
+	}
+
+	pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
+	pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd & ~PCI_COMMAND_MEMORY);
+
+	_resize_bar(xe, LMEM_BAR, rebar_size);
+
+	pci_assign_unassigned_bus_resources(pdev->bus);
+	pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
+}
+
+static bool xe_pci_resource_valid(struct pci_dev *pdev, int bar)
+{
+	if (!pci_resource_flags(pdev, bar))
+		return false;
+
+	if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET)
+		return false;
+
+	if (!pci_resource_len(pdev, bar))
+		return false;
+
+	return true;
+}
+
+static int xe_determine_lmem_bar_size(struct xe_device *xe)
+{
+	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+
+	if (!xe_pci_resource_valid(pdev, LMEM_BAR)) {
+		drm_err(&xe->drm, "pci resource is not valid\n");
+		return -ENXIO;
+	}
+
+	xe_resize_vram_bar(xe);
+
+	xe->mem.vram.io_start = pci_resource_start(pdev, LMEM_BAR);
+	xe->mem.vram.io_size = pci_resource_len(pdev, LMEM_BAR);
+	if (!xe->mem.vram.io_size)
+		return -EIO;
+
+	/* XXX: Need to change when xe link code is ready */
+	xe->mem.vram.dpa_base = 0;
+
+	/* set up a map to the total memory area. */
+	xe->mem.vram.mapping = ioremap_wc(xe->mem.vram.io_start, xe->mem.vram.io_size);
+
+	return 0;
+}
+
+static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
+{
+	struct xe_device *xe = gt_to_xe(gt);
+	u64 offset;
+	u32 reg;
+
+	if (GRAPHICS_VER(xe) >= 20) {
+		u64 ccs_size = tile_size / 512;
+		u64 offset_hi, offset_lo;
+		u32 nodes, num_enabled;
+
+		reg = xe_mmio_read32(gt, MIRROR_FUSE3);
+		nodes = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, reg);
+		num_enabled = hweight32(nodes); /* Number of enabled l3 nodes */
+
+		reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_LOWER);
+		offset_lo = REG_FIELD_GET(XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK, reg);
+
+		reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_UPPER);
+		offset_hi = REG_FIELD_GET(XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK, reg);
+
+		offset = offset_hi << 32; /* HW view bits 39:32 */
+		offset |= offset_lo << 6; /* HW view bits 31:6 */
+		offset *= num_enabled; /* convert to SW view */
+
+		/* We don't expect any holes */
+		xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(gt, GSMBASE) - ccs_size),
+			      "Hole between CCS and GSM.\n");
+	} else {
+		reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
+		offset = (u64)REG_FIELD_GET(XEHP_FLAT_CCS_PTR, reg) * SZ_64K;
+	}
+
+	return offset;
+}
+
+/**
+ * xe_mmio_tile_vram_size() - Collect vram size and offset information
+ * @tile: tile to get info for
+ * @vram_size: available vram (size - device reserved portions)
+ * @tile_size: actual vram size
+ * @tile_offset: physical start point in the vram address space
+ *
+ * There are 4 places for size information:
+ * - io size (from pci_resource_len of LMEM bar) (only used for small bar and DG1)
+ * - TILEx size (actual vram size)
+ * - GSMBASE offset (TILEx - "stolen")
+ * - CSSBASE offset (TILEx - CSS space necessary)
+ *
+ * CSSBASE is always a lower/smaller offset then GSMBASE.
+ *
+ * The actual available size of memory is to the CCS or GSM base.
+ * NOTE: multi-tile bases will include the tile offset.
+ *
+ */
+static int xe_mmio_tile_vram_size(struct xe_tile *tile, u64 *vram_size,
+				  u64 *tile_size, u64 *tile_offset)
+{
+	struct xe_device *xe = tile_to_xe(tile);
+	struct xe_gt *gt = tile->primary_gt;
+	u64 offset;
+	int err;
+	u32 reg;
+
+	err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
+	if (err)
+		return err;
+
+	/* actual size */
+	if (unlikely(xe->info.platform == XE_DG1)) {
+		*tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), LMEM_BAR);
+		*tile_offset = 0;
+	} else {
+		reg = xe_gt_mcr_unicast_read_any(gt, XEHP_TILE_ADDR_RANGE(gt->info.id));
+		*tile_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G;
+		*tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G;
+	}
+
+	/* minus device usage */
+	if (xe->info.has_flat_ccs) {
+		offset = get_flat_ccs_offset(gt, *tile_size);
+	} else {
+		offset = xe_mmio_read64_2x32(gt, GSMBASE);
+	}
+
+	/* remove the tile offset so we have just the available size */
+	*vram_size = offset - *tile_offset;
+
+	return xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
+}
+
+static void vram_fini(void *arg)
+{
+	struct xe_device *xe = arg;
+	struct xe_tile *tile;
+	int id;
+
+	if (xe->mem.vram.mapping)
+		iounmap(xe->mem.vram.mapping);
+
+	xe->mem.vram.mapping = NULL;
+
+	for_each_tile(tile, xe, id)
+		tile->mem.vram.mapping = NULL;
+}
+
+/**
+ * xe_vram_probe() - Probe VRAM configuration
+ * @xe: the &xe_device
+ *
+ * Collect VRAM size and offset information for all tiles.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int xe_vram_probe(struct xe_device *xe)
+{
+	struct xe_tile *tile;
+	resource_size_t io_size;
+	u64 available_size = 0;
+	u64 total_size = 0;
+	u64 tile_offset;
+	u64 tile_size;
+	u64 vram_size;
+	int err;
+	u8 id;
+
+	if (!IS_DGFX(xe))
+		return 0;
+
+	/* Get the size of the root tile's vram for later accessibility comparison */
+	tile = xe_device_get_root_tile(xe);
+	err = xe_mmio_tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
+	if (err)
+		return err;
+
+	err = xe_determine_lmem_bar_size(xe);
+	if (err)
+		return err;
+
+	drm_info(&xe->drm, "VISIBLE VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
+		 &xe->mem.vram.io_size);
+
+	io_size = xe->mem.vram.io_size;
+
+	/* tile specific ranges */
+	for_each_tile(tile, xe, id) {
+		err = xe_mmio_tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
+		if (err)
+			return err;
+
+		tile->mem.vram.actual_physical_size = tile_size;
+		tile->mem.vram.io_start = xe->mem.vram.io_start + tile_offset;
+		tile->mem.vram.io_size = min_t(u64, vram_size, io_size);
+
+		if (!tile->mem.vram.io_size) {
+			drm_err(&xe->drm, "Tile without any CPU visible VRAM. Aborting.\n");
+			return -ENODEV;
+		}
+
+		tile->mem.vram.dpa_base = xe->mem.vram.dpa_base + tile_offset;
+		tile->mem.vram.usable_size = vram_size;
+		tile->mem.vram.mapping = xe->mem.vram.mapping + tile_offset;
+
+		if (tile->mem.vram.io_size < tile->mem.vram.usable_size)
+			drm_info(&xe->drm, "Small BAR device\n");
+		drm_info(&xe->drm, "VRAM[%u, %u]: Actual physical size %pa, usable size exclude stolen %pa, CPU accessible size %pa\n", id,
+			 tile->id, &tile->mem.vram.actual_physical_size, &tile->mem.vram.usable_size, &tile->mem.vram.io_size);
+		drm_info(&xe->drm, "VRAM[%u, %u]: DPA range: [%pa-%llx], io range: [%pa-%llx]\n", id, tile->id,
+			 &tile->mem.vram.dpa_base, tile->mem.vram.dpa_base + (u64)tile->mem.vram.actual_physical_size,
+			 &tile->mem.vram.io_start, tile->mem.vram.io_start + (u64)tile->mem.vram.io_size);
+
+		/* calculate total size using tile size to get the correct HW sizing */
+		total_size += tile_size;
+		available_size += vram_size;
+
+		if (total_size > xe->mem.vram.io_size) {
+			drm_info(&xe->drm, "VRAM: %pa is larger than resource %pa\n",
+				 &total_size, &xe->mem.vram.io_size);
+		}
+
+		io_size -= min_t(u64, tile_size, io_size);
+	}
+
+	xe->mem.vram.actual_physical_size = total_size;
+
+	drm_info(&xe->drm, "Total VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
+		 &xe->mem.vram.actual_physical_size);
+	drm_info(&xe->drm, "Available VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
+		 &available_size);
+
+	return devm_add_action_or_reset(xe->drm.dev, vram_fini, xe);
+}
diff --git a/drivers/gpu/drm/xe/xe_vram.h b/drivers/gpu/drm/xe/xe_vram.h
new file mode 100644
index 000000000000..e31cc04ec0db
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_vram.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef _XE_VRAM_H_
+#define _XE_VRAM_H_
+
+struct xe_device;
+
+int xe_vram_probe(struct xe_device *xe);
+
+#endif
-- 
2.43.0

[PATCH 4/5] drm/xe: Rename internal vram helper function

[Michal Wajdeczko]

Drop no longer applicable "xe_mmio_" prefix and downgrade the
existing kernel-doc for internal function to normal comment.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/xe/xe_vram.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
index d8b81e4e050c..411e8d23fd4d 100644
--- a/drivers/gpu/drm/xe/xe_vram.c
+++ b/drivers/gpu/drm/xe/xe_vram.c
@@ -192,8 +192,8 @@ static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
 	return offset;
 }
 
-/**
- * xe_mmio_tile_vram_size() - Collect vram size and offset information
+/*
+ * tile_vram_size() - Collect vram size and offset information
  * @tile: tile to get info for
  * @vram_size: available vram (size - device reserved portions)
  * @tile_size: actual vram size
@@ -211,8 +211,8 @@ static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
  * NOTE: multi-tile bases will include the tile offset.
  *
  */
-static int xe_mmio_tile_vram_size(struct xe_tile *tile, u64 *vram_size,
-				  u64 *tile_size, u64 *tile_offset)
+static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
+			  u64 *tile_size, u64 *tile_offset)
 {
 	struct xe_device *xe = tile_to_xe(tile);
 	struct xe_gt *gt = tile->primary_gt;
@@ -287,7 +287,7 @@ int xe_vram_probe(struct xe_device *xe)
 
 	/* Get the size of the root tile's vram for later accessibility comparison */
 	tile = xe_device_get_root_tile(xe);
-	err = xe_mmio_tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
+	err = tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
 	if (err)
 		return err;
 
@@ -302,7 +302,7 @@ int xe_vram_probe(struct xe_device *xe)
 
 	/* tile specific ranges */
 	for_each_tile(tile, xe, id) {
-		err = xe_mmio_tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
+		err = tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
 		if (err)
 			return err;
 
-- 
2.43.0

[PATCH 5/5] drm/xe/vf: Setup VRAM based on received config data

[Michal Wajdeczko]

VF drivers will obtain VRAM configuration from the GuC as part of
the VF self config. Use that configuration instead of trying to
read inaccessible registers.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/xe/xe_gt_sriov_vf.c | 17 +++++++++++++++++
 drivers/gpu/drm/xe/xe_gt_sriov_vf.h |  1 +
 drivers/gpu/drm/xe/xe_vram.c        | 18 ++++++++++++++++++
 3 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_vf.c b/drivers/gpu/drm/xe/xe_gt_sriov_vf.c
index da7c64f6285b..41e46a00c01e 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_vf.c
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_vf.c
@@ -478,6 +478,23 @@ u16 xe_gt_sriov_vf_guc_ids(struct xe_gt *gt)
 	return gt->sriov.vf.self_config.num_ctxs;
 }
 
+/**
+ * xe_gt_sriov_vf_lmem - VF LMEM configuration.
+ * @gt: the &xe_gt
+ *
+ * This function is for VF use only.
+ *
+ * Return: size of the LMEM assigned to VF.
+ */
+u64 xe_gt_sriov_vf_lmem(struct xe_gt *gt)
+{
+	xe_gt_assert(gt, IS_SRIOV_VF(gt_to_xe(gt)));
+	xe_gt_assert(gt, gt->sriov.vf.guc_version.major);
+	xe_gt_assert(gt, gt->sriov.vf.self_config.lmem_size);
+
+	return gt->sriov.vf.self_config.lmem_size;
+}
+
 static int vf_balloon_ggtt(struct xe_gt *gt)
 {
 	struct xe_gt_sriov_vf_selfconfig *config = &gt->sriov.vf.self_config;
diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_vf.h b/drivers/gpu/drm/xe/xe_gt_sriov_vf.h
index 7a04bcaffe9f..0de7f8cbcfa6 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_vf.h
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_vf.h
@@ -20,6 +20,7 @@ int xe_gt_sriov_vf_prepare_ggtt(struct xe_gt *gt);
 
 u32 xe_gt_sriov_vf_gmdid(struct xe_gt *gt);
 u16 xe_gt_sriov_vf_guc_ids(struct xe_gt *gt);
+u64 xe_gt_sriov_vf_lmem(struct xe_gt *gt);
 u32 xe_gt_sriov_vf_read32(struct xe_gt *gt, struct xe_reg reg);
 
 void xe_gt_sriov_vf_print_config(struct xe_gt *gt, struct drm_printer *p);
diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
index 411e8d23fd4d..ccc4791c0e34 100644
--- a/drivers/gpu/drm/xe/xe_vram.c
+++ b/drivers/gpu/drm/xe/xe_vram.c
@@ -15,8 +15,10 @@
 #include "xe_device.h"
 #include "xe_force_wake.h"
 #include "xe_gt_mcr.h"
+#include "xe_gt_sriov_vf.h"
 #include "xe_mmio.h"
 #include "xe_module.h"
+#include "xe_sriov.h"
 #include "xe_vram.h"
 
 #define BAR_SIZE_SHIFT 20
@@ -220,6 +222,22 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
 	int err;
 	u32 reg;
 
+	if (IS_SRIOV_VF(xe)) {
+		struct xe_tile *t;
+		int id;
+
+		offset = 0;
+		for_each_tile(t, xe, id)
+			for_each_if(t->id < tile->id)
+				offset += xe_gt_sriov_vf_lmem(t->primary_gt);
+
+		*tile_size = xe_gt_sriov_vf_lmem(gt);
+		*vram_size = *tile_size;
+		*tile_offset = offset;
+
+		return 0;
+	}
+
 	err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
 	if (err)
 		return err;
-- 
2.43.0

✓ CI.Patch_applied: success for VF: Setup VRAM based on received config data

[Patchwork]

== Series Details ==

Series: VF: Setup VRAM based on received config data
URL   : https://patchwork.freedesktop.org/series/134097/
State : success

== Summary ==

=== Applying kernel patches on branch 'drm-tip' with base: ===
Base commit: 0f0c00c367c8 drm-tip: 2024y-05m-27d-16h-52m-00s UTC integration manifest
=== git am output follows ===
Applying: drm/xe: Move XEHP_MTCFG_ADDR register definition to xe_regs.h
Applying: drm/xe: Move BAR definitions to dedicated file
Applying: drm/xe: Promote VRAM initialization function to own file
Applying: drm/xe: Rename internal vram helper function
Applying: drm/xe/vf: Setup VRAM based on received config data

✗ CI.checkpatch: warning for VF: Setup VRAM based on received config data

[Patchwork]

== Series Details ==

Series: VF: Setup VRAM based on received config data
URL   : https://patchwork.freedesktop.org/series/134097/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
51ce9f6cd981d42d7467409d7dbc559a450abc1e
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 2e2f3baed713ab3990efb5cd7d7ad7395b483224
Author: Michal Wajdeczko <michal.wajdeczko@intel.com>
Date:   Mon May 27 19:35:54 2024 +0200

    drm/xe/vf: Setup VRAM based on received config data
    
    VF drivers will obtain VRAM configuration from the GuC as part of
    the VF self config. Use that configuration instead of trying to
    read inaccessible registers.
    
    Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
+ /mt/dim checkpatch 0f0c00c367c8a8621a07443664d5f9a266889e84 drm-intel
7643ce7c27f9 drm/xe: Move XEHP_MTCFG_ADDR register definition to xe_regs.h
1b8ded9f1014 drm/xe: Move BAR definitions to dedicated file
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:14: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#14: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 41 lines checked
af18993b70d9 drm/xe: Promote VRAM initialization function to own file
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:402: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#402: 
new file mode 100644

-:644: WARNING:BRACES: braces {} are not necessary for any arm of this statement
#644: FILE: drivers/gpu/drm/xe/xe_vram.c:238:
+	if (xe->info.has_flat_ccs) {
[...]
+	} else {
[...]

-:730: WARNING:LONG_LINE: line length of 139 exceeds 100 columns
#730: FILE: drivers/gpu/drm/xe/xe_vram.c:324:
+		drm_info(&xe->drm, "VRAM[%u, %u]: Actual physical size %pa, usable size exclude stolen %pa, CPU accessible size %pa\n", id,

-:731: WARNING:LONG_LINE: line length of 127 exceeds 100 columns
#731: FILE: drivers/gpu/drm/xe/xe_vram.c:325:
+			 tile->id, &tile->mem.vram.actual_physical_size, &tile->mem.vram.usable_size, &tile->mem.vram.io_size);

-:732: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#732: FILE: drivers/gpu/drm/xe/xe_vram.c:326:
+		drm_info(&xe->drm, "VRAM[%u, %u]: DPA range: [%pa-%llx], io range: [%pa-%llx]\n", id, tile->id,

-:733: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#733: FILE: drivers/gpu/drm/xe/xe_vram.c:327:
+			 &tile->mem.vram.dpa_base, tile->mem.vram.dpa_base + (u64)tile->mem.vram.actual_physical_size,

-:734: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#734: FILE: drivers/gpu/drm/xe/xe_vram.c:328:
+			 &tile->mem.vram.io_start, tile->mem.vram.io_start + (u64)tile->mem.vram.io_size);

total: 0 errors, 7 warnings, 0 checks, 735 lines checked
f7d9cbaec1e6 drm/xe: Rename internal vram helper function
2e2f3baed713 drm/xe/vf: Setup VRAM based on received config data

✓ CI.KUnit: success for VF: Setup VRAM based on received config data

[Patchwork]

== Series Details ==

Series: VF: Setup VRAM based on received config data
URL   : https://patchwork.freedesktop.org/series/134097/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[17:42:29] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:42:34] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes]
  156 | u64 ioread64_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes]
  163 | u64 ioread64_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes]
  170 | u64 ioread64be_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes]
  178 | u64 ioread64be_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes]
  264 | void iowrite64_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes]
  272 | void iowrite64_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes]
  280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~
../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes]
  288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~

[17:43:00] Starting KUnit Kernel (1/1)...
[17:43:00] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:43:00] =================== guc_dbm (7 subtests) ===================
[17:43:00] [PASSED] test_empty
[17:43:00] [PASSED] test_default
[17:43:00] ======================== test_size  ========================
[17:43:00] [PASSED] 4
[17:43:00] [PASSED] 8
[17:43:00] [PASSED] 32
[17:43:00] [PASSED] 256
[17:43:00] ==================== [PASSED] test_size ====================
[17:43:00] ======================= test_reuse  ========================
[17:43:00] [PASSED] 4
[17:43:00] [PASSED] 8
[17:43:00] [PASSED] 32
[17:43:00] [PASSED] 256
[17:43:00] =================== [PASSED] test_reuse ====================
[17:43:00] =================== test_range_overlap  ====================
[17:43:00] [PASSED] 4
[17:43:00] [PASSED] 8
[17:43:00] [PASSED] 32
[17:43:00] [PASSED] 256
[17:43:00] =============== [PASSED] test_range_overlap ================
[17:43:00] =================== test_range_compact  ====================
[17:43:00] [PASSED] 4
[17:43:00] [PASSED] 8
[17:43:00] [PASSED] 32
[17:43:00] [PASSED] 256
[17:43:00] =============== [PASSED] test_range_compact ================
[17:43:00] ==================== test_range_spare  =====================
[17:43:00] [PASSED] 4
[17:43:00] [PASSED] 8
[17:43:00] [PASSED] 32
[17:43:00] [PASSED] 256
[17:43:00] ================ [PASSED] test_range_spare =================
[17:43:00] ===================== [PASSED] guc_dbm =====================
[17:43:00] =================== guc_idm (6 subtests) ===================
[17:43:00] [PASSED] bad_init
[17:43:00] [PASSED] no_init
[17:43:00] [PASSED] init_fini
[17:43:00] [PASSED] check_used
[17:43:00] [PASSED] check_quota
[17:43:00] [PASSED] check_all
[17:43:00] ===================== [PASSED] guc_idm =====================
[17:43:00] ================== no_relay (3 subtests) ===================
[17:43:00] [PASSED] xe_drops_guc2pf_if_not_ready
[17:43:00] [PASSED] xe_drops_guc2vf_if_not_ready
[17:43:00] [PASSED] xe_rejects_send_if_not_ready
[17:43:00] ==================== [PASSED] no_relay =====================
[17:43:00] ================== pf_relay (14 subtests) ==================
[17:43:00] [PASSED] pf_rejects_guc2pf_too_short
[17:43:00] [PASSED] pf_rejects_guc2pf_too_long
[17:43:00] [PASSED] pf_rejects_guc2pf_no_payload
[17:43:00] [PASSED] pf_fails_no_payload
[17:43:00] [PASSED] pf_fails_bad_origin
[17:43:00] [PASSED] pf_fails_bad_type
[17:43:00] [PASSED] pf_txn_reports_error
[17:43:00] [PASSED] pf_txn_sends_pf2guc
[17:43:00] [PASSED] pf_sends_pf2guc
[17:43:00] [SKIPPED] pf_loopback_nop
[17:43:00] [SKIPPED] pf_loopback_echo
[17:43:00] [SKIPPED] pf_loopback_fail
[17:43:00] [SKIPPED] pf_loopback_busy
[17:43:00] [SKIPPED] pf_loopback_retry
[17:43:00] ==================== [PASSED] pf_relay =====================
[17:43:00] ================== vf_relay (3 subtests) ===================
[17:43:00] [PASSED] vf_rejects_guc2vf_too_short
[17:43:00] [PASSED] vf_rejects_guc2vf_too_long
[17:43:00] [PASSED] vf_rejects_guc2vf_no_payload
[17:43:00] ==================== [PASSED] vf_relay =====================
[17:43:00] ================= pf_service (11 subtests) =================
[17:43:00] [PASSED] pf_negotiate_any
[17:43:00] [PASSED] pf_negotiate_base_match
[17:43:00] [PASSED] pf_negotiate_base_newer
[17:43:00] [PASSED] pf_negotiate_base_next
[17:43:00] [SKIPPED] pf_negotiate_base_older
[17:43:00] [PASSED] pf_negotiate_base_prev
[17:43:00] [PASSED] pf_negotiate_latest_match
[17:43:00] [PASSED] pf_negotiate_latest_newer
[17:43:00] [PASSED] pf_negotiate_latest_next
[17:43:00] [SKIPPED] pf_negotiate_latest_older
[17:43:00] [SKIPPED] pf_negotiate_latest_prev
[17:43:00] =================== [PASSED] pf_service ====================
[17:43:00] ===================== lmtt (1 subtest) =====================
[17:43:00] ======================== test_ops  =========================
[17:43:00] [PASSED] 2-level
[17:43:00] [PASSED] multi-level
[17:43:00] ==================== [PASSED] test_ops =====================
[17:43:00] ====================== [PASSED] lmtt =======================
[17:43:00] ==================== xe_bo (2 subtests) ====================
[17:43:00] [SKIPPED] xe_ccs_migrate_kunit
[17:43:00] [SKIPPED] xe_bo_evict_kunit
[17:43:00] ===================== [SKIPPED] xe_bo ======================
[17:43:00] ================== xe_dma_buf (1 subtest) ==================
[17:43:00] [SKIPPED] xe_dma_buf_kunit
[17:43:00] =================== [SKIPPED] xe_dma_buf ===================
[17:43:00] ================== xe_migrate (1 subtest) ==================
[17:43:00] [SKIPPED] xe_migrate_sanity_kunit
[17:43:00] =================== [SKIPPED] xe_migrate ===================
[17:43:00] =================== xe_mocs (2 subtests) ===================
[17:43:00] [SKIPPED] xe_live_mocs_kernel_kunit
[17:43:00] [SKIPPED] xe_live_mocs_reset_kunit
[17:43:00] ==================== [SKIPPED] xe_mocs =====================
[17:43:00] ==================== args (11 subtests) ====================
[17:43:00] [PASSED] count_args_test
[17:43:00] [PASSED] call_args_example
[17:43:00] [PASSED] call_args_test
[17:43:00] [PASSED] drop_first_arg_example
[17:43:00] [PASSED] drop_first_arg_test
[17:43:00] [PASSED] first_arg_example
[17:43:00] [PASSED] first_arg_test
[17:43:00] [PASSED] last_arg_example
[17:43:00] [PASSED] last_arg_test
[17:43:00] [PASSED] pick_arg_example
[17:43:00] [PASSED] sep_comma_example
[17:43:00] ====================== [PASSED] args =======================
[17:43:00] =================== xe_pci (2 subtests) ====================
[17:43:00] [PASSED] xe_gmdid_graphics_ip
[17:43:00] [PASSED] xe_gmdid_media_ip
[17:43:00] ===================== [PASSED] xe_pci ======================
[17:43:00] ==================== xe_rtp (1 subtest) ====================
[17:43:00] ================== xe_rtp_process_tests  ===================
[17:43:00] [PASSED] coalesce-same-reg
[17:43:00] [PASSED] no-match-no-add
[17:43:00] [PASSED] no-match-no-add-multiple-rules
[17:43:00] [PASSED] two-regs-two-entries
[17:43:00] [PASSED] clr-one-set-other
[17:43:00] [PASSED] set-field
[17:43:00] [PASSED] conflict-duplicate
[17:43:00] [PASSED] conflict-not-disjoint
[17:43:00] [PASSED] conflict-reg-type
[17:43:00] ============== [PASSED] xe_rtp_process_tests ===============
stty: 'standard input': Inappropriate ioctl for device
[17:43:00] ===================== [PASSED] xe_rtp ======================
[17:43:00] ==================== xe_wa (1 subtest) =====================
[17:43:00] ======================== xe_wa_gt  =========================
[17:43:00] [PASSED] TIGERLAKE (B0)
[17:43:00] [PASSED] DG1 (A0)
[17:43:00] [PASSED] DG1 (B0)
[17:43:00] [PASSED] ALDERLAKE_S (A0)
[17:43:00] [PASSED] ALDERLAKE_S (B0)
[17:43:00] [PASSED] ALDERLAKE_S (C0)
[17:43:00] [PASSED] ALDERLAKE_S (D0)
[17:43:00] [PASSED] ALDERLAKE_P (A0)
[17:43:00] [PASSED] ALDERLAKE_P (B0)
[17:43:00] [PASSED] ALDERLAKE_P (C0)
[17:43:00] [PASSED] ALDERLAKE_S_RPLS (D0)
[17:43:00] [PASSED] ALDERLAKE_P_RPLU (E0)
[17:43:00] [PASSED] DG2_G10 (C0)
[17:43:00] [PASSED] DG2_G11 (B1)
[17:43:00] [PASSED] DG2_G12 (A1)
[17:43:00] [PASSED] METEORLAKE (g:A0, m:A0)
[17:43:00] [PASSED] METEORLAKE (g:A0, m:A0)
[17:43:00] [PASSED] METEORLAKE (g:A0, m:A0)
[17:43:00] [PASSED] LUNARLAKE (g:A0, m:A0)
[17:43:00] [PASSED] LUNARLAKE (g:B0, m:A0)
[17:43:00] ==================== [PASSED] xe_wa_gt =====================
[17:43:00] ====================== [PASSED] xe_wa ======================
[17:43:00] ============================================================
[17:43:00] Testing complete. Ran 109 tests: passed: 95, skipped: 14
[17:43:00] Elapsed time: 31.010s total, 4.283s configuring, 26.456s building, 0.216s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[17:43:00] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:43:02] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes]
  156 | u64 ioread64_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes]
  163 | u64 ioread64_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes]
  170 | u64 ioread64be_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes]
  178 | u64 ioread64be_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes]
  264 | void iowrite64_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes]
  272 | void iowrite64_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes]
  280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~
../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes]
  288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~

[17:43:23] Starting KUnit Kernel (1/1)...
[17:43:23] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:43:24] ============ drm_test_pick_cmdline (2 subtests) ============
[17:43:24] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[17:43:24] =============== drm_test_pick_cmdline_named  ===============
[17:43:24] [PASSED] NTSC
[17:43:24] [PASSED] NTSC-J
[17:43:24] [PASSED] PAL
[17:43:24] [PASSED] PAL-M
[17:43:24] =========== [PASSED] drm_test_pick_cmdline_named ===========
[17:43:24] ============== [PASSED] drm_test_pick_cmdline ==============
[17:43:24] ================== drm_buddy (7 subtests) ==================
[17:43:24] [PASSED] drm_test_buddy_alloc_limit
[17:43:24] [PASSED] drm_test_buddy_alloc_optimistic
[17:43:24] [PASSED] drm_test_buddy_alloc_pessimistic
[17:43:24] [PASSED] drm_test_buddy_alloc_pathological
[17:43:24] [PASSED] drm_test_buddy_alloc_contiguous
[17:43:24] [PASSED] drm_test_buddy_alloc_clear
[17:43:24] [PASSED] drm_test_buddy_alloc_range_bias
[17:43:24] ==================== [PASSED] drm_buddy ====================
[17:43:24] ============= drm_cmdline_parser (40 subtests) =============
[17:43:24] [PASSED] drm_test_cmdline_force_d_only
[17:43:24] [PASSED] drm_test_cmdline_force_D_only_dvi
[17:43:24] [PASSED] drm_test_cmdline_force_D_only_hdmi
[17:43:24] [PASSED] drm_test_cmdline_force_D_only_not_digital
[17:43:24] [PASSED] drm_test_cmdline_force_e_only
[17:43:24] [PASSED] drm_test_cmdline_res
[17:43:24] [PASSED] drm_test_cmdline_res_vesa
[17:43:24] [PASSED] drm_test_cmdline_res_vesa_rblank
[17:43:24] [PASSED] drm_test_cmdline_res_rblank
[17:43:24] [PASSED] drm_test_cmdline_res_bpp
[17:43:24] [PASSED] drm_test_cmdline_res_refresh
[17:43:24] [PASSED] drm_test_cmdline_res_bpp_refresh
[17:43:24] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[17:43:24] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[17:43:24] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[17:43:24] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[17:43:24] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[17:43:24] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[17:43:24] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[17:43:24] [PASSED] drm_test_cmdline_res_margins_force_on
[17:43:24] [PASSED] drm_test_cmdline_res_vesa_margins
[17:43:24] [PASSED] drm_test_cmdline_name
[17:43:24] [PASSED] drm_test_cmdline_name_bpp
[17:43:24] [PASSED] drm_test_cmdline_name_option
[17:43:24] [PASSED] drm_test_cmdline_name_bpp_option
[17:43:24] [PASSED] drm_test_cmdline_rotate_0
[17:43:24] [PASSED] drm_test_cmdline_rotate_90
[17:43:24] [PASSED] drm_test_cmdline_rotate_180
[17:43:24] [PASSED] drm_test_cmdline_rotate_270
[17:43:24] [PASSED] drm_test_cmdline_hmirror
[17:43:24] [PASSED] drm_test_cmdline_vmirror
[17:43:24] [PASSED] drm_test_cmdline_margin_options
[17:43:24] [PASSED] drm_test_cmdline_multiple_options
[17:43:24] [PASSED] drm_test_cmdline_bpp_extra_and_option
[17:43:24] [PASSED] drm_test_cmdline_extra_and_option
[17:43:24] [PASSED] drm_test_cmdline_freestanding_options
[17:43:24] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[17:43:24] [PASSED] drm_test_cmdline_panel_orientation
[17:43:24] ================ drm_test_cmdline_invalid  =================
[17:43:24] [PASSED] margin_only
[17:43:24] [PASSED] interlace_only
[17:43:24] [PASSED] res_missing_x
[17:43:24] [PASSED] res_missing_y
[17:43:24] [PASSED] res_bad_y
[17:43:24] [PASSED] res_missing_y_bpp
[17:43:24] [PASSED] res_bad_bpp
[17:43:24] [PASSED] res_bad_refresh
[17:43:24] [PASSED] res_bpp_refresh_force_on_off
[17:43:24] [PASSED] res_invalid_mode
[17:43:24] [PASSED] res_bpp_wrong_place_mode
[17:43:24] [PASSED] name_bpp_refresh
[17:43:24] [PASSED] name_refresh
[17:43:24] [PASSED] name_refresh_wrong_mode
[17:43:24] [PASSED] name_refresh_invalid_mode
[17:43:24] [PASSED] rotate_multiple
[17:43:24] [PASSED] rotate_invalid_val
[17:43:24] [PASSED] rotate_truncated
[17:43:24] [PASSED] invalid_option
[17:43:24] [PASSED] invalid_tv_option
[17:43:24] [PASSED] truncated_tv_option
[17:43:24] ============ [PASSED] drm_test_cmdline_invalid =============
[17:43:24] =============== drm_test_cmdline_tv_options  ===============
[17:43:24] [PASSED] NTSC
[17:43:24] [PASSED] NTSC_443
[17:43:24] [PASSED] NTSC_J
[17:43:24] [PASSED] PAL
[17:43:24] [PASSED] PAL_M
[17:43:24] [PASSED] PAL_N
[17:43:24] [PASSED] SECAM
[17:43:24] =========== [PASSED] drm_test_cmdline_tv_options ===========
[17:43:24] =============== [PASSED] drm_cmdline_parser ================
[17:43:24] ============= drmm_connector_init (3 subtests) =============
[17:43:24] [PASSED] drm_test_drmm_connector_init
[17:43:24] [PASSED] drm_test_drmm_connector_init_null_ddc
[17:43:24] ========= drm_test_drmm_connector_init_type_valid  =========
[17:43:24] [PASSED] Unknown
[17:43:24] [PASSED] VGA
[17:43:24] [PASSED] DVI-I
[17:43:24] [PASSED] DVI-D
[17:43:24] [PASSED] DVI-A
[17:43:24] [PASSED] Composite
[17:43:24] [PASSED] SVIDEO
[17:43:24] [PASSED] LVDS
[17:43:24] [PASSED] Component
[17:43:24] [PASSED] DIN
[17:43:24] [PASSED] DP
[17:43:24] [PASSED] HDMI-A
[17:43:24] [PASSED] HDMI-B
[17:43:24] [PASSED] TV
[17:43:24] [PASSED] eDP
[17:43:24] [PASSED] Virtual
[17:43:24] [PASSED] DSI
[17:43:24] [PASSED] DPI
[17:43:24] [PASSED] Writeback
[17:43:24] [PASSED] SPI
[17:43:24] [PASSED] USB
[17:43:24] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[17:43:24] =============== [PASSED] drmm_connector_init ===============
[17:43:24] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[17:43:24] ========== drm_test_get_tv_mode_from_name_valid  ===========
[17:43:24] [PASSED] NTSC
[17:43:24] [PASSED] NTSC-443
[17:43:24] [PASSED] NTSC-J
[17:43:24] [PASSED] PAL
[17:43:24] [PASSED] PAL-M
[17:43:24] [PASSED] PAL-N
[17:43:24] [PASSED] SECAM
[17:43:24] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[17:43:24] [PASSED] drm_test_get_tv_mode_from_name_truncated
[17:43:24] ============ [PASSED] drm_get_tv_mode_from_name ============
[17:43:24] ============= drm_damage_helper (21 subtests) ==============
[17:43:24] [PASSED] drm_test_damage_iter_no_damage
[17:43:24] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[17:43:24] [PASSED] drm_test_damage_iter_no_damage_src_moved
[17:43:24] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[17:43:24] [PASSED] drm_test_damage_iter_no_damage_not_visible
[17:43:24] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[17:43:24] [PASSED] drm_test_damage_iter_no_damage_no_fb
[17:43:24] [PASSED] drm_test_damage_iter_simple_damage
[17:43:24] [PASSED] drm_test_damage_iter_single_damage
[17:43:24] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[17:43:24] [PASSED] drm_test_damage_iter_single_damage_outside_src
[17:43:24] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[17:43:24] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[17:43:24] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[17:43:24] [PASSED] drm_test_damage_iter_single_damage_src_moved
[17:43:24] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[17:43:24] [PASSED] drm_test_damage_iter_damage
[17:43:24] [PASSED] drm_test_damage_iter_damage_one_intersect
[17:43:24] [PASSED] drm_test_damage_iter_damage_one_outside
[17:43:24] [PASSED] drm_test_damage_iter_damage_src_moved
[17:43:24] [PASSED] drm_test_damage_iter_damage_not_visible
[17:43:24] ================ [PASSED] drm_damage_helper ================
[17:43:24] ============== drm_dp_mst_helper (3 subtests) ==============
[17:43:24] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[17:43:24] [PASSED] Clock 154000 BPP 30 DSC disabled
[17:43:24] [PASSED] Clock 234000 BPP 30 DSC disabled
[17:43:24] [PASSED] Clock 297000 BPP 24 DSC disabled
[17:43:24] [PASSED] Clock 332880 BPP 24 DSC enabled
[17:43:24] [PASSED] Clock 324540 BPP 24 DSC enabled
[17:43:24] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[17:43:24] ============== drm_test_dp_mst_calc_pbn_div  ===============
[17:43:24] [PASSED] Link rate 2000000 lane count 4
[17:43:24] [PASSED] Link rate 2000000 lane count 2
[17:43:24] [PASSED] Link rate 2000000 lane count 1
[17:43:24] [PASSED] Link rate 1350000 lane count 4
[17:43:24] [PASSED] Link rate 1350000 lane count 2
[17:43:24] [PASSED] Link rate 1350000 lane count 1
[17:43:24] [PASSED] Link rate 1000000 lane count 4
[17:43:24] [PASSED] Link rate 1000000 lane count 2
[17:43:24] [PASSED] Link rate 1000000 lane count 1
[17:43:24] [PASSED] Link rate 810000 lane count 4
[17:43:24] [PASSED] Link rate 810000 lane count 2
[17:43:24] [PASSED] Link rate 810000 lane count 1
[17:43:24] [PASSED] Link rate 540000 lane count 4
[17:43:24] [PASSED] Link rate 540000 lane count 2
[17:43:24] [PASSED] Link rate 540000 lane count 1
[17:43:24] [PASSED] Link rate 270000 lane count 4
[17:43:24] [PASSED] Link rate 270000 lane count 2
[17:43:24] [PASSED] Link rate 270000 lane count 1
[17:43:24] [PASSED] Link rate 162000 lane count 4
[17:43:24] [PASSED] Link rate 162000 lane count 2
[17:43:24] [PASSED] Link rate 162000 lane count 1
[17:43:24] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[17:43:24] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[17:43:24] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[17:43:24] [PASSED] DP_POWER_UP_PHY with port number
[17:43:24] [PASSED] DP_POWER_DOWN_PHY with port number
[17:43:24] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[17:43:24] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[17:43:24] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[17:43:24] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[17:43:24] [PASSED] DP_QUERY_PAYLOAD with port number
[17:43:24] [PASSED] DP_QUERY_PAYLOAD with VCPI
[17:43:24] [PASSED] DP_REMOTE_DPCD_READ with port number
[17:43:24] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[17:43:24] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[17:43:24] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[17:43:24] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[17:43:24] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[17:43:24] [PASSED] DP_REMOTE_I2C_READ with port number
[17:43:24] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[17:43:24] [PASSED] DP_REMOTE_I2C_READ with transactions array
[17:43:24] [PASSED] DP_REMOTE_I2C_WRITE with port number
[17:43:24] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[17:43:24] [PASSED] DP_REMOTE_I2C_WRITE with data array
[17:43:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[17:43:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[17:43:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[17:43:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[17:43:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[17:43:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[17:43:24] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[17:43:24] ================ [PASSED] drm_dp_mst_helper ================
[17:43:24] ================== drm_exec (7 subtests) ===================
[17:43:24] [PASSED] sanitycheck
[17:43:24] [PASSED] test_lock
[17:43:24] [PASSED] test_lock_unlock
[17:43:24] [PASSED] test_duplicates
[17:43:24] [PASSED] test_prepare
[17:43:24] [PASSED] test_prepare_array
[17:43:24] [PASSED] test_multiple_loops
[17:43:24] ==================== [PASSED] drm_exec =====================
[17:43:24] =========== drm_format_helper_test (17 subtests) ===========
[17:43:24] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[17:43:24] [PASSED] single_pixel_source_buffer
[17:43:24] [PASSED] single_pixel_clip_rectangle
[17:43:24] [PASSED] well_known_colors
[17:43:24] [PASSED] destination_pitch
[17:43:24] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[17:43:24] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[17:43:24] [PASSED] single_pixel_source_buffer
[17:43:24] [PASSED] single_pixel_clip_rectangle
[17:43:24] [PASSED] well_known_colors
[17:43:24] [PASSED] destination_pitch
[17:43:24] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[17:43:24] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[17:43:24] [PASSED] single_pixel_source_buffer
[17:43:24] [PASSED] single_pixel_clip_rectangle
[17:43:24] [PASSED] well_known_colors
[17:43:24] [PASSED] destination_pitch
[17:43:24] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[17:43:24] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[17:43:24] [PASSED] single_pixel_source_buffer
[17:43:24] [PASSED] single_pixel_clip_rectangle
[17:43:24] [PASSED] well_known_colors
[17:43:24] [PASSED] destination_pitch
[17:43:24] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[17:43:24] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[17:43:24] [PASSED] single_pixel_source_buffer
[17:43:24] [PASSED] single_pixel_clip_rectangle
[17:43:24] [PASSED] well_known_colors
[17:43:24] [PASSED] destination_pitch
[17:43:24] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[17:43:24] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[17:43:24] [PASSED] single_pixel_source_buffer
[17:43:24] [PASSED] single_pixel_clip_rectangle
[17:43:24] [PASSED] well_known_colors
[17:43:24] [PASSED] destination_pitch
[17:43:24] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[17:43:24] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[17:43:24] [PASSED] single_pixel_source_buffer
[17:43:24] [PASSED] single_pixel_clip_rectangle
[17:43:24] [PASSED] well_known_colors
[17:43:24] [PASSED] destination_pitch
[17:43:24] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[17:43:24] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[17:43:24] [PASSED] single_pixel_source_buffer
[17:43:24] [PASSED] single_pixel_clip_rectangle
[17:43:24] [PASSED] well_known_colors
[17:43:24] [PASSED] destination_pitch
[17:43:24] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[17:43:24] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[17:43:24] [PASSED] single_pixel_source_buffer
[17:43:24] [PASSED] single_pixel_clip_rectangle
[17:43:24] [PASSED] well_known_colors
[17:43:24] [PASSED] destination_pitch
[17:43:24] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[17:43:24] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[17:43:24] [PASSED] single_pixel_source_buffer
[17:43:24] [PASSED] single_pixel_clip_rectangle
[17:43:24] [PASSED] well_known_colors
[17:43:24] [PASSED] destination_pitch
[17:43:24] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[17:43:24] ============== drm_test_fb_xrgb8888_to_mono  ===============
[17:43:24] [PASSED] single_pixel_source_buffer
[17:43:24] [PASSED] single_pixel_clip_rectangle
[17:43:24] [PASSED] well_known_colors
[17:43:24] [PASSED] destination_pitch
[17:43:24] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[17:43:24] ==================== drm_test_fb_swab  =====================
[17:43:24] [PASSED] single_pixel_source_buffer
[17:43:24] [PASSED] single_pixel_clip_rectangle
[17:43:24] [PASSED] well_known_colors
[17:43:24] [PASSED] destination_pitch
[17:43:24] ================ [PASSED] drm_test_fb_swab =================
[17:43:24] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[17:43:24] [PASSED] single_pixel_source_buffer
[17:43:24] [PASSED] single_pixel_clip_rectangle
[17:43:24] [PASSED] well_known_colors
[17:43:24] [PASSED] destination_pitch
[17:43:24] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[17:43:24] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[17:43:24] [PASSED] single_pixel_source_buffer
[17:43:24] [PASSED] single_pixel_clip_rectangle
[17:43:24] [PASSED] well_known_colors
[17:43:24] [PASSED] destination_pitch
[17:43:24] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[17:43:24] ================= drm_test_fb_clip_offset  =================
[17:43:24] [PASSED] pass through
[17:43:24] [PASSED] horizontal offset
[17:43:24] [PASSED] vertical offset
[17:43:24] [PASSED] horizontal and vertical offset
[17:43:24] [PASSED] horizontal offset (custom pitch)
[17:43:24] [PASSED] vertical offset (custom pitch)
[17:43:24] [PASSED] horizontal and vertical offset (custom pitch)
[17:43:24] ============= [PASSED] drm_test_fb_clip_offset =============
[17:43:24] ============== drm_test_fb_build_fourcc_list  ==============
[17:43:24] [PASSED] no native formats
[17:43:24] [PASSED] XRGB8888 as native format
[17:43:24] [PASSED] remove duplicates
[17:43:24] [PASSED] convert alpha formats
[17:43:24] [PASSED] random formats
[17:43:24] ========== [PASSED] drm_test_fb_build_fourcc_list ==========
[17:43:24] =================== drm_test_fb_memcpy  ====================
[17:43:24] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[17:43:24] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[17:43:24] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[17:43:24] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[17:43:24] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[17:43:24] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[17:43:24] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[17:43:24] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[17:43:24] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[17:43:24] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[17:43:24] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[17:43:24] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[17:43:24] =============== [PASSED] drm_test_fb_memcpy ================
[17:43:24] ============= [PASSED] drm_format_helper_test ==============
[17:43:24] ================= drm_format (18 subtests) =================
[17:43:24] [PASSED] drm_test_format_block_width_invalid
[17:43:24] [PASSED] drm_test_format_block_width_one_plane
[17:43:24] [PASSED] drm_test_format_block_width_two_plane
[17:43:24] [PASSED] drm_test_format_block_width_three_plane
[17:43:24] [PASSED] drm_test_format_block_width_tiled
[17:43:24] [PASSED] drm_test_format_block_height_invalid
[17:43:24] [PASSED] drm_test_format_block_height_one_plane
[17:43:24] [PASSED] drm_test_format_block_height_two_plane
[17:43:24] [PASSED] drm_test_format_block_height_three_plane
[17:43:24] [PASSED] drm_test_format_block_height_tiled
[17:43:24] [PASSED] drm_test_format_min_pitch_invalid
[17:43:24] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[17:43:24] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[17:43:24] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[17:43:24] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[17:43:24] [PASSED] drm_test_format_min_pitch_two_plane
[17:43:24] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[17:43:24] [PASSED] drm_test_format_min_pitch_tiled
[17:43:24] =================== [PASSED] drm_format ====================
[17:43:24] =============== drm_framebuffer (1 subtest) ================
[17:43:24] =============== drm_test_framebuffer_create  ===============
[17:43:24] [PASSED] ABGR8888 normal sizes
[17:43:24] [PASSED] ABGR8888 max sizes
[17:43:24] [PASSED] ABGR8888 pitch greater than min required
[17:43:24] [PASSED] ABGR8888 pitch less than min required
[17:43:24] [PASSED] ABGR8888 Invalid width
[17:43:24] [PASSED] ABGR8888 Invalid buffer handle
[17:43:24] [PASSED] No pixel format
[17:43:24] [PASSED] ABGR8888 Width 0
[17:43:24] [PASSED] ABGR8888 Height 0
[17:43:24] [PASSED] ABGR8888 Out of bound height * pitch combination
[17:43:24] [PASSED] ABGR8888 Large buffer offset
[17:43:24] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[17:43:24] [PASSED] ABGR8888 Valid buffer modifier
[17:43:24] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[17:43:24] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[17:43:24] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[17:43:24] [PASSED] NV12 Normal sizes
[17:43:24] [PASSED] NV12 Max sizes
[17:43:24] [PASSED] NV12 Invalid pitch
[17:43:24] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[17:43:24] [PASSED] NV12 different  modifier per-plane
[17:43:24] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[17:43:24] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[17:43:24] [PASSED] NV12 Modifier for inexistent plane
[17:43:24] [PASSED] NV12 Handle for inexistent plane
[17:43:24] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[17:43:24] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[17:43:24] [PASSED] YVU420 Normal sizes
[17:43:24] [PASSED] YVU420 Max sizes
[17:43:24] [PASSED] YVU420 Invalid pitch
[17:43:24] [PASSED] YVU420 Different pitches
[17:43:24] [PASSED] YVU420 Different buffer offsets/pitches
[17:43:24] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[17:43:24] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[17:43:24] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[17:43:24] [PASSED] YVU420 Valid modifier
[17:43:24] [PASSED] YVU420 Different modifiers per plane
[17:43:24] [PASSED] YVU420 Modifier for inexistent plane
[17:43:24] [PASSED] X0L2 Normal sizes
[17:43:24] [PASSED] X0L2 Max sizes
[17:43:24] [PASSED] X0L2 Invalid pitch
[17:43:24] [PASSED] X0L2 Pitch greater than minimum required
[17:43:24] [PASSED] X0L2 Handle for inexistent plane
[17:43:24] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[17:43:24] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[17:43:24] [PASSED] X0L2 Valid modifier
[17:43:24] [PASSED] X0L2 Modifier for inexistent plane
[17:43:24] =========== [PASSED] drm_test_framebuffer_create ===========
[17:43:24] ================= [PASSED] drm_framebuffer =================
[17:43:24] ================ drm_gem_shmem (8 subtests) ================
[17:43:24] [PASSED] drm_gem_shmem_test_obj_create
[17:43:24] [PASSED] drm_gem_shmem_test_obj_create_private
[17:43:24] [PASSED] drm_gem_shmem_test_pin_pages
[17:43:24] [PASSED] drm_gem_shmem_test_vmap
[17:43:24] [PASSED] drm_gem_shmem_test_get_pages_sgt
[17:43:24] [PASSED] drm_gem_shmem_test_get_sg_table
[17:43:24] [PASSED] drm_gem_shmem_test_madvise
[17:43:24] [PASSED] drm_gem_shmem_test_purge
[17:43:24] ================== [PASSED] drm_gem_shmem ==================
[17:43:24] ================= drm_managed (2 subtests) =================
[17:43:24] [PASSED] drm_test_managed_release_action
[17:43:24] [PASSED] drm_test_managed_run_action
[17:43:24] =================== [PASSED] drm_managed ===================
stty: 'standard input': Inappropriate ioctl for device
[17:43:24] =================== drm_mm (6 subtests) ====================
[17:43:24] [PASSED] drm_test_mm_init
[17:43:24] [PASSED] drm_test_mm_debug
[17:43:24] [PASSED] drm_test_mm_align32
[17:43:24] [PASSED] drm_test_mm_align64
[17:43:24] [PASSED] drm_test_mm_lowest
[17:43:24] [PASSED] drm_test_mm_highest
[17:43:24] ===================== [PASSED] drm_mm ======================
[17:43:24] ============= drm_modes_analog_tv (4 subtests) =============
[17:43:24] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[17:43:24] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[17:43:24] [PASSED] drm_test_modes_analog_tv_pal_576i
[17:43:24] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[17:43:24] =============== [PASSED] drm_modes_analog_tv ===============
[17:43:24] ============== drm_plane_helper (2 subtests) ===============
[17:43:24] =============== drm_test_check_plane_state  ================
[17:43:24] [PASSED] clipping_simple
[17:43:24] [PASSED] clipping_rotate_reflect
[17:43:24] [PASSED] positioning_simple
[17:43:24] [PASSED] upscaling
[17:43:24] [PASSED] downscaling
[17:43:24] [PASSED] rounding1
[17:43:24] [PASSED] rounding2
[17:43:24] [PASSED] rounding3
[17:43:24] [PASSED] rounding4
[17:43:24] =========== [PASSED] drm_test_check_plane_state ============
[17:43:24] =========== drm_test_check_invalid_plane_state  ============
[17:43:24] [PASSED] positioning_invalid
[17:43:24] [PASSED] upscaling_invalid
[17:43:24] [PASSED] downscaling_invalid
[17:43:24] ======= [PASSED] drm_test_check_invalid_plane_state ========
[17:43:24] ================ [PASSED] drm_plane_helper =================
[17:43:24] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[17:43:24] ====== drm_test_connector_helper_tv_get_modes_check  =======
[17:43:24] [PASSED] None
[17:43:24] [PASSED] PAL
[17:43:24] [PASSED] NTSC
[17:43:24] [PASSED] Both, NTSC Default
[17:43:24] [PASSED] Both, PAL Default
[17:43:24] [PASSED] Both, NTSC Default, with PAL on command-line
[17:43:24] [PASSED] Both, PAL Default, with NTSC on command-line
[17:43:24] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[17:43:24] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[17:43:24] ================== drm_rect (9 subtests) ===================
[17:43:24] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[17:43:24] [PASSED] drm_test_rect_clip_scaled_not_clipped
[17:43:24] [PASSED] drm_test_rect_clip_scaled_clipped
[17:43:24] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[17:43:24] ================= drm_test_rect_intersect  =================
[17:43:24] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[17:43:24] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[17:43:24] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[17:43:24] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[17:43:24] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[17:43:24] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[17:43:24] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[17:43:24] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[17:43:24] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[17:43:24] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[17:43:24] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[17:43:24] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[17:43:24] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[17:43:24] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[17:43:24] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[17:43:24] ============= [PASSED] drm_test_rect_intersect =============
[17:43:24] ================ drm_test_rect_calc_hscale  ================
[17:43:24] [PASSED] normal use
[17:43:24] [PASSED] out of max range
[17:43:24] [PASSED] out of min range
[17:43:24] [PASSED] zero dst
[17:43:24] [PASSED] negative src
[17:43:24] [PASSED] negative dst
[17:43:24] ============ [PASSED] drm_test_rect_calc_hscale ============
[17:43:24] ================ drm_test_rect_calc_vscale  ================
[17:43:24] [PASSED] normal use
[17:43:24] [PASSED] out of max range
[17:43:24] [PASSED] out of min range
[17:43:24] [PASSED] zero dst
[17:43:24] [PASSED] negative src
[17:43:24] [PASSED] negative dst
[17:43:24] ============ [PASSED] drm_test_rect_calc_vscale ============
[17:43:24] ================== drm_test_rect_rotate  ===================
[17:43:24] [PASSED] reflect-x
[17:43:24] [PASSED] reflect-y
[17:43:24] [PASSED] rotate-0
[17:43:24] [PASSED] rotate-90
[17:43:24] [PASSED] rotate-180
[17:43:24] [PASSED] rotate-270
[17:43:24] ============== [PASSED] drm_test_rect_rotate ===============
[17:43:24] ================ drm_test_rect_rotate_inv  =================
[17:43:24] [PASSED] reflect-x
[17:43:24] [PASSED] reflect-y
[17:43:24] [PASSED] rotate-0
[17:43:24] [PASSED] rotate-90
[17:43:24] [PASSED] rotate-180
[17:43:24] [PASSED] rotate-270
[17:43:24] ============ [PASSED] drm_test_rect_rotate_inv =============
[17:43:24] ==================== [PASSED] drm_rect =====================
[17:43:24] ============================================================
[17:43:24] Testing complete. Ran 417 tests: passed: 417
[17:43:24] Elapsed time: 23.291s total, 1.733s configuring, 21.314s building, 0.195s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ CI.Build: success for VF: Setup VRAM based on received config data

[Patchwork]

== Series Details ==

Series: VF: Setup VRAM based on received config data
URL   : https://patchwork.freedesktop.org/series/134097/
State : success

== Summary ==

lib/modules/6.10.0-rc1-xe/kernel/sound/core/seq/
lib/modules/6.10.0-rc1-xe/kernel/sound/core/seq/snd-seq.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/core/snd-seq-device.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/core/snd-hwdep.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/core/snd.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/core/snd-pcm.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/core/snd-compress.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/core/snd-timer.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soundcore.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/intel/
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/intel/atom/
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/intel/atom/snd-soc-sst-atom-hifi2-platform.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/intel/atom/sst/
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/intel/atom/sst/snd-intel-sst-acpi.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/intel/atom/sst/snd-intel-sst-core.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/intel/common/
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/intel/common/snd-soc-acpi-intel-match.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/amd/
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/amd/snd-acp-config.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/sof/
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/sof/intel/
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-tgl.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda-mlink.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-cnl.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-lnl.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda-common.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda-generic.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-mtl.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/sof/amd/
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/sof/amd/snd-sof-amd-renoir.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/sof/amd/snd-sof-amd-acp.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/sof/snd-sof-utils.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/sof/snd-sof-pci.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/sof/snd-sof.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/sof/snd-sof-probes.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/sof/xtensa/
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/sof/xtensa/snd-sof-xtensa-dsp.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/snd-soc-core.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/snd-soc-acpi.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/codecs/
lib/modules/6.10.0-rc1-xe/kernel/sound/soc/codecs/snd-soc-hdac-hda.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/hda/
lib/modules/6.10.0-rc1-xe/kernel/sound/hda/snd-intel-sdw-acpi.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/hda/ext/
lib/modules/6.10.0-rc1-xe/kernel/sound/hda/ext/snd-hda-ext-core.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/hda/snd-intel-dspcfg.ko
lib/modules/6.10.0-rc1-xe/kernel/sound/hda/snd-hda-core.ko
lib/modules/6.10.0-rc1-xe/kernel/arch/
lib/modules/6.10.0-rc1-xe/kernel/arch/x86/
lib/modules/6.10.0-rc1-xe/kernel/arch/x86/kernel/
lib/modules/6.10.0-rc1-xe/kernel/arch/x86/kernel/msr.ko
lib/modules/6.10.0-rc1-xe/kernel/arch/x86/kernel/cpuid.ko
lib/modules/6.10.0-rc1-xe/kernel/arch/x86/crypto/
lib/modules/6.10.0-rc1-xe/kernel/arch/x86/crypto/sha512-ssse3.ko
lib/modules/6.10.0-rc1-xe/kernel/arch/x86/crypto/crct10dif-pclmul.ko
lib/modules/6.10.0-rc1-xe/kernel/arch/x86/crypto/ghash-clmulni-intel.ko
lib/modules/6.10.0-rc1-xe/kernel/arch/x86/crypto/sha1-ssse3.ko
lib/modules/6.10.0-rc1-xe/kernel/arch/x86/crypto/crc32-pclmul.ko
lib/modules/6.10.0-rc1-xe/kernel/arch/x86/crypto/sha256-ssse3.ko
lib/modules/6.10.0-rc1-xe/kernel/arch/x86/crypto/aesni-intel.ko
lib/modules/6.10.0-rc1-xe/kernel/arch/x86/crypto/polyval-clmulni.ko
lib/modules/6.10.0-rc1-xe/kernel/arch/x86/events/
lib/modules/6.10.0-rc1-xe/kernel/arch/x86/events/intel/
lib/modules/6.10.0-rc1-xe/kernel/arch/x86/events/intel/intel-cstate.ko
lib/modules/6.10.0-rc1-xe/kernel/arch/x86/events/rapl.ko
lib/modules/6.10.0-rc1-xe/kernel/arch/x86/kvm/
lib/modules/6.10.0-rc1-xe/kernel/arch/x86/kvm/kvm.ko
lib/modules/6.10.0-rc1-xe/kernel/arch/x86/kvm/kvm-intel.ko
lib/modules/6.10.0-rc1-xe/kernel/crypto/
lib/modules/6.10.0-rc1-xe/kernel/crypto/crypto_simd.ko
lib/modules/6.10.0-rc1-xe/kernel/crypto/cmac.ko
lib/modules/6.10.0-rc1-xe/kernel/crypto/ccm.ko
lib/modules/6.10.0-rc1-xe/kernel/crypto/cryptd.ko
lib/modules/6.10.0-rc1-xe/kernel/crypto/polyval-generic.ko
lib/modules/6.10.0-rc1-xe/kernel/crypto/async_tx/
lib/modules/6.10.0-rc1-xe/kernel/crypto/async_tx/async_xor.ko
lib/modules/6.10.0-rc1-xe/kernel/crypto/async_tx/async_tx.ko
lib/modules/6.10.0-rc1-xe/kernel/crypto/async_tx/async_memcpy.ko
lib/modules/6.10.0-rc1-xe/kernel/crypto/async_tx/async_pq.ko
lib/modules/6.10.0-rc1-xe/kernel/crypto/async_tx/async_raid6_recov.ko
lib/modules/6.10.0-rc1-xe/build
lib/modules/6.10.0-rc1-xe/modules.alias.bin
lib/modules/6.10.0-rc1-xe/modules.builtin
lib/modules/6.10.0-rc1-xe/modules.softdep
lib/modules/6.10.0-rc1-xe/modules.alias
lib/modules/6.10.0-rc1-xe/modules.order
lib/modules/6.10.0-rc1-xe/modules.symbols
lib/modules/6.10.0-rc1-xe/modules.dep.bin
+ mv kernel-nodebug.tar.gz ..
+ cd ..
+ rm -rf archive
++ date +%s
^[[0Ksection_end:1716832500:package_x86_64_nodebug
^[[0K
+ echo -e '\e[0Ksection_end:1716832500:package_x86_64_nodebug\r\e[0K'
+ sync
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.Hooks: failure for VF: Setup VRAM based on received config data

[Patchwork]

== Series Details ==

Series: VF: Setup VRAM based on received config data
URL   : https://patchwork.freedesktop.org/series/134097/
State : failure

== Summary ==

run-parts: executing /workspace/ci/hooks/00-showenv
+ export
+ grep -Ei '(^|\W)CI_'
declare -x CI_KERNEL_BUILD_DIR="/workspace/kernel/build64-default"
declare -x CI_KERNEL_SRC_DIR="/workspace/kernel"
declare -x CI_TOOLS_SRC_DIR="/workspace/ci"
declare -x CI_WORKSPACE_DIR="/workspace"
run-parts: executing /workspace/ci/hooks/10-build-W1
+ SRC_DIR=/workspace/kernel
+ RESTORE_DISPLAY_CONFIG=0
+ '[' -n /workspace/kernel/build64-default ']'
+ BUILD_DIR=/workspace/kernel/build64-default
+ cd /workspace/kernel
++ nproc
+ make -j48 O=/workspace/kernel/build64-default modules_prepare
make[1]: Entering directory '/workspace/kernel/build64-default'
  GEN     Makefile
  UPD     include/generated/compile.h
  UPD     include/config/kernel.release
mkdir -p /workspace/kernel/build64-default/tools/objtool && make O=/workspace/kernel/build64-default subdir=tools/objtool --no-print-directory -C objtool 
  UPD     include/generated/utsrelease.h
  HOSTCC  /workspace/kernel/build64-default/tools/objtool/fixdep.o
  CALL    ../scripts/checksyscalls.sh
  HOSTLD  /workspace/kernel/build64-default/tools/objtool/fixdep-in.o
  LINK    /workspace/kernel/build64-default/tools/objtool/fixdep
  INSTALL libsubcmd_headers
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/exec-cmd.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/help.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/pager.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/parse-options.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/run-command.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/subcmd-config.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/sigchain.o
  LD      /workspace/kernel/build64-default/tools/objtool/libsubcmd/libsubcmd-in.o
  AR      /workspace/kernel/build64-default/tools/objtool/libsubcmd/libsubcmd.a
  CC      /workspace/kernel/build64-default/tools/objtool/weak.o
  CC      /workspace/kernel/build64-default/tools/objtool/check.o
  CC      /workspace/kernel/build64-default/tools/objtool/special.o
  CC      /workspace/kernel/build64-default/tools/objtool/builtin-check.o
  CC      /workspace/kernel/build64-default/tools/objtool/elf.o
  CC      /workspace/kernel/build64-default/tools/objtool/objtool.o
  CC      /workspace/kernel/build64-default/tools/objtool/orc_gen.o
  CC      /workspace/kernel/build64-default/tools/objtool/orc_dump.o
  CC      /workspace/kernel/build64-default/tools/objtool/libstring.o
  CC      /workspace/kernel/build64-default/tools/objtool/libctype.o
  CC      /workspace/kernel/build64-default/tools/objtool/str_error_r.o
  CC      /workspace/kernel/build64-default/tools/objtool/librbtree.o
  CC      /workspace/kernel/build64-default/tools/objtool/arch/x86/special.o
  CC      /workspace/kernel/build64-default/tools/objtool/arch/x86/decode.o
  CC      /workspace/kernel/build64-default/tools/objtool/arch/x86/orc.o
  LD      /workspace/kernel/build64-default/tools/objtool/arch/x86/objtool-in.o
  LD      /workspace/kernel/build64-default/tools/objtool/objtool-in.o
  LINK    /workspace/kernel/build64-default/tools/objtool/objtool
make[1]: Leaving directory '/workspace/kernel/build64-default'
++ nproc
+ make -j48 O=/workspace/kernel/build64-default M=drivers/gpu/drm/xe W=1
make[1]: Entering directory '/workspace/kernel/build64-default'
../scripts/Makefile.build:41: drivers/gpu/drm/xe/Makefile: No such file or directory
make[3]: *** No rule to make target 'drivers/gpu/drm/xe/Makefile'.  Stop.
make[2]: *** [/workspace/kernel/Makefile:1934: drivers/gpu/drm/xe] Error 2
make[1]: *** [/workspace/kernel/Makefile:240: __sub-make] Error 2
make[1]: Leaving directory '/workspace/kernel/build64-default'
make: *** [Makefile:240: __sub-make] Error 2
run-parts: /workspace/ci/hooks/10-build-W1 exited with return code 2

✓ CI.checksparse: success for VF: Setup VRAM based on received config data

[Patchwork]

== Series Details ==

Series: VF: Setup VRAM based on received config data
URL   : https://patchwork.freedesktop.org/series/134097/
State : success

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 0f0c00c367c8a8621a07443664d5f9a266889e84
Sparse version: 0.6.1 (Ubuntu: 0.6.1-2build1)
Fast mode used, each commit won't be checked separately.
Okay!

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.BAT: failure for VF: Setup VRAM based on received config data

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 7996 bytes --]

== Series Details ==

Series: VF: Setup VRAM based on received config data
URL   : https://patchwork.freedesktop.org/series/134097/
State : failure

== Summary ==

CI Bug Log - changes from xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84_BAT -> xe-pw-134097v1_BAT
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-134097v1_BAT absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-134097v1_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (5 -> 5)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-134097v1_BAT:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_live_ktest@xe_migrate:
    - bat-atsm-2:         NOTRUN -> [SKIP][1] +3 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/bat-atsm-2/igt@xe_live_ktest@xe_migrate.html

  * igt@xe_module_load@load:
    - bat-atsm-2:         [PASS][2] -> [FAIL][3]
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/bat-atsm-2/igt@xe_module_load@load.html
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/bat-atsm-2/igt@xe_module_load@load.html

  
#### Warnings ####

  * igt@kms_addfb_basic@invalid-set-prop-any:
    - bat-atsm-2:         [SKIP][4] ([i915#6077]) -> [SKIP][5] +30 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/bat-atsm-2/igt@kms_addfb_basic@invalid-set-prop-any.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/bat-atsm-2/igt@kms_addfb_basic@invalid-set-prop-any.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
    - bat-atsm-2:         [SKIP][6] ([Intel XE#1024] / [Intel XE#782]) -> [SKIP][7] +5 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/bat-atsm-2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/bat-atsm-2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html

  * igt@kms_dsc@dsc-basic:
    - bat-atsm-2:         [SKIP][8] ([Intel XE#1024] / [Intel XE#784]) -> [SKIP][9]
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/bat-atsm-2/igt@kms_dsc@dsc-basic.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/bat-atsm-2/igt@kms_dsc@dsc-basic.html

  * igt@kms_flip@basic-flip-vs-modeset:
    - bat-atsm-2:         [SKIP][10] ([Intel XE#1024] / [Intel XE#947]) -> [SKIP][11] +3 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/bat-atsm-2/igt@kms_flip@basic-flip-vs-modeset.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/bat-atsm-2/igt@kms_flip@basic-flip-vs-modeset.html

  * igt@kms_force_connector_basic@force-connector-state:
    - bat-atsm-2:         [SKIP][12] ([Intel XE#540]) -> [SKIP][13] +3 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/bat-atsm-2/igt@kms_force_connector_basic@force-connector-state.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/bat-atsm-2/igt@kms_force_connector_basic@force-connector-state.html

  * igt@kms_frontbuffer_tracking@basic:
    - bat-atsm-2:         [SKIP][14] ([Intel XE#1024] / [Intel XE#783]) -> [SKIP][15]
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/bat-atsm-2/igt@kms_frontbuffer_tracking@basic.html
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/bat-atsm-2/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_pipe_crc_basic@nonblocking-crc:
    - bat-atsm-2:         [SKIP][16] ([i915#1836]) -> [SKIP][17] +6 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/bat-atsm-2/igt@kms_pipe_crc_basic@nonblocking-crc.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/bat-atsm-2/igt@kms_pipe_crc_basic@nonblocking-crc.html

  * igt@kms_prop_blob@basic:
    - bat-atsm-2:         [SKIP][18] ([Intel XE#780]) -> [SKIP][19]
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/bat-atsm-2/igt@kms_prop_blob@basic.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/bat-atsm-2/igt@kms_prop_blob@basic.html

  * igt@kms_psr@psr-primary-page-flip:
    - bat-atsm-2:         [SKIP][20] ([Intel XE#1024]) -> [SKIP][21] +2 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/bat-atsm-2/igt@kms_psr@psr-primary-page-flip.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/bat-atsm-2/igt@kms_psr@psr-primary-page-flip.html

  
Known issues
------------

  Here are the changes found in xe-pw-134097v1_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_exec_compute_mode@twice-userptr-invalidate:
    - bat-atsm-2:         [PASS][22] -> [SKIP][23] ([Intel XE#1130]) +52 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/bat-atsm-2/igt@xe_exec_compute_mode@twice-userptr-invalidate.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/bat-atsm-2/igt@xe_exec_compute_mode@twice-userptr-invalidate.html

  * igt@xe_exec_fault_mode@twice-userptr-invalidate-imm:
    - bat-atsm-2:         NOTRUN -> [SKIP][24] ([Intel XE#1130]) +138 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/bat-atsm-2/igt@xe_exec_fault_mode@twice-userptr-invalidate-imm.html

  
#### Warnings ####

  * igt@xe_exec_compute_mode@twice-bindexecqueue:
    - bat-atsm-2:         [DMESG-WARN][25] -> [SKIP][26] ([Intel XE#1130])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/bat-atsm-2/igt@xe_exec_compute_mode@twice-bindexecqueue.html
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/bat-atsm-2/igt@xe_exec_compute_mode@twice-bindexecqueue.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1024]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1024
  [Intel XE#1130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1130
  [Intel XE#1908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1908
  [Intel XE#1939]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1939
  [Intel XE#540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/540
  [Intel XE#780]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/780
  [Intel XE#782]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/782
  [Intel XE#783]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/783
  [Intel XE#784]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/784
  [Intel XE#947]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/947
  [i915#1836]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1836
  [i915#6077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6077


Build changes
-------------

  * Linux: xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84 -> xe-pw-134097v1

  IGT_7871: 1d7b961235e345db20933c057f265898e2e96fd2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84: 0f0c00c367c8a8621a07443664d5f9a266889e84
  xe-pw-134097v1: 134097v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/index.html

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✗ CI.FULL: failure for VF: Setup VRAM based on received config data

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 37135 bytes --]

== Series Details ==

Series: VF: Setup VRAM based on received config data
URL   : https://patchwork.freedesktop.org/series/134097/
State : failure

== Summary ==

CI Bug Log - changes from xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84_full -> xe-pw-134097v1_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-134097v1_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-134097v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (3 -> 3)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-134097v1_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_sysfs_edid_timing:
    - shard-adlp:         NOTRUN -> [DMESG-FAIL][1]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-8/igt@kms_sysfs_edid_timing.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_psr@fbc-psr-suspend@edp-1:
    - {shard-lnl}:        NOTRUN -> [FAIL][2] +2 other tests fail
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-lnl-7/igt@kms_psr@fbc-psr-suspend@edp-1.html

  * igt@kms_vblank@ts-continuation-suspend:
    - {shard-lnl}:        NOTRUN -> [DMESG-FAIL][3] +1 other test dmesg-fail
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-lnl-7/igt@kms_vblank@ts-continuation-suspend.html

  * igt@xe_exec_basic@no-exec-basic-defer-bind:
    - {shard-lnl}:        NOTRUN -> [INCOMPLETE][4] +2 other tests incomplete
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-lnl-7/igt@xe_exec_basic@no-exec-basic-defer-bind.html

  * igt@xe_pm@d3cold-mmap-vram:
    - {shard-lnl}:        NOTRUN -> [SKIP][5]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-lnl-3/igt@xe_pm@d3cold-mmap-vram.html

  
Known issues
------------

  Here are the changes found in xe-pw-134097v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-x:
    - shard-adlp:         [PASS][6] -> [DMESG-WARN][7] ([Intel XE#1214] / [Intel XE#324])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-adlp-9/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-x.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-2/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-x.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-270:
    - shard-adlp:         NOTRUN -> [SKIP][8] ([Intel XE#1124] / [Intel XE#1201]) +13 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-addfb-size-overflow:
    - shard-adlp:         NOTRUN -> [SKIP][9] ([Intel XE#1201] / [Intel XE#610])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-1/igt@kms_big_fb@4-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-270:
    - shard-adlp:         NOTRUN -> [SKIP][10] ([Intel XE#1201] / [Intel XE#316]) +6 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-adlp:         NOTRUN -> [FAIL][11] ([Intel XE#1231])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-9/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_big_joiner@basic:
    - shard-adlp:         NOTRUN -> [SKIP][12] ([Intel XE#1201] / [Intel XE#346])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-8/igt@kms_big_joiner@basic.html

  * igt@kms_bw@linear-tiling-1-displays-1920x1080p:
    - shard-adlp:         NOTRUN -> [SKIP][13] ([Intel XE#1201] / [Intel XE#367]) +3 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-1/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][14] ([Intel XE#1201] / [Intel XE#787]) +68 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][15] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +45 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-xe2-ccs:
    - shard-adlp:         NOTRUN -> [SKIP][16] ([Intel XE#1201] / [Intel XE#1252])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-xe2-ccs.html

  * igt@kms_cdclk@mode-transition:
    - shard-adlp:         NOTRUN -> [SKIP][17] ([Intel XE#1201] / [Intel XE#314] / [Intel XE#455]) +1 other test skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_cdclk@mode-transition.html

  * igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][18] ([Intel XE#1201] / [Intel XE#314]) +2 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-1.html

  * igt@kms_chamelium_hpd@dp-hpd-storm:
    - shard-adlp:         NOTRUN -> [SKIP][19] ([Intel XE#1201] / [Intel XE#373]) +10 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-2/igt@kms_chamelium_hpd@dp-hpd-storm.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-adlp:         NOTRUN -> [SKIP][20] ([Intel XE#1201] / [Intel XE#307])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@uevent:
    - shard-adlp:         NOTRUN -> [SKIP][21] ([Intel XE#1201] / [Intel XE#455]) +39 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-1/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-adlp:         NOTRUN -> [SKIP][22] ([Intel XE#1201] / [Intel XE#308]) +2 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-9/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
    - shard-adlp:         NOTRUN -> [SKIP][23] ([Intel XE#1201] / [Intel XE#309]) +7 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-8/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-adlp:         NOTRUN -> [SKIP][24] ([Intel XE#1201] / [Intel XE#323]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_feature_discovery@display-4x:
    - shard-adlp:         NOTRUN -> [SKIP][25] ([Intel XE#1138] / [Intel XE#1201])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-8/igt@kms_feature_discovery@display-4x.html

  * igt@kms_flip@2x-blocking-wf_vblank:
    - shard-adlp:         NOTRUN -> [SKIP][26] ([Intel XE#1201] / [Intel XE#310]) +7 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-9/igt@kms_flip@2x-blocking-wf_vblank.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-adlp:         NOTRUN -> [DMESG-WARN][27] ([Intel XE#1191] / [Intel XE#1214] / [Intel XE#1608]) +1 other test dmesg-warn
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-adlp:         NOTRUN -> [INCOMPLETE][28] ([Intel XE#1195] / [Intel XE#927])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-9/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a1:
    - shard-adlp:         NOTRUN -> [INCOMPLETE][29] ([Intel XE#1195])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-9/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend@b-hdmi-a1:
    - shard-adlp:         NOTRUN -> [DMESG-WARN][30] ([Intel XE#1214] / [Intel XE#1608]) +3 other tests dmesg-warn
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling:
    - shard-adlp:         NOTRUN -> [DMESG-FAIL][31] ([Intel XE#324]) +1 other test dmesg-fail
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render:
    - shard-adlp:         NOTRUN -> [FAIL][32] ([Intel XE#1861])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-4:
    - shard-adlp:         NOTRUN -> [SKIP][33] ([Intel XE#1151] / [Intel XE#1201])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_frontbuffer_tracking@fbc-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-blt:
    - shard-adlp:         NOTRUN -> [SKIP][34] ([Intel XE#1201] / [Intel XE#651]) +28 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-9/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-blt.html

  * igt@kms_frontbuffer_tracking@plane-fbc-rte:
    - shard-adlp:         NOTRUN -> [SKIP][35] ([Intel XE#1158] / [Intel XE#1201])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_frontbuffer_tracking@plane-fbc-rte.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt:
    - shard-adlp:         NOTRUN -> [SKIP][36] ([Intel XE#1201] / [Intel XE#653]) +24 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-pri-indfb-multidraw:
    - shard-adlp:         NOTRUN -> [ABORT][37] ([Intel XE#1939]) +1 other test abort
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-8/igt@kms_frontbuffer_tracking@psr-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-render:
    - shard-adlp:         NOTRUN -> [SKIP][38] ([Intel XE#1201] / [Intel XE#656]) +65 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_getfb@getfb-reject-ccs:
    - shard-adlp:         NOTRUN -> [SKIP][39] ([Intel XE#1201] / [Intel XE#1341])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-1/igt@kms_getfb@getfb-reject-ccs.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-adlp:         NOTRUN -> [SKIP][40] ([Intel XE#1201] / [Intel XE#417])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-2/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_plane@pixel-format@pipe-b:
    - shard-adlp:         NOTRUN -> [FAIL][41] ([Intel XE#1331]) +2 other tests fail
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-1/igt@kms_plane@pixel-format@pipe-b.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [FAIL][42] ([Intel XE#361]) +1 other test fail
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][43] ([Intel XE#1201] / [Intel XE#498]) +2 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-d-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][44] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#498]) +1 other test skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-d-hdmi-a-1.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][45] ([Intel XE#1201] / [Intel XE#305]) +14 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25:
    - shard-adlp:         NOTRUN -> [SKIP][46] ([Intel XE#1201] / [Intel XE#305] / [Intel XE#455]) +9 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-adlp:         NOTRUN -> [SKIP][47] ([Intel XE#1201] / [Intel XE#734])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-9/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-adlp:         NOTRUN -> [SKIP][48] ([Intel XE#1201] / [Intel XE#836]) +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-1/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_psr2_sf@fbc-overlay-plane-move-continuous-sf:
    - shard-adlp:         NOTRUN -> [SKIP][49] ([Intel XE#1201]) +5 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_psr2_sf@fbc-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-adlp:         NOTRUN -> [SKIP][50] ([Intel XE#1122] / [Intel XE#1201]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-1/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@fbc-pr-sprite-plane-onoff:
    - shard-adlp:         NOTRUN -> [SKIP][51] ([Intel XE#1201] / [Intel XE#929]) +24 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-9/igt@kms_psr@fbc-pr-sprite-plane-onoff.html

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-adlp:         NOTRUN -> [FAIL][52] ([Intel XE#1874]) +4 other tests fail
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-8/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html

  * igt@kms_rotation_crc@sprite-rotation-90:
    - shard-adlp:         NOTRUN -> [SKIP][53] ([Intel XE#1201] / [Intel XE#327]) +2 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_rotation_crc@sprite-rotation-90.html

  * igt@kms_vblank@wait-idle-hang:
    - shard-adlp:         [PASS][54] -> [ABORT][55] ([Intel XE#1939]) +1 other test abort
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-adlp-6/igt@kms_vblank@wait-idle-hang.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-2/igt@kms_vblank@wait-idle-hang.html

  * igt@kms_writeback@writeback-check-output:
    - shard-adlp:         NOTRUN -> [SKIP][56] ([Intel XE#1201] / [Intel XE#756]) +1 other test skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-9/igt@kms_writeback@writeback-check-output.html

  * igt@xe_ccs@block-copy-compressed:
    - shard-adlp:         NOTRUN -> [SKIP][57] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#488]) +3 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-2/igt@xe_ccs@block-copy-compressed.html

  * igt@xe_compute@ccs-mode-compute-kernel:
    - shard-adlp:         NOTRUN -> [SKIP][58] ([Intel XE#1201] / [Intel XE#1447]) +1 other test skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-9/igt@xe_compute@ccs-mode-compute-kernel.html

  * igt@xe_evict@evict-small-external-cm:
    - shard-adlp:         NOTRUN -> [SKIP][59] ([Intel XE#1201] / [Intel XE#261] / [Intel XE#688]) +8 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@xe_evict@evict-small-external-cm.html

  * igt@xe_evict@evict-threads-large:
    - shard-adlp:         NOTRUN -> [SKIP][60] ([Intel XE#1201] / [Intel XE#261]) +5 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@xe_evict@evict-threads-large.html

  * igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-samefd:
    - shard-adlp:         NOTRUN -> [SKIP][61] ([Intel XE#1201] / [Intel XE#688]) +1 other test skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-9/igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-samefd.html

  * igt@xe_exec_basic@multigpu-no-exec-null-defer-bind:
    - shard-adlp:         NOTRUN -> [SKIP][62] ([Intel XE#1201] / [Intel XE#1392]) +14 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-9/igt@xe_exec_basic@multigpu-no-exec-null-defer-bind.html

  * igt@xe_exec_fault_mode@once-userptr-imm:
    - shard-adlp:         NOTRUN -> [SKIP][63] ([Intel XE#1201] / [Intel XE#288]) +42 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-1/igt@xe_exec_fault_mode@once-userptr-imm.html

  * igt@xe_exec_threads@threads-bal-mixed-userptr-rebind:
    - shard-adlp:         [PASS][64] -> [FAIL][65] ([Intel XE#1069])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-adlp-2/igt@xe_exec_threads@threads-bal-mixed-userptr-rebind.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-8/igt@xe_exec_threads@threads-bal-mixed-userptr-rebind.html

  * igt@xe_mmap@small-bar:
    - shard-adlp:         NOTRUN -> [SKIP][66] ([Intel XE#1201] / [Intel XE#512])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-8/igt@xe_mmap@small-bar.html

  * igt@xe_mmap@vram:
    - shard-adlp:         NOTRUN -> [SKIP][67] ([Intel XE#1008] / [Intel XE#1201])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@xe_mmap@vram.html

  * igt@xe_module_load@load:
    - shard-adlp:         NOTRUN -> [SKIP][68] ([Intel XE#1201] / [Intel XE#378])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@xe_module_load@load.html

  * igt@xe_module_load@reload-no-display:
    - shard-adlp:         [PASS][69] -> [ABORT][70] ([Intel XE#1205] / [Intel XE#1939])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-adlp-1/igt@xe_module_load@reload-no-display.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-8/igt@xe_module_load@reload-no-display.html

  * igt@xe_pm@d3cold-multiple-execs:
    - shard-adlp:         NOTRUN -> [SKIP][71] ([Intel XE#1201] / [Intel XE#366]) +1 other test skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@xe_pm@d3cold-multiple-execs.html

  * igt@xe_pm@s2idle-vm-bind-userptr:
    - shard-adlp:         NOTRUN -> [INCOMPLETE][72] ([Intel XE#1195] / [Intel XE#1694])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-1/igt@xe_pm@s2idle-vm-bind-userptr.html

  * igt@xe_pm@s4-vm-bind-prefetch:
    - shard-adlp:         [PASS][73] -> [DMESG-WARN][74] ([Intel XE#1214])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-adlp-1/igt@xe_pm@s4-vm-bind-prefetch.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-8/igt@xe_pm@s4-vm-bind-prefetch.html

  * igt@xe_pm@vram-d3cold-threshold:
    - shard-adlp:         NOTRUN -> [SKIP][75] ([Intel XE#1201] / [Intel XE#579])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@xe_pm@vram-d3cold-threshold.html

  * igt@xe_query@multigpu-query-topology-l3-bank-mask:
    - shard-adlp:         NOTRUN -> [SKIP][76] ([Intel XE#1201] / [Intel XE#944]) +2 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@xe_query@multigpu-query-topology-l3-bank-mask.html

  
#### Possible fixes ####

  * igt@kms_big_fb@4-tiled-64bpp-rotate-180:
    - {shard-lnl}:        [FAIL][77] ([Intel XE#1659]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-lnl-5/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-lnl-7/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - {shard-lnl}:        [DMESG-WARN][79] ([Intel XE#1830]) -> [PASS][80] +1 other test pass
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-lnl-6/igt@kms_fbcon_fbt@psr-suspend.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-lnl-6/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank:
    - {shard-lnl}:        [FAIL][81] ([Intel XE#480] / [Intel XE#886]) -> [PASS][82] +1 other test pass
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-lnl-2/igt@kms_flip@flip-vs-absolute-wf_vblank.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-lnl-2/igt@kms_flip@flip-vs-absolute-wf_vblank.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-1:
    - shard-adlp:         [DMESG-WARN][83] ([Intel XE#1191] / [Intel XE#1214]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-adlp-6/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-1.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-2/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-1.html

  * igt@xe_ccs@ctrl-surf-copy-new-ctx:
    - {shard-lnl}:        [INCOMPLETE][85] ([Intel XE#1330]) -> [PASS][86] +1 other test pass
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-lnl-8/igt@xe_ccs@ctrl-surf-copy-new-ctx.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-lnl-3/igt@xe_ccs@ctrl-surf-copy-new-ctx.html

  * igt@xe_exec_basic@many-execqueues-many-vm-basic:
    - {shard-lnl}:        [ABORT][87] ([Intel XE#1939]) -> [PASS][88] +2 other tests pass
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-lnl-1/igt@xe_exec_basic@many-execqueues-many-vm-basic.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-lnl-7/igt@xe_exec_basic@many-execqueues-many-vm-basic.html

  * igt@xe_exec_compute_mode@many-userptr-invalidate:
    - {shard-lnl}:        [FAIL][89] ([Intel XE#1069]) -> [PASS][90]
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-lnl-3/igt@xe_exec_compute_mode@many-userptr-invalidate.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-lnl-8/igt@xe_exec_compute_mode@many-userptr-invalidate.html

  * igt@xe_gt_freq@freq_fixed_exec:
    - {shard-lnl}:        [DMESG-WARN][91] -> [PASS][92]
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-lnl-3/igt@xe_gt_freq@freq_fixed_exec.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-lnl-2/igt@xe_gt_freq@freq_fixed_exec.html

  * igt@xe_gt_freq@freq_low_max:
    - {shard-lnl}:        [FAIL][93] ([Intel XE#1045]) -> [PASS][94]
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-lnl-5/igt@xe_gt_freq@freq_low_max.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-lnl-6/igt@xe_gt_freq@freq_low_max.html

  
#### Warnings ####

  * igt@kms_async_flips@async-flip-with-page-flip-events:
    - shard-adlp:         [DMESG-WARN][95] ([Intel XE#1033] / [Intel XE#1214]) -> [DMESG-WARN][96] ([Intel XE#1033] / [Intel XE#1214] / [Intel XE#324])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-adlp-9/igt@kms_async_flips@async-flip-with-page-flip-events.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-2/igt@kms_async_flips@async-flip-with-page-flip-events.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-adlp:         [DMESG-FAIL][97] ([Intel XE#324]) -> [FAIL][98] ([Intel XE#1231]) +1 other test fail
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-adlp-2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-adlp:         [FAIL][99] ([Intel XE#1231]) -> [DMESG-FAIL][100] ([Intel XE#324])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-adlp-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_cursor_crc@cursor-suspend:
    - shard-adlp:         [INCOMPLETE][101] ([Intel XE#1195] / [Intel XE#927]) -> [DMESG-WARN][102] ([Intel XE#1191] / [Intel XE#1214] / [Intel XE#1608])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-adlp-1/igt@kms_cursor_crc@cursor-suspend.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_cursor_crc@cursor-suspend.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1:
    - shard-adlp:         [INCOMPLETE][103] ([Intel XE#1195]) -> [DMESG-WARN][104] ([Intel XE#1191] / [Intel XE#1214] / [Intel XE#1608])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-adlp-1/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1.html

  * igt@xe_pm@s2idle-basic-exec:
    - shard-adlp:         [DMESG-WARN][105] ([Intel XE#1191] / [Intel XE#1214] / [Intel XE#1608]) -> [INCOMPLETE][106] ([Intel XE#1195] / [Intel XE#1358] / [Intel XE#927])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-adlp-2/igt@xe_pm@s2idle-basic-exec.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-1/igt@xe_pm@s2idle-basic-exec.html

  * igt@xe_pm@s2idle-mocs:
    - shard-adlp:         [INCOMPLETE][107] ([Intel XE#1195]) -> [DMESG-WARN][108] ([Intel XE#1214])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-adlp-1/igt@xe_pm@s2idle-mocs.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-6/igt@xe_pm@s2idle-mocs.html

  * igt@xe_pm@s2idle-vm-bind-prefetch:
    - shard-adlp:         [INCOMPLETE][109] ([Intel XE#1195] / [Intel XE#1694]) -> [DMESG-WARN][110] ([Intel XE#1214] / [Intel XE#1608])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-adlp-1/igt@xe_pm@s2idle-vm-bind-prefetch.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-8/igt@xe_pm@s2idle-vm-bind-prefetch.html

  * igt@xe_pm@s4-vm-bind-unbind-all:
    - shard-adlp:         [DMESG-WARN][111] ([Intel XE#1214]) -> [INCOMPLETE][112] ([Intel XE#1195])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-adlp-6/igt@xe_pm@s4-vm-bind-unbind-all.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-9/igt@xe_pm@s4-vm-bind-unbind-all.html

  * igt@xe_pm@s4-vm-bind-userptr:
    - shard-adlp:         [ABORT][113] ([Intel XE#1794]) -> [DMESG-WARN][114] ([Intel XE#1214])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84/shard-adlp-9/igt@xe_pm@s4-vm-bind-userptr.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/shard-adlp-2/igt@xe_pm@s4-vm-bind-userptr.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1008]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1008
  [Intel XE#1033]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1033
  [Intel XE#1045]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1045
  [Intel XE#1069]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1069
  [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1125]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1125
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
  [Intel XE#1151]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1151
  [Intel XE#1158]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1158
  [Intel XE#1191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1191
  [Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195
  [Intel XE#1201]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1201
  [Intel XE#1205]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1205
  [Intel XE#1214]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1214
  [Intel XE#1231]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1231
  [Intel XE#1252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1252
  [Intel XE#1330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1330
  [Intel XE#1331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1331
  [Intel XE#1341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1341
  [Intel XE#1358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1358
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1399
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1428
  [Intel XE#1437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1437
  [Intel XE#1446]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1446
  [Intel XE#1447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1447
  [Intel XE#1494]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1494
  [Intel XE#1512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1512
  [Intel XE#1608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1608
  [Intel XE#1659]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1659
  [Intel XE#1694]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1694
  [Intel XE#1725]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1725
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#1760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1760
  [Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
  [Intel XE#1830]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1830
  [Intel XE#1861]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1861
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#1939]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1939
  [Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#305]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/305
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/314
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#324]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/324
  [Intel XE#327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/327
  [Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
  [Intel XE#352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/352
  [Intel XE#361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/361
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/417
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#480]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/480
  [Intel XE#488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/488
  [Intel XE#498]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/498
  [Intel XE#512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/512
  [Intel XE#579]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/579
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/599
  [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#702]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/702
  [Intel XE#734]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/734
  [Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
  [Intel XE#927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/927
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977


Build changes
-------------

  * Linux: xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84 -> xe-pw-134097v1

  IGT_7871: 1d7b961235e345db20933c057f265898e2e96fd2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-1351-0f0c00c367c8a8621a07443664d5f9a266889e84: 0f0c00c367c8a8621a07443664d5f9a266889e84
  xe-pw-134097v1: 134097v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-134097v1/index.html

[-- Attachment #2: Type: text/html, Size: 45221 bytes --]

Re: [PATCH 1/5] drm/xe: Move XEHP_MTCFG_ADDR register definition to xe_regs.h

[Matt Roper]

On Mon, May 27, 2024 at 07:35:50PM +0200, Michal Wajdeczko wrote:
> We should not define registers directly in the code while we have
> dedicated files for all register definitions. Move XEHP_MTCFG_ADDR
> to regs/xe_regs.h
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/xe/regs/xe_regs.h | 3 +++
>  drivers/gpu/drm/xe/xe_mmio.c      | 3 ---
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
> index 722fb6dbb72e..23e33ec84902 100644
> --- a/drivers/gpu/drm/xe/regs/xe_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_regs.h
> @@ -30,6 +30,9 @@
>  #define XEHP_CLOCK_GATE_DIS			XE_REG(0x101014)
>  #define   SGSI_SIDECLK_DIS			REG_BIT(17)
>  
> +#define XEHP_MTCFG_ADDR				XE_REG(0x101800)
> +#define   TILE_COUNT				REG_GENMASK(15, 8)
> +
>  #define GGC					XE_REG(0x108040)
>  #define   GMS_MASK				REG_GENMASK(15, 8)
>  #define   GGMS_MASK				REG_GENMASK(7, 6)
> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> index 248e93ec6df7..44bff104c011 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.c
> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> @@ -28,9 +28,6 @@
>  #include "xe_sriov.h"
>  #include "xe_tile.h"
>  
> -#define XEHP_MTCFG_ADDR		XE_REG(0x101800)
> -#define TILE_COUNT		REG_GENMASK(15, 8)
> -
>  #define BAR_SIZE_SHIFT 20
>  
>  static void
> -- 
> 2.43.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 2/5] drm/xe: Move BAR definitions to dedicated file

[Matt Roper]

On Mon, May 27, 2024 at 07:35:51PM +0200, Michal Wajdeczko wrote:
> We should keep all hardware definitions separated from the driver
> code. Move LMEM_BAR definition to new regs/xe_bars.h file and also
> add there GTTMMADR_BAR definition to avoid using magic 0 resource.
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_bars.h      | 11 +++++++++++
>  drivers/gpu/drm/xe/xe_mmio.c           |  3 ++-
>  drivers/gpu/drm/xe/xe_mmio.h           |  2 --
>  drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c |  1 +
>  4 files changed, 14 insertions(+), 3 deletions(-)
>  create mode 100644 drivers/gpu/drm/xe/regs/xe_bars.h
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_bars.h b/drivers/gpu/drm/xe/regs/xe_bars.h
> new file mode 100644
> index 000000000000..ce05b6ae832f
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/regs/xe_bars.h

It seems like we're starting to put stuff in this folder that isn't
technically (or exclusively) "regs" anymore.  We might want to rename or
reorganize the folder at some point down the road.  Anyway, this seems
fine for the time being.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>


Matt

> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
> +#ifndef _XE_BARS_H_
> +#define _XE_BARS_H_
> +
> +#define GTTMMADR_BAR			0 /* MMIO + GTT */
> +#define LMEM_BAR			2 /* VRAM */
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> index 44bff104c011..1272246dd8a3 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.c
> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> @@ -12,6 +12,7 @@
>  #include <drm/drm_managed.h>
>  #include <drm/xe_drm.h>
>  
> +#include "regs/xe_bars.h"
>  #include "regs/xe_engine_regs.h"
>  #include "regs/xe_gt_regs.h"
>  #include "regs/xe_regs.h"
> @@ -435,7 +436,7 @@ int xe_mmio_init(struct xe_device *xe)
>  	 * registers (0-4MB), reserved space (4MB-8MB) and GGTT (8MB-16MB).
>  	 */
>  	xe->mmio.size = pci_resource_len(pdev, mmio_bar);
> -	xe->mmio.regs = pci_iomap(pdev, mmio_bar, 0);
> +	xe->mmio.regs = pci_iomap(pdev, mmio_bar, GTTMMADR_BAR);
>  	if (xe->mmio.regs == NULL) {
>  		drm_err(&xe->drm, "failed to map registers\n");
>  		return -EIO;
> diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
> index 1d578fd6ffc2..6ae0cc32c651 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.h
> +++ b/drivers/gpu/drm/xe/xe_mmio.h
> @@ -11,8 +11,6 @@
>  struct xe_device;
>  struct xe_reg;
>  
> -#define LMEM_BAR		2
> -
>  int xe_mmio_init(struct xe_device *xe);
>  int xe_mmio_probe_tiles(struct xe_device *xe);
>  
> diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
> index 64592a8e527b..f46fd2df84de 100644
> --- a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
> +++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
> @@ -13,6 +13,7 @@
>  
>  #include <generated/xe_wa_oob.h>
>  
> +#include "regs/xe_bars.h"
>  #include "regs/xe_gt_regs.h"
>  #include "regs/xe_regs.h"
>  #include "xe_bo.h"
> -- 
> 2.43.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 3/5] drm/xe: Promote VRAM initialization function to own file

[Matt Roper]

On Mon, May 27, 2024 at 07:35:52PM +0200, Michal Wajdeczko wrote:
> There is no point in mixing MMIO and VRAM code in the same file.

I'd say s/MMIO/register access/ since the VRAM BAR is technically
memory-mapped IO.  It's just that when we usually talk about "mmio" in
the driver we're more focused on register IO.

Separating this out still makes sense regardless.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

As a side note, I notice that there are a bunch of static VRAM functions
that have an "xe_" prefix.  You rename one of them in the next series of
the patch, but we should probably rename the others somewhere in this
series as well to align with our typical coding style.


Matt

> Move and rename the VRAM probe function to a new file (there are
> no other changes other then simple kernel-doc).
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/xe/Makefile    |   1 +
>  drivers/gpu/drm/xe/xe_device.c |   3 +-
>  drivers/gpu/drm/xe/xe_mmio.c   | 333 +------------------------------
>  drivers/gpu/drm/xe/xe_vram.c   | 350 +++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_vram.h   |  13 ++
>  5 files changed, 368 insertions(+), 332 deletions(-)
>  create mode 100644 drivers/gpu/drm/xe/xe_vram.c
>  create mode 100644 drivers/gpu/drm/xe/xe_vram.h
> 
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index d5b137e762ed..74bd64d9e8ab 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -143,6 +143,7 @@ xe-y += xe_bb.o \
>  	xe_uc_debugfs.o \
>  	xe_uc_fw.o \
>  	xe_vm.o \
> +	xe_vram.o \
>  	xe_vram_freq.o \
>  	xe_wait_user_fence.o \
>  	xe_wa.o \
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index f04b11e45c2d..61ec15f2034b 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -51,6 +51,7 @@
>  #include "xe_ttm_stolen_mgr.h"
>  #include "xe_ttm_sys_mgr.h"
>  #include "xe_vm.h"
> +#include "xe_vram.h"
>  #include "xe_wait_user_fence.h"
>  
>  static int xe_file_open(struct drm_device *dev, struct drm_file *file)
> @@ -615,7 +616,7 @@ int xe_device_probe(struct xe_device *xe)
>  	if (err)
>  		goto err_irq_shutdown;
>  
> -	err = xe_mmio_probe_vram(xe);
> +	err = xe_vram_probe(xe);
>  	if (err)
>  		goto err_irq_shutdown;
>  
> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> index 1272246dd8a3..7962eeb9adb7 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.c
> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> @@ -8,348 +8,19 @@
>  #include <linux/delay.h>
>  #include <linux/io-64-nonatomic-lo-hi.h>
>  #include <linux/minmax.h>
> +#include <linux/pci.h>
>  
>  #include <drm/drm_managed.h>
> -#include <drm/xe_drm.h>
> +#include <drm/drm_print.h>
>  
>  #include "regs/xe_bars.h"
> -#include "regs/xe_engine_regs.h"
> -#include "regs/xe_gt_regs.h"
>  #include "regs/xe_regs.h"
> -#include "xe_bo.h"
>  #include "xe_device.h"
> -#include "xe_force_wake.h"
> -#include "xe_ggtt.h"
>  #include "xe_gt.h"
> -#include "xe_gt_mcr.h"
>  #include "xe_gt_printk.h"
>  #include "xe_gt_sriov_vf.h"
>  #include "xe_macros.h"
> -#include "xe_module.h"
>  #include "xe_sriov.h"
> -#include "xe_tile.h"
> -
> -#define BAR_SIZE_SHIFT 20
> -
> -static void
> -_resize_bar(struct xe_device *xe, int resno, resource_size_t size)
> -{
> -	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> -	int bar_size = pci_rebar_bytes_to_size(size);
> -	int ret;
> -
> -	if (pci_resource_len(pdev, resno))
> -		pci_release_resource(pdev, resno);
> -
> -	ret = pci_resize_resource(pdev, resno, bar_size);
> -	if (ret) {
> -		drm_info(&xe->drm, "Failed to resize BAR%d to %dM (%pe). Consider enabling 'Resizable BAR' support in your BIOS\n",
> -			 resno, 1 << bar_size, ERR_PTR(ret));
> -		return;
> -	}
> -
> -	drm_info(&xe->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
> -}
> -
> -/*
> - * if force_vram_bar_size is set, attempt to set to the requested size
> - * else set to maximum possible size
> - */
> -static void xe_resize_vram_bar(struct xe_device *xe)
> -{
> -	u64 force_vram_bar_size = xe_modparam.force_vram_bar_size;
> -	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> -	struct pci_bus *root = pdev->bus;
> -	resource_size_t current_size;
> -	resource_size_t rebar_size;
> -	struct resource *root_res;
> -	u32 bar_size_mask;
> -	u32 pci_cmd;
> -	int i;
> -
> -	/* gather some relevant info */
> -	current_size = pci_resource_len(pdev, LMEM_BAR);
> -	bar_size_mask = pci_rebar_get_possible_sizes(pdev, LMEM_BAR);
> -
> -	if (!bar_size_mask)
> -		return;
> -
> -	/* set to a specific size? */
> -	if (force_vram_bar_size) {
> -		u32 bar_size_bit;
> -
> -		rebar_size = force_vram_bar_size * (resource_size_t)SZ_1M;
> -
> -		bar_size_bit = bar_size_mask & BIT(pci_rebar_bytes_to_size(rebar_size));
> -
> -		if (!bar_size_bit) {
> -			drm_info(&xe->drm,
> -				 "Requested size: %lluMiB is not supported by rebar sizes: 0x%x. Leaving default: %lluMiB\n",
> -				 (u64)rebar_size >> 20, bar_size_mask, (u64)current_size >> 20);
> -			return;
> -		}
> -
> -		rebar_size = 1ULL << (__fls(bar_size_bit) + BAR_SIZE_SHIFT);
> -
> -		if (rebar_size == current_size)
> -			return;
> -	} else {
> -		rebar_size = 1ULL << (__fls(bar_size_mask) + BAR_SIZE_SHIFT);
> -
> -		/* only resize if larger than current */
> -		if (rebar_size <= current_size)
> -			return;
> -	}
> -
> -	drm_info(&xe->drm, "Attempting to resize bar from %lluMiB -> %lluMiB\n",
> -		 (u64)current_size >> 20, (u64)rebar_size >> 20);
> -
> -	while (root->parent)
> -		root = root->parent;
> -
> -	pci_bus_for_each_resource(root, root_res, i) {
> -		if (root_res && root_res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
> -		    (u64)root_res->start > 0x100000000ul)
> -			break;
> -	}
> -
> -	if (!root_res) {
> -		drm_info(&xe->drm, "Can't resize VRAM BAR - platform support is missing. Consider enabling 'Resizable BAR' support in your BIOS\n");
> -		return;
> -	}
> -
> -	pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
> -	pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd & ~PCI_COMMAND_MEMORY);
> -
> -	_resize_bar(xe, LMEM_BAR, rebar_size);
> -
> -	pci_assign_unassigned_bus_resources(pdev->bus);
> -	pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
> -}
> -
> -static bool xe_pci_resource_valid(struct pci_dev *pdev, int bar)
> -{
> -	if (!pci_resource_flags(pdev, bar))
> -		return false;
> -
> -	if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET)
> -		return false;
> -
> -	if (!pci_resource_len(pdev, bar))
> -		return false;
> -
> -	return true;
> -}
> -
> -static int xe_determine_lmem_bar_size(struct xe_device *xe)
> -{
> -	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> -
> -	if (!xe_pci_resource_valid(pdev, LMEM_BAR)) {
> -		drm_err(&xe->drm, "pci resource is not valid\n");
> -		return -ENXIO;
> -	}
> -
> -	xe_resize_vram_bar(xe);
> -
> -	xe->mem.vram.io_start = pci_resource_start(pdev, LMEM_BAR);
> -	xe->mem.vram.io_size = pci_resource_len(pdev, LMEM_BAR);
> -	if (!xe->mem.vram.io_size)
> -		return -EIO;
> -
> -	/* XXX: Need to change when xe link code is ready */
> -	xe->mem.vram.dpa_base = 0;
> -
> -	/* set up a map to the total memory area. */
> -	xe->mem.vram.mapping = ioremap_wc(xe->mem.vram.io_start, xe->mem.vram.io_size);
> -
> -	return 0;
> -}
> -
> -static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
> -{
> -	struct xe_device *xe = gt_to_xe(gt);
> -	u64 offset;
> -	u32 reg;
> -
> -	if (GRAPHICS_VER(xe) >= 20) {
> -		u64 ccs_size = tile_size / 512;
> -		u64 offset_hi, offset_lo;
> -		u32 nodes, num_enabled;
> -
> -		reg = xe_mmio_read32(gt, MIRROR_FUSE3);
> -		nodes = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, reg);
> -		num_enabled = hweight32(nodes); /* Number of enabled l3 nodes */
> -
> -		reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_LOWER);
> -		offset_lo = REG_FIELD_GET(XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK, reg);
> -
> -		reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_UPPER);
> -		offset_hi = REG_FIELD_GET(XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK, reg);
> -
> -		offset = offset_hi << 32; /* HW view bits 39:32 */
> -		offset |= offset_lo << 6; /* HW view bits 31:6 */
> -		offset *= num_enabled; /* convert to SW view */
> -
> -		/* We don't expect any holes */
> -		xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(gt, GSMBASE) - ccs_size),
> -			      "Hole between CCS and GSM.\n");
> -	} else {
> -		reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
> -		offset = (u64)REG_FIELD_GET(XEHP_FLAT_CCS_PTR, reg) * SZ_64K;
> -	}
> -
> -	return offset;
> -}
> -
> -/**
> - * xe_mmio_tile_vram_size() - Collect vram size and offset information
> - * @tile: tile to get info for
> - * @vram_size: available vram (size - device reserved portions)
> - * @tile_size: actual vram size
> - * @tile_offset: physical start point in the vram address space
> - *
> - * There are 4 places for size information:
> - * - io size (from pci_resource_len of LMEM bar) (only used for small bar and DG1)
> - * - TILEx size (actual vram size)
> - * - GSMBASE offset (TILEx - "stolen")
> - * - CSSBASE offset (TILEx - CSS space necessary)
> - *
> - * CSSBASE is always a lower/smaller offset then GSMBASE.
> - *
> - * The actual available size of memory is to the CCS or GSM base.
> - * NOTE: multi-tile bases will include the tile offset.
> - *
> - */
> -static int xe_mmio_tile_vram_size(struct xe_tile *tile, u64 *vram_size,
> -				  u64 *tile_size, u64 *tile_offset)
> -{
> -	struct xe_device *xe = tile_to_xe(tile);
> -	struct xe_gt *gt = tile->primary_gt;
> -	u64 offset;
> -	int err;
> -	u32 reg;
> -
> -	err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
> -	if (err)
> -		return err;
> -
> -	/* actual size */
> -	if (unlikely(xe->info.platform == XE_DG1)) {
> -		*tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), LMEM_BAR);
> -		*tile_offset = 0;
> -	} else {
> -		reg = xe_gt_mcr_unicast_read_any(gt, XEHP_TILE_ADDR_RANGE(gt->info.id));
> -		*tile_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G;
> -		*tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G;
> -	}
> -
> -	/* minus device usage */
> -	if (xe->info.has_flat_ccs) {
> -		offset = get_flat_ccs_offset(gt, *tile_size);
> -	} else {
> -		offset = xe_mmio_read64_2x32(gt, GSMBASE);
> -	}
> -
> -	/* remove the tile offset so we have just the available size */
> -	*vram_size = offset - *tile_offset;
> -
> -	return xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
> -}
> -
> -static void vram_fini(void *arg)
> -{
> -	struct xe_device *xe = arg;
> -	struct xe_tile *tile;
> -	int id;
> -
> -	if (xe->mem.vram.mapping)
> -		iounmap(xe->mem.vram.mapping);
> -
> -	xe->mem.vram.mapping = NULL;
> -
> -	for_each_tile(tile, xe, id)
> -		tile->mem.vram.mapping = NULL;
> -}
> -
> -int xe_mmio_probe_vram(struct xe_device *xe)
> -{
> -	struct xe_tile *tile;
> -	resource_size_t io_size;
> -	u64 available_size = 0;
> -	u64 total_size = 0;
> -	u64 tile_offset;
> -	u64 tile_size;
> -	u64 vram_size;
> -	int err;
> -	u8 id;
> -
> -	if (!IS_DGFX(xe))
> -		return 0;
> -
> -	/* Get the size of the root tile's vram for later accessibility comparison */
> -	tile = xe_device_get_root_tile(xe);
> -	err = xe_mmio_tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
> -	if (err)
> -		return err;
> -
> -	err = xe_determine_lmem_bar_size(xe);
> -	if (err)
> -		return err;
> -
> -	drm_info(&xe->drm, "VISIBLE VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
> -		 &xe->mem.vram.io_size);
> -
> -	io_size = xe->mem.vram.io_size;
> -
> -	/* tile specific ranges */
> -	for_each_tile(tile, xe, id) {
> -		err = xe_mmio_tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
> -		if (err)
> -			return err;
> -
> -		tile->mem.vram.actual_physical_size = tile_size;
> -		tile->mem.vram.io_start = xe->mem.vram.io_start + tile_offset;
> -		tile->mem.vram.io_size = min_t(u64, vram_size, io_size);
> -
> -		if (!tile->mem.vram.io_size) {
> -			drm_err(&xe->drm, "Tile without any CPU visible VRAM. Aborting.\n");
> -			return -ENODEV;
> -		}
> -
> -		tile->mem.vram.dpa_base = xe->mem.vram.dpa_base + tile_offset;
> -		tile->mem.vram.usable_size = vram_size;
> -		tile->mem.vram.mapping = xe->mem.vram.mapping + tile_offset;
> -
> -		if (tile->mem.vram.io_size < tile->mem.vram.usable_size)
> -			drm_info(&xe->drm, "Small BAR device\n");
> -		drm_info(&xe->drm, "VRAM[%u, %u]: Actual physical size %pa, usable size exclude stolen %pa, CPU accessible size %pa\n", id,
> -			 tile->id, &tile->mem.vram.actual_physical_size, &tile->mem.vram.usable_size, &tile->mem.vram.io_size);
> -		drm_info(&xe->drm, "VRAM[%u, %u]: DPA range: [%pa-%llx], io range: [%pa-%llx]\n", id, tile->id,
> -			 &tile->mem.vram.dpa_base, tile->mem.vram.dpa_base + (u64)tile->mem.vram.actual_physical_size,
> -			 &tile->mem.vram.io_start, tile->mem.vram.io_start + (u64)tile->mem.vram.io_size);
> -
> -		/* calculate total size using tile size to get the correct HW sizing */
> -		total_size += tile_size;
> -		available_size += vram_size;
> -
> -		if (total_size > xe->mem.vram.io_size) {
> -			drm_info(&xe->drm, "VRAM: %pa is larger than resource %pa\n",
> -				 &total_size, &xe->mem.vram.io_size);
> -		}
> -
> -		io_size -= min_t(u64, tile_size, io_size);
> -	}
> -
> -	xe->mem.vram.actual_physical_size = total_size;
> -
> -	drm_info(&xe->drm, "Total VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
> -		 &xe->mem.vram.actual_physical_size);
> -	drm_info(&xe->drm, "Available VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
> -		 &available_size);
> -
> -	return devm_add_action_or_reset(xe->drm.dev, vram_fini, xe);
> -}
>  
>  static void tiles_fini(void *arg)
>  {
> diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
> new file mode 100644
> index 000000000000..d8b81e4e050c
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_vram.c
> @@ -0,0 +1,350 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2021-2024 Intel Corporation
> + */
> +
> +#include <linux/pci.h>
> +
> +#include <drm/drm_managed.h>
> +#include <drm/drm_print.h>
> +
> +#include "regs/xe_bars.h"
> +#include "regs/xe_gt_regs.h"
> +#include "regs/xe_regs.h"
> +#include "xe_assert.h"
> +#include "xe_device.h"
> +#include "xe_force_wake.h"
> +#include "xe_gt_mcr.h"
> +#include "xe_mmio.h"
> +#include "xe_module.h"
> +#include "xe_vram.h"
> +
> +#define BAR_SIZE_SHIFT 20
> +
> +static void
> +_resize_bar(struct xe_device *xe, int resno, resource_size_t size)
> +{
> +	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> +	int bar_size = pci_rebar_bytes_to_size(size);
> +	int ret;
> +
> +	if (pci_resource_len(pdev, resno))
> +		pci_release_resource(pdev, resno);
> +
> +	ret = pci_resize_resource(pdev, resno, bar_size);
> +	if (ret) {
> +		drm_info(&xe->drm, "Failed to resize BAR%d to %dM (%pe). Consider enabling 'Resizable BAR' support in your BIOS\n",
> +			 resno, 1 << bar_size, ERR_PTR(ret));
> +		return;
> +	}
> +
> +	drm_info(&xe->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
> +}
> +
> +/*
> + * if force_vram_bar_size is set, attempt to set to the requested size
> + * else set to maximum possible size
> + */
> +static void xe_resize_vram_bar(struct xe_device *xe)
> +{
> +	u64 force_vram_bar_size = xe_modparam.force_vram_bar_size;
> +	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> +	struct pci_bus *root = pdev->bus;
> +	resource_size_t current_size;
> +	resource_size_t rebar_size;
> +	struct resource *root_res;
> +	u32 bar_size_mask;
> +	u32 pci_cmd;
> +	int i;
> +
> +	/* gather some relevant info */
> +	current_size = pci_resource_len(pdev, LMEM_BAR);
> +	bar_size_mask = pci_rebar_get_possible_sizes(pdev, LMEM_BAR);
> +
> +	if (!bar_size_mask)
> +		return;
> +
> +	/* set to a specific size? */
> +	if (force_vram_bar_size) {
> +		u32 bar_size_bit;
> +
> +		rebar_size = force_vram_bar_size * (resource_size_t)SZ_1M;
> +
> +		bar_size_bit = bar_size_mask & BIT(pci_rebar_bytes_to_size(rebar_size));
> +
> +		if (!bar_size_bit) {
> +			drm_info(&xe->drm,
> +				 "Requested size: %lluMiB is not supported by rebar sizes: 0x%x. Leaving default: %lluMiB\n",
> +				 (u64)rebar_size >> 20, bar_size_mask, (u64)current_size >> 20);
> +			return;
> +		}
> +
> +		rebar_size = 1ULL << (__fls(bar_size_bit) + BAR_SIZE_SHIFT);
> +
> +		if (rebar_size == current_size)
> +			return;
> +	} else {
> +		rebar_size = 1ULL << (__fls(bar_size_mask) + BAR_SIZE_SHIFT);
> +
> +		/* only resize if larger than current */
> +		if (rebar_size <= current_size)
> +			return;
> +	}
> +
> +	drm_info(&xe->drm, "Attempting to resize bar from %lluMiB -> %lluMiB\n",
> +		 (u64)current_size >> 20, (u64)rebar_size >> 20);
> +
> +	while (root->parent)
> +		root = root->parent;
> +
> +	pci_bus_for_each_resource(root, root_res, i) {
> +		if (root_res && root_res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
> +		    (u64)root_res->start > 0x100000000ul)
> +			break;
> +	}
> +
> +	if (!root_res) {
> +		drm_info(&xe->drm, "Can't resize VRAM BAR - platform support is missing. Consider enabling 'Resizable BAR' support in your BIOS\n");
> +		return;
> +	}
> +
> +	pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
> +	pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd & ~PCI_COMMAND_MEMORY);
> +
> +	_resize_bar(xe, LMEM_BAR, rebar_size);
> +
> +	pci_assign_unassigned_bus_resources(pdev->bus);
> +	pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
> +}
> +
> +static bool xe_pci_resource_valid(struct pci_dev *pdev, int bar)
> +{
> +	if (!pci_resource_flags(pdev, bar))
> +		return false;
> +
> +	if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET)
> +		return false;
> +
> +	if (!pci_resource_len(pdev, bar))
> +		return false;
> +
> +	return true;
> +}
> +
> +static int xe_determine_lmem_bar_size(struct xe_device *xe)
> +{
> +	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> +
> +	if (!xe_pci_resource_valid(pdev, LMEM_BAR)) {
> +		drm_err(&xe->drm, "pci resource is not valid\n");
> +		return -ENXIO;
> +	}
> +
> +	xe_resize_vram_bar(xe);
> +
> +	xe->mem.vram.io_start = pci_resource_start(pdev, LMEM_BAR);
> +	xe->mem.vram.io_size = pci_resource_len(pdev, LMEM_BAR);
> +	if (!xe->mem.vram.io_size)
> +		return -EIO;
> +
> +	/* XXX: Need to change when xe link code is ready */
> +	xe->mem.vram.dpa_base = 0;
> +
> +	/* set up a map to the total memory area. */
> +	xe->mem.vram.mapping = ioremap_wc(xe->mem.vram.io_start, xe->mem.vram.io_size);
> +
> +	return 0;
> +}
> +
> +static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
> +{
> +	struct xe_device *xe = gt_to_xe(gt);
> +	u64 offset;
> +	u32 reg;
> +
> +	if (GRAPHICS_VER(xe) >= 20) {
> +		u64 ccs_size = tile_size / 512;
> +		u64 offset_hi, offset_lo;
> +		u32 nodes, num_enabled;
> +
> +		reg = xe_mmio_read32(gt, MIRROR_FUSE3);
> +		nodes = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, reg);
> +		num_enabled = hweight32(nodes); /* Number of enabled l3 nodes */
> +
> +		reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_LOWER);
> +		offset_lo = REG_FIELD_GET(XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK, reg);
> +
> +		reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_UPPER);
> +		offset_hi = REG_FIELD_GET(XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK, reg);
> +
> +		offset = offset_hi << 32; /* HW view bits 39:32 */
> +		offset |= offset_lo << 6; /* HW view bits 31:6 */
> +		offset *= num_enabled; /* convert to SW view */
> +
> +		/* We don't expect any holes */
> +		xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(gt, GSMBASE) - ccs_size),
> +			      "Hole between CCS and GSM.\n");
> +	} else {
> +		reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
> +		offset = (u64)REG_FIELD_GET(XEHP_FLAT_CCS_PTR, reg) * SZ_64K;
> +	}
> +
> +	return offset;
> +}
> +
> +/**
> + * xe_mmio_tile_vram_size() - Collect vram size and offset information
> + * @tile: tile to get info for
> + * @vram_size: available vram (size - device reserved portions)
> + * @tile_size: actual vram size
> + * @tile_offset: physical start point in the vram address space
> + *
> + * There are 4 places for size information:
> + * - io size (from pci_resource_len of LMEM bar) (only used for small bar and DG1)
> + * - TILEx size (actual vram size)
> + * - GSMBASE offset (TILEx - "stolen")
> + * - CSSBASE offset (TILEx - CSS space necessary)
> + *
> + * CSSBASE is always a lower/smaller offset then GSMBASE.
> + *
> + * The actual available size of memory is to the CCS or GSM base.
> + * NOTE: multi-tile bases will include the tile offset.
> + *
> + */
> +static int xe_mmio_tile_vram_size(struct xe_tile *tile, u64 *vram_size,
> +				  u64 *tile_size, u64 *tile_offset)
> +{
> +	struct xe_device *xe = tile_to_xe(tile);
> +	struct xe_gt *gt = tile->primary_gt;
> +	u64 offset;
> +	int err;
> +	u32 reg;
> +
> +	err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
> +	if (err)
> +		return err;
> +
> +	/* actual size */
> +	if (unlikely(xe->info.platform == XE_DG1)) {
> +		*tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), LMEM_BAR);
> +		*tile_offset = 0;
> +	} else {
> +		reg = xe_gt_mcr_unicast_read_any(gt, XEHP_TILE_ADDR_RANGE(gt->info.id));
> +		*tile_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G;
> +		*tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G;
> +	}
> +
> +	/* minus device usage */
> +	if (xe->info.has_flat_ccs) {
> +		offset = get_flat_ccs_offset(gt, *tile_size);
> +	} else {
> +		offset = xe_mmio_read64_2x32(gt, GSMBASE);
> +	}
> +
> +	/* remove the tile offset so we have just the available size */
> +	*vram_size = offset - *tile_offset;
> +
> +	return xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
> +}
> +
> +static void vram_fini(void *arg)
> +{
> +	struct xe_device *xe = arg;
> +	struct xe_tile *tile;
> +	int id;
> +
> +	if (xe->mem.vram.mapping)
> +		iounmap(xe->mem.vram.mapping);
> +
> +	xe->mem.vram.mapping = NULL;
> +
> +	for_each_tile(tile, xe, id)
> +		tile->mem.vram.mapping = NULL;
> +}
> +
> +/**
> + * xe_vram_probe() - Probe VRAM configuration
> + * @xe: the &xe_device
> + *
> + * Collect VRAM size and offset information for all tiles.
> + *
> + * Return: 0 on success, error code on failure
> + */
> +int xe_vram_probe(struct xe_device *xe)
> +{
> +	struct xe_tile *tile;
> +	resource_size_t io_size;
> +	u64 available_size = 0;
> +	u64 total_size = 0;
> +	u64 tile_offset;
> +	u64 tile_size;
> +	u64 vram_size;
> +	int err;
> +	u8 id;
> +
> +	if (!IS_DGFX(xe))
> +		return 0;
> +
> +	/* Get the size of the root tile's vram for later accessibility comparison */
> +	tile = xe_device_get_root_tile(xe);
> +	err = xe_mmio_tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
> +	if (err)
> +		return err;
> +
> +	err = xe_determine_lmem_bar_size(xe);
> +	if (err)
> +		return err;
> +
> +	drm_info(&xe->drm, "VISIBLE VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
> +		 &xe->mem.vram.io_size);
> +
> +	io_size = xe->mem.vram.io_size;
> +
> +	/* tile specific ranges */
> +	for_each_tile(tile, xe, id) {
> +		err = xe_mmio_tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
> +		if (err)
> +			return err;
> +
> +		tile->mem.vram.actual_physical_size = tile_size;
> +		tile->mem.vram.io_start = xe->mem.vram.io_start + tile_offset;
> +		tile->mem.vram.io_size = min_t(u64, vram_size, io_size);
> +
> +		if (!tile->mem.vram.io_size) {
> +			drm_err(&xe->drm, "Tile without any CPU visible VRAM. Aborting.\n");
> +			return -ENODEV;
> +		}
> +
> +		tile->mem.vram.dpa_base = xe->mem.vram.dpa_base + tile_offset;
> +		tile->mem.vram.usable_size = vram_size;
> +		tile->mem.vram.mapping = xe->mem.vram.mapping + tile_offset;
> +
> +		if (tile->mem.vram.io_size < tile->mem.vram.usable_size)
> +			drm_info(&xe->drm, "Small BAR device\n");
> +		drm_info(&xe->drm, "VRAM[%u, %u]: Actual physical size %pa, usable size exclude stolen %pa, CPU accessible size %pa\n", id,
> +			 tile->id, &tile->mem.vram.actual_physical_size, &tile->mem.vram.usable_size, &tile->mem.vram.io_size);
> +		drm_info(&xe->drm, "VRAM[%u, %u]: DPA range: [%pa-%llx], io range: [%pa-%llx]\n", id, tile->id,
> +			 &tile->mem.vram.dpa_base, tile->mem.vram.dpa_base + (u64)tile->mem.vram.actual_physical_size,
> +			 &tile->mem.vram.io_start, tile->mem.vram.io_start + (u64)tile->mem.vram.io_size);
> +
> +		/* calculate total size using tile size to get the correct HW sizing */
> +		total_size += tile_size;
> +		available_size += vram_size;
> +
> +		if (total_size > xe->mem.vram.io_size) {
> +			drm_info(&xe->drm, "VRAM: %pa is larger than resource %pa\n",
> +				 &total_size, &xe->mem.vram.io_size);
> +		}
> +
> +		io_size -= min_t(u64, tile_size, io_size);
> +	}
> +
> +	xe->mem.vram.actual_physical_size = total_size;
> +
> +	drm_info(&xe->drm, "Total VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
> +		 &xe->mem.vram.actual_physical_size);
> +	drm_info(&xe->drm, "Available VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
> +		 &available_size);
> +
> +	return devm_add_action_or_reset(xe->drm.dev, vram_fini, xe);
> +}
> diff --git a/drivers/gpu/drm/xe/xe_vram.h b/drivers/gpu/drm/xe/xe_vram.h
> new file mode 100644
> index 000000000000..e31cc04ec0db
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_vram.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
> +
> +#ifndef _XE_VRAM_H_
> +#define _XE_VRAM_H_
> +
> +struct xe_device;
> +
> +int xe_vram_probe(struct xe_device *xe);
> +
> +#endif
> -- 
> 2.43.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 4/5] drm/xe: Rename internal vram helper function

[Matt Roper]

On Mon, May 27, 2024 at 07:35:53PM +0200, Michal Wajdeczko wrote:
> Drop no longer applicable "xe_mmio_" prefix and downgrade the
> existing kernel-doc for internal function to normal comment.

As noted on the previous patch, there are several other functions with
"xe_" prefixes even though they're static (xe_resize_vram_bar,
xe_pci_resource_valid, xe_determine_lmem_bar_size, and the
xe_mmio_tile_vram_size you're updating here).  Maybe we should drop the
"xe_" prefix from all of them (and "xe_mmio" from this one) before the
movement of VRAM code to a new file?


Matt
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_vram.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
> index d8b81e4e050c..411e8d23fd4d 100644
> --- a/drivers/gpu/drm/xe/xe_vram.c
> +++ b/drivers/gpu/drm/xe/xe_vram.c
> @@ -192,8 +192,8 @@ static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
>  	return offset;
>  }
>  
> -/**
> - * xe_mmio_tile_vram_size() - Collect vram size and offset information
> +/*
> + * tile_vram_size() - Collect vram size and offset information
>   * @tile: tile to get info for
>   * @vram_size: available vram (size - device reserved portions)
>   * @tile_size: actual vram size
> @@ -211,8 +211,8 @@ static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
>   * NOTE: multi-tile bases will include the tile offset.
>   *
>   */
> -static int xe_mmio_tile_vram_size(struct xe_tile *tile, u64 *vram_size,
> -				  u64 *tile_size, u64 *tile_offset)
> +static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
> +			  u64 *tile_size, u64 *tile_offset)
>  {
>  	struct xe_device *xe = tile_to_xe(tile);
>  	struct xe_gt *gt = tile->primary_gt;
> @@ -287,7 +287,7 @@ int xe_vram_probe(struct xe_device *xe)
>  
>  	/* Get the size of the root tile's vram for later accessibility comparison */
>  	tile = xe_device_get_root_tile(xe);
> -	err = xe_mmio_tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
> +	err = tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
>  	if (err)
>  		return err;
>  
> @@ -302,7 +302,7 @@ int xe_vram_probe(struct xe_device *xe)
>  
>  	/* tile specific ranges */
>  	for_each_tile(tile, xe, id) {
> -		err = xe_mmio_tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
> +		err = tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
>  		if (err)
>  			return err;
>  
> -- 
> 2.43.0
> 
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 5/5] drm/xe/vf: Setup VRAM based on received config data

[Matt Roper]

On Mon, May 27, 2024 at 07:35:54PM +0200, Michal Wajdeczko wrote:
> VF drivers will obtain VRAM configuration from the GuC as part of
> the VF self config. Use that configuration instead of trying to
> read inaccessible registers.
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_gt_sriov_vf.c | 17 +++++++++++++++++
>  drivers/gpu/drm/xe/xe_gt_sriov_vf.h |  1 +
>  drivers/gpu/drm/xe/xe_vram.c        | 18 ++++++++++++++++++
>  3 files changed, 36 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_vf.c b/drivers/gpu/drm/xe/xe_gt_sriov_vf.c
> index da7c64f6285b..41e46a00c01e 100644
> --- a/drivers/gpu/drm/xe/xe_gt_sriov_vf.c
> +++ b/drivers/gpu/drm/xe/xe_gt_sriov_vf.c
> @@ -478,6 +478,23 @@ u16 xe_gt_sriov_vf_guc_ids(struct xe_gt *gt)
>  	return gt->sriov.vf.self_config.num_ctxs;
>  }
>  
> +/**
> + * xe_gt_sriov_vf_lmem - VF LMEM configuration.
> + * @gt: the &xe_gt
> + *
> + * This function is for VF use only.
> + *
> + * Return: size of the LMEM assigned to VF.
> + */
> +u64 xe_gt_sriov_vf_lmem(struct xe_gt *gt)
> +{
> +	xe_gt_assert(gt, IS_SRIOV_VF(gt_to_xe(gt)));
> +	xe_gt_assert(gt, gt->sriov.vf.guc_version.major);
> +	xe_gt_assert(gt, gt->sriov.vf.self_config.lmem_size);
> +
> +	return gt->sriov.vf.self_config.lmem_size;
> +}
> +
>  static int vf_balloon_ggtt(struct xe_gt *gt)
>  {
>  	struct xe_gt_sriov_vf_selfconfig *config = &gt->sriov.vf.self_config;
> diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_vf.h b/drivers/gpu/drm/xe/xe_gt_sriov_vf.h
> index 7a04bcaffe9f..0de7f8cbcfa6 100644
> --- a/drivers/gpu/drm/xe/xe_gt_sriov_vf.h
> +++ b/drivers/gpu/drm/xe/xe_gt_sriov_vf.h
> @@ -20,6 +20,7 @@ int xe_gt_sriov_vf_prepare_ggtt(struct xe_gt *gt);
>  
>  u32 xe_gt_sriov_vf_gmdid(struct xe_gt *gt);
>  u16 xe_gt_sriov_vf_guc_ids(struct xe_gt *gt);
> +u64 xe_gt_sriov_vf_lmem(struct xe_gt *gt);
>  u32 xe_gt_sriov_vf_read32(struct xe_gt *gt, struct xe_reg reg);
>  
>  void xe_gt_sriov_vf_print_config(struct xe_gt *gt, struct drm_printer *p);
> diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
> index 411e8d23fd4d..ccc4791c0e34 100644
> --- a/drivers/gpu/drm/xe/xe_vram.c
> +++ b/drivers/gpu/drm/xe/xe_vram.c
> @@ -15,8 +15,10 @@
>  #include "xe_device.h"
>  #include "xe_force_wake.h"
>  #include "xe_gt_mcr.h"
> +#include "xe_gt_sriov_vf.h"
>  #include "xe_mmio.h"
>  #include "xe_module.h"
> +#include "xe_sriov.h"
>  #include "xe_vram.h"
>  
>  #define BAR_SIZE_SHIFT 20
> @@ -220,6 +222,22 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
>  	int err;
>  	u32 reg;
>  
> +	if (IS_SRIOV_VF(xe)) {
> +		struct xe_tile *t;
> +		int id;
> +
> +		offset = 0;
> +		for_each_tile(t, xe, id)
> +			for_each_if(t->id < tile->id)
> +				offset += xe_gt_sriov_vf_lmem(t->primary_gt);
> +
> +		*tile_size = xe_gt_sriov_vf_lmem(gt);
> +		*vram_size = *tile_size;
> +		*tile_offset = offset;
> +
> +		return 0;
> +	}
> +
>  	err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
>  	if (err)
>  		return err;
> -- 
> 2.43.0
> 
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 4/5] drm/xe: Rename internal vram helper function

[Matthew Brost]

On Tue, May 28, 2024 at 02:35:15PM -0700, Matt Roper wrote:
> On Mon, May 27, 2024 at 07:35:53PM +0200, Michal Wajdeczko wrote:
> > Drop no longer applicable "xe_mmio_" prefix and downgrade the
> > existing kernel-doc for internal function to normal comment.
> 
> As noted on the previous patch, there are several other functions with
> "xe_" prefixes even though they're static (xe_resize_vram_bar,
> xe_pci_resource_valid, xe_determine_lmem_bar_size, and the
> xe_mmio_tile_vram_size you're updating here).  Maybe we should drop the
> "xe_" prefix from all of them (and "xe_mmio" from this one) before the
> movement of VRAM code to a new file?
> 

We have talked about this before and I think the consensous was "xe_"
prefixes for static functions are fine, perhaps even desired. I can't
find a reference but I do recall a discussion on the list about this.

I think the maintainers should make / document a rule wrt to "xe_"
prefixes before we start making changes in this area as it is not clear.

Matt

> 
> Matt
> > 
> > Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_vram.c | 12 ++++++------
> >  1 file changed, 6 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
> > index d8b81e4e050c..411e8d23fd4d 100644
> > --- a/drivers/gpu/drm/xe/xe_vram.c
> > +++ b/drivers/gpu/drm/xe/xe_vram.c
> > @@ -192,8 +192,8 @@ static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
> >  	return offset;
> >  }
> >  
> > -/**
> > - * xe_mmio_tile_vram_size() - Collect vram size and offset information
> > +/*
> > + * tile_vram_size() - Collect vram size and offset information
> >   * @tile: tile to get info for
> >   * @vram_size: available vram (size - device reserved portions)
> >   * @tile_size: actual vram size
> > @@ -211,8 +211,8 @@ static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
> >   * NOTE: multi-tile bases will include the tile offset.
> >   *
> >   */
> > -static int xe_mmio_tile_vram_size(struct xe_tile *tile, u64 *vram_size,
> > -				  u64 *tile_size, u64 *tile_offset)
> > +static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
> > +			  u64 *tile_size, u64 *tile_offset)
> >  {
> >  	struct xe_device *xe = tile_to_xe(tile);
> >  	struct xe_gt *gt = tile->primary_gt;
> > @@ -287,7 +287,7 @@ int xe_vram_probe(struct xe_device *xe)
> >  
> >  	/* Get the size of the root tile's vram for later accessibility comparison */
> >  	tile = xe_device_get_root_tile(xe);
> > -	err = xe_mmio_tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
> > +	err = tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
> >  	if (err)
> >  		return err;
> >  
> > @@ -302,7 +302,7 @@ int xe_vram_probe(struct xe_device *xe)
> >  
> >  	/* tile specific ranges */
> >  	for_each_tile(tile, xe, id) {
> > -		err = xe_mmio_tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
> > +		err = tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
> >  		if (err)
> >  			return err;
> >  
> > -- 
> > 2.43.0
> > 
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation

Re: [PATCH 4/5] drm/xe: Rename internal vram helper function

[Michal Wajdeczko]

++ maintainers

On 29.05.2024 00:15, Matthew Brost wrote:
> On Tue, May 28, 2024 at 02:35:15PM -0700, Matt Roper wrote:
>> On Mon, May 27, 2024 at 07:35:53PM +0200, Michal Wajdeczko wrote:
>>> Drop no longer applicable "xe_mmio_" prefix and downgrade the
>>> existing kernel-doc for internal function to normal comment.
>>
>> As noted on the previous patch, there are several other functions with
>> "xe_" prefixes even though they're static (xe_resize_vram_bar,
>> xe_pci_resource_valid, xe_determine_lmem_bar_size, and the
>> xe_mmio_tile_vram_size you're updating here).  Maybe we should drop the
>> "xe_" prefix from all of them (and "xe_mmio" from this one) before the
>> movement of VRAM code to a new file?

agree on doing all renames for consistency, but this time I just didn't
want to make too many cleanups in one shot, my focus was to do clear
code separation first

>>
> 
> We have talked about this before and I think the consensous was "xe_"
> prefixes for static functions are fine, perhaps even desired. I can't

IMO use of "xe_foo" prefix for static functions is inconsistent (as its
name suggests that it is public function while OTOH it is declared as
static) and may mislead that it could be used in other compilation unit.

thus use of "xe_" (for static) should be rather discouraged but also at
the same time it shouldn't be treated as showstopper (with the hope
better name will be provided later)

> find a reference but I do recall a discussion on the list about this.
> 
> I think the maintainers should make / document a rule wrt to "xe_"
> prefixes before we start making changes in this area as it is not clear.

before we start writing rules for static functions, better to focus only
on rules for public naming convention for the components, like:

files:
	GOOD
		xe_foo.ch
		xe_foo_types.h
		xe_foo_helpers.h
	FINE
		xe_gt_foo.ch
	BAD
		foo.ch

types:
	GOOD
		struct xe_foo_xxx
		enum xe_foo_yyy
		typedef xe_foo_zzz
	BAD
		struct foo
		struct xe_bar

functions:
	GOOD
		xe_foo_bar(struct xe_foo *foo, ...)
	FINE
		xe_foo_bar(struct xe_device *xe, ...)
		xe_gt_foo_bar(struct xe_gt *gt, ...)
	BAD
		xe_foo_bar(..., struct xe_foo *foo)
		xe_bar_foo(struct xe_foo *foo, ...)

> 
> Matt
> 
>>
>> Matt
>>>
>>> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
>>> ---
>>>  drivers/gpu/drm/xe/xe_vram.c | 12 ++++++------
>>>  1 file changed, 6 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
>>> index d8b81e4e050c..411e8d23fd4d 100644
>>> --- a/drivers/gpu/drm/xe/xe_vram.c
>>> +++ b/drivers/gpu/drm/xe/xe_vram.c
>>> @@ -192,8 +192,8 @@ static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
>>>  	return offset;
>>>  }
>>>  
>>> -/**
>>> - * xe_mmio_tile_vram_size() - Collect vram size and offset information
>>> +/*
>>> + * tile_vram_size() - Collect vram size and offset information
>>>   * @tile: tile to get info for
>>>   * @vram_size: available vram (size - device reserved portions)
>>>   * @tile_size: actual vram size
>>> @@ -211,8 +211,8 @@ static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
>>>   * NOTE: multi-tile bases will include the tile offset.
>>>   *
>>>   */
>>> -static int xe_mmio_tile_vram_size(struct xe_tile *tile, u64 *vram_size,
>>> -				  u64 *tile_size, u64 *tile_offset)
>>> +static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
>>> +			  u64 *tile_size, u64 *tile_offset)
>>>  {
>>>  	struct xe_device *xe = tile_to_xe(tile);
>>>  	struct xe_gt *gt = tile->primary_gt;
>>> @@ -287,7 +287,7 @@ int xe_vram_probe(struct xe_device *xe)
>>>  
>>>  	/* Get the size of the root tile's vram for later accessibility comparison */
>>>  	tile = xe_device_get_root_tile(xe);
>>> -	err = xe_mmio_tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
>>> +	err = tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
>>>  	if (err)
>>>  		return err;
>>>  
>>> @@ -302,7 +302,7 @@ int xe_vram_probe(struct xe_device *xe)
>>>  
>>>  	/* tile specific ranges */
>>>  	for_each_tile(tile, xe, id) {
>>> -		err = xe_mmio_tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
>>> +		err = tile_vram_size(tile, &vram_size, &tile_size, &tile_offset);
>>>  		if (err)
>>>  			return err;
>>>  
>>> -- 
>>> 2.43.0
>>>
>>>
>>
>> -- 
>> Matt Roper
>> Graphics Software Engineer
>> Linux GPU Platform Enablement
>> Intel Corporation

Re: [PATCH 4/5] drm/xe: Rename internal vram helper function

[Jani Nikula]

On Wed, 29 May 2024, Michal Wajdeczko <michal.wajdeczko@intel.com> wrote:
> ++ maintainers
>
> On 29.05.2024 00:15, Matthew Brost wrote:
>> We have talked about this before and I think the consensous was "xe_"
>> prefixes for static functions are fine, perhaps even desired. I can't
>
> IMO use of "xe_foo" prefix for static functions is inconsistent (as its
> name suggests that it is public function while OTOH it is declared as
> static) and may mislead that it could be used in other compilation unit.
>
> thus use of "xe_" (for static) should be rather discouraged but also at
> the same time it shouldn't be treated as showstopper (with the hope
> better name will be provided later)
>
>> find a reference but I do recall a discussion on the list about this.
>> 
>> I think the maintainers should make / document a rule wrt to "xe_"
>> prefixes before we start making changes in this area as it is not clear.

IMO the prefix is useful even for static functions for a few reasons:

- C has no namespaces. The use of prefixes in the kernel global
  functions and macros is inconsistent at best. Prefixes avoid clashes.

- It's quite handy to be able to just glance at a backtrace to see where
  it's originating from. With a bunch of generic non-prefixed functions
  in there, you kind of lose track, and have to look at the source.

- During refactoring, it's not uncommon to make functions
  static/non-static, and having to rename at that point is a bit
  tedious.

That said, we haven't required this in i915. Also platform acronym
prefixes are common especially in display code. Some people have started
adding single underscore prefixes for static functions in a few places,
but I pretty much frown on that.

> before we start writing rules for static functions, better to focus only
> on rules for public naming convention for the components, like:
>
> files:
> 	GOOD
> 		xe_foo.ch
> 		xe_foo_types.h
> 		xe_foo_helpers.h
> 	FINE
> 		xe_gt_foo.ch
> 	BAD
> 		foo.ch
>
> types:
> 	GOOD
> 		struct xe_foo_xxx
> 		enum xe_foo_yyy
> 		typedef xe_foo_zzz
> 	BAD
> 		struct foo
> 		struct xe_bar
>
> functions:
> 	GOOD
> 		xe_foo_bar(struct xe_foo *foo, ...)
> 	FINE
> 		xe_foo_bar(struct xe_device *xe, ...)
> 		xe_gt_foo_bar(struct xe_gt *gt, ...)
> 	BAD
> 		xe_foo_bar(..., struct xe_foo *foo)
> 		xe_bar_foo(struct xe_foo *foo, ...)

And sometimes you want to prefer names that are easy to pronounce and
make sense over names that strictly adhere to rules...

BR,
Jani.


-- 
Jani Nikula, Intel

Re: [PATCH 4/5] drm/xe: Rename internal vram helper function

[Michal Wajdeczko]

On 29.05.2024 13:50, Jani Nikula wrote:
> On Wed, 29 May 2024, Michal Wajdeczko <michal.wajdeczko@intel.com> wrote:
>> ++ maintainers
>>
>> On 29.05.2024 00:15, Matthew Brost wrote:
>>> We have talked about this before and I think the consensous was "xe_"
>>> prefixes for static functions are fine, perhaps even desired. I can't
>>
>> IMO use of "xe_foo" prefix for static functions is inconsistent (as its
>> name suggests that it is public function while OTOH it is declared as
>> static) and may mislead that it could be used in other compilation unit.
>>
>> thus use of "xe_" (for static) should be rather discouraged but also at
>> the same time it shouldn't be treated as showstopper (with the hope
>> better name will be provided later)
>>
>>> find a reference but I do recall a discussion on the list about this.
>>>
>>> I think the maintainers should make / document a rule wrt to "xe_"
>>> prefixes before we start making changes in this area as it is not clear.
> 
> IMO the prefix is useful even for static functions for a few reasons:
> 
> - C has no namespaces. The use of prefixes in the kernel global
>   functions and macros is inconsistent at best. Prefixes avoid clashes.

good point but I guess any new global function will be named in a way
that will minimize risk of clash

> 
> - It's quite handy to be able to just glance at a backtrace to see where
>   it's originating from. With a bunch of generic non-prefixed functions
>   in there, you kind of lose track, and have to look at the source.

if you are unlucky and not all static functions were inlined then still
the backtrace shall include top level public xe_foo() function

> 
> - During refactoring, it's not uncommon to make functions
>   static/non-static, and having to rename at that point is a bit
>   tedious.

another good reason to avoid refactoring and come with good design in
the first place ;)

> 
> That said, we haven't required this in i915. Also platform acronym
> prefixes are common especially in display code. Some people have started
> adding single underscore prefixes for static functions in a few places,
> but I pretty much frown on that.

and sometimes static functions names are defined/added to clarify the
flow or function logic, and strict adhere to rules to have a prefix
might make it less clear, so some room for common sense is still needed

> 
>> before we start writing rules for static functions, better to focus only
>> on rules for public naming convention for the components, like:
>>
>> files:
>> 	GOOD
>> 		xe_foo.ch
>> 		xe_foo_types.h
>> 		xe_foo_helpers.h
>> 	FINE
>> 		xe_gt_foo.ch
>> 	BAD
>> 		foo.ch
>>
>> types:
>> 	GOOD
>> 		struct xe_foo_xxx
>> 		enum xe_foo_yyy
>> 		typedef xe_foo_zzz
>> 	BAD
>> 		struct foo
>> 		struct xe_bar
>>
>> functions:
>> 	GOOD
>> 		xe_foo_bar(struct xe_foo *foo, ...)
>> 	FINE
>> 		xe_foo_bar(struct xe_device *xe, ...)
>> 		xe_gt_foo_bar(struct xe_gt *gt, ...)
>> 	BAD
>> 		xe_foo_bar(..., struct xe_foo *foo)
>> 		xe_bar_foo(struct xe_foo *foo, ...)
> 
> And sometimes you want to prefer names that are easy to pronounce and
> make sense over names that strictly adhere to rules...

but then it should be treated as an exception, to be approved by the
maintainer, from general guidelines that maintainers can still document

> 
> BR,
> Jani.
> 
> 

Re: [PATCH 4/5] drm/xe: Rename internal vram helper function

[Jani Nikula]

On Wed, 29 May 2024, Michal Wajdeczko <michal.wajdeczko@intel.com> wrote:

[snip]

> but then it should be treated as an exception, to be approved by the
> maintainer, from general guidelines that maintainers can still document

I'll just note that I only provided some points of view for
consideration, won't argue them further, and I'll just defer to the xe
maintainers to provide the guidelines here. (What a nice feeling to be
able to do so. ;)

BR,
Jani.

-- 
Jani Nikula, Intel

Re: [PATCH 4/5] drm/xe: Rename internal vram helper function

[Lucas De Marchi]

On Wed, May 29, 2024 at 03:52:14PM GMT, Jani Nikula wrote:
>On Wed, 29 May 2024, Michal Wajdeczko <michal.wajdeczko@intel.com> wrote:
>
>[snip]
>
>> but then it should be treated as an exception, to be approved by the
>> maintainer, from general guidelines that maintainers can still document
>
>I'll just note that I only provided some points of view for
>consideration, won't argue them further, and I'll just defer to the xe
>maintainers to provide the guidelines here. (What a nice feeling to be
>able to do so. ;)

I very much prefer dropping the prefix for static functions.  If there's
a clash with a global one, either a) you're including too much b) you
should use a better name or c) the global one could use a better
name.... An often we can just add the second part of the prefix, just
leaving the xe_ out, which makes those clashes go away. It makes a clear
separation of what can be use in a single compilation unit vs what is
calling something from outside.

IMO platform prefixes and double underscores that i915 uses are also
bad:  a compilation unit should abstract it with proper layer of
separation, otherwise it made a bad abstraction.

Lucas De Marchi

>
>BR,
>Jani.
>
>-- 
>Jani Nikula, Intel

Re: [PATCH 4/5] drm/xe: Rename internal vram helper function

[Jani Nikula]

On Wed, 29 May 2024, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> I very much prefer dropping the prefix for static functions.  If there's
> a clash with a global one, either a) you're including too much b) you
> should use a better name or c) the global one could use a better
> name....

I think all of the a), b), and c) evaluate to true. ;D

But sadly a) and c) are often out of your control, a) due to recursively
transitive includes that end up including the world, and c) simply
because you can't fix the world.

Case in point, commit 35b22649eb41 ("drm/xe: Fix END redefinition").

But then you just fix it, and move on.

> IMO platform prefixes and double underscores that i915 uses are also
> bad:  a compilation unit should abstract it with proper layer of
> separation, otherwise it made a bad abstraction.

No argument there. It's just a lot of legacy.


BR,
Jani.


-- 
Jani Nikula, Intel

Re: [PATCH 4/5] drm/xe: Rename internal vram helper function

[Lucas De Marchi]

On Wed, May 29, 2024 at 09:01:57PM GMT, Jani Nikula wrote:
>On Wed, 29 May 2024, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> I very much prefer dropping the prefix for static functions.  If there's
>> a clash with a global one, either a) you're including too much b) you
>> should use a better name or c) the global one could use a better
>> name....
>
>I think all of the a), b), and c) evaluate to true. ;D
>
>But sadly a) and c) are often out of your control, a) due to recursively
>transitive includes that end up including the world, and c) simply
>because you can't fix the world.
>
>Case in point, commit 35b22649eb41 ("drm/xe: Fix END redefinition").
>
>But then you just fix it, and move on.

yes, and that is perfectly fine. That particular fix happened mostly
because we were out of tree and not trying to build to all possible
arches. Now that we are, we noticed the issue, fixed it and
moved on.

Lucas De Marchi

>
>> IMO platform prefixes and double underscores that i915 uses are also
>> bad:  a compilation unit should abstract it with proper layer of
>> separation, otherwise it made a bad abstraction.
>
>No argument there. It's just a lot of legacy.
>
>
>BR,
>Jani.
>
>
>-- 
>Jani Nikula, Intel