From: Jani Nikula <jani.nikula@linux.intel.com>
To: Luca Coelho <luciano.coelho@intel.com>, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org, ville.syrjala@linux.intel.com
Subject: Re: [PATCH v4 5/8] drm/i915/display: move GLK clock gating init to display
Date: Mon, 27 Apr 2026 12:50:03 +0300 [thread overview]
Message-ID: <c4cea3b1fe889f18692508d7795d07b2a42b686e@intel.com> (raw)
In-Reply-To: <20260420202252.3846880-6-luciano.coelho@intel.com>
On Mon, 20 Apr 2026, Luca Coelho <luciano.coelho@intel.com> wrote:
> Move the GLK-specific display clock gating programming into display
> intel_display_clock_gating.c, to remove more dependencies from i915 to
> display registers.
>
> Now that all remaining Gen9-family callers moved into display, we can
> move the shared Gen9 display clock gating helper into display and
> remove the old local helper from intel_clock_gating.c.
>
> Additionally, the SKL_DE_COMPRESSED_HASH_MODE programming was
> protected by HAS_LLC(), but that's incidental, because in Gen9
> platforms, only SKL and KBL, for which this workaround applies, have
> LLC(). In order not to use HAS_LLC() in display code, we can simply
> remove this check from the generic Gen9 function and move the
> SKL_DE_COMPRESSED_HASH_MODE programming to the KBL and SKL specific
> functions.
The macros in i915_pci.c are hard to read, but basically for gen 9 you
have GEN9_FEATURES and GEN9_LP_FEATURES.
GEN9_FEATURES "inherits" .has_llc = 1 through GEN7_FEATURES ->
G75_FEATURES -> GEN8_FEATURES -> GEN9_FEATURES. GEN9_LP_FEATURES does
not have it.
SKL, KBL, CFL, and CML use GEN9_FEATURES i.e. have LLC.
BXT, GLK use GEN9_LP_FEATURES i.e. don't have LLC.
CML and CFL share the functions, so this is a long-winded way of saying
that intel_display_cfl_init_clock_gating() also needs the
SKL_DE_COMPRESSED_HASH_MODE programming.
BR,
Jani.
>
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> ---
> .../i915/display/intel_display_clock_gating.c | 57 +++++++++++++++++++
> .../i915/display/intel_display_clock_gating.h | 1 +
> drivers/gpu/drm/i915/intel_clock_gating.c | 44 +-------------
> 3 files changed, 59 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> index 59041c807d6d..b2cb18478577 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> @@ -6,11 +6,39 @@
> #include <drm/intel/intel_gmd_misc_regs.h>
>
> #include "intel_de.h"
> +#include "intel_display.h"
> #include "intel_display_clock_gating.h"
> +#include "intel_display_core.h"
> #include "intel_display_regs.h"
>
> +static void intel_display_gen9_init_clock_gating(struct intel_display *display)
> +{
> + /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
> + intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP);
> +
> + /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
> + intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
> +
> + /*
> + * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
> + * Display WA #0859: skl,bxt,kbl,glk,cfl
> + */
> + intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
> +}
> +
> void intel_display_skl_init_clock_gating(struct intel_display *display)
> {
> + /*
> + * WaCompressedResourceDisplayNewHashMode:skl,kbl
> + * Display WA #0390: skl,kbl
> + *
> + * Must match Sampler, Pixel Back End, and Media. See
> + * WaCompressedResourceSamplerPbeMediaNewHashMode.
> + */
> + intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
> +
> + intel_display_gen9_init_clock_gating(display);
> +
> /*
> * WaFbcTurnOffFbcWatermark:skl
> * Display WA #0562: skl
> @@ -20,6 +48,17 @@ void intel_display_skl_init_clock_gating(struct intel_display *display)
>
> void intel_display_kbl_init_clock_gating(struct intel_display *display)
> {
> + /*
> + * WaCompressedResourceDisplayNewHashMode:skl,kbl
> + * Display WA #0390: skl,kbl
> + *
> + * Must match Sampler, Pixel Back End, and Media. See
> + * WaCompressedResourceSamplerPbeMediaNewHashMode.
> + */
> + intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
> +
> + intel_display_gen9_init_clock_gating(display);
> +
> /*
> * WaFbcTurnOffFbcWatermark:kbl
> * Display WA #0562: kbl
> @@ -29,6 +68,8 @@ void intel_display_kbl_init_clock_gating(struct intel_display *display)
>
> void intel_display_cfl_init_clock_gating(struct intel_display *display)
> {
> + intel_display_gen9_init_clock_gating(display);
> +
> /*
> * WaFbcTurnOffFbcWatermark:cfl
> * Display WA #0562: cfl
> @@ -38,6 +79,8 @@ void intel_display_cfl_init_clock_gating(struct intel_display *display)
>
> void intel_display_bxt_init_clock_gating(struct intel_display *display)
> {
> + intel_display_gen9_init_clock_gating(display);
> +
> /*
> * Wa: Backlight PWM may stop in the asserted state, causing backlight
> * to stay fully on.
> @@ -60,3 +103,17 @@ void intel_display_bxt_init_clock_gating(struct intel_display *display)
> */
> intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
> }
> +
> +void intel_display_glk_init_clock_gating(struct intel_display *display)
> +{
> + intel_display_gen9_init_clock_gating(display);
> +
> + /*
> + * WaDisablePWMClockGating:glk
> + * Backlight PWM may stop in the asserted state, causing backlight
> + * to stay fully on.
> + */
> + intel_de_write(display, GEN9_CLKGATE_DIS_0,
> + intel_de_read(display, GEN9_CLKGATE_DIS_0) |
> + PWM1_GATING_DIS | PWM2_GATING_DIS);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> index 6bc84a9a4342..a7784db9d97a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> @@ -12,5 +12,6 @@ void intel_display_skl_init_clock_gating(struct intel_display *display);
> void intel_display_kbl_init_clock_gating(struct intel_display *display);
> void intel_display_cfl_init_clock_gating(struct intel_display *display);
> void intel_display_bxt_init_clock_gating(struct intel_display *display);
> +void intel_display_glk_init_clock_gating(struct intel_display *display);
>
> #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
> diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
> index a9efa5ce8f6a..96fe16753e58 100644
> --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> @@ -49,36 +49,8 @@ struct drm_i915_clock_gating_funcs {
> void (*init_clock_gating)(struct drm_i915_private *i915);
> };
>
> -static void gen9_init_clock_gating(struct drm_i915_private *i915)
> -{
> - if (HAS_LLC(i915)) {
> - /*
> - * WaCompressedResourceDisplayNewHashMode:skl,kbl
> - * Display WA #0390: skl,kbl
> - *
> - * Must match Sampler, Pixel Back End, and Media. See
> - * WaCompressedResourceSamplerPbeMediaNewHashMode.
> - */
> - intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
> - }
> -
> - /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
> - intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP);
> -
> - /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
> - intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
> -
> - /*
> - * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
> - * Display WA #0859: skl,bxt,kbl,glk,cfl
> - */
> - intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
> -}
> -
> static void bxt_init_clock_gating(struct drm_i915_private *i915)
> {
> - gen9_init_clock_gating(i915);
> -
> /* WaDisableSDEUnitClockGating:bxt */
> intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>
> @@ -93,16 +65,7 @@ static void bxt_init_clock_gating(struct drm_i915_private *i915)
>
> static void glk_init_clock_gating(struct drm_i915_private *i915)
> {
> - gen9_init_clock_gating(i915);
> -
> - /*
> - * WaDisablePWMClockGating:glk
> - * Backlight PWM may stop in the asserted state, causing backlight
> - * to stay fully on.
> - */
> - intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0,
> - intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) |
> - PWM1_GATING_DIS | PWM2_GATING_DIS);
> + intel_display_glk_init_clock_gating(i915->display);
> }
>
> static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
> @@ -282,7 +245,6 @@ static void dg2_init_clock_gating(struct drm_i915_private *i915)
> static void cfl_init_clock_gating(struct drm_i915_private *i915)
> {
> intel_pch_init_clock_gating(i915->display);
> - gen9_init_clock_gating(i915);
>
> /* WAC6entrylatency:cfl */
> intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
> @@ -292,8 +254,6 @@ static void cfl_init_clock_gating(struct drm_i915_private *i915)
>
> static void kbl_init_clock_gating(struct drm_i915_private *i915)
> {
> - gen9_init_clock_gating(i915);
> -
> /* WAC6entrylatency:kbl */
> intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
>
> @@ -312,8 +272,6 @@ static void kbl_init_clock_gating(struct drm_i915_private *i915)
>
> static void skl_init_clock_gating(struct drm_i915_private *i915)
> {
> - gen9_init_clock_gating(i915);
> -
> /* WaDisableDopClockGating:skl */
> intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL,
> GEN7_DOP_CLOCK_GATE_ENABLE, 0);
--
Jani Nikula, Intel
next prev parent reply other threads:[~2026-04-27 9:50 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-20 20:22 [PATCH v4 0/8] drm/i915: move more display dependencies from i915 Luca Coelho
2026-04-20 20:22 ` [PATCH v4 1/8] drm/i915: move SKL clock gating init to display Luca Coelho
2026-04-20 20:22 ` [PATCH v4 2/8] drm/i915: move KBL " Luca Coelho
2026-04-20 20:22 ` [PATCH v4 3/8] drm/i915/display: move CFL " Luca Coelho
2026-04-20 20:22 ` [PATCH v4 4/8] drm/i915/display: move BXT " Luca Coelho
2026-04-20 20:22 ` [PATCH v4 5/8] drm/i915/display: move GLK " Luca Coelho
2026-04-27 9:50 ` Jani Nikula [this message]
2026-04-28 9:14 ` Luca Coelho
2026-04-20 20:22 ` [PATCH v4 6/8] drm/i915/display: move HSW and BDW " Luca Coelho
2026-04-20 20:22 ` [PATCH v4 7/8] drm/i915/display: move pre-HSW " Luca Coelho
2026-04-20 20:22 ` [PATCH v4 8/8] drm/i915: remove HAS_PCH_NOP() dependency from clock gating Luca Coelho
2026-04-21 2:39 ` ✗ CI.checkpatch: warning for drm/i915: move more display dependencies from i915 (rev4) Patchwork
2026-04-21 2:40 ` ✓ CI.KUnit: success " Patchwork
2026-04-21 3:27 ` ✓ Xe.CI.BAT: " Patchwork
2026-04-21 5:46 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-04-27 10:06 ` [PATCH v4 0/8] drm/i915: move more display dependencies from i915 Jani Nikula
2026-04-28 9:41 ` Luca Coelho
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