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* [PATCH v2] drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling
@ 2025-12-12  5:54 Animesh Manna
  2025-12-12  8:00 ` ✓ CI.KUnit: success for drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling (rev3) Patchwork
                   ` (3 more replies)
  0 siblings, 4 replies; 6+ messages in thread
From: Animesh Manna @ 2025-12-12  5:54 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: jani.nikula, Animesh Manna

Unused bandwidth can be used by external display agents for Panel Replay
enabled DP panel during idleness with link on. Enable source to replace
dummy data from the display with data from another agent by programming
TRANS_DP2_CTL [Panel Replay Tunneling Enable].

Bspec: 68920
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 .../gpu/drm/i915/display/intel_display_regs.h |  1 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 23 +++++++++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9e0d853f4b61..b6fc249a9f09 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2051,6 +2051,7 @@
 #define TRANS_DP2_CTL(trans)			_MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
 #define  TRANS_DP2_128B132B_CHANNEL_CODING	REG_BIT(31)
 #define  TRANS_DP2_PANEL_REPLAY_ENABLE		REG_BIT(30)
+#define  TRANS_DP2_PR_TUNNELING_ENABLE		REG_BIT(26)
 #define  TRANS_DP2_DEBUG_ENABLE			REG_BIT(23)
 
 #define _TRANS_DP2_VFREQHIGH_A			0x600a4
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 2a378a5adc59..0d4cac30e40e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -44,6 +44,7 @@
 #include "intel_dmc.h"
 #include "intel_dp.h"
 #include "intel_dp_aux.h"
+#include "intel_dp_tunnel.h"
 #include "intel_dsb.h"
 #include "intel_frontbuffer.h"
 #include "intel_hdmi.h"
@@ -1018,6 +1019,25 @@ static u8 frames_before_su_entry(struct intel_dp *intel_dp)
 	return frames_before_su_entry;
 }
 
+static void intel_psr_set_pr_bw_optimization(struct intel_dp *intel_dp)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	u8 val;
+
+	if (DISPLAY_VER(display) < 35)
+		return;
+
+	if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
+		return;
+
+	drm_dp_dpcd_readb(&intel_dp->aux, DP_TUNNELING_CAPABILITIES, &val);
+	if (!(val & DP_PANEL_REPLAY_OPTIMIZATION_SUPPORT))
+		return;
+
+	intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
+		     TRANS_DP2_PR_TUNNELING_ENABLE);
+}
+
 static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
@@ -1041,6 +1061,9 @@ static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
 
 	intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
 		     TRANS_DP2_PANEL_REPLAY_ENABLE);
+
+	if (!intel_dp_is_edp(intel_dp))
+		intel_psr_set_pr_bw_optimization(intel_dp);
 }
 
 static void hsw_activate_psr2(struct intel_dp *intel_dp)
-- 
2.29.0


^ permalink raw reply related	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-12-29 10:36 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-12-12  5:54 [PATCH v2] drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling Animesh Manna
2025-12-12  8:00 ` ✓ CI.KUnit: success for drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling (rev3) Patchwork
2025-12-12  8:06 ` [PATCH v2] drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling Jani Nikula
2025-12-29 10:36   ` Manna, Animesh
2025-12-12  8:42 ` ✓ Xe.CI.BAT: success for drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling (rev3) Patchwork
2025-12-12 21:53 ` ✗ Xe.CI.Full: failure " Patchwork

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