Re: [PATCH v3 2/5] drm/xe/xe_ras: Add support to get error counter in CRI

["Tauro, Riana" <riana.tauro@intel.com>]

On 4/23/2026 4:21 PM, Raag Jadav wrote:
> On Tue, Apr 21, 2026 at 08:20:58PM +0530, Riana Tauro wrote:
>> Add request/response structures and helper functions to query system
>> controller to get error counter value.
> ...
>
>> +/**
>> + * xe_ras_get_error_counter() - Get error counter value
>> + * @xe: xe device instance
>> + * @severity: Error severity level to be queried
>> + * @error_id: Error component to be queried
>> + * @value: Counter value
>> + *
>> + * This function retrieves the value of a specific RAS error counter based on
>> + * the provided severity and component.
>> + *
>> + * Return: 0 on success, negative error code on failure.
>> + */
>> +int xe_ras_get_error_counter(struct xe_device *xe, enum drm_xe_ras_error_severity severity,
> xe_ras_get_counter()? Pretty please.

Any reason?

>
>> +			     u32 error_id, u32 *value)
>> +{
>> +	struct xe_ras_error_class error_class = {0};
>> +
>> +	error_class.common.severity = drm_to_xe_ras_severity[severity];
>> +	error_class.common.component = drm_to_xe_ras_component[error_id];
>> +
>> +	guard(xe_pm_runtime)(xe);
>> +	return get_error_counter(xe, &error_class, value);
>> +}
> ...
>
>> +++ b/drivers/gpu/drm/xe/xe_ras_types.h
>> @@ -0,0 +1,92 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2026 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_RAS_TYPES_H_
>> +#define _XE_RAS_TYPES_H_
>> +
>> +#include <linux/types.h>
>> +
>> +#define XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE	200
> Any users?


Missed removing this..

Thanks
Riana

>
> Raag