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* [PATCH 0/7] Add support for 3 VDSC engines 12 slices
@ 2024-10-27 13:45 Ankit Nautiyal
  2024-10-27 13:45 ` [PATCH 1/7] drm/i915/dp: Update Comment for Valid DSC Slices per Line Ankit Nautiyal
                   ` (15 more replies)
  0 siblings, 16 replies; 19+ messages in thread
From: Ankit Nautiyal @ 2024-10-27 13:45 UTC (permalink / raw)
  To: intel-gfx; +Cc: intel-xe, suraj.kandpal

For BMG 3 VDSC engines are supported and each pipe can then support
3 slices. For Ultra joiner cases for modes like 8k@120 Hz we require
ultrajoiner and 3 x 4= 12 slices.
Add support for 3 VDSC engines and 12 DSC slices.

Rev2: Rebase
Rev3:
-Add patch to account for pixel replication in pipe_src.
-Fix kernel test bot warning.
-Minor refactoring.
Rev4:
-Address review comments from last version.
-Add BW consideration with pixel replication
-Split Odd pixel handling in separate patches.
Rev 5:
-Use num_streams instead of dsc_split.
Rev 6:
-Dropped patches for pixel replication and odd pixel removal.

Ankit Nautiyal (7):
  drm/i915/dp: Update Comment for Valid DSC Slices per Line
  drm/i915/display: Prepare for dsc 3 stream splitter
  drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine
  drm/i915/vdsc: Introduce 3rd VDSC engine VDSC2
  drm/i915/vdsc: Add support for read/write PPS for 3rd DSC engine
  drm/i915/dp: Ensure hactive is divisible by slice count
  drm/i915/dp: Enable 3 DSC engines for 12 slices

 drivers/gpu/drm/i915/display/icl_dsi.c        |  4 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
 .../drm/i915/display/intel_display_types.h    |  2 +-
 drivers/gpu/drm/i915/display/intel_dp.c       | 36 +++++++++++++++---
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 38 +++++++++++++------
 .../gpu/drm/i915/display/intel_vdsc_regs.h    | 12 +++++-
 6 files changed, 73 insertions(+), 21 deletions(-)

-- 
2.45.2


^ permalink raw reply	[flat|nested] 19+ messages in thread
* [PATCH 0/7] Add support for 3 VDSC engines 12 slices
@ 2024-10-30  4:10 Ankit Nautiyal
  0 siblings, 0 replies; 19+ messages in thread
From: Ankit Nautiyal @ 2024-10-30  4:10 UTC (permalink / raw)
  To: intel-gfx; +Cc: intel-xe, suraj.kandpal

For BMG 3 VDSC engines are supported and each pipe can then support
3 slices. For Ultra joiner cases for modes like 8k@120 Hz we require
ultrajoiner and 3 x 4= 12 slices.
Add support for 3 VDSC engines and 12 DSC slices.

Rev2: Rebase
Rev3:
-Add patch to account for pixel replication in pipe_src.
-Fix kernel test bot warning.
-Minor refactoring.
Rev4:
-Address review comments from last version.
-Add BW consideration with pixel replication
-Split Odd pixel handling in separate patches.
Rev 5:
-Use num_streams instead of dsc_split.
Rev 6:
-Drop patches for pixel replication and odd pixel removal.
Rev 7:
-Fix Hw readout for DSC in Patch#2, and rebase.

Ankit Nautiyal (7):
  drm/i915/dp: Update Comment for Valid DSC Slices per Line
  drm/i915/display: Prepare for dsc 3 stream splitter
  drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine
  drm/i915/vdsc: Introduce 3rd VDSC engine VDSC2
  drm/i915/vdsc: Add support for read/write PPS for 3rd DSC engine
  drm/i915/dp: Ensure hactive is divisible by slice count
  drm/i915/dp: Enable 3 DSC engines for 12 slices

 drivers/gpu/drm/i915/display/icl_dsi.c        |  4 ++-
 drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
 .../drm/i915/display/intel_display_types.h    |  2 +-
 drivers/gpu/drm/i915/display/intel_dp.c       | 36 ++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 34 ++++++++++++------
 .../gpu/drm/i915/display/intel_vdsc_regs.h    | 12 +++++--
 6 files changed, 69 insertions(+), 21 deletions(-)

-- 
2.45.2


^ permalink raw reply	[flat|nested] 19+ messages in thread

end of thread, other threads:[~2024-11-06 13:01 UTC | newest]

Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-10-27 13:45 [PATCH 0/7] Add support for 3 VDSC engines 12 slices Ankit Nautiyal
2024-10-27 13:45 ` [PATCH 1/7] drm/i915/dp: Update Comment for Valid DSC Slices per Line Ankit Nautiyal
2024-10-27 13:45 ` [PATCH 2/7] drm/i915/display: Prepare for dsc 3 stream splitter Ankit Nautiyal
2024-10-28  4:26   ` Nautiyal, Ankit K
2024-10-27 13:45 ` [PATCH 3/7] drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine Ankit Nautiyal
2024-10-27 13:45 ` [PATCH 4/7] drm/i915/vdsc: Introduce 3rd VDSC engine VDSC2 Ankit Nautiyal
2024-10-27 13:45 ` [PATCH 5/7] drm/i915/vdsc: Add support for read/write PPS for 3rd DSC engine Ankit Nautiyal
2024-10-27 13:45 ` [PATCH 6/7] drm/i915/dp: Ensure hactive is divisible by slice count Ankit Nautiyal
2024-10-27 13:45 ` [PATCH 7/7] drm/i915/dp: Enable 3 DSC engines for 12 slices Ankit Nautiyal
2024-10-27 13:49 ` ✓ CI.Patch_applied: success for Add support for 3 VDSC engines 12 slices (rev6) Patchwork
2024-10-27 13:49 ` ✓ CI.checkpatch: " Patchwork
2024-10-27 13:50 ` ✓ CI.KUnit: " Patchwork
2024-10-27 14:02 ` ✓ CI.Build: " Patchwork
2024-10-27 14:04 ` ✓ CI.Hooks: " Patchwork
2024-10-27 14:06 ` ✗ CI.checksparse: warning " Patchwork
2024-10-27 14:40 ` ✗ CI.BAT: failure " Patchwork
2024-10-27 18:20 ` ✗ CI.FULL: " Patchwork
2024-11-06 13:00 ` [PATCH 0/7] Add support for 3 VDSC engines 12 slices Nautiyal, Ankit K
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2024-10-30  4:10 Ankit Nautiyal

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