Re: [PATCH] drm/xe: derive mem copy capability from graphics version

[Matthew Auld <matthew.auld@intel.com>]

On 19/01/2026 12:18, Nitin Gote wrote:
> Drop .has_mem_copy_instr from the platform descriptors and compute
> it in xe_info_init() once handle_gmdid() populates graphics_verx100.
> Early init was running with graphics_verx100==0, so the old placement
> silently disabled MEM_COPY on every GMDID platform. Centralizing the
> GRAPHICS_VER(xe) >= 20 || platform == XE_PVC check keeps Xe2+/PVC enabled
> and removes redundant per-platform plumbing for future Xe platforms.

PVC had a slightly different instruction layout for this IIRC, which is 
why I kept it to xe2+. I doubt it is worth the effort, but if you want 
to add support for PVC I think best keep as a separate patch (need to 
also change the instruction emit part).

> 
> Bspec: 57561
> 
> Fixes: 1e12dbae9d72 ("drm/xe/migrate: support MEM_COPY instruction")
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Suggested-by: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_pci.c       | 7 ++-----
>   drivers/gpu/drm/xe/xe_pci_types.h | 1 -
>   2 files changed, 2 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 34df063024fe..b41e3afc0431 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -350,7 +350,6 @@ static const struct xe_device_desc lnl_desc = {
>   	.has_display = true,
>   	.has_flat_ccs = 1,
>   	.has_pxp = true,
> -	.has_mem_copy_instr = true,
>   	.max_gt_per_tile = 2,
>   	.needs_scratch = true,
>   	.va_bits = 48,
> @@ -375,7 +374,6 @@ static const struct xe_device_desc bmg_desc = {
>   	.has_pre_prod_wa = 1,
>   	.has_soc_remapper_telem = true,
>   	.has_sriov = true,
> -	.has_mem_copy_instr = true,
>   	.max_gt_per_tile = 2,
>   	.needs_scratch = true,
>   	.subplatforms = (const struct xe_subplatform_desc[]) {
> @@ -392,7 +390,6 @@ static const struct xe_device_desc ptl_desc = {
>   	.has_display = true,
>   	.has_flat_ccs = 1,
>   	.has_sriov = true,
> -	.has_mem_copy_instr = true,
>   	.has_pre_prod_wa = 1,
>   	.has_pxp = true,
>   	.max_gt_per_tile = 2,
> @@ -407,7 +404,6 @@ static const struct xe_device_desc nvls_desc = {
>   	.dma_mask_size = 46,
>   	.has_display = true,
>   	.has_flat_ccs = 1,
> -	.has_mem_copy_instr = true,
>   	.has_pre_prod_wa = 1,
>   	.max_gt_per_tile = 2,
>   	.require_force_probe = true,
> @@ -706,7 +702,6 @@ static int xe_info_init_early(struct xe_device *xe,
>   	xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem;
>   	xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) &&
>   		desc->has_sriov;
> -	xe->info.has_mem_copy_instr = desc->has_mem_copy_instr;
>   	xe->info.skip_guc_pc = desc->skip_guc_pc;
>   	xe->info.skip_mtcfg = desc->skip_mtcfg;
>   	xe->info.skip_pcode = desc->skip_pcode;
> @@ -897,6 +892,8 @@ static int xe_info_init(struct xe_device *xe,
>   	xe->info.has_ctx_tlb_inval = graphics_desc->has_ctx_tlb_inval;
>   	xe->info.has_usm = graphics_desc->has_usm;
>   	xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp;
> +	xe->info.has_mem_copy_instr = GRAPHICS_VER(xe) >= 20 ||
> +				      xe->info.platform == XE_PVC;
>   
>   	xe_info_probe_tile_count(xe);
>   
> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> index 7ccb0ab7a53b..8b2ff3f25607 100644
> --- a/drivers/gpu/drm/xe/xe_pci_types.h
> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> @@ -49,7 +49,6 @@ struct xe_device_desc {
>   	u8 has_llc:1;
>   	u8 has_mbx_power_limits:1;
>   	u8 has_mbx_thermal_info:1;
> -	u8 has_mem_copy_instr:1;
>   	u8 has_mert:1;
>   	u8 has_pre_prod_wa:1;
>   	u8 has_page_reclaim_hw_assist:1;