[PATCH v4 0/8] drm/i915: add display irq hooks

[PATCH v4 0/8] drm/i915: add display irq hooks

[Jani Nikula]

v4 of [1], splitting patches 5-6 into two, resulting in patches 5-8
here. There's no diff between the end results of v3 and v4, just the
intermediate steps are there.

BR,
Jani.

[1] https://lore.kernel.org/r/cover.1778666967.git.jani.nikula@intel.com

Jani Nikula (8):
  drm/i915/irq: deduplicate dg1_de_irq_postinstall() and
    gen11_de_irq_postinstall()
  drm/i915/irq: constify pipe stats parameters
  drm/i915/irq: add display irq funcs, start with
    intel_display_irq_reset()
  drm/i915/irq: add intel_display_irq_postinstall() to irq funcs
  drm/i915/irq: add platform specific display irq ack functions
  drm/i915/irq: add platform specific display irq handler functions
  drm/i915/irq: add intel_display_irq_ack() to irq funcs
  drm/i915/irq: add intel_display_irq_handler() to irq funcs

 .../gpu/drm/i915/display/intel_display_core.h |   3 +
 .../gpu/drm/i915/display/intel_display_irq.c  | 238 +++++++++++++++---
 .../gpu/drm/i915/display/intel_display_irq.h  |  37 +--
 drivers/gpu/drm/i915/i915_irq.c               | 182 +++++---------
 drivers/gpu/drm/xe/display/xe_display.c       |   6 +-
 5 files changed, 277 insertions(+), 189 deletions(-)

-- 
2.47.3

[PATCH v4 1/8] drm/i915/irq: deduplicate dg1_de_irq_postinstall() and gen11_de_irq_postinstall()

[Jani Nikula]

dg1_de_irq_postinstall() and gen11_de_irq_postinstall() are exactly the
same. Remove dg1_de_irq_postinstall() and call
gen11_de_irq_postinstall() instead.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_irq.c | 9 ---------
 drivers/gpu/drm/i915/display/intel_display_irq.h | 1 -
 drivers/gpu/drm/i915/i915_irq.c                  | 2 +-
 3 files changed, 1 insertion(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 27fb72e5cefb..a1dbf20c2e02 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -2449,15 +2449,6 @@ void gen11_de_irq_postinstall(struct intel_display *display)
 	intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
 }
 
-void dg1_de_irq_postinstall(struct intel_display *display)
-{
-	if (!HAS_DISPLAY(display))
-		return;
-
-	gen8_de_irq_postinstall(display);
-	intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
-}
-
 struct intel_display_irq_funcs {
 	void (*reset)(struct intel_display *display);
 };
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index b25d180254d7..e2b1674fae06 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -71,7 +71,6 @@ void vlv_display_irq_postinstall(struct intel_display *display);
 void ilk_de_irq_postinstall(struct intel_display *display);
 void gen8_de_irq_postinstall(struct intel_display *display);
 void gen11_de_irq_postinstall(struct intel_display *display);
-void dg1_de_irq_postinstall(struct intel_display *display);
 
 u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
 void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d4d8dd0a4174..ef9eadf38a53 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -778,7 +778,7 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
 
-	dg1_de_irq_postinstall(display);
+	gen11_de_irq_postinstall(display);
 
 	dg1_master_intr_enable(intel_uncore_regs(uncore));
 	intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
-- 
2.47.3

[PATCH v4 2/8] drm/i915/irq: constify pipe stats parameters

[Jani Nikula]

The pipe stat irq handling doesn't need to modify the pipe stats
arrays. Make them const.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_irq.c | 6 +++---
 drivers/gpu/drm/i915/display/intel_display_irq.h | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index a1dbf20c2e02..c656d59c7571 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -597,7 +597,7 @@ void i9xx_pipestat_irq_ack(struct intel_display *display,
 }
 
 void i915_pipestat_irq_handler(struct intel_display *display,
-			       u32 iir, u32 pipe_stats[I915_MAX_PIPES])
+			       u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
 {
 	bool blc_event = false;
 	enum pipe pipe;
@@ -621,7 +621,7 @@ void i915_pipestat_irq_handler(struct intel_display *display,
 }
 
 void i965_pipestat_irq_handler(struct intel_display *display,
-			       u32 iir, u32 pipe_stats[I915_MAX_PIPES])
+			       u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
 {
 	bool blc_event = false;
 	enum pipe pipe;
@@ -648,7 +648,7 @@ void i965_pipestat_irq_handler(struct intel_display *display,
 }
 
 void valleyview_pipestat_irq_handler(struct intel_display *display,
-				     u32 pipe_stats[I915_MAX_PIPES])
+				     const u32 pipe_stats[I915_MAX_PIPES])
 {
 	enum pipe pipe;
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index e2b1674fae06..d25b9ea4272b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -78,9 +78,9 @@ void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 st
 
 void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
 
-void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
-void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
-void valleyview_pipestat_irq_handler(struct intel_display *display, u32 pipe_stats[I915_MAX_PIPES]);
+void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
+void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
+void valleyview_pipestat_irq_handler(struct intel_display *display, const u32 pipe_stats[I915_MAX_PIPES]);
 
 void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt);
 void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);
-- 
2.47.3

[PATCH v4 3/8] drm/i915/irq: add display irq funcs, start with intel_display_irq_reset()

[Jani Nikula]

Introduce display irq hooks with struct intel_display_irq_funcs, and add
the ->reset hook as the first thing. Call the reset hooks from i915 and
xe core via intel_display_irq_reset().

Relocate the gen8 and gen11 HAS_DISPLAY() check to
intel_display_irq_reset(), as the funcs pointer won't be initialized for
no display.

Note: We're increasingly moving to the territory of not touching display
at all if there's no display or it has been fused off. Which is good,
but care must be taken to not have hardware setup required also for no
display cases in display code. Also note that the line is fuzzy for
older platforms, but there we also don't have fusing.

v2:
- make the structs static const (Sashiko)
- relocate HAS_DISPLAY() (Sashiko)

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/display/intel_display_core.h |  3 +
 .../gpu/drm/i915/display/intel_display_irq.c  | 61 +++++++++++++++----
 .../gpu/drm/i915/display/intel_display_irq.h  |  6 +-
 drivers/gpu/drm/i915/i915_irq.c               | 16 ++---
 drivers/gpu/drm/xe/display/xe_display.c       |  2 +-
 5 files changed, 63 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 76745ce6a716..3dc5ac75a98b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -475,6 +475,9 @@ struct intel_display {
 	} ips;
 
 	struct {
+		/* internal display irq functions */
+		const struct intel_display_irq_funcs *funcs;
+
 		/* protects the irq masks */
 		spinlock_t lock;
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index c656d59c7571..27599a303843 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1947,7 +1947,7 @@ static void _vlv_display_irq_reset(struct intel_display *display)
 	display->irq.vlv_imr_mask = ~0u;
 }
 
-void vlv_display_irq_reset(struct intel_display *display)
+static void vlv_display_irq_reset(struct intel_display *display)
 {
 	spin_lock_irq(&display->irq.lock);
 	if (display->irq.vlv_display_irqs_enabled)
@@ -1955,7 +1955,7 @@ void vlv_display_irq_reset(struct intel_display *display)
 	spin_unlock_irq(&display->irq.lock);
 }
 
-void i9xx_display_irq_reset(struct intel_display *display)
+static void i9xx_display_irq_reset(struct intel_display *display)
 {
 	if (HAS_HOTPLUG(display)) {
 		i915_hotplug_interrupt_update(display, 0xffffffff, 0);
@@ -2076,7 +2076,7 @@ static void ibx_display_irq_reset(struct intel_display *display)
 		intel_de_write(display, SERR_INT, 0xffffffff);
 }
 
-void ilk_display_irq_reset(struct intel_display *display)
+static void ilk_display_irq_reset(struct intel_display *display)
 {
 	irq_reset(display, DE_IRQ_REGS);
 	display->irq.ilk_de_imr_mask = ~0u;
@@ -2092,13 +2092,10 @@ void ilk_display_irq_reset(struct intel_display *display)
 	ibx_display_irq_reset(display);
 }
 
-void gen8_display_irq_reset(struct intel_display *display)
+static void gen8_display_irq_reset(struct intel_display *display)
 {
 	enum pipe pipe;
 
-	if (!HAS_DISPLAY(display))
-		return;
-
 	intel_de_write(display, EDP_PSR_IMR, 0xffffffff);
 	intel_de_write(display, EDP_PSR_IIR, 0xffffffff);
 
@@ -2114,15 +2111,12 @@ void gen8_display_irq_reset(struct intel_display *display)
 		ibx_display_irq_reset(display);
 }
 
-void gen11_display_irq_reset(struct intel_display *display)
+static void gen11_display_irq_reset(struct intel_display *display)
 {
 	enum pipe pipe;
 	u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 		BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
 
-	if (!HAS_DISPLAY(display))
-		return;
-
 	intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0);
 
 	if (DISPLAY_VER(display) >= 12) {
@@ -2453,6 +2447,38 @@ struct intel_display_irq_funcs {
 	void (*reset)(struct intel_display *display);
 };
 
+static const struct intel_display_irq_funcs gen11_display_irq_funcs = {
+	.reset = gen11_display_irq_reset,
+};
+
+static const struct intel_display_irq_funcs gen8_display_irq_funcs = {
+	.reset = gen8_display_irq_reset,
+};
+
+static const struct intel_display_irq_funcs vlv_display_irq_funcs = {
+	.reset = vlv_display_irq_reset,
+};
+
+static const struct intel_display_irq_funcs ilk_display_irq_funcs = {
+	.reset = ilk_display_irq_reset,
+};
+
+static const struct intel_display_irq_funcs i965_display_irq_funcs = {
+	.reset = i9xx_display_irq_reset,
+};
+
+static const struct intel_display_irq_funcs i915_display_irq_funcs = {
+	.reset = i9xx_display_irq_reset,
+};
+
+void intel_display_irq_reset(struct intel_display *display)
+{
+	if (!HAS_DISPLAY(display))
+		return;
+
+	display->irq.funcs->reset(display);
+}
+
 void intel_display_irq_init(struct intel_display *display)
 {
 	spin_lock_init(&display->irq.lock);
@@ -2463,6 +2489,19 @@ void intel_display_irq_init(struct intel_display *display)
 
 	INIT_WORK(&display->irq.vblank_notify_work,
 		  intel_display_vblank_notify_work);
+
+	if (DISPLAY_VER(display) >= 11)
+		display->irq.funcs = &gen11_display_irq_funcs;
+	else if (display->platform.cherryview || display->platform.valleyview)
+		display->irq.funcs = &vlv_display_irq_funcs;
+	else if (DISPLAY_VER(display) >= 8)
+		display->irq.funcs = &gen8_display_irq_funcs;
+	else if (DISPLAY_VER(display) >= 5)
+		display->irq.funcs = &ilk_display_irq_funcs;
+	else if (DISPLAY_VER(display) == 4)
+		display->irq.funcs = &i965_display_irq_funcs;
+	else
+		display->irq.funcs = &i915_display_irq_funcs;
 }
 
 struct intel_display_irq_snapshot {
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index d25b9ea4272b..21b2145656cd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -58,11 +58,7 @@ void gen11_display_irq_handler(struct intel_display *display);
 u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
 void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
 
-void i9xx_display_irq_reset(struct intel_display *display);
-void ilk_display_irq_reset(struct intel_display *display);
-void vlv_display_irq_reset(struct intel_display *display);
-void gen8_display_irq_reset(struct intel_display *display);
-void gen11_display_irq_reset(struct intel_display *display);
+void intel_display_irq_reset(struct intel_display *display);
 
 u32 i9xx_display_irq_enable_mask(struct intel_display *display);
 void i915_display_irq_postinstall(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ef9eadf38a53..c4f56a869910 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -640,7 +640,7 @@ static void ilk_irq_reset(struct drm_i915_private *dev_priv)
 	struct intel_display *display = dev_priv->display;
 
 	/* The master interrupt enable is in DEIER, reset display irq first */
-	ilk_display_irq_reset(display);
+	intel_display_irq_reset(display);
 	gen5_gt_irq_reset(to_gt(dev_priv));
 }
 
@@ -653,7 +653,7 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
 
 	gen5_gt_irq_reset(to_gt(dev_priv));
 
-	vlv_display_irq_reset(display);
+	intel_display_irq_reset(display);
 }
 
 static void gen8_irq_reset(struct drm_i915_private *dev_priv)
@@ -664,7 +664,7 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
 	gen8_master_intr_disable(intel_uncore_regs(uncore));
 
 	gen8_gt_irq_reset(to_gt(dev_priv));
-	gen8_display_irq_reset(display);
+	intel_display_irq_reset(display);
 	gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
 }
 
@@ -677,7 +677,7 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv)
 	gen11_master_intr_disable(intel_uncore_regs(&dev_priv->uncore));
 
 	gen11_gt_irq_reset(gt);
-	gen11_display_irq_reset(display);
+	intel_display_irq_reset(display);
 
 	gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
 	gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
@@ -695,7 +695,7 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv)
 	for_each_gt(gt, dev_priv, i)
 		gen11_gt_irq_reset(gt);
 
-	gen11_display_irq_reset(display);
+	intel_display_irq_reset(display);
 
 	gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
 	gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
@@ -715,7 +715,7 @@ static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
 
 	gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
 
-	vlv_display_irq_reset(display);
+	intel_display_irq_reset(display);
 }
 
 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -864,7 +864,7 @@ static void i915_irq_reset(struct drm_i915_private *dev_priv)
 	struct intel_display *display = dev_priv->display;
 	struct intel_uncore *uncore = &dev_priv->uncore;
 
-	i9xx_display_irq_reset(display);
+	intel_display_irq_reset(display);
 
 	gen2_error_reset(uncore, GEN2_ERROR_REGS);
 	gen2_irq_reset(uncore, GEN2_IRQ_REGS);
@@ -951,7 +951,7 @@ static void i965_irq_reset(struct drm_i915_private *dev_priv)
 	struct intel_display *display = dev_priv->display;
 	struct intel_uncore *uncore = &dev_priv->uncore;
 
-	i9xx_display_irq_reset(display);
+	intel_display_irq_reset(display);
 
 	gen2_error_reset(uncore, GEN2_ERROR_REGS);
 	gen2_irq_reset(uncore, GEN2_IRQ_REGS);
diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index aa73023b7398..ba3225878c61 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -236,7 +236,7 @@ void xe_display_irq_reset(struct xe_device *xe)
 	if (!xe->info.probe_display)
 		return;
 
-	gen11_display_irq_reset(display);
+	intel_display_irq_reset(display);
 }
 
 void xe_display_irq_postinstall(struct xe_device *xe)
-- 
2.47.3

[PATCH v4 4/8] drm/i915/irq: add intel_display_irq_postinstall() to irq funcs

[Jani Nikula]

Call the platform specific display irq postinstall hooks via
intel_display_irq_postinstall().

Relocate the gen11 HAS_DISPLAY() check to
intel_display_irq_postinstall(), as the funcs pointer won't be
initialized for no display.

v2:
- relocate HAS_DISPLAY() (Sashiko)

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/display/intel_display_irq.c  | 30 +++++++++++++------
 .../gpu/drm/i915/display/intel_display_irq.h  |  7 +----
 drivers/gpu/drm/i915/i915_irq.c               | 16 +++++-----
 drivers/gpu/drm/xe/display/xe_display.c       |  2 +-
 4 files changed, 31 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 27599a303843..9d6596ad8b3b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1981,7 +1981,7 @@ u32 i9xx_display_irq_enable_mask(struct intel_display *display)
 	return enable_mask;
 }
 
-void i915_display_irq_postinstall(struct intel_display *display)
+static void i915_display_irq_postinstall(struct intel_display *display)
 {
 	/*
 	 * Interrupt setup is already guaranteed to be single-threaded, this is
@@ -1995,7 +1995,7 @@ void i915_display_irq_postinstall(struct intel_display *display)
 	i915_enable_asle_pipestat(display);
 }
 
-void i965_display_irq_postinstall(struct intel_display *display)
+static void i965_display_irq_postinstall(struct intel_display *display)
 {
 	/*
 	 * Interrupt setup is already guaranteed to be single-threaded, this is
@@ -2057,7 +2057,7 @@ static void _vlv_display_irq_postinstall(struct intel_display *display)
 	irq_init(display, VLV_IRQ_REGS, display->irq.vlv_imr_mask, enable_mask);
 }
 
-void vlv_display_irq_postinstall(struct intel_display *display)
+static void vlv_display_irq_postinstall(struct intel_display *display)
 {
 	spin_lock_irq(&display->irq.lock);
 	if (display->irq.vlv_display_irqs_enabled)
@@ -2262,7 +2262,7 @@ void valleyview_disable_display_irqs(struct intel_display *display)
 	spin_unlock_irq(&display->irq.lock);
 }
 
-void ilk_de_irq_postinstall(struct intel_display *display)
+static void ilk_de_irq_postinstall(struct intel_display *display)
 {
 	u32 display_mask, extra_mask;
 
@@ -2306,7 +2306,7 @@ void ilk_de_irq_postinstall(struct intel_display *display)
 static void mtp_irq_postinstall(struct intel_display *display);
 static void icp_irq_postinstall(struct intel_display *display);
 
-void gen8_de_irq_postinstall(struct intel_display *display)
+static void gen8_de_irq_postinstall(struct intel_display *display)
 {
 	u32 de_pipe_masked = gen8_de_pipe_fault_mask(display) |
 		GEN8_PIPE_CDCLK_CRC_DONE;
@@ -2433,11 +2433,8 @@ static void icp_irq_postinstall(struct intel_display *display)
 	irq_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);
 }
 
-void gen11_de_irq_postinstall(struct intel_display *display)
+static void gen11_de_irq_postinstall(struct intel_display *display)
 {
-	if (!HAS_DISPLAY(display))
-		return;
-
 	gen8_de_irq_postinstall(display);
 
 	intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
@@ -2445,30 +2442,37 @@ void gen11_de_irq_postinstall(struct intel_display *display)
 
 struct intel_display_irq_funcs {
 	void (*reset)(struct intel_display *display);
+	void (*postinstall)(struct intel_display *display);
 };
 
 static const struct intel_display_irq_funcs gen11_display_irq_funcs = {
 	.reset = gen11_display_irq_reset,
+	.postinstall = gen11_de_irq_postinstall,
 };
 
 static const struct intel_display_irq_funcs gen8_display_irq_funcs = {
 	.reset = gen8_display_irq_reset,
+	.postinstall = gen8_de_irq_postinstall,
 };
 
 static const struct intel_display_irq_funcs vlv_display_irq_funcs = {
 	.reset = vlv_display_irq_reset,
+	.postinstall = vlv_display_irq_postinstall,
 };
 
 static const struct intel_display_irq_funcs ilk_display_irq_funcs = {
 	.reset = ilk_display_irq_reset,
+	.postinstall = ilk_de_irq_postinstall,
 };
 
 static const struct intel_display_irq_funcs i965_display_irq_funcs = {
 	.reset = i9xx_display_irq_reset,
+	.postinstall = i965_display_irq_postinstall,
 };
 
 static const struct intel_display_irq_funcs i915_display_irq_funcs = {
 	.reset = i9xx_display_irq_reset,
+	.postinstall = i915_display_irq_postinstall,
 };
 
 void intel_display_irq_reset(struct intel_display *display)
@@ -2479,6 +2483,14 @@ void intel_display_irq_reset(struct intel_display *display)
 	display->irq.funcs->reset(display);
 }
 
+void intel_display_irq_postinstall(struct intel_display *display)
+{
+	if (!HAS_DISPLAY(display))
+		return;
+
+	display->irq.funcs->postinstall(display);
+}
+
 void intel_display_irq_init(struct intel_display *display)
 {
 	spin_lock_init(&display->irq.lock);
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index 21b2145656cd..fd9873ce9755 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -59,14 +59,9 @@ u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
 void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
 
 void intel_display_irq_reset(struct intel_display *display);
+void intel_display_irq_postinstall(struct intel_display *display);
 
 u32 i9xx_display_irq_enable_mask(struct intel_display *display);
-void i915_display_irq_postinstall(struct intel_display *display);
-void i965_display_irq_postinstall(struct intel_display *display);
-void vlv_display_irq_postinstall(struct intel_display *display);
-void ilk_de_irq_postinstall(struct intel_display *display);
-void gen8_de_irq_postinstall(struct intel_display *display);
-void gen11_de_irq_postinstall(struct intel_display *display);
 
 u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
 void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c4f56a869910..c21b289b8007 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -724,7 +724,7 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen5_gt_irq_postinstall(to_gt(dev_priv));
 
-	ilk_de_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 }
 
 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -733,7 +733,7 @@ static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen5_gt_irq_postinstall(to_gt(dev_priv));
 
-	vlv_display_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 
 	intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
 	intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
@@ -744,7 +744,7 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
 	struct intel_display *display = dev_priv->display;
 
 	gen8_gt_irq_postinstall(to_gt(dev_priv));
-	gen8_de_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 
 	gen8_master_intr_enable(intel_uncore_regs(&dev_priv->uncore));
 }
@@ -757,7 +757,7 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
 	u32 gu_misc_masked = GEN11_GU_MISC_GSE;
 
 	gen11_gt_irq_postinstall(gt);
-	gen11_de_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 
 	gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
 
@@ -778,7 +778,7 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
 
-	gen11_de_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 
 	dg1_master_intr_enable(intel_uncore_regs(uncore));
 	intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
@@ -790,7 +790,7 @@ static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen8_gt_irq_postinstall(to_gt(dev_priv));
 
-	vlv_display_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 
 	intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
 	intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
@@ -888,7 +888,7 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->gen2_imr_mask, enable_mask);
 
-	i915_display_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 }
 
 static irqreturn_t i915_irq_handler(int irq, void *arg)
@@ -997,7 +997,7 @@ static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->gen2_imr_mask, enable_mask);
 
-	i965_display_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 }
 
 static irqreturn_t i965_irq_handler(int irq, void *arg)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index ba3225878c61..62e5d38938eb 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -246,7 +246,7 @@ void xe_display_irq_postinstall(struct xe_device *xe)
 	if (!xe->info.probe_display)
 		return;
 
-	gen11_de_irq_postinstall(display);
+	intel_display_irq_postinstall(display);
 }
 
 static bool suspend_to_idle(void)
-- 
2.47.3

[PATCH v4 5/8] drm/i915/irq: add platform specific display irq ack functions

[Jani Nikula]

Add i9xx_display_irq_ack() and vlv_display_irq_ack() to group together
the various irq ack parts for the platforms, to declutter the core i915
irq code from the details.

Introduce struct intel_display_irq_state to group together all the data
the ack functions need. In the follow-up, this state will be passed on
to similar platform specific handler functions.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/display/intel_display_irq.c  |  45 +++++-
 .../gpu/drm/i915/display/intel_display_irq.h  |  14 +-
 drivers/gpu/drm/i915/i915_irq.c               | 144 ++++++------------
 3 files changed, 102 insertions(+), 101 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 9d6596ad8b3b..5eefb7e093c4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -23,6 +23,7 @@
 #include "intel_fifo_underrun.h"
 #include "intel_gmbus.h"
 #include "intel_hotplug_irq.h"
+#include "intel_lpe_audio.h"
 #include "intel_parent.h"
 #include "intel_pipe_crc_regs.h"
 #include "intel_plane.h"
@@ -529,8 +530,8 @@ static void i9xx_pipestat_irq_reset(struct intel_display *display)
 	}
 }
 
-void i9xx_pipestat_irq_ack(struct intel_display *display,
-			   u32 iir, u32 pipe_stats[I915_MAX_PIPES])
+static void i9xx_pipestat_irq_ack(struct intel_display *display,
+				  u32 iir, u32 pipe_stats[I915_MAX_PIPES])
 {
 	enum pipe pipe;
 
@@ -1898,8 +1899,8 @@ static void vlv_page_table_error_irq_handler(struct intel_display *display, u32
 	}
 }
 
-void vlv_display_error_irq_ack(struct intel_display *display,
-			       u32 *eir, u32 *dpinvgtt)
+static void vlv_display_error_irq_ack(struct intel_display *display,
+				      u32 *eir, u32 *dpinvgtt)
 {
 	u32 emr;
 
@@ -2010,6 +2011,16 @@ static void i965_display_irq_postinstall(struct intel_display *display)
 	i915_enable_asle_pipestat(display);
 }
 
+void i9xx_display_irq_ack(struct intel_display *display,
+			  struct intel_display_irq_state *state)
+{
+	if (state->iir & I915_DISPLAY_PORT_INTERRUPT)
+		state->hotplug_status = i9xx_hpd_irq_ack(display);
+
+	/* Call regardless, as some status bits might not be signalled in IIR */
+	i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
+}
+
 static u32 vlv_error_mask(void)
 {
 	/* TODO enable other errors too? */
@@ -2065,6 +2076,32 @@ static void vlv_display_irq_postinstall(struct intel_display *display)
 	spin_unlock_irq(&display->irq.lock);
 }
 
+static u32 vlv_lpe_irq_mask(struct intel_display *display)
+{
+	if (display->platform.cherryview)
+		return I915_LPE_PIPE_A_INTERRUPT | I915_LPE_PIPE_B_INTERRUPT |
+			I915_LPE_PIPE_C_INTERRUPT;
+	else
+		return I915_LPE_PIPE_A_INTERRUPT | I915_LPE_PIPE_B_INTERRUPT;
+}
+
+void vlv_display_irq_ack(struct intel_display *display,
+			 struct intel_display_irq_state *state)
+{
+	if (state->iir & I915_DISPLAY_PORT_INTERRUPT)
+		state->hotplug_status = i9xx_hpd_irq_ack(display);
+
+	if (state->iir & I915_MASTER_ERROR_INTERRUPT)
+		vlv_display_error_irq_ack(display, &state->eir, &state->dpinvgtt);
+
+	/* Call regardless, as some status bits might not be signalled in IIR */
+	i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
+
+	/* The handler acks the irq, so need to call the handler here */
+	if (state->iir & vlv_lpe_irq_mask(display))
+		intel_lpe_audio_irq_handler(display);
+}
+
 static void ibx_display_irq_reset(struct intel_display *display)
 {
 	if (HAS_PCH_NOP(display))
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index fd9873ce9755..8d4ea53bb9db 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -58,22 +58,30 @@ void gen11_display_irq_handler(struct intel_display *display);
 u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
 void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
 
+struct intel_display_irq_state {
+	u32 iir;
+	u32 eir;
+	u32 hotplug_status;
+	u32 dpinvgtt;
+	u32 pipe_stats[I915_MAX_PIPES];
+};
+
 void intel_display_irq_reset(struct intel_display *display);
 void intel_display_irq_postinstall(struct intel_display *display);
 
+void vlv_display_irq_ack(struct intel_display *display, struct intel_display_irq_state *state);
+void i9xx_display_irq_ack(struct intel_display *display, struct intel_display_irq_state *state);
+
 u32 i9xx_display_irq_enable_mask(struct intel_display *display);
 
 u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
 void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
 void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
 
-void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
-
 void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
 void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
 void valleyview_pipestat_irq_handler(struct intel_display *display, const u32 pipe_stats[I915_MAX_PIPES]);
 
-void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt);
 void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);
 
 void intel_display_irq_init(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c21b289b8007..9022e32156a5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -39,7 +39,6 @@
 #include "display/intel_display_irq.h"
 #include "display/intel_hotplug.h"
 #include "display/intel_hotplug_irq.h"
-#include "display/intel_lpe_audio.h"
 
 #include "gt/intel_breadcrumbs.h"
 #include "gt/intel_gt.h"
@@ -236,17 +235,15 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 
 	do {
-		u32 iir, gt_iir, pm_iir;
-		u32 eir = 0, dpinvgtt = 0;
-		u32 pipe_stats[I915_MAX_PIPES] = {};
-		u32 hotplug_status = 0;
+		struct intel_display_irq_state state = {};
+		u32 gt_iir, pm_iir;
 		u32 ier = 0;
 
 		gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR);
 		pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR);
-		iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
+		state.iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
 
-		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
+		if (gt_iir == 0 && pm_iir == 0 && state.iir == 0)
 			break;
 
 		ret = IRQ_HANDLED;
@@ -272,26 +269,14 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 		if (pm_iir)
 			intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir);
 
-		if (iir & I915_DISPLAY_PORT_INTERRUPT)
-			hotplug_status = i9xx_hpd_irq_ack(display);
-
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
-			vlv_display_error_irq_ack(display, &eir, &dpinvgtt);
-
-		/* Call regardless, as some status bits might not be
-		 * signalled in IIR */
-		i9xx_pipestat_irq_ack(display, iir, pipe_stats);
-
-		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
-			   I915_LPE_PIPE_B_INTERRUPT))
-			intel_lpe_audio_irq_handler(display);
+		vlv_display_irq_ack(display, &state);
 
 		/*
 		 * VLV_IIR is single buffered, and reflects the level
 		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
 		 */
-		if (iir)
-			intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
+		if (state.iir)
+			intel_uncore_write(&dev_priv->uncore, VLV_IIR, state.iir);
 
 		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
 		intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
@@ -301,13 +286,13 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 		if (pm_iir)
 			gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir);
 
-		if (hotplug_status)
-			i9xx_hpd_irq_handler(display, hotplug_status);
+		if (state.hotplug_status)
+			i9xx_hpd_irq_handler(display, state.hotplug_status);
 
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
-			vlv_display_error_irq_handler(display, eir, dpinvgtt);
+		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
+			vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
 
-		valleyview_pipestat_irq_handler(display, pipe_stats);
+		valleyview_pipestat_irq_handler(display, state.pipe_stats);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, ret);
@@ -330,16 +315,14 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 
 	do {
-		u32 master_ctl, iir;
-		u32 eir = 0, dpinvgtt = 0;
-		u32 pipe_stats[I915_MAX_PIPES] = {};
-		u32 hotplug_status = 0;
+		struct intel_display_irq_state state = {};
+		u32 master_ctl;
 		u32 ier = 0;
 
 		master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
-		iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
+		state.iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
 
-		if (master_ctl == 0 && iir == 0)
+		if (master_ctl == 0 && state.iir == 0)
 			break;
 
 		ret = IRQ_HANDLED;
@@ -362,38 +345,25 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 
 		gen8_gt_irq_handler(to_gt(dev_priv), master_ctl);
 
-		if (iir & I915_DISPLAY_PORT_INTERRUPT)
-			hotplug_status = i9xx_hpd_irq_ack(display);
-
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
-			vlv_display_error_irq_ack(display, &eir, &dpinvgtt);
-
-		/* Call regardless, as some status bits might not be
-		 * signalled in IIR */
-		i9xx_pipestat_irq_ack(display, iir, pipe_stats);
-
-		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
-			   I915_LPE_PIPE_B_INTERRUPT |
-			   I915_LPE_PIPE_C_INTERRUPT))
-			intel_lpe_audio_irq_handler(display);
+		vlv_display_irq_ack(display, &state);
 
 		/*
 		 * VLV_IIR is single buffered, and reflects the level
 		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
 		 */
-		if (iir)
-			intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
+		if (state.iir)
+			intel_uncore_write(&dev_priv->uncore, VLV_IIR, state.iir);
 
 		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
 		intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
 
-		if (hotplug_status)
-			i9xx_hpd_irq_handler(display, hotplug_status);
+		if (state.hotplug_status)
+			i9xx_hpd_irq_handler(display, state.hotplug_status);
 
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
-			vlv_display_error_irq_handler(display, eir, dpinvgtt);
+		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
+			vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
 
-		valleyview_pipestat_irq_handler(display, pipe_stats);
+		valleyview_pipestat_irq_handler(display, state.pipe_stats);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, ret);
@@ -904,39 +874,32 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 
 	do {
-		u32 pipe_stats[I915_MAX_PIPES] = {};
+		struct intel_display_irq_state state = {};
 		u32 eir = 0, eir_stuck = 0;
-		u32 hotplug_status = 0;
-		u32 iir;
 
-		iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
-		if (iir == 0)
+		state.iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
+		if (state.iir == 0)
 			break;
 
 		ret = IRQ_HANDLED;
 
-		if (iir & I915_DISPLAY_PORT_INTERRUPT)
-			hotplug_status = i9xx_hpd_irq_ack(display);
+		i9xx_display_irq_ack(display, &state);
 
-		/* Call regardless, as some status bits might not be
-		 * signalled in IIR */
-		i9xx_pipestat_irq_ack(display, iir, pipe_stats);
-
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
+		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
 
-		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
+		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, state.iir);
 
-		if (iir & I915_USER_INTERRUPT)
-			intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir);
+		if (state.iir & I915_USER_INTERRUPT)
+			intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], state.iir);
 
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
+		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
 
-		if (hotplug_status)
-			i9xx_hpd_irq_handler(display, hotplug_status);
+		if (state.hotplug_status)
+			i9xx_hpd_irq_handler(display, state.hotplug_status);
 
-		i915_pipestat_irq_handler(display, iir, pipe_stats);
+		i915_pipestat_irq_handler(display, state.iir, state.pipe_stats);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, ret);
@@ -1013,44 +976,37 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 
 	do {
-		u32 pipe_stats[I915_MAX_PIPES] = {};
+		struct intel_display_irq_state state = {};
 		u32 eir = 0, eir_stuck = 0;
-		u32 hotplug_status = 0;
-		u32 iir;
 
-		iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
-		if (iir == 0)
+		state.iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
+		if (state.iir == 0)
 			break;
 
 		ret = IRQ_HANDLED;
 
-		if (iir & I915_DISPLAY_PORT_INTERRUPT)
-			hotplug_status = i9xx_hpd_irq_ack(display);
-
-		/* Call regardless, as some status bits might not be
-		 * signalled in IIR */
-		i9xx_pipestat_irq_ack(display, iir, pipe_stats);
+		i9xx_display_irq_ack(display, &state);
 
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
+		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
 
-		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
+		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, state.iir);
 
-		if (iir & I915_USER_INTERRUPT)
+		if (state.iir & I915_USER_INTERRUPT)
 			intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0],
-					    iir);
+					    state.iir);
 
-		if (iir & I915_BSD_USER_INTERRUPT)
+		if (state.iir & I915_BSD_USER_INTERRUPT)
 			intel_engine_cs_irq(to_gt(dev_priv)->engine[VCS0],
-					    iir >> 25);
+					    state.iir >> 25);
 
-		if (iir & I915_MASTER_ERROR_INTERRUPT)
+		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
 
-		if (hotplug_status)
-			i9xx_hpd_irq_handler(display, hotplug_status);
+		if (state.hotplug_status)
+			i9xx_hpd_irq_handler(display, state.hotplug_status);
 
-		i965_pipestat_irq_handler(display, iir, pipe_stats);
+		i965_pipestat_irq_handler(display, state.iir, state.pipe_stats);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, IRQ_HANDLED);
-- 
2.47.3

[PATCH v4 6/8] drm/i915/irq: add platform specific display irq handler functions

[Jani Nikula]

Add a number of *_display_irq_handler() functions to group together the
various display irq handler parts for the platforms, to declutter the
core i915 irq code from the details.

Add master_ctl to struct intel_display_irq_state, and pass the state
pointer to the handlers where necessary. The handler function signatures
are intentionally the same to allow for more refactoring.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/display/intel_display_irq.c  | 70 ++++++++++++++++---
 .../gpu/drm/i915/display/intel_display_irq.h  | 17 +++--
 drivers/gpu/drm/i915/i915_irq.c               | 38 +++-------
 drivers/gpu/drm/xe/display/xe_display.c       |  2 +-
 4 files changed, 79 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 5eefb7e093c4..672fd4f245ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -597,8 +597,8 @@ static void i9xx_pipestat_irq_ack(struct intel_display *display,
 	spin_unlock(&display->irq.lock);
 }
 
-void i915_pipestat_irq_handler(struct intel_display *display,
-			       u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
+static void i915_pipestat_irq_handler(struct intel_display *display,
+				      u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
 {
 	bool blc_event = false;
 	enum pipe pipe;
@@ -621,8 +621,8 @@ void i915_pipestat_irq_handler(struct intel_display *display,
 		intel_opregion_asle_intr(display);
 }
 
-void i965_pipestat_irq_handler(struct intel_display *display,
-			       u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
+static void i965_pipestat_irq_handler(struct intel_display *display,
+				      u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
 {
 	bool blc_event = false;
 	enum pipe pipe;
@@ -648,8 +648,8 @@ void i965_pipestat_irq_handler(struct intel_display *display,
 		intel_gmbus_irq_handler(display);
 }
 
-void valleyview_pipestat_irq_handler(struct intel_display *display,
-				     const u32 pipe_stats[I915_MAX_PIPES])
+static void valleyview_pipestat_irq_handler(struct intel_display *display,
+					    const u32 pipe_stats[I915_MAX_PIPES])
 {
 	enum pipe pipe;
 
@@ -1021,7 +1021,8 @@ void ilk_display_irq_master_enable(struct intel_display *display, u32 de_ier, u3
 		intel_de_write_fw(display, SDEIER, sde_ier);
 }
 
-bool ilk_display_irq_handler(struct intel_display *display)
+bool ilk_display_irq_handler(struct intel_display *display,
+			     const struct intel_display_irq_state *state)
 {
 	u32 de_iir;
 	bool handled = false;
@@ -1405,7 +1406,7 @@ static void gen8_read_and_ack_pch_irqs(struct intel_display *display, u32 *pch_i
 		intel_de_write(display, PICAINTERRUPT_IER, pica_ier);
 }
 
-void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
+static void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
 {
 	u32 iir;
 	enum pipe pipe;
@@ -1566,6 +1567,14 @@ void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
 	}
 }
 
+bool gen8_display_irq_handler(struct intel_display *display,
+			      const struct intel_display_irq_state *state)
+{
+	gen8_de_irq_handler(display, state->master_ctl);
+
+	return true;
+}
+
 u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl)
 {
 	u32 iir;
@@ -1590,7 +1599,8 @@ void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir)
 		intel_opregion_asle_intr(display);
 }
 
-void gen11_display_irq_handler(struct intel_display *display)
+bool gen11_display_irq_handler(struct intel_display *display,
+			       const struct intel_display_irq_state *state)
 {
 	u32 disp_ctl;
 
@@ -1606,6 +1616,8 @@ void gen11_display_irq_handler(struct intel_display *display)
 	intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
 
 	intel_display_rpm_assert_unblock(display);
+
+	return true;
 }
 
 static void i915gm_irq_cstate_wa_enable(struct intel_display *display)
@@ -1921,8 +1933,8 @@ static void vlv_display_error_irq_ack(struct intel_display *display,
 	intel_de_write(display, VLV_EMR, emr);
 }
 
-void vlv_display_error_irq_handler(struct intel_display *display,
-				   u32 eir, u32 dpinvgtt)
+static void vlv_display_error_irq_handler(struct intel_display *display,
+					  u32 eir, u32 dpinvgtt)
 {
 	drm_dbg(display->drm, "Master Error, EIR 0x%08x\n", eir);
 
@@ -2021,6 +2033,28 @@ void i9xx_display_irq_ack(struct intel_display *display,
 	i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
 }
 
+bool i965_display_irq_handler(struct intel_display *display,
+			      const struct intel_display_irq_state *state)
+{
+	if (state->hotplug_status)
+		i9xx_hpd_irq_handler(display, state->hotplug_status);
+
+	i965_pipestat_irq_handler(display, state->iir, state->pipe_stats);
+
+	return true;
+}
+
+bool i915_display_irq_handler(struct intel_display *display,
+			      const struct intel_display_irq_state *state)
+{
+	if (state->hotplug_status)
+		i9xx_hpd_irq_handler(display, state->hotplug_status);
+
+	i915_pipestat_irq_handler(display, state->iir, state->pipe_stats);
+
+	return true;
+}
+
 static u32 vlv_error_mask(void)
 {
 	/* TODO enable other errors too? */
@@ -2102,6 +2136,20 @@ void vlv_display_irq_ack(struct intel_display *display,
 		intel_lpe_audio_irq_handler(display);
 }
 
+bool vlv_display_irq_handler(struct intel_display *display,
+			     const struct intel_display_irq_state *state)
+{
+	if (state->hotplug_status)
+		i9xx_hpd_irq_handler(display, state->hotplug_status);
+
+	if (state->iir & I915_MASTER_ERROR_INTERRUPT)
+		vlv_display_error_irq_handler(display, state->eir, state->dpinvgtt);
+
+	valleyview_pipestat_irq_handler(display, state->pipe_stats);
+
+	return true;
+}
+
 static void ibx_display_irq_reset(struct intel_display *display)
 {
 	if (HAS_PCH_NOP(display))
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index 8d4ea53bb9db..59ec673ffc9b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -51,14 +51,12 @@ void bdw_disable_vblank(struct drm_crtc *crtc);
 
 void ilk_display_irq_master_disable(struct intel_display *display, u32 *de_ier, u32 *sde_ier);
 void ilk_display_irq_master_enable(struct intel_display *display, u32 de_ier, u32 sde_ier);
-bool ilk_display_irq_handler(struct intel_display *display);
-void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl);
-void gen11_display_irq_handler(struct intel_display *display);
 
 u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
 void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
 
 struct intel_display_irq_state {
+	u32 master_ctl;
 	u32 iir;
 	u32 eir;
 	u32 hotplug_status;
@@ -72,18 +70,19 @@ void intel_display_irq_postinstall(struct intel_display *display);
 void vlv_display_irq_ack(struct intel_display *display, struct intel_display_irq_state *state);
 void i9xx_display_irq_ack(struct intel_display *display, struct intel_display_irq_state *state);
 
+bool ilk_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);
+bool gen8_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);
+bool gen11_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);
+bool i965_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);
+bool i915_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);
+bool vlv_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);
+
 u32 i9xx_display_irq_enable_mask(struct intel_display *display);
 
 u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
 void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
 void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
 
-void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
-void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
-void valleyview_pipestat_irq_handler(struct intel_display *display, const u32 pipe_stats[I915_MAX_PIPES]);
-
-void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);
-
 void intel_display_irq_init(struct intel_display *display);
 
 void i915gm_irq_cstate_wa(struct intel_display *display, bool enable);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9022e32156a5..0d0ee2c43f00 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -38,7 +38,6 @@
 
 #include "display/intel_display_irq.h"
 #include "display/intel_hotplug.h"
-#include "display/intel_hotplug_irq.h"
 
 #include "gt/intel_breadcrumbs.h"
 #include "gt/intel_gt.h"
@@ -286,13 +285,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 		if (pm_iir)
 			gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir);
 
-		if (state.hotplug_status)
-			i9xx_hpd_irq_handler(display, state.hotplug_status);
-
-		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
-			vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
-
-		valleyview_pipestat_irq_handler(display, state.pipe_stats);
+		vlv_display_irq_handler(display, &state);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, ret);
@@ -357,13 +350,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
 		intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
 
-		if (state.hotplug_status)
-			i9xx_hpd_irq_handler(display, state.hotplug_status);
-
-		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
-			vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
-
-		valleyview_pipestat_irq_handler(display, state.pipe_stats);
+		vlv_display_irq_handler(display, &state);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, ret);
@@ -410,7 +397,7 @@ static irqreturn_t ilk_irq_handler(int irq, void *arg)
 		ret = IRQ_HANDLED;
 	}
 
-	if (ilk_display_irq_handler(display))
+	if (ilk_display_irq_handler(display, NULL))
 		ret = IRQ_HANDLED;
 
 	if (GRAPHICS_VER(i915) >= 6) {
@@ -472,8 +459,11 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 
 	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
 	if (master_ctl & ~GEN8_GT_IRQS) {
+		const struct intel_display_irq_state state = {
+			.master_ctl = master_ctl,
+		};
 		disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
-		gen8_de_irq_handler(display, master_ctl);
+		gen8_display_irq_handler(display, &state);
 		enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 	}
 
@@ -525,7 +515,7 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
 
 	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
 	if (master_ctl & GEN11_DISPLAY_IRQ)
-		gen11_display_irq_handler(display);
+		gen11_display_irq_handler(display, NULL);
 
 	gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);
 
@@ -592,7 +582,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
 	gen11_gt_irq_handler(gt, master_ctl);
 
 	if (master_ctl & GEN11_DISPLAY_IRQ)
-		gen11_display_irq_handler(display);
+		gen11_display_irq_handler(display, NULL);
 
 	gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);
 
@@ -896,10 +886,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
 		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
 
-		if (state.hotplug_status)
-			i9xx_hpd_irq_handler(display, state.hotplug_status);
-
-		i915_pipestat_irq_handler(display, state.iir, state.pipe_stats);
+		i915_display_irq_handler(display, &state);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, ret);
@@ -1003,10 +990,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
 		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
 
-		if (state.hotplug_status)
-			i9xx_hpd_irq_handler(display, state.hotplug_status);
-
-		i965_pipestat_irq_handler(display, state.iir, state.pipe_stats);
+		i965_display_irq_handler(display, &state);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, IRQ_HANDLED);
diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index 62e5d38938eb..c26e2f62542b 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -215,7 +215,7 @@ void xe_display_irq_handler(struct xe_device *xe, u32 master_ctl)
 		return;
 
 	if (master_ctl & DISPLAY_IRQ)
-		gen11_display_irq_handler(display);
+		gen11_display_irq_handler(display, NULL);
 }
 
 void xe_display_irq_enable(struct xe_device *xe, u32 gu_misc_iir)
-- 
2.47.3

[PATCH v4 7/8] drm/i915/irq: add intel_display_irq_ack() to irq funcs

[Jani Nikula]

Call the platform specific display irq ack hooks, if any, via
intel_display_irq_ack().

Check for HAS_DISPLAY() in intel_display_irq_ack() for completeness even
though fusing is not possible on the platforms in question.

v3:
- Pure vfunc change (Ville)

v2:
- Include LPE audio in the ack part
- Check for HAS_DISPLAY()

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/display/intel_display_irq.c  | 21 +++++++++++++++----
 .../gpu/drm/i915/display/intel_display_irq.h  |  4 +---
 drivers/gpu/drm/i915/i915_irq.c               |  8 +++----
 3 files changed, 22 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 672fd4f245ff..c777b7f249c8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -2023,8 +2023,8 @@ static void i965_display_irq_postinstall(struct intel_display *display)
 	i915_enable_asle_pipestat(display);
 }
 
-void i9xx_display_irq_ack(struct intel_display *display,
-			  struct intel_display_irq_state *state)
+static void i9xx_display_irq_ack(struct intel_display *display,
+				 struct intel_display_irq_state *state)
 {
 	if (state->iir & I915_DISPLAY_PORT_INTERRUPT)
 		state->hotplug_status = i9xx_hpd_irq_ack(display);
@@ -2119,8 +2119,8 @@ static u32 vlv_lpe_irq_mask(struct intel_display *display)
 		return I915_LPE_PIPE_A_INTERRUPT | I915_LPE_PIPE_B_INTERRUPT;
 }
 
-void vlv_display_irq_ack(struct intel_display *display,
-			 struct intel_display_irq_state *state)
+static void vlv_display_irq_ack(struct intel_display *display,
+				struct intel_display_irq_state *state)
 {
 	if (state->iir & I915_DISPLAY_PORT_INTERRUPT)
 		state->hotplug_status = i9xx_hpd_irq_ack(display);
@@ -2528,6 +2528,7 @@ static void gen11_de_irq_postinstall(struct intel_display *display)
 struct intel_display_irq_funcs {
 	void (*reset)(struct intel_display *display);
 	void (*postinstall)(struct intel_display *display);
+	void (*ack)(struct intel_display *display, struct intel_display_irq_state *state);
 };
 
 static const struct intel_display_irq_funcs gen11_display_irq_funcs = {
@@ -2543,6 +2544,7 @@ static const struct intel_display_irq_funcs gen8_display_irq_funcs = {
 static const struct intel_display_irq_funcs vlv_display_irq_funcs = {
 	.reset = vlv_display_irq_reset,
 	.postinstall = vlv_display_irq_postinstall,
+	.ack = vlv_display_irq_ack,
 };
 
 static const struct intel_display_irq_funcs ilk_display_irq_funcs = {
@@ -2553,11 +2555,13 @@ static const struct intel_display_irq_funcs ilk_display_irq_funcs = {
 static const struct intel_display_irq_funcs i965_display_irq_funcs = {
 	.reset = i9xx_display_irq_reset,
 	.postinstall = i965_display_irq_postinstall,
+	.ack = i9xx_display_irq_ack,
 };
 
 static const struct intel_display_irq_funcs i915_display_irq_funcs = {
 	.reset = i9xx_display_irq_reset,
 	.postinstall = i915_display_irq_postinstall,
+	.ack = i9xx_display_irq_ack,
 };
 
 void intel_display_irq_reset(struct intel_display *display)
@@ -2576,6 +2580,15 @@ void intel_display_irq_postinstall(struct intel_display *display)
 	display->irq.funcs->postinstall(display);
 }
 
+void intel_display_irq_ack(struct intel_display *display,
+			   struct intel_display_irq_state *state)
+{
+	if (!HAS_DISPLAY(display) || !display->irq.funcs->ack)
+		return;
+
+	display->irq.funcs->ack(display, state);
+}
+
 void intel_display_irq_init(struct intel_display *display)
 {
 	spin_lock_init(&display->irq.lock);
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index 59ec673ffc9b..876ee171d74a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -66,9 +66,7 @@ struct intel_display_irq_state {
 
 void intel_display_irq_reset(struct intel_display *display);
 void intel_display_irq_postinstall(struct intel_display *display);
-
-void vlv_display_irq_ack(struct intel_display *display, struct intel_display_irq_state *state);
-void i9xx_display_irq_ack(struct intel_display *display, struct intel_display_irq_state *state);
+void intel_display_irq_ack(struct intel_display *display, struct intel_display_irq_state *state);
 
 bool ilk_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);
 bool gen8_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0d0ee2c43f00..321dc1e573cc 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -268,7 +268,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 		if (pm_iir)
 			intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir);
 
-		vlv_display_irq_ack(display, &state);
+		intel_display_irq_ack(display, &state);
 
 		/*
 		 * VLV_IIR is single buffered, and reflects the level
@@ -338,7 +338,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 
 		gen8_gt_irq_handler(to_gt(dev_priv), master_ctl);
 
-		vlv_display_irq_ack(display, &state);
+		intel_display_irq_ack(display, &state);
 
 		/*
 		 * VLV_IIR is single buffered, and reflects the level
@@ -873,7 +873,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
 
 		ret = IRQ_HANDLED;
 
-		i9xx_display_irq_ack(display, &state);
+		intel_display_irq_ack(display, &state);
 
 		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
@@ -972,7 +972,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
 
 		ret = IRQ_HANDLED;
 
-		i9xx_display_irq_ack(display, &state);
+		intel_display_irq_ack(display, &state);
 
 		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
-- 
2.47.3

[PATCH v4 8/8] drm/i915/irq: add intel_display_irq_handler() to irq funcs

[Jani Nikula]

Call the platform specific display irq handler hooks via
intel_display_irq_handler().

v3: Pure vfunc change (Ville)

v2: Rebase, handle LPE audio in ack (Ville)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/display/intel_display_irq.c  | 40 +++++++++++++------
 .../gpu/drm/i915/display/intel_display_irq.h  |  8 +---
 drivers/gpu/drm/i915/i915_irq.c               | 16 ++++----
 drivers/gpu/drm/xe/display/xe_display.c       |  2 +-
 4 files changed, 38 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index c777b7f249c8..899a38c0a7b7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1021,8 +1021,8 @@ void ilk_display_irq_master_enable(struct intel_display *display, u32 de_ier, u3
 		intel_de_write_fw(display, SDEIER, sde_ier);
 }
 
-bool ilk_display_irq_handler(struct intel_display *display,
-			     const struct intel_display_irq_state *state)
+static bool ilk_display_irq_handler(struct intel_display *display,
+				    const struct intel_display_irq_state *state)
 {
 	u32 de_iir;
 	bool handled = false;
@@ -1567,8 +1567,8 @@ static void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
 	}
 }
 
-bool gen8_display_irq_handler(struct intel_display *display,
-			      const struct intel_display_irq_state *state)
+static bool gen8_display_irq_handler(struct intel_display *display,
+				     const struct intel_display_irq_state *state)
 {
 	gen8_de_irq_handler(display, state->master_ctl);
 
@@ -1599,8 +1599,8 @@ void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir)
 		intel_opregion_asle_intr(display);
 }
 
-bool gen11_display_irq_handler(struct intel_display *display,
-			       const struct intel_display_irq_state *state)
+static bool gen11_display_irq_handler(struct intel_display *display,
+				      const struct intel_display_irq_state *state)
 {
 	u32 disp_ctl;
 
@@ -2033,8 +2033,8 @@ static void i9xx_display_irq_ack(struct intel_display *display,
 	i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
 }
 
-bool i965_display_irq_handler(struct intel_display *display,
-			      const struct intel_display_irq_state *state)
+static bool i965_display_irq_handler(struct intel_display *display,
+				     const struct intel_display_irq_state *state)
 {
 	if (state->hotplug_status)
 		i9xx_hpd_irq_handler(display, state->hotplug_status);
@@ -2044,8 +2044,8 @@ bool i965_display_irq_handler(struct intel_display *display,
 	return true;
 }
 
-bool i915_display_irq_handler(struct intel_display *display,
-			      const struct intel_display_irq_state *state)
+static bool i915_display_irq_handler(struct intel_display *display,
+				     const struct intel_display_irq_state *state)
 {
 	if (state->hotplug_status)
 		i9xx_hpd_irq_handler(display, state->hotplug_status);
@@ -2136,8 +2136,8 @@ static void vlv_display_irq_ack(struct intel_display *display,
 		intel_lpe_audio_irq_handler(display);
 }
 
-bool vlv_display_irq_handler(struct intel_display *display,
-			     const struct intel_display_irq_state *state)
+static bool vlv_display_irq_handler(struct intel_display *display,
+				    const struct intel_display_irq_state *state)
 {
 	if (state->hotplug_status)
 		i9xx_hpd_irq_handler(display, state->hotplug_status);
@@ -2529,39 +2529,46 @@ struct intel_display_irq_funcs {
 	void (*reset)(struct intel_display *display);
 	void (*postinstall)(struct intel_display *display);
 	void (*ack)(struct intel_display *display, struct intel_display_irq_state *state);
+	bool (*handler)(struct intel_display *display, const struct intel_display_irq_state *state);
 };
 
 static const struct intel_display_irq_funcs gen11_display_irq_funcs = {
 	.reset = gen11_display_irq_reset,
 	.postinstall = gen11_de_irq_postinstall,
+	.handler = gen11_display_irq_handler,
 };
 
 static const struct intel_display_irq_funcs gen8_display_irq_funcs = {
 	.reset = gen8_display_irq_reset,
 	.postinstall = gen8_de_irq_postinstall,
+	.handler = gen8_display_irq_handler,
 };
 
 static const struct intel_display_irq_funcs vlv_display_irq_funcs = {
 	.reset = vlv_display_irq_reset,
 	.postinstall = vlv_display_irq_postinstall,
 	.ack = vlv_display_irq_ack,
+	.handler = vlv_display_irq_handler,
 };
 
 static const struct intel_display_irq_funcs ilk_display_irq_funcs = {
 	.reset = ilk_display_irq_reset,
 	.postinstall = ilk_de_irq_postinstall,
+	.handler = ilk_display_irq_handler,
 };
 
 static const struct intel_display_irq_funcs i965_display_irq_funcs = {
 	.reset = i9xx_display_irq_reset,
 	.postinstall = i965_display_irq_postinstall,
 	.ack = i9xx_display_irq_ack,
+	.handler = i965_display_irq_handler,
 };
 
 static const struct intel_display_irq_funcs i915_display_irq_funcs = {
 	.reset = i9xx_display_irq_reset,
 	.postinstall = i915_display_irq_postinstall,
 	.ack = i9xx_display_irq_ack,
+	.handler = i915_display_irq_handler,
 };
 
 void intel_display_irq_reset(struct intel_display *display)
@@ -2589,6 +2596,15 @@ void intel_display_irq_ack(struct intel_display *display,
 	display->irq.funcs->ack(display, state);
 }
 
+bool intel_display_irq_handler(struct intel_display *display,
+			       const struct intel_display_irq_state *state)
+{
+	if (!HAS_DISPLAY(display) || !display->irq.funcs->handler)
+		return true;
+
+	return display->irq.funcs->handler(display, state);
+}
+
 void intel_display_irq_init(struct intel_display *display)
 {
 	spin_lock_init(&display->irq.lock);
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index 876ee171d74a..a1227cee885a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -67,13 +67,7 @@ struct intel_display_irq_state {
 void intel_display_irq_reset(struct intel_display *display);
 void intel_display_irq_postinstall(struct intel_display *display);
 void intel_display_irq_ack(struct intel_display *display, struct intel_display_irq_state *state);
-
-bool ilk_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);
-bool gen8_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);
-bool gen11_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);
-bool i965_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);
-bool i915_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);
-bool vlv_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);
+bool intel_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);
 
 u32 i9xx_display_irq_enable_mask(struct intel_display *display);
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 321dc1e573cc..30ce462e92ab 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -285,7 +285,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 		if (pm_iir)
 			gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir);
 
-		vlv_display_irq_handler(display, &state);
+		intel_display_irq_handler(display, &state);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, ret);
@@ -350,7 +350,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
 		intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
 
-		vlv_display_irq_handler(display, &state);
+		intel_display_irq_handler(display, &state);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, ret);
@@ -397,7 +397,7 @@ static irqreturn_t ilk_irq_handler(int irq, void *arg)
 		ret = IRQ_HANDLED;
 	}
 
-	if (ilk_display_irq_handler(display, NULL))
+	if (intel_display_irq_handler(display, NULL))
 		ret = IRQ_HANDLED;
 
 	if (GRAPHICS_VER(i915) >= 6) {
@@ -463,7 +463,7 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 			.master_ctl = master_ctl,
 		};
 		disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
-		gen8_display_irq_handler(display, &state);
+		intel_display_irq_handler(display, &state);
 		enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 	}
 
@@ -515,7 +515,7 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
 
 	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
 	if (master_ctl & GEN11_DISPLAY_IRQ)
-		gen11_display_irq_handler(display, NULL);
+		intel_display_irq_handler(display, NULL);
 
 	gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);
 
@@ -582,7 +582,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
 	gen11_gt_irq_handler(gt, master_ctl);
 
 	if (master_ctl & GEN11_DISPLAY_IRQ)
-		gen11_display_irq_handler(display, NULL);
+		intel_display_irq_handler(display, NULL);
 
 	gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);
 
@@ -886,7 +886,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
 		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
 
-		i915_display_irq_handler(display, &state);
+		intel_display_irq_handler(display, &state);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, ret);
@@ -990,7 +990,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
 		if (state.iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
 
-		i965_display_irq_handler(display, &state);
+		intel_display_irq_handler(display, &state);
 	} while (0);
 
 	pmu_irq_stats(dev_priv, IRQ_HANDLED);
diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index c26e2f62542b..796164e9bc20 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -215,7 +215,7 @@ void xe_display_irq_handler(struct xe_device *xe, u32 master_ctl)
 		return;
 
 	if (master_ctl & DISPLAY_IRQ)
-		gen11_display_irq_handler(display, NULL);
+		intel_display_irq_handler(display, NULL);
 }
 
 void xe_display_irq_enable(struct xe_device *xe, u32 gu_misc_iir)
-- 
2.47.3

✗ CI.checkpatch: warning for drm/i915: add display irq hooks (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: add display irq hooks (rev3)
URL   : https://patchwork.freedesktop.org/series/165936/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
061140b9bc586ae7f40abc1249c97e1cc72d1b9d
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 08cac07cafff393a95c8e5bbdea9a10a05dcfc71
Author: Jani Nikula <jani.nikula@intel.com>
Date:   Wed May 13 19:13:31 2026 +0300

    drm/i915/irq: add intel_display_irq_handler() to irq funcs
    
    Call the platform specific display irq handler hooks via
    intel_display_irq_handler().
    
    v3: Pure vfunc change (Ville)
    
    v2: Rebase, handle LPE audio in ack (Ville)
    
    Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+ /mt/dim checkpatch 21b42374be17d486baf9392b56377afde67a778d drm-intel
0d73ccdb90fd drm/i915/irq: deduplicate dg1_de_irq_postinstall() and gen11_de_irq_postinstall()
893bc59c4e01 drm/i915/irq: constify pipe stats parameters
-:57: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#57: FILE: drivers/gpu/drm/i915/display/intel_display_irq.h:81:
+void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);

-:58: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#58: FILE: drivers/gpu/drm/i915/display/intel_display_irq.h:82:
+void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);

-:59: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#59: FILE: drivers/gpu/drm/i915/display/intel_display_irq.h:83:
+void valleyview_pipestat_irq_handler(struct intel_display *display, const u32 pipe_stats[I915_MAX_PIPES]);

total: 0 errors, 3 warnings, 0 checks, 36 lines checked
f3f1da9d7759 drm/i915/irq: add display irq funcs, start with intel_display_irq_reset()
438f34ca2c9a drm/i915/irq: add intel_display_irq_postinstall() to irq funcs
42663327fd75 drm/i915/irq: add platform specific display irq ack functions
0fc8ef8bcae2 drm/i915/irq: add platform specific display irq handler functions
-:192: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#192: FILE: drivers/gpu/drm/i915/display/intel_display_irq.h:73:
+bool ilk_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);

-:193: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#193: FILE: drivers/gpu/drm/i915/display/intel_display_irq.h:74:
+bool gen8_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);

-:194: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#194: FILE: drivers/gpu/drm/i915/display/intel_display_irq.h:75:
+bool gen11_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);

-:195: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#195: FILE: drivers/gpu/drm/i915/display/intel_display_irq.h:76:
+bool i965_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);

-:196: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#196: FILE: drivers/gpu/drm/i915/display/intel_display_irq.h:77:
+bool i915_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);

-:197: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#197: FILE: drivers/gpu/drm/i915/display/intel_display_irq.h:78:
+bool vlv_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);

total: 0 errors, 6 warnings, 0 checks, 277 lines checked
976efead2eb1 drm/i915/irq: add intel_display_irq_ack() to irq funcs
08cac07cafff drm/i915/irq: add intel_display_irq_handler() to irq funcs
-:163: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#163: FILE: drivers/gpu/drm/i915/display/intel_display_irq.h:70:
+bool intel_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);

total: 0 errors, 1 warnings, 0 checks, 207 lines checked

✓ CI.KUnit: success for drm/i915: add display irq hooks (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: add display irq hooks (rev3)
URL   : https://patchwork.freedesktop.org/series/165936/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[16:39:56] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:40:00] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[16:40:31] Starting KUnit Kernel (1/1)...
[16:40:31] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[16:40:32] ================== guc_buf (11 subtests) ===================
[16:40:32] [PASSED] test_smallest
[16:40:32] [PASSED] test_largest
[16:40:32] [PASSED] test_granular
[16:40:32] [PASSED] test_unique
[16:40:32] [PASSED] test_overlap
[16:40:32] [PASSED] test_reusable
[16:40:32] [PASSED] test_too_big
[16:40:32] [PASSED] test_flush
[16:40:32] [PASSED] test_lookup
[16:40:32] [PASSED] test_data
[16:40:32] [PASSED] test_class
[16:40:32] ===================== [PASSED] guc_buf =====================
[16:40:32] =================== guc_dbm (7 subtests) ===================
[16:40:32] [PASSED] test_empty
[16:40:32] [PASSED] test_default
[16:40:32] ======================== test_size  ========================
[16:40:32] [PASSED] 4
[16:40:32] [PASSED] 8
[16:40:32] [PASSED] 32
[16:40:32] [PASSED] 256
[16:40:32] ==================== [PASSED] test_size ====================
[16:40:32] ======================= test_reuse  ========================
[16:40:32] [PASSED] 4
[16:40:32] [PASSED] 8
[16:40:32] [PASSED] 32
[16:40:32] [PASSED] 256
[16:40:32] =================== [PASSED] test_reuse ====================
[16:40:32] =================== test_range_overlap  ====================
[16:40:32] [PASSED] 4
[16:40:32] [PASSED] 8
[16:40:32] [PASSED] 32
[16:40:32] [PASSED] 256
[16:40:32] =============== [PASSED] test_range_overlap ================
[16:40:32] =================== test_range_compact  ====================
[16:40:32] [PASSED] 4
[16:40:32] [PASSED] 8
[16:40:32] [PASSED] 32
[16:40:32] [PASSED] 256
[16:40:32] =============== [PASSED] test_range_compact ================
[16:40:32] ==================== test_range_spare  =====================
[16:40:32] [PASSED] 4
[16:40:32] [PASSED] 8
[16:40:32] [PASSED] 32
[16:40:32] [PASSED] 256
[16:40:32] ================ [PASSED] test_range_spare =================
[16:40:32] ===================== [PASSED] guc_dbm =====================
[16:40:32] =================== guc_idm (6 subtests) ===================
[16:40:32] [PASSED] bad_init
[16:40:32] [PASSED] no_init
[16:40:32] [PASSED] init_fini
[16:40:32] [PASSED] check_used
[16:40:32] [PASSED] check_quota
[16:40:32] [PASSED] check_all
[16:40:32] ===================== [PASSED] guc_idm =====================
[16:40:32] ================== no_relay (3 subtests) ===================
[16:40:32] [PASSED] xe_drops_guc2pf_if_not_ready
[16:40:32] [PASSED] xe_drops_guc2vf_if_not_ready
[16:40:32] [PASSED] xe_rejects_send_if_not_ready
[16:40:32] ==================== [PASSED] no_relay =====================
[16:40:32] ================== pf_relay (14 subtests) ==================
[16:40:32] [PASSED] pf_rejects_guc2pf_too_short
[16:40:32] [PASSED] pf_rejects_guc2pf_too_long
[16:40:32] [PASSED] pf_rejects_guc2pf_no_payload
[16:40:32] [PASSED] pf_fails_no_payload
[16:40:32] [PASSED] pf_fails_bad_origin
[16:40:32] [PASSED] pf_fails_bad_type
[16:40:32] [PASSED] pf_txn_reports_error
[16:40:32] [PASSED] pf_txn_sends_pf2guc
[16:40:32] [PASSED] pf_sends_pf2guc
[16:40:32] [SKIPPED] pf_loopback_nop
[16:40:32] [SKIPPED] pf_loopback_echo
[16:40:32] [SKIPPED] pf_loopback_fail
[16:40:32] [SKIPPED] pf_loopback_busy
[16:40:32] [SKIPPED] pf_loopback_retry
[16:40:32] ==================== [PASSED] pf_relay =====================
[16:40:32] ================== vf_relay (3 subtests) ===================
[16:40:32] [PASSED] vf_rejects_guc2vf_too_short
[16:40:32] [PASSED] vf_rejects_guc2vf_too_long
[16:40:32] [PASSED] vf_rejects_guc2vf_no_payload
[16:40:32] ==================== [PASSED] vf_relay =====================
[16:40:32] ================ pf_gt_config (9 subtests) =================
[16:40:32] [PASSED] fair_contexts_1vf
[16:40:32] [PASSED] fair_doorbells_1vf
[16:40:32] [PASSED] fair_ggtt_1vf
[16:40:32] ====================== fair_vram_1vf  ======================
[16:40:32] [PASSED] 3.50 GiB
[16:40:32] [PASSED] 11.5 GiB
[16:40:32] [PASSED] 15.5 GiB
[16:40:32] [PASSED] 31.5 GiB
[16:40:32] [PASSED] 63.5 GiB
[16:40:32] [PASSED] 1.91 GiB
[16:40:32] ================== [PASSED] fair_vram_1vf ==================
[16:40:32] ================ fair_vram_1vf_admin_only  =================
[16:40:32] [PASSED] 3.50 GiB
[16:40:32] [PASSED] 11.5 GiB
[16:40:32] [PASSED] 15.5 GiB
[16:40:32] [PASSED] 31.5 GiB
[16:40:32] [PASSED] 63.5 GiB
[16:40:32] [PASSED] 1.91 GiB
[16:40:32] ============ [PASSED] fair_vram_1vf_admin_only =============
[16:40:32] ====================== fair_contexts  ======================
[16:40:32] [PASSED] 1 VF
[16:40:32] [PASSED] 2 VFs
[16:40:32] [PASSED] 3 VFs
[16:40:32] [PASSED] 4 VFs
[16:40:32] [PASSED] 5 VFs
[16:40:32] [PASSED] 6 VFs
[16:40:32] [PASSED] 7 VFs
[16:40:32] [PASSED] 8 VFs
[16:40:32] [PASSED] 9 VFs
[16:40:32] [PASSED] 10 VFs
[16:40:32] [PASSED] 11 VFs
[16:40:32] [PASSED] 12 VFs
[16:40:32] [PASSED] 13 VFs
[16:40:32] [PASSED] 14 VFs
[16:40:32] [PASSED] 15 VFs
[16:40:32] [PASSED] 16 VFs
[16:40:32] [PASSED] 17 VFs
[16:40:32] [PASSED] 18 VFs
[16:40:32] [PASSED] 19 VFs
[16:40:32] [PASSED] 20 VFs
[16:40:32] [PASSED] 21 VFs
[16:40:32] [PASSED] 22 VFs
[16:40:32] [PASSED] 23 VFs
[16:40:32] [PASSED] 24 VFs
[16:40:32] [PASSED] 25 VFs
[16:40:32] [PASSED] 26 VFs
[16:40:32] [PASSED] 27 VFs
[16:40:32] [PASSED] 28 VFs
[16:40:32] [PASSED] 29 VFs
[16:40:32] [PASSED] 30 VFs
[16:40:32] [PASSED] 31 VFs
[16:40:32] [PASSED] 32 VFs
[16:40:32] [PASSED] 33 VFs
[16:40:32] [PASSED] 34 VFs
[16:40:32] [PASSED] 35 VFs
[16:40:32] [PASSED] 36 VFs
[16:40:32] [PASSED] 37 VFs
[16:40:32] [PASSED] 38 VFs
[16:40:32] [PASSED] 39 VFs
[16:40:32] [PASSED] 40 VFs
[16:40:32] [PASSED] 41 VFs
[16:40:32] [PASSED] 42 VFs
[16:40:32] [PASSED] 43 VFs
[16:40:32] [PASSED] 44 VFs
[16:40:32] [PASSED] 45 VFs
[16:40:32] [PASSED] 46 VFs
[16:40:32] [PASSED] 47 VFs
[16:40:32] [PASSED] 48 VFs
[16:40:32] [PASSED] 49 VFs
[16:40:32] [PASSED] 50 VFs
[16:40:32] [PASSED] 51 VFs
[16:40:32] [PASSED] 52 VFs
[16:40:32] [PASSED] 53 VFs
[16:40:32] [PASSED] 54 VFs
[16:40:32] [PASSED] 55 VFs
[16:40:32] [PASSED] 56 VFs
[16:40:32] [PASSED] 57 VFs
[16:40:32] [PASSED] 58 VFs
[16:40:32] [PASSED] 59 VFs
[16:40:32] [PASSED] 60 VFs
[16:40:32] [PASSED] 61 VFs
[16:40:32] [PASSED] 62 VFs
[16:40:32] [PASSED] 63 VFs
[16:40:32] ================== [PASSED] fair_contexts ==================
[16:40:32] ===================== fair_doorbells  ======================
[16:40:32] [PASSED] 1 VF
[16:40:32] [PASSED] 2 VFs
[16:40:32] [PASSED] 3 VFs
[16:40:32] [PASSED] 4 VFs
[16:40:32] [PASSED] 5 VFs
[16:40:32] [PASSED] 6 VFs
[16:40:32] [PASSED] 7 VFs
[16:40:32] [PASSED] 8 VFs
[16:40:32] [PASSED] 9 VFs
[16:40:32] [PASSED] 10 VFs
[16:40:32] [PASSED] 11 VFs
[16:40:32] [PASSED] 12 VFs
[16:40:32] [PASSED] 13 VFs
[16:40:32] [PASSED] 14 VFs
[16:40:32] [PASSED] 15 VFs
[16:40:32] [PASSED] 16 VFs
[16:40:32] [PASSED] 17 VFs
[16:40:32] [PASSED] 18 VFs
[16:40:32] [PASSED] 19 VFs
[16:40:32] [PASSED] 20 VFs
[16:40:32] [PASSED] 21 VFs
[16:40:32] [PASSED] 22 VFs
[16:40:32] [PASSED] 23 VFs
[16:40:32] [PASSED] 24 VFs
[16:40:32] [PASSED] 25 VFs
[16:40:32] [PASSED] 26 VFs
[16:40:32] [PASSED] 27 VFs
[16:40:32] [PASSED] 28 VFs
[16:40:32] [PASSED] 29 VFs
[16:40:32] [PASSED] 30 VFs
[16:40:32] [PASSED] 31 VFs
[16:40:32] [PASSED] 32 VFs
[16:40:32] [PASSED] 33 VFs
[16:40:32] [PASSED] 34 VFs
[16:40:32] [PASSED] 35 VFs
[16:40:32] [PASSED] 36 VFs
[16:40:32] [PASSED] 37 VFs
[16:40:32] [PASSED] 38 VFs
[16:40:32] [PASSED] 39 VFs
[16:40:32] [PASSED] 40 VFs
[16:40:32] [PASSED] 41 VFs
[16:40:32] [PASSED] 42 VFs
[16:40:32] [PASSED] 43 VFs
[16:40:32] [PASSED] 44 VFs
[16:40:32] [PASSED] 45 VFs
[16:40:32] [PASSED] 46 VFs
[16:40:32] [PASSED] 47 VFs
[16:40:32] [PASSED] 48 VFs
[16:40:32] [PASSED] 49 VFs
[16:40:32] [PASSED] 50 VFs
[16:40:32] [PASSED] 51 VFs
[16:40:32] [PASSED] 52 VFs
[16:40:32] [PASSED] 53 VFs
[16:40:32] [PASSED] 54 VFs
[16:40:32] [PASSED] 55 VFs
[16:40:32] [PASSED] 56 VFs
[16:40:32] [PASSED] 57 VFs
[16:40:32] [PASSED] 58 VFs
[16:40:32] [PASSED] 59 VFs
[16:40:32] [PASSED] 60 VFs
[16:40:32] [PASSED] 61 VFs
[16:40:32] [PASSED] 62 VFs
[16:40:32] [PASSED] 63 VFs
[16:40:32] ================= [PASSED] fair_doorbells ==================
[16:40:32] ======================== fair_ggtt  ========================
[16:40:32] [PASSED] 1 VF
[16:40:32] [PASSED] 2 VFs
[16:40:32] [PASSED] 3 VFs
[16:40:32] [PASSED] 4 VFs
[16:40:32] [PASSED] 5 VFs
[16:40:32] [PASSED] 6 VFs
[16:40:32] [PASSED] 7 VFs
[16:40:32] [PASSED] 8 VFs
[16:40:32] [PASSED] 9 VFs
[16:40:32] [PASSED] 10 VFs
[16:40:32] [PASSED] 11 VFs
[16:40:32] [PASSED] 12 VFs
[16:40:32] [PASSED] 13 VFs
[16:40:32] [PASSED] 14 VFs
[16:40:32] [PASSED] 15 VFs
[16:40:32] [PASSED] 16 VFs
[16:40:32] [PASSED] 17 VFs
[16:40:32] [PASSED] 18 VFs
[16:40:32] [PASSED] 19 VFs
[16:40:32] [PASSED] 20 VFs
[16:40:32] [PASSED] 21 VFs
[16:40:32] [PASSED] 22 VFs
[16:40:32] [PASSED] 23 VFs
[16:40:32] [PASSED] 24 VFs
[16:40:32] [PASSED] 25 VFs
[16:40:32] [PASSED] 26 VFs
[16:40:32] [PASSED] 27 VFs
[16:40:32] [PASSED] 28 VFs
[16:40:32] [PASSED] 29 VFs
[16:40:32] [PASSED] 30 VFs
[16:40:32] [PASSED] 31 VFs
[16:40:32] [PASSED] 32 VFs
[16:40:32] [PASSED] 33 VFs
[16:40:32] [PASSED] 34 VFs
[16:40:32] [PASSED] 35 VFs
[16:40:32] [PASSED] 36 VFs
[16:40:32] [PASSED] 37 VFs
[16:40:32] [PASSED] 38 VFs
[16:40:32] [PASSED] 39 VFs
[16:40:32] [PASSED] 40 VFs
[16:40:32] [PASSED] 41 VFs
[16:40:32] [PASSED] 42 VFs
[16:40:32] [PASSED] 43 VFs
[16:40:32] [PASSED] 44 VFs
[16:40:32] [PASSED] 45 VFs
[16:40:32] [PASSED] 46 VFs
[16:40:32] [PASSED] 47 VFs
[16:40:32] [PASSED] 48 VFs
[16:40:32] [PASSED] 49 VFs
[16:40:32] [PASSED] 50 VFs
[16:40:32] [PASSED] 51 VFs
[16:40:32] [PASSED] 52 VFs
[16:40:32] [PASSED] 53 VFs
[16:40:32] [PASSED] 54 VFs
[16:40:32] [PASSED] 55 VFs
[16:40:32] [PASSED] 56 VFs
[16:40:32] [PASSED] 57 VFs
[16:40:32] [PASSED] 58 VFs
[16:40:32] [PASSED] 59 VFs
[16:40:32] [PASSED] 60 VFs
[16:40:32] [PASSED] 61 VFs
[16:40:32] [PASSED] 62 VFs
[16:40:32] [PASSED] 63 VFs
[16:40:32] ==================== [PASSED] fair_ggtt ====================
[16:40:32] ======================== fair_vram  ========================
[16:40:32] [PASSED] 1 VF
[16:40:32] [PASSED] 2 VFs
[16:40:32] [PASSED] 3 VFs
[16:40:32] [PASSED] 4 VFs
[16:40:32] [PASSED] 5 VFs
[16:40:32] [PASSED] 6 VFs
[16:40:32] [PASSED] 7 VFs
[16:40:32] [PASSED] 8 VFs
[16:40:32] [PASSED] 9 VFs
[16:40:32] [PASSED] 10 VFs
[16:40:32] [PASSED] 11 VFs
[16:40:32] [PASSED] 12 VFs
[16:40:32] [PASSED] 13 VFs
[16:40:32] [PASSED] 14 VFs
[16:40:32] [PASSED] 15 VFs
[16:40:32] [PASSED] 16 VFs
[16:40:32] [PASSED] 17 VFs
[16:40:32] [PASSED] 18 VFs
[16:40:32] [PASSED] 19 VFs
[16:40:32] [PASSED] 20 VFs
[16:40:32] [PASSED] 21 VFs
[16:40:32] [PASSED] 22 VFs
[16:40:32] [PASSED] 23 VFs
[16:40:32] [PASSED] 24 VFs
[16:40:32] [PASSED] 25 VFs
[16:40:32] [PASSED] 26 VFs
[16:40:32] [PASSED] 27 VFs
[16:40:32] [PASSED] 28 VFs
[16:40:32] [PASSED] 29 VFs
[16:40:32] [PASSED] 30 VFs
[16:40:32] [PASSED] 31 VFs
[16:40:32] [PASSED] 32 VFs
[16:40:32] [PASSED] 33 VFs
[16:40:32] [PASSED] 34 VFs
[16:40:32] [PASSED] 35 VFs
[16:40:32] [PASSED] 36 VFs
[16:40:32] [PASSED] 37 VFs
[16:40:32] [PASSED] 38 VFs
[16:40:32] [PASSED] 39 VFs
[16:40:32] [PASSED] 40 VFs
[16:40:32] [PASSED] 41 VFs
[16:40:32] [PASSED] 42 VFs
[16:40:32] [PASSED] 43 VFs
[16:40:32] [PASSED] 44 VFs
[16:40:32] [PASSED] 45 VFs
[16:40:32] [PASSED] 46 VFs
[16:40:32] [PASSED] 47 VFs
[16:40:32] [PASSED] 48 VFs
[16:40:32] [PASSED] 49 VFs
[16:40:32] [PASSED] 50 VFs
[16:40:32] [PASSED] 51 VFs
[16:40:32] [PASSED] 52 VFs
[16:40:32] [PASSED] 53 VFs
[16:40:32] [PASSED] 54 VFs
[16:40:32] [PASSED] 55 VFs
[16:40:32] [PASSED] 56 VFs
[16:40:32] [PASSED] 57 VFs
[16:40:32] [PASSED] 58 VFs
[16:40:32] [PASSED] 59 VFs
[16:40:32] [PASSED] 60 VFs
[16:40:32] [PASSED] 61 VFs
[16:40:32] [PASSED] 62 VFs
[16:40:32] [PASSED] 63 VFs
[16:40:32] ==================== [PASSED] fair_vram ====================
[16:40:32] ================== [PASSED] pf_gt_config ===================
[16:40:32] ===================== lmtt (1 subtest) =====================
[16:40:32] ======================== test_ops  =========================
[16:40:32] [PASSED] 2-level
[16:40:32] [PASSED] multi-level
[16:40:32] ==================== [PASSED] test_ops =====================
[16:40:32] ====================== [PASSED] lmtt =======================
[16:40:32] ================= pf_service (11 subtests) =================
[16:40:32] [PASSED] pf_negotiate_any
[16:40:32] [PASSED] pf_negotiate_base_match
[16:40:32] [PASSED] pf_negotiate_base_newer
[16:40:32] [PASSED] pf_negotiate_base_next
[16:40:32] [SKIPPED] pf_negotiate_base_older
[16:40:32] [PASSED] pf_negotiate_base_prev
[16:40:32] [PASSED] pf_negotiate_latest_match
[16:40:32] [PASSED] pf_negotiate_latest_newer
[16:40:32] [PASSED] pf_negotiate_latest_next
[16:40:32] [SKIPPED] pf_negotiate_latest_older
[16:40:32] [SKIPPED] pf_negotiate_latest_prev
[16:40:32] =================== [PASSED] pf_service ====================
[16:40:32] ================= xe_guc_g2g (2 subtests) ==================
[16:40:32] ============== xe_live_guc_g2g_kunit_default  ==============
[16:40:32] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[16:40:32] ============== xe_live_guc_g2g_kunit_allmem  ===============
[16:40:32] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[16:40:32] =================== [SKIPPED] xe_guc_g2g ===================
[16:40:32] =================== xe_mocs (2 subtests) ===================
[16:40:32] ================ xe_live_mocs_kernel_kunit  ================
[16:40:32] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[16:40:32] ================ xe_live_mocs_reset_kunit  =================
[16:40:32] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[16:40:32] ==================== [SKIPPED] xe_mocs =====================
[16:40:32] ================= xe_migrate (2 subtests) ==================
[16:40:32] ================= xe_migrate_sanity_kunit  =================
[16:40:32] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[16:40:32] ================== xe_validate_ccs_kunit  ==================
[16:40:32] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[16:40:32] =================== [SKIPPED] xe_migrate ===================
[16:40:32] ================== xe_dma_buf (1 subtest) ==================
[16:40:32] ==================== xe_dma_buf_kunit  =====================
[16:40:32] ================ [SKIPPED] xe_dma_buf_kunit ================
[16:40:32] =================== [SKIPPED] xe_dma_buf ===================
[16:40:32] ================= xe_bo_shrink (1 subtest) =================
[16:40:32] =================== xe_bo_shrink_kunit  ====================
[16:40:32] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[16:40:32] ================== [SKIPPED] xe_bo_shrink ==================
[16:40:32] ==================== xe_bo (2 subtests) ====================
[16:40:32] ================== xe_ccs_migrate_kunit  ===================
[16:40:32] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[16:40:32] ==================== xe_bo_evict_kunit  ====================
[16:40:32] =============== [SKIPPED] xe_bo_evict_kunit ================
[16:40:32] ===================== [SKIPPED] xe_bo ======================
[16:40:32] ==================== args (13 subtests) ====================
[16:40:32] [PASSED] count_args_test
[16:40:32] [PASSED] call_args_example
[16:40:32] [PASSED] call_args_test
[16:40:32] [PASSED] drop_first_arg_example
[16:40:32] [PASSED] drop_first_arg_test
[16:40:32] [PASSED] first_arg_example
[16:40:32] [PASSED] first_arg_test
[16:40:32] [PASSED] last_arg_example
[16:40:32] [PASSED] last_arg_test
[16:40:32] [PASSED] pick_arg_example
[16:40:32] [PASSED] if_args_example
[16:40:32] [PASSED] if_args_test
[16:40:32] [PASSED] sep_comma_example
[16:40:32] ====================== [PASSED] args =======================
[16:40:32] =================== xe_pci (3 subtests) ====================
[16:40:32] ==================== check_graphics_ip  ====================
[16:40:32] [PASSED] 12.00 Xe_LP
[16:40:32] [PASSED] 12.10 Xe_LP+
[16:40:32] [PASSED] 12.55 Xe_HPG
[16:40:32] [PASSED] 12.60 Xe_HPC
[16:40:32] [PASSED] 12.70 Xe_LPG
[16:40:32] [PASSED] 12.71 Xe_LPG
[16:40:32] [PASSED] 12.74 Xe_LPG+
[16:40:32] [PASSED] 20.01 Xe2_HPG
[16:40:32] [PASSED] 20.02 Xe2_HPG
[16:40:32] [PASSED] 20.04 Xe2_LPG
[16:40:32] [PASSED] 30.00 Xe3_LPG
[16:40:32] [PASSED] 30.01 Xe3_LPG
[16:40:32] [PASSED] 30.03 Xe3_LPG
[16:40:32] [PASSED] 30.04 Xe3_LPG
[16:40:32] [PASSED] 30.05 Xe3_LPG
[16:40:32] [PASSED] 35.10 Xe3p_LPG
[16:40:32] [PASSED] 35.11 Xe3p_XPC
[16:40:32] ================ [PASSED] check_graphics_ip ================
[16:40:32] ===================== check_media_ip  ======================
[16:40:32] [PASSED] 12.00 Xe_M
[16:40:32] [PASSED] 12.55 Xe_HPM
[16:40:32] [PASSED] 13.00 Xe_LPM+
[16:40:32] [PASSED] 13.01 Xe2_HPM
[16:40:32] [PASSED] 20.00 Xe2_LPM
[16:40:32] [PASSED] 30.00 Xe3_LPM
[16:40:32] [PASSED] 30.02 Xe3_LPM
[16:40:32] [PASSED] 35.00 Xe3p_LPM
[16:40:32] [PASSED] 35.03 Xe3p_HPM
[16:40:32] ================= [PASSED] check_media_ip ==================
[16:40:32] =================== check_platform_desc  ===================
[16:40:32] [PASSED] 0x9A60 (TIGERLAKE)
[16:40:32] [PASSED] 0x9A68 (TIGERLAKE)
[16:40:32] [PASSED] 0x9A70 (TIGERLAKE)
[16:40:32] [PASSED] 0x9A40 (TIGERLAKE)
[16:40:32] [PASSED] 0x9A49 (TIGERLAKE)
[16:40:32] [PASSED] 0x9A59 (TIGERLAKE)
[16:40:32] [PASSED] 0x9A78 (TIGERLAKE)
[16:40:32] [PASSED] 0x9AC0 (TIGERLAKE)
[16:40:32] [PASSED] 0x9AC9 (TIGERLAKE)
[16:40:32] [PASSED] 0x9AD9 (TIGERLAKE)
[16:40:32] [PASSED] 0x9AF8 (TIGERLAKE)
[16:40:32] [PASSED] 0x4C80 (ROCKETLAKE)
[16:40:32] [PASSED] 0x4C8A (ROCKETLAKE)
[16:40:32] [PASSED] 0x4C8B (ROCKETLAKE)
[16:40:32] [PASSED] 0x4C8C (ROCKETLAKE)
[16:40:32] [PASSED] 0x4C90 (ROCKETLAKE)
[16:40:32] [PASSED] 0x4C9A (ROCKETLAKE)
[16:40:32] [PASSED] 0x4680 (ALDERLAKE_S)
[16:40:32] [PASSED] 0x4682 (ALDERLAKE_S)
[16:40:32] [PASSED] 0x4688 (ALDERLAKE_S)
[16:40:32] [PASSED] 0x468A (ALDERLAKE_S)
[16:40:32] [PASSED] 0x468B (ALDERLAKE_S)
[16:40:32] [PASSED] 0x4690 (ALDERLAKE_S)
[16:40:32] [PASSED] 0x4692 (ALDERLAKE_S)
[16:40:32] [PASSED] 0x4693 (ALDERLAKE_S)
[16:40:32] [PASSED] 0x46A0 (ALDERLAKE_P)
[16:40:32] [PASSED] 0x46A1 (ALDERLAKE_P)
[16:40:32] [PASSED] 0x46A2 (ALDERLAKE_P)
[16:40:32] [PASSED] 0x46A3 (ALDERLAKE_P)
[16:40:32] [PASSED] 0x46A6 (ALDERLAKE_P)
[16:40:32] [PASSED] 0x46A8 (ALDERLAKE_P)
[16:40:32] [PASSED] 0x46AA (ALDERLAKE_P)
[16:40:32] [PASSED] 0x462A (ALDERLAKE_P)
[16:40:32] [PASSED] 0x4626 (ALDERLAKE_P)
[16:40:32] [PASSED] 0x4628 (ALDERLAKE_P)
[16:40:32] [PASSED] 0x46B0 (ALDERLAKE_P)
[16:40:32] [PASSED] 0x46B1 (ALDERLAKE_P)
[16:40:32] [PASSED] 0x46B2 (ALDERLAKE_P)
[16:40:32] [PASSED] 0x46B3 (ALDERLAKE_P)
[16:40:32] [PASSED] 0x46C0 (ALDERLAKE_P)
[16:40:32] [PASSED] 0x46C1 (ALDERLAKE_P)
[16:40:32] [PASSED] 0x46C2 (ALDERLAKE_P)
[16:40:32] [PASSED] 0x46C3 (ALDERLAKE_P)
[16:40:32] [PASSED] 0x46D0 (ALDERLAKE_N)
[16:40:32] [PASSED] 0x46D1 (ALDERLAKE_N)
[16:40:32] [PASSED] 0x46D2 (ALDERLAKE_N)
[16:40:32] [PASSED] 0x46D3 (ALDERLAKE_N)
[16:40:32] [PASSED] 0x46D4 (ALDERLAKE_N)
[16:40:32] [PASSED] 0xA721 (ALDERLAKE_P)
[16:40:32] [PASSED] 0xA7A1 (ALDERLAKE_P)
[16:40:32] [PASSED] 0xA7A9 (ALDERLAKE_P)
[16:40:32] [PASSED] 0xA7AC (ALDERLAKE_P)
[16:40:32] [PASSED] 0xA7AD (ALDERLAKE_P)
[16:40:32] [PASSED] 0xA720 (ALDERLAKE_P)
[16:40:32] [PASSED] 0xA7A0 (ALDERLAKE_P)
[16:40:32] [PASSED] 0xA7A8 (ALDERLAKE_P)
[16:40:32] [PASSED] 0xA7AA (ALDERLAKE_P)
[16:40:32] [PASSED] 0xA7AB (ALDERLAKE_P)
[16:40:32] [PASSED] 0xA780 (ALDERLAKE_S)
[16:40:32] [PASSED] 0xA781 (ALDERLAKE_S)
[16:40:32] [PASSED] 0xA782 (ALDERLAKE_S)
[16:40:32] [PASSED] 0xA783 (ALDERLAKE_S)
[16:40:32] [PASSED] 0xA788 (ALDERLAKE_S)
[16:40:32] [PASSED] 0xA789 (ALDERLAKE_S)
[16:40:32] [PASSED] 0xA78A (ALDERLAKE_S)
[16:40:32] [PASSED] 0xA78B (ALDERLAKE_S)
[16:40:32] [PASSED] 0x4905 (DG1)
[16:40:32] [PASSED] 0x4906 (DG1)
[16:40:32] [PASSED] 0x4907 (DG1)
[16:40:32] [PASSED] 0x4908 (DG1)
[16:40:32] [PASSED] 0x4909 (DG1)
[16:40:32] [PASSED] 0x56C0 (DG2)
[16:40:32] [PASSED] 0x56C2 (DG2)
[16:40:32] [PASSED] 0x56C1 (DG2)
[16:40:32] [PASSED] 0x7D51 (METEORLAKE)
[16:40:32] [PASSED] 0x7DD1 (METEORLAKE)
[16:40:32] [PASSED] 0x7D41 (METEORLAKE)
[16:40:32] [PASSED] 0x7D67 (METEORLAKE)
[16:40:32] [PASSED] 0xB640 (METEORLAKE)
[16:40:32] [PASSED] 0x56A0 (DG2)
[16:40:32] [PASSED] 0x56A1 (DG2)
[16:40:32] [PASSED] 0x56A2 (DG2)
[16:40:32] [PASSED] 0x56BE (DG2)
[16:40:32] [PASSED] 0x56BF (DG2)
[16:40:32] [PASSED] 0x5690 (DG2)
[16:40:32] [PASSED] 0x5691 (DG2)
[16:40:32] [PASSED] 0x5692 (DG2)
[16:40:32] [PASSED] 0x56A5 (DG2)
[16:40:32] [PASSED] 0x56A6 (DG2)
[16:40:32] [PASSED] 0x56B0 (DG2)
[16:40:32] [PASSED] 0x56B1 (DG2)
[16:40:32] [PASSED] 0x56BA (DG2)
[16:40:32] [PASSED] 0x56BB (DG2)
[16:40:32] [PASSED] 0x56BC (DG2)
[16:40:32] [PASSED] 0x56BD (DG2)
[16:40:32] [PASSED] 0x5693 (DG2)
[16:40:32] [PASSED] 0x5694 (DG2)
[16:40:32] [PASSED] 0x5695 (DG2)
[16:40:32] [PASSED] 0x56A3 (DG2)
[16:40:32] [PASSED] 0x56A4 (DG2)
[16:40:32] [PASSED] 0x56B2 (DG2)
[16:40:32] [PASSED] 0x56B3 (DG2)
[16:40:32] [PASSED] 0x5696 (DG2)
[16:40:32] [PASSED] 0x5697 (DG2)
[16:40:32] [PASSED] 0xB69 (PVC)
[16:40:32] [PASSED] 0xB6E (PVC)
[16:40:32] [PASSED] 0xBD4 (PVC)
[16:40:32] [PASSED] 0xBD5 (PVC)
[16:40:32] [PASSED] 0xBD6 (PVC)
[16:40:32] [PASSED] 0xBD7 (PVC)
[16:40:32] [PASSED] 0xBD8 (PVC)
[16:40:32] [PASSED] 0xBD9 (PVC)
[16:40:32] [PASSED] 0xBDA (PVC)
[16:40:32] [PASSED] 0xBDB (PVC)
[16:40:32] [PASSED] 0xBE0 (PVC)
[16:40:32] [PASSED] 0xBE1 (PVC)
[16:40:32] [PASSED] 0xBE5 (PVC)
[16:40:32] [PASSED] 0x7D40 (METEORLAKE)
[16:40:32] [PASSED] 0x7D45 (METEORLAKE)
[16:40:32] [PASSED] 0x7D55 (METEORLAKE)
[16:40:32] [PASSED] 0x7D60 (METEORLAKE)
[16:40:32] [PASSED] 0x7DD5 (METEORLAKE)
[16:40:32] [PASSED] 0x6420 (LUNARLAKE)
[16:40:32] [PASSED] 0x64A0 (LUNARLAKE)
[16:40:32] [PASSED] 0x64B0 (LUNARLAKE)
[16:40:32] [PASSED] 0xE202 (BATTLEMAGE)
[16:40:32] [PASSED] 0xE209 (BATTLEMAGE)
[16:40:32] [PASSED] 0xE20B (BATTLEMAGE)
[16:40:32] [PASSED] 0xE20C (BATTLEMAGE)
[16:40:32] [PASSED] 0xE20D (BATTLEMAGE)
[16:40:32] [PASSED] 0xE210 (BATTLEMAGE)
[16:40:32] [PASSED] 0xE211 (BATTLEMAGE)
[16:40:32] [PASSED] 0xE212 (BATTLEMAGE)
[16:40:32] [PASSED] 0xE216 (BATTLEMAGE)
[16:40:32] [PASSED] 0xE220 (BATTLEMAGE)
[16:40:32] [PASSED] 0xE221 (BATTLEMAGE)
[16:40:32] [PASSED] 0xE222 (BATTLEMAGE)
[16:40:32] [PASSED] 0xE223 (BATTLEMAGE)
[16:40:32] [PASSED] 0xB080 (PANTHERLAKE)
[16:40:32] [PASSED] 0xB081 (PANTHERLAKE)
[16:40:32] [PASSED] 0xB082 (PANTHERLAKE)
[16:40:32] [PASSED] 0xB083 (PANTHERLAKE)
[16:40:32] [PASSED] 0xB084 (PANTHERLAKE)
[16:40:32] [PASSED] 0xB085 (PANTHERLAKE)
[16:40:32] [PASSED] 0xB086 (PANTHERLAKE)
[16:40:32] [PASSED] 0xB087 (PANTHERLAKE)
[16:40:32] [PASSED] 0xB08F (PANTHERLAKE)
[16:40:32] [PASSED] 0xB090 (PANTHERLAKE)
[16:40:32] [PASSED] 0xB0A0 (PANTHERLAKE)
[16:40:32] [PASSED] 0xB0B0 (PANTHERLAKE)
[16:40:32] [PASSED] 0xFD80 (PANTHERLAKE)
[16:40:32] [PASSED] 0xFD81 (PANTHERLAKE)
[16:40:32] [PASSED] 0xD740 (NOVALAKE_S)
[16:40:32] [PASSED] 0xD741 (NOVALAKE_S)
[16:40:32] [PASSED] 0xD742 (NOVALAKE_S)
[16:40:32] [PASSED] 0xD743 (NOVALAKE_S)
[16:40:32] [PASSED] 0xD744 (NOVALAKE_S)
[16:40:32] [PASSED] 0xD745 (NOVALAKE_S)
[16:40:32] [PASSED] 0x674C (CRESCENTISLAND)
[16:40:32] [PASSED] 0x674D (CRESCENTISLAND)
[16:40:32] [PASSED] 0x674E (CRESCENTISLAND)
[16:40:32] [PASSED] 0x674F (CRESCENTISLAND)
[16:40:32] [PASSED] 0x6750 (CRESCENTISLAND)
[16:40:32] [PASSED] 0xD750 (NOVALAKE_P)
[16:40:32] [PASSED] 0xD751 (NOVALAKE_P)
[16:40:32] [PASSED] 0xD752 (NOVALAKE_P)
[16:40:32] [PASSED] 0xD753 (NOVALAKE_P)
[16:40:32] [PASSED] 0xD754 (NOVALAKE_P)
[16:40:32] [PASSED] 0xD755 (NOVALAKE_P)
[16:40:32] [PASSED] 0xD756 (NOVALAKE_P)
[16:40:32] [PASSED] 0xD757 (NOVALAKE_P)
[16:40:32] [PASSED] 0xD75F (NOVALAKE_P)
[16:40:32] =============== [PASSED] check_platform_desc ===============
[16:40:32] ===================== [PASSED] xe_pci ======================
[16:40:32] =================== xe_rtp (2 subtests) ====================
[16:40:32] =============== xe_rtp_process_to_sr_tests  ================
[16:40:32] [PASSED] coalesce-same-reg
[16:40:32] [PASSED] no-match-no-add
[16:40:32] [PASSED] match-or
[16:40:32] [PASSED] match-or-xfail
[16:40:32] [PASSED] no-match-no-add-multiple-rules
[16:40:32] [PASSED] two-regs-two-entries
[16:40:32] [PASSED] clr-one-set-other
[16:40:32] [PASSED] set-field
[16:40:32] [PASSED] conflict-duplicate
[16:40:32] [PASSED] conflict-not-disjoint
[16:40:32] [PASSED] conflict-reg-type
[16:40:32] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[16:40:32] ================== xe_rtp_process_tests  ===================
[16:40:32] [PASSED] active1
[16:40:32] [PASSED] active2
[16:40:32] [PASSED] active-inactive
[16:40:32] [PASSED] inactive-active
[16:40:32] [PASSED] inactive-1st_or_active-inactive
[16:40:32] [PASSED] inactive-2nd_or_active-inactive
[16:40:32] [PASSED] inactive-last_or_active-inactive
[16:40:32] [PASSED] inactive-no_or_active-inactive
[16:40:32] ============== [PASSED] xe_rtp_process_tests ===============
[16:40:32] ===================== [PASSED] xe_rtp ======================
[16:40:32] ==================== xe_wa (1 subtest) =====================
[16:40:32] ======================== xe_wa_gt  =========================
[16:40:32] [PASSED] TIGERLAKE B0
[16:40:32] [PASSED] DG1 A0
[16:40:32] [PASSED] DG1 B0
[16:40:32] [PASSED] ALDERLAKE_S A0
[16:40:32] [PASSED] ALDERLAKE_S B0
[16:40:32] [PASSED] ALDERLAKE_S C0
[16:40:32] [PASSED] ALDERLAKE_S D0
[16:40:32] [PASSED] ALDERLAKE_P A0
[16:40:32] [PASSED] ALDERLAKE_P B0
[16:40:32] [PASSED] ALDERLAKE_P C0
[16:40:32] [PASSED] ALDERLAKE_S RPLS D0
[16:40:32] [PASSED] ALDERLAKE_P RPLU E0
[16:40:32] [PASSED] DG2 G10 C0
[16:40:32] [PASSED] DG2 G11 B1
[16:40:32] [PASSED] DG2 G12 A1
[16:40:32] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[16:40:32] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[16:40:32] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[16:40:32] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[16:40:32] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[16:40:32] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[16:40:32] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[16:40:32] ==================== [PASSED] xe_wa_gt =====================
[16:40:32] ====================== [PASSED] xe_wa ======================
[16:40:32] ============================================================
[16:40:32] Testing complete. Ran 601 tests: passed: 583, skipped: 18
[16:40:32] Elapsed time: 36.206s total, 4.267s configuring, 31.323s building, 0.604s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[16:40:32] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:40:34] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[16:40:58] Starting KUnit Kernel (1/1)...
[16:40:58] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[16:40:58] ============ drm_test_pick_cmdline (2 subtests) ============
[16:40:58] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[16:40:58] =============== drm_test_pick_cmdline_named  ===============
[16:40:58] [PASSED] NTSC
[16:40:58] [PASSED] NTSC-J
[16:40:58] [PASSED] PAL
[16:40:58] [PASSED] PAL-M
[16:40:58] =========== [PASSED] drm_test_pick_cmdline_named ===========
[16:40:58] ============== [PASSED] drm_test_pick_cmdline ==============
[16:40:58] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[16:40:58] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[16:40:58] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[16:40:58] =========== drm_validate_clone_mode (2 subtests) ===========
[16:40:58] ============== drm_test_check_in_clone_mode  ===============
[16:40:58] [PASSED] in_clone_mode
[16:40:58] [PASSED] not_in_clone_mode
[16:40:58] ========== [PASSED] drm_test_check_in_clone_mode ===========
[16:40:58] =============== drm_test_check_valid_clones  ===============
[16:40:58] [PASSED] not_in_clone_mode
[16:40:58] [PASSED] valid_clone
[16:40:58] [PASSED] invalid_clone
[16:40:58] =========== [PASSED] drm_test_check_valid_clones ===========
[16:40:58] ============= [PASSED] drm_validate_clone_mode =============
[16:40:58] ============= drm_validate_modeset (1 subtest) =============
[16:40:58] [PASSED] drm_test_check_connector_changed_modeset
[16:40:58] ============== [PASSED] drm_validate_modeset ===============
[16:40:58] ====== drm_test_bridge_get_current_state (2 subtests) ======
[16:40:58] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[16:40:58] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[16:40:58] ======== [PASSED] drm_test_bridge_get_current_state ========
[16:40:58] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[16:40:58] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[16:40:58] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[16:40:58] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[16:40:58] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[16:40:58] ============== drm_bridge_alloc (2 subtests) ===============
[16:40:58] [PASSED] drm_test_drm_bridge_alloc_basic
[16:40:58] [PASSED] drm_test_drm_bridge_alloc_get_put
[16:40:58] ================ [PASSED] drm_bridge_alloc =================
[16:40:58] ============= drm_cmdline_parser (40 subtests) =============
[16:40:58] [PASSED] drm_test_cmdline_force_d_only
[16:40:58] [PASSED] drm_test_cmdline_force_D_only_dvi
[16:40:58] [PASSED] drm_test_cmdline_force_D_only_hdmi
[16:40:58] [PASSED] drm_test_cmdline_force_D_only_not_digital
[16:40:58] [PASSED] drm_test_cmdline_force_e_only
[16:40:58] [PASSED] drm_test_cmdline_res
[16:40:58] [PASSED] drm_test_cmdline_res_vesa
[16:40:58] [PASSED] drm_test_cmdline_res_vesa_rblank
[16:40:58] [PASSED] drm_test_cmdline_res_rblank
[16:40:58] [PASSED] drm_test_cmdline_res_bpp
[16:40:58] [PASSED] drm_test_cmdline_res_refresh
[16:40:58] [PASSED] drm_test_cmdline_res_bpp_refresh
[16:40:58] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[16:40:58] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[16:40:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[16:40:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[16:40:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[16:40:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[16:40:58] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[16:40:58] [PASSED] drm_test_cmdline_res_margins_force_on
[16:40:58] [PASSED] drm_test_cmdline_res_vesa_margins
[16:40:58] [PASSED] drm_test_cmdline_name
[16:40:58] [PASSED] drm_test_cmdline_name_bpp
[16:40:58] [PASSED] drm_test_cmdline_name_option
[16:40:58] [PASSED] drm_test_cmdline_name_bpp_option
[16:40:58] [PASSED] drm_test_cmdline_rotate_0
[16:40:58] [PASSED] drm_test_cmdline_rotate_90
[16:40:58] [PASSED] drm_test_cmdline_rotate_180
[16:40:58] [PASSED] drm_test_cmdline_rotate_270
[16:40:58] [PASSED] drm_test_cmdline_hmirror
[16:40:58] [PASSED] drm_test_cmdline_vmirror
[16:40:58] [PASSED] drm_test_cmdline_margin_options
[16:40:58] [PASSED] drm_test_cmdline_multiple_options
[16:40:58] [PASSED] drm_test_cmdline_bpp_extra_and_option
[16:40:58] [PASSED] drm_test_cmdline_extra_and_option
[16:40:58] [PASSED] drm_test_cmdline_freestanding_options
[16:40:58] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[16:40:58] [PASSED] drm_test_cmdline_panel_orientation
[16:40:58] ================ drm_test_cmdline_invalid  =================
[16:40:58] [PASSED] margin_only
[16:40:58] [PASSED] interlace_only
[16:40:58] [PASSED] res_missing_x
[16:40:58] [PASSED] res_missing_y
[16:40:58] [PASSED] res_bad_y
[16:40:58] [PASSED] res_missing_y_bpp
[16:40:58] [PASSED] res_bad_bpp
[16:40:58] [PASSED] res_bad_refresh
[16:40:58] [PASSED] res_bpp_refresh_force_on_off
[16:40:58] [PASSED] res_invalid_mode
[16:40:58] [PASSED] res_bpp_wrong_place_mode
[16:40:58] [PASSED] name_bpp_refresh
[16:40:58] [PASSED] name_refresh
[16:40:58] [PASSED] name_refresh_wrong_mode
[16:40:58] [PASSED] name_refresh_invalid_mode
[16:40:58] [PASSED] rotate_multiple
[16:40:58] [PASSED] rotate_invalid_val
[16:40:58] [PASSED] rotate_truncated
[16:40:58] [PASSED] invalid_option
[16:40:58] [PASSED] invalid_tv_option
[16:40:58] [PASSED] truncated_tv_option
[16:40:58] ============ [PASSED] drm_test_cmdline_invalid =============
[16:40:58] =============== drm_test_cmdline_tv_options  ===============
[16:40:58] [PASSED] NTSC
[16:40:58] [PASSED] NTSC_443
[16:40:58] [PASSED] NTSC_J
[16:40:58] [PASSED] PAL
[16:40:58] [PASSED] PAL_M
[16:40:58] [PASSED] PAL_N
[16:40:58] [PASSED] SECAM
[16:40:58] [PASSED] MONO_525
[16:40:58] [PASSED] MONO_625
[16:40:58] =========== [PASSED] drm_test_cmdline_tv_options ===========
[16:40:58] =============== [PASSED] drm_cmdline_parser ================
[16:40:58] ========== drmm_connector_hdmi_init (20 subtests) ==========
[16:40:58] [PASSED] drm_test_connector_hdmi_init_valid
[16:40:58] [PASSED] drm_test_connector_hdmi_init_bpc_8
[16:40:58] [PASSED] drm_test_connector_hdmi_init_bpc_10
[16:40:58] [PASSED] drm_test_connector_hdmi_init_bpc_12
[16:40:58] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[16:40:58] [PASSED] drm_test_connector_hdmi_init_bpc_null
[16:40:58] [PASSED] drm_test_connector_hdmi_init_formats_empty
[16:40:58] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[16:40:58] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[16:40:58] [PASSED] supported_formats=0x9 yuv420_allowed=1
[16:40:58] [PASSED] supported_formats=0x9 yuv420_allowed=0
[16:40:58] [PASSED] supported_formats=0x5 yuv420_allowed=1
[16:40:58] [PASSED] supported_formats=0x5 yuv420_allowed=0
[16:40:58] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[16:40:58] [PASSED] drm_test_connector_hdmi_init_null_ddc
[16:40:58] [PASSED] drm_test_connector_hdmi_init_null_product
[16:40:58] [PASSED] drm_test_connector_hdmi_init_null_vendor
[16:40:58] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[16:40:58] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[16:40:58] [PASSED] drm_test_connector_hdmi_init_product_valid
[16:40:58] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[16:40:58] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[16:40:58] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[16:40:58] ========= drm_test_connector_hdmi_init_type_valid  =========
[16:40:58] [PASSED] HDMI-A
[16:40:58] [PASSED] HDMI-B
[16:40:58] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[16:40:58] ======== drm_test_connector_hdmi_init_type_invalid  ========
[16:40:58] [PASSED] Unknown
[16:40:58] [PASSED] VGA
[16:40:58] [PASSED] DVI-I
[16:40:58] [PASSED] DVI-D
[16:40:58] [PASSED] DVI-A
[16:40:58] [PASSED] Composite
[16:40:58] [PASSED] SVIDEO
[16:40:58] [PASSED] LVDS
[16:40:58] [PASSED] Component
[16:40:58] [PASSED] DIN
[16:40:58] [PASSED] DP
[16:40:58] [PASSED] TV
[16:40:58] [PASSED] eDP
[16:40:58] [PASSED] Virtual
[16:40:58] [PASSED] DSI
[16:40:58] [PASSED] DPI
[16:40:58] [PASSED] Writeback
[16:40:58] [PASSED] SPI
[16:40:58] [PASSED] USB
[16:40:58] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[16:40:58] ============ [PASSED] drmm_connector_hdmi_init =============
[16:40:58] ============= drmm_connector_init (3 subtests) =============
[16:40:58] [PASSED] drm_test_drmm_connector_init
[16:40:58] [PASSED] drm_test_drmm_connector_init_null_ddc
[16:40:58] ========= drm_test_drmm_connector_init_type_valid  =========
[16:40:58] [PASSED] Unknown
[16:40:58] [PASSED] VGA
[16:40:58] [PASSED] DVI-I
[16:40:58] [PASSED] DVI-D
[16:40:58] [PASSED] DVI-A
[16:40:58] [PASSED] Composite
[16:40:58] [PASSED] SVIDEO
[16:40:58] [PASSED] LVDS
[16:40:58] [PASSED] Component
[16:40:58] [PASSED] DIN
[16:40:58] [PASSED] DP
[16:40:58] [PASSED] HDMI-A
[16:40:58] [PASSED] HDMI-B
[16:40:58] [PASSED] TV
[16:40:58] [PASSED] eDP
[16:40:58] [PASSED] Virtual
[16:40:58] [PASSED] DSI
[16:40:58] [PASSED] DPI
[16:40:58] [PASSED] Writeback
[16:40:58] [PASSED] SPI
[16:40:58] [PASSED] USB
[16:40:58] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[16:40:58] =============== [PASSED] drmm_connector_init ===============
[16:40:58] ========= drm_connector_dynamic_init (6 subtests) ==========
[16:40:58] [PASSED] drm_test_drm_connector_dynamic_init
[16:40:58] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[16:40:58] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[16:40:58] [PASSED] drm_test_drm_connector_dynamic_init_properties
[16:40:58] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[16:40:58] [PASSED] Unknown
[16:40:58] [PASSED] VGA
[16:40:58] [PASSED] DVI-I
[16:40:58] [PASSED] DVI-D
[16:40:58] [PASSED] DVI-A
[16:40:58] [PASSED] Composite
[16:40:58] [PASSED] SVIDEO
[16:40:58] [PASSED] LVDS
[16:40:58] [PASSED] Component
[16:40:58] [PASSED] DIN
[16:40:58] [PASSED] DP
[16:40:58] [PASSED] HDMI-A
[16:40:58] [PASSED] HDMI-B
[16:40:58] [PASSED] TV
[16:40:58] [PASSED] eDP
[16:40:58] [PASSED] Virtual
[16:40:58] [PASSED] DSI
[16:40:58] [PASSED] DPI
[16:40:58] [PASSED] Writeback
[16:40:58] [PASSED] SPI
[16:40:58] [PASSED] USB
[16:40:58] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[16:40:58] ======== drm_test_drm_connector_dynamic_init_name  =========
[16:40:58] [PASSED] Unknown
[16:40:58] [PASSED] VGA
[16:40:58] [PASSED] DVI-I
[16:40:58] [PASSED] DVI-D
[16:40:58] [PASSED] DVI-A
[16:40:58] [PASSED] Composite
[16:40:58] [PASSED] SVIDEO
[16:40:58] [PASSED] LVDS
[16:40:58] [PASSED] Component
[16:40:58] [PASSED] DIN
[16:40:58] [PASSED] DP
[16:40:58] [PASSED] HDMI-A
[16:40:58] [PASSED] HDMI-B
[16:40:58] [PASSED] TV
[16:40:58] [PASSED] eDP
[16:40:58] [PASSED] Virtual
[16:40:58] [PASSED] DSI
[16:40:58] [PASSED] DPI
[16:40:58] [PASSED] Writeback
[16:40:58] [PASSED] SPI
[16:40:58] [PASSED] USB
[16:40:58] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[16:40:58] =========== [PASSED] drm_connector_dynamic_init ============
[16:40:58] ==== drm_connector_dynamic_register_early (4 subtests) =====
[16:40:58] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[16:40:58] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[16:40:58] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[16:40:58] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[16:40:58] ====== [PASSED] drm_connector_dynamic_register_early =======
[16:40:58] ======= drm_connector_dynamic_register (7 subtests) ========
[16:40:58] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[16:40:58] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[16:40:58] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[16:40:58] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[16:40:58] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[16:40:58] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[16:40:58] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[16:40:58] ========= [PASSED] drm_connector_dynamic_register ==========
[16:40:58] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[16:40:58] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[16:40:58] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[16:40:58] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[16:40:58] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[16:40:58] ========== drm_test_get_tv_mode_from_name_valid  ===========
[16:40:58] [PASSED] NTSC
[16:40:58] [PASSED] NTSC-443
[16:40:58] [PASSED] NTSC-J
[16:40:58] [PASSED] PAL
[16:40:58] [PASSED] PAL-M
[16:40:58] [PASSED] PAL-N
[16:40:58] [PASSED] SECAM
[16:40:58] [PASSED] Mono
[16:40:58] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[16:40:58] [PASSED] drm_test_get_tv_mode_from_name_truncated
[16:40:58] ============ [PASSED] drm_get_tv_mode_from_name ============
[16:40:58] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[16:40:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[16:40:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[16:40:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[16:40:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[16:40:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[16:40:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[16:40:58] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[16:40:58] [PASSED] VIC 96
[16:40:58] [PASSED] VIC 97
[16:40:58] [PASSED] VIC 101
[16:40:58] [PASSED] VIC 102
[16:40:58] [PASSED] VIC 106
[16:40:58] [PASSED] VIC 107
[16:40:58] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[16:40:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[16:40:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[16:40:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[16:40:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[16:40:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[16:40:58] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[16:40:58] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[16:40:58] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[16:40:58] [PASSED] Automatic
[16:40:58] [PASSED] Full
[16:40:58] [PASSED] Limited 16:235
[16:40:58] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[16:40:58] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[16:40:58] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[16:40:58] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[16:40:58] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[16:40:58] [PASSED] RGB
[16:40:58] [PASSED] YUV 4:2:0
[16:40:58] [PASSED] YUV 4:2:2
[16:40:58] [PASSED] YUV 4:4:4
[16:40:58] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[16:40:58] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[16:40:58] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[16:40:58] ============= drm_damage_helper (21 subtests) ==============
[16:40:58] [PASSED] drm_test_damage_iter_no_damage
[16:40:58] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[16:40:58] [PASSED] drm_test_damage_iter_no_damage_src_moved
[16:40:58] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[16:40:58] [PASSED] drm_test_damage_iter_no_damage_not_visible
[16:40:58] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[16:40:58] [PASSED] drm_test_damage_iter_no_damage_no_fb
[16:40:58] [PASSED] drm_test_damage_iter_simple_damage
[16:40:58] [PASSED] drm_test_damage_iter_single_damage
[16:40:58] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[16:40:58] [PASSED] drm_test_damage_iter_single_damage_outside_src
[16:40:58] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[16:40:58] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[16:40:58] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[16:40:58] [PASSED] drm_test_damage_iter_single_damage_src_moved
[16:40:58] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[16:40:58] [PASSED] drm_test_damage_iter_damage
[16:40:58] [PASSED] drm_test_damage_iter_damage_one_intersect
[16:40:58] [PASSED] drm_test_damage_iter_damage_one_outside
[16:40:58] [PASSED] drm_test_damage_iter_damage_src_moved
[16:40:58] [PASSED] drm_test_damage_iter_damage_not_visible
[16:40:58] ================ [PASSED] drm_damage_helper ================
[16:40:58] ============== drm_dp_mst_helper (3 subtests) ==============
[16:40:58] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[16:40:58] [PASSED] Clock 154000 BPP 30 DSC disabled
[16:40:58] [PASSED] Clock 234000 BPP 30 DSC disabled
[16:40:58] [PASSED] Clock 297000 BPP 24 DSC disabled
[16:40:58] [PASSED] Clock 332880 BPP 24 DSC enabled
[16:40:58] [PASSED] Clock 324540 BPP 24 DSC enabled
[16:40:58] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[16:40:58] ============== drm_test_dp_mst_calc_pbn_div  ===============
[16:40:58] [PASSED] Link rate 2000000 lane count 4
[16:40:58] [PASSED] Link rate 2000000 lane count 2
[16:40:58] [PASSED] Link rate 2000000 lane count 1
[16:40:58] [PASSED] Link rate 1350000 lane count 4
[16:40:58] [PASSED] Link rate 1350000 lane count 2
[16:40:58] [PASSED] Link rate 1350000 lane count 1
[16:40:58] [PASSED] Link rate 1000000 lane count 4
[16:40:58] [PASSED] Link rate 1000000 lane count 2
[16:40:58] [PASSED] Link rate 1000000 lane count 1
[16:40:58] [PASSED] Link rate 810000 lane count 4
[16:40:58] [PASSED] Link rate 810000 lane count 2
[16:40:58] [PASSED] Link rate 810000 lane count 1
[16:40:58] [PASSED] Link rate 540000 lane count 4
[16:40:58] [PASSED] Link rate 540000 lane count 2
[16:40:58] [PASSED] Link rate 540000 lane count 1
[16:40:58] [PASSED] Link rate 270000 lane count 4
[16:40:58] [PASSED] Link rate 270000 lane count 2
[16:40:58] [PASSED] Link rate 270000 lane count 1
[16:40:58] [PASSED] Link rate 162000 lane count 4
[16:40:58] [PASSED] Link rate 162000 lane count 2
[16:40:58] [PASSED] Link rate 162000 lane count 1
[16:40:58] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[16:40:58] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[16:40:58] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[16:40:58] [PASSED] DP_POWER_UP_PHY with port number
[16:40:58] [PASSED] DP_POWER_DOWN_PHY with port number
[16:40:58] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[16:40:58] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[16:40:58] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[16:40:58] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[16:40:58] [PASSED] DP_QUERY_PAYLOAD with port number
[16:40:58] [PASSED] DP_QUERY_PAYLOAD with VCPI
[16:40:58] [PASSED] DP_REMOTE_DPCD_READ with port number
[16:40:58] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[16:40:58] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[16:40:58] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[16:40:58] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[16:40:58] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[16:40:58] [PASSED] DP_REMOTE_I2C_READ with port number
[16:40:58] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[16:40:58] [PASSED] DP_REMOTE_I2C_READ with transactions array
[16:40:58] [PASSED] DP_REMOTE_I2C_WRITE with port number
[16:40:58] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[16:40:58] [PASSED] DP_REMOTE_I2C_WRITE with data array
[16:40:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[16:40:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[16:40:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[16:40:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[16:40:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[16:40:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[16:40:58] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[16:40:58] ================ [PASSED] drm_dp_mst_helper ================
[16:40:58] ================== drm_exec (7 subtests) ===================
[16:40:58] [PASSED] sanitycheck
[16:40:58] [PASSED] test_lock
[16:40:58] [PASSED] test_lock_unlock
[16:40:58] [PASSED] test_duplicates
[16:40:58] [PASSED] test_prepare
[16:40:58] [PASSED] test_prepare_array
[16:40:58] [PASSED] test_multiple_loops
[16:40:58] ==================== [PASSED] drm_exec =====================
[16:40:58] =========== drm_format_helper_test (17 subtests) ===========
[16:40:58] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[16:40:58] [PASSED] single_pixel_source_buffer
[16:40:58] [PASSED] single_pixel_clip_rectangle
[16:40:58] [PASSED] well_known_colors
[16:40:58] [PASSED] destination_pitch
[16:40:58] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[16:40:58] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[16:40:58] [PASSED] single_pixel_source_buffer
[16:40:58] [PASSED] single_pixel_clip_rectangle
[16:40:58] [PASSED] well_known_colors
[16:40:58] [PASSED] destination_pitch
[16:40:58] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[16:40:58] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[16:40:58] [PASSED] single_pixel_source_buffer
[16:40:58] [PASSED] single_pixel_clip_rectangle
[16:40:58] [PASSED] well_known_colors
[16:40:58] [PASSED] destination_pitch
[16:40:58] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[16:40:58] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[16:40:58] [PASSED] single_pixel_source_buffer
[16:40:58] [PASSED] single_pixel_clip_rectangle
[16:40:58] [PASSED] well_known_colors
[16:40:58] [PASSED] destination_pitch
[16:40:58] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[16:40:58] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[16:40:58] [PASSED] single_pixel_source_buffer
[16:40:58] [PASSED] single_pixel_clip_rectangle
[16:40:58] [PASSED] well_known_colors
[16:40:58] [PASSED] destination_pitch
[16:40:58] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[16:40:58] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[16:40:58] [PASSED] single_pixel_source_buffer
[16:40:58] [PASSED] single_pixel_clip_rectangle
[16:40:58] [PASSED] well_known_colors
[16:40:58] [PASSED] destination_pitch
[16:40:58] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[16:40:58] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[16:40:58] [PASSED] single_pixel_source_buffer
[16:40:58] [PASSED] single_pixel_clip_rectangle
[16:40:58] [PASSED] well_known_colors
[16:40:58] [PASSED] destination_pitch
[16:40:58] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[16:40:58] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[16:40:58] [PASSED] single_pixel_source_buffer
[16:40:58] [PASSED] single_pixel_clip_rectangle
[16:40:58] [PASSED] well_known_colors
[16:40:58] [PASSED] destination_pitch
[16:40:58] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[16:40:58] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[16:40:58] [PASSED] single_pixel_source_buffer
[16:40:58] [PASSED] single_pixel_clip_rectangle
[16:40:58] [PASSED] well_known_colors
[16:40:58] [PASSED] destination_pitch
[16:40:58] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[16:40:58] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[16:40:58] [PASSED] single_pixel_source_buffer
[16:40:58] [PASSED] single_pixel_clip_rectangle
[16:40:58] [PASSED] well_known_colors
[16:40:58] [PASSED] destination_pitch
[16:40:58] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[16:40:58] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[16:40:58] [PASSED] single_pixel_source_buffer
[16:40:58] [PASSED] single_pixel_clip_rectangle
[16:40:58] [PASSED] well_known_colors
[16:40:58] [PASSED] destination_pitch
[16:40:58] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[16:40:58] ============== drm_test_fb_xrgb8888_to_mono  ===============
[16:40:58] [PASSED] single_pixel_source_buffer
[16:40:58] [PASSED] single_pixel_clip_rectangle
[16:40:58] [PASSED] well_known_colors
[16:40:58] [PASSED] destination_pitch
[16:40:58] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[16:40:58] ==================== drm_test_fb_swab  =====================
[16:40:58] [PASSED] single_pixel_source_buffer
[16:40:58] [PASSED] single_pixel_clip_rectangle
[16:40:58] [PASSED] well_known_colors
[16:40:58] [PASSED] destination_pitch
[16:40:58] ================ [PASSED] drm_test_fb_swab =================
[16:40:58] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[16:40:58] [PASSED] single_pixel_source_buffer
[16:40:58] [PASSED] single_pixel_clip_rectangle
[16:40:58] [PASSED] well_known_colors
[16:40:58] [PASSED] destination_pitch
[16:40:58] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[16:40:58] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[16:40:58] [PASSED] single_pixel_source_buffer
[16:40:58] [PASSED] single_pixel_clip_rectangle
[16:40:58] [PASSED] well_known_colors
[16:40:58] [PASSED] destination_pitch
[16:40:58] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[16:40:58] ================= drm_test_fb_clip_offset  =================
[16:40:58] [PASSED] pass through
[16:40:58] [PASSED] horizontal offset
[16:40:58] [PASSED] vertical offset
[16:40:58] [PASSED] horizontal and vertical offset
[16:40:58] [PASSED] horizontal offset (custom pitch)
[16:40:58] [PASSED] vertical offset (custom pitch)
[16:40:58] [PASSED] horizontal and vertical offset (custom pitch)
[16:40:58] ============= [PASSED] drm_test_fb_clip_offset =============
[16:40:58] =================== drm_test_fb_memcpy  ====================
[16:40:58] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[16:40:58] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[16:40:58] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[16:40:58] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[16:40:58] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[16:40:58] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[16:40:58] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[16:40:58] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[16:40:58] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[16:40:58] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[16:40:58] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[16:40:58] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[16:40:58] =============== [PASSED] drm_test_fb_memcpy ================
[16:40:58] ============= [PASSED] drm_format_helper_test ==============
[16:40:58] ================= drm_format (18 subtests) =================
[16:40:58] [PASSED] drm_test_format_block_width_invalid
[16:40:58] [PASSED] drm_test_format_block_width_one_plane
[16:40:58] [PASSED] drm_test_format_block_width_two_plane
[16:40:58] [PASSED] drm_test_format_block_width_three_plane
[16:40:58] [PASSED] drm_test_format_block_width_tiled
[16:40:58] [PASSED] drm_test_format_block_height_invalid
[16:40:58] [PASSED] drm_test_format_block_height_one_plane
[16:40:58] [PASSED] drm_test_format_block_height_two_plane
[16:40:58] [PASSED] drm_test_format_block_height_three_plane
[16:40:58] [PASSED] drm_test_format_block_height_tiled
[16:40:58] [PASSED] drm_test_format_min_pitch_invalid
[16:40:58] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[16:40:58] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[16:40:58] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[16:40:58] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[16:40:58] [PASSED] drm_test_format_min_pitch_two_plane
[16:40:58] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[16:40:58] [PASSED] drm_test_format_min_pitch_tiled
[16:40:58] =================== [PASSED] drm_format ====================
[16:40:58] ============== drm_framebuffer (10 subtests) ===============
[16:40:58] ========== drm_test_framebuffer_check_src_coords  ==========
[16:40:58] [PASSED] Success: source fits into fb
[16:40:58] [PASSED] Fail: overflowing fb with x-axis coordinate
[16:40:58] [PASSED] Fail: overflowing fb with y-axis coordinate
[16:40:58] [PASSED] Fail: overflowing fb with source width
[16:40:58] [PASSED] Fail: overflowing fb with source height
[16:40:58] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[16:40:58] [PASSED] drm_test_framebuffer_cleanup
[16:40:58] =============== drm_test_framebuffer_create  ===============
[16:40:58] [PASSED] ABGR8888 normal sizes
[16:40:58] [PASSED] ABGR8888 max sizes
[16:40:58] [PASSED] ABGR8888 pitch greater than min required
[16:40:58] [PASSED] ABGR8888 pitch less than min required
[16:40:58] [PASSED] ABGR8888 Invalid width
[16:40:58] [PASSED] ABGR8888 Invalid buffer handle
[16:40:58] [PASSED] No pixel format
[16:40:58] [PASSED] ABGR8888 Width 0
[16:40:58] [PASSED] ABGR8888 Height 0
[16:40:58] [PASSED] ABGR8888 Out of bound height * pitch combination
[16:40:58] [PASSED] ABGR8888 Large buffer offset
[16:40:58] [PASSED] ABGR8888 Buffer offset for inexistent plane
[16:40:58] [PASSED] ABGR8888 Invalid flag
[16:40:58] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[16:40:58] [PASSED] ABGR8888 Valid buffer modifier
[16:40:58] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[16:40:58] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[16:40:58] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[16:40:58] [PASSED] NV12 Normal sizes
[16:40:58] [PASSED] NV12 Max sizes
[16:40:58] [PASSED] NV12 Invalid pitch
[16:40:58] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[16:40:58] [PASSED] NV12 different  modifier per-plane
[16:40:58] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[16:40:58] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[16:40:58] [PASSED] NV12 Modifier for inexistent plane
[16:40:58] [PASSED] NV12 Handle for inexistent plane
[16:40:58] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[16:40:58] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[16:40:58] [PASSED] YVU420 Normal sizes
[16:40:58] [PASSED] YVU420 Max sizes
[16:40:58] [PASSED] YVU420 Invalid pitch
[16:40:58] [PASSED] YVU420 Different pitches
[16:40:58] [PASSED] YVU420 Different buffer offsets/pitches
[16:40:58] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[16:40:58] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[16:40:58] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[16:40:58] [PASSED] YVU420 Valid modifier
[16:40:58] [PASSED] YVU420 Different modifiers per plane
[16:40:58] [PASSED] YVU420 Modifier for inexistent plane
[16:40:58] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[16:40:58] [PASSED] X0L2 Normal sizes
[16:40:58] [PASSED] X0L2 Max sizes
[16:40:58] [PASSED] X0L2 Invalid pitch
[16:40:58] [PASSED] X0L2 Pitch greater than minimum required
[16:40:58] [PASSED] X0L2 Handle for inexistent plane
[16:40:58] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[16:40:58] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[16:40:58] [PASSED] X0L2 Valid modifier
[16:40:58] [PASSED] X0L2 Modifier for inexistent plane
[16:40:58] =========== [PASSED] drm_test_framebuffer_create ===========
[16:40:58] [PASSED] drm_test_framebuffer_free
[16:40:58] [PASSED] drm_test_framebuffer_init
[16:40:58] [PASSED] drm_test_framebuffer_init_bad_format
[16:40:58] [PASSED] drm_test_framebuffer_init_dev_mismatch
[16:40:58] [PASSED] drm_test_framebuffer_lookup
[16:40:58] [PASSED] drm_test_framebuffer_lookup_inexistent
[16:40:58] [PASSED] drm_test_framebuffer_modifiers_not_supported
[16:40:58] ================= [PASSED] drm_framebuffer =================
[16:40:58] ================ drm_gem_shmem (8 subtests) ================
[16:40:58] [PASSED] drm_gem_shmem_test_obj_create
[16:40:58] [PASSED] drm_gem_shmem_test_obj_create_private
[16:40:58] [PASSED] drm_gem_shmem_test_pin_pages
[16:40:58] [PASSED] drm_gem_shmem_test_vmap
[16:40:58] [PASSED] drm_gem_shmem_test_get_sg_table
[16:40:58] [PASSED] drm_gem_shmem_test_get_pages_sgt
[16:40:58] [PASSED] drm_gem_shmem_test_madvise
[16:40:58] [PASSED] drm_gem_shmem_test_purge
[16:40:58] ================== [PASSED] drm_gem_shmem ==================
[16:40:58] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[16:40:58] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[16:40:58] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[16:40:58] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[16:40:58] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[16:40:58] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[16:40:58] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[16:40:58] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[16:40:58] [PASSED] Automatic
[16:40:58] [PASSED] Full
[16:40:58] [PASSED] Limited 16:235
[16:40:58] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[16:40:58] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[16:40:58] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[16:40:58] [PASSED] drm_test_check_disable_connector
[16:40:58] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[16:40:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[16:40:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[16:40:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[16:40:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[16:40:58] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[16:40:58] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[16:40:58] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[16:40:58] [PASSED] drm_test_check_output_bpc_dvi
[16:40:58] [PASSED] drm_test_check_output_bpc_format_vic_1
[16:40:58] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[16:40:58] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[16:40:58] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[16:40:58] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[16:40:58] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[16:40:58] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[16:40:58] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[16:40:58] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[16:40:58] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[16:40:58] [PASSED] drm_test_check_broadcast_rgb_value
[16:40:58] [PASSED] drm_test_check_bpc_8_value
[16:40:58] [PASSED] drm_test_check_bpc_10_value
[16:40:58] [PASSED] drm_test_check_bpc_12_value
[16:40:58] [PASSED] drm_test_check_format_value
[16:40:58] [PASSED] drm_test_check_tmds_char_value
[16:40:58] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[16:40:58] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[16:40:58] [PASSED] drm_test_check_mode_valid
[16:40:58] [PASSED] drm_test_check_mode_valid_reject
[16:40:58] [PASSED] drm_test_check_mode_valid_reject_rate
[16:40:58] [PASSED] drm_test_check_mode_valid_reject_max_clock
[16:40:58] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[16:40:58] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[16:40:58] [PASSED] drm_test_check_infoframes
[16:40:58] [PASSED] drm_test_check_reject_avi_infoframe
[16:40:58] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[16:40:58] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[16:40:58] [PASSED] drm_test_check_reject_audio_infoframe
[16:40:58] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[16:40:58] ================= drm_managed (2 subtests) =================
[16:40:58] [PASSED] drm_test_managed_release_action
[16:40:58] [PASSED] drm_test_managed_run_action
[16:40:58] =================== [PASSED] drm_managed ===================
[16:40:58] =================== drm_mm (6 subtests) ====================
[16:40:58] [PASSED] drm_test_mm_init
[16:40:58] [PASSED] drm_test_mm_debug
[16:40:58] [PASSED] drm_test_mm_align32
[16:40:58] [PASSED] drm_test_mm_align64
[16:40:58] [PASSED] drm_test_mm_lowest
[16:40:58] [PASSED] drm_test_mm_highest
[16:40:58] ===================== [PASSED] drm_mm ======================
[16:40:58] ============= drm_modes_analog_tv (5 subtests) =============
[16:40:58] [PASSED] drm_test_modes_analog_tv_mono_576i
[16:40:58] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[16:40:58] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[16:40:58] [PASSED] drm_test_modes_analog_tv_pal_576i
[16:40:58] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[16:40:58] =============== [PASSED] drm_modes_analog_tv ===============
[16:40:58] ============== drm_plane_helper (2 subtests) ===============
[16:40:58] =============== drm_test_check_plane_state  ================
[16:40:58] [PASSED] clipping_simple
[16:40:58] [PASSED] clipping_rotate_reflect
[16:40:58] [PASSED] positioning_simple
[16:40:58] [PASSED] upscaling
[16:40:58] [PASSED] downscaling
[16:40:58] [PASSED] rounding1
[16:40:58] [PASSED] rounding2
[16:40:58] [PASSED] rounding3
[16:40:58] [PASSED] rounding4
[16:40:58] =========== [PASSED] drm_test_check_plane_state ============
[16:40:58] =========== drm_test_check_invalid_plane_state  ============
[16:40:58] [PASSED] positioning_invalid
[16:40:58] [PASSED] upscaling_invalid
[16:40:58] [PASSED] downscaling_invalid
[16:40:58] ======= [PASSED] drm_test_check_invalid_plane_state ========
[16:40:58] ================ [PASSED] drm_plane_helper =================
[16:40:58] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[16:40:58] ====== drm_test_connector_helper_tv_get_modes_check  =======
[16:40:58] [PASSED] None
[16:40:58] [PASSED] PAL
[16:40:58] [PASSED] NTSC
[16:40:58] [PASSED] Both, NTSC Default
[16:40:58] [PASSED] Both, PAL Default
[16:40:58] [PASSED] Both, NTSC Default, with PAL on command-line
[16:40:58] [PASSED] Both, PAL Default, with NTSC on command-line
[16:40:58] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[16:40:58] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[16:40:58] ================== drm_rect (9 subtests) ===================
[16:40:58] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[16:40:58] [PASSED] drm_test_rect_clip_scaled_not_clipped
[16:40:58] [PASSED] drm_test_rect_clip_scaled_clipped
[16:40:58] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[16:40:58] ================= drm_test_rect_intersect  =================
[16:40:58] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[16:40:58] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[16:40:58] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[16:40:58] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[16:40:58] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[16:40:58] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[16:40:58] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[16:40:58] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[16:40:58] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[16:40:58] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[16:40:58] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[16:40:58] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[16:40:58] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[16:40:58] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[16:40:58] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[16:40:58] ============= [PASSED] drm_test_rect_intersect =============
[16:40:58] ================ drm_test_rect_calc_hscale  ================
[16:40:58] [PASSED] normal use
[16:40:58] [PASSED] out of max range
[16:40:58] [PASSED] out of min range
[16:40:58] [PASSED] zero dst
[16:40:58] [PASSED] negative src
[16:40:58] [PASSED] negative dst
[16:40:58] ============ [PASSED] drm_test_rect_calc_hscale ============
[16:40:58] ================ drm_test_rect_calc_vscale  ================
[16:40:58] [PASSED] normal use
[16:40:58] [PASSED] out of max range
[16:40:58] [PASSED] out of min range
[16:40:58] [PASSED] zero dst
[16:40:58] [PASSED] negative src
[16:40:58] [PASSED] negative dst
[16:40:58] ============ [PASSED] drm_test_rect_calc_vscale ============
[16:40:58] ================== drm_test_rect_rotate  ===================
[16:40:58] [PASSED] reflect-x
[16:40:58] [PASSED] reflect-y
[16:40:58] [PASSED] rotate-0
[16:40:58] [PASSED] rotate-90
[16:40:58] [PASSED] rotate-180
[16:40:58] [PASSED] rotate-270
[16:40:58] ============== [PASSED] drm_test_rect_rotate ===============
[16:40:58] ================ drm_test_rect_rotate_inv  =================
[16:40:58] [PASSED] reflect-x
[16:40:58] [PASSED] reflect-y
[16:40:58] [PASSED] rotate-0
[16:40:58] [PASSED] rotate-90
[16:40:58] [PASSED] rotate-180
[16:40:58] [PASSED] rotate-270
[16:40:58] ============ [PASSED] drm_test_rect_rotate_inv =============
[16:40:58] ==================== [PASSED] drm_rect =====================
[16:40:58] ============ drm_sysfb_modeset_test (1 subtest) ============
[16:40:58] ============ drm_test_sysfb_build_fourcc_list  =============
[16:40:58] [PASSED] no native formats
[16:40:58] [PASSED] XRGB8888 as native format
[16:40:58] [PASSED] remove duplicates
[16:40:58] [PASSED] convert alpha formats
[16:40:58] [PASSED] random formats
[16:40:58] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[16:40:58] ============= [PASSED] drm_sysfb_modeset_test ==============
[16:40:58] ================== drm_fixp (2 subtests) ===================
[16:40:58] [PASSED] drm_test_int2fixp
[16:40:58] [PASSED] drm_test_sm2fixp
[16:40:58] ==================== [PASSED] drm_fixp =====================
[16:40:58] ============================================================
[16:40:58] Testing complete. Ran 621 tests: passed: 621
[16:40:58] Elapsed time: 26.134s total, 1.746s configuring, 24.259s building, 0.128s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[16:40:58] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:41:00] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[16:41:10] Starting KUnit Kernel (1/1)...
[16:41:10] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[16:41:10] ================= ttm_device (5 subtests) ==================
[16:41:10] [PASSED] ttm_device_init_basic
[16:41:10] [PASSED] ttm_device_init_multiple
[16:41:10] [PASSED] ttm_device_fini_basic
[16:41:10] [PASSED] ttm_device_init_no_vma_man
[16:41:10] ================== ttm_device_init_pools  ==================
[16:41:10] [PASSED] No DMA allocations, no DMA32 required
[16:41:10] [PASSED] DMA allocations, DMA32 required
[16:41:10] [PASSED] No DMA allocations, DMA32 required
[16:41:10] [PASSED] DMA allocations, no DMA32 required
[16:41:10] ============== [PASSED] ttm_device_init_pools ==============
[16:41:10] =================== [PASSED] ttm_device ====================
[16:41:10] ================== ttm_pool (8 subtests) ===================
[16:41:10] ================== ttm_pool_alloc_basic  ===================
[16:41:10] [PASSED] One page
[16:41:10] [PASSED] More than one page
[16:41:10] [PASSED] Above the allocation limit
[16:41:10] [PASSED] One page, with coherent DMA mappings enabled
[16:41:10] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[16:41:10] ============== [PASSED] ttm_pool_alloc_basic ===============
[16:41:10] ============== ttm_pool_alloc_basic_dma_addr  ==============
[16:41:10] [PASSED] One page
[16:41:10] [PASSED] More than one page
[16:41:10] [PASSED] Above the allocation limit
[16:41:10] [PASSED] One page, with coherent DMA mappings enabled
[16:41:10] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[16:41:10] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[16:41:10] [PASSED] ttm_pool_alloc_order_caching_match
[16:41:10] [PASSED] ttm_pool_alloc_caching_mismatch
[16:41:10] [PASSED] ttm_pool_alloc_order_mismatch
[16:41:10] [PASSED] ttm_pool_free_dma_alloc
[16:41:10] [PASSED] ttm_pool_free_no_dma_alloc
[16:41:10] [PASSED] ttm_pool_fini_basic
[16:41:10] ==================== [PASSED] ttm_pool =====================
[16:41:10] ================ ttm_resource (8 subtests) =================
[16:41:10] ================= ttm_resource_init_basic  =================
[16:41:10] [PASSED] Init resource in TTM_PL_SYSTEM
[16:41:10] [PASSED] Init resource in TTM_PL_VRAM
[16:41:10] [PASSED] Init resource in a private placement
[16:41:10] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[16:41:10] ============= [PASSED] ttm_resource_init_basic =============
[16:41:10] [PASSED] ttm_resource_init_pinned
[16:41:10] [PASSED] ttm_resource_fini_basic
[16:41:10] [PASSED] ttm_resource_manager_init_basic
[16:41:10] [PASSED] ttm_resource_manager_usage_basic
[16:41:10] [PASSED] ttm_resource_manager_set_used_basic
[16:41:10] [PASSED] ttm_sys_man_alloc_basic
[16:41:10] [PASSED] ttm_sys_man_free_basic
[16:41:10] ================== [PASSED] ttm_resource ===================
[16:41:10] =================== ttm_tt (15 subtests) ===================
[16:41:10] ==================== ttm_tt_init_basic  ====================
[16:41:10] [PASSED] Page-aligned size
[16:41:10] [PASSED] Extra pages requested
[16:41:10] ================ [PASSED] ttm_tt_init_basic ================
[16:41:10] [PASSED] ttm_tt_init_misaligned
[16:41:10] [PASSED] ttm_tt_fini_basic
[16:41:10] [PASSED] ttm_tt_fini_sg
[16:41:10] [PASSED] ttm_tt_fini_shmem
[16:41:10] [PASSED] ttm_tt_create_basic
[16:41:10] [PASSED] ttm_tt_create_invalid_bo_type
[16:41:10] [PASSED] ttm_tt_create_ttm_exists
[16:41:10] [PASSED] ttm_tt_create_failed
[16:41:10] [PASSED] ttm_tt_destroy_basic
[16:41:10] [PASSED] ttm_tt_populate_null_ttm
[16:41:10] [PASSED] ttm_tt_populate_populated_ttm
[16:41:10] [PASSED] ttm_tt_unpopulate_basic
[16:41:10] [PASSED] ttm_tt_unpopulate_empty_ttm
[16:41:10] [PASSED] ttm_tt_swapin_basic
[16:41:10] ===================== [PASSED] ttm_tt ======================
[16:41:10] =================== ttm_bo (14 subtests) ===================
[16:41:10] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[16:41:10] [PASSED] Cannot be interrupted and sleeps
[16:41:10] [PASSED] Cannot be interrupted, locks straight away
[16:41:10] [PASSED] Can be interrupted, sleeps
[16:41:10] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[16:41:10] [PASSED] ttm_bo_reserve_locked_no_sleep
[16:41:10] [PASSED] ttm_bo_reserve_no_wait_ticket
[16:41:10] [PASSED] ttm_bo_reserve_double_resv
[16:41:10] [PASSED] ttm_bo_reserve_interrupted
[16:41:10] [PASSED] ttm_bo_reserve_deadlock
[16:41:10] [PASSED] ttm_bo_unreserve_basic
[16:41:10] [PASSED] ttm_bo_unreserve_pinned
[16:41:10] [PASSED] ttm_bo_unreserve_bulk
[16:41:10] [PASSED] ttm_bo_fini_basic
[16:41:10] [PASSED] ttm_bo_fini_shared_resv
[16:41:10] [PASSED] ttm_bo_pin_basic
[16:41:10] [PASSED] ttm_bo_pin_unpin_resource
[16:41:10] [PASSED] ttm_bo_multiple_pin_one_unpin
[16:41:10] ===================== [PASSED] ttm_bo ======================
[16:41:10] ============== ttm_bo_validate (22 subtests) ===============
[16:41:10] ============== ttm_bo_init_reserved_sys_man  ===============
[16:41:10] [PASSED] Buffer object for userspace
[16:41:10] [PASSED] Kernel buffer object
[16:41:10] [PASSED] Shared buffer object
[16:41:10] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[16:41:10] ============== ttm_bo_init_reserved_mock_man  ==============
[16:41:10] [PASSED] Buffer object for userspace
[16:41:10] [PASSED] Kernel buffer object
[16:41:10] [PASSED] Shared buffer object
[16:41:10] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[16:41:10] [PASSED] ttm_bo_init_reserved_resv
[16:41:10] ================== ttm_bo_validate_basic  ==================
[16:41:10] [PASSED] Buffer object for userspace
[16:41:10] [PASSED] Kernel buffer object
[16:41:10] [PASSED] Shared buffer object
[16:41:10] ============== [PASSED] ttm_bo_validate_basic ==============
[16:41:10] [PASSED] ttm_bo_validate_invalid_placement
[16:41:10] ============= ttm_bo_validate_same_placement  ==============
[16:41:10] [PASSED] System manager
[16:41:10] [PASSED] VRAM manager
[16:41:10] ========= [PASSED] ttm_bo_validate_same_placement ==========
[16:41:10] [PASSED] ttm_bo_validate_failed_alloc
[16:41:10] [PASSED] ttm_bo_validate_pinned
[16:41:10] [PASSED] ttm_bo_validate_busy_placement
[16:41:10] ================ ttm_bo_validate_multihop  =================
[16:41:10] [PASSED] Buffer object for userspace
[16:41:10] [PASSED] Kernel buffer object
[16:41:10] [PASSED] Shared buffer object
[16:41:10] ============ [PASSED] ttm_bo_validate_multihop =============
[16:41:10] ========== ttm_bo_validate_no_placement_signaled  ==========
[16:41:10] [PASSED] Buffer object in system domain, no page vector
[16:41:10] [PASSED] Buffer object in system domain with an existing page vector
[16:41:10] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[16:41:10] ======== ttm_bo_validate_no_placement_not_signaled  ========
[16:41:10] [PASSED] Buffer object for userspace
[16:41:10] [PASSED] Kernel buffer object
[16:41:10] [PASSED] Shared buffer object
[16:41:10] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[16:41:10] [PASSED] ttm_bo_validate_move_fence_signaled
[16:41:10] ========= ttm_bo_validate_move_fence_not_signaled  =========
[16:41:10] [PASSED] Waits for GPU
[16:41:10] [PASSED] Tries to lock straight away
[16:41:10] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[16:41:10] [PASSED] ttm_bo_validate_swapout
[16:41:10] [PASSED] ttm_bo_validate_happy_evict
[16:41:10] [PASSED] ttm_bo_validate_all_pinned_evict
[16:41:10] [PASSED] ttm_bo_validate_allowed_only_evict
[16:41:10] [PASSED] ttm_bo_validate_deleted_evict
[16:41:10] [PASSED] ttm_bo_validate_busy_domain_evict
[16:41:10] [PASSED] ttm_bo_validate_evict_gutting
[16:41:10] [PASSED] ttm_bo_validate_recrusive_evict
[16:41:10] ================= [PASSED] ttm_bo_validate =================
[16:41:10] ============================================================
[16:41:10] Testing complete. Ran 102 tests: passed: 102
[16:41:10] Elapsed time: 11.505s total, 1.738s configuring, 9.552s building, 0.175s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915: add display irq hooks (rev3)

[Patchwork]

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== Series Details ==

Series: drm/i915: add display irq hooks (rev3)
URL   : https://patchwork.freedesktop.org/series/165936/
State : success

== Summary ==

CI Bug Log - changes from xe-5058-21b42374be17d486baf9392b56377afde67a778d_BAT -> xe-pw-165936v3_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-5058-21b42374be17d486baf9392b56377afde67a778d -> xe-pw-165936v3

  IGT_8909: e68d82b442e3909dd053c97542aeb029707124cf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5058-21b42374be17d486baf9392b56377afde67a778d: 21b42374be17d486baf9392b56377afde67a778d
  xe-pw-165936v3: 165936v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165936v3/index.html

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