From: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
To: Tejas Upadhyay <tejas.upadhyay@intel.com>,
intel-xe@lists.freedesktop.org
Cc: matthew.auld@intel.com, carl.zhang@intel.com, jose.souza@intel.com
Subject: Re: [PATCH V5 4/4] drm/xe/xe3p: Skip TD flush
Date: Thu, 05 Mar 2026 12:15:14 +0100 [thread overview]
Message-ID: <d67940a798cfcaba0cf6506947f02f23cacd388e.camel@linux.intel.com> (raw)
In-Reply-To: <20260303062441.1860959-10-tejas.upadhyay@intel.com>
On Tue, 2026-03-03 at 11:54 +0530, Tejas Upadhyay wrote:
> Xe3p has HW ability to do transient display flush so the xe driver
> can
> enable this HW feature by default and skip the software TD flush.
>
> Bspec: 60002
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
> drivers/gpu/drm/xe/xe_device.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_device.c
> b/drivers/gpu/drm/xe/xe_device.c
> index 94c9f17da4b4..0dca20133b94 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -1166,6 +1166,14 @@ void xe_device_td_flush(struct xe_device *xe)
> {
> struct xe_gt *root_gt;
>
> + /*
> + * From Xe3p onward the HW takes care of flush of TD entries
> also along
> + * with flushing XA entries, which will be at the usual sync
> points,
> + * like at the end of submission, so no manual flush is
> needed here.
> + */
> + if (GRAPHICS_VER(xe) >= 35)
> + return;
> +
> if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20)
> return;
>
next prev parent reply other threads:[~2026-03-05 11:15 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-03 6:24 [PATCH V5 0/4] drm/xe/xe3p_lpg: L2 flush optimization Tejas Upadhyay
2026-03-03 6:24 ` [PATCH V5 1/4] drm/xe/xe3p_lpg: flush shrinker bo cachelines manually Tejas Upadhyay
2026-03-05 10:41 ` Thomas Hellström
2026-03-03 6:24 ` [PATCH V5 2/4] drm/xe/pat: define coh_mode 2way Tejas Upadhyay
2026-03-03 6:24 ` [PATCH V5 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization Tejas Upadhyay
2026-03-03 14:56 ` Souza, Jose
2026-03-05 11:02 ` Thomas Hellström
2026-03-05 11:53 ` Upadhyay, Tejas
2026-03-03 6:24 ` [PATCH V5 4/4] drm/xe/xe3p: Skip TD flush Tejas Upadhyay
2026-03-05 11:15 ` Thomas Hellström [this message]
2026-03-03 7:27 ` ✓ CI.KUnit: success for drm/xe/xe3p_lpg: L2 flush optimization (rev6) Patchwork
2026-03-03 8:22 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-03 17:06 ` ✓ Xe.CI.FULL: " Patchwork
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