* [PATCH V5 0/4] drm/xe/xe3p_lpg: L2 flush optimization
@ 2026-03-03 6:24 Tejas Upadhyay
2026-03-03 6:24 ` [PATCH V5 1/4] drm/xe/xe3p_lpg: flush shrinker bo cachelines manually Tejas Upadhyay
` (6 more replies)
0 siblings, 7 replies; 13+ messages in thread
From: Tejas Upadhyay @ 2026-03-03 6:24 UTC (permalink / raw)
To: intel-xe
Cc: matthew.auld, thomas.hellstrom, carl.zhang, jose.souza,
Tejas Upadhyay
The optimization involves two key changes:
Hardware-assisted Transient Display Flush:
The new hardware can automatically manage the flushing of "transient"
display data from the L2 cache. This eliminates the need for manual
(software-driven) transient display (TD) flushes by the driver,
simplifying the code and likely improving efficiency.
Transient Application (App) Cacheline Management:
The hardware gains the ability to flush transient application cache
lines more efficiently. The patch handles the necessary integration
to utilize this new functionality and manages manual flushing where
it is still required, ensuring data coherency and optimizing
performance.
Additional handling due to L2 flush optimization:
1. Need to flush cachelines manually via async tlb flush for internal/shrinker bo
2. Define coh_mode 2way for differentiating coherency modes
3. Add restrictions for userptr, svm/madvise and dmabuf to use either 2WAY or XA+1WAY
pat settings
Tejas Upadhyay (4):
drm/xe/xe3p_lpg: flush shrinker bo cachelines manually
drm/xe/pat: define coh_mode 2way
drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization
drm/xe/xe3p: Skip TD flush
drivers/gpu/drm/xe/xe_bo.c | 3 ++-
drivers/gpu/drm/xe/xe_device.c | 31 ++++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_device.h | 1 +
drivers/gpu/drm/xe/xe_guc.c | 3 +++
drivers/gpu/drm/xe/xe_guc_fwif.h | 1 +
drivers/gpu/drm/xe/xe_pat.c | 14 +++++++-------
drivers/gpu/drm/xe/xe_pat.h | 5 +++--
drivers/gpu/drm/xe/xe_vm.c | 10 +++++++++-
drivers/gpu/drm/xe/xe_vm_madvise.c | 25 +++++++++++++++++++++++-
include/uapi/drm/xe_drm.h | 4 +++-
10 files changed, 84 insertions(+), 13 deletions(-)
--
2.52.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH V5 1/4] drm/xe/xe3p_lpg: flush shrinker bo cachelines manually
2026-03-03 6:24 [PATCH V5 0/4] drm/xe/xe3p_lpg: L2 flush optimization Tejas Upadhyay
@ 2026-03-03 6:24 ` Tejas Upadhyay
2026-03-05 10:41 ` Thomas Hellström
2026-03-03 6:24 ` [PATCH V5 2/4] drm/xe/pat: define coh_mode 2way Tejas Upadhyay
` (5 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Tejas Upadhyay @ 2026-03-03 6:24 UTC (permalink / raw)
To: intel-xe
Cc: matthew.auld, thomas.hellstrom, carl.zhang, jose.souza,
Tejas Upadhyay
XA, new pat_index introduced post xe3p_lpg, is memory shared between the
CPU and GPU is treated differently from other GPU memory when the Media
engine is power-gated.
XA is *always* flushed, like at the end-of-submssion (and maybe other
places), just that internally as an optimisation hw doesn't need to make
that a full flush (which will also include XA) when Media is
off/powergated, since it doesn't need to worry about GT caches vs Media
coherency, and only CPU vs GPU coherency, so can make that flush a
targeted XA flush, since stuff tagged with XA now means it's shared with
the CPU. The main implication is that we now need to somehow flush non-XA
before freeing system memory pages, otherwise dirty cachelines could be
flushed after the free (like if Media suddenly turns on and does a full
flush)
V3(Thomas/MattA/MattR): Restrict userptr with non-xa, then no need to
flush manually
V2(MattA): Expand commit description
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
---
drivers/gpu/drm/xe/xe_bo.c | 3 ++-
drivers/gpu/drm/xe/xe_device.c | 23 +++++++++++++++++++++++
drivers/gpu/drm/xe/xe_device.h | 1 +
3 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index d6c2cb959cdd..d2ee9701eae6 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -689,7 +689,8 @@ static int xe_bo_trigger_rebind(struct xe_device *xe, struct xe_bo *bo,
if (!xe_vm_in_fault_mode(vm)) {
drm_gpuvm_bo_evict(vm_bo, true);
- continue;
+ if (!xe_device_is_l2_flush_optimized(xe))
+ continue;
}
if (!idle) {
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 4b68a2d55651..94c9f17da4b4 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -1097,6 +1097,29 @@ static void tdf_request_sync(struct xe_device *xe)
}
}
+/**
+ * xe_device_is_l2_flush_optimized - if L2 flush is optimized by HW
+ * @xe: The device to check.
+ *
+ * Return: true if the HW device optimizing L2 flush, false otherwise.
+ */
+bool xe_device_is_l2_flush_optimized(struct xe_device *xe)
+{
+ /* XA is *always* flushed, like at the end-of-submssion (and maybe other
+ * places), just that internally as an optimisation hw doesn't need to make
+ * that a full flush (which will also include XA) when Media is
+ * off/powergated, since it doesn't need to worry about GT caches vs Media
+ * coherency, and only CPU vs GPU coherency, so can make that flush a
+ * targeted XA flush, since stuff tagged with XA now means it's shared with
+ * the CPU. The main implication is that we now need to somehow flush non-XA before
+ * freeing system memory pages, otherwise dirty cachelines could be flushed after the free
+ * (like if Media suddenly turns on and does a full flush)
+ */
+ if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe))
+ return true;
+ return false;
+}
+
void xe_device_l2_flush(struct xe_device *xe)
{
struct xe_gt *gt;
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index 39464650533b..dfbf96e12d2e 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -184,6 +184,7 @@ void xe_device_snapshot_print(struct xe_device *xe, struct drm_printer *p);
u64 xe_device_canonicalize_addr(struct xe_device *xe, u64 address);
u64 xe_device_uncanonicalize_addr(struct xe_device *xe, u64 address);
+bool xe_device_is_l2_flush_optimized(struct xe_device *xe);
void xe_device_td_flush(struct xe_device *xe);
void xe_device_l2_flush(struct xe_device *xe);
--
2.52.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH V5 2/4] drm/xe/pat: define coh_mode 2way
2026-03-03 6:24 [PATCH V5 0/4] drm/xe/xe3p_lpg: L2 flush optimization Tejas Upadhyay
2026-03-03 6:24 ` [PATCH V5 1/4] drm/xe/xe3p_lpg: flush shrinker bo cachelines manually Tejas Upadhyay
@ 2026-03-03 6:24 ` Tejas Upadhyay
2026-03-03 6:24 ` [PATCH V5 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization Tejas Upadhyay
` (4 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Tejas Upadhyay @ 2026-03-03 6:24 UTC (permalink / raw)
To: intel-xe
Cc: matthew.auld, thomas.hellstrom, carl.zhang, jose.souza,
Tejas Upadhyay
Defining 2way (two-way coherency) is critical for
Xe3p_LPG (Nova Lake P) platforms to support L2 flush
optimization safely.
This mode allows the driver to skip certain manual cache
flushes (L2 flush optimization) without risking memory
corruption because the hardware ensures the most recent
data is visible to both entities.
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
---
drivers/gpu/drm/xe/xe_pat.c | 14 +++++++-------
drivers/gpu/drm/xe/xe_pat.h | 5 +++--
drivers/gpu/drm/xe/xe_vm.c | 2 +-
drivers/gpu/drm/xe/xe_vm_madvise.c | 2 +-
4 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index f840d9a58740..bf581afd4d60 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -92,7 +92,7 @@ struct xe_pat_ops {
};
static const struct xe_pat_table_entry xelp_pat_table[] = {
- [0] = { XELP_PAT_WB, XE_COH_AT_LEAST_1WAY },
+ [0] = { XELP_PAT_WB, XE_COH_1WAY },
[1] = { XELP_PAT_WC, XE_COH_NONE },
[2] = { XELP_PAT_WT, XE_COH_NONE },
[3] = { XELP_PAT_UC, XE_COH_NONE },
@@ -102,19 +102,19 @@ static const struct xe_pat_table_entry xehpc_pat_table[] = {
[0] = { XELP_PAT_UC, XE_COH_NONE },
[1] = { XELP_PAT_WC, XE_COH_NONE },
[2] = { XELP_PAT_WT, XE_COH_NONE },
- [3] = { XELP_PAT_WB, XE_COH_AT_LEAST_1WAY },
+ [3] = { XELP_PAT_WB, XE_COH_1WAY },
[4] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WT, XE_COH_NONE },
- [5] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WB, XE_COH_AT_LEAST_1WAY },
+ [5] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WB, XE_COH_1WAY },
[6] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WT, XE_COH_NONE },
- [7] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WB, XE_COH_AT_LEAST_1WAY },
+ [7] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WB, XE_COH_1WAY },
};
static const struct xe_pat_table_entry xelpg_pat_table[] = {
[0] = { XELPG_PAT_0_WB, XE_COH_NONE },
[1] = { XELPG_PAT_1_WT, XE_COH_NONE },
[2] = { XELPG_PAT_3_UC, XE_COH_NONE },
- [3] = { XELPG_PAT_0_WB | XELPG_2_COH_1W, XE_COH_AT_LEAST_1WAY },
- [4] = { XELPG_PAT_0_WB | XELPG_3_COH_2W, XE_COH_AT_LEAST_1WAY },
+ [3] = { XELPG_PAT_0_WB | XELPG_2_COH_1W, XE_COH_1WAY },
+ [4] = { XELPG_PAT_0_WB | XELPG_3_COH_2W, XE_COH_2WAY },
};
/*
@@ -147,7 +147,7 @@ static const struct xe_pat_table_entry xelpg_pat_table[] = {
REG_FIELD_PREP(XE2_L3_POLICY, l3_policy) | \
REG_FIELD_PREP(XE2_L4_POLICY, l4_policy) | \
REG_FIELD_PREP(XE2_COH_MODE, __coh_mode), \
- .coh_mode = __coh_mode ? XE_COH_AT_LEAST_1WAY : XE_COH_NONE, \
+ .coh_mode = __coh_mode ? __coh_mode : XE_COH_NONE, \
.valid = 1 \
}
diff --git a/drivers/gpu/drm/xe/xe_pat.h b/drivers/gpu/drm/xe/xe_pat.h
index c7e2a53d8cee..a1e287c08f57 100644
--- a/drivers/gpu/drm/xe/xe_pat.h
+++ b/drivers/gpu/drm/xe/xe_pat.h
@@ -28,8 +28,9 @@ struct xe_pat_table_entry {
/**
* @coh_mode: The GPU coherency mode that @value maps to.
*/
-#define XE_COH_NONE 1
-#define XE_COH_AT_LEAST_1WAY 2
+#define XE_COH_NONE 1
+#define XE_COH_1WAY 2
+#define XE_COH_2WAY 3
u16 coh_mode;
/**
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index 550208ef63f8..da0ce0b3704c 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -3456,7 +3456,7 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm,
goto free_bind_ops;
}
- if (XE_WARN_ON(coh_mode > XE_COH_AT_LEAST_1WAY)) {
+ if (XE_WARN_ON(coh_mode > XE_COH_2WAY)) {
err = -EINVAL;
goto free_bind_ops;
}
diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c b/drivers/gpu/drm/xe/xe_vm_madvise.c
index 52147f5eaaa0..1a1ad8c07d49 100644
--- a/drivers/gpu/drm/xe/xe_vm_madvise.c
+++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
@@ -301,7 +301,7 @@ static bool madvise_args_are_sane(struct xe_device *xe, const struct drm_xe_madv
if (XE_IOCTL_DBG(xe, !coh_mode))
return false;
- if (XE_WARN_ON(coh_mode > XE_COH_AT_LEAST_1WAY))
+ if (XE_WARN_ON(coh_mode > XE_COH_2WAY))
return false;
if (XE_IOCTL_DBG(xe, args->pat_index.pad))
--
2.52.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH V5 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization
2026-03-03 6:24 [PATCH V5 0/4] drm/xe/xe3p_lpg: L2 flush optimization Tejas Upadhyay
2026-03-03 6:24 ` [PATCH V5 1/4] drm/xe/xe3p_lpg: flush shrinker bo cachelines manually Tejas Upadhyay
2026-03-03 6:24 ` [PATCH V5 2/4] drm/xe/pat: define coh_mode 2way Tejas Upadhyay
@ 2026-03-03 6:24 ` Tejas Upadhyay
2026-03-03 14:56 ` Souza, Jose
2026-03-05 11:02 ` Thomas Hellström
2026-03-03 6:24 ` [PATCH V5 4/4] drm/xe/xe3p: Skip TD flush Tejas Upadhyay
` (3 subsequent siblings)
6 siblings, 2 replies; 13+ messages in thread
From: Tejas Upadhyay @ 2026-03-03 6:24 UTC (permalink / raw)
To: intel-xe
Cc: matthew.auld, thomas.hellstrom, carl.zhang, jose.souza,
Tejas Upadhyay, Michal Mrozek
When set, starting xe3p_lpg, the L2 flush optimization
feature will control whether L2 is in Persistent or
Transient mode through monitoring of media activity.
To enable L2 flush optimization include new feature flag
GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when
media type is detected.
Tighten UAPI validation to restrict userptr, svm and
dmabuf mappings to be either 2WAY or XA+1WAY
V4(MattA): Modify uapi doc and commit
V3(MattA): check valid op and pat_index value
V2(MattA): validate dma-buf bos and madvise pat-index
Acked-by: Michal Mrozek <michal.mrozek@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
---
drivers/gpu/drm/xe/xe_guc.c | 3 +++
drivers/gpu/drm/xe/xe_guc_fwif.h | 1 +
drivers/gpu/drm/xe/xe_vm.c | 8 ++++++++
drivers/gpu/drm/xe/xe_vm_madvise.c | 23 +++++++++++++++++++++++
include/uapi/drm/xe_drm.h | 4 +++-
5 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 54d2fc780127..43dc4353206f 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -98,6 +98,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
if (xe_guc_using_main_gamctrl_queues(guc))
flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
+ if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) && xe_gt_is_media_type(guc_to_gt(guc)))
+ flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
+
return flags;
}
diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
index bb8f71d38611..b73fae063fac 100644
--- a/drivers/gpu/drm/xe/xe_guc_fwif.h
+++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
@@ -67,6 +67,7 @@ struct guc_update_exec_queue_policy {
#define GUC_CTL_ENABLE_PSMI_LOGGING BIT(7)
#define GUC_CTL_MAIN_GAMCTRL_QUEUES BIT(9)
#define GUC_CTL_DISABLE_SCHEDULER BIT(14)
+#define GUC_CTL_ENABLE_L2FLUSH_OPT BIT(15)
#define GUC_CTL_DEBUG 3
#define GUC_LOG_VERBOSITY REG_GENMASK(1, 0)
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index da0ce0b3704c..424e1c742b95 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -3481,6 +3481,10 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm,
op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
+ XE_IOCTL_DBG(xe, xe_device_is_l2_flush_optimized(xe) &&
+ (op == DRM_XE_VM_BIND_OP_MAP_USERPTR ||
+ is_cpu_addr_mirror) &&
+ (pat_index != 19 || coh_mode != XE_COH_2WAY)) ||
XE_IOCTL_DBG(xe, comp_en &&
op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
XE_IOCTL_DBG(xe, op == DRM_XE_VM_BIND_OP_MAP_USERPTR &&
@@ -3615,6 +3619,10 @@ static int xe_vm_bind_ioctl_validate_bo(struct xe_device *xe, struct xe_bo *bo,
if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach && comp_en))
return -EINVAL;
+ if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach && xe_device_is_l2_flush_optimized(xe) &&
+ (pat_index != 19 || coh_mode != XE_COH_2WAY)))
+ return -EINVAL;
+
/* If a BO is protected it can only be mapped if the key is still valid */
if ((bind_flags & DRM_XE_VM_BIND_FLAG_CHECK_PXP) && xe_bo_is_protected(bo) &&
op != DRM_XE_VM_BIND_OP_UNMAP && op != DRM_XE_VM_BIND_OP_UNMAP_ALL)
diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c b/drivers/gpu/drm/xe/xe_vm_madvise.c
index 1a1ad8c07d49..e669e578618b 100644
--- a/drivers/gpu/drm/xe/xe_vm_madvise.c
+++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
@@ -411,6 +411,7 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *fil
struct xe_vmas_in_madvise_range madvise_range = {.addr = args->start,
.range = args->range, };
struct xe_madvise_details details;
+ u16 pat_index, coh_mode;
struct xe_vm *vm;
struct drm_exec exec;
int err, attr_type;
@@ -447,6 +448,17 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *fil
if (err || !madvise_range.num_vmas)
goto madv_fini;
+ if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) {
+ pat_index = array_index_nospec(args->pat_index.val, xe->pat.n_entries);
+ coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
+ if (XE_IOCTL_DBG(xe, madvise_range.has_svm_userptr_vmas &&
+ xe_device_is_l2_flush_optimized(xe) &&
+ (pat_index != 19 || coh_mode != XE_COH_2WAY))) {
+ err = -EINVAL;
+ goto madv_fini;
+ }
+ }
+
if (madvise_range.has_bo_vmas) {
if (args->type == DRM_XE_MEM_RANGE_ATTR_ATOMIC) {
if (!check_bo_args_are_sane(vm, madvise_range.vmas,
@@ -464,6 +476,17 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *fil
if (!bo)
continue;
+
+ if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) {
+ if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
+ xe_device_is_l2_flush_optimized(xe) &&
+ (pat_index != 19 ||
+ coh_mode != XE_COH_2WAY))) {
+ err = -EINVAL;
+ goto err_fini;
+ }
+ }
+
err = drm_exec_lock_obj(&exec, &bo->ttm.base);
drm_exec_retry_on_contention(&exec);
if (err)
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index ef2565048bdf..862fed3cf1ed 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -1103,7 +1103,9 @@ struct drm_xe_vm_bind_op {
* incoherent GT access is possible.
*
* Note: For userptr and externally imported dma-buf the kernel expects
- * either 1WAY or 2WAY for the @pat_index.
+ * either 1WAY or 2WAY for the @pat_index. Starting from NVL-P, for
+ * userptr, svm, madvise and externally imported dma-buf the kernel expects
+ * either 2WAY or 1WAY and XA @pat_index.
*
* For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions
* on the @pat_index. For such mappings there is no actual memory being
--
2.52.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH V5 4/4] drm/xe/xe3p: Skip TD flush
2026-03-03 6:24 [PATCH V5 0/4] drm/xe/xe3p_lpg: L2 flush optimization Tejas Upadhyay
` (2 preceding siblings ...)
2026-03-03 6:24 ` [PATCH V5 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization Tejas Upadhyay
@ 2026-03-03 6:24 ` Tejas Upadhyay
2026-03-05 11:15 ` Thomas Hellström
2026-03-03 7:27 ` ✓ CI.KUnit: success for drm/xe/xe3p_lpg: L2 flush optimization (rev6) Patchwork
` (2 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Tejas Upadhyay @ 2026-03-03 6:24 UTC (permalink / raw)
To: intel-xe
Cc: matthew.auld, thomas.hellstrom, carl.zhang, jose.souza,
Tejas Upadhyay
Xe3p has HW ability to do transient display flush so the xe driver can
enable this HW feature by default and skip the software TD flush.
Bspec: 60002
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
---
drivers/gpu/drm/xe/xe_device.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 94c9f17da4b4..0dca20133b94 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -1166,6 +1166,14 @@ void xe_device_td_flush(struct xe_device *xe)
{
struct xe_gt *root_gt;
+ /*
+ * From Xe3p onward the HW takes care of flush of TD entries also along
+ * with flushing XA entries, which will be at the usual sync points,
+ * like at the end of submission, so no manual flush is needed here.
+ */
+ if (GRAPHICS_VER(xe) >= 35)
+ return;
+
if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20)
return;
--
2.52.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* ✓ CI.KUnit: success for drm/xe/xe3p_lpg: L2 flush optimization (rev6)
2026-03-03 6:24 [PATCH V5 0/4] drm/xe/xe3p_lpg: L2 flush optimization Tejas Upadhyay
` (3 preceding siblings ...)
2026-03-03 6:24 ` [PATCH V5 4/4] drm/xe/xe3p: Skip TD flush Tejas Upadhyay
@ 2026-03-03 7:27 ` Patchwork
2026-03-03 8:22 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-03 17:06 ` ✓ Xe.CI.FULL: " Patchwork
6 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2026-03-03 7:27 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: intel-xe
== Series Details ==
Series: drm/xe/xe3p_lpg: L2 flush optimization (rev6)
URL : https://patchwork.freedesktop.org/series/158017/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[07:26:04] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:26:08] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:26:42] Starting KUnit Kernel (1/1)...
[07:26:42] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:26:42] ================== guc_buf (11 subtests) ===================
[07:26:42] [PASSED] test_smallest
[07:26:42] [PASSED] test_largest
[07:26:42] [PASSED] test_granular
[07:26:42] [PASSED] test_unique
[07:26:42] [PASSED] test_overlap
[07:26:42] [PASSED] test_reusable
[07:26:42] [PASSED] test_too_big
[07:26:42] [PASSED] test_flush
[07:26:42] [PASSED] test_lookup
[07:26:42] [PASSED] test_data
[07:26:42] [PASSED] test_class
[07:26:42] ===================== [PASSED] guc_buf =====================
[07:26:42] =================== guc_dbm (7 subtests) ===================
[07:26:42] [PASSED] test_empty
[07:26:42] [PASSED] test_default
[07:26:42] ======================== test_size ========================
[07:26:42] [PASSED] 4
[07:26:42] [PASSED] 8
[07:26:42] [PASSED] 32
[07:26:42] [PASSED] 256
[07:26:42] ==================== [PASSED] test_size ====================
[07:26:42] ======================= test_reuse ========================
[07:26:42] [PASSED] 4
[07:26:42] [PASSED] 8
[07:26:42] [PASSED] 32
[07:26:42] [PASSED] 256
[07:26:42] =================== [PASSED] test_reuse ====================
[07:26:42] =================== test_range_overlap ====================
[07:26:42] [PASSED] 4
[07:26:42] [PASSED] 8
[07:26:42] [PASSED] 32
[07:26:42] [PASSED] 256
[07:26:42] =============== [PASSED] test_range_overlap ================
[07:26:42] =================== test_range_compact ====================
[07:26:42] [PASSED] 4
[07:26:42] [PASSED] 8
[07:26:42] [PASSED] 32
[07:26:42] [PASSED] 256
[07:26:42] =============== [PASSED] test_range_compact ================
[07:26:42] ==================== test_range_spare =====================
[07:26:42] [PASSED] 4
[07:26:42] [PASSED] 8
[07:26:42] [PASSED] 32
[07:26:42] [PASSED] 256
[07:26:42] ================ [PASSED] test_range_spare =================
[07:26:42] ===================== [PASSED] guc_dbm =====================
[07:26:42] =================== guc_idm (6 subtests) ===================
[07:26:42] [PASSED] bad_init
[07:26:42] [PASSED] no_init
[07:26:42] [PASSED] init_fini
[07:26:42] [PASSED] check_used
[07:26:42] [PASSED] check_quota
[07:26:42] [PASSED] check_all
[07:26:42] ===================== [PASSED] guc_idm =====================
[07:26:42] ================== no_relay (3 subtests) ===================
[07:26:42] [PASSED] xe_drops_guc2pf_if_not_ready
[07:26:42] [PASSED] xe_drops_guc2vf_if_not_ready
[07:26:42] [PASSED] xe_rejects_send_if_not_ready
[07:26:42] ==================== [PASSED] no_relay =====================
[07:26:42] ================== pf_relay (14 subtests) ==================
[07:26:42] [PASSED] pf_rejects_guc2pf_too_short
[07:26:42] [PASSED] pf_rejects_guc2pf_too_long
[07:26:42] [PASSED] pf_rejects_guc2pf_no_payload
[07:26:42] [PASSED] pf_fails_no_payload
[07:26:42] [PASSED] pf_fails_bad_origin
[07:26:42] [PASSED] pf_fails_bad_type
[07:26:42] [PASSED] pf_txn_reports_error
[07:26:42] [PASSED] pf_txn_sends_pf2guc
[07:26:42] [PASSED] pf_sends_pf2guc
[07:26:42] [SKIPPED] pf_loopback_nop
[07:26:42] [SKIPPED] pf_loopback_echo
[07:26:42] [SKIPPED] pf_loopback_fail
[07:26:42] [SKIPPED] pf_loopback_busy
[07:26:42] [SKIPPED] pf_loopback_retry
[07:26:42] ==================== [PASSED] pf_relay =====================
[07:26:42] ================== vf_relay (3 subtests) ===================
[07:26:42] [PASSED] vf_rejects_guc2vf_too_short
[07:26:42] [PASSED] vf_rejects_guc2vf_too_long
[07:26:42] [PASSED] vf_rejects_guc2vf_no_payload
[07:26:42] ==================== [PASSED] vf_relay =====================
[07:26:42] ================ pf_gt_config (9 subtests) =================
[07:26:42] [PASSED] fair_contexts_1vf
[07:26:42] [PASSED] fair_doorbells_1vf
[07:26:42] [PASSED] fair_ggtt_1vf
[07:26:42] ====================== fair_vram_1vf ======================
[07:26:42] [PASSED] 3.50 GiB
[07:26:42] [PASSED] 11.5 GiB
[07:26:42] [PASSED] 15.5 GiB
[07:26:42] [PASSED] 31.5 GiB
[07:26:42] [PASSED] 63.5 GiB
[07:26:42] [PASSED] 13.9 GiB
[07:26:42] ================== [PASSED] fair_vram_1vf ==================
[07:26:42] ================ fair_vram_1vf_admin_only =================
[07:26:42] [PASSED] 3.50 GiB
[07:26:42] [PASSED] 11.5 GiB
[07:26:42] [PASSED] 15.5 GiB
[07:26:42] [PASSED] 31.5 GiB
[07:26:42] [PASSED] 63.5 GiB
[07:26:42] [PASSED] 13.9 GiB
[07:26:42] ============ [PASSED] fair_vram_1vf_admin_only =============
[07:26:42] ====================== fair_contexts ======================
[07:26:42] [PASSED] 1 VF
[07:26:42] [PASSED] 2 VFs
[07:26:42] [PASSED] 3 VFs
[07:26:42] [PASSED] 4 VFs
[07:26:42] [PASSED] 5 VFs
[07:26:42] [PASSED] 6 VFs
[07:26:42] [PASSED] 7 VFs
[07:26:42] [PASSED] 8 VFs
[07:26:42] [PASSED] 9 VFs
[07:26:42] [PASSED] 10 VFs
[07:26:42] [PASSED] 11 VFs
[07:26:42] [PASSED] 12 VFs
[07:26:42] [PASSED] 13 VFs
[07:26:42] [PASSED] 14 VFs
[07:26:42] [PASSED] 15 VFs
[07:26:42] [PASSED] 16 VFs
[07:26:42] [PASSED] 17 VFs
[07:26:42] [PASSED] 18 VFs
[07:26:42] [PASSED] 19 VFs
[07:26:42] [PASSED] 20 VFs
[07:26:42] [PASSED] 21 VFs
[07:26:42] [PASSED] 22 VFs
[07:26:42] [PASSED] 23 VFs
[07:26:42] [PASSED] 24 VFs
[07:26:42] [PASSED] 25 VFs
[07:26:42] [PASSED] 26 VFs
[07:26:42] [PASSED] 27 VFs
[07:26:42] [PASSED] 28 VFs
[07:26:42] [PASSED] 29 VFs
[07:26:42] [PASSED] 30 VFs
[07:26:42] [PASSED] 31 VFs
[07:26:42] [PASSED] 32 VFs
[07:26:42] [PASSED] 33 VFs
[07:26:42] [PASSED] 34 VFs
[07:26:42] [PASSED] 35 VFs
[07:26:42] [PASSED] 36 VFs
[07:26:42] [PASSED] 37 VFs
[07:26:42] [PASSED] 38 VFs
[07:26:42] [PASSED] 39 VFs
[07:26:42] [PASSED] 40 VFs
[07:26:42] [PASSED] 41 VFs
[07:26:42] [PASSED] 42 VFs
[07:26:42] [PASSED] 43 VFs
[07:26:42] [PASSED] 44 VFs
[07:26:42] [PASSED] 45 VFs
[07:26:42] [PASSED] 46 VFs
[07:26:42] [PASSED] 47 VFs
[07:26:42] [PASSED] 48 VFs
[07:26:42] [PASSED] 49 VFs
[07:26:42] [PASSED] 50 VFs
[07:26:42] [PASSED] 51 VFs
[07:26:42] [PASSED] 52 VFs
[07:26:42] [PASSED] 53 VFs
[07:26:42] [PASSED] 54 VFs
[07:26:42] [PASSED] 55 VFs
[07:26:42] [PASSED] 56 VFs
[07:26:42] [PASSED] 57 VFs
[07:26:42] [PASSED] 58 VFs
[07:26:42] [PASSED] 59 VFs
[07:26:42] [PASSED] 60 VFs
[07:26:42] [PASSED] 61 VFs
[07:26:42] [PASSED] 62 VFs
[07:26:42] [PASSED] 63 VFs
[07:26:42] ================== [PASSED] fair_contexts ==================
[07:26:42] ===================== fair_doorbells ======================
[07:26:42] [PASSED] 1 VF
[07:26:42] [PASSED] 2 VFs
[07:26:42] [PASSED] 3 VFs
[07:26:42] [PASSED] 4 VFs
[07:26:42] [PASSED] 5 VFs
[07:26:42] [PASSED] 6 VFs
[07:26:42] [PASSED] 7 VFs
[07:26:42] [PASSED] 8 VFs
[07:26:42] [PASSED] 9 VFs
[07:26:42] [PASSED] 10 VFs
[07:26:42] [PASSED] 11 VFs
[07:26:42] [PASSED] 12 VFs
[07:26:42] [PASSED] 13 VFs
[07:26:42] [PASSED] 14 VFs
[07:26:42] [PASSED] 15 VFs
[07:26:42] [PASSED] 16 VFs
[07:26:42] [PASSED] 17 VFs
[07:26:42] [PASSED] 18 VFs
[07:26:42] [PASSED] 19 VFs
[07:26:42] [PASSED] 20 VFs
[07:26:42] [PASSED] 21 VFs
[07:26:42] [PASSED] 22 VFs
[07:26:42] [PASSED] 23 VFs
[07:26:42] [PASSED] 24 VFs
[07:26:42] [PASSED] 25 VFs
[07:26:42] [PASSED] 26 VFs
[07:26:42] [PASSED] 27 VFs
[07:26:42] [PASSED] 28 VFs
[07:26:42] [PASSED] 29 VFs
[07:26:42] [PASSED] 30 VFs
[07:26:42] [PASSED] 31 VFs
[07:26:42] [PASSED] 32 VFs
[07:26:42] [PASSED] 33 VFs
[07:26:42] [PASSED] 34 VFs
[07:26:42] [PASSED] 35 VFs
[07:26:42] [PASSED] 36 VFs
[07:26:42] [PASSED] 37 VFs
[07:26:42] [PASSED] 38 VFs
[07:26:42] [PASSED] 39 VFs
[07:26:42] [PASSED] 40 VFs
[07:26:42] [PASSED] 41 VFs
[07:26:42] [PASSED] 42 VFs
[07:26:42] [PASSED] 43 VFs
[07:26:42] [PASSED] 44 VFs
[07:26:42] [PASSED] 45 VFs
[07:26:42] [PASSED] 46 VFs
[07:26:42] [PASSED] 47 VFs
[07:26:42] [PASSED] 48 VFs
[07:26:42] [PASSED] 49 VFs
[07:26:42] [PASSED] 50 VFs
[07:26:42] [PASSED] 51 VFs
[07:26:42] [PASSED] 52 VFs
[07:26:42] [PASSED] 53 VFs
[07:26:42] [PASSED] 54 VFs
[07:26:42] [PASSED] 55 VFs
[07:26:42] [PASSED] 56 VFs
[07:26:42] [PASSED] 57 VFs
[07:26:42] [PASSED] 58 VFs
[07:26:42] [PASSED] 59 VFs
[07:26:42] [PASSED] 60 VFs
[07:26:42] [PASSED] 61 VFs
[07:26:42] [PASSED] 62 VFs
[07:26:42] [PASSED] 63 VFs
[07:26:42] ================= [PASSED] fair_doorbells ==================
[07:26:42] ======================== fair_ggtt ========================
[07:26:42] [PASSED] 1 VF
[07:26:42] [PASSED] 2 VFs
[07:26:42] [PASSED] 3 VFs
[07:26:42] [PASSED] 4 VFs
[07:26:42] [PASSED] 5 VFs
[07:26:42] [PASSED] 6 VFs
[07:26:42] [PASSED] 7 VFs
[07:26:42] [PASSED] 8 VFs
[07:26:42] [PASSED] 9 VFs
[07:26:42] [PASSED] 10 VFs
[07:26:42] [PASSED] 11 VFs
[07:26:42] [PASSED] 12 VFs
[07:26:42] [PASSED] 13 VFs
[07:26:42] [PASSED] 14 VFs
[07:26:42] [PASSED] 15 VFs
[07:26:42] [PASSED] 16 VFs
[07:26:42] [PASSED] 17 VFs
[07:26:42] [PASSED] 18 VFs
[07:26:42] [PASSED] 19 VFs
[07:26:42] [PASSED] 20 VFs
[07:26:42] [PASSED] 21 VFs
[07:26:42] [PASSED] 22 VFs
[07:26:42] [PASSED] 23 VFs
[07:26:42] [PASSED] 24 VFs
[07:26:42] [PASSED] 25 VFs
[07:26:42] [PASSED] 26 VFs
[07:26:42] [PASSED] 27 VFs
[07:26:42] [PASSED] 28 VFs
[07:26:42] [PASSED] 29 VFs
[07:26:42] [PASSED] 30 VFs
[07:26:42] [PASSED] 31 VFs
[07:26:42] [PASSED] 32 VFs
[07:26:42] [PASSED] 33 VFs
[07:26:42] [PASSED] 34 VFs
[07:26:42] [PASSED] 35 VFs
[07:26:42] [PASSED] 36 VFs
[07:26:42] [PASSED] 37 VFs
[07:26:42] [PASSED] 38 VFs
[07:26:42] [PASSED] 39 VFs
[07:26:42] [PASSED] 40 VFs
[07:26:42] [PASSED] 41 VFs
[07:26:42] [PASSED] 42 VFs
[07:26:42] [PASSED] 43 VFs
[07:26:42] [PASSED] 44 VFs
[07:26:42] [PASSED] 45 VFs
[07:26:42] [PASSED] 46 VFs
[07:26:42] [PASSED] 47 VFs
[07:26:42] [PASSED] 48 VFs
[07:26:42] [PASSED] 49 VFs
[07:26:42] [PASSED] 50 VFs
[07:26:42] [PASSED] 51 VFs
[07:26:42] [PASSED] 52 VFs
[07:26:42] [PASSED] 53 VFs
[07:26:42] [PASSED] 54 VFs
[07:26:42] [PASSED] 55 VFs
[07:26:42] [PASSED] 56 VFs
[07:26:42] [PASSED] 57 VFs
[07:26:42] [PASSED] 58 VFs
[07:26:42] [PASSED] 59 VFs
[07:26:42] [PASSED] 60 VFs
[07:26:42] [PASSED] 61 VFs
[07:26:42] [PASSED] 62 VFs
[07:26:42] [PASSED] 63 VFs
[07:26:42] ==================== [PASSED] fair_ggtt ====================
[07:26:42] ======================== fair_vram ========================
[07:26:42] [PASSED] 1 VF
[07:26:42] [PASSED] 2 VFs
[07:26:42] [PASSED] 3 VFs
[07:26:42] [PASSED] 4 VFs
[07:26:42] [PASSED] 5 VFs
[07:26:42] [PASSED] 6 VFs
[07:26:42] [PASSED] 7 VFs
[07:26:42] [PASSED] 8 VFs
[07:26:42] [PASSED] 9 VFs
[07:26:42] [PASSED] 10 VFs
[07:26:42] [PASSED] 11 VFs
[07:26:42] [PASSED] 12 VFs
[07:26:42] [PASSED] 13 VFs
[07:26:42] [PASSED] 14 VFs
[07:26:42] [PASSED] 15 VFs
[07:26:42] [PASSED] 16 VFs
[07:26:42] [PASSED] 17 VFs
[07:26:42] [PASSED] 18 VFs
[07:26:42] [PASSED] 19 VFs
[07:26:42] [PASSED] 20 VFs
[07:26:42] [PASSED] 21 VFs
[07:26:42] [PASSED] 22 VFs
[07:26:42] [PASSED] 23 VFs
[07:26:42] [PASSED] 24 VFs
[07:26:42] [PASSED] 25 VFs
[07:26:42] [PASSED] 26 VFs
[07:26:42] [PASSED] 27 VFs
[07:26:42] [PASSED] 28 VFs
[07:26:42] [PASSED] 29 VFs
[07:26:42] [PASSED] 30 VFs
[07:26:42] [PASSED] 31 VFs
[07:26:42] [PASSED] 32 VFs
[07:26:42] [PASSED] 33 VFs
[07:26:42] [PASSED] 34 VFs
[07:26:42] [PASSED] 35 VFs
[07:26:42] [PASSED] 36 VFs
[07:26:42] [PASSED] 37 VFs
[07:26:42] [PASSED] 38 VFs
[07:26:42] [PASSED] 39 VFs
[07:26:42] [PASSED] 40 VFs
[07:26:42] [PASSED] 41 VFs
[07:26:42] [PASSED] 42 VFs
[07:26:42] [PASSED] 43 VFs
[07:26:42] [PASSED] 44 VFs
[07:26:42] [PASSED] 45 VFs
[07:26:42] [PASSED] 46 VFs
[07:26:42] [PASSED] 47 VFs
[07:26:42] [PASSED] 48 VFs
[07:26:42] [PASSED] 49 VFs
[07:26:42] [PASSED] 50 VFs
[07:26:42] [PASSED] 51 VFs
[07:26:42] [PASSED] 52 VFs
[07:26:42] [PASSED] 53 VFs
[07:26:42] [PASSED] 54 VFs
[07:26:42] [PASSED] 55 VFs
[07:26:42] [PASSED] 56 VFs
[07:26:42] [PASSED] 57 VFs
[07:26:42] [PASSED] 58 VFs
[07:26:42] [PASSED] 59 VFs
[07:26:42] [PASSED] 60 VFs
[07:26:42] [PASSED] 61 VFs
[07:26:43] [PASSED] 62 VFs
[07:26:43] [PASSED] 63 VFs
[07:26:43] ==================== [PASSED] fair_vram ====================
[07:26:43] ================== [PASSED] pf_gt_config ===================
[07:26:43] ===================== lmtt (1 subtest) =====================
[07:26:43] ======================== test_ops =========================
[07:26:43] [PASSED] 2-level
[07:26:43] [PASSED] multi-level
[07:26:43] ==================== [PASSED] test_ops =====================
[07:26:43] ====================== [PASSED] lmtt =======================
[07:26:43] ================= pf_service (11 subtests) =================
[07:26:43] [PASSED] pf_negotiate_any
[07:26:43] [PASSED] pf_negotiate_base_match
[07:26:43] [PASSED] pf_negotiate_base_newer
[07:26:43] [PASSED] pf_negotiate_base_next
[07:26:43] [SKIPPED] pf_negotiate_base_older
[07:26:43] [PASSED] pf_negotiate_base_prev
[07:26:43] [PASSED] pf_negotiate_latest_match
[07:26:43] [PASSED] pf_negotiate_latest_newer
[07:26:43] [PASSED] pf_negotiate_latest_next
[07:26:43] [SKIPPED] pf_negotiate_latest_older
[07:26:43] [SKIPPED] pf_negotiate_latest_prev
[07:26:43] =================== [PASSED] pf_service ====================
[07:26:43] ================= xe_guc_g2g (2 subtests) ==================
[07:26:43] ============== xe_live_guc_g2g_kunit_default ==============
[07:26:43] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[07:26:43] ============== xe_live_guc_g2g_kunit_allmem ===============
[07:26:43] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[07:26:43] =================== [SKIPPED] xe_guc_g2g ===================
[07:26:43] =================== xe_mocs (2 subtests) ===================
[07:26:43] ================ xe_live_mocs_kernel_kunit ================
[07:26:43] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[07:26:43] ================ xe_live_mocs_reset_kunit =================
[07:26:43] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[07:26:43] ==================== [SKIPPED] xe_mocs =====================
[07:26:43] ================= xe_migrate (2 subtests) ==================
[07:26:43] ================= xe_migrate_sanity_kunit =================
[07:26:43] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[07:26:43] ================== xe_validate_ccs_kunit ==================
[07:26:43] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[07:26:43] =================== [SKIPPED] xe_migrate ===================
[07:26:43] ================== xe_dma_buf (1 subtest) ==================
[07:26:43] ==================== xe_dma_buf_kunit =====================
[07:26:43] ================ [SKIPPED] xe_dma_buf_kunit ================
[07:26:43] =================== [SKIPPED] xe_dma_buf ===================
[07:26:43] ================= xe_bo_shrink (1 subtest) =================
[07:26:43] =================== xe_bo_shrink_kunit ====================
[07:26:43] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[07:26:43] ================== [SKIPPED] xe_bo_shrink ==================
[07:26:43] ==================== xe_bo (2 subtests) ====================
[07:26:43] ================== xe_ccs_migrate_kunit ===================
[07:26:43] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[07:26:43] ==================== xe_bo_evict_kunit ====================
[07:26:43] =============== [SKIPPED] xe_bo_evict_kunit ================
[07:26:43] ===================== [SKIPPED] xe_bo ======================
[07:26:43] ==================== args (13 subtests) ====================
[07:26:43] [PASSED] count_args_test
[07:26:43] [PASSED] call_args_example
[07:26:43] [PASSED] call_args_test
[07:26:43] [PASSED] drop_first_arg_example
[07:26:43] [PASSED] drop_first_arg_test
[07:26:43] [PASSED] first_arg_example
[07:26:43] [PASSED] first_arg_test
[07:26:43] [PASSED] last_arg_example
[07:26:43] [PASSED] last_arg_test
[07:26:43] [PASSED] pick_arg_example
[07:26:43] [PASSED] if_args_example
[07:26:43] [PASSED] if_args_test
[07:26:43] [PASSED] sep_comma_example
[07:26:43] ====================== [PASSED] args =======================
[07:26:43] =================== xe_pci (3 subtests) ====================
[07:26:43] ==================== check_graphics_ip ====================
[07:26:43] [PASSED] 12.00 Xe_LP
[07:26:43] [PASSED] 12.10 Xe_LP+
[07:26:43] [PASSED] 12.55 Xe_HPG
[07:26:43] [PASSED] 12.60 Xe_HPC
[07:26:43] [PASSED] 12.70 Xe_LPG
[07:26:43] [PASSED] 12.71 Xe_LPG
[07:26:43] [PASSED] 12.74 Xe_LPG+
[07:26:43] [PASSED] 20.01 Xe2_HPG
[07:26:43] [PASSED] 20.02 Xe2_HPG
[07:26:43] [PASSED] 20.04 Xe2_LPG
[07:26:43] [PASSED] 30.00 Xe3_LPG
[07:26:43] [PASSED] 30.01 Xe3_LPG
[07:26:43] [PASSED] 30.03 Xe3_LPG
[07:26:43] [PASSED] 30.04 Xe3_LPG
[07:26:43] [PASSED] 30.05 Xe3_LPG
[07:26:43] [PASSED] 35.10 Xe3p_LPG
[07:26:43] [PASSED] 35.11 Xe3p_XPC
[07:26:43] ================ [PASSED] check_graphics_ip ================
[07:26:43] ===================== check_media_ip ======================
[07:26:43] [PASSED] 12.00 Xe_M
[07:26:43] [PASSED] 12.55 Xe_HPM
[07:26:43] [PASSED] 13.00 Xe_LPM+
[07:26:43] [PASSED] 13.01 Xe2_HPM
[07:26:43] [PASSED] 20.00 Xe2_LPM
[07:26:43] [PASSED] 30.00 Xe3_LPM
[07:26:43] [PASSED] 30.02 Xe3_LPM
[07:26:43] [PASSED] 35.00 Xe3p_LPM
[07:26:43] [PASSED] 35.03 Xe3p_HPM
[07:26:43] ================= [PASSED] check_media_ip ==================
[07:26:43] =================== check_platform_desc ===================
[07:26:43] [PASSED] 0x9A60 (TIGERLAKE)
[07:26:43] [PASSED] 0x9A68 (TIGERLAKE)
[07:26:43] [PASSED] 0x9A70 (TIGERLAKE)
[07:26:43] [PASSED] 0x9A40 (TIGERLAKE)
[07:26:43] [PASSED] 0x9A49 (TIGERLAKE)
[07:26:43] [PASSED] 0x9A59 (TIGERLAKE)
[07:26:43] [PASSED] 0x9A78 (TIGERLAKE)
[07:26:43] [PASSED] 0x9AC0 (TIGERLAKE)
[07:26:43] [PASSED] 0x9AC9 (TIGERLAKE)
[07:26:43] [PASSED] 0x9AD9 (TIGERLAKE)
[07:26:43] [PASSED] 0x9AF8 (TIGERLAKE)
[07:26:43] [PASSED] 0x4C80 (ROCKETLAKE)
[07:26:43] [PASSED] 0x4C8A (ROCKETLAKE)
[07:26:43] [PASSED] 0x4C8B (ROCKETLAKE)
[07:26:43] [PASSED] 0x4C8C (ROCKETLAKE)
[07:26:43] [PASSED] 0x4C90 (ROCKETLAKE)
[07:26:43] [PASSED] 0x4C9A (ROCKETLAKE)
[07:26:43] [PASSED] 0x4680 (ALDERLAKE_S)
[07:26:43] [PASSED] 0x4682 (ALDERLAKE_S)
[07:26:43] [PASSED] 0x4688 (ALDERLAKE_S)
[07:26:43] [PASSED] 0x468A (ALDERLAKE_S)
[07:26:43] [PASSED] 0x468B (ALDERLAKE_S)
[07:26:43] [PASSED] 0x4690 (ALDERLAKE_S)
[07:26:43] [PASSED] 0x4692 (ALDERLAKE_S)
[07:26:43] [PASSED] 0x4693 (ALDERLAKE_S)
[07:26:43] [PASSED] 0x46A0 (ALDERLAKE_P)
[07:26:43] [PASSED] 0x46A1 (ALDERLAKE_P)
[07:26:43] [PASSED] 0x46A2 (ALDERLAKE_P)
[07:26:43] [PASSED] 0x46A3 (ALDERLAKE_P)
[07:26:43] [PASSED] 0x46A6 (ALDERLAKE_P)
[07:26:43] [PASSED] 0x46A8 (ALDERLAKE_P)
[07:26:43] [PASSED] 0x46AA (ALDERLAKE_P)
[07:26:43] [PASSED] 0x462A (ALDERLAKE_P)
[07:26:43] [PASSED] 0x4626 (ALDERLAKE_P)
[07:26:43] [PASSED] 0x4628 (ALDERLAKE_P)
[07:26:43] [PASSED] 0x46B0 (ALDERLAKE_P)
[07:26:43] [PASSED] 0x46B1 (ALDERLAKE_P)
[07:26:43] [PASSED] 0x46B2 (ALDERLAKE_P)
[07:26:43] [PASSED] 0x46B3 (ALDERLAKE_P)
[07:26:43] [PASSED] 0x46C0 (ALDERLAKE_P)
[07:26:43] [PASSED] 0x46C1 (ALDERLAKE_P)
[07:26:43] [PASSED] 0x46C2 (ALDERLAKE_P)
[07:26:43] [PASSED] 0x46C3 (ALDERLAKE_P)
[07:26:43] [PASSED] 0x46D0 (ALDERLAKE_N)
[07:26:43] [PASSED] 0x46D1 (ALDERLAKE_N)
[07:26:43] [PASSED] 0x46D2 (ALDERLAKE_N)
[07:26:43] [PASSED] 0x46D3 (ALDERLAKE_N)
[07:26:43] [PASSED] 0x46D4 (ALDERLAKE_N)
[07:26:43] [PASSED] 0xA721 (ALDERLAKE_P)
[07:26:43] [PASSED] 0xA7A1 (ALDERLAKE_P)
[07:26:43] [PASSED] 0xA7A9 (ALDERLAKE_P)
[07:26:43] [PASSED] 0xA7AC (ALDERLAKE_P)
[07:26:43] [PASSED] 0xA7AD (ALDERLAKE_P)
[07:26:43] [PASSED] 0xA720 (ALDERLAKE_P)
[07:26:43] [PASSED] 0xA7A0 (ALDERLAKE_P)
[07:26:43] [PASSED] 0xA7A8 (ALDERLAKE_P)
[07:26:43] [PASSED] 0xA7AA (ALDERLAKE_P)
[07:26:43] [PASSED] 0xA7AB (ALDERLAKE_P)
[07:26:43] [PASSED] 0xA780 (ALDERLAKE_S)
[07:26:43] [PASSED] 0xA781 (ALDERLAKE_S)
[07:26:43] [PASSED] 0xA782 (ALDERLAKE_S)
[07:26:43] [PASSED] 0xA783 (ALDERLAKE_S)
[07:26:43] [PASSED] 0xA788 (ALDERLAKE_S)
[07:26:43] [PASSED] 0xA789 (ALDERLAKE_S)
[07:26:43] [PASSED] 0xA78A (ALDERLAKE_S)
[07:26:43] [PASSED] 0xA78B (ALDERLAKE_S)
[07:26:43] [PASSED] 0x4905 (DG1)
[07:26:43] [PASSED] 0x4906 (DG1)
[07:26:43] [PASSED] 0x4907 (DG1)
[07:26:43] [PASSED] 0x4908 (DG1)
[07:26:43] [PASSED] 0x4909 (DG1)
[07:26:43] [PASSED] 0x56C0 (DG2)
[07:26:43] [PASSED] 0x56C2 (DG2)
[07:26:43] [PASSED] 0x56C1 (DG2)
[07:26:43] [PASSED] 0x7D51 (METEORLAKE)
[07:26:43] [PASSED] 0x7DD1 (METEORLAKE)
[07:26:43] [PASSED] 0x7D41 (METEORLAKE)
[07:26:43] [PASSED] 0x7D67 (METEORLAKE)
[07:26:43] [PASSED] 0xB640 (METEORLAKE)
[07:26:43] [PASSED] 0x56A0 (DG2)
[07:26:43] [PASSED] 0x56A1 (DG2)
[07:26:43] [PASSED] 0x56A2 (DG2)
[07:26:43] [PASSED] 0x56BE (DG2)
[07:26:43] [PASSED] 0x56BF (DG2)
[07:26:43] [PASSED] 0x5690 (DG2)
[07:26:43] [PASSED] 0x5691 (DG2)
[07:26:43] [PASSED] 0x5692 (DG2)
[07:26:43] [PASSED] 0x56A5 (DG2)
[07:26:43] [PASSED] 0x56A6 (DG2)
[07:26:43] [PASSED] 0x56B0 (DG2)
[07:26:43] [PASSED] 0x56B1 (DG2)
[07:26:43] [PASSED] 0x56BA (DG2)
[07:26:43] [PASSED] 0x56BB (DG2)
[07:26:43] [PASSED] 0x56BC (DG2)
[07:26:43] [PASSED] 0x56BD (DG2)
[07:26:43] [PASSED] 0x5693 (DG2)
[07:26:43] [PASSED] 0x5694 (DG2)
[07:26:43] [PASSED] 0x5695 (DG2)
[07:26:43] [PASSED] 0x56A3 (DG2)
[07:26:43] [PASSED] 0x56A4 (DG2)
[07:26:43] [PASSED] 0x56B2 (DG2)
[07:26:43] [PASSED] 0x56B3 (DG2)
[07:26:43] [PASSED] 0x5696 (DG2)
[07:26:43] [PASSED] 0x5697 (DG2)
[07:26:43] [PASSED] 0xB69 (PVC)
[07:26:43] [PASSED] 0xB6E (PVC)
[07:26:43] [PASSED] 0xBD4 (PVC)
[07:26:43] [PASSED] 0xBD5 (PVC)
[07:26:43] [PASSED] 0xBD6 (PVC)
[07:26:43] [PASSED] 0xBD7 (PVC)
[07:26:43] [PASSED] 0xBD8 (PVC)
[07:26:43] [PASSED] 0xBD9 (PVC)
[07:26:43] [PASSED] 0xBDA (PVC)
[07:26:43] [PASSED] 0xBDB (PVC)
[07:26:43] [PASSED] 0xBE0 (PVC)
[07:26:43] [PASSED] 0xBE1 (PVC)
[07:26:43] [PASSED] 0xBE5 (PVC)
[07:26:43] [PASSED] 0x7D40 (METEORLAKE)
[07:26:43] [PASSED] 0x7D45 (METEORLAKE)
[07:26:43] [PASSED] 0x7D55 (METEORLAKE)
[07:26:43] [PASSED] 0x7D60 (METEORLAKE)
[07:26:43] [PASSED] 0x7DD5 (METEORLAKE)
[07:26:43] [PASSED] 0x6420 (LUNARLAKE)
[07:26:43] [PASSED] 0x64A0 (LUNARLAKE)
[07:26:43] [PASSED] 0x64B0 (LUNARLAKE)
[07:26:43] [PASSED] 0xE202 (BATTLEMAGE)
[07:26:43] [PASSED] 0xE209 (BATTLEMAGE)
[07:26:43] [PASSED] 0xE20B (BATTLEMAGE)
[07:26:43] [PASSED] 0xE20C (BATTLEMAGE)
[07:26:43] [PASSED] 0xE20D (BATTLEMAGE)
[07:26:43] [PASSED] 0xE210 (BATTLEMAGE)
[07:26:43] [PASSED] 0xE211 (BATTLEMAGE)
[07:26:43] [PASSED] 0xE212 (BATTLEMAGE)
[07:26:43] [PASSED] 0xE216 (BATTLEMAGE)
[07:26:43] [PASSED] 0xE220 (BATTLEMAGE)
[07:26:43] [PASSED] 0xE221 (BATTLEMAGE)
[07:26:43] [PASSED] 0xE222 (BATTLEMAGE)
[07:26:43] [PASSED] 0xE223 (BATTLEMAGE)
[07:26:43] [PASSED] 0xB080 (PANTHERLAKE)
[07:26:43] [PASSED] 0xB081 (PANTHERLAKE)
[07:26:43] [PASSED] 0xB082 (PANTHERLAKE)
[07:26:43] [PASSED] 0xB083 (PANTHERLAKE)
[07:26:43] [PASSED] 0xB084 (PANTHERLAKE)
[07:26:43] [PASSED] 0xB085 (PANTHERLAKE)
[07:26:43] [PASSED] 0xB086 (PANTHERLAKE)
[07:26:43] [PASSED] 0xB087 (PANTHERLAKE)
[07:26:43] [PASSED] 0xB08F (PANTHERLAKE)
[07:26:43] [PASSED] 0xB090 (PANTHERLAKE)
[07:26:43] [PASSED] 0xB0A0 (PANTHERLAKE)
[07:26:43] [PASSED] 0xB0B0 (PANTHERLAKE)
[07:26:43] [PASSED] 0xFD80 (PANTHERLAKE)
[07:26:43] [PASSED] 0xFD81 (PANTHERLAKE)
[07:26:43] [PASSED] 0xD740 (NOVALAKE_S)
[07:26:43] [PASSED] 0xD741 (NOVALAKE_S)
[07:26:43] [PASSED] 0xD742 (NOVALAKE_S)
[07:26:43] [PASSED] 0xD743 (NOVALAKE_S)
[07:26:43] [PASSED] 0xD744 (NOVALAKE_S)
[07:26:43] [PASSED] 0xD745 (NOVALAKE_S)
[07:26:43] [PASSED] 0x674C (CRESCENTISLAND)
[07:26:43] [PASSED] 0xD750 (NOVALAKE_P)
[07:26:43] [PASSED] 0xD751 (NOVALAKE_P)
[07:26:43] [PASSED] 0xD752 (NOVALAKE_P)
[07:26:43] [PASSED] 0xD753 (NOVALAKE_P)
[07:26:43] [PASSED] 0xD754 (NOVALAKE_P)
[07:26:43] [PASSED] 0xD755 (NOVALAKE_P)
[07:26:43] [PASSED] 0xD756 (NOVALAKE_P)
[07:26:43] [PASSED] 0xD757 (NOVALAKE_P)
[07:26:43] [PASSED] 0xD75F (NOVALAKE_P)
[07:26:43] =============== [PASSED] check_platform_desc ===============
[07:26:43] ===================== [PASSED] xe_pci ======================
[07:26:43] =================== xe_rtp (2 subtests) ====================
[07:26:43] =============== xe_rtp_process_to_sr_tests ================
[07:26:43] [PASSED] coalesce-same-reg
[07:26:43] [PASSED] no-match-no-add
[07:26:43] [PASSED] match-or
[07:26:43] [PASSED] match-or-xfail
[07:26:43] [PASSED] no-match-no-add-multiple-rules
[07:26:43] [PASSED] two-regs-two-entries
[07:26:43] [PASSED] clr-one-set-other
[07:26:43] [PASSED] set-field
[07:26:43] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[07:26:43] [PASSED] conflict-not-disjoint
[07:26:43] [PASSED] conflict-reg-type
[07:26:43] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[07:26:43] ================== xe_rtp_process_tests ===================
[07:26:43] [PASSED] active1
[07:26:43] [PASSED] active2
[07:26:43] [PASSED] active-inactive
[07:26:43] [PASSED] inactive-active
[07:26:43] [PASSED] inactive-1st_or_active-inactive
[07:26:43] [PASSED] inactive-2nd_or_active-inactive
[07:26:43] [PASSED] inactive-last_or_active-inactive
[07:26:43] [PASSED] inactive-no_or_active-inactive
[07:26:43] ============== [PASSED] xe_rtp_process_tests ===============
[07:26:43] ===================== [PASSED] xe_rtp ======================
[07:26:43] ==================== xe_wa (1 subtest) =====================
[07:26:43] ======================== xe_wa_gt =========================
[07:26:43] [PASSED] TIGERLAKE B0
[07:26:43] [PASSED] DG1 A0
[07:26:43] [PASSED] DG1 B0
[07:26:43] [PASSED] ALDERLAKE_S A0
[07:26:43] [PASSED] ALDERLAKE_S B0
[07:26:43] [PASSED] ALDERLAKE_S C0
[07:26:43] [PASSED] ALDERLAKE_S D0
[07:26:43] [PASSED] ALDERLAKE_P A0
[07:26:43] [PASSED] ALDERLAKE_P B0
[07:26:43] [PASSED] ALDERLAKE_P C0
[07:26:43] [PASSED] ALDERLAKE_S RPLS D0
[07:26:43] [PASSED] ALDERLAKE_P RPLU E0
[07:26:43] [PASSED] DG2 G10 C0
[07:26:43] [PASSED] DG2 G11 B1
[07:26:43] [PASSED] DG2 G12 A1
[07:26:43] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[07:26:43] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[07:26:43] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[07:26:43] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[07:26:43] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[07:26:43] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[07:26:43] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[07:26:43] ==================== [PASSED] xe_wa_gt =====================
[07:26:43] ====================== [PASSED] xe_wa ======================
[07:26:43] ============================================================
[07:26:43] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[07:26:43] Elapsed time: 38.412s total, 4.225s configuring, 33.520s building, 0.616s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[07:26:43] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:26:44] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:27:09] Starting KUnit Kernel (1/1)...
[07:27:09] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:27:09] ============ drm_test_pick_cmdline (2 subtests) ============
[07:27:09] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[07:27:09] =============== drm_test_pick_cmdline_named ===============
[07:27:09] [PASSED] NTSC
[07:27:09] [PASSED] NTSC-J
[07:27:09] [PASSED] PAL
[07:27:09] [PASSED] PAL-M
[07:27:09] =========== [PASSED] drm_test_pick_cmdline_named ===========
[07:27:09] ============== [PASSED] drm_test_pick_cmdline ==============
[07:27:09] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[07:27:09] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[07:27:09] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[07:27:09] =========== drm_validate_clone_mode (2 subtests) ===========
[07:27:09] ============== drm_test_check_in_clone_mode ===============
[07:27:09] [PASSED] in_clone_mode
[07:27:09] [PASSED] not_in_clone_mode
[07:27:09] ========== [PASSED] drm_test_check_in_clone_mode ===========
[07:27:09] =============== drm_test_check_valid_clones ===============
[07:27:09] [PASSED] not_in_clone_mode
[07:27:09] [PASSED] valid_clone
[07:27:09] [PASSED] invalid_clone
[07:27:09] =========== [PASSED] drm_test_check_valid_clones ===========
[07:27:09] ============= [PASSED] drm_validate_clone_mode =============
[07:27:09] ============= drm_validate_modeset (1 subtest) =============
[07:27:09] [PASSED] drm_test_check_connector_changed_modeset
[07:27:09] ============== [PASSED] drm_validate_modeset ===============
[07:27:09] ====== drm_test_bridge_get_current_state (2 subtests) ======
[07:27:09] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[07:27:09] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[07:27:09] ======== [PASSED] drm_test_bridge_get_current_state ========
[07:27:09] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[07:27:09] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[07:27:09] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[07:27:09] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[07:27:09] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[07:27:09] ============== drm_bridge_alloc (2 subtests) ===============
[07:27:09] [PASSED] drm_test_drm_bridge_alloc_basic
[07:27:09] [PASSED] drm_test_drm_bridge_alloc_get_put
[07:27:09] ================ [PASSED] drm_bridge_alloc =================
[07:27:09] ============= drm_cmdline_parser (40 subtests) =============
[07:27:09] [PASSED] drm_test_cmdline_force_d_only
[07:27:09] [PASSED] drm_test_cmdline_force_D_only_dvi
[07:27:09] [PASSED] drm_test_cmdline_force_D_only_hdmi
[07:27:09] [PASSED] drm_test_cmdline_force_D_only_not_digital
[07:27:09] [PASSED] drm_test_cmdline_force_e_only
[07:27:09] [PASSED] drm_test_cmdline_res
[07:27:09] [PASSED] drm_test_cmdline_res_vesa
[07:27:09] [PASSED] drm_test_cmdline_res_vesa_rblank
[07:27:09] [PASSED] drm_test_cmdline_res_rblank
[07:27:09] [PASSED] drm_test_cmdline_res_bpp
[07:27:09] [PASSED] drm_test_cmdline_res_refresh
[07:27:09] [PASSED] drm_test_cmdline_res_bpp_refresh
[07:27:09] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[07:27:09] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[07:27:09] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[07:27:09] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[07:27:09] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[07:27:09] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[07:27:09] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[07:27:09] [PASSED] drm_test_cmdline_res_margins_force_on
[07:27:09] [PASSED] drm_test_cmdline_res_vesa_margins
[07:27:09] [PASSED] drm_test_cmdline_name
[07:27:09] [PASSED] drm_test_cmdline_name_bpp
[07:27:09] [PASSED] drm_test_cmdline_name_option
[07:27:09] [PASSED] drm_test_cmdline_name_bpp_option
[07:27:09] [PASSED] drm_test_cmdline_rotate_0
[07:27:09] [PASSED] drm_test_cmdline_rotate_90
[07:27:09] [PASSED] drm_test_cmdline_rotate_180
[07:27:09] [PASSED] drm_test_cmdline_rotate_270
[07:27:09] [PASSED] drm_test_cmdline_hmirror
[07:27:09] [PASSED] drm_test_cmdline_vmirror
[07:27:09] [PASSED] drm_test_cmdline_margin_options
[07:27:09] [PASSED] drm_test_cmdline_multiple_options
[07:27:09] [PASSED] drm_test_cmdline_bpp_extra_and_option
[07:27:09] [PASSED] drm_test_cmdline_extra_and_option
[07:27:09] [PASSED] drm_test_cmdline_freestanding_options
[07:27:09] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[07:27:09] [PASSED] drm_test_cmdline_panel_orientation
[07:27:09] ================ drm_test_cmdline_invalid =================
[07:27:09] [PASSED] margin_only
[07:27:09] [PASSED] interlace_only
[07:27:09] [PASSED] res_missing_x
[07:27:09] [PASSED] res_missing_y
[07:27:09] [PASSED] res_bad_y
[07:27:09] [PASSED] res_missing_y_bpp
[07:27:09] [PASSED] res_bad_bpp
[07:27:09] [PASSED] res_bad_refresh
[07:27:09] [PASSED] res_bpp_refresh_force_on_off
[07:27:09] [PASSED] res_invalid_mode
[07:27:09] [PASSED] res_bpp_wrong_place_mode
[07:27:09] [PASSED] name_bpp_refresh
[07:27:09] [PASSED] name_refresh
[07:27:09] [PASSED] name_refresh_wrong_mode
[07:27:09] [PASSED] name_refresh_invalid_mode
[07:27:09] [PASSED] rotate_multiple
[07:27:09] [PASSED] rotate_invalid_val
[07:27:09] [PASSED] rotate_truncated
[07:27:09] [PASSED] invalid_option
[07:27:09] [PASSED] invalid_tv_option
[07:27:09] [PASSED] truncated_tv_option
[07:27:09] ============ [PASSED] drm_test_cmdline_invalid =============
[07:27:09] =============== drm_test_cmdline_tv_options ===============
[07:27:09] [PASSED] NTSC
[07:27:09] [PASSED] NTSC_443
[07:27:09] [PASSED] NTSC_J
[07:27:09] [PASSED] PAL
[07:27:09] [PASSED] PAL_M
[07:27:09] [PASSED] PAL_N
[07:27:09] [PASSED] SECAM
[07:27:09] [PASSED] MONO_525
[07:27:09] [PASSED] MONO_625
[07:27:09] =========== [PASSED] drm_test_cmdline_tv_options ===========
[07:27:09] =============== [PASSED] drm_cmdline_parser ================
[07:27:09] ========== drmm_connector_hdmi_init (20 subtests) ==========
[07:27:09] [PASSED] drm_test_connector_hdmi_init_valid
[07:27:09] [PASSED] drm_test_connector_hdmi_init_bpc_8
[07:27:09] [PASSED] drm_test_connector_hdmi_init_bpc_10
[07:27:09] [PASSED] drm_test_connector_hdmi_init_bpc_12
[07:27:09] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[07:27:09] [PASSED] drm_test_connector_hdmi_init_bpc_null
[07:27:09] [PASSED] drm_test_connector_hdmi_init_formats_empty
[07:27:09] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[07:27:09] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[07:27:09] [PASSED] supported_formats=0x9 yuv420_allowed=1
[07:27:09] [PASSED] supported_formats=0x9 yuv420_allowed=0
[07:27:09] [PASSED] supported_formats=0x3 yuv420_allowed=1
[07:27:09] [PASSED] supported_formats=0x3 yuv420_allowed=0
[07:27:09] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[07:27:09] [PASSED] drm_test_connector_hdmi_init_null_ddc
[07:27:09] [PASSED] drm_test_connector_hdmi_init_null_product
[07:27:09] [PASSED] drm_test_connector_hdmi_init_null_vendor
[07:27:09] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[07:27:09] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[07:27:09] [PASSED] drm_test_connector_hdmi_init_product_valid
[07:27:09] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[07:27:09] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[07:27:09] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[07:27:09] ========= drm_test_connector_hdmi_init_type_valid =========
[07:27:09] [PASSED] HDMI-A
[07:27:09] [PASSED] HDMI-B
[07:27:09] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[07:27:09] ======== drm_test_connector_hdmi_init_type_invalid ========
[07:27:09] [PASSED] Unknown
[07:27:09] [PASSED] VGA
[07:27:09] [PASSED] DVI-I
[07:27:09] [PASSED] DVI-D
[07:27:09] [PASSED] DVI-A
[07:27:09] [PASSED] Composite
[07:27:09] [PASSED] SVIDEO
[07:27:09] [PASSED] LVDS
[07:27:09] [PASSED] Component
[07:27:09] [PASSED] DIN
[07:27:09] [PASSED] DP
[07:27:09] [PASSED] TV
[07:27:09] [PASSED] eDP
[07:27:09] [PASSED] Virtual
[07:27:09] [PASSED] DSI
[07:27:09] [PASSED] DPI
[07:27:09] [PASSED] Writeback
[07:27:09] [PASSED] SPI
[07:27:09] [PASSED] USB
[07:27:09] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[07:27:09] ============ [PASSED] drmm_connector_hdmi_init =============
[07:27:09] ============= drmm_connector_init (3 subtests) =============
[07:27:09] [PASSED] drm_test_drmm_connector_init
[07:27:09] [PASSED] drm_test_drmm_connector_init_null_ddc
[07:27:09] ========= drm_test_drmm_connector_init_type_valid =========
[07:27:09] [PASSED] Unknown
[07:27:09] [PASSED] VGA
[07:27:09] [PASSED] DVI-I
[07:27:09] [PASSED] DVI-D
[07:27:09] [PASSED] DVI-A
[07:27:09] [PASSED] Composite
[07:27:09] [PASSED] SVIDEO
[07:27:09] [PASSED] LVDS
[07:27:09] [PASSED] Component
[07:27:09] [PASSED] DIN
[07:27:09] [PASSED] DP
[07:27:09] [PASSED] HDMI-A
[07:27:09] [PASSED] HDMI-B
[07:27:09] [PASSED] TV
[07:27:09] [PASSED] eDP
[07:27:09] [PASSED] Virtual
[07:27:09] [PASSED] DSI
[07:27:09] [PASSED] DPI
[07:27:09] [PASSED] Writeback
[07:27:09] [PASSED] SPI
[07:27:09] [PASSED] USB
[07:27:09] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[07:27:09] =============== [PASSED] drmm_connector_init ===============
[07:27:09] ========= drm_connector_dynamic_init (6 subtests) ==========
[07:27:09] [PASSED] drm_test_drm_connector_dynamic_init
[07:27:09] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[07:27:09] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[07:27:09] [PASSED] drm_test_drm_connector_dynamic_init_properties
[07:27:09] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[07:27:09] [PASSED] Unknown
[07:27:09] [PASSED] VGA
[07:27:09] [PASSED] DVI-I
[07:27:09] [PASSED] DVI-D
[07:27:09] [PASSED] DVI-A
[07:27:09] [PASSED] Composite
[07:27:09] [PASSED] SVIDEO
[07:27:09] [PASSED] LVDS
[07:27:09] [PASSED] Component
[07:27:09] [PASSED] DIN
[07:27:09] [PASSED] DP
[07:27:09] [PASSED] HDMI-A
[07:27:09] [PASSED] HDMI-B
[07:27:09] [PASSED] TV
[07:27:09] [PASSED] eDP
[07:27:09] [PASSED] Virtual
[07:27:09] [PASSED] DSI
[07:27:09] [PASSED] DPI
[07:27:09] [PASSED] Writeback
[07:27:09] [PASSED] SPI
[07:27:09] [PASSED] USB
[07:27:09] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[07:27:09] ======== drm_test_drm_connector_dynamic_init_name =========
[07:27:09] [PASSED] Unknown
[07:27:09] [PASSED] VGA
[07:27:09] [PASSED] DVI-I
[07:27:09] [PASSED] DVI-D
[07:27:09] [PASSED] DVI-A
[07:27:09] [PASSED] Composite
[07:27:09] [PASSED] SVIDEO
[07:27:09] [PASSED] LVDS
[07:27:09] [PASSED] Component
[07:27:09] [PASSED] DIN
[07:27:09] [PASSED] DP
[07:27:09] [PASSED] HDMI-A
[07:27:09] [PASSED] HDMI-B
[07:27:09] [PASSED] TV
[07:27:09] [PASSED] eDP
[07:27:09] [PASSED] Virtual
[07:27:09] [PASSED] DSI
[07:27:09] [PASSED] DPI
[07:27:09] [PASSED] Writeback
[07:27:09] [PASSED] SPI
[07:27:09] [PASSED] USB
[07:27:09] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[07:27:09] =========== [PASSED] drm_connector_dynamic_init ============
[07:27:09] ==== drm_connector_dynamic_register_early (4 subtests) =====
[07:27:09] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[07:27:09] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[07:27:09] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[07:27:09] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[07:27:09] ====== [PASSED] drm_connector_dynamic_register_early =======
[07:27:09] ======= drm_connector_dynamic_register (7 subtests) ========
[07:27:09] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[07:27:09] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[07:27:09] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[07:27:09] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[07:27:09] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[07:27:09] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[07:27:09] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[07:27:09] ========= [PASSED] drm_connector_dynamic_register ==========
[07:27:09] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[07:27:09] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[07:27:09] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[07:27:09] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[07:27:09] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[07:27:09] ========== drm_test_get_tv_mode_from_name_valid ===========
[07:27:09] [PASSED] NTSC
[07:27:09] [PASSED] NTSC-443
[07:27:09] [PASSED] NTSC-J
[07:27:09] [PASSED] PAL
[07:27:09] [PASSED] PAL-M
[07:27:09] [PASSED] PAL-N
[07:27:09] [PASSED] SECAM
[07:27:09] [PASSED] Mono
[07:27:09] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[07:27:09] [PASSED] drm_test_get_tv_mode_from_name_truncated
[07:27:09] ============ [PASSED] drm_get_tv_mode_from_name ============
[07:27:09] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[07:27:09] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[07:27:09] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[07:27:09] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[07:27:09] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[07:27:09] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[07:27:09] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[07:27:09] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[07:27:09] [PASSED] VIC 96
[07:27:09] [PASSED] VIC 97
[07:27:09] [PASSED] VIC 101
[07:27:09] [PASSED] VIC 102
[07:27:09] [PASSED] VIC 106
[07:27:09] [PASSED] VIC 107
[07:27:09] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[07:27:09] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[07:27:09] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[07:27:09] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[07:27:09] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[07:27:09] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[07:27:09] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[07:27:09] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[07:27:09] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[07:27:09] [PASSED] Automatic
[07:27:09] [PASSED] Full
[07:27:09] [PASSED] Limited 16:235
[07:27:09] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[07:27:09] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[07:27:09] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[07:27:09] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[07:27:09] === drm_test_drm_hdmi_connector_get_output_format_name ====
[07:27:09] [PASSED] RGB
[07:27:09] [PASSED] YUV 4:2:0
[07:27:09] [PASSED] YUV 4:2:2
[07:27:09] [PASSED] YUV 4:4:4
[07:27:09] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[07:27:09] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[07:27:09] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[07:27:09] ============= drm_damage_helper (21 subtests) ==============
[07:27:09] [PASSED] drm_test_damage_iter_no_damage
[07:27:09] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[07:27:09] [PASSED] drm_test_damage_iter_no_damage_src_moved
[07:27:09] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[07:27:09] [PASSED] drm_test_damage_iter_no_damage_not_visible
[07:27:09] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[07:27:09] [PASSED] drm_test_damage_iter_no_damage_no_fb
[07:27:09] [PASSED] drm_test_damage_iter_simple_damage
[07:27:09] [PASSED] drm_test_damage_iter_single_damage
[07:27:09] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[07:27:09] [PASSED] drm_test_damage_iter_single_damage_outside_src
[07:27:09] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[07:27:09] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[07:27:09] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[07:27:09] [PASSED] drm_test_damage_iter_single_damage_src_moved
[07:27:09] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[07:27:09] [PASSED] drm_test_damage_iter_damage
[07:27:09] [PASSED] drm_test_damage_iter_damage_one_intersect
[07:27:09] [PASSED] drm_test_damage_iter_damage_one_outside
[07:27:09] [PASSED] drm_test_damage_iter_damage_src_moved
[07:27:09] [PASSED] drm_test_damage_iter_damage_not_visible
[07:27:09] ================ [PASSED] drm_damage_helper ================
[07:27:09] ============== drm_dp_mst_helper (3 subtests) ==============
[07:27:09] ============== drm_test_dp_mst_calc_pbn_mode ==============
[07:27:09] [PASSED] Clock 154000 BPP 30 DSC disabled
[07:27:09] [PASSED] Clock 234000 BPP 30 DSC disabled
[07:27:09] [PASSED] Clock 297000 BPP 24 DSC disabled
[07:27:09] [PASSED] Clock 332880 BPP 24 DSC enabled
[07:27:09] [PASSED] Clock 324540 BPP 24 DSC enabled
[07:27:09] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[07:27:09] ============== drm_test_dp_mst_calc_pbn_div ===============
[07:27:09] [PASSED] Link rate 2000000 lane count 4
[07:27:09] [PASSED] Link rate 2000000 lane count 2
[07:27:09] [PASSED] Link rate 2000000 lane count 1
[07:27:09] [PASSED] Link rate 1350000 lane count 4
[07:27:09] [PASSED] Link rate 1350000 lane count 2
[07:27:09] [PASSED] Link rate 1350000 lane count 1
[07:27:09] [PASSED] Link rate 1000000 lane count 4
[07:27:09] [PASSED] Link rate 1000000 lane count 2
[07:27:09] [PASSED] Link rate 1000000 lane count 1
[07:27:09] [PASSED] Link rate 810000 lane count 4
[07:27:09] [PASSED] Link rate 810000 lane count 2
[07:27:09] [PASSED] Link rate 810000 lane count 1
[07:27:09] [PASSED] Link rate 540000 lane count 4
[07:27:09] [PASSED] Link rate 540000 lane count 2
[07:27:09] [PASSED] Link rate 540000 lane count 1
[07:27:09] [PASSED] Link rate 270000 lane count 4
[07:27:09] [PASSED] Link rate 270000 lane count 2
[07:27:09] [PASSED] Link rate 270000 lane count 1
[07:27:09] [PASSED] Link rate 162000 lane count 4
[07:27:09] [PASSED] Link rate 162000 lane count 2
[07:27:09] [PASSED] Link rate 162000 lane count 1
[07:27:09] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[07:27:09] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[07:27:09] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[07:27:09] [PASSED] DP_POWER_UP_PHY with port number
[07:27:09] [PASSED] DP_POWER_DOWN_PHY with port number
[07:27:09] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[07:27:09] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[07:27:09] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[07:27:09] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[07:27:09] [PASSED] DP_QUERY_PAYLOAD with port number
[07:27:09] [PASSED] DP_QUERY_PAYLOAD with VCPI
[07:27:09] [PASSED] DP_REMOTE_DPCD_READ with port number
[07:27:09] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[07:27:09] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[07:27:09] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[07:27:09] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[07:27:09] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[07:27:09] [PASSED] DP_REMOTE_I2C_READ with port number
[07:27:09] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[07:27:09] [PASSED] DP_REMOTE_I2C_READ with transactions array
[07:27:09] [PASSED] DP_REMOTE_I2C_WRITE with port number
[07:27:09] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[07:27:09] [PASSED] DP_REMOTE_I2C_WRITE with data array
[07:27:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[07:27:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[07:27:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[07:27:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[07:27:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[07:27:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[07:27:09] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[07:27:09] ================ [PASSED] drm_dp_mst_helper ================
[07:27:09] ================== drm_exec (7 subtests) ===================
[07:27:09] [PASSED] sanitycheck
[07:27:09] [PASSED] test_lock
[07:27:09] [PASSED] test_lock_unlock
[07:27:09] [PASSED] test_duplicates
[07:27:09] [PASSED] test_prepare
[07:27:09] [PASSED] test_prepare_array
[07:27:09] [PASSED] test_multiple_loops
[07:27:09] ==================== [PASSED] drm_exec =====================
[07:27:09] =========== drm_format_helper_test (17 subtests) ===========
[07:27:09] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[07:27:09] [PASSED] single_pixel_source_buffer
[07:27:09] [PASSED] single_pixel_clip_rectangle
[07:27:09] [PASSED] well_known_colors
[07:27:09] [PASSED] destination_pitch
[07:27:09] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[07:27:09] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[07:27:09] [PASSED] single_pixel_source_buffer
[07:27:09] [PASSED] single_pixel_clip_rectangle
[07:27:09] [PASSED] well_known_colors
[07:27:09] [PASSED] destination_pitch
[07:27:09] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[07:27:09] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[07:27:09] [PASSED] single_pixel_source_buffer
[07:27:09] [PASSED] single_pixel_clip_rectangle
[07:27:09] [PASSED] well_known_colors
[07:27:09] [PASSED] destination_pitch
[07:27:09] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[07:27:09] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[07:27:09] [PASSED] single_pixel_source_buffer
[07:27:09] [PASSED] single_pixel_clip_rectangle
[07:27:09] [PASSED] well_known_colors
[07:27:09] [PASSED] destination_pitch
[07:27:09] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[07:27:09] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[07:27:09] [PASSED] single_pixel_source_buffer
[07:27:09] [PASSED] single_pixel_clip_rectangle
[07:27:09] [PASSED] well_known_colors
[07:27:09] [PASSED] destination_pitch
[07:27:09] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[07:27:09] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[07:27:09] [PASSED] single_pixel_source_buffer
[07:27:09] [PASSED] single_pixel_clip_rectangle
[07:27:09] [PASSED] well_known_colors
[07:27:09] [PASSED] destination_pitch
[07:27:09] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[07:27:09] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[07:27:09] [PASSED] single_pixel_source_buffer
[07:27:09] [PASSED] single_pixel_clip_rectangle
[07:27:09] [PASSED] well_known_colors
[07:27:09] [PASSED] destination_pitch
[07:27:09] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[07:27:09] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[07:27:09] [PASSED] single_pixel_source_buffer
[07:27:09] [PASSED] single_pixel_clip_rectangle
[07:27:09] [PASSED] well_known_colors
[07:27:09] [PASSED] destination_pitch
[07:27:09] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[07:27:09] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[07:27:09] [PASSED] single_pixel_source_buffer
[07:27:09] [PASSED] single_pixel_clip_rectangle
[07:27:09] [PASSED] well_known_colors
[07:27:09] [PASSED] destination_pitch
[07:27:09] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[07:27:09] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[07:27:09] [PASSED] single_pixel_source_buffer
[07:27:09] [PASSED] single_pixel_clip_rectangle
[07:27:09] [PASSED] well_known_colors
[07:27:09] [PASSED] destination_pitch
[07:27:09] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[07:27:09] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[07:27:09] [PASSED] single_pixel_source_buffer
[07:27:09] [PASSED] single_pixel_clip_rectangle
[07:27:09] [PASSED] well_known_colors
[07:27:09] [PASSED] destination_pitch
[07:27:09] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[07:27:09] ============== drm_test_fb_xrgb8888_to_mono ===============
[07:27:09] [PASSED] single_pixel_source_buffer
[07:27:09] [PASSED] single_pixel_clip_rectangle
[07:27:09] [PASSED] well_known_colors
[07:27:09] [PASSED] destination_pitch
[07:27:09] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[07:27:09] ==================== drm_test_fb_swab =====================
[07:27:09] [PASSED] single_pixel_source_buffer
[07:27:09] [PASSED] single_pixel_clip_rectangle
[07:27:09] [PASSED] well_known_colors
[07:27:09] [PASSED] destination_pitch
[07:27:09] ================ [PASSED] drm_test_fb_swab =================
[07:27:09] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[07:27:09] [PASSED] single_pixel_source_buffer
[07:27:09] [PASSED] single_pixel_clip_rectangle
[07:27:09] [PASSED] well_known_colors
[07:27:09] [PASSED] destination_pitch
[07:27:09] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[07:27:09] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[07:27:09] [PASSED] single_pixel_source_buffer
[07:27:09] [PASSED] single_pixel_clip_rectangle
[07:27:09] [PASSED] well_known_colors
[07:27:09] [PASSED] destination_pitch
[07:27:09] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[07:27:09] ================= drm_test_fb_clip_offset =================
[07:27:09] [PASSED] pass through
[07:27:09] [PASSED] horizontal offset
[07:27:09] [PASSED] vertical offset
[07:27:09] [PASSED] horizontal and vertical offset
[07:27:09] [PASSED] horizontal offset (custom pitch)
[07:27:09] [PASSED] vertical offset (custom pitch)
[07:27:09] [PASSED] horizontal and vertical offset (custom pitch)
[07:27:09] ============= [PASSED] drm_test_fb_clip_offset =============
[07:27:09] =================== drm_test_fb_memcpy ====================
[07:27:09] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[07:27:09] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[07:27:09] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[07:27:09] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[07:27:09] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[07:27:09] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[07:27:09] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[07:27:09] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[07:27:09] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[07:27:09] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[07:27:09] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[07:27:09] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[07:27:09] =============== [PASSED] drm_test_fb_memcpy ================
[07:27:09] ============= [PASSED] drm_format_helper_test ==============
[07:27:09] ================= drm_format (18 subtests) =================
[07:27:09] [PASSED] drm_test_format_block_width_invalid
[07:27:09] [PASSED] drm_test_format_block_width_one_plane
[07:27:09] [PASSED] drm_test_format_block_width_two_plane
[07:27:09] [PASSED] drm_test_format_block_width_three_plane
[07:27:09] [PASSED] drm_test_format_block_width_tiled
[07:27:09] [PASSED] drm_test_format_block_height_invalid
[07:27:09] [PASSED] drm_test_format_block_height_one_plane
[07:27:09] [PASSED] drm_test_format_block_height_two_plane
[07:27:09] [PASSED] drm_test_format_block_height_three_plane
[07:27:09] [PASSED] drm_test_format_block_height_tiled
[07:27:09] [PASSED] drm_test_format_min_pitch_invalid
[07:27:09] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[07:27:09] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[07:27:09] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[07:27:09] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[07:27:09] [PASSED] drm_test_format_min_pitch_two_plane
[07:27:09] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[07:27:09] [PASSED] drm_test_format_min_pitch_tiled
[07:27:09] =================== [PASSED] drm_format ====================
[07:27:09] ============== drm_framebuffer (10 subtests) ===============
[07:27:09] ========== drm_test_framebuffer_check_src_coords ==========
[07:27:09] [PASSED] Success: source fits into fb
[07:27:09] [PASSED] Fail: overflowing fb with x-axis coordinate
[07:27:09] [PASSED] Fail: overflowing fb with y-axis coordinate
[07:27:09] [PASSED] Fail: overflowing fb with source width
[07:27:09] [PASSED] Fail: overflowing fb with source height
[07:27:09] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[07:27:09] [PASSED] drm_test_framebuffer_cleanup
[07:27:09] =============== drm_test_framebuffer_create ===============
[07:27:09] [PASSED] ABGR8888 normal sizes
[07:27:09] [PASSED] ABGR8888 max sizes
[07:27:09] [PASSED] ABGR8888 pitch greater than min required
[07:27:09] [PASSED] ABGR8888 pitch less than min required
[07:27:09] [PASSED] ABGR8888 Invalid width
[07:27:09] [PASSED] ABGR8888 Invalid buffer handle
[07:27:09] [PASSED] No pixel format
[07:27:09] [PASSED] ABGR8888 Width 0
[07:27:09] [PASSED] ABGR8888 Height 0
[07:27:09] [PASSED] ABGR8888 Out of bound height * pitch combination
[07:27:09] [PASSED] ABGR8888 Large buffer offset
[07:27:09] [PASSED] ABGR8888 Buffer offset for inexistent plane
[07:27:09] [PASSED] ABGR8888 Invalid flag
[07:27:09] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[07:27:09] [PASSED] ABGR8888 Valid buffer modifier
[07:27:09] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[07:27:09] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[07:27:09] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[07:27:09] [PASSED] NV12 Normal sizes
[07:27:09] [PASSED] NV12 Max sizes
[07:27:09] [PASSED] NV12 Invalid pitch
[07:27:09] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[07:27:09] [PASSED] NV12 different modifier per-plane
[07:27:09] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[07:27:09] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[07:27:09] [PASSED] NV12 Modifier for inexistent plane
[07:27:09] [PASSED] NV12 Handle for inexistent plane
[07:27:09] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[07:27:09] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[07:27:09] [PASSED] YVU420 Normal sizes
[07:27:09] [PASSED] YVU420 Max sizes
[07:27:09] [PASSED] YVU420 Invalid pitch
[07:27:09] [PASSED] YVU420 Different pitches
[07:27:09] [PASSED] YVU420 Different buffer offsets/pitches
[07:27:09] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[07:27:09] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[07:27:09] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[07:27:09] [PASSED] YVU420 Valid modifier
[07:27:09] [PASSED] YVU420 Different modifiers per plane
[07:27:09] [PASSED] YVU420 Modifier for inexistent plane
[07:27:09] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[07:27:09] [PASSED] X0L2 Normal sizes
[07:27:09] [PASSED] X0L2 Max sizes
[07:27:09] [PASSED] X0L2 Invalid pitch
[07:27:09] [PASSED] X0L2 Pitch greater than minimum required
[07:27:09] [PASSED] X0L2 Handle for inexistent plane
[07:27:09] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[07:27:09] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[07:27:09] [PASSED] X0L2 Valid modifier
[07:27:09] [PASSED] X0L2 Modifier for inexistent plane
[07:27:09] =========== [PASSED] drm_test_framebuffer_create ===========
[07:27:09] [PASSED] drm_test_framebuffer_free
[07:27:09] [PASSED] drm_test_framebuffer_init
[07:27:09] [PASSED] drm_test_framebuffer_init_bad_format
[07:27:09] [PASSED] drm_test_framebuffer_init_dev_mismatch
[07:27:09] [PASSED] drm_test_framebuffer_lookup
[07:27:09] [PASSED] drm_test_framebuffer_lookup_inexistent
[07:27:09] [PASSED] drm_test_framebuffer_modifiers_not_supported
[07:27:09] ================= [PASSED] drm_framebuffer =================
[07:27:09] ================ drm_gem_shmem (8 subtests) ================
[07:27:09] [PASSED] drm_gem_shmem_test_obj_create
[07:27:09] [PASSED] drm_gem_shmem_test_obj_create_private
[07:27:09] [PASSED] drm_gem_shmem_test_pin_pages
[07:27:09] [PASSED] drm_gem_shmem_test_vmap
[07:27:09] [PASSED] drm_gem_shmem_test_get_sg_table
[07:27:09] [PASSED] drm_gem_shmem_test_get_pages_sgt
[07:27:09] [PASSED] drm_gem_shmem_test_madvise
[07:27:09] [PASSED] drm_gem_shmem_test_purge
[07:27:09] ================== [PASSED] drm_gem_shmem ==================
[07:27:09] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[07:27:09] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[07:27:09] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[07:27:09] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[07:27:09] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[07:27:09] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[07:27:09] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[07:27:09] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[07:27:09] [PASSED] Automatic
[07:27:09] [PASSED] Full
[07:27:09] [PASSED] Limited 16:235
[07:27:09] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[07:27:09] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[07:27:09] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[07:27:09] [PASSED] drm_test_check_disable_connector
[07:27:09] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[07:27:09] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[07:27:09] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[07:27:09] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[07:27:09] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[07:27:09] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[07:27:09] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[07:27:09] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[07:27:09] [PASSED] drm_test_check_output_bpc_dvi
[07:27:09] [PASSED] drm_test_check_output_bpc_format_vic_1
[07:27:09] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[07:27:09] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[07:27:09] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[07:27:09] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[07:27:09] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[07:27:09] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[07:27:09] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[07:27:09] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[07:27:09] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[07:27:09] [PASSED] drm_test_check_broadcast_rgb_value
[07:27:09] [PASSED] drm_test_check_bpc_8_value
[07:27:09] [PASSED] drm_test_check_bpc_10_value
[07:27:09] [PASSED] drm_test_check_bpc_12_value
[07:27:09] [PASSED] drm_test_check_format_value
[07:27:09] [PASSED] drm_test_check_tmds_char_value
[07:27:09] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[07:27:09] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[07:27:09] [PASSED] drm_test_check_mode_valid
[07:27:09] [PASSED] drm_test_check_mode_valid_reject
[07:27:09] [PASSED] drm_test_check_mode_valid_reject_rate
[07:27:09] [PASSED] drm_test_check_mode_valid_reject_max_clock
[07:27:09] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[07:27:09] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[07:27:09] [PASSED] drm_test_check_infoframes
[07:27:09] [PASSED] drm_test_check_reject_avi_infoframe
[07:27:09] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[07:27:09] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[07:27:09] [PASSED] drm_test_check_reject_audio_infoframe
[07:27:09] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[07:27:09] ================= drm_managed (2 subtests) =================
[07:27:09] [PASSED] drm_test_managed_release_action
[07:27:09] [PASSED] drm_test_managed_run_action
[07:27:09] =================== [PASSED] drm_managed ===================
[07:27:09] =================== drm_mm (6 subtests) ====================
[07:27:09] [PASSED] drm_test_mm_init
[07:27:09] [PASSED] drm_test_mm_debug
[07:27:09] [PASSED] drm_test_mm_align32
[07:27:09] [PASSED] drm_test_mm_align64
[07:27:09] [PASSED] drm_test_mm_lowest
[07:27:09] [PASSED] drm_test_mm_highest
[07:27:09] ===================== [PASSED] drm_mm ======================
[07:27:09] ============= drm_modes_analog_tv (5 subtests) =============
[07:27:09] [PASSED] drm_test_modes_analog_tv_mono_576i
[07:27:09] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[07:27:09] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[07:27:09] [PASSED] drm_test_modes_analog_tv_pal_576i
[07:27:09] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[07:27:09] =============== [PASSED] drm_modes_analog_tv ===============
[07:27:09] ============== drm_plane_helper (2 subtests) ===============
[07:27:09] =============== drm_test_check_plane_state ================
[07:27:09] [PASSED] clipping_simple
[07:27:09] [PASSED] clipping_rotate_reflect
[07:27:09] [PASSED] positioning_simple
[07:27:09] [PASSED] upscaling
[07:27:09] [PASSED] downscaling
[07:27:09] [PASSED] rounding1
[07:27:09] [PASSED] rounding2
[07:27:09] [PASSED] rounding3
[07:27:09] [PASSED] rounding4
[07:27:09] =========== [PASSED] drm_test_check_plane_state ============
[07:27:09] =========== drm_test_check_invalid_plane_state ============
[07:27:09] [PASSED] positioning_invalid
[07:27:09] [PASSED] upscaling_invalid
[07:27:09] [PASSED] downscaling_invalid
[07:27:09] ======= [PASSED] drm_test_check_invalid_plane_state ========
[07:27:09] ================ [PASSED] drm_plane_helper =================
[07:27:09] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[07:27:09] ====== drm_test_connector_helper_tv_get_modes_check =======
[07:27:09] [PASSED] None
[07:27:09] [PASSED] PAL
[07:27:09] [PASSED] NTSC
[07:27:09] [PASSED] Both, NTSC Default
[07:27:09] [PASSED] Both, PAL Default
[07:27:09] [PASSED] Both, NTSC Default, with PAL on command-line
[07:27:09] [PASSED] Both, PAL Default, with NTSC on command-line
[07:27:09] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[07:27:09] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[07:27:09] ================== drm_rect (9 subtests) ===================
[07:27:09] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[07:27:09] [PASSED] drm_test_rect_clip_scaled_not_clipped
[07:27:09] [PASSED] drm_test_rect_clip_scaled_clipped
[07:27:09] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[07:27:09] ================= drm_test_rect_intersect =================
[07:27:09] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[07:27:09] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[07:27:09] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[07:27:09] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[07:27:09] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[07:27:09] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[07:27:09] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[07:27:09] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[07:27:09] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[07:27:09] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[07:27:09] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[07:27:09] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[07:27:09] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[07:27:09] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[07:27:09] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[07:27:09] ============= [PASSED] drm_test_rect_intersect =============
[07:27:09] ================ drm_test_rect_calc_hscale ================
[07:27:09] [PASSED] normal use
[07:27:09] [PASSED] out of max range
[07:27:09] [PASSED] out of min range
[07:27:09] [PASSED] zero dst
[07:27:09] [PASSED] negative src
[07:27:09] [PASSED] negative dst
[07:27:09] ============ [PASSED] drm_test_rect_calc_hscale ============
[07:27:09] ================ drm_test_rect_calc_vscale ================
[07:27:09] [PASSED] normal use
[07:27:09] [PASSED] out of max range
[07:27:09] [PASSED] out of min range
[07:27:09] [PASSED] zero dst
[07:27:09] [PASSED] negative src
[07:27:09] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[07:27:09] ============ [PASSED] drm_test_rect_calc_vscale ============
[07:27:09] ================== drm_test_rect_rotate ===================
[07:27:09] [PASSED] reflect-x
[07:27:09] [PASSED] reflect-y
[07:27:09] [PASSED] rotate-0
[07:27:09] [PASSED] rotate-90
[07:27:09] [PASSED] rotate-180
[07:27:09] [PASSED] rotate-270
[07:27:09] ============== [PASSED] drm_test_rect_rotate ===============
[07:27:09] ================ drm_test_rect_rotate_inv =================
[07:27:09] [PASSED] reflect-x
[07:27:09] [PASSED] reflect-y
[07:27:09] [PASSED] rotate-0
[07:27:09] [PASSED] rotate-90
[07:27:09] [PASSED] rotate-180
[07:27:09] [PASSED] rotate-270
[07:27:09] ============ [PASSED] drm_test_rect_rotate_inv =============
[07:27:09] ==================== [PASSED] drm_rect =====================
[07:27:09] ============ drm_sysfb_modeset_test (1 subtest) ============
[07:27:09] ============ drm_test_sysfb_build_fourcc_list =============
[07:27:09] [PASSED] no native formats
[07:27:09] [PASSED] XRGB8888 as native format
[07:27:09] [PASSED] remove duplicates
[07:27:09] [PASSED] convert alpha formats
[07:27:09] [PASSED] random formats
[07:27:09] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[07:27:09] ============= [PASSED] drm_sysfb_modeset_test ==============
[07:27:09] ================== drm_fixp (2 subtests) ===================
[07:27:09] [PASSED] drm_test_int2fixp
[07:27:09] [PASSED] drm_test_sm2fixp
[07:27:09] ==================== [PASSED] drm_fixp =====================
[07:27:09] ============================================================
[07:27:09] Testing complete. Ran 621 tests: passed: 621
[07:27:09] Elapsed time: 26.692s total, 1.751s configuring, 24.775s building, 0.133s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[07:27:10] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:27:11] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:27:21] Starting KUnit Kernel (1/1)...
[07:27:21] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:27:21] ================= ttm_device (5 subtests) ==================
[07:27:21] [PASSED] ttm_device_init_basic
[07:27:21] [PASSED] ttm_device_init_multiple
[07:27:21] [PASSED] ttm_device_fini_basic
[07:27:21] [PASSED] ttm_device_init_no_vma_man
[07:27:21] ================== ttm_device_init_pools ==================
[07:27:21] [PASSED] No DMA allocations, no DMA32 required
[07:27:21] [PASSED] DMA allocations, DMA32 required
[07:27:21] [PASSED] No DMA allocations, DMA32 required
[07:27:21] [PASSED] DMA allocations, no DMA32 required
[07:27:21] ============== [PASSED] ttm_device_init_pools ==============
[07:27:21] =================== [PASSED] ttm_device ====================
[07:27:21] ================== ttm_pool (8 subtests) ===================
[07:27:21] ================== ttm_pool_alloc_basic ===================
[07:27:21] [PASSED] One page
[07:27:21] [PASSED] More than one page
[07:27:21] [PASSED] Above the allocation limit
[07:27:21] [PASSED] One page, with coherent DMA mappings enabled
[07:27:21] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[07:27:21] ============== [PASSED] ttm_pool_alloc_basic ===============
[07:27:21] ============== ttm_pool_alloc_basic_dma_addr ==============
[07:27:21] [PASSED] One page
[07:27:21] [PASSED] More than one page
[07:27:21] [PASSED] Above the allocation limit
[07:27:21] [PASSED] One page, with coherent DMA mappings enabled
[07:27:21] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[07:27:21] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[07:27:21] [PASSED] ttm_pool_alloc_order_caching_match
[07:27:21] [PASSED] ttm_pool_alloc_caching_mismatch
[07:27:21] [PASSED] ttm_pool_alloc_order_mismatch
[07:27:21] [PASSED] ttm_pool_free_dma_alloc
[07:27:21] [PASSED] ttm_pool_free_no_dma_alloc
[07:27:21] [PASSED] ttm_pool_fini_basic
[07:27:21] ==================== [PASSED] ttm_pool =====================
[07:27:21] ================ ttm_resource (8 subtests) =================
[07:27:21] ================= ttm_resource_init_basic =================
[07:27:21] [PASSED] Init resource in TTM_PL_SYSTEM
[07:27:21] [PASSED] Init resource in TTM_PL_VRAM
[07:27:21] [PASSED] Init resource in a private placement
[07:27:21] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[07:27:21] ============= [PASSED] ttm_resource_init_basic =============
[07:27:21] [PASSED] ttm_resource_init_pinned
[07:27:21] [PASSED] ttm_resource_fini_basic
[07:27:21] [PASSED] ttm_resource_manager_init_basic
[07:27:21] [PASSED] ttm_resource_manager_usage_basic
[07:27:21] [PASSED] ttm_resource_manager_set_used_basic
[07:27:21] [PASSED] ttm_sys_man_alloc_basic
[07:27:21] [PASSED] ttm_sys_man_free_basic
[07:27:21] ================== [PASSED] ttm_resource ===================
[07:27:21] =================== ttm_tt (15 subtests) ===================
[07:27:21] ==================== ttm_tt_init_basic ====================
[07:27:21] [PASSED] Page-aligned size
[07:27:21] [PASSED] Extra pages requested
[07:27:21] ================ [PASSED] ttm_tt_init_basic ================
[07:27:21] [PASSED] ttm_tt_init_misaligned
[07:27:21] [PASSED] ttm_tt_fini_basic
[07:27:21] [PASSED] ttm_tt_fini_sg
[07:27:21] [PASSED] ttm_tt_fini_shmem
[07:27:21] [PASSED] ttm_tt_create_basic
[07:27:21] [PASSED] ttm_tt_create_invalid_bo_type
[07:27:21] [PASSED] ttm_tt_create_ttm_exists
[07:27:21] [PASSED] ttm_tt_create_failed
[07:27:21] [PASSED] ttm_tt_destroy_basic
[07:27:21] [PASSED] ttm_tt_populate_null_ttm
[07:27:21] [PASSED] ttm_tt_populate_populated_ttm
[07:27:21] [PASSED] ttm_tt_unpopulate_basic
[07:27:21] [PASSED] ttm_tt_unpopulate_empty_ttm
[07:27:21] [PASSED] ttm_tt_swapin_basic
[07:27:21] ===================== [PASSED] ttm_tt ======================
[07:27:21] =================== ttm_bo (14 subtests) ===================
[07:27:21] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[07:27:21] [PASSED] Cannot be interrupted and sleeps
[07:27:21] [PASSED] Cannot be interrupted, locks straight away
[07:27:21] [PASSED] Can be interrupted, sleeps
[07:27:21] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[07:27:21] [PASSED] ttm_bo_reserve_locked_no_sleep
[07:27:21] [PASSED] ttm_bo_reserve_no_wait_ticket
[07:27:21] [PASSED] ttm_bo_reserve_double_resv
[07:27:21] [PASSED] ttm_bo_reserve_interrupted
[07:27:21] [PASSED] ttm_bo_reserve_deadlock
[07:27:21] [PASSED] ttm_bo_unreserve_basic
[07:27:21] [PASSED] ttm_bo_unreserve_pinned
[07:27:21] [PASSED] ttm_bo_unreserve_bulk
[07:27:21] [PASSED] ttm_bo_fini_basic
[07:27:21] [PASSED] ttm_bo_fini_shared_resv
[07:27:21] [PASSED] ttm_bo_pin_basic
[07:27:21] [PASSED] ttm_bo_pin_unpin_resource
[07:27:21] [PASSED] ttm_bo_multiple_pin_one_unpin
[07:27:21] ===================== [PASSED] ttm_bo ======================
[07:27:21] ============== ttm_bo_validate (21 subtests) ===============
[07:27:21] ============== ttm_bo_init_reserved_sys_man ===============
[07:27:21] [PASSED] Buffer object for userspace
[07:27:21] [PASSED] Kernel buffer object
[07:27:21] [PASSED] Shared buffer object
[07:27:21] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[07:27:21] ============== ttm_bo_init_reserved_mock_man ==============
[07:27:21] [PASSED] Buffer object for userspace
[07:27:21] [PASSED] Kernel buffer object
[07:27:21] [PASSED] Shared buffer object
[07:27:21] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[07:27:21] [PASSED] ttm_bo_init_reserved_resv
[07:27:21] ================== ttm_bo_validate_basic ==================
[07:27:21] [PASSED] Buffer object for userspace
[07:27:21] [PASSED] Kernel buffer object
[07:27:21] [PASSED] Shared buffer object
[07:27:21] ============== [PASSED] ttm_bo_validate_basic ==============
[07:27:21] [PASSED] ttm_bo_validate_invalid_placement
[07:27:21] ============= ttm_bo_validate_same_placement ==============
[07:27:21] [PASSED] System manager
[07:27:21] [PASSED] VRAM manager
[07:27:21] ========= [PASSED] ttm_bo_validate_same_placement ==========
[07:27:21] [PASSED] ttm_bo_validate_failed_alloc
[07:27:21] [PASSED] ttm_bo_validate_pinned
[07:27:21] [PASSED] ttm_bo_validate_busy_placement
[07:27:21] ================ ttm_bo_validate_multihop =================
[07:27:21] [PASSED] Buffer object for userspace
[07:27:21] [PASSED] Kernel buffer object
[07:27:21] [PASSED] Shared buffer object
[07:27:21] ============ [PASSED] ttm_bo_validate_multihop =============
[07:27:21] ========== ttm_bo_validate_no_placement_signaled ==========
[07:27:21] [PASSED] Buffer object in system domain, no page vector
[07:27:21] [PASSED] Buffer object in system domain with an existing page vector
[07:27:21] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[07:27:21] ======== ttm_bo_validate_no_placement_not_signaled ========
[07:27:21] [PASSED] Buffer object for userspace
[07:27:21] [PASSED] Kernel buffer object
[07:27:21] [PASSED] Shared buffer object
[07:27:21] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[07:27:21] [PASSED] ttm_bo_validate_move_fence_signaled
[07:27:21] ========= ttm_bo_validate_move_fence_not_signaled =========
[07:27:21] [PASSED] Waits for GPU
[07:27:21] [PASSED] Tries to lock straight away
[07:27:21] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[07:27:21] [PASSED] ttm_bo_validate_happy_evict
[07:27:21] [PASSED] ttm_bo_validate_all_pinned_evict
[07:27:21] [PASSED] ttm_bo_validate_allowed_only_evict
[07:27:21] [PASSED] ttm_bo_validate_deleted_evict
[07:27:21] [PASSED] ttm_bo_validate_busy_domain_evict
[07:27:21] [PASSED] ttm_bo_validate_evict_gutting
[07:27:21] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[07:27:21] ================= [PASSED] ttm_bo_validate =================
[07:27:21] ============================================================
[07:27:21] Testing complete. Ran 101 tests: passed: 101
[07:27:21] Elapsed time: 11.372s total, 1.708s configuring, 9.447s building, 0.180s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Xe.CI.BAT: success for drm/xe/xe3p_lpg: L2 flush optimization (rev6)
2026-03-03 6:24 [PATCH V5 0/4] drm/xe/xe3p_lpg: L2 flush optimization Tejas Upadhyay
` (4 preceding siblings ...)
2026-03-03 7:27 ` ✓ CI.KUnit: success for drm/xe/xe3p_lpg: L2 flush optimization (rev6) Patchwork
@ 2026-03-03 8:22 ` Patchwork
2026-03-03 17:06 ` ✓ Xe.CI.FULL: " Patchwork
6 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2026-03-03 8:22 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 2158 bytes --]
== Series Details ==
Series: drm/xe/xe3p_lpg: L2 flush optimization (rev6)
URL : https://patchwork.freedesktop.org/series/158017/
State : success
== Summary ==
CI Bug Log - changes from xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143_BAT -> xe-pw-158017v6_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 14)
------------------------------
Additional (1): bat-bmg-3
Known issues
------------
Here are the changes found in xe-pw-158017v6_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@xe_module_load@load:
- bat-bmg-3: NOTRUN -> [DMESG-WARN][1] ([Intel XE#7433])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/bat-bmg-3/igt@xe_module_load@load.html
* igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p:
- bat-bmg-3: NOTRUN -> [SKIP][2] ([Intel XE#6566]) +3 other tests skip
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/bat-bmg-3/igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p.html
#### Possible fixes ####
* igt@xe_waitfence@reltime:
- bat-dg2-oem2: [FAIL][3] ([Intel XE#6520]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/bat-dg2-oem2/igt@xe_waitfence@reltime.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/bat-dg2-oem2/igt@xe_waitfence@reltime.html
[Intel XE#6520]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6520
[Intel XE#6566]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6566
[Intel XE#7433]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7433
Build changes
-------------
* Linux: xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143 -> xe-pw-158017v6
IGT_8777: a50285a68dbef0fe11140adef4016a756f57b324 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143: 69ee18cb718c8e62d92b25235881fc562e71a143
xe-pw-158017v6: 158017v6
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/index.html
[-- Attachment #2: Type: text/html, Size: 2777 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V5 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization
2026-03-03 6:24 ` [PATCH V5 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization Tejas Upadhyay
@ 2026-03-03 14:56 ` Souza, Jose
2026-03-05 11:02 ` Thomas Hellström
1 sibling, 0 replies; 13+ messages in thread
From: Souza, Jose @ 2026-03-03 14:56 UTC (permalink / raw)
To: intel-xe@lists.freedesktop.org, Upadhyay, Tejas
Cc: Zhang, Carl, Auld, Matthew, thomas.hellstrom@linux.intel.com,
Mrozek, Michal
On Tue, 2026-03-03 at 11:54 +0530, Tejas Upadhyay wrote:
> When set, starting xe3p_lpg, the L2 flush optimization
> feature will control whether L2 is in Persistent or
> Transient mode through monitoring of media activity.
>
> To enable L2 flush optimization include new feature flag
> GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when
> media type is detected.
>
> Tighten UAPI validation to restrict userptr, svm and
> dmabuf mappings to be either 2WAY or XA+1WAY
>
> V4(MattA): Modify uapi doc and commit
> V3(MattA): check valid op and pat_index value
> V2(MattA): validate dma-buf bos and madvise pat-index
Acked-by: José Roberto de Souza <jose.souza@intel.com>
>
> Acked-by: Michal Mrozek <michal.mrozek@intel.com>
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> ---
> drivers/gpu/drm/xe/xe_guc.c | 3 +++
> drivers/gpu/drm/xe/xe_guc_fwif.h | 1 +
> drivers/gpu/drm/xe/xe_vm.c | 8 ++++++++
> drivers/gpu/drm/xe/xe_vm_madvise.c | 23 +++++++++++++++++++++++
> include/uapi/drm/xe_drm.h | 4 +++-
> 5 files changed, 38 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc.c
> b/drivers/gpu/drm/xe/xe_guc.c
> index 54d2fc780127..43dc4353206f 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -98,6 +98,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc
> *guc)
> if (xe_guc_using_main_gamctrl_queues(guc))
> flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
>
> + if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) &&
> xe_gt_is_media_type(guc_to_gt(guc)))
> + flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
> +
> return flags;
> }
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h
> b/drivers/gpu/drm/xe/xe_guc_fwif.h
> index bb8f71d38611..b73fae063fac 100644
> --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> @@ -67,6 +67,7 @@ struct guc_update_exec_queue_policy {
> #define GUC_CTL_ENABLE_PSMI_LOGGING BIT(7)
> #define GUC_CTL_MAIN_GAMCTRL_QUEUES BIT(9)
> #define GUC_CTL_DISABLE_SCHEDULER BIT(14)
> +#define GUC_CTL_ENABLE_L2FLUSH_OPT BIT(15)
>
> #define GUC_CTL_DEBUG 3
> #define GUC_LOG_VERBOSITY REG_GENMASK(1, 0)
> diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
> index da0ce0b3704c..424e1c742b95 100644
> --- a/drivers/gpu/drm/xe/xe_vm.c
> +++ b/drivers/gpu/drm/xe/xe_vm.c
> @@ -3481,6 +3481,10 @@ static int vm_bind_ioctl_check_args(struct
> xe_device *xe, struct xe_vm *vm,
> op ==
> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
> op ==
> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> + XE_IOCTL_DBG(xe,
> xe_device_is_l2_flush_optimized(xe) &&
> + (op ==
> DRM_XE_VM_BIND_OP_MAP_USERPTR ||
> + is_cpu_addr_mirror) &&
> + (pat_index != 19 || coh_mode !=
> XE_COH_2WAY)) ||
> XE_IOCTL_DBG(xe, comp_en &&
> op ==
> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> XE_IOCTL_DBG(xe, op ==
> DRM_XE_VM_BIND_OP_MAP_USERPTR &&
> @@ -3615,6 +3619,10 @@ static int xe_vm_bind_ioctl_validate_bo(struct
> xe_device *xe, struct xe_bo *bo,
> if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach && comp_en))
> return -EINVAL;
>
> + if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
> xe_device_is_l2_flush_optimized(xe) &&
> + (pat_index != 19 || coh_mode !=
> XE_COH_2WAY)))
> + return -EINVAL;
> +
> /* If a BO is protected it can only be mapped if the key is
> still valid */
> if ((bind_flags & DRM_XE_VM_BIND_FLAG_CHECK_PXP) &&
> xe_bo_is_protected(bo) &&
> op != DRM_XE_VM_BIND_OP_UNMAP && op !=
> DRM_XE_VM_BIND_OP_UNMAP_ALL)
> diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c
> b/drivers/gpu/drm/xe/xe_vm_madvise.c
> index 1a1ad8c07d49..e669e578618b 100644
> --- a/drivers/gpu/drm/xe/xe_vm_madvise.c
> +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
> @@ -411,6 +411,7 @@ int xe_vm_madvise_ioctl(struct drm_device *dev,
> void *data, struct drm_file *fil
> struct xe_vmas_in_madvise_range madvise_range = {.addr =
> args->start,
> .range =
> args->range, };
> struct xe_madvise_details details;
> + u16 pat_index, coh_mode;
> struct xe_vm *vm;
> struct drm_exec exec;
> int err, attr_type;
> @@ -447,6 +448,17 @@ int xe_vm_madvise_ioctl(struct drm_device *dev,
> void *data, struct drm_file *fil
> if (err || !madvise_range.num_vmas)
> goto madv_fini;
>
> + if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) {
> + pat_index = array_index_nospec(args->pat_index.val,
> xe->pat.n_entries);
> + coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
> + if (XE_IOCTL_DBG(xe,
> madvise_range.has_svm_userptr_vmas &&
> + xe_device_is_l2_flush_optimized(xe)
> &&
> + (pat_index != 19 || coh_mode !=
> XE_COH_2WAY))) {
> + err = -EINVAL;
> + goto madv_fini;
> + }
> + }
> +
> if (madvise_range.has_bo_vmas) {
> if (args->type == DRM_XE_MEM_RANGE_ATTR_ATOMIC) {
> if (!check_bo_args_are_sane(vm,
> madvise_range.vmas,
> @@ -464,6 +476,17 @@ int xe_vm_madvise_ioctl(struct drm_device *dev,
> void *data, struct drm_file *fil
>
> if (!bo)
> continue;
> +
> + if (args->type ==
> DRM_XE_MEM_RANGE_ATTR_PAT) {
> + if (XE_IOCTL_DBG(xe, bo-
> >ttm.base.import_attach &&
> +
> xe_device_is_l2_flush_optimized(xe) &&
> + (pat_index
> != 19 ||
> + coh_mode
> != XE_COH_2WAY))) {
> + err = -EINVAL;
> + goto err_fini;
> + }
> + }
> +
> err = drm_exec_lock_obj(&exec, &bo-
> >ttm.base);
> drm_exec_retry_on_contention(&exec);
> if (err)
> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> index ef2565048bdf..862fed3cf1ed 100644
> --- a/include/uapi/drm/xe_drm.h
> +++ b/include/uapi/drm/xe_drm.h
> @@ -1103,7 +1103,9 @@ struct drm_xe_vm_bind_op {
> * incoherent GT access is possible.
> *
> * Note: For userptr and externally imported dma-buf the
> kernel expects
> - * either 1WAY or 2WAY for the @pat_index.
> + * either 1WAY or 2WAY for the @pat_index. Starting from
> NVL-P, for
> + * userptr, svm, madvise and externally imported dma-buf the
> kernel expects
> + * either 2WAY or 1WAY and XA @pat_index.
> *
> * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD
> restrictions
> * on the @pat_index. For such mappings there is no actual
> memory being
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Xe.CI.FULL: success for drm/xe/xe3p_lpg: L2 flush optimization (rev6)
2026-03-03 6:24 [PATCH V5 0/4] drm/xe/xe3p_lpg: L2 flush optimization Tejas Upadhyay
` (5 preceding siblings ...)
2026-03-03 8:22 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-03-03 17:06 ` Patchwork
6 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2026-03-03 17:06 UTC (permalink / raw)
To: Upadhyay, Tejas; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 9948 bytes --]
== Series Details ==
Series: drm/xe/xe3p_lpg: L2 flush optimization (rev6)
URL : https://patchwork.freedesktop.org/series/158017/
State : success
== Summary ==
CI Bug Log - changes from xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143_FULL -> xe-pw-158017v6_FULL
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-158017v6_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-lnl: [PASS][1] -> [FAIL][2] ([Intel XE#301]) +2 other tests fail
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma:
- shard-lnl: [PASS][3] -> [FAIL][4] ([Intel XE#5625])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-lnl-8/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-lnl-2/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html
#### Possible fixes ####
* igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma:
- shard-lnl: [FAIL][5] ([Intel XE#5625]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-lnl-5/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-lnl-4/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html
#### Warnings ####
* igt@xe_module_load@load:
- shard-bmg: ([DMESG-WARN][7], [DMESG-WARN][8], [DMESG-WARN][9], [PASS][10], [DMESG-WARN][11], [DMESG-WARN][12], [DMESG-WARN][13], [DMESG-WARN][14], [DMESG-WARN][15], [DMESG-WARN][16], [DMESG-WARN][17], [DMESG-WARN][18], [DMESG-WARN][19], [DMESG-WARN][20], [DMESG-WARN][21], [DMESG-WARN][22], [DMESG-WARN][23], [DMESG-WARN][24], [DMESG-WARN][25], [DMESG-WARN][26], [DMESG-WARN][27], [DMESG-WARN][28], [DMESG-WARN][29], [PASS][30], [DMESG-WARN][31]) ([Intel XE#7433]) -> ([DMESG-WARN][32], [DMESG-WARN][33], [DMESG-WARN][34], [DMESG-WARN][35], [DMESG-WARN][36], [DMESG-WARN][37], [DMESG-WARN][38], [DMESG-WARN][39], [DMESG-WARN][40], [DMESG-WARN][41], [DMESG-WARN][42], [DMESG-WARN][43], [DMESG-WARN][44], [DMESG-WARN][45], [DMESG-WARN][46], [DMESG-WARN][47], [DMESG-WARN][48], [DMESG-WARN][49], [DMESG-WARN][50], [DMESG-WARN][51], [DMESG-WARN][52], [DMESG-WARN][53], [DMESG-WARN][54], [DMESG-WARN][55], [DMESG-WARN][56]) ([Intel XE#7433])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-2/igt@xe_module_load@load.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-5/igt@xe_module_load@load.html
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-5/igt@xe_module_load@load.html
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-3/igt@xe_module_load@load.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-6/igt@xe_module_load@load.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-6/igt@xe_module_load@load.html
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-6/igt@xe_module_load@load.html
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-8/igt@xe_module_load@load.html
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-8/igt@xe_module_load@load.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-8/igt@xe_module_load@load.html
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-4/igt@xe_module_load@load.html
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-4/igt@xe_module_load@load.html
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-4/igt@xe_module_load@load.html
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-2/igt@xe_module_load@load.html
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-2/igt@xe_module_load@load.html
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-9/igt@xe_module_load@load.html
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-9/igt@xe_module_load@load.html
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-9/igt@xe_module_load@load.html
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-7/igt@xe_module_load@load.html
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-7/igt@xe_module_load@load.html
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-7/igt@xe_module_load@load.html
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-1/igt@xe_module_load@load.html
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-1/igt@xe_module_load@load.html
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-3/igt@xe_module_load@load.html
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143/shard-bmg-1/igt@xe_module_load@load.html
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-8/igt@xe_module_load@load.html
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-3/igt@xe_module_load@load.html
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-8/igt@xe_module_load@load.html
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-3/igt@xe_module_load@load.html
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-3/igt@xe_module_load@load.html
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-6/igt@xe_module_load@load.html
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-6/igt@xe_module_load@load.html
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-5/igt@xe_module_load@load.html
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-8/igt@xe_module_load@load.html
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-4/igt@xe_module_load@load.html
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-4/igt@xe_module_load@load.html
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-1/igt@xe_module_load@load.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-1/igt@xe_module_load@load.html
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-1/igt@xe_module_load@load.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-7/igt@xe_module_load@load.html
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-7/igt@xe_module_load@load.html
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-7/igt@xe_module_load@load.html
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-9/igt@xe_module_load@load.html
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-9/igt@xe_module_load@load.html
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-9/igt@xe_module_load@load.html
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-2/igt@xe_module_load@load.html
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-2/igt@xe_module_load@load.html
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-2/igt@xe_module_load@load.html
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-5/igt@xe_module_load@load.html
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/shard-bmg-5/igt@xe_module_load@load.html
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
[Intel XE#7433]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7433
Build changes
-------------
* Linux: xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143 -> xe-pw-158017v6
IGT_8777: a50285a68dbef0fe11140adef4016a756f57b324 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-4646-69ee18cb718c8e62d92b25235881fc562e71a143: 69ee18cb718c8e62d92b25235881fc562e71a143
xe-pw-158017v6: 158017v6
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v6/index.html
[-- Attachment #2: Type: text/html, Size: 10763 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V5 1/4] drm/xe/xe3p_lpg: flush shrinker bo cachelines manually
2026-03-03 6:24 ` [PATCH V5 1/4] drm/xe/xe3p_lpg: flush shrinker bo cachelines manually Tejas Upadhyay
@ 2026-03-05 10:41 ` Thomas Hellström
0 siblings, 0 replies; 13+ messages in thread
From: Thomas Hellström @ 2026-03-05 10:41 UTC (permalink / raw)
To: Tejas Upadhyay, intel-xe; +Cc: matthew.auld, carl.zhang, jose.souza
Hi, Tejas
On Tue, 2026-03-03 at 11:54 +0530, Tejas Upadhyay wrote:
> XA, new pat_index introduced post xe3p_lpg, is memory shared between
> the
> CPU and GPU is treated differently from other GPU memory when the
> Media
> engine is power-gated.
>
> XA is *always* flushed, like at the end-of-submssion (and maybe other
> places), just that internally as an optimisation hw doesn't need to
> make
> that a full flush (which will also include XA) when Media is
> off/powergated, since it doesn't need to worry about GT caches vs
> Media
> coherency, and only CPU vs GPU coherency, so can make that flush a
> targeted XA flush, since stuff tagged with XA now means it's shared
> with
> the CPU. The main implication is that we now need to somehow flush
> non-XA
> before freeing system memory pages, otherwise dirty cachelines could
> be
> flushed after the free (like if Media suddenly turns on and does a
> full
> flush)
>
> V3(Thomas/MattA/MattR): Restrict userptr with non-xa, then no need to
> flush manually
> V2(MattA): Expand commit description
>
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> ---
> drivers/gpu/drm/xe/xe_bo.c | 3 ++-
> drivers/gpu/drm/xe/xe_device.c | 23 +++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_device.h | 1 +
> 3 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
> index d6c2cb959cdd..d2ee9701eae6 100644
> --- a/drivers/gpu/drm/xe/xe_bo.c
> +++ b/drivers/gpu/drm/xe/xe_bo.c
> @@ -689,7 +689,8 @@ static int xe_bo_trigger_rebind(struct xe_device
> *xe, struct xe_bo *bo,
>
> if (!xe_vm_in_fault_mode(vm)) {
> drm_gpuvm_bo_evict(vm_bo, true);
> - continue;
> + if (!xe_device_is_l2_flush_optimized(xe))
> + continue;
Could you please add a code comment here something along the lines of
"L2 cache may not be flushed, so ensure that is done in
xe_vm_invalidate_vma() below"
With that,
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
I also think a possible follow-up here would be to check the PAT
indices of the vmas we loop over only invalidate if they indicate non-
XA? If that makes sense, please consider as a follow-up patch.
Thanks,
Thomas
> }
>
> if (!idle) {
> diff --git a/drivers/gpu/drm/xe/xe_device.c
> b/drivers/gpu/drm/xe/xe_device.c
> index 4b68a2d55651..94c9f17da4b4 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -1097,6 +1097,29 @@ static void tdf_request_sync(struct xe_device
> *xe)
> }
> }
>
> +/**
> + * xe_device_is_l2_flush_optimized - if L2 flush is optimized by HW
> + * @xe: The device to check.
> + *
> + * Return: true if the HW device optimizing L2 flush, false
> otherwise.
> + */
> +bool xe_device_is_l2_flush_optimized(struct xe_device *xe)
> +{
> + /* XA is *always* flushed, like at the end-of-submssion (and
> maybe other
> + * places), just that internally as an optimisation hw
> doesn't need to make
> + * that a full flush (which will also include XA) when Media
> is
> + * off/powergated, since it doesn't need to worry about GT
> caches vs Media
> + * coherency, and only CPU vs GPU coherency, so can make
> that flush a
> + * targeted XA flush, since stuff tagged with XA now means
> it's shared with
> + * the CPU. The main implication is that we now need to
> somehow flush non-XA before
> + * freeing system memory pages, otherwise dirty cachelines
> could be flushed after the free
> + * (like if Media suddenly turns on and does a full flush)
> + */
> + if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe))
> + return true;
> + return false;
> +}
> +
> void xe_device_l2_flush(struct xe_device *xe)
> {
> struct xe_gt *gt;
> diff --git a/drivers/gpu/drm/xe/xe_device.h
> b/drivers/gpu/drm/xe/xe_device.h
> index 39464650533b..dfbf96e12d2e 100644
> --- a/drivers/gpu/drm/xe/xe_device.h
> +++ b/drivers/gpu/drm/xe/xe_device.h
> @@ -184,6 +184,7 @@ void xe_device_snapshot_print(struct xe_device
> *xe, struct drm_printer *p);
> u64 xe_device_canonicalize_addr(struct xe_device *xe, u64 address);
> u64 xe_device_uncanonicalize_addr(struct xe_device *xe, u64
> address);
>
> +bool xe_device_is_l2_flush_optimized(struct xe_device *xe);
> void xe_device_td_flush(struct xe_device *xe);
> void xe_device_l2_flush(struct xe_device *xe);
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V5 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization
2026-03-03 6:24 ` [PATCH V5 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization Tejas Upadhyay
2026-03-03 14:56 ` Souza, Jose
@ 2026-03-05 11:02 ` Thomas Hellström
2026-03-05 11:53 ` Upadhyay, Tejas
1 sibling, 1 reply; 13+ messages in thread
From: Thomas Hellström @ 2026-03-05 11:02 UTC (permalink / raw)
To: Tejas Upadhyay, intel-xe
Cc: matthew.auld, carl.zhang, jose.souza, Michal Mrozek
Hi, Tejas,
On Tue, 2026-03-03 at 11:54 +0530, Tejas Upadhyay wrote:
> When set, starting xe3p_lpg, the L2 flush optimization
> feature will control whether L2 is in Persistent or
> Transient mode through monitoring of media activity.
>
> To enable L2 flush optimization include new feature flag
> GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when
> media type is detected.
>
> Tighten UAPI validation to restrict userptr, svm and
> dmabuf mappings to be either 2WAY or XA+1WAY
>
> V4(MattA): Modify uapi doc and commit
> V3(MattA): check valid op and pat_index value
> V2(MattA): validate dma-buf bos and madvise pat-index
>
> Acked-by: Michal Mrozek <michal.mrozek@intel.com>
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> ---
> drivers/gpu/drm/xe/xe_guc.c | 3 +++
> drivers/gpu/drm/xe/xe_guc_fwif.h | 1 +
> drivers/gpu/drm/xe/xe_vm.c | 8 ++++++++
> drivers/gpu/drm/xe/xe_vm_madvise.c | 23 +++++++++++++++++++++++
> include/uapi/drm/xe_drm.h | 4 +++-
> 5 files changed, 38 insertions(+), 1 deletion(-)
>
Claude has some suggestions on this patch:
"
commit 77271d8c323486ebe5dc6f1264fc318a43a29084
Author: Tejas Upadhyay <tejas.upadhyay@intel.com>
drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization
This commit adds UAPI validation to restrict userptr, svm, and dmabuf
mappings on L2 flush optimized platforms (Xe3p+ non-DGFX) to use either
2WAY coherency or XA with 1WAY coherency (pat_index 19).
> diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
> index 99fa36123f58..42356d73ca65 100644
> --- a/drivers/gpu/drm/xe/xe_vm.c
> +++ b/drivers/gpu/drm/xe/xe_vm.c
[ ... ]
> @@ -3480,6 +3480,10 @@ static int vm_bind_ioctl_check_args(struct
xe_device *xe, struct xe_vm *vm,
> op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
> op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> + XE_IOCTL_DBG(xe, xe_device_is_l2_flush_optimized(xe) &&
> + (op == DRM_XE_VM_BIND_OP_MAP_USERPTR ||
> + is_cpu_addr_mirror) &&
> + (pat_index != 19 || coh_mode != XE_COH_2WAY))
||
The condition uses || but should this use && instead?
The commit message says mappings should be allowed if they use "either
2WAY or XA+1WAY". The UAPI documentation also says "the kernel expects
either 2WAY or 1WAY and XA @pat_index".
Looking at xe3p_lpg_pat_table in xe_pat.c:
[19] = XE2_PAT( 1, 0, 0, 2, 3, 2 )
The last parameter is coh_mode=2, which maps to XE_COH_1WAY based on
the XE2_PAT macro:
.coh_mode = __coh_mode ? __coh_mode : XE_COH_NONE
So pat_index 19 has coh_mode=XE_COH_1WAY, not XE_COH_2WAY.
With the current || condition, for pat_index 19:
- pat_index != 19 is false
- coh_mode != XE_COH_2WAY is true (since coh_mode is XE_COH_1WAY)
- false || true = true, validation fails
This means userptr/svm operations will always fail validation on L2
flush optimized platforms, even when using the correct pat_index 19.
Should the condition be:
(pat_index != 19 && coh_mode != XE_COH_2WAY)
This would fail only if the mapping is neither pat_index 19 (XA+1WAY)
nor using 2WAY coherency, matching the commit message intent.
The same issue appears in xe_vm_bind_ioctl_validate_bo() and
xe_vm_madvise_ioctl() at the similar validation points.
"
Thanks,
Thomas
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V5 4/4] drm/xe/xe3p: Skip TD flush
2026-03-03 6:24 ` [PATCH V5 4/4] drm/xe/xe3p: Skip TD flush Tejas Upadhyay
@ 2026-03-05 11:15 ` Thomas Hellström
0 siblings, 0 replies; 13+ messages in thread
From: Thomas Hellström @ 2026-03-05 11:15 UTC (permalink / raw)
To: Tejas Upadhyay, intel-xe; +Cc: matthew.auld, carl.zhang, jose.souza
On Tue, 2026-03-03 at 11:54 +0530, Tejas Upadhyay wrote:
> Xe3p has HW ability to do transient display flush so the xe driver
> can
> enable this HW feature by default and skip the software TD flush.
>
> Bspec: 60002
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
> drivers/gpu/drm/xe/xe_device.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_device.c
> b/drivers/gpu/drm/xe/xe_device.c
> index 94c9f17da4b4..0dca20133b94 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -1166,6 +1166,14 @@ void xe_device_td_flush(struct xe_device *xe)
> {
> struct xe_gt *root_gt;
>
> + /*
> + * From Xe3p onward the HW takes care of flush of TD entries
> also along
> + * with flushing XA entries, which will be at the usual sync
> points,
> + * like at the end of submission, so no manual flush is
> needed here.
> + */
> + if (GRAPHICS_VER(xe) >= 35)
> + return;
> +
> if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20)
> return;
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH V5 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization
2026-03-05 11:02 ` Thomas Hellström
@ 2026-03-05 11:53 ` Upadhyay, Tejas
0 siblings, 0 replies; 13+ messages in thread
From: Upadhyay, Tejas @ 2026-03-05 11:53 UTC (permalink / raw)
To: Thomas Hellström, intel-xe@lists.freedesktop.org
Cc: Auld, Matthew, Zhang, Carl, Souza, Jose, Mrozek, Michal
> -----Original Message-----
> From: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Sent: 05 March 2026 16:33
> To: Upadhyay, Tejas <tejas.upadhyay@intel.com>; intel-
> xe@lists.freedesktop.org
> Cc: Auld, Matthew <matthew.auld@intel.com>; Zhang, Carl
> <carl.zhang@intel.com>; Souza, Jose <jose.souza@intel.com>; Mrozek, Michal
> <michal.mrozek@intel.com>
> Subject: Re: [PATCH V5 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush
> optimization
>
> Hi, Tejas,
>
> On Tue, 2026-03-03 at 11:54 +0530, Tejas Upadhyay wrote:
> > When set, starting xe3p_lpg, the L2 flush optimization feature will
> > control whether L2 is in Persistent or Transient mode through
> > monitoring of media activity.
> >
> > To enable L2 flush optimization include new feature flag
> > GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when media type is
> > detected.
> >
> > Tighten UAPI validation to restrict userptr, svm and dmabuf mappings
> > to be either 2WAY or XA+1WAY
> >
> > V4(MattA): Modify uapi doc and commit
> > V3(MattA): check valid op and pat_index value
> > V2(MattA): validate dma-buf bos and madvise pat-index
> >
> > Acked-by: Michal Mrozek <michal.mrozek@intel.com>
> > Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_guc.c | 3 +++
> > drivers/gpu/drm/xe/xe_guc_fwif.h | 1 +
> > drivers/gpu/drm/xe/xe_vm.c | 8 ++++++++
> > drivers/gpu/drm/xe/xe_vm_madvise.c | 23 +++++++++++++++++++++++
> > include/uapi/drm/xe_drm.h | 4 +++-
> > 5 files changed, 38 insertions(+), 1 deletion(-)
> >
>
> Claude has some suggestions on this patch:
>
> "
> commit 77271d8c323486ebe5dc6f1264fc318a43a29084
> Author: Tejas Upadhyay <tejas.upadhyay@intel.com>
>
> drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization
>
> This commit adds UAPI validation to restrict userptr, svm, and dmabuf
> mappings on L2 flush optimized platforms (Xe3p+ non-DGFX) to use either
> 2WAY coherency or XA with 1WAY coherency (pat_index 19).
>
> > diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
> > index 99fa36123f58..42356d73ca65 100644
> > --- a/drivers/gpu/drm/xe/xe_vm.c
> > +++ b/drivers/gpu/drm/xe/xe_vm.c
>
> [ ... ]
>
> > @@ -3480,6 +3480,10 @@ static int vm_bind_ioctl_check_args(struct
> xe_device *xe, struct xe_vm *vm,
> > op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> > XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
> > op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> > + XE_IOCTL_DBG(xe, xe_device_is_l2_flush_optimized(xe) &&
> > + (op == DRM_XE_VM_BIND_OP_MAP_USERPTR ||
> > + is_cpu_addr_mirror) &&
> > + (pat_index != 19 || coh_mode != XE_COH_2WAY))
> ||
>
> The condition uses || but should this use && instead?
>
> The commit message says mappings should be allowed if they use "either
> 2WAY or XA+1WAY". The UAPI documentation also says "the kernel expects
> either 2WAY or 1WAY and XA @pat_index".
>
> Looking at xe3p_lpg_pat_table in xe_pat.c:
>
> [19] = XE2_PAT( 1, 0, 0, 2, 3, 2 )
>
> The last parameter is coh_mode=2, which maps to XE_COH_1WAY based on
> the XE2_PAT macro:
>
> .coh_mode = __coh_mode ? __coh_mode : XE_COH_NONE
>
> So pat_index 19 has coh_mode=XE_COH_1WAY, not XE_COH_2WAY.
>
> With the current || condition, for pat_index 19:
> - pat_index != 19 is false
> - coh_mode != XE_COH_2WAY is true (since coh_mode is XE_COH_1WAY)
> - false || true = true, validation fails
>
> This means userptr/svm operations will always fail validation on L2 flush
> optimized platforms, even when using the correct pat_index 19.
>
> Should the condition be:
>
> (pat_index != 19 && coh_mode != XE_COH_2WAY)
Right. Its miss.
>
> This would fail only if the mapping is neither pat_index 19 (XA+1WAY) nor
> using 2WAY coherency, matching the commit message intent.
>
> The same issue appears in xe_vm_bind_ioctl_validate_bo() and
> xe_vm_madvise_ioctl() at the similar validation points.
>
> "
>
> Thanks,
> Thomas
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2026-03-05 11:53 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-03-03 6:24 [PATCH V5 0/4] drm/xe/xe3p_lpg: L2 flush optimization Tejas Upadhyay
2026-03-03 6:24 ` [PATCH V5 1/4] drm/xe/xe3p_lpg: flush shrinker bo cachelines manually Tejas Upadhyay
2026-03-05 10:41 ` Thomas Hellström
2026-03-03 6:24 ` [PATCH V5 2/4] drm/xe/pat: define coh_mode 2way Tejas Upadhyay
2026-03-03 6:24 ` [PATCH V5 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization Tejas Upadhyay
2026-03-03 14:56 ` Souza, Jose
2026-03-05 11:02 ` Thomas Hellström
2026-03-05 11:53 ` Upadhyay, Tejas
2026-03-03 6:24 ` [PATCH V5 4/4] drm/xe/xe3p: Skip TD flush Tejas Upadhyay
2026-03-05 11:15 ` Thomas Hellström
2026-03-03 7:27 ` ✓ CI.KUnit: success for drm/xe/xe3p_lpg: L2 flush optimization (rev6) Patchwork
2026-03-03 8:22 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-03 17:06 ` ✓ Xe.CI.FULL: " Patchwork
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