* [PATCH] drm/i915/power_well: Enable workaround for DSS clock gating issue (22021048059)
@ 2026-01-28 7:48 Mika Kahola
2026-01-28 10:36 ` Jani Nikula
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Mika Kahola @ 2026-01-28 7:48 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Mika Kahola
Prevent display corruption observed after restart, hotplug, or unplug
operations on Meteor Lake and newer platforms. The issue is caused by
DSS clock gating affecting DSC logic when pipe power wells are disabled.
Apply WA 22021048059 by disabling DSS clock gating for the affected pipes
before turning off their power wells. This avoids DSC corruption on
external displays.
WA: 22021048059
BSpec: 690991, 666241
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
.../i915/display/intel_display_power_well.c | 78 ++++++++++++++++++-
.../gpu/drm/i915/display/intel_display_regs.h | 7 ++
.../gpu/drm/i915/display/intel_display_wa.c | 2 +
.../gpu/drm/i915/display/intel_display_wa.h | 1 +
4 files changed, 86 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 6f9bc6f9615e..1ef450f26879 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -14,10 +14,13 @@
#include "intel_crt.h"
#include "intel_de.h"
#include "intel_display_irq.h"
+#include "intel_display_limits.h"
#include "intel_display_power_well.h"
#include "intel_display_regs.h"
#include "intel_display_rpm.h"
#include "intel_display_types.h"
+#include "intel_display_utils.h"
+#include "intel_display_wa.h"
#include "intel_dkl_phy.h"
#include "intel_dkl_phy_regs.h"
#include "intel_dmc.h"
@@ -194,6 +197,69 @@ int intel_power_well_refcount(struct i915_power_well *power_well)
return power_well->count;
}
+static void clock_gating_dss_enable_disable(struct intel_display *display,
+ u8 irq_pipe_mask,
+ bool disable)
+{
+ struct drm_printer p;
+ enum pipe pipe;
+
+ switch (irq_pipe_mask) {
+ case BIT(PIPE_A):
+ pipe = PIPE_A;
+
+ if (disable)
+ intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
+ 0, DSS_PIPE_A_GATING_DISABLED);
+ else
+ intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
+ DSS_PIPE_A_GATING_DISABLED, 0);
+ break;
+ case BIT(PIPE_B):
+ pipe = PIPE_B;
+
+ if (disable)
+ intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
+ 0, DSS_PIPE_B_GATING_DISABLED);
+ else
+ intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
+ DSS_PIPE_B_GATING_DISABLED, 0);
+ break;
+ case BIT(PIPE_C):
+ pipe = PIPE_C;
+
+ if (disable)
+ intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
+ 0, DSS_PIPE_C_GATING_DISABLED);
+ else
+ intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
+ DSS_PIPE_C_GATING_DISABLED, 0);
+ break;
+ case BIT(PIPE_D):
+ pipe = PIPE_D;
+
+ if (disable)
+ intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
+ 0, DSS_PIPE_D_GATING_DISABLED);
+ else
+ intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
+ DSS_PIPE_D_GATING_DISABLED, 0);
+ break;
+ default:
+ MISSING_CASE(irq_pipe_mask);
+ break;
+ }
+
+ if (!drm_debug_enabled(DRM_UT_KMS))
+ return;
+
+ p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
+
+ drm_printf(&p, "dss clock gating %sd on pipe %c (0x%.8x)\n",
+ str_enable_disable(!disable), pipe_name(pipe),
+ intel_de_read(display, CLKGATE_DIS_DSSDSC));
+}
+
/*
* Starting with Haswell, we have a "Power Down Well" that can be turned off
* when not needed anymore. We have 4 registers that can request the power well
@@ -203,15 +269,23 @@ int intel_power_well_refcount(struct i915_power_well *power_well)
static void hsw_power_well_post_enable(struct intel_display *display,
u8 irq_pipe_mask)
{
- if (irq_pipe_mask)
+ if (irq_pipe_mask) {
gen8_irq_power_well_post_enable(display, irq_pipe_mask);
+
+ if (intel_display_wa(display, 22021048059))
+ clock_gating_dss_enable_disable(display, irq_pipe_mask, false);
+ }
}
static void hsw_power_well_pre_disable(struct intel_display *display,
u8 irq_pipe_mask)
{
- if (irq_pipe_mask)
+ if (irq_pipe_mask) {
+ if (intel_display_wa(display, 22021048059))
+ clock_gating_dss_enable_disable(display, irq_pipe_mask, true);
+
gen8_irq_power_well_pre_disable(display, irq_pipe_mask);
+ }
}
#define ICL_AUX_PW_TO_PHY(pw_idx) \
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9e0d853f4b61..9740f32ced24 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2211,6 +2211,13 @@
#define HSW_PWR_WELL_FORCE_ON (1 << 19)
#define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
+/* clock gating DSS DSC disable register */
+#define CLKGATE_DIS_DSSDSC _MMIO(0x46548)
+#define DSS_PIPE_D_GATING_DISABLED REG_BIT(31)
+#define DSS_PIPE_C_GATING_DISABLED REG_BIT(29)
+#define DSS_PIPE_B_GATING_DISABLED REG_BIT(27)
+#define DSS_PIPE_A_GATING_DISABLED REG_BIT(25)
+
/* SKL Fuse Status */
enum skl_power_gate {
SKL_PG0,
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index 86a6cc45b6ab..f8e14aa34dae 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -84,6 +84,8 @@ bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa,
return intel_display_needs_wa_16025573575(display);
case INTEL_DISPLAY_WA_22014263786:
return IS_DISPLAY_VERx100(display, 1100, 1400);
+ case INTEL_DISPLAY_WA_22021048059:
+ return DISPLAY_VER(display) >= 14;
default:
drm_WARN(display->drm, 1, "Missing Wa number: %s\n", name);
break;
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h
index 40f989f19df1..767420d5f406 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.h
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
@@ -34,6 +34,7 @@ enum intel_display_wa {
INTEL_DISPLAY_WA_16023588340,
INTEL_DISPLAY_WA_16025573575,
INTEL_DISPLAY_WA_22014263786,
+ INTEL_DISPLAY_WA_22021048059,
};
bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name);
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/i915/power_well: Enable workaround for DSS clock gating issue (22021048059)
2026-01-28 7:48 [PATCH] drm/i915/power_well: Enable workaround for DSS clock gating issue (22021048059) Mika Kahola
@ 2026-01-28 10:36 ` Jani Nikula
2026-01-30 10:02 ` Kahola, Mika
2026-01-28 15:57 ` ✓ CI.KUnit: success for " Patchwork
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Jani Nikula @ 2026-01-28 10:36 UTC (permalink / raw)
To: Mika Kahola, intel-gfx, intel-xe; +Cc: Mika Kahola
On Wed, 28 Jan 2026, Mika Kahola <mika.kahola@intel.com> wrote:
> Prevent display corruption observed after restart, hotplug, or unplug
> operations on Meteor Lake and newer platforms. The issue is caused by
> DSS clock gating affecting DSC logic when pipe power wells are disabled.
>
> Apply WA 22021048059 by disabling DSS clock gating for the affected pipes
> before turning off their power wells. This avoids DSC corruption on
> external displays.
>
> WA: 22021048059
> BSpec: 690991, 666241
>
Superfluous blank line. The git commit trailers belong together.
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> .../i915/display/intel_display_power_well.c | 78 ++++++++++++++++++-
> .../gpu/drm/i915/display/intel_display_regs.h | 7 ++
> .../gpu/drm/i915/display/intel_display_wa.c | 2 +
> .../gpu/drm/i915/display/intel_display_wa.h | 1 +
> 4 files changed, 86 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 6f9bc6f9615e..1ef450f26879 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -14,10 +14,13 @@
> #include "intel_crt.h"
> #include "intel_de.h"
> #include "intel_display_irq.h"
> +#include "intel_display_limits.h"
> #include "intel_display_power_well.h"
> #include "intel_display_regs.h"
> #include "intel_display_rpm.h"
> #include "intel_display_types.h"
> +#include "intel_display_utils.h"
> +#include "intel_display_wa.h"
> #include "intel_dkl_phy.h"
> #include "intel_dkl_phy_regs.h"
> #include "intel_dmc.h"
> @@ -194,6 +197,69 @@ int intel_power_well_refcount(struct i915_power_well *power_well)
> return power_well->count;
> }
>
> +static void clock_gating_dss_enable_disable(struct intel_display *display,
> + u8 irq_pipe_mask,
> + bool disable)
> +{
> + struct drm_printer p;
> + enum pipe pipe;
> +
> + switch (irq_pipe_mask) {
> + case BIT(PIPE_A):
> + pipe = PIPE_A;
> +
> + if (disable)
> + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> + 0, DSS_PIPE_A_GATING_DISABLED);
> + else
> + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> + DSS_PIPE_A_GATING_DISABLED, 0);
> + break;
> + case BIT(PIPE_B):
> + pipe = PIPE_B;
> +
> + if (disable)
> + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> + 0, DSS_PIPE_B_GATING_DISABLED);
> + else
> + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> + DSS_PIPE_B_GATING_DISABLED, 0);
> + break;
> + case BIT(PIPE_C):
> + pipe = PIPE_C;
> +
> + if (disable)
> + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> + 0, DSS_PIPE_C_GATING_DISABLED);
> + else
> + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> + DSS_PIPE_C_GATING_DISABLED, 0);
> + break;
> + case BIT(PIPE_D):
> + pipe = PIPE_D;
> +
> + if (disable)
> + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> + 0, DSS_PIPE_D_GATING_DISABLED);
> + else
> + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> + DSS_PIPE_D_GATING_DISABLED, 0);
> + break;
> + default:
> + MISSING_CASE(irq_pipe_mask);
> + break;
> + }
irq_pipe_mask implies it can have multiple pipes set. That will lead to
a warning here. Does this need to use for_each_pipe_masked() instead?
The whole thing is awfully verbose as well. Perhaps figure out the bits
to set/unset based on the pipes, and have just one intel_de_rmw()
statement?
> +
> + if (!drm_debug_enabled(DRM_UT_KMS))
> + return;
This is redundant.
> +
> + p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
> +
> + drm_printf(&p, "dss clock gating %sd on pipe %c (0x%.8x)\n",
> + str_enable_disable(!disable), pipe_name(pipe),
> + intel_de_read(display, CLKGATE_DIS_DSSDSC));
Using a printer is overkill for one line. This should just be a
drm_dbg_kms().
And this also assumes just one pipe.
BR,
Jani.
> +}
> +
> /*
> * Starting with Haswell, we have a "Power Down Well" that can be turned off
> * when not needed anymore. We have 4 registers that can request the power well
> @@ -203,15 +269,23 @@ int intel_power_well_refcount(struct i915_power_well *power_well)
> static void hsw_power_well_post_enable(struct intel_display *display,
> u8 irq_pipe_mask)
> {
> - if (irq_pipe_mask)
> + if (irq_pipe_mask) {
> gen8_irq_power_well_post_enable(display, irq_pipe_mask);
> +
> + if (intel_display_wa(display, 22021048059))
> + clock_gating_dss_enable_disable(display, irq_pipe_mask, false);
> + }
> }
>
> static void hsw_power_well_pre_disable(struct intel_display *display,
> u8 irq_pipe_mask)
> {
> - if (irq_pipe_mask)
> + if (irq_pipe_mask) {
> + if (intel_display_wa(display, 22021048059))
> + clock_gating_dss_enable_disable(display, irq_pipe_mask, true);
> +
> gen8_irq_power_well_pre_disable(display, irq_pipe_mask);
> + }
> }
>
> #define ICL_AUX_PW_TO_PHY(pw_idx) \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 9e0d853f4b61..9740f32ced24 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -2211,6 +2211,13 @@
> #define HSW_PWR_WELL_FORCE_ON (1 << 19)
> #define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
>
> +/* clock gating DSS DSC disable register */
> +#define CLKGATE_DIS_DSSDSC _MMIO(0x46548)
> +#define DSS_PIPE_D_GATING_DISABLED REG_BIT(31)
> +#define DSS_PIPE_C_GATING_DISABLED REG_BIT(29)
> +#define DSS_PIPE_B_GATING_DISABLED REG_BIT(27)
> +#define DSS_PIPE_A_GATING_DISABLED REG_BIT(25)
> +
> /* SKL Fuse Status */
> enum skl_power_gate {
> SKL_PG0,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
> index 86a6cc45b6ab..f8e14aa34dae 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_wa.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
> @@ -84,6 +84,8 @@ bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa,
> return intel_display_needs_wa_16025573575(display);
> case INTEL_DISPLAY_WA_22014263786:
> return IS_DISPLAY_VERx100(display, 1100, 1400);
> + case INTEL_DISPLAY_WA_22021048059:
> + return DISPLAY_VER(display) >= 14;
> default:
> drm_WARN(display->drm, 1, "Missing Wa number: %s\n", name);
> break;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h
> index 40f989f19df1..767420d5f406 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_wa.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
> @@ -34,6 +34,7 @@ enum intel_display_wa {
> INTEL_DISPLAY_WA_16023588340,
> INTEL_DISPLAY_WA_16025573575,
> INTEL_DISPLAY_WA_22014263786,
> + INTEL_DISPLAY_WA_22021048059,
> };
>
> bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name);
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✓ CI.KUnit: success for drm/i915/power_well: Enable workaround for DSS clock gating issue (22021048059)
2026-01-28 7:48 [PATCH] drm/i915/power_well: Enable workaround for DSS clock gating issue (22021048059) Mika Kahola
2026-01-28 10:36 ` Jani Nikula
@ 2026-01-28 15:57 ` Patchwork
2026-01-28 16:32 ` ✓ Xe.CI.BAT: " Patchwork
2026-01-29 3:11 ` [PATCH] " Kandpal, Suraj
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2026-01-28 15:57 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-xe
== Series Details ==
Series: drm/i915/power_well: Enable workaround for DSS clock gating issue (22021048059)
URL : https://patchwork.freedesktop.org/series/160740/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[15:56:33] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:56:37] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:57:09] Starting KUnit Kernel (1/1)...
[15:57:09] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:57:09] ================== guc_buf (11 subtests) ===================
[15:57:09] [PASSED] test_smallest
[15:57:09] [PASSED] test_largest
[15:57:09] [PASSED] test_granular
[15:57:09] [PASSED] test_unique
[15:57:09] [PASSED] test_overlap
[15:57:09] [PASSED] test_reusable
[15:57:09] [PASSED] test_too_big
[15:57:09] [PASSED] test_flush
[15:57:09] [PASSED] test_lookup
[15:57:09] [PASSED] test_data
[15:57:09] [PASSED] test_class
[15:57:09] ===================== [PASSED] guc_buf =====================
[15:57:09] =================== guc_dbm (7 subtests) ===================
[15:57:09] [PASSED] test_empty
[15:57:09] [PASSED] test_default
[15:57:09] ======================== test_size ========================
[15:57:09] [PASSED] 4
[15:57:09] [PASSED] 8
[15:57:09] [PASSED] 32
[15:57:09] [PASSED] 256
[15:57:09] ==================== [PASSED] test_size ====================
[15:57:09] ======================= test_reuse ========================
[15:57:09] [PASSED] 4
[15:57:09] [PASSED] 8
[15:57:09] [PASSED] 32
[15:57:09] [PASSED] 256
[15:57:09] =================== [PASSED] test_reuse ====================
[15:57:09] =================== test_range_overlap ====================
[15:57:09] [PASSED] 4
[15:57:09] [PASSED] 8
[15:57:09] [PASSED] 32
[15:57:09] [PASSED] 256
[15:57:09] =============== [PASSED] test_range_overlap ================
[15:57:09] =================== test_range_compact ====================
[15:57:09] [PASSED] 4
[15:57:09] [PASSED] 8
[15:57:09] [PASSED] 32
[15:57:09] [PASSED] 256
[15:57:09] =============== [PASSED] test_range_compact ================
[15:57:09] ==================== test_range_spare =====================
[15:57:09] [PASSED] 4
[15:57:09] [PASSED] 8
[15:57:09] [PASSED] 32
[15:57:09] [PASSED] 256
[15:57:09] ================ [PASSED] test_range_spare =================
[15:57:09] ===================== [PASSED] guc_dbm =====================
[15:57:09] =================== guc_idm (6 subtests) ===================
[15:57:09] [PASSED] bad_init
[15:57:09] [PASSED] no_init
[15:57:09] [PASSED] init_fini
[15:57:09] [PASSED] check_used
[15:57:09] [PASSED] check_quota
[15:57:09] [PASSED] check_all
[15:57:09] ===================== [PASSED] guc_idm =====================
[15:57:09] ================== no_relay (3 subtests) ===================
[15:57:09] [PASSED] xe_drops_guc2pf_if_not_ready
[15:57:09] [PASSED] xe_drops_guc2vf_if_not_ready
[15:57:09] [PASSED] xe_rejects_send_if_not_ready
[15:57:09] ==================== [PASSED] no_relay =====================
[15:57:09] ================== pf_relay (14 subtests) ==================
[15:57:09] [PASSED] pf_rejects_guc2pf_too_short
[15:57:09] [PASSED] pf_rejects_guc2pf_too_long
[15:57:09] [PASSED] pf_rejects_guc2pf_no_payload
[15:57:09] [PASSED] pf_fails_no_payload
[15:57:09] [PASSED] pf_fails_bad_origin
[15:57:09] [PASSED] pf_fails_bad_type
[15:57:09] [PASSED] pf_txn_reports_error
[15:57:09] [PASSED] pf_txn_sends_pf2guc
[15:57:09] [PASSED] pf_sends_pf2guc
[15:57:09] [SKIPPED] pf_loopback_nop
[15:57:09] [SKIPPED] pf_loopback_echo
[15:57:09] [SKIPPED] pf_loopback_fail
[15:57:09] [SKIPPED] pf_loopback_busy
[15:57:09] [SKIPPED] pf_loopback_retry
[15:57:09] ==================== [PASSED] pf_relay =====================
[15:57:09] ================== vf_relay (3 subtests) ===================
[15:57:09] [PASSED] vf_rejects_guc2vf_too_short
[15:57:09] [PASSED] vf_rejects_guc2vf_too_long
[15:57:09] [PASSED] vf_rejects_guc2vf_no_payload
[15:57:09] ==================== [PASSED] vf_relay =====================
[15:57:09] ================ pf_gt_config (6 subtests) =================
[15:57:09] [PASSED] fair_contexts_1vf
[15:57:09] [PASSED] fair_doorbells_1vf
[15:57:09] [PASSED] fair_ggtt_1vf
[15:57:09] ====================== fair_contexts ======================
[15:57:09] [PASSED] 1 VF
[15:57:09] [PASSED] 2 VFs
[15:57:09] [PASSED] 3 VFs
[15:57:09] [PASSED] 4 VFs
[15:57:09] [PASSED] 5 VFs
[15:57:09] [PASSED] 6 VFs
[15:57:09] [PASSED] 7 VFs
[15:57:09] [PASSED] 8 VFs
[15:57:09] [PASSED] 9 VFs
[15:57:09] [PASSED] 10 VFs
[15:57:09] [PASSED] 11 VFs
[15:57:09] [PASSED] 12 VFs
[15:57:09] [PASSED] 13 VFs
[15:57:09] [PASSED] 14 VFs
[15:57:09] [PASSED] 15 VFs
[15:57:09] [PASSED] 16 VFs
[15:57:09] [PASSED] 17 VFs
[15:57:09] [PASSED] 18 VFs
[15:57:09] [PASSED] 19 VFs
[15:57:09] [PASSED] 20 VFs
[15:57:09] [PASSED] 21 VFs
[15:57:09] [PASSED] 22 VFs
[15:57:09] [PASSED] 23 VFs
[15:57:09] [PASSED] 24 VFs
[15:57:09] [PASSED] 25 VFs
[15:57:09] [PASSED] 26 VFs
[15:57:09] [PASSED] 27 VFs
[15:57:09] [PASSED] 28 VFs
[15:57:09] [PASSED] 29 VFs
[15:57:09] [PASSED] 30 VFs
[15:57:09] [PASSED] 31 VFs
[15:57:09] [PASSED] 32 VFs
[15:57:09] [PASSED] 33 VFs
[15:57:09] [PASSED] 34 VFs
[15:57:09] [PASSED] 35 VFs
[15:57:09] [PASSED] 36 VFs
[15:57:09] [PASSED] 37 VFs
[15:57:09] [PASSED] 38 VFs
[15:57:09] [PASSED] 39 VFs
[15:57:09] [PASSED] 40 VFs
[15:57:09] [PASSED] 41 VFs
[15:57:09] [PASSED] 42 VFs
[15:57:09] [PASSED] 43 VFs
[15:57:09] [PASSED] 44 VFs
[15:57:09] [PASSED] 45 VFs
[15:57:09] [PASSED] 46 VFs
[15:57:09] [PASSED] 47 VFs
[15:57:09] [PASSED] 48 VFs
[15:57:09] [PASSED] 49 VFs
[15:57:09] [PASSED] 50 VFs
[15:57:09] [PASSED] 51 VFs
[15:57:09] [PASSED] 52 VFs
[15:57:09] [PASSED] 53 VFs
[15:57:09] [PASSED] 54 VFs
[15:57:09] [PASSED] 55 VFs
[15:57:09] [PASSED] 56 VFs
[15:57:09] [PASSED] 57 VFs
[15:57:09] [PASSED] 58 VFs
[15:57:09] [PASSED] 59 VFs
[15:57:09] [PASSED] 60 VFs
[15:57:09] [PASSED] 61 VFs
[15:57:09] [PASSED] 62 VFs
[15:57:09] [PASSED] 63 VFs
[15:57:09] ================== [PASSED] fair_contexts ==================
[15:57:09] ===================== fair_doorbells ======================
[15:57:09] [PASSED] 1 VF
[15:57:09] [PASSED] 2 VFs
[15:57:09] [PASSED] 3 VFs
[15:57:09] [PASSED] 4 VFs
[15:57:09] [PASSED] 5 VFs
[15:57:09] [PASSED] 6 VFs
[15:57:09] [PASSED] 7 VFs
[15:57:09] [PASSED] 8 VFs
[15:57:09] [PASSED] 9 VFs
[15:57:09] [PASSED] 10 VFs
[15:57:09] [PASSED] 11 VFs
[15:57:09] [PASSED] 12 VFs
[15:57:09] [PASSED] 13 VFs
[15:57:09] [PASSED] 14 VFs
[15:57:09] [PASSED] 15 VFs
[15:57:09] [PASSED] 16 VFs
[15:57:09] [PASSED] 17 VFs
[15:57:09] [PASSED] 18 VFs
[15:57:09] [PASSED] 19 VFs
[15:57:09] [PASSED] 20 VFs
[15:57:09] [PASSED] 21 VFs
[15:57:09] [PASSED] 22 VFs
[15:57:09] [PASSED] 23 VFs
[15:57:09] [PASSED] 24 VFs
[15:57:09] [PASSED] 25 VFs
[15:57:09] [PASSED] 26 VFs
[15:57:09] [PASSED] 27 VFs
[15:57:09] [PASSED] 28 VFs
[15:57:09] [PASSED] 29 VFs
[15:57:09] [PASSED] 30 VFs
[15:57:09] [PASSED] 31 VFs
[15:57:09] [PASSED] 32 VFs
[15:57:09] [PASSED] 33 VFs
[15:57:09] [PASSED] 34 VFs
[15:57:09] [PASSED] 35 VFs
[15:57:09] [PASSED] 36 VFs
[15:57:09] [PASSED] 37 VFs
[15:57:09] [PASSED] 38 VFs
[15:57:09] [PASSED] 39 VFs
[15:57:09] [PASSED] 40 VFs
[15:57:09] [PASSED] 41 VFs
[15:57:09] [PASSED] 42 VFs
[15:57:09] [PASSED] 43 VFs
[15:57:09] [PASSED] 44 VFs
[15:57:09] [PASSED] 45 VFs
[15:57:09] [PASSED] 46 VFs
[15:57:09] [PASSED] 47 VFs
[15:57:09] [PASSED] 48 VFs
[15:57:09] [PASSED] 49 VFs
[15:57:09] [PASSED] 50 VFs
[15:57:09] [PASSED] 51 VFs
[15:57:09] [PASSED] 52 VFs
[15:57:09] [PASSED] 53 VFs
[15:57:09] [PASSED] 54 VFs
[15:57:09] [PASSED] 55 VFs
[15:57:09] [PASSED] 56 VFs
[15:57:09] [PASSED] 57 VFs
[15:57:09] [PASSED] 58 VFs
[15:57:09] [PASSED] 59 VFs
[15:57:09] [PASSED] 60 VFs
[15:57:09] [PASSED] 61 VFs
[15:57:09] [PASSED] 62 VFs
[15:57:09] [PASSED] 63 VFs
[15:57:09] ================= [PASSED] fair_doorbells ==================
[15:57:09] ======================== fair_ggtt ========================
[15:57:09] [PASSED] 1 VF
[15:57:09] [PASSED] 2 VFs
[15:57:09] [PASSED] 3 VFs
[15:57:09] [PASSED] 4 VFs
[15:57:09] [PASSED] 5 VFs
[15:57:09] [PASSED] 6 VFs
[15:57:09] [PASSED] 7 VFs
[15:57:09] [PASSED] 8 VFs
[15:57:09] [PASSED] 9 VFs
[15:57:09] [PASSED] 10 VFs
[15:57:09] [PASSED] 11 VFs
[15:57:09] [PASSED] 12 VFs
[15:57:09] [PASSED] 13 VFs
[15:57:09] [PASSED] 14 VFs
[15:57:09] [PASSED] 15 VFs
[15:57:09] [PASSED] 16 VFs
[15:57:09] [PASSED] 17 VFs
[15:57:09] [PASSED] 18 VFs
[15:57:09] [PASSED] 19 VFs
[15:57:09] [PASSED] 20 VFs
[15:57:09] [PASSED] 21 VFs
[15:57:09] [PASSED] 22 VFs
[15:57:09] [PASSED] 23 VFs
[15:57:09] [PASSED] 24 VFs
[15:57:09] [PASSED] 25 VFs
[15:57:09] [PASSED] 26 VFs
[15:57:09] [PASSED] 27 VFs
[15:57:09] [PASSED] 28 VFs
[15:57:09] [PASSED] 29 VFs
[15:57:09] [PASSED] 30 VFs
[15:57:09] [PASSED] 31 VFs
[15:57:09] [PASSED] 32 VFs
[15:57:09] [PASSED] 33 VFs
[15:57:09] [PASSED] 34 VFs
[15:57:09] [PASSED] 35 VFs
[15:57:09] [PASSED] 36 VFs
[15:57:09] [PASSED] 37 VFs
[15:57:09] [PASSED] 38 VFs
[15:57:09] [PASSED] 39 VFs
[15:57:09] [PASSED] 40 VFs
[15:57:09] [PASSED] 41 VFs
[15:57:09] [PASSED] 42 VFs
[15:57:09] [PASSED] 43 VFs
[15:57:09] [PASSED] 44 VFs
[15:57:09] [PASSED] 45 VFs
[15:57:09] [PASSED] 46 VFs
[15:57:09] [PASSED] 47 VFs
[15:57:09] [PASSED] 48 VFs
[15:57:09] [PASSED] 49 VFs
[15:57:09] [PASSED] 50 VFs
[15:57:09] [PASSED] 51 VFs
[15:57:09] [PASSED] 52 VFs
[15:57:09] [PASSED] 53 VFs
[15:57:09] [PASSED] 54 VFs
[15:57:09] [PASSED] 55 VFs
[15:57:09] [PASSED] 56 VFs
[15:57:09] [PASSED] 57 VFs
[15:57:09] [PASSED] 58 VFs
[15:57:09] [PASSED] 59 VFs
[15:57:09] [PASSED] 60 VFs
[15:57:09] [PASSED] 61 VFs
[15:57:09] [PASSED] 62 VFs
[15:57:09] [PASSED] 63 VFs
[15:57:09] ==================== [PASSED] fair_ggtt ====================
[15:57:09] ================== [PASSED] pf_gt_config ===================
[15:57:09] ===================== lmtt (1 subtest) =====================
[15:57:09] ======================== test_ops =========================
[15:57:09] [PASSED] 2-level
[15:57:09] [PASSED] multi-level
[15:57:09] ==================== [PASSED] test_ops =====================
[15:57:09] ====================== [PASSED] lmtt =======================
[15:57:09] ================= pf_service (11 subtests) =================
[15:57:09] [PASSED] pf_negotiate_any
[15:57:09] [PASSED] pf_negotiate_base_match
[15:57:09] [PASSED] pf_negotiate_base_newer
[15:57:09] [PASSED] pf_negotiate_base_next
[15:57:09] [SKIPPED] pf_negotiate_base_older
[15:57:09] [PASSED] pf_negotiate_base_prev
[15:57:09] [PASSED] pf_negotiate_latest_match
[15:57:09] [PASSED] pf_negotiate_latest_newer
[15:57:09] [PASSED] pf_negotiate_latest_next
[15:57:09] [SKIPPED] pf_negotiate_latest_older
[15:57:09] [SKIPPED] pf_negotiate_latest_prev
[15:57:09] =================== [PASSED] pf_service ====================
[15:57:09] ================= xe_guc_g2g (2 subtests) ==================
[15:57:09] ============== xe_live_guc_g2g_kunit_default ==============
[15:57:09] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[15:57:09] ============== xe_live_guc_g2g_kunit_allmem ===============
[15:57:09] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[15:57:09] =================== [SKIPPED] xe_guc_g2g ===================
[15:57:09] =================== xe_mocs (2 subtests) ===================
[15:57:09] ================ xe_live_mocs_kernel_kunit ================
[15:57:09] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[15:57:09] ================ xe_live_mocs_reset_kunit =================
[15:57:09] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[15:57:09] ==================== [SKIPPED] xe_mocs =====================
[15:57:09] ================= xe_migrate (2 subtests) ==================
[15:57:09] ================= xe_migrate_sanity_kunit =================
[15:57:09] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[15:57:09] ================== xe_validate_ccs_kunit ==================
[15:57:09] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[15:57:09] =================== [SKIPPED] xe_migrate ===================
[15:57:09] ================== xe_dma_buf (1 subtest) ==================
[15:57:09] ==================== xe_dma_buf_kunit =====================
[15:57:09] ================ [SKIPPED] xe_dma_buf_kunit ================
[15:57:09] =================== [SKIPPED] xe_dma_buf ===================
[15:57:09] ================= xe_bo_shrink (1 subtest) =================
[15:57:09] =================== xe_bo_shrink_kunit ====================
[15:57:09] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[15:57:09] ================== [SKIPPED] xe_bo_shrink ==================
[15:57:09] ==================== xe_bo (2 subtests) ====================
[15:57:09] ================== xe_ccs_migrate_kunit ===================
[15:57:09] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[15:57:09] ==================== xe_bo_evict_kunit ====================
[15:57:09] =============== [SKIPPED] xe_bo_evict_kunit ================
[15:57:09] ===================== [SKIPPED] xe_bo ======================
[15:57:09] ==================== args (13 subtests) ====================
[15:57:09] [PASSED] count_args_test
[15:57:09] [PASSED] call_args_example
[15:57:09] [PASSED] call_args_test
[15:57:09] [PASSED] drop_first_arg_example
[15:57:09] [PASSED] drop_first_arg_test
[15:57:09] [PASSED] first_arg_example
[15:57:09] [PASSED] first_arg_test
[15:57:09] [PASSED] last_arg_example
[15:57:09] [PASSED] last_arg_test
[15:57:09] [PASSED] pick_arg_example
[15:57:09] [PASSED] if_args_example
[15:57:09] [PASSED] if_args_test
[15:57:09] [PASSED] sep_comma_example
[15:57:09] ====================== [PASSED] args =======================
[15:57:09] =================== xe_pci (3 subtests) ====================
[15:57:09] ==================== check_graphics_ip ====================
[15:57:09] [PASSED] 12.00 Xe_LP
[15:57:09] [PASSED] 12.10 Xe_LP+
[15:57:09] [PASSED] 12.55 Xe_HPG
[15:57:09] [PASSED] 12.60 Xe_HPC
[15:57:09] [PASSED] 12.70 Xe_LPG
[15:57:09] [PASSED] 12.71 Xe_LPG
[15:57:09] [PASSED] 12.74 Xe_LPG+
[15:57:09] [PASSED] 20.01 Xe2_HPG
[15:57:09] [PASSED] 20.02 Xe2_HPG
[15:57:09] [PASSED] 20.04 Xe2_LPG
[15:57:09] [PASSED] 30.00 Xe3_LPG
[15:57:09] [PASSED] 30.01 Xe3_LPG
[15:57:09] [PASSED] 30.03 Xe3_LPG
[15:57:09] [PASSED] 30.04 Xe3_LPG
[15:57:09] [PASSED] 30.05 Xe3_LPG
[15:57:09] [PASSED] 35.11 Xe3p_XPC
[15:57:09] ================ [PASSED] check_graphics_ip ================
[15:57:09] ===================== check_media_ip ======================
[15:57:09] [PASSED] 12.00 Xe_M
[15:57:09] [PASSED] 12.55 Xe_HPM
[15:57:09] [PASSED] 13.00 Xe_LPM+
[15:57:09] [PASSED] 13.01 Xe2_HPM
[15:57:09] [PASSED] 20.00 Xe2_LPM
[15:57:09] [PASSED] 30.00 Xe3_LPM
[15:57:09] [PASSED] 30.02 Xe3_LPM
[15:57:09] [PASSED] 35.00 Xe3p_LPM
[15:57:09] [PASSED] 35.03 Xe3p_HPM
[15:57:09] ================= [PASSED] check_media_ip ==================
[15:57:09] =================== check_platform_desc ===================
[15:57:09] [PASSED] 0x9A60 (TIGERLAKE)
[15:57:09] [PASSED] 0x9A68 (TIGERLAKE)
[15:57:09] [PASSED] 0x9A70 (TIGERLAKE)
[15:57:09] [PASSED] 0x9A40 (TIGERLAKE)
[15:57:09] [PASSED] 0x9A49 (TIGERLAKE)
[15:57:09] [PASSED] 0x9A59 (TIGERLAKE)
[15:57:09] [PASSED] 0x9A78 (TIGERLAKE)
[15:57:09] [PASSED] 0x9AC0 (TIGERLAKE)
[15:57:09] [PASSED] 0x9AC9 (TIGERLAKE)
[15:57:09] [PASSED] 0x9AD9 (TIGERLAKE)
[15:57:09] [PASSED] 0x9AF8 (TIGERLAKE)
[15:57:09] [PASSED] 0x4C80 (ROCKETLAKE)
[15:57:09] [PASSED] 0x4C8A (ROCKETLAKE)
[15:57:09] [PASSED] 0x4C8B (ROCKETLAKE)
[15:57:09] [PASSED] 0x4C8C (ROCKETLAKE)
[15:57:09] [PASSED] 0x4C90 (ROCKETLAKE)
[15:57:09] [PASSED] 0x4C9A (ROCKETLAKE)
[15:57:09] [PASSED] 0x4680 (ALDERLAKE_S)
[15:57:09] [PASSED] 0x4682 (ALDERLAKE_S)
[15:57:09] [PASSED] 0x4688 (ALDERLAKE_S)
[15:57:09] [PASSED] 0x468A (ALDERLAKE_S)
[15:57:09] [PASSED] 0x468B (ALDERLAKE_S)
[15:57:09] [PASSED] 0x4690 (ALDERLAKE_S)
[15:57:09] [PASSED] 0x4692 (ALDERLAKE_S)
[15:57:09] [PASSED] 0x4693 (ALDERLAKE_S)
[15:57:09] [PASSED] 0x46A0 (ALDERLAKE_P)
[15:57:09] [PASSED] 0x46A1 (ALDERLAKE_P)
[15:57:09] [PASSED] 0x46A2 (ALDERLAKE_P)
[15:57:09] [PASSED] 0x46A3 (ALDERLAKE_P)
[15:57:09] [PASSED] 0x46A6 (ALDERLAKE_P)
[15:57:09] [PASSED] 0x46A8 (ALDERLAKE_P)
[15:57:09] [PASSED] 0x46AA (ALDERLAKE_P)
[15:57:09] [PASSED] 0x462A (ALDERLAKE_P)
[15:57:09] [PASSED] 0x4626 (ALDERLAKE_P)
[15:57:09] [PASSED] 0x4628 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[15:57:09] [PASSED] 0x46B0 (ALDERLAKE_P)
[15:57:09] [PASSED] 0x46B1 (ALDERLAKE_P)
[15:57:09] [PASSED] 0x46B2 (ALDERLAKE_P)
[15:57:09] [PASSED] 0x46B3 (ALDERLAKE_P)
[15:57:09] [PASSED] 0x46C0 (ALDERLAKE_P)
[15:57:09] [PASSED] 0x46C1 (ALDERLAKE_P)
[15:57:09] [PASSED] 0x46C2 (ALDERLAKE_P)
[15:57:09] [PASSED] 0x46C3 (ALDERLAKE_P)
[15:57:09] [PASSED] 0x46D0 (ALDERLAKE_N)
[15:57:09] [PASSED] 0x46D1 (ALDERLAKE_N)
[15:57:09] [PASSED] 0x46D2 (ALDERLAKE_N)
[15:57:09] [PASSED] 0x46D3 (ALDERLAKE_N)
[15:57:09] [PASSED] 0x46D4 (ALDERLAKE_N)
[15:57:09] [PASSED] 0xA721 (ALDERLAKE_P)
[15:57:09] [PASSED] 0xA7A1 (ALDERLAKE_P)
[15:57:09] [PASSED] 0xA7A9 (ALDERLAKE_P)
[15:57:09] [PASSED] 0xA7AC (ALDERLAKE_P)
[15:57:09] [PASSED] 0xA7AD (ALDERLAKE_P)
[15:57:09] [PASSED] 0xA720 (ALDERLAKE_P)
[15:57:09] [PASSED] 0xA7A0 (ALDERLAKE_P)
[15:57:09] [PASSED] 0xA7A8 (ALDERLAKE_P)
[15:57:09] [PASSED] 0xA7AA (ALDERLAKE_P)
[15:57:09] [PASSED] 0xA7AB (ALDERLAKE_P)
[15:57:09] [PASSED] 0xA780 (ALDERLAKE_S)
[15:57:09] [PASSED] 0xA781 (ALDERLAKE_S)
[15:57:09] [PASSED] 0xA782 (ALDERLAKE_S)
[15:57:09] [PASSED] 0xA783 (ALDERLAKE_S)
[15:57:09] [PASSED] 0xA788 (ALDERLAKE_S)
[15:57:09] [PASSED] 0xA789 (ALDERLAKE_S)
[15:57:09] [PASSED] 0xA78A (ALDERLAKE_S)
[15:57:09] [PASSED] 0xA78B (ALDERLAKE_S)
[15:57:09] [PASSED] 0x4905 (DG1)
[15:57:09] [PASSED] 0x4906 (DG1)
[15:57:09] [PASSED] 0x4907 (DG1)
[15:57:09] [PASSED] 0x4908 (DG1)
[15:57:09] [PASSED] 0x4909 (DG1)
[15:57:09] [PASSED] 0x56C0 (DG2)
[15:57:09] [PASSED] 0x56C2 (DG2)
[15:57:09] [PASSED] 0x56C1 (DG2)
[15:57:09] [PASSED] 0x7D51 (METEORLAKE)
[15:57:09] [PASSED] 0x7DD1 (METEORLAKE)
[15:57:09] [PASSED] 0x7D41 (METEORLAKE)
[15:57:09] [PASSED] 0x7D67 (METEORLAKE)
[15:57:09] [PASSED] 0xB640 (METEORLAKE)
[15:57:09] [PASSED] 0x56A0 (DG2)
[15:57:09] [PASSED] 0x56A1 (DG2)
[15:57:09] [PASSED] 0x56A2 (DG2)
[15:57:09] [PASSED] 0x56BE (DG2)
[15:57:09] [PASSED] 0x56BF (DG2)
[15:57:09] [PASSED] 0x5690 (DG2)
[15:57:09] [PASSED] 0x5691 (DG2)
[15:57:09] [PASSED] 0x5692 (DG2)
[15:57:09] [PASSED] 0x56A5 (DG2)
[15:57:09] [PASSED] 0x56A6 (DG2)
[15:57:09] [PASSED] 0x56B0 (DG2)
[15:57:09] [PASSED] 0x56B1 (DG2)
[15:57:09] [PASSED] 0x56BA (DG2)
[15:57:09] [PASSED] 0x56BB (DG2)
[15:57:09] [PASSED] 0x56BC (DG2)
[15:57:09] [PASSED] 0x56BD (DG2)
[15:57:09] [PASSED] 0x5693 (DG2)
[15:57:09] [PASSED] 0x5694 (DG2)
[15:57:09] [PASSED] 0x5695 (DG2)
[15:57:09] [PASSED] 0x56A3 (DG2)
[15:57:09] [PASSED] 0x56A4 (DG2)
[15:57:09] [PASSED] 0x56B2 (DG2)
[15:57:09] [PASSED] 0x56B3 (DG2)
[15:57:09] [PASSED] 0x5696 (DG2)
[15:57:09] [PASSED] 0x5697 (DG2)
[15:57:09] [PASSED] 0xB69 (PVC)
[15:57:09] [PASSED] 0xB6E (PVC)
[15:57:09] [PASSED] 0xBD4 (PVC)
[15:57:09] [PASSED] 0xBD5 (PVC)
[15:57:09] [PASSED] 0xBD6 (PVC)
[15:57:09] [PASSED] 0xBD7 (PVC)
[15:57:09] [PASSED] 0xBD8 (PVC)
[15:57:09] [PASSED] 0xBD9 (PVC)
[15:57:09] [PASSED] 0xBDA (PVC)
[15:57:09] [PASSED] 0xBDB (PVC)
[15:57:09] [PASSED] 0xBE0 (PVC)
[15:57:09] [PASSED] 0xBE1 (PVC)
[15:57:09] [PASSED] 0xBE5 (PVC)
[15:57:09] [PASSED] 0x7D40 (METEORLAKE)
[15:57:09] [PASSED] 0x7D45 (METEORLAKE)
[15:57:09] [PASSED] 0x7D55 (METEORLAKE)
[15:57:09] [PASSED] 0x7D60 (METEORLAKE)
[15:57:09] [PASSED] 0x7DD5 (METEORLAKE)
[15:57:09] [PASSED] 0x6420 (LUNARLAKE)
[15:57:09] [PASSED] 0x64A0 (LUNARLAKE)
[15:57:09] [PASSED] 0x64B0 (LUNARLAKE)
[15:57:09] [PASSED] 0xE202 (BATTLEMAGE)
[15:57:09] [PASSED] 0xE209 (BATTLEMAGE)
[15:57:09] [PASSED] 0xE20B (BATTLEMAGE)
[15:57:09] [PASSED] 0xE20C (BATTLEMAGE)
[15:57:09] [PASSED] 0xE20D (BATTLEMAGE)
[15:57:09] [PASSED] 0xE210 (BATTLEMAGE)
[15:57:09] [PASSED] 0xE211 (BATTLEMAGE)
[15:57:09] [PASSED] 0xE212 (BATTLEMAGE)
[15:57:09] [PASSED] 0xE216 (BATTLEMAGE)
[15:57:09] [PASSED] 0xE220 (BATTLEMAGE)
[15:57:09] [PASSED] 0xE221 (BATTLEMAGE)
[15:57:09] [PASSED] 0xE222 (BATTLEMAGE)
[15:57:09] [PASSED] 0xE223 (BATTLEMAGE)
[15:57:09] [PASSED] 0xB080 (PANTHERLAKE)
[15:57:09] [PASSED] 0xB081 (PANTHERLAKE)
[15:57:09] [PASSED] 0xB082 (PANTHERLAKE)
[15:57:09] [PASSED] 0xB083 (PANTHERLAKE)
[15:57:09] [PASSED] 0xB084 (PANTHERLAKE)
[15:57:09] [PASSED] 0xB085 (PANTHERLAKE)
[15:57:09] [PASSED] 0xB086 (PANTHERLAKE)
[15:57:09] [PASSED] 0xB087 (PANTHERLAKE)
[15:57:09] [PASSED] 0xB08F (PANTHERLAKE)
[15:57:09] [PASSED] 0xB090 (PANTHERLAKE)
[15:57:09] [PASSED] 0xB0A0 (PANTHERLAKE)
[15:57:09] [PASSED] 0xB0B0 (PANTHERLAKE)
[15:57:09] [PASSED] 0xFD80 (PANTHERLAKE)
[15:57:09] [PASSED] 0xFD81 (PANTHERLAKE)
[15:57:09] [PASSED] 0xD740 (NOVALAKE_S)
[15:57:09] [PASSED] 0xD741 (NOVALAKE_S)
[15:57:09] [PASSED] 0xD742 (NOVALAKE_S)
[15:57:09] [PASSED] 0xD743 (NOVALAKE_S)
[15:57:09] [PASSED] 0xD744 (NOVALAKE_S)
[15:57:09] [PASSED] 0xD745 (NOVALAKE_S)
[15:57:09] [PASSED] 0x674C (CRESCENTISLAND)
[15:57:09] =============== [PASSED] check_platform_desc ===============
[15:57:09] ===================== [PASSED] xe_pci ======================
[15:57:09] =================== xe_rtp (2 subtests) ====================
[15:57:09] =============== xe_rtp_process_to_sr_tests ================
[15:57:09] [PASSED] coalesce-same-reg
[15:57:09] [PASSED] no-match-no-add
[15:57:09] [PASSED] match-or
[15:57:09] [PASSED] match-or-xfail
[15:57:09] [PASSED] no-match-no-add-multiple-rules
[15:57:09] [PASSED] two-regs-two-entries
[15:57:09] [PASSED] clr-one-set-other
[15:57:09] [PASSED] set-field
[15:57:09] [PASSED] conflict-duplicate
[15:57:09] [PASSED] conflict-not-disjoint
[15:57:09] [PASSED] conflict-reg-type
[15:57:09] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[15:57:09] ================== xe_rtp_process_tests ===================
[15:57:09] [PASSED] active1
[15:57:09] [PASSED] active2
[15:57:09] [PASSED] active-inactive
[15:57:09] [PASSED] inactive-active
[15:57:09] [PASSED] inactive-1st_or_active-inactive
[15:57:09] [PASSED] inactive-2nd_or_active-inactive
[15:57:09] [PASSED] inactive-last_or_active-inactive
[15:57:09] [PASSED] inactive-no_or_active-inactive
[15:57:09] ============== [PASSED] xe_rtp_process_tests ===============
[15:57:09] ===================== [PASSED] xe_rtp ======================
[15:57:09] ==================== xe_wa (1 subtest) =====================
[15:57:09] ======================== xe_wa_gt =========================
[15:57:09] [PASSED] TIGERLAKE B0
[15:57:09] [PASSED] DG1 A0
[15:57:09] [PASSED] DG1 B0
[15:57:09] [PASSED] ALDERLAKE_S A0
[15:57:09] [PASSED] ALDERLAKE_S B0
[15:57:09] [PASSED] ALDERLAKE_S C0
[15:57:09] [PASSED] ALDERLAKE_S D0
[15:57:09] [PASSED] ALDERLAKE_P A0
[15:57:09] [PASSED] ALDERLAKE_P B0
[15:57:09] [PASSED] ALDERLAKE_P C0
[15:57:09] [PASSED] ALDERLAKE_S RPLS D0
[15:57:09] [PASSED] ALDERLAKE_P RPLU E0
[15:57:09] [PASSED] DG2 G10 C0
[15:57:09] [PASSED] DG2 G11 B1
[15:57:09] [PASSED] DG2 G12 A1
[15:57:09] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[15:57:09] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[15:57:09] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[15:57:09] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[15:57:09] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[15:57:09] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[15:57:09] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[15:57:09] ==================== [PASSED] xe_wa_gt =====================
[15:57:09] ====================== [PASSED] xe_wa ======================
[15:57:09] ============================================================
[15:57:09] Testing complete. Ran 512 tests: passed: 494, skipped: 18
[15:57:09] Elapsed time: 36.286s total, 4.223s configuring, 31.547s building, 0.472s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[15:57:09] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:57:11] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:57:36] Starting KUnit Kernel (1/1)...
[15:57:36] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:57:36] ============ drm_test_pick_cmdline (2 subtests) ============
[15:57:36] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[15:57:36] =============== drm_test_pick_cmdline_named ===============
[15:57:36] [PASSED] NTSC
[15:57:36] [PASSED] NTSC-J
[15:57:36] [PASSED] PAL
[15:57:36] [PASSED] PAL-M
[15:57:36] =========== [PASSED] drm_test_pick_cmdline_named ===========
[15:57:36] ============== [PASSED] drm_test_pick_cmdline ==============
[15:57:36] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[15:57:36] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[15:57:36] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[15:57:36] =========== drm_validate_clone_mode (2 subtests) ===========
[15:57:36] ============== drm_test_check_in_clone_mode ===============
[15:57:36] [PASSED] in_clone_mode
[15:57:36] [PASSED] not_in_clone_mode
[15:57:36] ========== [PASSED] drm_test_check_in_clone_mode ===========
[15:57:36] =============== drm_test_check_valid_clones ===============
[15:57:36] [PASSED] not_in_clone_mode
[15:57:36] [PASSED] valid_clone
[15:57:36] [PASSED] invalid_clone
[15:57:36] =========== [PASSED] drm_test_check_valid_clones ===========
[15:57:36] ============= [PASSED] drm_validate_clone_mode =============
[15:57:36] ============= drm_validate_modeset (1 subtest) =============
[15:57:36] [PASSED] drm_test_check_connector_changed_modeset
[15:57:36] ============== [PASSED] drm_validate_modeset ===============
[15:57:36] ====== drm_test_bridge_get_current_state (2 subtests) ======
[15:57:36] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[15:57:36] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[15:57:36] ======== [PASSED] drm_test_bridge_get_current_state ========
[15:57:36] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[15:57:36] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[15:57:36] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[15:57:36] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[15:57:36] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[15:57:36] ============== drm_bridge_alloc (2 subtests) ===============
[15:57:36] [PASSED] drm_test_drm_bridge_alloc_basic
[15:57:36] [PASSED] drm_test_drm_bridge_alloc_get_put
[15:57:36] ================ [PASSED] drm_bridge_alloc =================
[15:57:36] ================== drm_buddy (9 subtests) ==================
[15:57:36] [PASSED] drm_test_buddy_alloc_limit
[15:57:36] [PASSED] drm_test_buddy_alloc_optimistic
[15:57:36] [PASSED] drm_test_buddy_alloc_pessimistic
[15:57:36] [PASSED] drm_test_buddy_alloc_pathological
[15:57:36] [PASSED] drm_test_buddy_alloc_contiguous
[15:57:36] [PASSED] drm_test_buddy_alloc_clear
[15:57:36] [PASSED] drm_test_buddy_alloc_range_bias
[15:57:36] [PASSED] drm_test_buddy_fragmentation_performance
[15:57:36] [PASSED] drm_test_buddy_alloc_exceeds_max_order
[15:57:36] ==================== [PASSED] drm_buddy ====================
[15:57:36] ============= drm_cmdline_parser (40 subtests) =============
[15:57:36] [PASSED] drm_test_cmdline_force_d_only
[15:57:36] [PASSED] drm_test_cmdline_force_D_only_dvi
[15:57:36] [PASSED] drm_test_cmdline_force_D_only_hdmi
[15:57:36] [PASSED] drm_test_cmdline_force_D_only_not_digital
[15:57:36] [PASSED] drm_test_cmdline_force_e_only
[15:57:36] [PASSED] drm_test_cmdline_res
[15:57:36] [PASSED] drm_test_cmdline_res_vesa
[15:57:36] [PASSED] drm_test_cmdline_res_vesa_rblank
[15:57:36] [PASSED] drm_test_cmdline_res_rblank
[15:57:36] [PASSED] drm_test_cmdline_res_bpp
[15:57:36] [PASSED] drm_test_cmdline_res_refresh
[15:57:36] [PASSED] drm_test_cmdline_res_bpp_refresh
[15:57:36] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[15:57:36] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[15:57:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[15:57:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[15:57:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[15:57:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[15:57:36] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[15:57:36] [PASSED] drm_test_cmdline_res_margins_force_on
[15:57:36] [PASSED] drm_test_cmdline_res_vesa_margins
[15:57:36] [PASSED] drm_test_cmdline_name
[15:57:36] [PASSED] drm_test_cmdline_name_bpp
[15:57:36] [PASSED] drm_test_cmdline_name_option
[15:57:36] [PASSED] drm_test_cmdline_name_bpp_option
[15:57:36] [PASSED] drm_test_cmdline_rotate_0
[15:57:36] [PASSED] drm_test_cmdline_rotate_90
[15:57:36] [PASSED] drm_test_cmdline_rotate_180
[15:57:36] [PASSED] drm_test_cmdline_rotate_270
[15:57:36] [PASSED] drm_test_cmdline_hmirror
[15:57:36] [PASSED] drm_test_cmdline_vmirror
[15:57:36] [PASSED] drm_test_cmdline_margin_options
[15:57:36] [PASSED] drm_test_cmdline_multiple_options
[15:57:36] [PASSED] drm_test_cmdline_bpp_extra_and_option
[15:57:36] [PASSED] drm_test_cmdline_extra_and_option
[15:57:36] [PASSED] drm_test_cmdline_freestanding_options
[15:57:36] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[15:57:36] [PASSED] drm_test_cmdline_panel_orientation
[15:57:36] ================ drm_test_cmdline_invalid =================
[15:57:36] [PASSED] margin_only
[15:57:36] [PASSED] interlace_only
[15:57:36] [PASSED] res_missing_x
[15:57:36] [PASSED] res_missing_y
[15:57:36] [PASSED] res_bad_y
[15:57:36] [PASSED] res_missing_y_bpp
[15:57:36] [PASSED] res_bad_bpp
[15:57:36] [PASSED] res_bad_refresh
[15:57:36] [PASSED] res_bpp_refresh_force_on_off
[15:57:36] [PASSED] res_invalid_mode
[15:57:36] [PASSED] res_bpp_wrong_place_mode
[15:57:36] [PASSED] name_bpp_refresh
[15:57:36] [PASSED] name_refresh
[15:57:36] [PASSED] name_refresh_wrong_mode
[15:57:36] [PASSED] name_refresh_invalid_mode
[15:57:36] [PASSED] rotate_multiple
[15:57:36] [PASSED] rotate_invalid_val
[15:57:36] [PASSED] rotate_truncated
[15:57:36] [PASSED] invalid_option
[15:57:36] [PASSED] invalid_tv_option
[15:57:36] [PASSED] truncated_tv_option
[15:57:36] ============ [PASSED] drm_test_cmdline_invalid =============
[15:57:36] =============== drm_test_cmdline_tv_options ===============
[15:57:36] [PASSED] NTSC
[15:57:36] [PASSED] NTSC_443
[15:57:36] [PASSED] NTSC_J
[15:57:36] [PASSED] PAL
[15:57:36] [PASSED] PAL_M
[15:57:36] [PASSED] PAL_N
[15:57:36] [PASSED] SECAM
[15:57:36] [PASSED] MONO_525
[15:57:36] [PASSED] MONO_625
[15:57:36] =========== [PASSED] drm_test_cmdline_tv_options ===========
[15:57:36] =============== [PASSED] drm_cmdline_parser ================
[15:57:36] ========== drmm_connector_hdmi_init (20 subtests) ==========
[15:57:36] [PASSED] drm_test_connector_hdmi_init_valid
[15:57:36] [PASSED] drm_test_connector_hdmi_init_bpc_8
[15:57:36] [PASSED] drm_test_connector_hdmi_init_bpc_10
[15:57:36] [PASSED] drm_test_connector_hdmi_init_bpc_12
[15:57:36] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[15:57:36] [PASSED] drm_test_connector_hdmi_init_bpc_null
[15:57:36] [PASSED] drm_test_connector_hdmi_init_formats_empty
[15:57:36] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[15:57:36] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[15:57:36] [PASSED] supported_formats=0x9 yuv420_allowed=1
[15:57:36] [PASSED] supported_formats=0x9 yuv420_allowed=0
[15:57:36] [PASSED] supported_formats=0x3 yuv420_allowed=1
[15:57:36] [PASSED] supported_formats=0x3 yuv420_allowed=0
[15:57:36] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[15:57:36] [PASSED] drm_test_connector_hdmi_init_null_ddc
[15:57:36] [PASSED] drm_test_connector_hdmi_init_null_product
[15:57:36] [PASSED] drm_test_connector_hdmi_init_null_vendor
[15:57:36] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[15:57:36] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[15:57:36] [PASSED] drm_test_connector_hdmi_init_product_valid
[15:57:36] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[15:57:36] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[15:57:36] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[15:57:36] ========= drm_test_connector_hdmi_init_type_valid =========
[15:57:36] [PASSED] HDMI-A
[15:57:36] [PASSED] HDMI-B
[15:57:36] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[15:57:36] ======== drm_test_connector_hdmi_init_type_invalid ========
[15:57:36] [PASSED] Unknown
[15:57:36] [PASSED] VGA
[15:57:36] [PASSED] DVI-I
[15:57:36] [PASSED] DVI-D
[15:57:36] [PASSED] DVI-A
[15:57:36] [PASSED] Composite
[15:57:36] [PASSED] SVIDEO
[15:57:36] [PASSED] LVDS
[15:57:36] [PASSED] Component
[15:57:36] [PASSED] DIN
[15:57:36] [PASSED] DP
[15:57:36] [PASSED] TV
[15:57:36] [PASSED] eDP
[15:57:36] [PASSED] Virtual
[15:57:36] [PASSED] DSI
[15:57:36] [PASSED] DPI
[15:57:36] [PASSED] Writeback
[15:57:36] [PASSED] SPI
[15:57:36] [PASSED] USB
[15:57:36] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[15:57:36] ============ [PASSED] drmm_connector_hdmi_init =============
[15:57:36] ============= drmm_connector_init (3 subtests) =============
[15:57:36] [PASSED] drm_test_drmm_connector_init
[15:57:36] [PASSED] drm_test_drmm_connector_init_null_ddc
[15:57:36] ========= drm_test_drmm_connector_init_type_valid =========
[15:57:36] [PASSED] Unknown
[15:57:36] [PASSED] VGA
[15:57:36] [PASSED] DVI-I
[15:57:36] [PASSED] DVI-D
[15:57:36] [PASSED] DVI-A
[15:57:36] [PASSED] Composite
[15:57:36] [PASSED] SVIDEO
[15:57:36] [PASSED] LVDS
[15:57:36] [PASSED] Component
[15:57:36] [PASSED] DIN
[15:57:36] [PASSED] DP
[15:57:36] [PASSED] HDMI-A
[15:57:36] [PASSED] HDMI-B
[15:57:36] [PASSED] TV
[15:57:36] [PASSED] eDP
[15:57:36] [PASSED] Virtual
[15:57:36] [PASSED] DSI
[15:57:36] [PASSED] DPI
[15:57:36] [PASSED] Writeback
[15:57:36] [PASSED] SPI
[15:57:36] [PASSED] USB
[15:57:36] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[15:57:36] =============== [PASSED] drmm_connector_init ===============
[15:57:36] ========= drm_connector_dynamic_init (6 subtests) ==========
[15:57:36] [PASSED] drm_test_drm_connector_dynamic_init
[15:57:36] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[15:57:36] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[15:57:36] [PASSED] drm_test_drm_connector_dynamic_init_properties
[15:57:36] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[15:57:36] [PASSED] Unknown
[15:57:36] [PASSED] VGA
[15:57:36] [PASSED] DVI-I
[15:57:36] [PASSED] DVI-D
[15:57:36] [PASSED] DVI-A
[15:57:36] [PASSED] Composite
[15:57:36] [PASSED] SVIDEO
[15:57:36] [PASSED] LVDS
[15:57:36] [PASSED] Component
[15:57:36] [PASSED] DIN
[15:57:36] [PASSED] DP
[15:57:36] [PASSED] HDMI-A
[15:57:36] [PASSED] HDMI-B
[15:57:36] [PASSED] TV
[15:57:36] [PASSED] eDP
[15:57:36] [PASSED] Virtual
[15:57:36] [PASSED] DSI
[15:57:36] [PASSED] DPI
[15:57:36] [PASSED] Writeback
[15:57:36] [PASSED] SPI
[15:57:36] [PASSED] USB
[15:57:36] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[15:57:36] ======== drm_test_drm_connector_dynamic_init_name =========
[15:57:36] [PASSED] Unknown
[15:57:36] [PASSED] VGA
[15:57:36] [PASSED] DVI-I
[15:57:36] [PASSED] DVI-D
[15:57:36] [PASSED] DVI-A
[15:57:36] [PASSED] Composite
[15:57:36] [PASSED] SVIDEO
[15:57:36] [PASSED] LVDS
[15:57:36] [PASSED] Component
[15:57:36] [PASSED] DIN
[15:57:36] [PASSED] DP
[15:57:36] [PASSED] HDMI-A
[15:57:36] [PASSED] HDMI-B
[15:57:36] [PASSED] TV
[15:57:36] [PASSED] eDP
[15:57:36] [PASSED] Virtual
[15:57:36] [PASSED] DSI
[15:57:37] [PASSED] DPI
[15:57:37] [PASSED] Writeback
[15:57:37] [PASSED] SPI
[15:57:37] [PASSED] USB
[15:57:37] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[15:57:37] =========== [PASSED] drm_connector_dynamic_init ============
[15:57:37] ==== drm_connector_dynamic_register_early (4 subtests) =====
[15:57:37] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[15:57:37] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[15:57:37] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[15:57:37] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[15:57:37] ====== [PASSED] drm_connector_dynamic_register_early =======
[15:57:37] ======= drm_connector_dynamic_register (7 subtests) ========
[15:57:37] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[15:57:37] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[15:57:37] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[15:57:37] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[15:57:37] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[15:57:37] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[15:57:37] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[15:57:37] ========= [PASSED] drm_connector_dynamic_register ==========
[15:57:37] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[15:57:37] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[15:57:37] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[15:57:37] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[15:57:37] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[15:57:37] ========== drm_test_get_tv_mode_from_name_valid ===========
[15:57:37] [PASSED] NTSC
[15:57:37] [PASSED] NTSC-443
[15:57:37] [PASSED] NTSC-J
[15:57:37] [PASSED] PAL
[15:57:37] [PASSED] PAL-M
[15:57:37] [PASSED] PAL-N
[15:57:37] [PASSED] SECAM
[15:57:37] [PASSED] Mono
[15:57:37] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[15:57:37] [PASSED] drm_test_get_tv_mode_from_name_truncated
[15:57:37] ============ [PASSED] drm_get_tv_mode_from_name ============
[15:57:37] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[15:57:37] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[15:57:37] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[15:57:37] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[15:57:37] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[15:57:37] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[15:57:37] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[15:57:37] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[15:57:37] [PASSED] VIC 96
[15:57:37] [PASSED] VIC 97
[15:57:37] [PASSED] VIC 101
[15:57:37] [PASSED] VIC 102
[15:57:37] [PASSED] VIC 106
[15:57:37] [PASSED] VIC 107
[15:57:37] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[15:57:37] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[15:57:37] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[15:57:37] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[15:57:37] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[15:57:37] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[15:57:37] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[15:57:37] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[15:57:37] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[15:57:37] [PASSED] Automatic
[15:57:37] [PASSED] Full
[15:57:37] [PASSED] Limited 16:235
[15:57:37] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[15:57:37] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[15:57:37] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[15:57:37] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[15:57:37] === drm_test_drm_hdmi_connector_get_output_format_name ====
[15:57:37] [PASSED] RGB
[15:57:37] [PASSED] YUV 4:2:0
[15:57:37] [PASSED] YUV 4:2:2
[15:57:37] [PASSED] YUV 4:4:4
[15:57:37] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[15:57:37] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[15:57:37] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[15:57:37] ============= drm_damage_helper (21 subtests) ==============
[15:57:37] [PASSED] drm_test_damage_iter_no_damage
[15:57:37] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[15:57:37] [PASSED] drm_test_damage_iter_no_damage_src_moved
[15:57:37] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[15:57:37] [PASSED] drm_test_damage_iter_no_damage_not_visible
[15:57:37] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[15:57:37] [PASSED] drm_test_damage_iter_no_damage_no_fb
[15:57:37] [PASSED] drm_test_damage_iter_simple_damage
[15:57:37] [PASSED] drm_test_damage_iter_single_damage
[15:57:37] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[15:57:37] [PASSED] drm_test_damage_iter_single_damage_outside_src
[15:57:37] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[15:57:37] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[15:57:37] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[15:57:37] [PASSED] drm_test_damage_iter_single_damage_src_moved
[15:57:37] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[15:57:37] [PASSED] drm_test_damage_iter_damage
[15:57:37] [PASSED] drm_test_damage_iter_damage_one_intersect
[15:57:37] [PASSED] drm_test_damage_iter_damage_one_outside
[15:57:37] [PASSED] drm_test_damage_iter_damage_src_moved
[15:57:37] [PASSED] drm_test_damage_iter_damage_not_visible
[15:57:37] ================ [PASSED] drm_damage_helper ================
[15:57:37] ============== drm_dp_mst_helper (3 subtests) ==============
[15:57:37] ============== drm_test_dp_mst_calc_pbn_mode ==============
[15:57:37] [PASSED] Clock 154000 BPP 30 DSC disabled
[15:57:37] [PASSED] Clock 234000 BPP 30 DSC disabled
[15:57:37] [PASSED] Clock 297000 BPP 24 DSC disabled
[15:57:37] [PASSED] Clock 332880 BPP 24 DSC enabled
[15:57:37] [PASSED] Clock 324540 BPP 24 DSC enabled
[15:57:37] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[15:57:37] ============== drm_test_dp_mst_calc_pbn_div ===============
[15:57:37] [PASSED] Link rate 2000000 lane count 4
[15:57:37] [PASSED] Link rate 2000000 lane count 2
[15:57:37] [PASSED] Link rate 2000000 lane count 1
[15:57:37] [PASSED] Link rate 1350000 lane count 4
[15:57:37] [PASSED] Link rate 1350000 lane count 2
[15:57:37] [PASSED] Link rate 1350000 lane count 1
[15:57:37] [PASSED] Link rate 1000000 lane count 4
[15:57:37] [PASSED] Link rate 1000000 lane count 2
[15:57:37] [PASSED] Link rate 1000000 lane count 1
[15:57:37] [PASSED] Link rate 810000 lane count 4
[15:57:37] [PASSED] Link rate 810000 lane count 2
[15:57:37] [PASSED] Link rate 810000 lane count 1
[15:57:37] [PASSED] Link rate 540000 lane count 4
[15:57:37] [PASSED] Link rate 540000 lane count 2
[15:57:37] [PASSED] Link rate 540000 lane count 1
[15:57:37] [PASSED] Link rate 270000 lane count 4
[15:57:37] [PASSED] Link rate 270000 lane count 2
[15:57:37] [PASSED] Link rate 270000 lane count 1
[15:57:37] [PASSED] Link rate 162000 lane count 4
[15:57:37] [PASSED] Link rate 162000 lane count 2
[15:57:37] [PASSED] Link rate 162000 lane count 1
[15:57:37] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[15:57:37] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[15:57:37] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[15:57:37] [PASSED] DP_POWER_UP_PHY with port number
[15:57:37] [PASSED] DP_POWER_DOWN_PHY with port number
[15:57:37] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[15:57:37] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[15:57:37] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[15:57:37] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[15:57:37] [PASSED] DP_QUERY_PAYLOAD with port number
[15:57:37] [PASSED] DP_QUERY_PAYLOAD with VCPI
[15:57:37] [PASSED] DP_REMOTE_DPCD_READ with port number
[15:57:37] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[15:57:37] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[15:57:37] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[15:57:37] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[15:57:37] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[15:57:37] [PASSED] DP_REMOTE_I2C_READ with port number
[15:57:37] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[15:57:37] [PASSED] DP_REMOTE_I2C_READ with transactions array
[15:57:37] [PASSED] DP_REMOTE_I2C_WRITE with port number
[15:57:37] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[15:57:37] [PASSED] DP_REMOTE_I2C_WRITE with data array
[15:57:37] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[15:57:37] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[15:57:37] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[15:57:37] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[15:57:37] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[15:57:37] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[15:57:37] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[15:57:37] ================ [PASSED] drm_dp_mst_helper ================
[15:57:37] ================== drm_exec (7 subtests) ===================
[15:57:37] [PASSED] sanitycheck
[15:57:37] [PASSED] test_lock
[15:57:37] [PASSED] test_lock_unlock
[15:57:37] [PASSED] test_duplicates
[15:57:37] [PASSED] test_prepare
[15:57:37] [PASSED] test_prepare_array
[15:57:37] [PASSED] test_multiple_loops
[15:57:37] ==================== [PASSED] drm_exec =====================
[15:57:37] =========== drm_format_helper_test (17 subtests) ===========
[15:57:37] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[15:57:37] [PASSED] single_pixel_source_buffer
[15:57:37] [PASSED] single_pixel_clip_rectangle
[15:57:37] [PASSED] well_known_colors
[15:57:37] [PASSED] destination_pitch
[15:57:37] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[15:57:37] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[15:57:37] [PASSED] single_pixel_source_buffer
[15:57:37] [PASSED] single_pixel_clip_rectangle
[15:57:37] [PASSED] well_known_colors
[15:57:37] [PASSED] destination_pitch
[15:57:37] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[15:57:37] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[15:57:37] [PASSED] single_pixel_source_buffer
[15:57:37] [PASSED] single_pixel_clip_rectangle
[15:57:37] [PASSED] well_known_colors
[15:57:37] [PASSED] destination_pitch
[15:57:37] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[15:57:37] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[15:57:37] [PASSED] single_pixel_source_buffer
[15:57:37] [PASSED] single_pixel_clip_rectangle
[15:57:37] [PASSED] well_known_colors
[15:57:37] [PASSED] destination_pitch
[15:57:37] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[15:57:37] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[15:57:37] [PASSED] single_pixel_source_buffer
[15:57:37] [PASSED] single_pixel_clip_rectangle
[15:57:37] [PASSED] well_known_colors
[15:57:37] [PASSED] destination_pitch
[15:57:37] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[15:57:37] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[15:57:37] [PASSED] single_pixel_source_buffer
[15:57:37] [PASSED] single_pixel_clip_rectangle
[15:57:37] [PASSED] well_known_colors
[15:57:37] [PASSED] destination_pitch
[15:57:37] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[15:57:37] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[15:57:37] [PASSED] single_pixel_source_buffer
[15:57:37] [PASSED] single_pixel_clip_rectangle
[15:57:37] [PASSED] well_known_colors
[15:57:37] [PASSED] destination_pitch
[15:57:37] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[15:57:37] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[15:57:37] [PASSED] single_pixel_source_buffer
[15:57:37] [PASSED] single_pixel_clip_rectangle
[15:57:37] [PASSED] well_known_colors
[15:57:37] [PASSED] destination_pitch
[15:57:37] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[15:57:37] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[15:57:37] [PASSED] single_pixel_source_buffer
[15:57:37] [PASSED] single_pixel_clip_rectangle
[15:57:37] [PASSED] well_known_colors
[15:57:37] [PASSED] destination_pitch
[15:57:37] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[15:57:37] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[15:57:37] [PASSED] single_pixel_source_buffer
[15:57:37] [PASSED] single_pixel_clip_rectangle
[15:57:37] [PASSED] well_known_colors
[15:57:37] [PASSED] destination_pitch
[15:57:37] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[15:57:37] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[15:57:37] [PASSED] single_pixel_source_buffer
[15:57:37] [PASSED] single_pixel_clip_rectangle
[15:57:37] [PASSED] well_known_colors
[15:57:37] [PASSED] destination_pitch
[15:57:37] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[15:57:37] ============== drm_test_fb_xrgb8888_to_mono ===============
[15:57:37] [PASSED] single_pixel_source_buffer
[15:57:37] [PASSED] single_pixel_clip_rectangle
[15:57:37] [PASSED] well_known_colors
[15:57:37] [PASSED] destination_pitch
[15:57:37] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[15:57:37] ==================== drm_test_fb_swab =====================
[15:57:37] [PASSED] single_pixel_source_buffer
[15:57:37] [PASSED] single_pixel_clip_rectangle
[15:57:37] [PASSED] well_known_colors
[15:57:37] [PASSED] destination_pitch
[15:57:37] ================ [PASSED] drm_test_fb_swab =================
[15:57:37] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[15:57:37] [PASSED] single_pixel_source_buffer
[15:57:37] [PASSED] single_pixel_clip_rectangle
[15:57:37] [PASSED] well_known_colors
[15:57:37] [PASSED] destination_pitch
[15:57:37] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[15:57:37] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[15:57:37] [PASSED] single_pixel_source_buffer
[15:57:37] [PASSED] single_pixel_clip_rectangle
[15:57:37] [PASSED] well_known_colors
[15:57:37] [PASSED] destination_pitch
[15:57:37] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[15:57:37] ================= drm_test_fb_clip_offset =================
[15:57:37] [PASSED] pass through
[15:57:37] [PASSED] horizontal offset
[15:57:37] [PASSED] vertical offset
[15:57:37] [PASSED] horizontal and vertical offset
[15:57:37] [PASSED] horizontal offset (custom pitch)
[15:57:37] [PASSED] vertical offset (custom pitch)
[15:57:37] [PASSED] horizontal and vertical offset (custom pitch)
[15:57:37] ============= [PASSED] drm_test_fb_clip_offset =============
[15:57:37] =================== drm_test_fb_memcpy ====================
[15:57:37] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[15:57:37] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[15:57:37] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[15:57:37] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[15:57:37] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[15:57:37] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[15:57:37] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[15:57:37] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[15:57:37] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[15:57:37] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[15:57:37] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[15:57:37] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[15:57:37] =============== [PASSED] drm_test_fb_memcpy ================
[15:57:37] ============= [PASSED] drm_format_helper_test ==============
[15:57:37] ================= drm_format (18 subtests) =================
[15:57:37] [PASSED] drm_test_format_block_width_invalid
[15:57:37] [PASSED] drm_test_format_block_width_one_plane
[15:57:37] [PASSED] drm_test_format_block_width_two_plane
[15:57:37] [PASSED] drm_test_format_block_width_three_plane
[15:57:37] [PASSED] drm_test_format_block_width_tiled
[15:57:37] [PASSED] drm_test_format_block_height_invalid
[15:57:37] [PASSED] drm_test_format_block_height_one_plane
[15:57:37] [PASSED] drm_test_format_block_height_two_plane
[15:57:37] [PASSED] drm_test_format_block_height_three_plane
[15:57:37] [PASSED] drm_test_format_block_height_tiled
[15:57:37] [PASSED] drm_test_format_min_pitch_invalid
[15:57:37] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[15:57:37] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[15:57:37] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[15:57:37] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[15:57:37] [PASSED] drm_test_format_min_pitch_two_plane
[15:57:37] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[15:57:37] [PASSED] drm_test_format_min_pitch_tiled
[15:57:37] =================== [PASSED] drm_format ====================
[15:57:37] ============== drm_framebuffer (10 subtests) ===============
[15:57:37] ========== drm_test_framebuffer_check_src_coords ==========
[15:57:37] [PASSED] Success: source fits into fb
[15:57:37] [PASSED] Fail: overflowing fb with x-axis coordinate
[15:57:37] [PASSED] Fail: overflowing fb with y-axis coordinate
[15:57:37] [PASSED] Fail: overflowing fb with source width
[15:57:37] [PASSED] Fail: overflowing fb with source height
[15:57:37] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[15:57:37] [PASSED] drm_test_framebuffer_cleanup
[15:57:37] =============== drm_test_framebuffer_create ===============
[15:57:37] [PASSED] ABGR8888 normal sizes
[15:57:37] [PASSED] ABGR8888 max sizes
[15:57:37] [PASSED] ABGR8888 pitch greater than min required
[15:57:37] [PASSED] ABGR8888 pitch less than min required
[15:57:37] [PASSED] ABGR8888 Invalid width
[15:57:37] [PASSED] ABGR8888 Invalid buffer handle
[15:57:37] [PASSED] No pixel format
[15:57:37] [PASSED] ABGR8888 Width 0
[15:57:37] [PASSED] ABGR8888 Height 0
[15:57:37] [PASSED] ABGR8888 Out of bound height * pitch combination
[15:57:37] [PASSED] ABGR8888 Large buffer offset
[15:57:37] [PASSED] ABGR8888 Buffer offset for inexistent plane
[15:57:37] [PASSED] ABGR8888 Invalid flag
[15:57:37] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[15:57:37] [PASSED] ABGR8888 Valid buffer modifier
[15:57:37] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[15:57:37] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[15:57:37] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[15:57:37] [PASSED] NV12 Normal sizes
[15:57:37] [PASSED] NV12 Max sizes
[15:57:37] [PASSED] NV12 Invalid pitch
[15:57:37] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[15:57:37] [PASSED] NV12 different modifier per-plane
[15:57:37] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[15:57:37] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[15:57:37] [PASSED] NV12 Modifier for inexistent plane
[15:57:37] [PASSED] NV12 Handle for inexistent plane
[15:57:37] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[15:57:37] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[15:57:37] [PASSED] YVU420 Normal sizes
[15:57:37] [PASSED] YVU420 Max sizes
[15:57:37] [PASSED] YVU420 Invalid pitch
[15:57:37] [PASSED] YVU420 Different pitches
[15:57:37] [PASSED] YVU420 Different buffer offsets/pitches
[15:57:37] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[15:57:37] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[15:57:37] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[15:57:37] [PASSED] YVU420 Valid modifier
[15:57:37] [PASSED] YVU420 Different modifiers per plane
[15:57:37] [PASSED] YVU420 Modifier for inexistent plane
[15:57:37] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[15:57:37] [PASSED] X0L2 Normal sizes
[15:57:37] [PASSED] X0L2 Max sizes
[15:57:37] [PASSED] X0L2 Invalid pitch
[15:57:37] [PASSED] X0L2 Pitch greater than minimum required
[15:57:37] [PASSED] X0L2 Handle for inexistent plane
[15:57:37] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[15:57:37] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[15:57:37] [PASSED] X0L2 Valid modifier
[15:57:37] [PASSED] X0L2 Modifier for inexistent plane
[15:57:37] =========== [PASSED] drm_test_framebuffer_create ===========
[15:57:37] [PASSED] drm_test_framebuffer_free
[15:57:37] [PASSED] drm_test_framebuffer_init
[15:57:37] [PASSED] drm_test_framebuffer_init_bad_format
[15:57:37] [PASSED] drm_test_framebuffer_init_dev_mismatch
[15:57:37] [PASSED] drm_test_framebuffer_lookup
[15:57:37] [PASSED] drm_test_framebuffer_lookup_inexistent
[15:57:37] [PASSED] drm_test_framebuffer_modifiers_not_supported
[15:57:37] ================= [PASSED] drm_framebuffer =================
[15:57:37] ================ drm_gem_shmem (8 subtests) ================
[15:57:37] [PASSED] drm_gem_shmem_test_obj_create
[15:57:37] [PASSED] drm_gem_shmem_test_obj_create_private
[15:57:37] [PASSED] drm_gem_shmem_test_pin_pages
[15:57:37] [PASSED] drm_gem_shmem_test_vmap
[15:57:37] [PASSED] drm_gem_shmem_test_get_sg_table
[15:57:37] [PASSED] drm_gem_shmem_test_get_pages_sgt
[15:57:37] [PASSED] drm_gem_shmem_test_madvise
[15:57:37] [PASSED] drm_gem_shmem_test_purge
[15:57:37] ================== [PASSED] drm_gem_shmem ==================
[15:57:37] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[15:57:37] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[15:57:37] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[15:57:37] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[15:57:37] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[15:57:37] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[15:57:37] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[15:57:37] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[15:57:37] [PASSED] Automatic
[15:57:37] [PASSED] Full
[15:57:37] [PASSED] Limited 16:235
[15:57:37] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[15:57:37] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[15:57:37] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[15:57:37] [PASSED] drm_test_check_disable_connector
[15:57:37] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[15:57:37] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[15:57:37] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[15:57:37] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[15:57:37] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[15:57:37] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[15:57:37] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[15:57:37] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[15:57:37] [PASSED] drm_test_check_output_bpc_dvi
[15:57:37] [PASSED] drm_test_check_output_bpc_format_vic_1
[15:57:37] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[15:57:37] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[15:57:37] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[15:57:37] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[15:57:37] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[15:57:37] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[15:57:37] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[15:57:37] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[15:57:37] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[15:57:37] [PASSED] drm_test_check_broadcast_rgb_value
[15:57:37] [PASSED] drm_test_check_bpc_8_value
[15:57:37] [PASSED] drm_test_check_bpc_10_value
[15:57:37] [PASSED] drm_test_check_bpc_12_value
[15:57:37] [PASSED] drm_test_check_format_value
[15:57:37] [PASSED] drm_test_check_tmds_char_value
[15:57:37] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[15:57:37] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[15:57:37] [PASSED] drm_test_check_mode_valid
[15:57:37] [PASSED] drm_test_check_mode_valid_reject
[15:57:37] [PASSED] drm_test_check_mode_valid_reject_rate
[15:57:37] [PASSED] drm_test_check_mode_valid_reject_max_clock
[15:57:37] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[15:57:37] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[15:57:37] [PASSED] drm_test_check_infoframes
[15:57:37] [PASSED] drm_test_check_reject_avi_infoframe
[15:57:37] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[15:57:37] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[15:57:37] [PASSED] drm_test_check_reject_audio_infoframe
[15:57:37] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[15:57:37] ================= drm_managed (2 subtests) =================
[15:57:37] [PASSED] drm_test_managed_release_action
[15:57:37] [PASSED] drm_test_managed_run_action
[15:57:37] =================== [PASSED] drm_managed ===================
[15:57:37] =================== drm_mm (6 subtests) ====================
[15:57:37] [PASSED] drm_test_mm_init
[15:57:37] [PASSED] drm_test_mm_debug
[15:57:37] [PASSED] drm_test_mm_align32
[15:57:37] [PASSED] drm_test_mm_align64
[15:57:37] [PASSED] drm_test_mm_lowest
[15:57:37] [PASSED] drm_test_mm_highest
[15:57:37] ===================== [PASSED] drm_mm ======================
[15:57:37] ============= drm_modes_analog_tv (5 subtests) =============
[15:57:37] [PASSED] drm_test_modes_analog_tv_mono_576i
[15:57:37] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[15:57:37] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[15:57:37] [PASSED] drm_test_modes_analog_tv_pal_576i
[15:57:37] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[15:57:37] =============== [PASSED] drm_modes_analog_tv ===============
[15:57:37] ============== drm_plane_helper (2 subtests) ===============
[15:57:37] =============== drm_test_check_plane_state ================
[15:57:37] [PASSED] clipping_simple
[15:57:37] [PASSED] clipping_rotate_reflect
[15:57:37] [PASSED] positioning_simple
[15:57:37] [PASSED] upscaling
[15:57:37] [PASSED] downscaling
[15:57:37] [PASSED] rounding1
[15:57:37] [PASSED] rounding2
[15:57:37] [PASSED] rounding3
[15:57:37] [PASSED] rounding4
[15:57:37] =========== [PASSED] drm_test_check_plane_state ============
[15:57:37] =========== drm_test_check_invalid_plane_state ============
[15:57:37] [PASSED] positioning_invalid
[15:57:37] [PASSED] upscaling_invalid
[15:57:37] [PASSED] downscaling_invalid
[15:57:37] ======= [PASSED] drm_test_check_invalid_plane_state ========
[15:57:37] ================ [PASSED] drm_plane_helper =================
[15:57:37] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[15:57:37] ====== drm_test_connector_helper_tv_get_modes_check =======
[15:57:37] [PASSED] None
[15:57:37] [PASSED] PAL
[15:57:37] [PASSED] NTSC
[15:57:37] [PASSED] Both, NTSC Default
[15:57:37] [PASSED] Both, PAL Default
[15:57:37] [PASSED] Both, NTSC Default, with PAL on command-line
[15:57:37] [PASSED] Both, PAL Default, with NTSC on command-line
[15:57:37] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[15:57:37] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[15:57:37] ================== drm_rect (9 subtests) ===================
[15:57:37] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[15:57:37] [PASSED] drm_test_rect_clip_scaled_not_clipped
[15:57:37] [PASSED] drm_test_rect_clip_scaled_clipped
[15:57:37] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[15:57:37] ================= drm_test_rect_intersect =================
[15:57:37] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[15:57:37] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[15:57:37] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[15:57:37] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[15:57:37] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[15:57:37] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[15:57:37] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[15:57:37] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[15:57:37] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[15:57:37] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[15:57:37] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[15:57:37] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[15:57:37] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[15:57:37] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[15:57:37] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
stty: 'standard input': Inappropriate ioctl for device
[15:57:37] ============= [PASSED] drm_test_rect_intersect =============
[15:57:37] ================ drm_test_rect_calc_hscale ================
[15:57:37] [PASSED] normal use
[15:57:37] [PASSED] out of max range
[15:57:37] [PASSED] out of min range
[15:57:37] [PASSED] zero dst
[15:57:37] [PASSED] negative src
[15:57:37] [PASSED] negative dst
[15:57:37] ============ [PASSED] drm_test_rect_calc_hscale ============
[15:57:37] ================ drm_test_rect_calc_vscale ================
[15:57:37] [PASSED] normal use
[15:57:37] [PASSED] out of max range
[15:57:37] [PASSED] out of min range
[15:57:37] [PASSED] zero dst
[15:57:37] [PASSED] negative src
[15:57:37] [PASSED] negative dst
[15:57:37] ============ [PASSED] drm_test_rect_calc_vscale ============
[15:57:37] ================== drm_test_rect_rotate ===================
[15:57:37] [PASSED] reflect-x
[15:57:37] [PASSED] reflect-y
[15:57:37] [PASSED] rotate-0
[15:57:37] [PASSED] rotate-90
[15:57:37] [PASSED] rotate-180
[15:57:37] [PASSED] rotate-270
[15:57:37] ============== [PASSED] drm_test_rect_rotate ===============
[15:57:37] ================ drm_test_rect_rotate_inv =================
[15:57:37] [PASSED] reflect-x
[15:57:37] [PASSED] reflect-y
[15:57:37] [PASSED] rotate-0
[15:57:37] [PASSED] rotate-90
[15:57:37] [PASSED] rotate-180
[15:57:37] [PASSED] rotate-270
[15:57:37] ============ [PASSED] drm_test_rect_rotate_inv =============
[15:57:37] ==================== [PASSED] drm_rect =====================
[15:57:37] ============ drm_sysfb_modeset_test (1 subtest) ============
[15:57:37] ============ drm_test_sysfb_build_fourcc_list =============
[15:57:37] [PASSED] no native formats
[15:57:37] [PASSED] XRGB8888 as native format
[15:57:37] [PASSED] remove duplicates
[15:57:37] [PASSED] convert alpha formats
[15:57:37] [PASSED] random formats
[15:57:37] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[15:57:37] ============= [PASSED] drm_sysfb_modeset_test ==============
[15:57:37] ================== drm_fixp (2 subtests) ===================
[15:57:37] [PASSED] drm_test_int2fixp
[15:57:37] [PASSED] drm_test_sm2fixp
[15:57:37] ==================== [PASSED] drm_fixp =====================
[15:57:37] ============================================================
[15:57:37] Testing complete. Ran 630 tests: passed: 630
[15:57:37] Elapsed time: 27.393s total, 1.586s configuring, 25.340s building, 0.434s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[15:57:37] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:57:38] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:57:48] Starting KUnit Kernel (1/1)...
[15:57:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:57:48] ================= ttm_device (5 subtests) ==================
[15:57:48] [PASSED] ttm_device_init_basic
[15:57:48] [PASSED] ttm_device_init_multiple
[15:57:48] [PASSED] ttm_device_fini_basic
[15:57:48] [PASSED] ttm_device_init_no_vma_man
[15:57:48] ================== ttm_device_init_pools ==================
[15:57:48] [PASSED] No DMA allocations, no DMA32 required
[15:57:48] [PASSED] DMA allocations, DMA32 required
[15:57:48] [PASSED] No DMA allocations, DMA32 required
[15:57:48] [PASSED] DMA allocations, no DMA32 required
[15:57:48] ============== [PASSED] ttm_device_init_pools ==============
[15:57:48] =================== [PASSED] ttm_device ====================
[15:57:48] ================== ttm_pool (8 subtests) ===================
[15:57:48] ================== ttm_pool_alloc_basic ===================
[15:57:48] [PASSED] One page
[15:57:48] [PASSED] More than one page
[15:57:48] [PASSED] Above the allocation limit
[15:57:48] [PASSED] One page, with coherent DMA mappings enabled
[15:57:48] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[15:57:48] ============== [PASSED] ttm_pool_alloc_basic ===============
[15:57:48] ============== ttm_pool_alloc_basic_dma_addr ==============
[15:57:48] [PASSED] One page
[15:57:48] [PASSED] More than one page
[15:57:48] [PASSED] Above the allocation limit
[15:57:48] [PASSED] One page, with coherent DMA mappings enabled
[15:57:48] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[15:57:48] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[15:57:48] [PASSED] ttm_pool_alloc_order_caching_match
[15:57:48] [PASSED] ttm_pool_alloc_caching_mismatch
[15:57:48] [PASSED] ttm_pool_alloc_order_mismatch
[15:57:48] [PASSED] ttm_pool_free_dma_alloc
[15:57:48] [PASSED] ttm_pool_free_no_dma_alloc
[15:57:48] [PASSED] ttm_pool_fini_basic
[15:57:48] ==================== [PASSED] ttm_pool =====================
[15:57:48] ================ ttm_resource (8 subtests) =================
[15:57:48] ================= ttm_resource_init_basic =================
[15:57:48] [PASSED] Init resource in TTM_PL_SYSTEM
[15:57:48] [PASSED] Init resource in TTM_PL_VRAM
[15:57:48] [PASSED] Init resource in a private placement
[15:57:48] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[15:57:48] ============= [PASSED] ttm_resource_init_basic =============
[15:57:48] [PASSED] ttm_resource_init_pinned
[15:57:48] [PASSED] ttm_resource_fini_basic
[15:57:48] [PASSED] ttm_resource_manager_init_basic
[15:57:48] [PASSED] ttm_resource_manager_usage_basic
[15:57:48] [PASSED] ttm_resource_manager_set_used_basic
[15:57:48] [PASSED] ttm_sys_man_alloc_basic
[15:57:48] [PASSED] ttm_sys_man_free_basic
[15:57:48] ================== [PASSED] ttm_resource ===================
[15:57:48] =================== ttm_tt (15 subtests) ===================
[15:57:48] ==================== ttm_tt_init_basic ====================
[15:57:48] [PASSED] Page-aligned size
[15:57:48] [PASSED] Extra pages requested
[15:57:48] ================ [PASSED] ttm_tt_init_basic ================
[15:57:48] [PASSED] ttm_tt_init_misaligned
[15:57:48] [PASSED] ttm_tt_fini_basic
[15:57:48] [PASSED] ttm_tt_fini_sg
[15:57:48] [PASSED] ttm_tt_fini_shmem
[15:57:48] [PASSED] ttm_tt_create_basic
[15:57:48] [PASSED] ttm_tt_create_invalid_bo_type
[15:57:48] [PASSED] ttm_tt_create_ttm_exists
[15:57:48] [PASSED] ttm_tt_create_failed
[15:57:48] [PASSED] ttm_tt_destroy_basic
[15:57:48] [PASSED] ttm_tt_populate_null_ttm
[15:57:48] [PASSED] ttm_tt_populate_populated_ttm
[15:57:48] [PASSED] ttm_tt_unpopulate_basic
[15:57:48] [PASSED] ttm_tt_unpopulate_empty_ttm
[15:57:48] [PASSED] ttm_tt_swapin_basic
[15:57:48] ===================== [PASSED] ttm_tt ======================
[15:57:48] =================== ttm_bo (14 subtests) ===================
[15:57:48] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[15:57:48] [PASSED] Cannot be interrupted and sleeps
[15:57:48] [PASSED] Cannot be interrupted, locks straight away
[15:57:48] [PASSED] Can be interrupted, sleeps
[15:57:48] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[15:57:48] [PASSED] ttm_bo_reserve_locked_no_sleep
[15:57:48] [PASSED] ttm_bo_reserve_no_wait_ticket
[15:57:48] [PASSED] ttm_bo_reserve_double_resv
[15:57:48] [PASSED] ttm_bo_reserve_interrupted
[15:57:48] [PASSED] ttm_bo_reserve_deadlock
[15:57:48] [PASSED] ttm_bo_unreserve_basic
[15:57:48] [PASSED] ttm_bo_unreserve_pinned
[15:57:48] [PASSED] ttm_bo_unreserve_bulk
[15:57:48] [PASSED] ttm_bo_fini_basic
[15:57:48] [PASSED] ttm_bo_fini_shared_resv
[15:57:48] [PASSED] ttm_bo_pin_basic
[15:57:48] [PASSED] ttm_bo_pin_unpin_resource
[15:57:48] [PASSED] ttm_bo_multiple_pin_one_unpin
[15:57:48] ===================== [PASSED] ttm_bo ======================
[15:57:48] ============== ttm_bo_validate (21 subtests) ===============
[15:57:48] ============== ttm_bo_init_reserved_sys_man ===============
[15:57:48] [PASSED] Buffer object for userspace
[15:57:48] [PASSED] Kernel buffer object
[15:57:48] [PASSED] Shared buffer object
[15:57:48] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[15:57:48] ============== ttm_bo_init_reserved_mock_man ==============
[15:57:48] [PASSED] Buffer object for userspace
[15:57:48] [PASSED] Kernel buffer object
[15:57:48] [PASSED] Shared buffer object
[15:57:48] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[15:57:48] [PASSED] ttm_bo_init_reserved_resv
[15:57:48] ================== ttm_bo_validate_basic ==================
[15:57:48] [PASSED] Buffer object for userspace
[15:57:48] [PASSED] Kernel buffer object
[15:57:48] [PASSED] Shared buffer object
[15:57:48] ============== [PASSED] ttm_bo_validate_basic ==============
[15:57:48] [PASSED] ttm_bo_validate_invalid_placement
[15:57:48] ============= ttm_bo_validate_same_placement ==============
[15:57:48] [PASSED] System manager
[15:57:48] [PASSED] VRAM manager
[15:57:48] ========= [PASSED] ttm_bo_validate_same_placement ==========
[15:57:48] [PASSED] ttm_bo_validate_failed_alloc
[15:57:48] [PASSED] ttm_bo_validate_pinned
[15:57:48] [PASSED] ttm_bo_validate_busy_placement
[15:57:48] ================ ttm_bo_validate_multihop =================
[15:57:48] [PASSED] Buffer object for userspace
[15:57:48] [PASSED] Kernel buffer object
[15:57:48] [PASSED] Shared buffer object
[15:57:48] ============ [PASSED] ttm_bo_validate_multihop =============
[15:57:48] ========== ttm_bo_validate_no_placement_signaled ==========
[15:57:48] [PASSED] Buffer object in system domain, no page vector
[15:57:48] [PASSED] Buffer object in system domain with an existing page vector
[15:57:48] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[15:57:48] ======== ttm_bo_validate_no_placement_not_signaled ========
[15:57:48] [PASSED] Buffer object for userspace
[15:57:48] [PASSED] Kernel buffer object
[15:57:48] [PASSED] Shared buffer object
[15:57:48] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[15:57:48] [PASSED] ttm_bo_validate_move_fence_signaled
[15:57:48] ========= ttm_bo_validate_move_fence_not_signaled =========
[15:57:48] [PASSED] Waits for GPU
[15:57:48] [PASSED] Tries to lock straight away
[15:57:48] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[15:57:48] [PASSED] ttm_bo_validate_happy_evict
[15:57:48] [PASSED] ttm_bo_validate_all_pinned_evict
[15:57:48] [PASSED] ttm_bo_validate_allowed_only_evict
[15:57:48] [PASSED] ttm_bo_validate_deleted_evict
[15:57:48] [PASSED] ttm_bo_validate_busy_domain_evict
[15:57:48] [PASSED] ttm_bo_validate_evict_gutting
[15:57:48] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[15:57:48] ================= [PASSED] ttm_bo_validate =================
[15:57:48] ============================================================
[15:57:48] Testing complete. Ran 101 tests: passed: 101
[15:57:48] Elapsed time: 11.503s total, 1.658s configuring, 9.579s building, 0.229s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✓ Xe.CI.BAT: success for drm/i915/power_well: Enable workaround for DSS clock gating issue (22021048059)
2026-01-28 7:48 [PATCH] drm/i915/power_well: Enable workaround for DSS clock gating issue (22021048059) Mika Kahola
2026-01-28 10:36 ` Jani Nikula
2026-01-28 15:57 ` ✓ CI.KUnit: success for " Patchwork
@ 2026-01-28 16:32 ` Patchwork
2026-01-29 3:11 ` [PATCH] " Kandpal, Suraj
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2026-01-28 16:32 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 1956 bytes --]
== Series Details ==
Series: drm/i915/power_well: Enable workaround for DSS clock gating issue (22021048059)
URL : https://patchwork.freedesktop.org/series/160740/
State : success
== Summary ==
CI Bug Log - changes from xe-4465-8059f097e25f736bb3da09af6a9b283079abfd4f_BAT -> xe-pw-160740v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (11 -> 12)
------------------------------
Additional (1): bat-bmg-3
Known issues
------------
Here are the changes found in xe-pw-160740v1_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@xe_peer2peer@read@read-gpua-vram01-gpub-vram01-p2p:
- bat-bmg-3: NOTRUN -> [SKIP][1] ([Intel XE#6566]) +3 other tests skip
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160740v1/bat-bmg-3/igt@xe_peer2peer@read@read-gpua-vram01-gpub-vram01-p2p.html
#### Possible fixes ####
* igt@xe_waitfence@engine:
- bat-dg2-oem2: [FAIL][2] ([Intel XE#6519]) -> [PASS][3]
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4465-8059f097e25f736bb3da09af6a9b283079abfd4f/bat-dg2-oem2/igt@xe_waitfence@engine.html
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160740v1/bat-dg2-oem2/igt@xe_waitfence@engine.html
[Intel XE#6519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6519
[Intel XE#6566]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6566
Build changes
-------------
* IGT: IGT_8721 -> IGT_8722
* Linux: xe-4465-8059f097e25f736bb3da09af6a9b283079abfd4f -> xe-pw-160740v1
IGT_8721: 3707bb4267de22a18d61b232c4ab5fbaf61db90c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_8722: 8722
xe-4465-8059f097e25f736bb3da09af6a9b283079abfd4f: 8059f097e25f736bb3da09af6a9b283079abfd4f
xe-pw-160740v1: 160740v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160740v1/index.html
[-- Attachment #2: Type: text/html, Size: 2556 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH] drm/i915/power_well: Enable workaround for DSS clock gating issue (22021048059)
2026-01-28 7:48 [PATCH] drm/i915/power_well: Enable workaround for DSS clock gating issue (22021048059) Mika Kahola
` (2 preceding siblings ...)
2026-01-28 16:32 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-01-29 3:11 ` Kandpal, Suraj
2026-01-30 10:03 ` Kahola, Mika
3 siblings, 1 reply; 7+ messages in thread
From: Kandpal, Suraj @ 2026-01-29 3:11 UTC (permalink / raw)
To: Kahola, Mika, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Kahola, Mika
> Subject: [PATCH] drm/i915/power_well: Enable workaround for DSS clock
> gating issue (22021048059)
You don't need to mention the WA no in the subject since you describe what you are doing in the patch
>
> Prevent display corruption observed after restart, hotplug, or unplug
> operations on Meteor Lake and newer platforms. The issue is caused by DSS
> clock gating affecting DSC logic when pipe power wells are disabled.
>
> Apply WA 22021048059 by disabling DSS clock gating for the affected pipes
Also no need to mention it here since you have mentioned the WA no. in the trailer
Regards,
Suraj Kandpal
> before turning off their power wells. This avoids DSC corruption on external
> displays.
>
> WA: 22021048059
> BSpec: 690991, 666241
>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> .../i915/display/intel_display_power_well.c | 78 ++++++++++++++++++-
> .../gpu/drm/i915/display/intel_display_regs.h | 7 ++
> .../gpu/drm/i915/display/intel_display_wa.c | 2 +
> .../gpu/drm/i915/display/intel_display_wa.h | 1 +
> 4 files changed, 86 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 6f9bc6f9615e..1ef450f26879 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -14,10 +14,13 @@
> #include "intel_crt.h"
> #include "intel_de.h"
> #include "intel_display_irq.h"
> +#include "intel_display_limits.h"
> #include "intel_display_power_well.h"
> #include "intel_display_regs.h"
> #include "intel_display_rpm.h"
> #include "intel_display_types.h"
> +#include "intel_display_utils.h"
> +#include "intel_display_wa.h"
> #include "intel_dkl_phy.h"
> #include "intel_dkl_phy_regs.h"
> #include "intel_dmc.h"
> @@ -194,6 +197,69 @@ int intel_power_well_refcount(struct
> i915_power_well *power_well)
> return power_well->count;
> }
>
> +static void clock_gating_dss_enable_disable(struct intel_display *display,
> + u8 irq_pipe_mask,
> + bool disable)
> +{
> + struct drm_printer p;
> + enum pipe pipe;
> +
> + switch (irq_pipe_mask) {
> + case BIT(PIPE_A):
> + pipe = PIPE_A;
> +
> + if (disable)
> + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> + 0, DSS_PIPE_A_GATING_DISABLED);
> + else
> + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> + DSS_PIPE_A_GATING_DISABLED, 0);
> + break;
> + case BIT(PIPE_B):
> + pipe = PIPE_B;
> +
> + if (disable)
> + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> + 0, DSS_PIPE_B_GATING_DISABLED);
> + else
> + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> + DSS_PIPE_B_GATING_DISABLED, 0);
> + break;
> + case BIT(PIPE_C):
> + pipe = PIPE_C;
> +
> + if (disable)
> + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> + 0, DSS_PIPE_C_GATING_DISABLED);
> + else
> + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> + DSS_PIPE_C_GATING_DISABLED, 0);
> + break;
> + case BIT(PIPE_D):
> + pipe = PIPE_D;
> +
> + if (disable)
> + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> + 0, DSS_PIPE_D_GATING_DISABLED);
> + else
> + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> + DSS_PIPE_D_GATING_DISABLED, 0);
> + break;
> + default:
> + MISSING_CASE(irq_pipe_mask);
> + break;
> + }
> +
> + if (!drm_debug_enabled(DRM_UT_KMS))
> + return;
> +
> + p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
> +
> + drm_printf(&p, "dss clock gating %sd on pipe %c (0x%.8x)\n",
> + str_enable_disable(!disable), pipe_name(pipe),
> + intel_de_read(display, CLKGATE_DIS_DSSDSC)); }
> +
> /*
> * Starting with Haswell, we have a "Power Down Well" that can be turned off
> * when not needed anymore. We have 4 registers that can request the
> power well @@ -203,15 +269,23 @@ int intel_power_well_refcount(struct
> i915_power_well *power_well) static void
> hsw_power_well_post_enable(struct intel_display *display,
> u8 irq_pipe_mask)
> {
> - if (irq_pipe_mask)
> + if (irq_pipe_mask) {
> gen8_irq_power_well_post_enable(display, irq_pipe_mask);
> +
> + if (intel_display_wa(display, 22021048059))
> + clock_gating_dss_enable_disable(display,
> irq_pipe_mask, false);
> + }
> }
>
> static void hsw_power_well_pre_disable(struct intel_display *display,
> u8 irq_pipe_mask)
> {
> - if (irq_pipe_mask)
> + if (irq_pipe_mask) {
> + if (intel_display_wa(display, 22021048059))
> + clock_gating_dss_enable_disable(display,
> irq_pipe_mask, true);
> +
> gen8_irq_power_well_pre_disable(display, irq_pipe_mask);
> + }
> }
>
> #define ICL_AUX_PW_TO_PHY(pw_idx) \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 9e0d853f4b61..9740f32ced24 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -2211,6 +2211,13 @@
> #define HSW_PWR_WELL_FORCE_ON (1 << 19)
> #define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
>
> +/* clock gating DSS DSC disable register */
> +#define CLKGATE_DIS_DSSDSC _MMIO(0x46548)
> +#define DSS_PIPE_D_GATING_DISABLED REG_BIT(31)
> +#define DSS_PIPE_C_GATING_DISABLED REG_BIT(29)
> +#define DSS_PIPE_B_GATING_DISABLED REG_BIT(27)
> +#define DSS_PIPE_A_GATING_DISABLED REG_BIT(25)
> +
> /* SKL Fuse Status */
> enum skl_power_gate {
> SKL_PG0,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c
> b/drivers/gpu/drm/i915/display/intel_display_wa.c
> index 86a6cc45b6ab..f8e14aa34dae 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_wa.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
> @@ -84,6 +84,8 @@ bool __intel_display_wa(struct intel_display *display,
> enum intel_display_wa wa,
> return intel_display_needs_wa_16025573575(display);
> case INTEL_DISPLAY_WA_22014263786:
> return IS_DISPLAY_VERx100(display, 1100, 1400);
> + case INTEL_DISPLAY_WA_22021048059:
> + return DISPLAY_VER(display) >= 14;
> default:
> drm_WARN(display->drm, 1, "Missing Wa number: %s\n",
> name);
> break;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h
> b/drivers/gpu/drm/i915/display/intel_display_wa.h
> index 40f989f19df1..767420d5f406 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_wa.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
> @@ -34,6 +34,7 @@ enum intel_display_wa {
> INTEL_DISPLAY_WA_16023588340,
> INTEL_DISPLAY_WA_16025573575,
> INTEL_DISPLAY_WA_22014263786,
> + INTEL_DISPLAY_WA_22021048059,
> };
>
> bool __intel_display_wa(struct intel_display *display, enum intel_display_wa
> wa, const char *name);
> --
> 2.43.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH] drm/i915/power_well: Enable workaround for DSS clock gating issue (22021048059)
2026-01-28 10:36 ` Jani Nikula
@ 2026-01-30 10:02 ` Kahola, Mika
0 siblings, 0 replies; 7+ messages in thread
From: Kahola, Mika @ 2026-01-30 10:02 UTC (permalink / raw)
To: Jani Nikula, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Wednesday, 28 January 2026 12.37
> To: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>
> Subject: Re: [PATCH] drm/i915/power_well: Enable workaround for DSS clock gating issue (22021048059)
>
> On Wed, 28 Jan 2026, Mika Kahola <mika.kahola@intel.com> wrote:
> > Prevent display corruption observed after restart, hotplug, or unplug
> > operations on Meteor Lake and newer platforms. The issue is caused by
> > DSS clock gating affecting DSC logic when pipe power wells are disabled.
> >
> > Apply WA 22021048059 by disabling DSS clock gating for the affected
> > pipes before turning off their power wells. This avoids DSC corruption
> > on external displays.
> >
> > WA: 22021048059
> > BSpec: 690991, 666241
> >
>
> Superfluous blank line. The git commit trailers belong together.
Ok, I'll remove this blank line
>
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> > .../i915/display/intel_display_power_well.c | 78 ++++++++++++++++++-
> > .../gpu/drm/i915/display/intel_display_regs.h | 7 ++
> > .../gpu/drm/i915/display/intel_display_wa.c | 2 +
> > .../gpu/drm/i915/display/intel_display_wa.h | 1 +
> > 4 files changed, 86 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > index 6f9bc6f9615e..1ef450f26879 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > @@ -14,10 +14,13 @@
> > #include "intel_crt.h"
> > #include "intel_de.h"
> > #include "intel_display_irq.h"
> > +#include "intel_display_limits.h"
> > #include "intel_display_power_well.h"
> > #include "intel_display_regs.h"
> > #include "intel_display_rpm.h"
> > #include "intel_display_types.h"
> > +#include "intel_display_utils.h"
> > +#include "intel_display_wa.h"
> > #include "intel_dkl_phy.h"
> > #include "intel_dkl_phy_regs.h"
> > #include "intel_dmc.h"
> > @@ -194,6 +197,69 @@ int intel_power_well_refcount(struct i915_power_well *power_well)
> > return power_well->count;
> > }
> >
> > +static void clock_gating_dss_enable_disable(struct intel_display *display,
> > + u8 irq_pipe_mask,
> > + bool disable)
> > +{
> > + struct drm_printer p;
> > + enum pipe pipe;
> > +
> > + switch (irq_pipe_mask) {
> > + case BIT(PIPE_A):
> > + pipe = PIPE_A;
> > +
> > + if (disable)
> > + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> > + 0, DSS_PIPE_A_GATING_DISABLED);
> > + else
> > + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> > + DSS_PIPE_A_GATING_DISABLED, 0);
> > + break;
> > + case BIT(PIPE_B):
> > + pipe = PIPE_B;
> > +
> > + if (disable)
> > + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> > + 0, DSS_PIPE_B_GATING_DISABLED);
> > + else
> > + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> > + DSS_PIPE_B_GATING_DISABLED, 0);
> > + break;
> > + case BIT(PIPE_C):
> > + pipe = PIPE_C;
> > +
> > + if (disable)
> > + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> > + 0, DSS_PIPE_C_GATING_DISABLED);
> > + else
> > + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> > + DSS_PIPE_C_GATING_DISABLED, 0);
> > + break;
> > + case BIT(PIPE_D):
> > + pipe = PIPE_D;
> > +
> > + if (disable)
> > + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> > + 0, DSS_PIPE_D_GATING_DISABLED);
> > + else
> > + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> > + DSS_PIPE_D_GATING_DISABLED, 0);
> > + break;
> > + default:
> > + MISSING_CASE(irq_pipe_mask);
> > + break;
> > + }
>
> irq_pipe_mask implies it can have multiple pipes set. That will lead to a warning here. Does this need to use
> for_each_pipe_masked() instead?
>
> The whole thing is awfully verbose as well. Perhaps figure out the bits to set/unset based on the pipes, and have just one
> intel_de_rmw() statement?
Let me rephrase this. I will try to simplify this such that only one intel_de_rmw() call will be used.
>
> > +
> > + if (!drm_debug_enabled(DRM_UT_KMS))
> > + return;
>
> This is redundant.
>
> > +
> > + p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
> > +
> > + drm_printf(&p, "dss clock gating %sd on pipe %c (0x%.8x)\n",
> > + str_enable_disable(!disable), pipe_name(pipe),
> > + intel_de_read(display, CLKGATE_DIS_DSSDSC));
>
> Using a printer is overkill for one line. This should just be a drm_dbg_kms().
I had an impression that drm_printf() would be a preferred way but nice to hear that drm_dbg_kms() is still going strong.
I will switch to use that instead of drm_printf().
Thanks for the comments and review!
-Mika-
>
> And this also assumes just one pipe.
>
> BR,
> Jani.
>
>
> > +}
> > +
> > /*
> > * Starting with Haswell, we have a "Power Down Well" that can be turned off
> > * when not needed anymore. We have 4 registers that can request the
> > power well @@ -203,15 +269,23 @@ int intel_power_well_refcount(struct
> > i915_power_well *power_well) static void hsw_power_well_post_enable(struct intel_display *display,
> > u8 irq_pipe_mask)
> > {
> > - if (irq_pipe_mask)
> > + if (irq_pipe_mask) {
> > gen8_irq_power_well_post_enable(display, irq_pipe_mask);
> > +
> > + if (intel_display_wa(display, 22021048059))
> > + clock_gating_dss_enable_disable(display, irq_pipe_mask, false);
> > + }
> > }
> >
> > static void hsw_power_well_pre_disable(struct intel_display *display,
> > u8 irq_pipe_mask)
> > {
> > - if (irq_pipe_mask)
> > + if (irq_pipe_mask) {
> > + if (intel_display_wa(display, 22021048059))
> > + clock_gating_dss_enable_disable(display, irq_pipe_mask, true);
> > +
> > gen8_irq_power_well_pre_disable(display, irq_pipe_mask);
> > + }
> > }
> >
> > #define ICL_AUX_PW_TO_PHY(pw_idx) \
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 9e0d853f4b61..9740f32ced24 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -2211,6 +2211,13 @@
> > #define HSW_PWR_WELL_FORCE_ON (1 << 19)
> > #define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
> >
> > +/* clock gating DSS DSC disable register */
> > +#define CLKGATE_DIS_DSSDSC _MMIO(0x46548)
> > +#define DSS_PIPE_D_GATING_DISABLED REG_BIT(31)
> > +#define DSS_PIPE_C_GATING_DISABLED REG_BIT(29)
> > +#define DSS_PIPE_B_GATING_DISABLED REG_BIT(27)
> > +#define DSS_PIPE_A_GATING_DISABLED REG_BIT(25)
> > +
> > /* SKL Fuse Status */
> > enum skl_power_gate {
> > SKL_PG0,
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c
> > b/drivers/gpu/drm/i915/display/intel_display_wa.c
> > index 86a6cc45b6ab..f8e14aa34dae 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_wa.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
> > @@ -84,6 +84,8 @@ bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa,
> > return intel_display_needs_wa_16025573575(display);
> > case INTEL_DISPLAY_WA_22014263786:
> > return IS_DISPLAY_VERx100(display, 1100, 1400);
> > + case INTEL_DISPLAY_WA_22021048059:
> > + return DISPLAY_VER(display) >= 14;
> > default:
> > drm_WARN(display->drm, 1, "Missing Wa number: %s\n", name);
> > break;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h
> > b/drivers/gpu/drm/i915/display/intel_display_wa.h
> > index 40f989f19df1..767420d5f406 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_wa.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
> > @@ -34,6 +34,7 @@ enum intel_display_wa {
> > INTEL_DISPLAY_WA_16023588340,
> > INTEL_DISPLAY_WA_16025573575,
> > INTEL_DISPLAY_WA_22014263786,
> > + INTEL_DISPLAY_WA_22021048059,
> > };
> >
> > bool __intel_display_wa(struct intel_display *display, enum
> > intel_display_wa wa, const char *name);
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH] drm/i915/power_well: Enable workaround for DSS clock gating issue (22021048059)
2026-01-29 3:11 ` [PATCH] " Kandpal, Suraj
@ 2026-01-30 10:03 ` Kahola, Mika
0 siblings, 0 replies; 7+ messages in thread
From: Kahola, Mika @ 2026-01-30 10:03 UTC (permalink / raw)
To: Kandpal, Suraj, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Thursday, 29 January 2026 5.11
> To: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>
> Subject: RE: [PATCH] drm/i915/power_well: Enable workaround for DSS clock gating issue (22021048059)
>
> > Subject: [PATCH] drm/i915/power_well: Enable workaround for DSS clock
> > gating issue (22021048059)
>
> You don’t need to mention the WA no in the subject since you describe what you are doing in the patch
I will drop all mentions of WA number except the one in trailer.
Thanks for the review & comments!
-Mika-
>
> >
> > Prevent display corruption observed after restart, hotplug, or unplug
> > operations on Meteor Lake and newer platforms. The issue is caused by
> > DSS clock gating affecting DSC logic when pipe power wells are disabled.
> >
> > Apply WA 22021048059 by disabling DSS clock gating for the affected
> > pipes
>
> Also no need to mention it here since you have mentioned the WA no. in the trailer
>
> Regards,
> Suraj Kandpal
>
> > before turning off their power wells. This avoids DSC corruption on
> > external displays.
> >
> > WA: 22021048059
> > BSpec: 690991, 666241
> >
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> > .../i915/display/intel_display_power_well.c | 78 ++++++++++++++++++-
> > .../gpu/drm/i915/display/intel_display_regs.h | 7 ++
> > .../gpu/drm/i915/display/intel_display_wa.c | 2 +
> > .../gpu/drm/i915/display/intel_display_wa.h | 1 +
> > 4 files changed, 86 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > index 6f9bc6f9615e..1ef450f26879 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > @@ -14,10 +14,13 @@
> > #include "intel_crt.h"
> > #include "intel_de.h"
> > #include "intel_display_irq.h"
> > +#include "intel_display_limits.h"
> > #include "intel_display_power_well.h"
> > #include "intel_display_regs.h"
> > #include "intel_display_rpm.h"
> > #include "intel_display_types.h"
> > +#include "intel_display_utils.h"
> > +#include "intel_display_wa.h"
> > #include "intel_dkl_phy.h"
> > #include "intel_dkl_phy_regs.h"
> > #include "intel_dmc.h"
> > @@ -194,6 +197,69 @@ int intel_power_well_refcount(struct
> > i915_power_well *power_well)
> > return power_well->count;
> > }
> >
> > +static void clock_gating_dss_enable_disable(struct intel_display *display,
> > + u8 irq_pipe_mask,
> > + bool disable)
> > +{
> > + struct drm_printer p;
> > + enum pipe pipe;
> > +
> > + switch (irq_pipe_mask) {
> > + case BIT(PIPE_A):
> > + pipe = PIPE_A;
> > +
> > + if (disable)
> > + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> > + 0, DSS_PIPE_A_GATING_DISABLED);
> > + else
> > + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> > + DSS_PIPE_A_GATING_DISABLED, 0);
> > + break;
> > + case BIT(PIPE_B):
> > + pipe = PIPE_B;
> > +
> > + if (disable)
> > + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> > + 0, DSS_PIPE_B_GATING_DISABLED);
> > + else
> > + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> > + DSS_PIPE_B_GATING_DISABLED, 0);
> > + break;
> > + case BIT(PIPE_C):
> > + pipe = PIPE_C;
> > +
> > + if (disable)
> > + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> > + 0, DSS_PIPE_C_GATING_DISABLED);
> > + else
> > + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> > + DSS_PIPE_C_GATING_DISABLED, 0);
> > + break;
> > + case BIT(PIPE_D):
> > + pipe = PIPE_D;
> > +
> > + if (disable)
> > + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> > + 0, DSS_PIPE_D_GATING_DISABLED);
> > + else
> > + intel_de_rmw(display, CLKGATE_DIS_DSSDSC,
> > + DSS_PIPE_D_GATING_DISABLED, 0);
> > + break;
> > + default:
> > + MISSING_CASE(irq_pipe_mask);
> > + break;
> > + }
> > +
> > + if (!drm_debug_enabled(DRM_UT_KMS))
> > + return;
> > +
> > + p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
> > +
> > + drm_printf(&p, "dss clock gating %sd on pipe %c (0x%.8x)\n",
> > + str_enable_disable(!disable), pipe_name(pipe),
> > + intel_de_read(display, CLKGATE_DIS_DSSDSC)); }
> > +
> > /*
> > * Starting with Haswell, we have a "Power Down Well" that can be turned off
> > * when not needed anymore. We have 4 registers that can request the
> > power well @@ -203,15 +269,23 @@ int intel_power_well_refcount(struct
> > i915_power_well *power_well) static void
> > hsw_power_well_post_enable(struct intel_display *display,
> > u8 irq_pipe_mask)
> > {
> > - if (irq_pipe_mask)
> > + if (irq_pipe_mask) {
> > gen8_irq_power_well_post_enable(display, irq_pipe_mask);
> > +
> > + if (intel_display_wa(display, 22021048059))
> > + clock_gating_dss_enable_disable(display,
> > irq_pipe_mask, false);
> > + }
> > }
> >
> > static void hsw_power_well_pre_disable(struct intel_display *display,
> > u8 irq_pipe_mask)
> > {
> > - if (irq_pipe_mask)
> > + if (irq_pipe_mask) {
> > + if (intel_display_wa(display, 22021048059))
> > + clock_gating_dss_enable_disable(display,
> > irq_pipe_mask, true);
> > +
> > gen8_irq_power_well_pre_disable(display, irq_pipe_mask);
> > + }
> > }
> >
> > #define ICL_AUX_PW_TO_PHY(pw_idx) \
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 9e0d853f4b61..9740f32ced24 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -2211,6 +2211,13 @@
> > #define HSW_PWR_WELL_FORCE_ON (1 << 19)
> > #define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
> >
> > +/* clock gating DSS DSC disable register */
> > +#define CLKGATE_DIS_DSSDSC _MMIO(0x46548)
> > +#define DSS_PIPE_D_GATING_DISABLED REG_BIT(31)
> > +#define DSS_PIPE_C_GATING_DISABLED REG_BIT(29)
> > +#define DSS_PIPE_B_GATING_DISABLED REG_BIT(27)
> > +#define DSS_PIPE_A_GATING_DISABLED REG_BIT(25)
> > +
> > /* SKL Fuse Status */
> > enum skl_power_gate {
> > SKL_PG0,
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c
> > b/drivers/gpu/drm/i915/display/intel_display_wa.c
> > index 86a6cc45b6ab..f8e14aa34dae 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_wa.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
> > @@ -84,6 +84,8 @@ bool __intel_display_wa(struct intel_display
> > *display, enum intel_display_wa wa,
> > return intel_display_needs_wa_16025573575(display);
> > case INTEL_DISPLAY_WA_22014263786:
> > return IS_DISPLAY_VERx100(display, 1100, 1400);
> > + case INTEL_DISPLAY_WA_22021048059:
> > + return DISPLAY_VER(display) >= 14;
> > default:
> > drm_WARN(display->drm, 1, "Missing Wa number: %s\n", name);
> > break;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h
> > b/drivers/gpu/drm/i915/display/intel_display_wa.h
> > index 40f989f19df1..767420d5f406 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_wa.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
> > @@ -34,6 +34,7 @@ enum intel_display_wa {
> > INTEL_DISPLAY_WA_16023588340,
> > INTEL_DISPLAY_WA_16025573575,
> > INTEL_DISPLAY_WA_22014263786,
> > + INTEL_DISPLAY_WA_22021048059,
> > };
> >
> > bool __intel_display_wa(struct intel_display *display, enum
> > intel_display_wa wa, const char *name);
> > --
> > 2.43.0
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2026-01-30 10:03 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2026-01-28 7:48 [PATCH] drm/i915/power_well: Enable workaround for DSS clock gating issue (22021048059) Mika Kahola
2026-01-28 10:36 ` Jani Nikula
2026-01-30 10:02 ` Kahola, Mika
2026-01-28 15:57 ` ✓ CI.KUnit: success for " Patchwork
2026-01-28 16:32 ` ✓ Xe.CI.BAT: " Patchwork
2026-01-29 3:11 ` [PATCH] " Kandpal, Suraj
2026-01-30 10:03 ` Kahola, Mika
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