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* [PATCH CI] drm/i915/cx0: Fix port to PLL ID mapping on BMG
@ 2025-11-20  7:38 Imre Deak
  2025-11-20  8:11 ` ✗ CI.checkpatch: warning for " Patchwork
                   ` (5 more replies)
  0 siblings, 6 replies; 7+ messages in thread
From: Imre Deak @ 2025-11-20  7:38 UTC (permalink / raw)
  To: intel-xe

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      | 7 ++++---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 9 +++++----
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 96fcad6dbb2f4..8471bdab5c62f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4294,9 +4294,10 @@ static void mtl_ddi_cx0_get_config(struct intel_encoder *encoder,
 }
 
 /*
- * Get the configuration for either a port using a C10 PHY PLL, or in the case of
- * the PTL port B eDP on TypeC PHY case the configuration of a port using a C20
- * PHY PLL.
+ * Get the configuration for either a port using a C10 PHY PLL, or a port using a
+ * C20 PHY PLL in the cases of:
+ * - BMG port A/B
+ * - PTL port B eDP over TypeC PHY
  */
 static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder,
 					     struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 6d7d5394713d6..8ae8cc7ad79d3 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -206,7 +206,7 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
 enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port port)
 {
 	if (port >= PORT_TC1)
-		return icl_tc_port_to_pll_id(intel_port_to_tc(display, port));
+		return icl_tc_port_to_pll_id(port - PORT_TC1 + TC_PORT_1);
 
 	switch (port) {
 	case PORT_A:
@@ -3507,9 +3507,10 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
 }
 
 /*
- * Get the PLL for either a port using a C10 PHY PLL, or in the
- * PTL port B eDP over TypeC PHY case, the PLL for a port using
- * a C20 PHY PLL.
+ * Get the PLL for either a port using a C10 PHY PLL, or for a port using a
+ * C20 PHY PLL in the cases of:
+ * - BMG port A/B
+ * - PTL port B eDP over TypeC PHY
  */
 static int mtl_get_non_tc_phy_dpll(struct intel_atomic_state *state,
 				      struct intel_crtc *crtc,
-- 
2.49.1


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Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-11-20  7:38 [PATCH CI] drm/i915/cx0: Fix port to PLL ID mapping on BMG Imre Deak
2025-11-20  8:11 ` ✗ CI.checkpatch: warning for " Patchwork
2025-11-20  8:12 ` ✓ CI.KUnit: success " Patchwork
2025-11-20  9:02 ` ✓ Xe.CI.BAT: " Patchwork
2025-11-20 11:32 ` ✗ Xe.CI.Full: failure " Patchwork
2025-11-20 12:54 ` [PATCH CI] " Kahola, Mika
2025-11-20 13:03 ` Jani Nikula

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