[PATCH 0/7] Fix a couple of wedge corner-case memory leaks

[PATCH 0/7] Fix a couple of wedge corner-case memory leaks

[Stuart Summers]

Most of the patches in this series are just adding
some debug hints to help track these down. I split
these up in case we want to pick and choose which ones
to include in the tree. I found them useful.

The main two interesting patches are the last two in the
series which are fixing some corner cases when the
driver becomes wedged in the middle of either communication
with the DRM scheduler or in the event the GuC becomes
unresponsive. In both of these cases there is a chance
we could leak memory around the exec queue members
like the LRC and the LRC BO. These patches fix those
scenarios.

Stuart Summers (7):
  drm/xe: Add additional trace points for LRCs
  drm/xe: Add a trace point for VM close
  drm/xe: Add the BO pointer info to the BO trace
  drm/xe: Add new exec queue trace points
  drm/xe: Handle missing migration VM on VM creation
  drm/xe: Don't send a CLEANUP message on sched pause
  drm/xe: Check for GuC responses on disabling scheduling

 drivers/gpu/drm/xe/xe_exec_queue.c |  7 +++++
 drivers/gpu/drm/xe/xe_guc_submit.c | 37 +++++++++++++++++++++-----
 drivers/gpu/drm/xe/xe_lrc.c        |  4 +++
 drivers/gpu/drm/xe/xe_lrc.h        |  3 +++
 drivers/gpu/drm/xe/xe_trace.h      | 22 ++++++++++++++--
 drivers/gpu/drm/xe/xe_trace_bo.h   | 12 +++++++--
 drivers/gpu/drm/xe/xe_trace_lrc.h  | 42 +++++++++++++++++++++++++++++-
 drivers/gpu/drm/xe/xe_vm.c         |  2 ++
 8 files changed, 118 insertions(+), 11 deletions(-)

-- 
2.34.1

[PATCH 1/7] drm/xe: Add additional trace points for LRCs

[Stuart Summers]

Add trace points to indicate when an LRC has been
created and destroyed or get and put.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
 drivers/gpu/drm/xe/xe_lrc.c       |  4 +++
 drivers/gpu/drm/xe/xe_lrc.h       |  3 +++
 drivers/gpu/drm/xe/xe_trace_lrc.h | 42 ++++++++++++++++++++++++++++++-
 3 files changed, 48 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 47e9df775072..4c54f24b7a8f 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -1569,6 +1569,8 @@ struct xe_lrc *xe_lrc_create(struct xe_hw_engine *hwe, struct xe_vm *vm,
 		return ERR_PTR(err);
 	}
 
+	trace_xe_lrc_create(lrc);
+
 	return lrc;
 }
 
@@ -1583,6 +1585,8 @@ void xe_lrc_destroy(struct kref *ref)
 {
 	struct xe_lrc *lrc = container_of(ref, struct xe_lrc, refcount);
 
+	trace_xe_lrc_destroy(lrc);
+
 	xe_lrc_finish(lrc);
 	kfree(lrc);
 }
diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h
index 188565465779..8deb43b86f19 100644
--- a/drivers/gpu/drm/xe/xe_lrc.h
+++ b/drivers/gpu/drm/xe/xe_lrc.h
@@ -8,6 +8,7 @@
 #include <linux/types.h>
 
 #include "xe_lrc_types.h"
+#include "xe_trace_lrc.h"
 
 struct drm_printer;
 struct xe_bb;
@@ -59,6 +60,7 @@ void xe_lrc_destroy(struct kref *ref);
 static inline struct xe_lrc *xe_lrc_get(struct xe_lrc *lrc)
 {
 	kref_get(&lrc->refcount);
+	trace_xe_lrc_get(lrc);
 	return lrc;
 }
 
@@ -71,6 +73,7 @@ static inline struct xe_lrc *xe_lrc_get(struct xe_lrc *lrc)
  */
 static inline void xe_lrc_put(struct xe_lrc *lrc)
 {
+	trace_xe_lrc_put(lrc);
 	kref_put(&lrc->refcount, xe_lrc_destroy);
 }
 
diff --git a/drivers/gpu/drm/xe/xe_trace_lrc.h b/drivers/gpu/drm/xe/xe_trace_lrc.h
index d525cbee1e34..e8daa5d323e7 100644
--- a/drivers/gpu/drm/xe/xe_trace_lrc.h
+++ b/drivers/gpu/drm/xe/xe_trace_lrc.h
@@ -13,7 +13,6 @@
 #include <linux/types.h>
 
 #include "xe_gt_types.h"
-#include "xe_lrc.h"
 #include "xe_lrc_types.h"
 
 #define __dev_name_lrc(lrc)	dev_name(gt_to_xe((lrc)->fence_ctx.gt)->drm.dev)
@@ -42,6 +41,47 @@ TRACE_EVENT(xe_lrc_update_timestamp,
 		      __get_str(device_id))
 );
 
+DECLARE_EVENT_CLASS(xe_lrc,
+	    TP_PROTO(struct xe_lrc *lrc),
+	    TP_ARGS(lrc),
+
+	    TP_STRUCT__entry(
+		     __field(struct xe_lrc *, lrc)
+		     __string(name, lrc->fence_ctx.name)
+		     __string(device_id, __dev_name_lrc(lrc))
+	    ),
+
+	    TP_fast_assign(
+		   __entry->lrc	= lrc;
+		   __assign_str(name);
+		   __assign_str(device_id);
+		   ),
+
+	    TP_printk("lrc=:%p lrc->name=%s device_id:%s",
+		      __entry->lrc, __get_str(name),
+		      __get_str(device_id))
+);
+
+DEFINE_EVENT(xe_lrc, xe_lrc_create,
+	     TP_PROTO(struct xe_lrc *lrc),
+	     TP_ARGS(lrc)
+);
+
+DEFINE_EVENT(xe_lrc, xe_lrc_destroy,
+	     TP_PROTO(struct xe_lrc *lrc),
+	     TP_ARGS(lrc)
+);
+
+DEFINE_EVENT(xe_lrc, xe_lrc_get,
+	     TP_PROTO(struct xe_lrc *lrc),
+	     TP_ARGS(lrc)
+);
+
+DEFINE_EVENT(xe_lrc, xe_lrc_put,
+	     TP_PROTO(struct xe_lrc *lrc),
+	     TP_ARGS(lrc)
+);
+
 #endif
 
 /* This part must be outside protection */
-- 
2.34.1

[PATCH 2/7] drm/xe: Add a trace point for VM close

[Stuart Summers]

All better tracking of error cases when calling through
xe_vm_close_and_put().

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
 drivers/gpu/drm/xe/xe_trace_bo.h | 6 ++++++
 drivers/gpu/drm/xe/xe_vm.c       | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_trace_bo.h b/drivers/gpu/drm/xe/xe_trace_bo.h
index 86323cf3be2c..238311cfb816 100644
--- a/drivers/gpu/drm/xe/xe_trace_bo.h
+++ b/drivers/gpu/drm/xe/xe_trace_bo.h
@@ -14,6 +14,7 @@
 
 #include "xe_bo.h"
 #include "xe_bo_types.h"
+#include "xe_exec_queue_types.h"
 #include "xe_vm.h"
 
 #define __dev_name_bo(bo)	dev_name(xe_bo_device(bo)->drm.dev)
@@ -223,6 +224,11 @@ DEFINE_EVENT(xe_vm, xe_vm_free,
 	     TP_ARGS(vm)
 );
 
+DEFINE_EVENT(xe_vm, xe_vm_close,
+	     TP_PROTO(struct xe_vm *vm),
+	     TP_ARGS(vm)
+);
+
 DEFINE_EVENT(xe_vm, xe_vm_cpu_bind,
 	     TP_PROTO(struct xe_vm *vm),
 	     TP_ARGS(vm)
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index 4e914928e0a9..e5c196729b47 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -1657,6 +1657,8 @@ static void xe_vm_close(struct xe_vm *vm)
 	bool bound;
 	int idx;
 
+	trace_xe_vm_close(vm);
+
 	bound = drm_dev_enter(&xe->drm, &idx);
 
 	down_write(&vm->lock);
-- 
2.34.1

[PATCH 3/7] drm/xe: Add the BO pointer info to the BO trace

[Stuart Summers]

Just a little extra detail to make BOs easier to track
through the trace event log.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
 drivers/gpu/drm/xe/xe_trace_bo.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_trace_bo.h b/drivers/gpu/drm/xe/xe_trace_bo.h
index 238311cfb816..0d795733e0f0 100644
--- a/drivers/gpu/drm/xe/xe_trace_bo.h
+++ b/drivers/gpu/drm/xe/xe_trace_bo.h
@@ -27,6 +27,7 @@ DECLARE_EVENT_CLASS(xe_bo,
 
 		    TP_STRUCT__entry(
 			     __string(dev, __dev_name_bo(bo))
+			     __field(struct xe_bo *, bo)
 			     __field(size_t, size)
 			     __field(u32, flags)
 			     __field(struct xe_vm *, vm)
@@ -34,13 +35,14 @@ DECLARE_EVENT_CLASS(xe_bo,
 
 		    TP_fast_assign(
 			   __assign_str(dev);
+			   __entry->bo = bo;
 			   __entry->size = xe_bo_size(bo);
 			   __entry->flags = bo->flags;
 			   __entry->vm = bo->vm;
 			   ),
 
-		    TP_printk("dev=%s, size=%zu, flags=0x%02x, vm=%p",
-			      __get_str(dev), __entry->size,
+		    TP_printk("dev=%s, %p, size=%zu, flags=0x%02x, vm=%p",
+			      __get_str(dev), __entry->bo, __entry->size,
 			      __entry->flags, __entry->vm)
 );
 
-- 
2.34.1

[PATCH 4/7] drm/xe: Add new exec queue trace points

[Stuart Summers]

Add an exec queue and guc exec queue trace point
to separate out which part of the stack is executing.

This is helpful because several of the guc specific
paths rely on responses from guc which is interesting
to view separately in the event the guc stops responding
in the middle of an operation that would expect a
response from guc otherwise.

Also add in the exec queue pointer information to
the trace events for easier tracking. Contexts (guc_ids)
can get re-used, so this just makes grepping a little
easier in this type of debug.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
 drivers/gpu/drm/xe/xe_exec_queue.c |  4 ++++
 drivers/gpu/drm/xe/xe_guc_submit.c | 11 +++++++----
 drivers/gpu/drm/xe/xe_trace.h      | 22 ++++++++++++++++++++--
 3 files changed, 31 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index db3f869b53f3..c31bc8411a71 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -356,6 +356,8 @@ void xe_exec_queue_destroy(struct kref *ref)
 	struct xe_exec_queue *q = container_of(ref, struct xe_exec_queue, refcount);
 	struct xe_exec_queue *eq, *next;
 
+	trace_xe_exec_queue_destroy(q);
+
 	if (xe_exec_queue_uses_pxp(q))
 		xe_pxp_exec_queue_remove(gt_to_xe(q->gt)->pxp, q);
 
@@ -951,6 +953,8 @@ void xe_exec_queue_kill(struct xe_exec_queue *q)
 {
 	struct xe_exec_queue *eq = q, *next;
 
+	trace_xe_exec_queue_kill(q);
+
 	list_for_each_entry_safe(eq, next, &eq->multi_gt_list,
 				 multi_gt_link) {
 		q->ops->kill(eq);
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index 53024eb5670b..55a50c46ea2b 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -1022,9 +1022,12 @@ void xe_guc_submit_wedge(struct xe_guc *guc)
 	}
 
 	mutex_lock(&guc->submission_state.lock);
-	xa_for_each(&guc->submission_state.exec_queue_lookup, index, q)
-		if (xe_exec_queue_get_unless_zero(q))
+	xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) {
+		if (xe_exec_queue_get_unless_zero(q)) {
 			set_exec_queue_wedged(q);
+			trace_xe_exec_queue_wedge(q);
+		}
+	}
 	mutex_unlock(&guc->submission_state.lock);
 }
 
@@ -1443,7 +1446,7 @@ static void __guc_exec_queue_destroy_async(struct work_struct *w)
 	struct xe_guc *guc = exec_queue_to_guc(q);
 
 	xe_pm_runtime_get(guc_to_xe(guc));
-	trace_xe_exec_queue_destroy(q);
+	trace_xe_guc_exec_queue_destroy(q);
 
 	if (xe_exec_queue_is_lr(q))
 		cancel_work_sync(&ge->lr_tdr);
@@ -1688,7 +1691,7 @@ static int guc_exec_queue_init(struct xe_exec_queue *q)
 
 static void guc_exec_queue_kill(struct xe_exec_queue *q)
 {
-	trace_xe_exec_queue_kill(q);
+	trace_xe_guc_exec_queue_kill(q);
 	set_exec_queue_killed(q);
 	__suspend_fence_signal(q);
 	xe_guc_exec_queue_trigger_cleanup(q);
diff --git a/drivers/gpu/drm/xe/xe_trace.h b/drivers/gpu/drm/xe/xe_trace.h
index 314f42fcbcbd..a5dd0c48d894 100644
--- a/drivers/gpu/drm/xe/xe_trace.h
+++ b/drivers/gpu/drm/xe/xe_trace.h
@@ -71,6 +71,7 @@ DECLARE_EVENT_CLASS(xe_exec_queue,
 
 		    TP_STRUCT__entry(
 			     __string(dev, __dev_name_eq(q))
+			     __field(struct xe_exec_queue *, q)
 			     __field(enum xe_engine_class, class)
 			     __field(u32, logical_mask)
 			     __field(u8, gt_id)
@@ -82,6 +83,7 @@ DECLARE_EVENT_CLASS(xe_exec_queue,
 
 		    TP_fast_assign(
 			   __assign_str(dev);
+			   __entry->q = q;
 			   __entry->class = q->class;
 			   __entry->logical_mask = q->logical_mask;
 			   __entry->gt_id = q->gt->info.id;
@@ -91,8 +93,9 @@ DECLARE_EVENT_CLASS(xe_exec_queue,
 			   __entry->flags = q->flags;
 			   ),
 
-		    TP_printk("dev=%s, %d:0x%x, gt=%d, width=%d, guc_id=%d, guc_state=0x%x, flags=0x%x",
-			      __get_str(dev), __entry->class, __entry->logical_mask,
+		    TP_printk("dev=%s, %p, %d:0x%x, gt=%d, width=%d, guc_id=%d, guc_state=0x%x, flags=0x%x",
+			      __get_str(dev), __entry->q,
+			      __entry->class, __entry->logical_mask,
 			      __entry->gt_id, __entry->width, __entry->guc_id,
 			      __entry->guc_state, __entry->flags)
 );
@@ -147,11 +150,21 @@ DEFINE_EVENT(xe_exec_queue, xe_exec_queue_close,
 	     TP_ARGS(q)
 );
 
+DEFINE_EVENT(xe_exec_queue, xe_exec_queue_wedge,
+	     TP_PROTO(struct xe_exec_queue *q),
+	     TP_ARGS(q)
+);
+
 DEFINE_EVENT(xe_exec_queue, xe_exec_queue_kill,
 	     TP_PROTO(struct xe_exec_queue *q),
 	     TP_ARGS(q)
 );
 
+DEFINE_EVENT(xe_exec_queue, xe_guc_exec_queue_kill,
+	     TP_PROTO(struct xe_exec_queue *q),
+	     TP_ARGS(q)
+);
+
 DEFINE_EVENT(xe_exec_queue, xe_exec_queue_cleanup_entity,
 	     TP_PROTO(struct xe_exec_queue *q),
 	     TP_ARGS(q)
@@ -162,6 +175,11 @@ DEFINE_EVENT(xe_exec_queue, xe_exec_queue_destroy,
 	     TP_ARGS(q)
 );
 
+DEFINE_EVENT(xe_exec_queue, xe_guc_exec_queue_destroy,
+	     TP_PROTO(struct xe_exec_queue *q),
+	     TP_ARGS(q)
+);
+
 DEFINE_EVENT(xe_exec_queue, xe_exec_queue_reset,
 	     TP_PROTO(struct xe_exec_queue *q),
 	     TP_ARGS(q)
-- 
2.34.1

[PATCH 5/7] drm/xe: Handle missing migration VM on VM creation

[Stuart Summers]

Theoretically, a user could attempt to create a VM
while the migration VM is for some reason being
destroyed such that the xe_vm_create() routine gets
called, but when we assign a migration exec queue
to that VM, the VM for that migration exec queue is
no longer there. Add an error check here for that
case.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
 drivers/gpu/drm/xe/xe_exec_queue.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index c31bc8411a71..6baa19b8051c 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -326,6 +326,9 @@ struct xe_exec_queue *xe_exec_queue_create_bind(struct xe_device *xe,
 	struct xe_vm *migrate_vm;
 
 	migrate_vm = xe_migrate_get_vm(tile->migrate);
+	if (!migrate_vm)
+		return ERR_PTR(-ENODEV);
+
 	if (xe->info.has_usm) {
 		struct xe_hw_engine *hwe = xe_gt_hw_engine(gt,
 							   XE_ENGINE_CLASS_COPY,
-- 
2.34.1

[PATCH 6/7] drm/xe: Don't send a CLEANUP message on sched pause

[Stuart Summers]

When the DRM scheduler has been "paused" (see xe_gpu_scheduler.c),
if we then send a message to cleanup an exec queue at that time,
we will never get a response for it if for some reason the
unpause never happens. This can occur if for some reason during
exec queue creation, the device becomes wedged. The wedge event
will cause that scheduler to become paused and the creation
then leaves a dangling LRC that will never get cleaned up since
the recovery is a driver rebind. So essentially this change
fixes a potential memory leak in the event the device is
wedged during a test unexpectedly (e.g. during an unexpected
hardware failure).

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_submit.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index 55a50c46ea2b..45b72bebfc63 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -1732,7 +1732,8 @@ static void guc_exec_queue_destroy(struct xe_exec_queue *q)
 {
 	struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_CLEANUP;
 
-	if (!(q->flags & EXEC_QUEUE_FLAG_PERMANENT) && !exec_queue_wedged(q))
+	if (!(q->flags & EXEC_QUEUE_FLAG_PERMANENT) && !exec_queue_wedged(q) &&
+	    !READ_ONCE(q->guc->sched.base.pause_submit))
 		guc_exec_queue_add_msg(q, msg, CLEANUP);
 	else
 		__guc_exec_queue_destroy(exec_queue_to_guc(q), q);
-- 
2.34.1

[PATCH 7/7] drm/xe: Check for GuC responses on disabling scheduling

[Stuart Summers]

In the event the GuC becomes unresponsive during a scheduling
disable event, we still want the driver to be able to recover.
This patch follows the same methodology we already have in place
for TLB invalidation requests, where we send a request to GuC
and wait for that invalidation done response. If the response
doesn't come back in time we then at least print a message
indicating the invalidation failed for some reason.

In this case, we send the schedule disable and the expectation
is that GuC will respond with a schedule done response. The KMD
then catches that response and in turn sends a context deregistration
response. So in the event GuC becomes unresponsive after we send
the schedule disable, we actually have two g2h responses that
have been reserved but never received.

To handle this, make sure the pending disable event in the
exec queue gets cleared (i.e. we received that response from
GuC). If it doesn't in a reasonable amount of time, assume
GuC is dead: ban the exec queue, queue up a GT reset, and
manually call the schedule done handler. Then in the schedule
done handler, in turn, check whether the context had been
banned. If so, manually call the deregistration done handler
to ensure all resources related to that exec queue get
cleaned up properly. Without this, if the device becomes
wedged after an exec queue has been created, the attached
resources like the LRC will not get feed properly resulting
in a memory leak.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_submit.c | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index 45b72bebfc63..a177d87c8524 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -939,6 +939,9 @@ int xe_guc_read_stopped(struct xe_guc *guc)
 		GUC_CONTEXT_##enable_disable,				\
 	}
 
+static void handle_sched_done(struct xe_guc *guc, struct xe_exec_queue *q,
+			      u32 runnable_state);
+
 static void disable_scheduling_deregister(struct xe_guc *guc,
 					  struct xe_exec_queue *q)
 {
@@ -974,6 +977,17 @@ static void disable_scheduling_deregister(struct xe_guc *guc,
 	xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
 		       G2H_LEN_DW_SCHED_CONTEXT_MODE_SET +
 		       G2H_LEN_DW_DEREGISTER_CONTEXT, 2);
+
+	ret = wait_event_timeout(guc->ct.wq,
+				 !exec_queue_pending_disable(q) ||
+				 xe_guc_read_stopped(guc),
+				 HZ * 5);
+	if (!ret || xe_guc_read_stopped(guc)) {
+		xe_gt_warn(guc_to_gt(guc), "Schedule disable failed to respond");
+		set_exec_queue_banned(q);
+		handle_sched_done(guc, q, 0);
+		xe_gt_reset_async(q->gt);
+	}
 }
 
 static void xe_guc_exec_queue_trigger_cleanup(struct xe_exec_queue *q)
@@ -2117,6 +2131,8 @@ g2h_exec_queue_lookup(struct xe_guc *guc, u32 guc_id)
 	return q;
 }
 
+static void handle_deregister_done(struct xe_guc *guc, struct xe_exec_queue *q);
+
 static void deregister_exec_queue(struct xe_guc *guc, struct xe_exec_queue *q)
 {
 	u32 action[] = {
@@ -2131,7 +2147,12 @@ static void deregister_exec_queue(struct xe_guc *guc, struct xe_exec_queue *q)
 
 	trace_xe_exec_queue_deregister(q);
 
-	xe_guc_ct_send_g2h_handler(&guc->ct, action, ARRAY_SIZE(action));
+	if (exec_queue_banned(q)) {
+		handle_deregister_done(guc, q);
+	} else {
+		xe_guc_ct_send_g2h_handler(&guc->ct, action,
+					   ARRAY_SIZE(action));
+	}
 }
 
 static void handle_sched_done(struct xe_guc *guc, struct xe_exec_queue *q,
-- 
2.34.1

✗ CI.checkpatch: warning for Fix a couple of wedge corner-case memory leaks

[Patchwork]

== Series Details ==

Series: Fix a couple of wedge corner-case memory leaks
URL   : https://patchwork.freedesktop.org/series/155352/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
fbd08a78c3a3bb17964db2a326514c69c1dca660
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit de31da9099313aab3b3cc0baba9ea05a43dfafcc
Author: Stuart Summers <stuart.summers@intel.com>
Date:   Thu Oct 2 23:04:44 2025 +0000

    drm/xe: Check for GuC responses on disabling scheduling
    
    In the event the GuC becomes unresponsive during a scheduling
    disable event, we still want the driver to be able to recover.
    This patch follows the same methodology we already have in place
    for TLB invalidation requests, where we send a request to GuC
    and wait for that invalidation done response. If the response
    doesn't come back in time we then at least print a message
    indicating the invalidation failed for some reason.
    
    In this case, we send the schedule disable and the expectation
    is that GuC will respond with a schedule done response. The KMD
    then catches that response and in turn sends a context deregistration
    response. So in the event GuC becomes unresponsive after we send
    the schedule disable, we actually have two g2h responses that
    have been reserved but never received.
    
    To handle this, make sure the pending disable event in the
    exec queue gets cleared (i.e. we received that response from
    GuC). If it doesn't in a reasonable amount of time, assume
    GuC is dead: ban the exec queue, queue up a GT reset, and
    manually call the schedule done handler. Then in the schedule
    done handler, in turn, check whether the context had been
    banned. If so, manually call the deregistration done handler
    to ensure all resources related to that exec queue get
    cleaned up properly. Without this, if the device becomes
    wedged after an exec queue has been created, the attached
    resources like the LRC will not get feed properly resulting
    in a memory leak.
    
    Signed-off-by: Stuart Summers <stuart.summers@intel.com>
+ /mt/dim checkpatch 0aa5ad66ed77cd8c3bb9fb01997f68f31200f434 drm-intel
4b91a6dcfe12 drm/xe: Add additional trace points for LRCs
-:78: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#78: FILE: drivers/gpu/drm/xe/xe_trace_lrc.h:45:
+DECLARE_EVENT_CLASS(xe_lrc,
+	    TP_PROTO(struct xe_lrc *lrc),

-:81: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#81: FILE: drivers/gpu/drm/xe/xe_trace_lrc.h:48:
+	    TP_STRUCT__entry(

-:87: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#87: FILE: drivers/gpu/drm/xe/xe_trace_lrc.h:54:
+	    TP_fast_assign(

total: 0 errors, 0 warnings, 3 checks, 91 lines checked
d50ab269d91b drm/xe: Add a trace point for VM close
c3be85cb82de drm/xe: Add the BO pointer info to the BO trace
24397ed525d4 drm/xe: Add new exec queue trace points
20f5efc635fe drm/xe: Handle missing migration VM on VM creation
0e538d3bb166 drm/xe: Don't send a CLEANUP message on sched pause
de31da909931 drm/xe: Check for GuC responses on disabling scheduling

✓ CI.KUnit: success for Fix a couple of wedge corner-case memory leaks

[Patchwork]

== Series Details ==

Series: Fix a couple of wedge corner-case memory leaks
URL   : https://patchwork.freedesktop.org/series/155352/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[23:11:04] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:11:08] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:11:38] Starting KUnit Kernel (1/1)...
[23:11:38] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:11:38] ================== guc_buf (11 subtests) ===================
[23:11:38] [PASSED] test_smallest
[23:11:38] [PASSED] test_largest
[23:11:38] [PASSED] test_granular
[23:11:38] [PASSED] test_unique
[23:11:38] [PASSED] test_overlap
[23:11:38] [PASSED] test_reusable
[23:11:38] [PASSED] test_too_big
[23:11:38] [PASSED] test_flush
[23:11:38] [PASSED] test_lookup
[23:11:38] [PASSED] test_data
[23:11:38] [PASSED] test_class
[23:11:38] ===================== [PASSED] guc_buf =====================
[23:11:38] =================== guc_dbm (7 subtests) ===================
[23:11:38] [PASSED] test_empty
[23:11:38] [PASSED] test_default
[23:11:38] ======================== test_size  ========================
[23:11:38] [PASSED] 4
[23:11:38] [PASSED] 8
[23:11:38] [PASSED] 32
[23:11:38] [PASSED] 256
[23:11:38] ==================== [PASSED] test_size ====================
[23:11:38] ======================= test_reuse  ========================
[23:11:38] [PASSED] 4
[23:11:38] [PASSED] 8
[23:11:38] [PASSED] 32
[23:11:38] [PASSED] 256
[23:11:38] =================== [PASSED] test_reuse ====================
[23:11:38] =================== test_range_overlap  ====================
[23:11:38] [PASSED] 4
[23:11:38] [PASSED] 8
[23:11:38] [PASSED] 32
[23:11:38] [PASSED] 256
[23:11:38] =============== [PASSED] test_range_overlap ================
[23:11:38] =================== test_range_compact  ====================
[23:11:38] [PASSED] 4
[23:11:38] [PASSED] 8
[23:11:38] [PASSED] 32
[23:11:38] [PASSED] 256
[23:11:38] =============== [PASSED] test_range_compact ================
[23:11:38] ==================== test_range_spare  =====================
[23:11:38] [PASSED] 4
[23:11:38] [PASSED] 8
[23:11:38] [PASSED] 32
[23:11:38] [PASSED] 256
[23:11:38] ================ [PASSED] test_range_spare =================
[23:11:38] ===================== [PASSED] guc_dbm =====================
[23:11:38] =================== guc_idm (6 subtests) ===================
[23:11:38] [PASSED] bad_init
[23:11:38] [PASSED] no_init
[23:11:38] [PASSED] init_fini
[23:11:38] [PASSED] check_used
[23:11:38] [PASSED] check_quota
[23:11:38] [PASSED] check_all
[23:11:38] ===================== [PASSED] guc_idm =====================
[23:11:38] ================== no_relay (3 subtests) ===================
[23:11:38] [PASSED] xe_drops_guc2pf_if_not_ready
[23:11:38] [PASSED] xe_drops_guc2vf_if_not_ready
[23:11:38] [PASSED] xe_rejects_send_if_not_ready
[23:11:38] ==================== [PASSED] no_relay =====================
[23:11:38] ================== pf_relay (14 subtests) ==================
[23:11:38] [PASSED] pf_rejects_guc2pf_too_short
[23:11:38] [PASSED] pf_rejects_guc2pf_too_long
[23:11:38] [PASSED] pf_rejects_guc2pf_no_payload
[23:11:38] [PASSED] pf_fails_no_payload
[23:11:38] [PASSED] pf_fails_bad_origin
[23:11:38] [PASSED] pf_fails_bad_type
[23:11:38] [PASSED] pf_txn_reports_error
[23:11:38] [PASSED] pf_txn_sends_pf2guc
[23:11:38] [PASSED] pf_sends_pf2guc
[23:11:38] [SKIPPED] pf_loopback_nop
[23:11:38] [SKIPPED] pf_loopback_echo
[23:11:38] [SKIPPED] pf_loopback_fail
[23:11:38] [SKIPPED] pf_loopback_busy
[23:11:38] [SKIPPED] pf_loopback_retry
[23:11:38] ==================== [PASSED] pf_relay =====================
[23:11:38] ================== vf_relay (3 subtests) ===================
[23:11:38] [PASSED] vf_rejects_guc2vf_too_short
[23:11:38] [PASSED] vf_rejects_guc2vf_too_long
[23:11:38] [PASSED] vf_rejects_guc2vf_no_payload
[23:11:38] ==================== [PASSED] vf_relay =====================
[23:11:38] ===================== lmtt (1 subtest) =====================
[23:11:38] ======================== test_ops  =========================
[23:11:38] [PASSED] 2-level
[23:11:38] [PASSED] multi-level
[23:11:38] ==================== [PASSED] test_ops =====================
[23:11:38] ====================== [PASSED] lmtt =======================
[23:11:38] ================= pf_service (11 subtests) =================
[23:11:38] [PASSED] pf_negotiate_any
[23:11:38] [PASSED] pf_negotiate_base_match
[23:11:38] [PASSED] pf_negotiate_base_newer
[23:11:38] [PASSED] pf_negotiate_base_next
[23:11:38] [SKIPPED] pf_negotiate_base_older
[23:11:38] [PASSED] pf_negotiate_base_prev
[23:11:38] [PASSED] pf_negotiate_latest_match
[23:11:38] [PASSED] pf_negotiate_latest_newer
[23:11:38] [PASSED] pf_negotiate_latest_next
[23:11:38] [SKIPPED] pf_negotiate_latest_older
[23:11:38] [SKIPPED] pf_negotiate_latest_prev
[23:11:38] =================== [PASSED] pf_service ====================
[23:11:38] ================= xe_guc_g2g (2 subtests) ==================
[23:11:38] ============== xe_live_guc_g2g_kunit_default  ==============
[23:11:38] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[23:11:38] ============== xe_live_guc_g2g_kunit_allmem  ===============
[23:11:38] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[23:11:38] =================== [SKIPPED] xe_guc_g2g ===================
[23:11:38] =================== xe_mocs (2 subtests) ===================
[23:11:38] ================ xe_live_mocs_kernel_kunit  ================
[23:11:38] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[23:11:38] ================ xe_live_mocs_reset_kunit  =================
[23:11:38] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[23:11:38] ==================== [SKIPPED] xe_mocs =====================
[23:11:38] ================= xe_migrate (2 subtests) ==================
[23:11:38] ================= xe_migrate_sanity_kunit  =================
[23:11:38] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[23:11:38] ================== xe_validate_ccs_kunit  ==================
[23:11:38] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[23:11:38] =================== [SKIPPED] xe_migrate ===================
[23:11:38] ================== xe_dma_buf (1 subtest) ==================
[23:11:38] ==================== xe_dma_buf_kunit  =====================
[23:11:38] ================ [SKIPPED] xe_dma_buf_kunit ================
[23:11:38] =================== [SKIPPED] xe_dma_buf ===================
[23:11:38] ================= xe_bo_shrink (1 subtest) =================
[23:11:38] =================== xe_bo_shrink_kunit  ====================
[23:11:38] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[23:11:38] ================== [SKIPPED] xe_bo_shrink ==================
[23:11:38] ==================== xe_bo (2 subtests) ====================
[23:11:38] ================== xe_ccs_migrate_kunit  ===================
[23:11:38] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[23:11:38] ==================== xe_bo_evict_kunit  ====================
[23:11:38] =============== [SKIPPED] xe_bo_evict_kunit ================
[23:11:38] ===================== [SKIPPED] xe_bo ======================
[23:11:38] ==================== args (11 subtests) ====================
[23:11:38] [PASSED] count_args_test
[23:11:38] [PASSED] call_args_example
[23:11:38] [PASSED] call_args_test
[23:11:38] [PASSED] drop_first_arg_example
[23:11:38] [PASSED] drop_first_arg_test
[23:11:38] [PASSED] first_arg_example
[23:11:38] [PASSED] first_arg_test
[23:11:38] [PASSED] last_arg_example
[23:11:38] [PASSED] last_arg_test
[23:11:38] [PASSED] pick_arg_example
[23:11:38] [PASSED] sep_comma_example
[23:11:38] ====================== [PASSED] args =======================
[23:11:38] =================== xe_pci (3 subtests) ====================
[23:11:38] ==================== check_graphics_ip  ====================
[23:11:38] [PASSED] 12.00 Xe_LP
[23:11:38] [PASSED] 12.10 Xe_LP+
[23:11:38] [PASSED] 12.55 Xe_HPG
[23:11:38] [PASSED] 12.60 Xe_HPC
[23:11:38] [PASSED] 12.70 Xe_LPG
[23:11:38] [PASSED] 12.71 Xe_LPG
[23:11:38] [PASSED] 12.74 Xe_LPG+
[23:11:38] [PASSED] 20.01 Xe2_HPG
[23:11:38] [PASSED] 20.02 Xe2_HPG
[23:11:38] [PASSED] 20.04 Xe2_LPG
[23:11:38] [PASSED] 30.00 Xe3_LPG
[23:11:38] [PASSED] 30.01 Xe3_LPG
[23:11:38] [PASSED] 30.03 Xe3_LPG
[23:11:38] ================ [PASSED] check_graphics_ip ================
[23:11:38] ===================== check_media_ip  ======================
[23:11:38] [PASSED] 12.00 Xe_M
[23:11:38] [PASSED] 12.55 Xe_HPM
[23:11:38] [PASSED] 13.00 Xe_LPM+
[23:11:38] [PASSED] 13.01 Xe2_HPM
[23:11:38] [PASSED] 20.00 Xe2_LPM
[23:11:38] [PASSED] 30.00 Xe3_LPM
[23:11:38] [PASSED] 30.02 Xe3_LPM
[23:11:38] ================= [PASSED] check_media_ip ==================
[23:11:38] ================= check_platform_gt_count  =================
[23:11:38] [PASSED] 0x9A60 (TIGERLAKE)
[23:11:38] [PASSED] 0x9A68 (TIGERLAKE)
[23:11:38] [PASSED] 0x9A70 (TIGERLAKE)
[23:11:38] [PASSED] 0x9A40 (TIGERLAKE)
[23:11:38] [PASSED] 0x9A49 (TIGERLAKE)
[23:11:38] [PASSED] 0x9A59 (TIGERLAKE)
[23:11:38] [PASSED] 0x9A78 (TIGERLAKE)
[23:11:38] [PASSED] 0x9AC0 (TIGERLAKE)
[23:11:38] [PASSED] 0x9AC9 (TIGERLAKE)
[23:11:38] [PASSED] 0x9AD9 (TIGERLAKE)
[23:11:38] [PASSED] 0x9AF8 (TIGERLAKE)
[23:11:38] [PASSED] 0x4C80 (ROCKETLAKE)
[23:11:38] [PASSED] 0x4C8A (ROCKETLAKE)
[23:11:38] [PASSED] 0x4C8B (ROCKETLAKE)
[23:11:38] [PASSED] 0x4C8C (ROCKETLAKE)
[23:11:38] [PASSED] 0x4C90 (ROCKETLAKE)
[23:11:38] [PASSED] 0x4C9A (ROCKETLAKE)
[23:11:38] [PASSED] 0x4680 (ALDERLAKE_S)
[23:11:38] [PASSED] 0x4682 (ALDERLAKE_S)
[23:11:38] [PASSED] 0x4688 (ALDERLAKE_S)
[23:11:38] [PASSED] 0x468A (ALDERLAKE_S)
[23:11:38] [PASSED] 0x468B (ALDERLAKE_S)
[23:11:38] [PASSED] 0x4690 (ALDERLAKE_S)
[23:11:38] [PASSED] 0x4692 (ALDERLAKE_S)
[23:11:38] [PASSED] 0x4693 (ALDERLAKE_S)
[23:11:38] [PASSED] 0x46A0 (ALDERLAKE_P)
[23:11:38] [PASSED] 0x46A1 (ALDERLAKE_P)
[23:11:38] [PASSED] 0x46A2 (ALDERLAKE_P)
[23:11:38] [PASSED] 0x46A3 (ALDERLAKE_P)
[23:11:38] [PASSED] 0x46A6 (ALDERLAKE_P)
[23:11:38] [PASSED] 0x46A8 (ALDERLAKE_P)
[23:11:38] [PASSED] 0x46AA (ALDERLAKE_P)
[23:11:38] [PASSED] 0x462A (ALDERLAKE_P)
[23:11:38] [PASSED] 0x4626 (ALDERLAKE_P)
[23:11:38] [PASSED] 0x4628 (ALDERLAKE_P)
[23:11:38] [PASSED] 0x46B0 (ALDERLAKE_P)
[23:11:38] [PASSED] 0x46B1 (ALDERLAKE_P)
[23:11:38] [PASSED] 0x46B2 (ALDERLAKE_P)
[23:11:38] [PASSED] 0x46B3 (ALDERLAKE_P)
[23:11:38] [PASSED] 0x46C0 (ALDERLAKE_P)
[23:11:38] [PASSED] 0x46C1 (ALDERLAKE_P)
[23:11:38] [PASSED] 0x46C2 (ALDERLAKE_P)
[23:11:38] [PASSED] 0x46C3 (ALDERLAKE_P)
[23:11:38] [PASSED] 0x46D0 (ALDERLAKE_N)
[23:11:38] [PASSED] 0x46D1 (ALDERLAKE_N)
[23:11:38] [PASSED] 0x46D2 (ALDERLAKE_N)
[23:11:38] [PASSED] 0x46D3 (ALDERLAKE_N)
[23:11:38] [PASSED] 0x46D4 (ALDERLAKE_N)
[23:11:38] [PASSED] 0xA721 (ALDERLAKE_P)
[23:11:38] [PASSED] 0xA7A1 (ALDERLAKE_P)
[23:11:38] [PASSED] 0xA7A9 (ALDERLAKE_P)
[23:11:38] [PASSED] 0xA7AC (ALDERLAKE_P)
[23:11:38] [PASSED] 0xA7AD (ALDERLAKE_P)
[23:11:38] [PASSED] 0xA720 (ALDERLAKE_P)
[23:11:38] [PASSED] 0xA7A0 (ALDERLAKE_P)
[23:11:38] [PASSED] 0xA7A8 (ALDERLAKE_P)
[23:11:38] [PASSED] 0xA7AA (ALDERLAKE_P)
[23:11:38] [PASSED] 0xA7AB (ALDERLAKE_P)
[23:11:38] [PASSED] 0xA780 (ALDERLAKE_S)
[23:11:38] [PASSED] 0xA781 (ALDERLAKE_S)
[23:11:38] [PASSED] 0xA782 (ALDERLAKE_S)
[23:11:38] [PASSED] 0xA783 (ALDERLAKE_S)
[23:11:38] [PASSED] 0xA788 (ALDERLAKE_S)
[23:11:38] [PASSED] 0xA789 (ALDERLAKE_S)
[23:11:38] [PASSED] 0xA78A (ALDERLAKE_S)
[23:11:38] [PASSED] 0xA78B (ALDERLAKE_S)
[23:11:38] [PASSED] 0x4905 (DG1)
[23:11:38] [PASSED] 0x4906 (DG1)
[23:11:38] [PASSED] 0x4907 (DG1)
[23:11:38] [PASSED] 0x4908 (DG1)
[23:11:38] [PASSED] 0x4909 (DG1)
[23:11:38] [PASSED] 0x56C0 (DG2)
[23:11:38] [PASSED] 0x56C2 (DG2)
[23:11:38] [PASSED] 0x56C1 (DG2)
[23:11:38] [PASSED] 0x7D51 (METEORLAKE)
[23:11:38] [PASSED] 0x7DD1 (METEORLAKE)
[23:11:38] [PASSED] 0x7D41 (METEORLAKE)
[23:11:38] [PASSED] 0x7D67 (METEORLAKE)
[23:11:38] [PASSED] 0xB640 (METEORLAKE)
[23:11:38] [PASSED] 0x56A0 (DG2)
[23:11:38] [PASSED] 0x56A1 (DG2)
[23:11:38] [PASSED] 0x56A2 (DG2)
[23:11:38] [PASSED] 0x56BE (DG2)
[23:11:38] [PASSED] 0x56BF (DG2)
[23:11:38] [PASSED] 0x5690 (DG2)
[23:11:38] [PASSED] 0x5691 (DG2)
[23:11:38] [PASSED] 0x5692 (DG2)
[23:11:38] [PASSED] 0x56A5 (DG2)
[23:11:38] [PASSED] 0x56A6 (DG2)
[23:11:38] [PASSED] 0x56B0 (DG2)
[23:11:38] [PASSED] 0x56B1 (DG2)
[23:11:38] [PASSED] 0x56BA (DG2)
[23:11:38] [PASSED] 0x56BB (DG2)
[23:11:38] [PASSED] 0x56BC (DG2)
[23:11:38] [PASSED] 0x56BD (DG2)
[23:11:38] [PASSED] 0x5693 (DG2)
[23:11:38] [PASSED] 0x5694 (DG2)
[23:11:38] [PASSED] 0x5695 (DG2)
[23:11:38] [PASSED] 0x56A3 (DG2)
[23:11:38] [PASSED] 0x56A4 (DG2)
[23:11:38] [PASSED] 0x56B2 (DG2)
[23:11:38] [PASSED] 0x56B3 (DG2)
[23:11:38] [PASSED] 0x5696 (DG2)
[23:11:38] [PASSED] 0x5697 (DG2)
[23:11:38] [PASSED] 0xB69 (PVC)
[23:11:38] [PASSED] 0xB6E (PVC)
[23:11:38] [PASSED] 0xBD4 (PVC)
[23:11:38] [PASSED] 0xBD5 (PVC)
[23:11:38] [PASSED] 0xBD6 (PVC)
[23:11:38] [PASSED] 0xBD7 (PVC)
[23:11:38] [PASSED] 0xBD8 (PVC)
[23:11:38] [PASSED] 0xBD9 (PVC)
[23:11:38] [PASSED] 0xBDA (PVC)
[23:11:38] [PASSED] 0xBDB (PVC)
[23:11:38] [PASSED] 0xBE0 (PVC)
[23:11:38] [PASSED] 0xBE1 (PVC)
[23:11:38] [PASSED] 0xBE5 (PVC)
[23:11:38] [PASSED] 0x7D40 (METEORLAKE)
[23:11:38] [PASSED] 0x7D45 (METEORLAKE)
[23:11:38] [PASSED] 0x7D55 (METEORLAKE)
[23:11:38] [PASSED] 0x7D60 (METEORLAKE)
[23:11:38] [PASSED] 0x7DD5 (METEORLAKE)
[23:11:38] [PASSED] 0x6420 (LUNARLAKE)
[23:11:38] [PASSED] 0x64A0 (LUNARLAKE)
[23:11:38] [PASSED] 0x64B0 (LUNARLAKE)
[23:11:38] [PASSED] 0xE202 (BATTLEMAGE)
[23:11:38] [PASSED] 0xE209 (BATTLEMAGE)
[23:11:38] [PASSED] 0xE20B (BATTLEMAGE)
[23:11:38] [PASSED] 0xE20C (BATTLEMAGE)
[23:11:38] [PASSED] 0xE20D (BATTLEMAGE)
[23:11:38] [PASSED] 0xE210 (BATTLEMAGE)
[23:11:38] [PASSED] 0xE211 (BATTLEMAGE)
[23:11:38] [PASSED] 0xE212 (BATTLEMAGE)
[23:11:38] [PASSED] 0xE216 (BATTLEMAGE)
[23:11:38] [PASSED] 0xE220 (BATTLEMAGE)
[23:11:38] [PASSED] 0xE221 (BATTLEMAGE)
[23:11:38] [PASSED] 0xE222 (BATTLEMAGE)
[23:11:38] [PASSED] 0xE223 (BATTLEMAGE)
[23:11:38] [PASSED] 0xB080 (PANTHERLAKE)
[23:11:38] [PASSED] 0xB081 (PANTHERLAKE)
[23:11:38] [PASSED] 0xB082 (PANTHERLAKE)
[23:11:38] [PASSED] 0xB083 (PANTHERLAKE)
[23:11:38] [PASSED] 0xB084 (PANTHERLAKE)
[23:11:38] [PASSED] 0xB085 (PANTHERLAKE)
[23:11:38] [PASSED] 0xB086 (PANTHERLAKE)
[23:11:38] [PASSED] 0xB087 (PANTHERLAKE)
[23:11:38] [PASSED] 0xB08F (PANTHERLAKE)
[23:11:38] [PASSED] 0xB090 (PANTHERLAKE)
[23:11:38] [PASSED] 0xB0A0 (PANTHERLAKE)
[23:11:38] [PASSED] 0xB0B0 (PANTHERLAKE)
[23:11:38] [PASSED] 0xFD80 (PANTHERLAKE)
[23:11:38] [PASSED] 0xFD81 (PANTHERLAKE)
[23:11:38] ============= [PASSED] check_platform_gt_count =============
[23:11:38] ===================== [PASSED] xe_pci ======================
[23:11:38] =================== xe_rtp (2 subtests) ====================
[23:11:38] =============== xe_rtp_process_to_sr_tests  ================
[23:11:38] [PASSED] coalesce-same-reg
[23:11:38] [PASSED] no-match-no-add
[23:11:38] [PASSED] match-or
[23:11:38] [PASSED] match-or-xfail
[23:11:38] [PASSED] no-match-no-add-multiple-rules
[23:11:38] [PASSED] two-regs-two-entries
[23:11:38] [PASSED] clr-one-set-other
[23:11:38] [PASSED] set-field
[23:11:38] [PASSED] conflict-duplicate
[23:11:38] [PASSED] conflict-not-disjoint
[23:11:38] [PASSED] conflict-reg-type
[23:11:38] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[23:11:38] ================== xe_rtp_process_tests  ===================
[23:11:38] [PASSED] active1
[23:11:38] [PASSED] active2
[23:11:38] [PASSED] active-inactive
[23:11:38] [PASSED] inactive-active
[23:11:38] [PASSED] inactive-1st_or_active-inactive
[23:11:38] [PASSED] inactive-2nd_or_active-inactive
[23:11:38] [PASSED] inactive-last_or_active-inactive
[23:11:38] [PASSED] inactive-no_or_active-inactive
[23:11:38] ============== [PASSED] xe_rtp_process_tests ===============
[23:11:38] ===================== [PASSED] xe_rtp ======================
[23:11:38] ==================== xe_wa (1 subtest) =====================
[23:11:38] ======================== xe_wa_gt  =========================
[23:11:38] [PASSED] TIGERLAKE B0
[23:11:38] [PASSED] DG1 A0
[23:11:38] [PASSED] DG1 B0
[23:11:38] [PASSED] ALDERLAKE_S A0
[23:11:38] [PASSED] ALDERLAKE_S B0
stty: 'standard input': Inappropriate ioctl for device
[23:11:38] [PASSED] ALDERLAKE_S C0
[23:11:38] [PASSED] ALDERLAKE_S D0
[23:11:38] [PASSED] ALDERLAKE_P A0
[23:11:38] [PASSED] ALDERLAKE_P B0
[23:11:38] [PASSED] ALDERLAKE_P C0
[23:11:38] [PASSED] ALDERLAKE_S RPLS D0
[23:11:38] [PASSED] ALDERLAKE_P RPLU E0
[23:11:38] [PASSED] DG2 G10 C0
[23:11:38] [PASSED] DG2 G11 B1
[23:11:38] [PASSED] DG2 G12 A1
[23:11:38] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[23:11:38] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[23:11:38] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[23:11:38] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[23:11:38] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[23:11:38] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[23:11:38] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[23:11:38] ==================== [PASSED] xe_wa_gt =====================
[23:11:38] ====================== [PASSED] xe_wa ======================
[23:11:38] ============================================================
[23:11:38] Testing complete. Ran 306 tests: passed: 288, skipped: 18
[23:11:38] Elapsed time: 33.829s total, 4.281s configuring, 29.181s building, 0.327s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[23:11:38] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:11:40] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:12:04] Starting KUnit Kernel (1/1)...
[23:12:04] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:12:04] ============ drm_test_pick_cmdline (2 subtests) ============
[23:12:04] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[23:12:04] =============== drm_test_pick_cmdline_named  ===============
[23:12:04] [PASSED] NTSC
[23:12:04] [PASSED] NTSC-J
[23:12:04] [PASSED] PAL
[23:12:04] [PASSED] PAL-M
[23:12:04] =========== [PASSED] drm_test_pick_cmdline_named ===========
[23:12:04] ============== [PASSED] drm_test_pick_cmdline ==============
[23:12:04] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[23:12:04] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[23:12:04] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[23:12:04] =========== drm_validate_clone_mode (2 subtests) ===========
[23:12:04] ============== drm_test_check_in_clone_mode  ===============
[23:12:04] [PASSED] in_clone_mode
[23:12:04] [PASSED] not_in_clone_mode
[23:12:04] ========== [PASSED] drm_test_check_in_clone_mode ===========
[23:12:04] =============== drm_test_check_valid_clones  ===============
[23:12:04] [PASSED] not_in_clone_mode
[23:12:04] [PASSED] valid_clone
[23:12:04] [PASSED] invalid_clone
[23:12:04] =========== [PASSED] drm_test_check_valid_clones ===========
[23:12:04] ============= [PASSED] drm_validate_clone_mode =============
[23:12:04] ============= drm_validate_modeset (1 subtest) =============
[23:12:04] [PASSED] drm_test_check_connector_changed_modeset
[23:12:04] ============== [PASSED] drm_validate_modeset ===============
[23:12:04] ====== drm_test_bridge_get_current_state (2 subtests) ======
[23:12:04] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[23:12:04] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[23:12:04] ======== [PASSED] drm_test_bridge_get_current_state ========
[23:12:04] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[23:12:04] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[23:12:04] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[23:12:04] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[23:12:04] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[23:12:04] ============== drm_bridge_alloc (2 subtests) ===============
[23:12:04] [PASSED] drm_test_drm_bridge_alloc_basic
[23:12:04] [PASSED] drm_test_drm_bridge_alloc_get_put
[23:12:04] ================ [PASSED] drm_bridge_alloc =================
[23:12:04] ================== drm_buddy (7 subtests) ==================
[23:12:04] [PASSED] drm_test_buddy_alloc_limit
[23:12:04] [PASSED] drm_test_buddy_alloc_optimistic
[23:12:04] [PASSED] drm_test_buddy_alloc_pessimistic
[23:12:04] [PASSED] drm_test_buddy_alloc_pathological
[23:12:04] [PASSED] drm_test_buddy_alloc_contiguous
[23:12:04] [PASSED] drm_test_buddy_alloc_clear
[23:12:04] [PASSED] drm_test_buddy_alloc_range_bias
[23:12:04] ==================== [PASSED] drm_buddy ====================
[23:12:04] ============= drm_cmdline_parser (40 subtests) =============
[23:12:04] [PASSED] drm_test_cmdline_force_d_only
[23:12:04] [PASSED] drm_test_cmdline_force_D_only_dvi
[23:12:04] [PASSED] drm_test_cmdline_force_D_only_hdmi
[23:12:04] [PASSED] drm_test_cmdline_force_D_only_not_digital
[23:12:04] [PASSED] drm_test_cmdline_force_e_only
[23:12:04] [PASSED] drm_test_cmdline_res
[23:12:04] [PASSED] drm_test_cmdline_res_vesa
[23:12:04] [PASSED] drm_test_cmdline_res_vesa_rblank
[23:12:04] [PASSED] drm_test_cmdline_res_rblank
[23:12:04] [PASSED] drm_test_cmdline_res_bpp
[23:12:04] [PASSED] drm_test_cmdline_res_refresh
[23:12:04] [PASSED] drm_test_cmdline_res_bpp_refresh
[23:12:04] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[23:12:04] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[23:12:04] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[23:12:04] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[23:12:04] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[23:12:04] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[23:12:04] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[23:12:04] [PASSED] drm_test_cmdline_res_margins_force_on
[23:12:04] [PASSED] drm_test_cmdline_res_vesa_margins
[23:12:04] [PASSED] drm_test_cmdline_name
[23:12:04] [PASSED] drm_test_cmdline_name_bpp
[23:12:04] [PASSED] drm_test_cmdline_name_option
[23:12:04] [PASSED] drm_test_cmdline_name_bpp_option
[23:12:04] [PASSED] drm_test_cmdline_rotate_0
[23:12:04] [PASSED] drm_test_cmdline_rotate_90
[23:12:04] [PASSED] drm_test_cmdline_rotate_180
[23:12:04] [PASSED] drm_test_cmdline_rotate_270
[23:12:04] [PASSED] drm_test_cmdline_hmirror
[23:12:04] [PASSED] drm_test_cmdline_vmirror
[23:12:04] [PASSED] drm_test_cmdline_margin_options
[23:12:04] [PASSED] drm_test_cmdline_multiple_options
[23:12:04] [PASSED] drm_test_cmdline_bpp_extra_and_option
[23:12:04] [PASSED] drm_test_cmdline_extra_and_option
[23:12:04] [PASSED] drm_test_cmdline_freestanding_options
[23:12:04] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[23:12:04] [PASSED] drm_test_cmdline_panel_orientation
[23:12:04] ================ drm_test_cmdline_invalid  =================
[23:12:04] [PASSED] margin_only
[23:12:04] [PASSED] interlace_only
[23:12:04] [PASSED] res_missing_x
[23:12:04] [PASSED] res_missing_y
[23:12:04] [PASSED] res_bad_y
[23:12:04] [PASSED] res_missing_y_bpp
[23:12:04] [PASSED] res_bad_bpp
[23:12:04] [PASSED] res_bad_refresh
[23:12:04] [PASSED] res_bpp_refresh_force_on_off
[23:12:04] [PASSED] res_invalid_mode
[23:12:04] [PASSED] res_bpp_wrong_place_mode
[23:12:04] [PASSED] name_bpp_refresh
[23:12:04] [PASSED] name_refresh
[23:12:04] [PASSED] name_refresh_wrong_mode
[23:12:04] [PASSED] name_refresh_invalid_mode
[23:12:04] [PASSED] rotate_multiple
[23:12:04] [PASSED] rotate_invalid_val
[23:12:04] [PASSED] rotate_truncated
[23:12:04] [PASSED] invalid_option
[23:12:04] [PASSED] invalid_tv_option
[23:12:04] [PASSED] truncated_tv_option
[23:12:04] ============ [PASSED] drm_test_cmdline_invalid =============
[23:12:04] =============== drm_test_cmdline_tv_options  ===============
[23:12:04] [PASSED] NTSC
[23:12:04] [PASSED] NTSC_443
[23:12:04] [PASSED] NTSC_J
[23:12:04] [PASSED] PAL
[23:12:04] [PASSED] PAL_M
[23:12:04] [PASSED] PAL_N
[23:12:04] [PASSED] SECAM
[23:12:04] [PASSED] MONO_525
[23:12:04] [PASSED] MONO_625
[23:12:04] =========== [PASSED] drm_test_cmdline_tv_options ===========
[23:12:04] =============== [PASSED] drm_cmdline_parser ================
[23:12:04] ========== drmm_connector_hdmi_init (20 subtests) ==========
[23:12:04] [PASSED] drm_test_connector_hdmi_init_valid
[23:12:04] [PASSED] drm_test_connector_hdmi_init_bpc_8
[23:12:04] [PASSED] drm_test_connector_hdmi_init_bpc_10
[23:12:04] [PASSED] drm_test_connector_hdmi_init_bpc_12
[23:12:04] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[23:12:04] [PASSED] drm_test_connector_hdmi_init_bpc_null
[23:12:04] [PASSED] drm_test_connector_hdmi_init_formats_empty
[23:12:04] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[23:12:04] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[23:12:04] [PASSED] supported_formats=0x9 yuv420_allowed=1
[23:12:04] [PASSED] supported_formats=0x9 yuv420_allowed=0
[23:12:04] [PASSED] supported_formats=0x3 yuv420_allowed=1
[23:12:04] [PASSED] supported_formats=0x3 yuv420_allowed=0
[23:12:04] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[23:12:04] [PASSED] drm_test_connector_hdmi_init_null_ddc
[23:12:04] [PASSED] drm_test_connector_hdmi_init_null_product
[23:12:04] [PASSED] drm_test_connector_hdmi_init_null_vendor
[23:12:04] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[23:12:04] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[23:12:04] [PASSED] drm_test_connector_hdmi_init_product_valid
[23:12:04] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[23:12:04] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[23:12:04] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[23:12:04] ========= drm_test_connector_hdmi_init_type_valid  =========
[23:12:04] [PASSED] HDMI-A
[23:12:04] [PASSED] HDMI-B
[23:12:04] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[23:12:04] ======== drm_test_connector_hdmi_init_type_invalid  ========
[23:12:04] [PASSED] Unknown
[23:12:04] [PASSED] VGA
[23:12:04] [PASSED] DVI-I
[23:12:04] [PASSED] DVI-D
[23:12:04] [PASSED] DVI-A
[23:12:04] [PASSED] Composite
[23:12:04] [PASSED] SVIDEO
[23:12:04] [PASSED] LVDS
[23:12:04] [PASSED] Component
[23:12:04] [PASSED] DIN
[23:12:04] [PASSED] DP
[23:12:04] [PASSED] TV
[23:12:04] [PASSED] eDP
[23:12:04] [PASSED] Virtual
[23:12:04] [PASSED] DSI
[23:12:04] [PASSED] DPI
[23:12:04] [PASSED] Writeback
[23:12:04] [PASSED] SPI
[23:12:04] [PASSED] USB
[23:12:04] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[23:12:04] ============ [PASSED] drmm_connector_hdmi_init =============
[23:12:04] ============= drmm_connector_init (3 subtests) =============
[23:12:04] [PASSED] drm_test_drmm_connector_init
[23:12:04] [PASSED] drm_test_drmm_connector_init_null_ddc
[23:12:04] ========= drm_test_drmm_connector_init_type_valid  =========
[23:12:04] [PASSED] Unknown
[23:12:04] [PASSED] VGA
[23:12:04] [PASSED] DVI-I
[23:12:04] [PASSED] DVI-D
[23:12:04] [PASSED] DVI-A
[23:12:04] [PASSED] Composite
[23:12:04] [PASSED] SVIDEO
[23:12:04] [PASSED] LVDS
[23:12:04] [PASSED] Component
[23:12:04] [PASSED] DIN
[23:12:04] [PASSED] DP
[23:12:04] [PASSED] HDMI-A
[23:12:04] [PASSED] HDMI-B
[23:12:04] [PASSED] TV
[23:12:04] [PASSED] eDP
[23:12:04] [PASSED] Virtual
[23:12:04] [PASSED] DSI
[23:12:04] [PASSED] DPI
[23:12:04] [PASSED] Writeback
[23:12:04] [PASSED] SPI
[23:12:04] [PASSED] USB
[23:12:04] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[23:12:04] =============== [PASSED] drmm_connector_init ===============
[23:12:04] ========= drm_connector_dynamic_init (6 subtests) ==========
[23:12:04] [PASSED] drm_test_drm_connector_dynamic_init
[23:12:04] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[23:12:04] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[23:12:04] [PASSED] drm_test_drm_connector_dynamic_init_properties
[23:12:04] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[23:12:04] [PASSED] Unknown
[23:12:04] [PASSED] VGA
[23:12:04] [PASSED] DVI-I
[23:12:04] [PASSED] DVI-D
[23:12:04] [PASSED] DVI-A
[23:12:04] [PASSED] Composite
[23:12:04] [PASSED] SVIDEO
[23:12:04] [PASSED] LVDS
[23:12:04] [PASSED] Component
[23:12:04] [PASSED] DIN
[23:12:04] [PASSED] DP
[23:12:04] [PASSED] HDMI-A
[23:12:04] [PASSED] HDMI-B
[23:12:04] [PASSED] TV
[23:12:04] [PASSED] eDP
[23:12:04] [PASSED] Virtual
[23:12:04] [PASSED] DSI
[23:12:04] [PASSED] DPI
[23:12:04] [PASSED] Writeback
[23:12:04] [PASSED] SPI
[23:12:04] [PASSED] USB
[23:12:04] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[23:12:04] ======== drm_test_drm_connector_dynamic_init_name  =========
[23:12:04] [PASSED] Unknown
[23:12:04] [PASSED] VGA
[23:12:04] [PASSED] DVI-I
[23:12:04] [PASSED] DVI-D
[23:12:04] [PASSED] DVI-A
[23:12:04] [PASSED] Composite
[23:12:04] [PASSED] SVIDEO
[23:12:04] [PASSED] LVDS
[23:12:04] [PASSED] Component
[23:12:04] [PASSED] DIN
[23:12:04] [PASSED] DP
[23:12:04] [PASSED] HDMI-A
[23:12:04] [PASSED] HDMI-B
[23:12:04] [PASSED] TV
[23:12:04] [PASSED] eDP
[23:12:04] [PASSED] Virtual
[23:12:04] [PASSED] DSI
[23:12:04] [PASSED] DPI
[23:12:04] [PASSED] Writeback
[23:12:04] [PASSED] SPI
[23:12:04] [PASSED] USB
[23:12:04] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[23:12:04] =========== [PASSED] drm_connector_dynamic_init ============
[23:12:04] ==== drm_connector_dynamic_register_early (4 subtests) =====
[23:12:04] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[23:12:04] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[23:12:04] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[23:12:04] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[23:12:04] ====== [PASSED] drm_connector_dynamic_register_early =======
[23:12:04] ======= drm_connector_dynamic_register (7 subtests) ========
[23:12:04] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[23:12:04] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[23:12:04] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[23:12:04] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[23:12:04] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[23:12:04] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[23:12:04] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[23:12:04] ========= [PASSED] drm_connector_dynamic_register ==========
[23:12:04] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[23:12:04] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[23:12:04] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[23:12:04] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[23:12:04] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[23:12:04] ========== drm_test_get_tv_mode_from_name_valid  ===========
[23:12:04] [PASSED] NTSC
[23:12:04] [PASSED] NTSC-443
[23:12:04] [PASSED] NTSC-J
[23:12:04] [PASSED] PAL
[23:12:04] [PASSED] PAL-M
[23:12:04] [PASSED] PAL-N
[23:12:04] [PASSED] SECAM
[23:12:04] [PASSED] Mono
[23:12:04] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[23:12:04] [PASSED] drm_test_get_tv_mode_from_name_truncated
[23:12:04] ============ [PASSED] drm_get_tv_mode_from_name ============
[23:12:04] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[23:12:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[23:12:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[23:12:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[23:12:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[23:12:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[23:12:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[23:12:04] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[23:12:04] [PASSED] VIC 96
[23:12:04] [PASSED] VIC 97
[23:12:04] [PASSED] VIC 101
[23:12:04] [PASSED] VIC 102
[23:12:04] [PASSED] VIC 106
[23:12:04] [PASSED] VIC 107
[23:12:04] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[23:12:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[23:12:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[23:12:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[23:12:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[23:12:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[23:12:04] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[23:12:04] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[23:12:04] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[23:12:04] [PASSED] Automatic
[23:12:04] [PASSED] Full
[23:12:04] [PASSED] Limited 16:235
[23:12:04] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[23:12:04] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[23:12:04] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[23:12:04] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[23:12:04] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[23:12:04] [PASSED] RGB
[23:12:04] [PASSED] YUV 4:2:0
[23:12:04] [PASSED] YUV 4:2:2
[23:12:04] [PASSED] YUV 4:4:4
[23:12:04] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[23:12:04] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[23:12:04] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[23:12:04] ============= drm_damage_helper (21 subtests) ==============
[23:12:04] [PASSED] drm_test_damage_iter_no_damage
[23:12:04] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[23:12:04] [PASSED] drm_test_damage_iter_no_damage_src_moved
[23:12:04] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[23:12:04] [PASSED] drm_test_damage_iter_no_damage_not_visible
[23:12:04] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[23:12:04] [PASSED] drm_test_damage_iter_no_damage_no_fb
[23:12:04] [PASSED] drm_test_damage_iter_simple_damage
[23:12:04] [PASSED] drm_test_damage_iter_single_damage
[23:12:04] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[23:12:04] [PASSED] drm_test_damage_iter_single_damage_outside_src
[23:12:04] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[23:12:04] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[23:12:04] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[23:12:04] [PASSED] drm_test_damage_iter_single_damage_src_moved
[23:12:04] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[23:12:04] [PASSED] drm_test_damage_iter_damage
[23:12:04] [PASSED] drm_test_damage_iter_damage_one_intersect
[23:12:04] [PASSED] drm_test_damage_iter_damage_one_outside
[23:12:04] [PASSED] drm_test_damage_iter_damage_src_moved
[23:12:04] [PASSED] drm_test_damage_iter_damage_not_visible
[23:12:04] ================ [PASSED] drm_damage_helper ================
[23:12:04] ============== drm_dp_mst_helper (3 subtests) ==============
[23:12:04] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[23:12:04] [PASSED] Clock 154000 BPP 30 DSC disabled
[23:12:04] [PASSED] Clock 234000 BPP 30 DSC disabled
[23:12:04] [PASSED] Clock 297000 BPP 24 DSC disabled
[23:12:04] [PASSED] Clock 332880 BPP 24 DSC enabled
[23:12:04] [PASSED] Clock 324540 BPP 24 DSC enabled
[23:12:04] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[23:12:04] ============== drm_test_dp_mst_calc_pbn_div  ===============
[23:12:04] [PASSED] Link rate 2000000 lane count 4
[23:12:04] [PASSED] Link rate 2000000 lane count 2
[23:12:04] [PASSED] Link rate 2000000 lane count 1
[23:12:04] [PASSED] Link rate 1350000 lane count 4
[23:12:04] [PASSED] Link rate 1350000 lane count 2
[23:12:04] [PASSED] Link rate 1350000 lane count 1
[23:12:04] [PASSED] Link rate 1000000 lane count 4
[23:12:04] [PASSED] Link rate 1000000 lane count 2
[23:12:04] [PASSED] Link rate 1000000 lane count 1
[23:12:04] [PASSED] Link rate 810000 lane count 4
[23:12:04] [PASSED] Link rate 810000 lane count 2
[23:12:04] [PASSED] Link rate 810000 lane count 1
[23:12:04] [PASSED] Link rate 540000 lane count 4
[23:12:04] [PASSED] Link rate 540000 lane count 2
[23:12:04] [PASSED] Link rate 540000 lane count 1
[23:12:04] [PASSED] Link rate 270000 lane count 4
[23:12:04] [PASSED] Link rate 270000 lane count 2
[23:12:04] [PASSED] Link rate 270000 lane count 1
[23:12:04] [PASSED] Link rate 162000 lane count 4
[23:12:04] [PASSED] Link rate 162000 lane count 2
[23:12:04] [PASSED] Link rate 162000 lane count 1
[23:12:04] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[23:12:04] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[23:12:04] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[23:12:04] [PASSED] DP_POWER_UP_PHY with port number
[23:12:04] [PASSED] DP_POWER_DOWN_PHY with port number
[23:12:04] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[23:12:04] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[23:12:04] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[23:12:04] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[23:12:04] [PASSED] DP_QUERY_PAYLOAD with port number
[23:12:04] [PASSED] DP_QUERY_PAYLOAD with VCPI
[23:12:04] [PASSED] DP_REMOTE_DPCD_READ with port number
[23:12:04] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[23:12:04] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[23:12:04] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[23:12:04] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[23:12:04] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[23:12:04] [PASSED] DP_REMOTE_I2C_READ with port number
[23:12:04] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[23:12:04] [PASSED] DP_REMOTE_I2C_READ with transactions array
[23:12:04] [PASSED] DP_REMOTE_I2C_WRITE with port number
[23:12:04] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[23:12:04] [PASSED] DP_REMOTE_I2C_WRITE with data array
[23:12:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[23:12:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[23:12:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[23:12:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[23:12:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[23:12:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[23:12:04] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[23:12:04] ================ [PASSED] drm_dp_mst_helper ================
[23:12:04] ================== drm_exec (7 subtests) ===================
[23:12:04] [PASSED] sanitycheck
[23:12:04] [PASSED] test_lock
[23:12:04] [PASSED] test_lock_unlock
[23:12:04] [PASSED] test_duplicates
[23:12:04] [PASSED] test_prepare
[23:12:04] [PASSED] test_prepare_array
[23:12:04] [PASSED] test_multiple_loops
[23:12:04] ==================== [PASSED] drm_exec =====================
[23:12:04] =========== drm_format_helper_test (17 subtests) ===========
[23:12:04] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[23:12:04] [PASSED] single_pixel_source_buffer
[23:12:04] [PASSED] single_pixel_clip_rectangle
[23:12:04] [PASSED] well_known_colors
[23:12:04] [PASSED] destination_pitch
[23:12:04] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[23:12:04] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[23:12:04] [PASSED] single_pixel_source_buffer
[23:12:04] [PASSED] single_pixel_clip_rectangle
[23:12:04] [PASSED] well_known_colors
[23:12:04] [PASSED] destination_pitch
[23:12:04] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[23:12:04] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[23:12:04] [PASSED] single_pixel_source_buffer
[23:12:04] [PASSED] single_pixel_clip_rectangle
[23:12:04] [PASSED] well_known_colors
[23:12:04] [PASSED] destination_pitch
[23:12:04] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[23:12:04] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[23:12:04] [PASSED] single_pixel_source_buffer
[23:12:04] [PASSED] single_pixel_clip_rectangle
[23:12:04] [PASSED] well_known_colors
[23:12:04] [PASSED] destination_pitch
[23:12:04] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[23:12:04] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[23:12:04] [PASSED] single_pixel_source_buffer
[23:12:04] [PASSED] single_pixel_clip_rectangle
[23:12:04] [PASSED] well_known_colors
[23:12:04] [PASSED] destination_pitch
[23:12:04] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[23:12:04] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[23:12:04] [PASSED] single_pixel_source_buffer
[23:12:04] [PASSED] single_pixel_clip_rectangle
[23:12:04] [PASSED] well_known_colors
[23:12:04] [PASSED] destination_pitch
[23:12:04] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[23:12:04] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[23:12:04] [PASSED] single_pixel_source_buffer
[23:12:04] [PASSED] single_pixel_clip_rectangle
[23:12:04] [PASSED] well_known_colors
[23:12:04] [PASSED] destination_pitch
[23:12:04] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[23:12:04] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[23:12:04] [PASSED] single_pixel_source_buffer
[23:12:04] [PASSED] single_pixel_clip_rectangle
[23:12:04] [PASSED] well_known_colors
[23:12:04] [PASSED] destination_pitch
[23:12:04] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[23:12:04] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[23:12:04] [PASSED] single_pixel_source_buffer
[23:12:04] [PASSED] single_pixel_clip_rectangle
[23:12:04] [PASSED] well_known_colors
[23:12:04] [PASSED] destination_pitch
[23:12:04] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[23:12:04] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[23:12:04] [PASSED] single_pixel_source_buffer
[23:12:04] [PASSED] single_pixel_clip_rectangle
[23:12:04] [PASSED] well_known_colors
[23:12:04] [PASSED] destination_pitch
[23:12:04] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[23:12:04] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[23:12:04] [PASSED] single_pixel_source_buffer
[23:12:04] [PASSED] single_pixel_clip_rectangle
[23:12:04] [PASSED] well_known_colors
[23:12:04] [PASSED] destination_pitch
[23:12:04] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[23:12:04] ============== drm_test_fb_xrgb8888_to_mono  ===============
[23:12:04] [PASSED] single_pixel_source_buffer
[23:12:04] [PASSED] single_pixel_clip_rectangle
[23:12:04] [PASSED] well_known_colors
[23:12:04] [PASSED] destination_pitch
[23:12:04] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[23:12:04] ==================== drm_test_fb_swab  =====================
[23:12:04] [PASSED] single_pixel_source_buffer
[23:12:04] [PASSED] single_pixel_clip_rectangle
[23:12:04] [PASSED] well_known_colors
[23:12:04] [PASSED] destination_pitch
[23:12:04] ================ [PASSED] drm_test_fb_swab =================
[23:12:04] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[23:12:04] [PASSED] single_pixel_source_buffer
[23:12:04] [PASSED] single_pixel_clip_rectangle
[23:12:04] [PASSED] well_known_colors
[23:12:04] [PASSED] destination_pitch
[23:12:04] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[23:12:04] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[23:12:04] [PASSED] single_pixel_source_buffer
[23:12:04] [PASSED] single_pixel_clip_rectangle
[23:12:04] [PASSED] well_known_colors
[23:12:04] [PASSED] destination_pitch
[23:12:04] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[23:12:04] ================= drm_test_fb_clip_offset  =================
[23:12:04] [PASSED] pass through
[23:12:04] [PASSED] horizontal offset
[23:12:04] [PASSED] vertical offset
[23:12:04] [PASSED] horizontal and vertical offset
[23:12:04] [PASSED] horizontal offset (custom pitch)
[23:12:04] [PASSED] vertical offset (custom pitch)
[23:12:04] [PASSED] horizontal and vertical offset (custom pitch)
[23:12:04] ============= [PASSED] drm_test_fb_clip_offset =============
[23:12:04] =================== drm_test_fb_memcpy  ====================
[23:12:04] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[23:12:04] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[23:12:04] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[23:12:04] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[23:12:04] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[23:12:04] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[23:12:04] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[23:12:04] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[23:12:04] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[23:12:04] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[23:12:04] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[23:12:04] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[23:12:04] =============== [PASSED] drm_test_fb_memcpy ================
[23:12:04] ============= [PASSED] drm_format_helper_test ==============
[23:12:04] ================= drm_format (18 subtests) =================
[23:12:04] [PASSED] drm_test_format_block_width_invalid
[23:12:04] [PASSED] drm_test_format_block_width_one_plane
[23:12:04] [PASSED] drm_test_format_block_width_two_plane
[23:12:04] [PASSED] drm_test_format_block_width_three_plane
[23:12:04] [PASSED] drm_test_format_block_width_tiled
[23:12:04] [PASSED] drm_test_format_block_height_invalid
[23:12:04] [PASSED] drm_test_format_block_height_one_plane
[23:12:04] [PASSED] drm_test_format_block_height_two_plane
[23:12:04] [PASSED] drm_test_format_block_height_three_plane
[23:12:04] [PASSED] drm_test_format_block_height_tiled
[23:12:04] [PASSED] drm_test_format_min_pitch_invalid
[23:12:04] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[23:12:04] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[23:12:04] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[23:12:04] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[23:12:04] [PASSED] drm_test_format_min_pitch_two_plane
[23:12:04] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[23:12:04] [PASSED] drm_test_format_min_pitch_tiled
[23:12:04] =================== [PASSED] drm_format ====================
[23:12:04] ============== drm_framebuffer (10 subtests) ===============
[23:12:04] ========== drm_test_framebuffer_check_src_coords  ==========
[23:12:04] [PASSED] Success: source fits into fb
[23:12:04] [PASSED] Fail: overflowing fb with x-axis coordinate
[23:12:04] [PASSED] Fail: overflowing fb with y-axis coordinate
[23:12:04] [PASSED] Fail: overflowing fb with source width
[23:12:04] [PASSED] Fail: overflowing fb with source height
[23:12:04] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[23:12:04] [PASSED] drm_test_framebuffer_cleanup
[23:12:04] =============== drm_test_framebuffer_create  ===============
[23:12:04] [PASSED] ABGR8888 normal sizes
[23:12:04] [PASSED] ABGR8888 max sizes
[23:12:04] [PASSED] ABGR8888 pitch greater than min required
[23:12:04] [PASSED] ABGR8888 pitch less than min required
[23:12:04] [PASSED] ABGR8888 Invalid width
[23:12:04] [PASSED] ABGR8888 Invalid buffer handle
[23:12:04] [PASSED] No pixel format
[23:12:04] [PASSED] ABGR8888 Width 0
[23:12:04] [PASSED] ABGR8888 Height 0
[23:12:04] [PASSED] ABGR8888 Out of bound height * pitch combination
[23:12:04] [PASSED] ABGR8888 Large buffer offset
[23:12:04] [PASSED] ABGR8888 Buffer offset for inexistent plane
[23:12:04] [PASSED] ABGR8888 Invalid flag
[23:12:04] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[23:12:04] [PASSED] ABGR8888 Valid buffer modifier
[23:12:04] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[23:12:04] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[23:12:04] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[23:12:04] [PASSED] NV12 Normal sizes
[23:12:04] [PASSED] NV12 Max sizes
[23:12:04] [PASSED] NV12 Invalid pitch
[23:12:04] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[23:12:04] [PASSED] NV12 different  modifier per-plane
[23:12:04] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[23:12:04] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[23:12:04] [PASSED] NV12 Modifier for inexistent plane
[23:12:04] [PASSED] NV12 Handle for inexistent plane
[23:12:04] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[23:12:04] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[23:12:04] [PASSED] YVU420 Normal sizes
[23:12:04] [PASSED] YVU420 Max sizes
[23:12:04] [PASSED] YVU420 Invalid pitch
[23:12:04] [PASSED] YVU420 Different pitches
[23:12:04] [PASSED] YVU420 Different buffer offsets/pitches
[23:12:04] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[23:12:04] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[23:12:04] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[23:12:04] [PASSED] YVU420 Valid modifier
[23:12:04] [PASSED] YVU420 Different modifiers per plane
[23:12:04] [PASSED] YVU420 Modifier for inexistent plane
[23:12:04] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[23:12:04] [PASSED] X0L2 Normal sizes
[23:12:04] [PASSED] X0L2 Max sizes
[23:12:04] [PASSED] X0L2 Invalid pitch
[23:12:04] [PASSED] X0L2 Pitch greater than minimum required
[23:12:04] [PASSED] X0L2 Handle for inexistent plane
[23:12:04] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[23:12:04] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[23:12:04] [PASSED] X0L2 Valid modifier
[23:12:04] [PASSED] X0L2 Modifier for inexistent plane
[23:12:04] =========== [PASSED] drm_test_framebuffer_create ===========
[23:12:04] [PASSED] drm_test_framebuffer_free
[23:12:04] [PASSED] drm_test_framebuffer_init
[23:12:04] [PASSED] drm_test_framebuffer_init_bad_format
[23:12:04] [PASSED] drm_test_framebuffer_init_dev_mismatch
[23:12:04] [PASSED] drm_test_framebuffer_lookup
[23:12:04] [PASSED] drm_test_framebuffer_lookup_inexistent
[23:12:04] [PASSED] drm_test_framebuffer_modifiers_not_supported
[23:12:04] ================= [PASSED] drm_framebuffer =================
[23:12:04] ================ drm_gem_shmem (8 subtests) ================
[23:12:04] [PASSED] drm_gem_shmem_test_obj_create
[23:12:04] [PASSED] drm_gem_shmem_test_obj_create_private
[23:12:04] [PASSED] drm_gem_shmem_test_pin_pages
[23:12:04] [PASSED] drm_gem_shmem_test_vmap
[23:12:04] [PASSED] drm_gem_shmem_test_get_pages_sgt
[23:12:04] [PASSED] drm_gem_shmem_test_get_sg_table
[23:12:04] [PASSED] drm_gem_shmem_test_madvise
[23:12:04] [PASSED] drm_gem_shmem_test_purge
[23:12:04] ================== [PASSED] drm_gem_shmem ==================
[23:12:04] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[23:12:04] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[23:12:04] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[23:12:04] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[23:12:04] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[23:12:04] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[23:12:04] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[23:12:04] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[23:12:04] [PASSED] Automatic
[23:12:04] [PASSED] Full
[23:12:04] [PASSED] Limited 16:235
[23:12:04] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[23:12:04] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[23:12:04] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[23:12:04] [PASSED] drm_test_check_disable_connector
[23:12:04] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[23:12:04] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[23:12:04] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[23:12:04] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[23:12:04] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[23:12:04] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[23:12:04] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[23:12:04] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[23:12:04] [PASSED] drm_test_check_output_bpc_dvi
[23:12:04] [PASSED] drm_test_check_output_bpc_format_vic_1
[23:12:04] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[23:12:04] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[23:12:04] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[23:12:04] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[23:12:04] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[23:12:04] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[23:12:04] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[23:12:04] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[23:12:04] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[23:12:04] [PASSED] drm_test_check_broadcast_rgb_value
[23:12:04] [PASSED] drm_test_check_bpc_8_value
[23:12:04] [PASSED] drm_test_check_bpc_10_value
[23:12:04] [PASSED] drm_test_check_bpc_12_value
[23:12:04] [PASSED] drm_test_check_format_value
[23:12:04] [PASSED] drm_test_check_tmds_char_value
[23:12:04] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[23:12:04] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[23:12:04] [PASSED] drm_test_check_mode_valid
[23:12:04] [PASSED] drm_test_check_mode_valid_reject
[23:12:04] [PASSED] drm_test_check_mode_valid_reject_rate
[23:12:04] [PASSED] drm_test_check_mode_valid_reject_max_clock
[23:12:04] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[23:12:04] ================= drm_managed (2 subtests) =================
[23:12:04] [PASSED] drm_test_managed_release_action
[23:12:04] [PASSED] drm_test_managed_run_action
[23:12:04] =================== [PASSED] drm_managed ===================
[23:12:04] =================== drm_mm (6 subtests) ====================
[23:12:04] [PASSED] drm_test_mm_init
[23:12:04] [PASSED] drm_test_mm_debug
[23:12:04] [PASSED] drm_test_mm_align32
[23:12:04] [PASSED] drm_test_mm_align64
[23:12:04] [PASSED] drm_test_mm_lowest
[23:12:04] [PASSED] drm_test_mm_highest
[23:12:04] ===================== [PASSED] drm_mm ======================
[23:12:04] ============= drm_modes_analog_tv (5 subtests) =============
[23:12:04] [PASSED] drm_test_modes_analog_tv_mono_576i
[23:12:04] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[23:12:04] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[23:12:04] [PASSED] drm_test_modes_analog_tv_pal_576i
[23:12:04] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[23:12:04] =============== [PASSED] drm_modes_analog_tv ===============
[23:12:04] ============== drm_plane_helper (2 subtests) ===============
[23:12:04] =============== drm_test_check_plane_state  ================
[23:12:04] [PASSED] clipping_simple
[23:12:04] [PASSED] clipping_rotate_reflect
[23:12:04] [PASSED] positioning_simple
[23:12:04] [PASSED] upscaling
[23:12:04] [PASSED] downscaling
[23:12:04] [PASSED] rounding1
[23:12:04] [PASSED] rounding2
[23:12:04] [PASSED] rounding3
[23:12:04] [PASSED] rounding4
[23:12:04] =========== [PASSED] drm_test_check_plane_state ============
[23:12:04] =========== drm_test_check_invalid_plane_state  ============
[23:12:04] [PASSED] positioning_invalid
[23:12:04] [PASSED] upscaling_invalid
[23:12:04] [PASSED] downscaling_invalid
[23:12:04] ======= [PASSED] drm_test_check_invalid_plane_state ========
[23:12:04] ================ [PASSED] drm_plane_helper =================
[23:12:04] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[23:12:04] ====== drm_test_connector_helper_tv_get_modes_check  =======
[23:12:04] [PASSED] None
[23:12:04] [PASSED] PAL
[23:12:04] [PASSED] NTSC
[23:12:04] [PASSED] Both, NTSC Default
[23:12:04] [PASSED] Both, PAL Default
[23:12:04] [PASSED] Both, NTSC Default, with PAL on command-line
[23:12:04] [PASSED] Both, PAL Default, with NTSC on command-line
[23:12:04] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[23:12:04] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[23:12:04] ================== drm_rect (9 subtests) ===================
[23:12:04] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[23:12:04] [PASSED] drm_test_rect_clip_scaled_not_clipped
[23:12:04] [PASSED] drm_test_rect_clip_scaled_clipped
[23:12:04] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[23:12:04] ================= drm_test_rect_intersect  =================
[23:12:04] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[23:12:04] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[23:12:04] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[23:12:04] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[23:12:04] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[23:12:04] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[23:12:04] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[23:12:04] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[23:12:04] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[23:12:04] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[23:12:04] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[23:12:04] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[23:12:04] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[23:12:04] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[23:12:04] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[23:12:04] ============= [PASSED] drm_test_rect_intersect =============
[23:12:04] ================ drm_test_rect_calc_hscale  ================
[23:12:04] [PASSED] normal use
[23:12:04] [PASSED] out of max range
[23:12:04] [PASSED] out of min range
[23:12:04] [PASSED] zero dst
[23:12:04] [PASSED] negative src
[23:12:04] [PASSED] negative dst
[23:12:04] ============ [PASSED] drm_test_rect_calc_hscale ============
[23:12:04] ================ drm_test_rect_calc_vscale  ================
[23:12:04] [PASSED] normal use
[23:12:04] [PASSED] out of max range
[23:12:04] [PASSED] out of min range
[23:12:04] [PASSED] zero dst
[23:12:04] [PASSED] negative src
stty: 'standard input': Inappropriate ioctl for device
[23:12:04] [PASSED] negative dst
[23:12:04] ============ [PASSED] drm_test_rect_calc_vscale ============
[23:12:04] ================== drm_test_rect_rotate  ===================
[23:12:04] [PASSED] reflect-x
[23:12:04] [PASSED] reflect-y
[23:12:04] [PASSED] rotate-0
[23:12:04] [PASSED] rotate-90
[23:12:04] [PASSED] rotate-180
[23:12:04] [PASSED] rotate-270
[23:12:04] ============== [PASSED] drm_test_rect_rotate ===============
[23:12:04] ================ drm_test_rect_rotate_inv  =================
[23:12:04] [PASSED] reflect-x
[23:12:04] [PASSED] reflect-y
[23:12:04] [PASSED] rotate-0
[23:12:04] [PASSED] rotate-90
[23:12:04] [PASSED] rotate-180
[23:12:04] [PASSED] rotate-270
[23:12:04] ============ [PASSED] drm_test_rect_rotate_inv =============
[23:12:04] ==================== [PASSED] drm_rect =====================
[23:12:04] ============ drm_sysfb_modeset_test (1 subtest) ============
[23:12:04] ============ drm_test_sysfb_build_fourcc_list  =============
[23:12:04] [PASSED] no native formats
[23:12:04] [PASSED] XRGB8888 as native format
[23:12:04] [PASSED] remove duplicates
[23:12:04] [PASSED] convert alpha formats
[23:12:04] [PASSED] random formats
[23:12:04] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[23:12:04] ============= [PASSED] drm_sysfb_modeset_test ==============
[23:12:04] ============================================================
[23:12:04] Testing complete. Ran 621 tests: passed: 621
[23:12:04] Elapsed time: 25.847s total, 1.742s configuring, 23.938s building, 0.143s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[23:12:04] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:12:06] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:12:15] Starting KUnit Kernel (1/1)...
[23:12:15] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:12:15] ================= ttm_device (5 subtests) ==================
[23:12:15] [PASSED] ttm_device_init_basic
[23:12:15] [PASSED] ttm_device_init_multiple
[23:12:15] [PASSED] ttm_device_fini_basic
[23:12:15] [PASSED] ttm_device_init_no_vma_man
[23:12:15] ================== ttm_device_init_pools  ==================
[23:12:15] [PASSED] No DMA allocations, no DMA32 required
[23:12:15] [PASSED] DMA allocations, DMA32 required
[23:12:15] [PASSED] No DMA allocations, DMA32 required
[23:12:15] [PASSED] DMA allocations, no DMA32 required
[23:12:15] ============== [PASSED] ttm_device_init_pools ==============
[23:12:15] =================== [PASSED] ttm_device ====================
[23:12:15] ================== ttm_pool (8 subtests) ===================
[23:12:15] ================== ttm_pool_alloc_basic  ===================
[23:12:15] [PASSED] One page
[23:12:15] [PASSED] More than one page
[23:12:15] [PASSED] Above the allocation limit
[23:12:15] [PASSED] One page, with coherent DMA mappings enabled
[23:12:15] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[23:12:15] ============== [PASSED] ttm_pool_alloc_basic ===============
[23:12:15] ============== ttm_pool_alloc_basic_dma_addr  ==============
[23:12:15] [PASSED] One page
[23:12:15] [PASSED] More than one page
[23:12:15] [PASSED] Above the allocation limit
[23:12:15] [PASSED] One page, with coherent DMA mappings enabled
[23:12:15] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[23:12:15] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[23:12:15] [PASSED] ttm_pool_alloc_order_caching_match
[23:12:15] [PASSED] ttm_pool_alloc_caching_mismatch
[23:12:15] [PASSED] ttm_pool_alloc_order_mismatch
[23:12:15] [PASSED] ttm_pool_free_dma_alloc
[23:12:15] [PASSED] ttm_pool_free_no_dma_alloc
[23:12:15] [PASSED] ttm_pool_fini_basic
[23:12:15] ==================== [PASSED] ttm_pool =====================
[23:12:15] ================ ttm_resource (8 subtests) =================
[23:12:15] ================= ttm_resource_init_basic  =================
[23:12:15] [PASSED] Init resource in TTM_PL_SYSTEM
[23:12:15] [PASSED] Init resource in TTM_PL_VRAM
[23:12:15] [PASSED] Init resource in a private placement
[23:12:15] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[23:12:15] ============= [PASSED] ttm_resource_init_basic =============
[23:12:15] [PASSED] ttm_resource_init_pinned
[23:12:15] [PASSED] ttm_resource_fini_basic
[23:12:15] [PASSED] ttm_resource_manager_init_basic
[23:12:15] [PASSED] ttm_resource_manager_usage_basic
[23:12:15] [PASSED] ttm_resource_manager_set_used_basic
[23:12:15] [PASSED] ttm_sys_man_alloc_basic
[23:12:15] [PASSED] ttm_sys_man_free_basic
[23:12:15] ================== [PASSED] ttm_resource ===================
[23:12:15] =================== ttm_tt (15 subtests) ===================
[23:12:15] ==================== ttm_tt_init_basic  ====================
[23:12:15] [PASSED] Page-aligned size
[23:12:15] [PASSED] Extra pages requested
[23:12:15] ================ [PASSED] ttm_tt_init_basic ================
[23:12:15] [PASSED] ttm_tt_init_misaligned
[23:12:15] [PASSED] ttm_tt_fini_basic
[23:12:15] [PASSED] ttm_tt_fini_sg
[23:12:15] [PASSED] ttm_tt_fini_shmem
[23:12:15] [PASSED] ttm_tt_create_basic
[23:12:15] [PASSED] ttm_tt_create_invalid_bo_type
[23:12:15] [PASSED] ttm_tt_create_ttm_exists
[23:12:15] [PASSED] ttm_tt_create_failed
[23:12:15] [PASSED] ttm_tt_destroy_basic
[23:12:15] [PASSED] ttm_tt_populate_null_ttm
[23:12:15] [PASSED] ttm_tt_populate_populated_ttm
[23:12:15] [PASSED] ttm_tt_unpopulate_basic
[23:12:15] [PASSED] ttm_tt_unpopulate_empty_ttm
[23:12:15] [PASSED] ttm_tt_swapin_basic
[23:12:15] ===================== [PASSED] ttm_tt ======================
[23:12:15] =================== ttm_bo (14 subtests) ===================
[23:12:15] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[23:12:15] [PASSED] Cannot be interrupted and sleeps
[23:12:15] [PASSED] Cannot be interrupted, locks straight away
[23:12:15] [PASSED] Can be interrupted, sleeps
[23:12:15] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[23:12:15] [PASSED] ttm_bo_reserve_locked_no_sleep
[23:12:15] [PASSED] ttm_bo_reserve_no_wait_ticket
[23:12:15] [PASSED] ttm_bo_reserve_double_resv
[23:12:15] [PASSED] ttm_bo_reserve_interrupted
[23:12:15] [PASSED] ttm_bo_reserve_deadlock
[23:12:15] [PASSED] ttm_bo_unreserve_basic
[23:12:15] [PASSED] ttm_bo_unreserve_pinned
[23:12:15] [PASSED] ttm_bo_unreserve_bulk
[23:12:15] [PASSED] ttm_bo_fini_basic
[23:12:15] [PASSED] ttm_bo_fini_shared_resv
[23:12:15] [PASSED] ttm_bo_pin_basic
[23:12:15] [PASSED] ttm_bo_pin_unpin_resource
[23:12:15] [PASSED] ttm_bo_multiple_pin_one_unpin
[23:12:15] ===================== [PASSED] ttm_bo ======================
[23:12:15] ============== ttm_bo_validate (21 subtests) ===============
[23:12:15] ============== ttm_bo_init_reserved_sys_man  ===============
[23:12:15] [PASSED] Buffer object for userspace
[23:12:15] [PASSED] Kernel buffer object
[23:12:15] [PASSED] Shared buffer object
[23:12:15] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[23:12:15] ============== ttm_bo_init_reserved_mock_man  ==============
[23:12:15] [PASSED] Buffer object for userspace
[23:12:15] [PASSED] Kernel buffer object
[23:12:15] [PASSED] Shared buffer object
[23:12:15] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[23:12:15] [PASSED] ttm_bo_init_reserved_resv
[23:12:15] ================== ttm_bo_validate_basic  ==================
[23:12:15] [PASSED] Buffer object for userspace
[23:12:15] [PASSED] Kernel buffer object
[23:12:15] [PASSED] Shared buffer object
[23:12:15] ============== [PASSED] ttm_bo_validate_basic ==============
[23:12:15] [PASSED] ttm_bo_validate_invalid_placement
[23:12:15] ============= ttm_bo_validate_same_placement  ==============
[23:12:15] [PASSED] System manager
[23:12:15] [PASSED] VRAM manager
[23:12:15] ========= [PASSED] ttm_bo_validate_same_placement ==========
[23:12:15] [PASSED] ttm_bo_validate_failed_alloc
[23:12:15] [PASSED] ttm_bo_validate_pinned
[23:12:15] [PASSED] ttm_bo_validate_busy_placement
[23:12:15] ================ ttm_bo_validate_multihop  =================
[23:12:15] [PASSED] Buffer object for userspace
[23:12:15] [PASSED] Kernel buffer object
[23:12:15] [PASSED] Shared buffer object
[23:12:15] ============ [PASSED] ttm_bo_validate_multihop =============
[23:12:15] ========== ttm_bo_validate_no_placement_signaled  ==========
[23:12:15] [PASSED] Buffer object in system domain, no page vector
[23:12:15] [PASSED] Buffer object in system domain with an existing page vector
[23:12:15] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[23:12:15] ======== ttm_bo_validate_no_placement_not_signaled  ========
[23:12:15] [PASSED] Buffer object for userspace
[23:12:15] [PASSED] Kernel buffer object
[23:12:15] [PASSED] Shared buffer object
[23:12:15] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[23:12:15] [PASSED] ttm_bo_validate_move_fence_signaled
[23:12:15] ========= ttm_bo_validate_move_fence_not_signaled  =========
[23:12:15] [PASSED] Waits for GPU
[23:12:15] [PASSED] Tries to lock straight away
[23:12:15] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[23:12:15] [PASSED] ttm_bo_validate_happy_evict
[23:12:15] [PASSED] ttm_bo_validate_all_pinned_evict
[23:12:15] [PASSED] ttm_bo_validate_allowed_only_evict
[23:12:15] [PASSED] ttm_bo_validate_deleted_evict
[23:12:15] [PASSED] ttm_bo_validate_busy_domain_evict
[23:12:15] [PASSED] ttm_bo_validate_evict_gutting
[23:12:15] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[23:12:15] ================= [PASSED] ttm_bo_validate =================
[23:12:15] ============================================================
[23:12:15] Testing complete. Ran 101 tests: passed: 101
[23:12:15] Elapsed time: 11.066s total, 1.793s configuring, 9.057s building, 0.177s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

RE: [PATCH 5/7] drm/xe: Handle missing migration VM on VM creation

[Lin, Shuicheng]

On Thurs, Oct 2, 2025 4:05 PM Stuart Summers wrote:
> Theoretically, a user could attempt to create a VM while the migration VM is
> for some reason being destroyed such that the xe_vm_create() routine gets
> called, but when we assign a migration exec queue to that VM, the VM for that
> migration exec queue is no longer there. Add an error check here for that case.
> 
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_exec_queue.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c
> b/drivers/gpu/drm/xe/xe_exec_queue.c
> index c31bc8411a71..6baa19b8051c 100644
> --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> @@ -326,6 +326,9 @@ struct xe_exec_queue
> *xe_exec_queue_create_bind(struct xe_device *xe,
>  	struct xe_vm *migrate_vm;
> 
>  	migrate_vm = xe_migrate_get_vm(tile->migrate);

If migrate_vm is NULL, the xe_vm_get() called by xe_migrate_get_vm() should already crash the kernel with NULL pointer.
Should we add the check in xe_migrate_get_vm() or xe_vm_get() also? Thanks.

Shuicheng

> +	if (!migrate_vm)
> +		return ERR_PTR(-ENODEV);
> +
>  	if (xe->info.has_usm) {
>  		struct xe_hw_engine *hwe = xe_gt_hw_engine(gt,
> 
> XE_ENGINE_CLASS_COPY,
> --
> 2.34.1

✗ Xe.CI.BAT: failure for Fix a couple of wedge corner-case memory leaks

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 13845 bytes --]

== Series Details ==

Series: Fix a couple of wedge corner-case memory leaks
URL   : https://patchwork.freedesktop.org/series/155352/
State : failure

== Summary ==

CI Bug Log - changes from xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434_BAT -> xe-pw-155352v1_BAT
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-155352v1_BAT absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-155352v1_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-155352v1_BAT:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_dma_buf_sync@export-dma-buf-once-write-sync:
    - bat-adlp-7:         [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-adlp-7/igt@xe_dma_buf_sync@export-dma-buf-once-write-sync.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-adlp-7/igt@xe_dma_buf_sync@export-dma-buf-once-write-sync.html
    - bat-lnl-2:          [PASS][3] -> [DMESG-WARN][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-lnl-2/igt@xe_dma_buf_sync@export-dma-buf-once-write-sync.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-lnl-2/igt@xe_dma_buf_sync@export-dma-buf-once-write-sync.html
    - bat-adlp-vm:        [PASS][5] -> [DMESG-WARN][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-adlp-vm/igt@xe_dma_buf_sync@export-dma-buf-once-write-sync.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-adlp-vm/igt@xe_dma_buf_sync@export-dma-buf-once-write-sync.html
    - bat-dg2-oem2:       [PASS][7] -> [ABORT][8]
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-dg2-oem2/igt@xe_dma_buf_sync@export-dma-buf-once-write-sync.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-dg2-oem2/igt@xe_dma_buf_sync@export-dma-buf-once-write-sync.html
    - bat-lnl-1:          [PASS][9] -> [DMESG-WARN][10]
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-lnl-1/igt@xe_dma_buf_sync@export-dma-buf-once-write-sync.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-lnl-1/igt@xe_dma_buf_sync@export-dma-buf-once-write-sync.html

  * igt@xe_exec_balancer@twice-cm-virtual-userptr:
    - bat-bmg-2:          [PASS][11] -> [DMESG-WARN][12] +3 other tests dmesg-warn
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-bmg-2/igt@xe_exec_balancer@twice-cm-virtual-userptr.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-bmg-2/igt@xe_exec_balancer@twice-cm-virtual-userptr.html
    - bat-atsm-2:         [PASS][13] -> [DMESG-WARN][14] +3 other tests dmesg-warn
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-atsm-2/igt@xe_exec_balancer@twice-cm-virtual-userptr.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-atsm-2/igt@xe_exec_balancer@twice-cm-virtual-userptr.html

  * igt@xe_exec_balancer@twice-virtual-userptr:
    - bat-adlp-vm:        [PASS][15] -> [ABORT][16]
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-adlp-vm/igt@xe_exec_balancer@twice-virtual-userptr.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-adlp-vm/igt@xe_exec_balancer@twice-virtual-userptr.html

  * igt@xe_exec_balancer@twice-virtual-userptr-invalidate:
    - bat-bmg-1:          [PASS][17] -> [DMESG-WARN][18] +4 other tests dmesg-warn
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-bmg-1/igt@xe_exec_balancer@twice-virtual-userptr-invalidate.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-bmg-1/igt@xe_exec_balancer@twice-virtual-userptr-invalidate.html

  * igt@xe_exec_compute_mode@twice-preempt-fence-early:
    - bat-adlp-7:         [PASS][19] -> [DMESG-FAIL][20] +10 other tests dmesg-fail
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-adlp-7/igt@xe_exec_compute_mode@twice-preempt-fence-early.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-adlp-7/igt@xe_exec_compute_mode@twice-preempt-fence-early.html

  * igt@xe_exec_compute_mode@twice-userptr-invalidate:
    - bat-atsm-2:         [PASS][21] -> [DMESG-FAIL][22] +17 other tests dmesg-fail
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-atsm-2/igt@xe_exec_compute_mode@twice-userptr-invalidate.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-atsm-2/igt@xe_exec_compute_mode@twice-userptr-invalidate.html

  * igt@xe_exec_fault_mode@many-basic:
    - bat-bmg-2:          [PASS][23] -> [TIMEOUT][24]
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-bmg-2/igt@xe_exec_fault_mode@many-basic.html
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-bmg-2/igt@xe_exec_fault_mode@many-basic.html
    - bat-bmg-1:          [PASS][25] -> [TIMEOUT][26]
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-bmg-1/igt@xe_exec_fault_mode@many-basic.html
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-bmg-1/igt@xe_exec_fault_mode@many-basic.html
    - bat-lnl-2:          [PASS][27] -> [TIMEOUT][28]
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-lnl-2/igt@xe_exec_fault_mode@many-basic.html
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-lnl-2/igt@xe_exec_fault_mode@many-basic.html

  * igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-prefetch:
    - bat-lnl-1:          [PASS][29] -> [DMESG-FAIL][30] +46 other tests dmesg-fail
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-lnl-1/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-prefetch.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-lnl-1/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-prefetch.html

  * igt@xe_exec_fault_mode@twice-rebind-prefetch:
    - bat-bmg-1:          [PASS][31] -> [DMESG-FAIL][32] +47 other tests dmesg-fail
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-bmg-1/igt@xe_exec_fault_mode@twice-rebind-prefetch.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-bmg-1/igt@xe_exec_fault_mode@twice-rebind-prefetch.html

  * igt@xe_exec_fault_mode@twice-userptr-imm:
    - bat-bmg-2:          [PASS][33] -> [DMESG-FAIL][34] +47 other tests dmesg-fail
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-bmg-2/igt@xe_exec_fault_mode@twice-userptr-imm.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-bmg-2/igt@xe_exec_fault_mode@twice-userptr-imm.html

  * igt@xe_exec_fault_mode@twice-userptr-invalidate-prefetch:
    - bat-lnl-2:          [PASS][35] -> [DMESG-FAIL][36] +45 other tests dmesg-fail
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-lnl-2/igt@xe_exec_fault_mode@twice-userptr-invalidate-prefetch.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-lnl-2/igt@xe_exec_fault_mode@twice-userptr-invalidate-prefetch.html

  * igt@xe_exec_store@basic-store:
    - bat-adlp-7:         [PASS][37] -> [ABORT][38]
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-adlp-7/igt@xe_exec_store@basic-store.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-adlp-7/igt@xe_exec_store@basic-store.html

  * igt@xe_exec_threads@threads-mixed-shared-vm-userptr-invalidate-race:
    - bat-atsm-2:         [PASS][39] -> [ABORT][40]
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-atsm-2/igt@xe_exec_threads@threads-mixed-shared-vm-userptr-invalidate-race.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-atsm-2/igt@xe_exec_threads@threads-mixed-shared-vm-userptr-invalidate-race.html
    - bat-bmg-2:          [PASS][41] -> [ABORT][42]
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-bmg-2/igt@xe_exec_threads@threads-mixed-shared-vm-userptr-invalidate-race.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-bmg-2/igt@xe_exec_threads@threads-mixed-shared-vm-userptr-invalidate-race.html

  * igt@xe_exec_threads@threads-mixed-userptr-invalidate:
    - bat-bmg-1:          [PASS][43] -> [ABORT][44]
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-bmg-1/igt@xe_exec_threads@threads-mixed-userptr-invalidate.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-bmg-1/igt@xe_exec_threads@threads-mixed-userptr-invalidate.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@xe_dma_buf_sync@export-dma-buf-once-read-write-sync:
    - {bat-ptl-vm}:       [PASS][45] -> [DMESG-WARN][46] +1 other test dmesg-warn
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-ptl-vm/igt@xe_dma_buf_sync@export-dma-buf-once-read-write-sync.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-ptl-vm/igt@xe_dma_buf_sync@export-dma-buf-once-read-write-sync.html

  * igt@xe_dma_buf_sync@export-dma-buf-once-write-sync:
    - {bat-ptl-2}:        [PASS][47] -> [DMESG-WARN][48]
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-ptl-2/igt@xe_dma_buf_sync@export-dma-buf-once-write-sync.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-ptl-2/igt@xe_dma_buf_sync@export-dma-buf-once-write-sync.html
    - {bat-ptl-1}:        [PASS][49] -> [DMESG-WARN][50]
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-ptl-1/igt@xe_dma_buf_sync@export-dma-buf-once-write-sync.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-ptl-1/igt@xe_dma_buf_sync@export-dma-buf-once-write-sync.html

  * igt@xe_exec_compute_mode@twice-bindexecqueue:
    - {bat-ptl-1}:        [PASS][51] -> [DMESG-FAIL][52] +46 other tests dmesg-fail
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-ptl-1/igt@xe_exec_compute_mode@twice-bindexecqueue.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-ptl-1/igt@xe_exec_compute_mode@twice-bindexecqueue.html

  * igt@xe_exec_fault_mode@twice-basic:
    - {bat-ptl-vm}:       [PASS][53] -> [DMESG-FAIL][54] +46 other tests dmesg-fail
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-ptl-vm/igt@xe_exec_fault_mode@twice-basic.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-ptl-vm/igt@xe_exec_fault_mode@twice-basic.html

  * igt@xe_exec_fault_mode@twice-bindexecqueue-userptr:
    - {bat-ptl-2}:        [PASS][55] -> [DMESG-FAIL][56] +46 other tests dmesg-fail
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-ptl-2/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-ptl-2/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr.html

  
Known issues
------------

  Here are the changes found in xe-pw-155352v1_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_exec_threads@threads-basic:
    - bat-bmg-2:          [PASS][57] -> [DMESG-FAIL][58] ([Intel XE#3876]) +2 other tests dmesg-fail
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-bmg-2/igt@xe_exec_threads@threads-basic.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-bmg-2/igt@xe_exec_threads@threads-basic.html

  * igt@xe_exec_threads@threads-mixed-fd-basic:
    - bat-bmg-1:          [PASS][59] -> [DMESG-FAIL][60] ([Intel XE#3876])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/bat-bmg-1/igt@xe_exec_threads@threads-mixed-fd-basic.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/bat-bmg-1/igt@xe_exec_threads@threads-mixed-fd-basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876


Build changes
-------------

  * Linux: xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434 -> xe-pw-155352v1

  IGT_8572: 8572
  xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434: 0aa5ad66ed77cd8c3bb9fb01997f68f31200f434
  xe-pw-155352v1: 155352v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/index.html

[-- Attachment #2: Type: text/html, Size: 15142 bytes --]

✗ Xe.CI.Full: failure for Fix a couple of wedge corner-case memory leaks

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 60282 bytes --]

== Series Details ==

Series: Fix a couple of wedge corner-case memory leaks
URL   : https://patchwork.freedesktop.org/series/155352/
State : failure

== Summary ==

CI Bug Log - changes from xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434_FULL -> xe-pw-155352v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-155352v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-155352v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-155352v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@device_reset@unbind-reset-rebind:
    - shard-adlp:         [PASS][1] -> [ABORT][2] +2 other tests abort
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-6/igt@device_reset@unbind-reset-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-9/igt@device_reset@unbind-reset-rebind.html

  * igt@kms_atomic_transition@modeset-transition-nonblocking-fencing:
    - shard-dg2-set2:     [PASS][3] -> [ABORT][4] +10 other tests abort
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-dg2-463/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-435/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-1:
    - shard-adlp:         [PASS][5] -> [INCOMPLETE][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-2/igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-1.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-6/igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling:
    - shard-dg2-set2:     [PASS][7] -> [DMESG-WARN][8] +47 other tests dmesg-warn
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-dg2-434/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-463/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html

  * igt@kms_pm_rpm@dpms-mode-unset-lpsp:
    - shard-lnl:          [PASS][9] -> [SKIP][10] +2 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-5/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-7/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-dg2-set2:     [PASS][11] -> [SKIP][12] +2 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-dg2-436/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-435/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_pm_rpm@legacy-planes-dpms:
    - shard-adlp:         [PASS][13] -> [SKIP][14] +1 other test skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-4/igt@kms_pm_rpm@legacy-planes-dpms.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-3/igt@kms_pm_rpm@legacy-planes-dpms.html

  * igt@kms_vblank@wait-forked-hang@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][15] +2 other tests dmesg-warn
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-434/igt@kms_vblank@wait-forked-hang@pipe-a-hdmi-a-6.html

  * igt@xe_exec_balancer@many-cm-virtual-userptr:
    - shard-dg2-set2:     [PASS][16] -> [TIMEOUT][17] +3 other tests timeout
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-dg2-434/igt@xe_exec_balancer@many-cm-virtual-userptr.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-435/igt@xe_exec_balancer@many-cm-virtual-userptr.html

  * igt@xe_exec_balancer@many-execqueues-parallel-userptr-invalidate:
    - shard-dg2-set2:     [PASS][18] -> [DMESG-FAIL][19] +51 other tests dmesg-fail
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-dg2-434/igt@xe_exec_balancer@many-execqueues-parallel-userptr-invalidate.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-463/igt@xe_exec_balancer@many-execqueues-parallel-userptr-invalidate.html

  * igt@xe_exec_balancer@twice-cm-virtual-rebind:
    - shard-bmg:          NOTRUN -> [DMESG-FAIL][20] +1 other test dmesg-fail
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-4/igt@xe_exec_balancer@twice-cm-virtual-rebind.html

  * igt@xe_exec_basic@once-null-defer-bind:
    - shard-bmg:          [PASS][21] -> [DMESG-WARN][22] +9 other tests dmesg-warn
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-4/igt@xe_exec_basic@once-null-defer-bind.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-6/igt@xe_exec_basic@once-null-defer-bind.html

  * igt@xe_exec_basic@twice-bindexecqueue:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][23] +2 other tests dmesg-warn
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-4/igt@xe_exec_basic@twice-bindexecqueue.html

  * igt@xe_exec_compute_mode@many-userptr:
    - shard-adlp:         [PASS][24] -> [DMESG-FAIL][25] +40 other tests dmesg-fail
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-2/igt@xe_exec_compute_mode@many-userptr.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-6/igt@xe_exec_compute_mode@many-userptr.html

  * igt@xe_exec_compute_mode@many-userptr-unmap:
    - shard-adlp:         [PASS][26] -> [TIMEOUT][27]
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-2/igt@xe_exec_compute_mode@many-userptr-unmap.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-3/igt@xe_exec_compute_mode@many-userptr-unmap.html

  * igt@xe_exec_compute_mode@once-bindexecqueue-userptr:
    - shard-dg2-set2:     [PASS][28] -> [FAIL][29]
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-dg2-434/igt@xe_exec_compute_mode@once-bindexecqueue-userptr.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-435/igt@xe_exec_compute_mode@once-bindexecqueue-userptr.html

  * igt@xe_exec_fault_mode@many-basic-prefetch:
    - shard-bmg:          NOTRUN -> [TIMEOUT][30]
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-4/igt@xe_exec_fault_mode@many-basic-prefetch.html

  * igt@xe_exec_store@long-shader-bb-check@gt0-drm_xe_engine_class_compute0-bb-system-target-system:
    - shard-dg2-set2:     [PASS][31] -> [INCOMPLETE][32]
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-dg2-434/igt@xe_exec_store@long-shader-bb-check@gt0-drm_xe_engine_class_compute0-bb-system-target-system.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-434/igt@xe_exec_store@long-shader-bb-check@gt0-drm_xe_engine_class_compute0-bb-system-target-system.html

  * igt@xe_exec_system_allocator@many-large-malloc-busy-nomemset:
    - shard-bmg:          [PASS][33] -> [FAIL][34]
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-1/igt@xe_exec_system_allocator@many-large-malloc-busy-nomemset.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-3/igt@xe_exec_system_allocator@many-large-malloc-busy-nomemset.html

  * igt@xe_exec_system_allocator@many-malloc-fork-read-after:
    - shard-lnl:          [PASS][35] -> [DMESG-FAIL][36] +82 other tests dmesg-fail
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-8/igt@xe_exec_system_allocator@many-malloc-fork-read-after.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-1/igt@xe_exec_system_allocator@many-malloc-fork-read-after.html

  * igt@xe_exec_system_allocator@process-many-large-execqueues-malloc-mlock-nomemset:
    - shard-bmg:          NOTRUN -> [ABORT][37]
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-4/igt@xe_exec_system_allocator@process-many-large-execqueues-malloc-mlock-nomemset.html

  * igt@xe_exec_system_allocator@process-many-mmap-shared-remap:
    - shard-bmg:          [PASS][38] -> [ABORT][39] +17 other tests abort
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-5/igt@xe_exec_system_allocator@process-many-mmap-shared-remap.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-6/igt@xe_exec_system_allocator@process-many-mmap-shared-remap.html

  * igt@xe_exec_system_allocator@threads-many-large-execqueues-free-nomemset:
    - shard-lnl:          [PASS][40] -> [ABORT][41] +19 other tests abort
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-2/igt@xe_exec_system_allocator@threads-many-large-execqueues-free-nomemset.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-3/igt@xe_exec_system_allocator@threads-many-large-execqueues-free-nomemset.html

  * igt@xe_exec_system_allocator@twice-mmap-new-race-nomemset:
    - shard-bmg:          [PASS][42] -> [DMESG-FAIL][43] +65 other tests dmesg-fail
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-4/igt@xe_exec_system_allocator@twice-mmap-new-race-nomemset.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-7/igt@xe_exec_system_allocator@twice-mmap-new-race-nomemset.html

  * igt@xe_exec_threads@threads-bal-userptr-invalidate:
    - shard-lnl:          [PASS][44] -> [DMESG-WARN][45] +14 other tests dmesg-warn
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-5/igt@xe_exec_threads@threads-bal-userptr-invalidate.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-7/igt@xe_exec_threads@threads-bal-userptr-invalidate.html

  * igt@xe_pmu@engine-activity-single-load@engine-drm_xe_engine_class_video_enhance0:
    - shard-adlp:         [PASS][46] -> [FAIL][47] +3 other tests fail
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-1/igt@xe_pmu@engine-activity-single-load@engine-drm_xe_engine_class_video_enhance0.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-2/igt@xe_pmu@engine-activity-single-load@engine-drm_xe_engine_class_video_enhance0.html

  * igt@xe_vm@large-split-misaligned-binds-1073741824:
    - shard-adlp:         [PASS][48] -> [DMESG-WARN][49] +41 other tests dmesg-warn
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-8/igt@xe_vm@large-split-misaligned-binds-1073741824.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-2/igt@xe_vm@large-split-misaligned-binds-1073741824.html

  
#### Warnings ####

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-bmg:          [SKIP][50] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836]) -> [SKIP][51]
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-2/igt@kms_pm_rpm@modeset-lpsp.html
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-4/igt@kms_pm_rpm@modeset-lpsp.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_pipe_stress@stress-xrgb8888-xtiled}:
    - shard-adlp:         [PASS][52] -> [DMESG-WARN][53]
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-8/igt@kms_pipe_stress@stress-xrgb8888-xtiled.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-1/igt@kms_pipe_stress@stress-xrgb8888-xtiled.html
    - shard-dg2-set2:     [PASS][54] -> [DMESG-WARN][55]
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-dg2-464/igt@kms_pipe_stress@stress-xrgb8888-xtiled.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-466/igt@kms_pipe_stress@stress-xrgb8888-xtiled.html

  * {igt@xe_configfs@ctx-restore-post-bb-invalid}:
    - shard-lnl:          [PASS][56] -> [ABORT][57] +4 other tests abort
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-7/igt@xe_configfs@ctx-restore-post-bb-invalid.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-1/igt@xe_configfs@ctx-restore-post-bb-invalid.html
    - shard-adlp:         [PASS][58] -> [ABORT][59]
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-3/igt@xe_configfs@ctx-restore-post-bb-invalid.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-9/igt@xe_configfs@ctx-restore-post-bb-invalid.html

  * {igt@xe_exec_system_allocator@many-64k-mmap-remap-ro-dontunmap}:
    - shard-bmg:          [PASS][60] -> [DMESG-FAIL][61] +10 other tests dmesg-fail
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-6/igt@xe_exec_system_allocator@many-64k-mmap-remap-ro-dontunmap.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-7/igt@xe_exec_system_allocator@many-64k-mmap-remap-ro-dontunmap.html

  * {igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-free-madvise}:
    - shard-bmg:          [PASS][62] -> [ABORT][63] +3 other tests abort
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-5/igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-free-madvise.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-6/igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-free-madvise.html

  * {igt@xe_exec_system_allocator@twice-large-free-madvise}:
    - shard-lnl:          [PASS][64] -> [DMESG-FAIL][65] +14 other tests dmesg-fail
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-4/igt@xe_exec_system_allocator@twice-large-free-madvise.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-5/igt@xe_exec_system_allocator@twice-large-free-madvise.html

  * {igt@xe_fault_injection@inject-fault-probe-function-guc_wait_ucode}:
    - shard-dg2-set2:     [PASS][66] -> [ABORT][67] +1 other test abort
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-dg2-433/igt@xe_fault_injection@inject-fault-probe-function-guc_wait_ucode.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-434/igt@xe_fault_injection@inject-fault-probe-function-guc_wait_ucode.html

  
Known issues
------------

  Here are the changes found in xe-pw-155352v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@hotreplug:
    - shard-dg2-set2:     [PASS][68] -> [ABORT][69] ([Intel XE#5466])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-dg2-464/igt@core_hotunplug@hotreplug.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-466/igt@core_hotunplug@hotreplug.html

  * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1:
    - shard-adlp:         [PASS][70] -> [FAIL][71] ([Intel XE#3908]) +3 other tests fail
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-3/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-4/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html

  * igt@kms_bw@linear-tiling-1-displays-1920x1080p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][72] ([Intel XE#367])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-464/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html

  * igt@kms_ccs@bad-rotation-90-yf-tiled-ccs@pipe-c-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][73] ([Intel XE#787]) +97 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-432/igt@kms_ccs@bad-rotation-90-yf-tiled-ccs@pipe-c-dp-2.html

  * igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][74] ([Intel XE#455] / [Intel XE#787]) +13 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-432/igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-2.html

  * igt@kms_ccs@random-ccs-data-y-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#2887])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-4/igt@kms_ccs@random-ccs-data-y-tiled-ccs.html

  * igt@kms_cdclk@mode-transition@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][76] ([Intel XE#4417]) +3 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-434/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html

  * igt@kms_content_protection@atomic@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][77] ([Intel XE#1178])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-1/igt@kms_content_protection@atomic@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-suspend:
    - shard-adlp:         [PASS][78] -> [INCOMPLETE][79] ([Intel XE#5545])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-2/igt@kms_cursor_crc@cursor-suspend.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-6/igt@kms_cursor_crc@cursor-suspend.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1:
    - shard-adlp:         [PASS][80] -> [DMESG-FAIL][81] ([Intel XE#5545])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-2/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-6/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
    - shard-dg2-set2:     [PASS][82] -> [INCOMPLETE][83] ([Intel XE#3226])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-dg2-435/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-433/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html

  * igt@kms_flip@2x-flip-vs-rmfb-interruptible:
    - shard-bmg:          [PASS][84] -> [SKIP][85] ([Intel XE#2316])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-4/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-6/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html

  * igt@kms_flip@basic-flip-vs-wf_vblank:
    - shard-adlp:         [PASS][86] -> [DMESG-WARN][87] ([Intel XE#4543]) +2 other tests dmesg-warn
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-3/igt@kms_flip@basic-flip-vs-wf_vblank.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-2/igt@kms_flip@basic-flip-vs-wf_vblank.html

  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
    - shard-adlp:         [PASS][88] -> [ABORT][89] ([Intel XE#3970]) +1 other test abort
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-3/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-9/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][90] ([Intel XE#651])
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][91] ([Intel XE#653])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          NOTRUN -> [SKIP][92] ([Intel XE#2313])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64:
    - shard-dg2-set2:     NOTRUN -> [FAIL][93] ([Intel XE#616]) +3 other tests fail
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-434/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64.html

  * igt@kms_plane_lowres@tiling-x:
    - shard-dg2-set2:     [PASS][94] -> [DMESG-WARN][95] ([Intel XE#5681])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-dg2-432/igt@kms_plane_lowres@tiling-x.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-434/igt@kms_plane_lowres@tiling-x.html

  * igt@kms_pm_rpm@basic-pci-d3-state:
    - shard-adlp:         [PASS][96] -> [ABORT][97] ([Intel XE#5545])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-8/igt@kms_pm_rpm@basic-pci-d3-state.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-1/igt@kms_pm_rpm@basic-pci-d3-state.html

  * igt@kms_vblank@query-forked-hang@pipe-a-hdmi-a-1:
    - shard-adlp:         [PASS][98] -> [DMESG-WARN][99] ([Intel XE#2953] / [Intel XE#4173]) +1 other test dmesg-warn
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-9/igt@kms_vblank@query-forked-hang@pipe-a-hdmi-a-1.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-4/igt@kms_vblank@query-forked-hang@pipe-a-hdmi-a-1.html

  * igt@xe_eudebug_online@reset-with-attention:
    - shard-bmg:          NOTRUN -> [SKIP][100] ([Intel XE#4837])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-4/igt@xe_eudebug_online@reset-with-attention.html

  * igt@xe_exec_basic@multigpu-no-exec-null-defer-bind:
    - shard-dg2-set2:     [PASS][101] -> [SKIP][102] ([Intel XE#1392]) +4 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-dg2-436/igt@xe_exec_basic@multigpu-no-exec-null-defer-bind.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-null-defer-bind.html

  * igt@xe_exec_compute_mode@many-execqueues-preempt-fence-early:
    - shard-adlp:         [PASS][103] -> [FAIL][104] ([Intel XE#5625])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-9/igt@xe_exec_compute_mode@many-execqueues-preempt-fence-early.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-6/igt@xe_exec_compute_mode@many-execqueues-preempt-fence-early.html

  * igt@xe_exec_compute_mode@many-userptr-invalidate-race:
    - shard-adlp:         [PASS][105] -> [ABORT][106] ([Intel XE#5790])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-6/igt@xe_exec_compute_mode@many-userptr-invalidate-race.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-1/igt@xe_exec_compute_mode@many-userptr-invalidate-race.html

  * igt@xe_exec_fault_mode@many-invalid-userptr-fault:
    - shard-dg2-set2:     NOTRUN -> [SKIP][107] ([Intel XE#288])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-464/igt@xe_exec_fault_mode@many-invalid-userptr-fault.html

  * igt@xe_exec_system_allocator@many-large-execqueues-mmap-file-mlock-nomemset:
    - shard-dg2-set2:     NOTRUN -> [SKIP][108] ([Intel XE#4915]) +9 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-464/igt@xe_exec_system_allocator@many-large-execqueues-mmap-file-mlock-nomemset.html

  * igt@xe_exec_system_allocator@threads-many-large-execqueues-new:
    - shard-bmg:          [PASS][109] -> [ABORT][110] ([Intel XE#3970])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-7/igt@xe_exec_system_allocator@threads-many-large-execqueues-new.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-2/igt@xe_exec_system_allocator@threads-many-large-execqueues-new.html

  * igt@xe_exec_threads@threads-bal-mixed-fd-rebind:
    - shard-bmg:          [PASS][111] -> [DMESG-FAIL][112] ([Intel XE#3876]) +3 other tests dmesg-fail
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-7/igt@xe_exec_threads@threads-bal-mixed-fd-rebind.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-3/igt@xe_exec_threads@threads-bal-mixed-fd-rebind.html

  * igt@xe_exec_threads@threads-bal-userptr-invalidate:
    - shard-dg2-set2:     [PASS][113] -> [DMESG-FAIL][114] ([Intel XE#3876])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-dg2-463/igt@xe_exec_threads@threads-bal-userptr-invalidate.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-464/igt@xe_exec_threads@threads-bal-userptr-invalidate.html

  * igt@xe_exec_threads@threads-mixed-fd-userptr-invalidate:
    - shard-adlp:         [PASS][115] -> [DMESG-FAIL][116] ([Intel XE#3876]) +9 other tests dmesg-fail
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-8/igt@xe_exec_threads@threads-mixed-fd-userptr-invalidate.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-1/igt@xe_exec_threads@threads-mixed-fd-userptr-invalidate.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_guc_ads_init:
    - shard-adlp:         [PASS][117] -> [ABORT][118] ([Intel XE#5530]) +5 other tests abort
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-2/igt@xe_fault_injection@inject-fault-probe-function-xe_guc_ads_init.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-8/igt@xe_fault_injection@inject-fault-probe-function-xe_guc_ads_init.html

  * igt@xe_pm@s2idle-vm-bind-unbind-all:
    - shard-adlp:         [PASS][119] -> [DMESG-WARN][120] ([Intel XE#4504])
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-2/igt@xe_pm@s2idle-vm-bind-unbind-all.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-8/igt@xe_pm@s2idle-vm-bind-unbind-all.html

  * igt@xe_pxp@pxp-stale-bo-bind-post-rpm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][121] ([Intel XE#4733])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-464/igt@xe_pxp@pxp-stale-bo-bind-post-rpm.html

  
#### Possible fixes ####

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [INCOMPLETE][122] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345]) -> [PASS][123]
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-dp-4:
    - shard-dg2-set2:     [INCOMPLETE][124] ([Intel XE#6014]) -> [PASS][125]
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-dp-4.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     [DMESG-WARN][126] ([Intel XE#1727] / [Intel XE#3113]) -> [PASS][127]
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-6.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-6.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-bmg:          [SKIP][128] ([Intel XE#2316]) -> [PASS][129]
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-7/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][130] ([Intel XE#4543]) -> [PASS][131] +1 other test pass
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-4/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a1.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-adlp:         [DMESG-WARN][132] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][133] +1 other test pass
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-3/igt@kms_flip@flip-vs-suspend-interruptible.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-4/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@xe_exec_basic@multigpu-once-null-rebind:
    - shard-dg2-set2:     [SKIP][134] ([Intel XE#1392]) -> [PASS][135] +2 other tests pass
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-dg2-432/igt@xe_exec_basic@multigpu-once-null-rebind.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-dg2-434/igt@xe_exec_basic@multigpu-once-null-rebind.html

  * igt@xe_exec_reset@parallel-gt-reset:
    - shard-adlp:         [DMESG-WARN][136] ([Intel XE#3876]) -> [PASS][137]
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-8/igt@xe_exec_reset@parallel-gt-reset.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-6/igt@xe_exec_reset@parallel-gt-reset.html

  * igt@xe_module_load@load:
    - shard-lnl:          ([PASS][138], [PASS][139], [PASS][140], [PASS][141], [PASS][142], [PASS][143], [PASS][144], [PASS][145], [PASS][146], [PASS][147], [SKIP][148], [PASS][149], [PASS][150], [PASS][151], [PASS][152], [PASS][153], [PASS][154], [PASS][155], [PASS][156], [PASS][157], [PASS][158], [PASS][159], [PASS][160], [PASS][161], [PASS][162], [PASS][163]) ([Intel XE#378]) -> ([PASS][164], [PASS][165], [PASS][166], [PASS][167], [PASS][168], [PASS][169], [PASS][170], [PASS][171], [PASS][172], [PASS][173], [PASS][174], [PASS][175], [PASS][176], [PASS][177], [PASS][178], [PASS][179], [PASS][180], [PASS][181], [PASS][182], [PASS][183], [PASS][184], [PASS][185], [PASS][186], [PASS][187], [PASS][188])
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-1/igt@xe_module_load@load.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-7/igt@xe_module_load@load.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-7/igt@xe_module_load@load.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-3/igt@xe_module_load@load.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-4/igt@xe_module_load@load.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-4/igt@xe_module_load@load.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-4/igt@xe_module_load@load.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-1/igt@xe_module_load@load.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-1/igt@xe_module_load@load.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-8/igt@xe_module_load@load.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-8/igt@xe_module_load@load.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-4/igt@xe_module_load@load.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-7/igt@xe_module_load@load.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-5/igt@xe_module_load@load.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-5/igt@xe_module_load@load.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-2/igt@xe_module_load@load.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-2/igt@xe_module_load@load.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-3/igt@xe_module_load@load.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-2/igt@xe_module_load@load.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-3/igt@xe_module_load@load.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-8/igt@xe_module_load@load.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-7/igt@xe_module_load@load.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-5/igt@xe_module_load@load.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-5/igt@xe_module_load@load.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-8/igt@xe_module_load@load.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-lnl-8/igt@xe_module_load@load.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-5/igt@xe_module_load@load.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-5/igt@xe_module_load@load.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-7/igt@xe_module_load@load.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-7/igt@xe_module_load@load.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-2/igt@xe_module_load@load.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-8/igt@xe_module_load@load.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-8/igt@xe_module_load@load.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-7/igt@xe_module_load@load.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-7/igt@xe_module_load@load.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-4/igt@xe_module_load@load.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-3/igt@xe_module_load@load.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-4/igt@xe_module_load@load.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-4/igt@xe_module_load@load.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-3/igt@xe_module_load@load.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-3/igt@xe_module_load@load.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-4/igt@xe_module_load@load.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-2/igt@xe_module_load@load.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-8/igt@xe_module_load@load.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-1/igt@xe_module_load@load.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-3/igt@xe_module_load@load.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-1/igt@xe_module_load@load.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-1/igt@xe_module_load@load.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-2/igt@xe_module_load@load.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-1/igt@xe_module_load@load.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-lnl-5/igt@xe_module_load@load.html
    - shard-bmg:          ([PASS][189], [PASS][190], [PASS][191], [PASS][192], [PASS][193], [PASS][194], [PASS][195], [PASS][196], [PASS][197], [PASS][198], [PASS][199], [PASS][200], [PASS][201], [PASS][202], [PASS][203], [PASS][204], [PASS][205], [PASS][206], [PASS][207], [PASS][208], [PASS][209], [PASS][210], [PASS][211], [SKIP][212], [PASS][213]) ([Intel XE#2457]) -> ([PASS][214], [PASS][215], [PASS][216], [PASS][217], [PASS][218], [PASS][219], [PASS][220], [PASS][221], [PASS][222], [PASS][223], [PASS][224], [PASS][225], [PASS][226], [PASS][227], [PASS][228], [PASS][229], [PASS][230], [PASS][231], [PASS][232], [PASS][233], [PASS][234], [PASS][235], [PASS][236], [PASS][237])
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-3/igt@xe_module_load@load.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-3/igt@xe_module_load@load.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-2/igt@xe_module_load@load.html
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-7/igt@xe_module_load@load.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-7/igt@xe_module_load@load.html
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-7/igt@xe_module_load@load.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-1/igt@xe_module_load@load.html
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-1/igt@xe_module_load@load.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-8/igt@xe_module_load@load.html
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-8/igt@xe_module_load@load.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-4/igt@xe_module_load@load.html
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-4/igt@xe_module_load@load.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-5/igt@xe_module_load@load.html
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-5/igt@xe_module_load@load.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-6/igt@xe_module_load@load.html
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-1/igt@xe_module_load@load.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-7/igt@xe_module_load@load.html
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-2/igt@xe_module_load@load.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-3/igt@xe_module_load@load.html
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-2/igt@xe_module_load@load.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-5/igt@xe_module_load@load.html
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-6/igt@xe_module_load@load.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-6/igt@xe_module_load@load.html
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-6/igt@xe_module_load@load.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-5/igt@xe_module_load@load.html
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-7/igt@xe_module_load@load.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-3/igt@xe_module_load@load.html
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-1/igt@xe_module_load@load.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-5/igt@xe_module_load@load.html
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-5/igt@xe_module_load@load.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-7/igt@xe_module_load@load.html
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-4/igt@xe_module_load@load.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-4/igt@xe_module_load@load.html
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-8/igt@xe_module_load@load.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-8/igt@xe_module_load@load.html
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-8/igt@xe_module_load@load.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-6/igt@xe_module_load@load.html
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-6/igt@xe_module_load@load.html
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-3/igt@xe_module_load@load.html
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-2/igt@xe_module_load@load.html
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-5/igt@xe_module_load@load.html
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-2/igt@xe_module_load@load.html
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-2/igt@xe_module_load@load.html
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-4/igt@xe_module_load@load.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-2/igt@xe_module_load@load.html
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-3/igt@xe_module_load@load.html
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-1/igt@xe_module_load@load.html
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-6/igt@xe_module_load@load.html
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-1/igt@xe_module_load@load.html
    - shard-adlp:         ([PASS][238], [PASS][239], [PASS][240], [PASS][241], [PASS][242], [PASS][243], [PASS][244], [PASS][245], [PASS][246], [PASS][247], [PASS][248], [PASS][249], [PASS][250], [PASS][251], [PASS][252], [PASS][253], [PASS][254], [PASS][255], [PASS][256], [SKIP][257], [PASS][258], [PASS][259], [PASS][260], [PASS][261], [PASS][262], [PASS][263]) ([Intel XE#378] / [Intel XE#5612]) -> ([PASS][264], [PASS][265], [PASS][266], [PASS][267], [PASS][268], [PASS][269], [PASS][270], [PASS][271], [PASS][272], [PASS][273], [PASS][274], [PASS][275], [PASS][276], [PASS][277], [PASS][278], [PASS][279], [PASS][280], [PASS][281], [PASS][282], [PASS][283], [PASS][284], [PASS][285], [PASS][286], [PASS][287], [PASS][288])
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-3/igt@xe_module_load@load.html
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-2/igt@xe_module_load@load.html
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-2/igt@xe_module_load@load.html
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-2/igt@xe_module_load@load.html
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-4/igt@xe_module_load@load.html
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-4/igt@xe_module_load@load.html
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-2/igt@xe_module_load@load.html
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-9/igt@xe_module_load@load.html
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-9/igt@xe_module_load@load.html
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-3/igt@xe_module_load@load.html
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-3/igt@xe_module_load@load.html
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-6/igt@xe_module_load@load.html
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-1/igt@xe_module_load@load.html
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-8/igt@xe_module_load@load.html
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-8/igt@xe_module_load@load.html
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-3/igt@xe_module_load@load.html
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-6/igt@xe_module_load@load.html
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-6/igt@xe_module_load@load.html
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-1/igt@xe_module_load@load.html
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-8/igt@xe_module_load@load.html
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-9/igt@xe_module_load@load.html
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-4/igt@xe_module_load@load.html
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-1/igt@xe_module_load@load.html
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-1/igt@xe_module_load@load.html
   [262]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-8/igt@xe_module_load@load.html
   [263]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-9/igt@xe_module_load@load.html
   [264]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-9/igt@xe_module_load@load.html
   [265]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-4/igt@xe_module_load@load.html
   [266]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-8/igt@xe_module_load@load.html
   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-8/igt@xe_module_load@load.html
   [268]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-4/igt@xe_module_load@load.html
   [269]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-1/igt@xe_module_load@load.html
   [270]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-6/igt@xe_module_load@load.html
   [271]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-9/igt@xe_module_load@load.html
   [272]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-6/igt@xe_module_load@load.html
   [273]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-6/igt@xe_module_load@load.html
   [274]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-9/igt@xe_module_load@load.html
   [275]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-9/igt@xe_module_load@load.html
   [276]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-6/igt@xe_module_load@load.html
   [277]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-8/igt@xe_module_load@load.html
   [278]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-2/igt@xe_module_load@load.html
   [279]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-8/igt@xe_module_load@load.html
   [280]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-2/igt@xe_module_load@load.html
   [281]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-2/igt@xe_module_load@load.html
   [282]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-3/igt@xe_module_load@load.html
   [283]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-3/igt@xe_module_load@load.html
   [284]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-1/igt@xe_module_load@load.html
   [285]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-2/igt@xe_module_load@load.html
   [286]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-1/igt@xe_module_load@load.html
   [287]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-3/igt@xe_module_load@load.html
   [288]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-4/igt@xe_module_load@load.html

  
#### Warnings ####

  * igt@kms_big_fb@x-tiled-8bpp-rotate-0:
    - shard-adlp:         [DMESG-FAIL][289] ([Intel XE#4543]) -> [DMESG-WARN][290] ([Intel XE#4543])
   [289]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-2/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
   [290]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-3/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html

  * igt@kms_content_protection@atomic:
    - shard-bmg:          [SKIP][291] ([Intel XE#2341]) -> [FAIL][292] ([Intel XE#1178])
   [291]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-6/igt@kms_content_protection@atomic.html
   [292]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-1/igt@kms_content_protection@atomic.html

  * igt@kms_flip@flip-vs-rmfb:
    - shard-adlp:         [DMESG-WARN][293] ([Intel XE#4543] / [Intel XE#5208]) -> [DMESG-WARN][294] ([Intel XE#5208])
   [293]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-8/igt@kms_flip@flip-vs-rmfb.html
   [294]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-6/igt@kms_flip@flip-vs-rmfb.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][295] ([Intel XE#2311]) -> [SKIP][296] ([Intel XE#2312])
   [295]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-plflip-blt.html
   [296]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-msflip-blt:
    - shard-bmg:          [SKIP][297] ([Intel XE#2312]) -> [SKIP][298] ([Intel XE#2311]) +1 other test skip
   [297]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-msflip-blt.html
   [298]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-msflip-blt.html

  * igt@xe_pm@d3cold-basic-exec:
    - shard-adlp:         [SKIP][299] ([Intel XE#2284] / [Intel XE#366]) -> [ABORT][300] ([Intel XE#5545])
   [299]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434/shard-adlp-4/igt@xe_pm@d3cold-basic-exec.html
   [300]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/shard-adlp-1/igt@xe_pm@d3cold-basic-exec.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3226]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3226
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
  [Intel XE#3908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3908
  [Intel XE#3970]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3970
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4417
  [Intel XE#4504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4504
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
  [Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
  [Intel XE#5530]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5530
  [Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
  [Intel XE#5612]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5612
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#5681]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5681
  [Intel XE#5790]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5790
  [Intel XE#6014]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6014
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#6192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6192
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836


Build changes
-------------

  * Linux: xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434 -> xe-pw-155352v1

  IGT_8572: 8572
  xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434: 0aa5ad66ed77cd8c3bb9fb01997f68f31200f434
  xe-pw-155352v1: 155352v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/index.html

[-- Attachment #2: Type: text/html, Size: 64483 bytes --]

Re: [PATCH 5/7] drm/xe: Handle missing migration VM on VM creation

[Matthew Brost]

On Thu, Oct 02, 2025 at 11:34:29PM +0000, Lin, Shuicheng wrote:
> On Thurs, Oct 2, 2025 4:05 PM Stuart Summers wrote:
> > Theoretically, a user could attempt to create a VM while the migration VM is
> > for some reason being destroyed such that the xe_vm_create() routine gets
> > called, but when we assign a migration exec queue to that VM, the VM for that
> > migration exec queue is no longer there. Add an error check here for that case.
> > 
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_exec_queue.c | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c
> > b/drivers/gpu/drm/xe/xe_exec_queue.c
> > index c31bc8411a71..6baa19b8051c 100644
> > --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> > +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> > @@ -326,6 +326,9 @@ struct xe_exec_queue
> > *xe_exec_queue_create_bind(struct xe_device *xe,
> >  	struct xe_vm *migrate_vm;
> > 
> >  	migrate_vm = xe_migrate_get_vm(tile->migrate);
> 
> If migrate_vm is NULL, the xe_vm_get() called by xe_migrate_get_vm() should already crash the kernel with NULL pointer.
> Should we add the check in xe_migrate_get_vm() or xe_vm_get() also? Thanks.
> 

I'm not really convinecned this possible as migration VM is tied to
driver being loaded / bound. I don't think you should be able to unload
the driver or hotplug it if an IOCTL is running. Has this problem show
up during testing? If so, it likely points to an issue somewhere else.

Matt 

> Shuicheng
> 
> > +	if (!migrate_vm)
> > +		return ERR_PTR(-ENODEV);
> > +
> >  	if (xe->info.has_usm) {
> >  		struct xe_hw_engine *hwe = xe_gt_hw_engine(gt,
> > 
> > XE_ENGINE_CLASS_COPY,
> > --
> > 2.34.1
> 

Re: [PATCH 5/7] drm/xe: Handle missing migration VM on VM creation

[Summers, Stuart]

On Thu, 2025-10-02 at 23:56 -0700, Matthew Brost wrote:
> On Thu, Oct 02, 2025 at 11:34:29PM +0000, Lin, Shuicheng wrote:
> > On Thurs, Oct 2, 2025 4:05 PM Stuart Summers wrote:
> > > Theoretically, a user could attempt to create a VM while the
> > > migration VM is
> > > for some reason being destroyed such that the xe_vm_create()
> > > routine gets
> > > called, but when we assign a migration exec queue to that VM, the
> > > VM for that
> > > migration exec queue is no longer there. Add an error check here
> > > for that case.
> > > 
> > > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > > ---
> > >  drivers/gpu/drm/xe/xe_exec_queue.c | 3 +++
> > >  1 file changed, 3 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c
> > > b/drivers/gpu/drm/xe/xe_exec_queue.c
> > > index c31bc8411a71..6baa19b8051c 100644
> > > --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> > > +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> > > @@ -326,6 +326,9 @@ struct xe_exec_queue
> > > *xe_exec_queue_create_bind(struct xe_device *xe,
> > >         struct xe_vm *migrate_vm;
> > > 
> > >         migrate_vm = xe_migrate_get_vm(tile->migrate);
> > 
> > If migrate_vm is NULL, the xe_vm_get() called by
> > xe_migrate_get_vm() should already crash the kernel with NULL
> > pointer.
> > Should we add the check in xe_migrate_get_vm() or xe_vm_get() also?
> > Thanks.

Yeah I guess I wanted to keep the get and put agnostic, similar to how
we do the get and put in other parts of the driver for other data
structures.

> > 
> 
> I'm not really convinecned this possible as migration VM is tied to
> driver being loaded / bound. I don't think you should be able to
> unload
> the driver or hotplug it if an IOCTL is running. Has this problem
> show
> up during testing? If so, it likely points to an issue somewhere
> else.

No I didn't see this in live testing. I just wanted to make sure this
wasn't causing some issue. The scenario I'm debugging is in the event
we have either a hotplug or the BARs otherwise get dropped out from
under us (i.e. return all 0xf's) due to a hardware failure or
otherwise. If that happens in the middle of a VM creation, for
instance, I wanted to be extra sure we weren't missing something here.

But yeah you're right and that's why I had labeled this theoretical.
I'm not married to this change specifically so if you feel strongly we
don't want it, I'm happy to drop it. The main two fixes are the last
two patches in the series.

Thanks,
Stuart

> 
> Matt 
> 
> > Shuicheng
> > 
> > > +       if (!migrate_vm)
> > > +               return ERR_PTR(-ENODEV);
> > > +
> > >         if (xe->info.has_usm) {
> > >                 struct xe_hw_engine *hwe = xe_gt_hw_engine(gt,
> > > 
> > > XE_ENGINE_CLASS_COPY,
> > > --
> > > 2.34.1
> > 

Re: Xe.CI.Full: failure for Fix a couple of wedge corner-case memory leaks

[Summers, Stuart]

On Fri, 2025-10-03 at 02:16 +0000, Patchwork wrote:
> Patch Details
> Series: Fix a couple of wedge corner-case memory leaks URL:
> https://patchwork.freedesktop.org/series/155352/ State: failure
> Details:
> https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155352v1/index.html 
> CI Bug Log - changes from xe-3859-
> 0aa5ad66ed77cd8c3bb9fb01997f68f31200f434_FULL -> xe-pw-
> 155352v1_FULLSummaryFAILURE
> Serious unknown changes coming with xe-pw-155352v1_FULL absolutely
> need to be
>  verified manually.
> If you think the reported changes have nothing to do with the changes
>  introduced in xe-pw-155352v1_FULL, please notify your bug team
> (I915-ci-infra@lists.freedesktop.org) to allow them
>  to document this new failure mode, which will reduce false positives
> in CI.
> Participating hosts (4 -> 4)No changes in participating hosts
> Possible new issuesHere are the unknown changes that may have been
> introduced in xe-pw-155352v1_FULL:
> IGT changesPossible regressions *
> igt@device_reset@unbind-reset-rebind:shard-adlp: PASS -> ABORT +2
> other tests abort
>  *
> igt@kms_atomic_transition@modeset-transition-nonblocking-fencing:shar
> d-dg2-set2: PASS -> ABORT +10 other tests abort
>  * igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-1:shard-adlp: PASS
> -> INCOMPLETE
>  *
> igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling:s
> hard-dg2-set2: PASS -> DMESG-WARN +47 other tests dmesg-warn
>  * igt@kms_pm_rpm@dpms-mode-unset-lpsp:shard-lnl: PASS -> SKIP +2
> other tests skip
>  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:shard-dg2-set2: PASS ->
> SKIP +2 other tests skip
>  * igt@kms_pm_rpm@legacy-planes-dpms:shard-adlp: PASS -> SKIP +1
> other test skip
>  * igt@kms_vblank@wait-forked-hang@pipe-a-hdmi-a-6:shard-dg2-set2:
> NOTRUN -> DMESG-WARN +2 other tests dmesg-warn
>  * igt@xe_exec_balancer@many-cm-virtual-userptr:shard-dg2-set2: PASS
> -> TIMEOUT +3 other tests timeout
>  *
> igt@xe_exec_balancer@many-execqueues-parallel-userptr-invalidate:shar
> d-dg2-set2: PASS -> DMESG-FAIL +51 other tests dmesg-fail

I didn't see anything like this when I was testing locally, but let me
be extra sure there. I do see this signature popping up a couple of
times in testing here...
*ERROR* Tile0: GT0: FAST_REQ H2G fence 0xea61 failed! e=0x101, h=0

I'll make sure this isn't related before merging.

Thanks,
Stuart

>  * igt@xe_exec_balancer@twice-cm-virtual-rebind:shard-bmg: NOTRUN ->
> DMESG-FAIL +1 other test dmesg-fail
>  * igt@xe_exec_basic@once-null-defer-bind:shard-bmg: PASS -> DMESG-
> WARN +9 other tests dmesg-warn
>  * igt@xe_exec_basic@twice-bindexecqueue:shard-bmg: NOTRUN -> DMESG-
> WARN +2 other tests dmesg-warn
>  * igt@xe_exec_compute_mode@many-userptr:shard-adlp: PASS -> DMESG-
> FAIL +40 other tests dmesg-fail
>  * igt@xe_exec_compute_mode@many-userptr-unmap:shard-adlp: PASS ->
> TIMEOUT
>  * igt@xe_exec_compute_mode@once-bindexecqueue-userptr:shard-dg2-
> set2: PASS -> FAIL
>  * igt@xe_exec_fault_mode@many-basic-prefetch:shard-bmg: NOTRUN ->
> TIMEOUT
>  * igt@xe_exec_store@long-shader-bb-check@gt0-
> drm_xe_engine_class_compute0-bb-system-target-system:shard-dg2-set2:
> PASS -> INCOMPLETE
>  *
> igt@xe_exec_system_allocator@many-large-malloc-busy-nomemset:shard-
> bmg: PASS -> FAIL
>  * igt@xe_exec_system_allocator@many-malloc-fork-read-after:shard-
> lnl: PASS -> DMESG-FAIL +82 other tests dmesg-fail
>  *
> igt@xe_exec_system_allocator@process-many-large-execqueues-malloc-mlock-nomemset
> :shard-bmg: NOTRUN -> ABORT
>  * igt@xe_exec_system_allocator@process-many-mmap-shared-remap:shard-
> bmg: PASS -> ABORT +17 other tests abort
>  *
> igt@xe_exec_system_allocator@threads-many-large-execqueues-free-nomemset
> :shard-lnl: PASS -> ABORT +19 other tests abort
>  * igt@xe_exec_system_allocator@twice-mmap-new-race-nomemset:shard-
> bmg: PASS -> DMESG-FAIL +65 other tests dmesg-fail
>  * igt@xe_exec_threads@threads-bal-userptr-invalidate:shard-lnl: PASS
> -> DMESG-WARN +14 other tests dmesg-warn
>  * igt@xe_pmu@engine-activity-single-load@engine-
> drm_xe_engine_class_video_enhance0:shard-adlp: PASS -> FAIL +3 other
> tests fail
>  * igt@xe_vm@large-split-misaligned-binds-1073741824:shard-adlp: PASS
> -> DMESG-WARN +41 other tests dmesg-warn
> Warnings * igt@kms_pm_rpm@modeset-lpsp:shard-bmg: SKIP (Intel XE#1439
> / Intel XE#3141 / Intel XE#836) -> SKIP
> SuppressedThe following results come from untrusted machines, tests,
> or statuses.
>  They do not affect the overall result.
>  * {igt@kms_pipe_stress@stress-xrgb8888-xtiled}:shard-adlp: PASS ->
> DMESG-WARNshard-dg2-set2: PASS -> DMESG-WARN
>  * {igt@xe_configfs@ctx-restore-post-bb-invalid}:shard-lnl: PASS ->
> ABORT +4 other tests abortshard-adlp: PASS -> ABORT
>  *
> {igt@xe_exec_system_allocator@many-64k-mmap-remap-ro-dontunmap}:shard
> -bmg: PASS -> DMESG-FAIL +10 other tests dmesg-fail
>  *
> {igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-free-madvise
> }:shard-bmg: PASS -> ABORT +3 other tests abort
>  * {igt@xe_exec_system_allocator@twice-large-free-madvise}:shard-lnl:
> PASS -> DMESG-FAIL +14 other tests dmesg-fail
>  *
> {igt@xe_fault_injection@inject-fault-probe-function-guc_wait_ucode}:s
> hard-dg2-set2: PASS -> ABORT +1 other test abort
> Known issuesHere are the changes found in xe-pw-155352v1_FULL that
> come from known issues:
> IGT changesIssues hit * igt@core_hotunplug@hotreplug:shard-dg2-set2:
> PASS -> ABORT (Intel XE#5466)
>  * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-
> hdmi-a-1:shard-adlp: PASS -> FAIL (Intel XE#3908) +3 other tests fail
>  * igt@kms_bw@linear-tiling-1-displays-1920x1080p:shard-dg2-set2:
> NOTRUN -> SKIP (Intel XE#367)
>  * igt@kms_ccs@bad-rotation-90-yf-tiled-ccs@pipe-c-dp-2:shard-dg2-
> set2: NOTRUN -> SKIP (Intel XE#787) +97 other tests skip
>  * igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-2:shard-dg2-
> set2: NOTRUN -> SKIP (Intel XE#455 / Intel XE#787) +13 other tests
> skip
>  * igt@kms_ccs@random-ccs-data-y-tiled-ccs:shard-bmg: NOTRUN -> SKIP
> (Intel XE#2887)
>  * igt@kms_cdclk@mode-transition@pipe-d-dp-4:shard-dg2-set2: NOTRUN -
> > SKIP (Intel XE#4417) +3 other tests skip
>  * igt@kms_content_protection@atomic@pipe-a-dp-2:shard-bmg: NOTRUN ->
> FAIL (Intel XE#1178)
>  * igt@kms_cursor_crc@cursor-suspend:shard-adlp: PASS -> INCOMPLETE
> (Intel XE#5545)
>  * igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1:shard-adlp: PASS
> -> DMESG-FAIL (Intel XE#5545)
>  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:shard-dg2-
> set2: PASS -> INCOMPLETE (Intel XE#3226)
>  * igt@kms_flip@2x-flip-vs-rmfb-interruptible:shard-bmg: PASS -> SKIP
> (Intel XE#2316)
>  * igt@kms_flip@basic-flip-vs-wf_vblank:shard-adlp: PASS -> DMESG-
> WARN (Intel XE#4543) +2 other tests dmesg-warn
>  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:shard-
> adlp: PASS -> ABORT (Intel XE#3970) +1 other test abort
>  *
> igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-onoff:shar
> d-dg2-set2: NOTRUN -> SKIP (Intel XE#651)
>  *
> igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc
> :shard-dg2-set2: NOTRUN -> SKIP (Intel XE#653)
>  *
> igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen:
> shard-bmg: NOTRUN -> SKIP (Intel XE#2313)
>  * igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64:shard-dg2-
> set2: NOTRUN -> FAIL (Intel XE#616) +3 other tests fail
>  * igt@kms_plane_lowres@tiling-x:shard-dg2-set2: PASS -> DMESG-WARN
> (Intel XE#5681)
>  * igt@kms_pm_rpm@basic-pci-d3-state:shard-adlp: PASS -> ABORT (Intel
> XE#5545)
>  * igt@kms_vblank@query-forked-hang@pipe-a-hdmi-a-1:shard-adlp: PASS
> -> DMESG-WARN (Intel XE#2953 / Intel XE#4173) +1 other test dmesg-
> warn
>  * igt@xe_eudebug_online@reset-with-attention:shard-bmg: NOTRUN ->
> SKIP (Intel XE#4837)
>  * igt@xe_exec_basic@multigpu-no-exec-null-defer-bind:shard-dg2-set2:
> PASS -> SKIP (Intel XE#1392) +4 other tests skip
>  *
> igt@xe_exec_compute_mode@many-execqueues-preempt-fence-early:shard-
> adlp: PASS -> FAIL (Intel XE#5625)
>  * igt@xe_exec_compute_mode@many-userptr-invalidate-race:shard-adlp:
> PASS -> ABORT (Intel XE#5790)
>  * igt@xe_exec_fault_mode@many-invalid-userptr-fault:shard-dg2-set2:
> NOTRUN -> SKIP (Intel XE#288)
>  *
> igt@xe_exec_system_allocator@many-large-execqueues-mmap-file-mlock-nomemset
> :shard-dg2-set2: NOTRUN -> SKIP (Intel XE#4915) +9 other tests skip
>  *
> igt@xe_exec_system_allocator@threads-many-large-execqueues-new:shard-
> bmg: PASS -> ABORT (Intel XE#3970)
>  * igt@xe_exec_threads@threads-bal-mixed-fd-rebind:shard-bmg: PASS ->
> DMESG-FAIL (Intel XE#3876) +3 other tests dmesg-fail
>  * igt@xe_exec_threads@threads-bal-userptr-invalidate:shard-dg2-set2:
> PASS -> DMESG-FAIL (Intel XE#3876)
>  * igt@xe_exec_threads@threads-mixed-fd-userptr-invalidate:shard-
> adlp: PASS -> DMESG-FAIL (Intel XE#3876) +9 other tests dmesg-fail
>  *
> igt@xe_fault_injection@inject-fault-probe-function-xe_guc_ads_init:sh
> ard-adlp: PASS -> ABORT (Intel XE#5530) +5 other tests abort
>  * igt@xe_pm@s2idle-vm-bind-unbind-all:shard-adlp: PASS -> DMESG-WARN
> (Intel XE#4504)
>  * igt@xe_pxp@pxp-stale-bo-bind-post-rpm:shard-dg2-set2: NOTRUN ->
> SKIP (Intel XE#4733)
> Possible fixes *
> igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:shard-dg2-set2:
> INCOMPLETE (Intel XE#1727 / Intel XE#3113 / Intel XE#4345) -> PASS
>  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-dp-
> 4:shard-dg2-set2: INCOMPLETE (Intel XE#6014) -> PASS
>  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-
> 6:shard-dg2-set2: DMESG-WARN (Intel XE#1727 / Intel XE#3113) -> PASS
>  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:shard-
> bmg: SKIP (Intel XE#2316) -> PASS
>  * igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a1:shard-
> adlp: DMESG-WARN (Intel XE#4543) -> PASS +1 other test pass
>  * igt@kms_flip@flip-vs-suspend-interruptible:shard-adlp: DMESG-WARN
> (Intel XE#2953 / Intel XE#4173) -> PASS +1 other test pass
>  * igt@xe_exec_basic@multigpu-once-null-rebind:shard-dg2-set2: SKIP
> (Intel XE#1392) -> PASS +2 other tests pass
>  * igt@xe_exec_reset@parallel-gt-reset:shard-adlp: DMESG-WARN (Intel
> XE#3876) -> PASS
>  * igt@xe_module_load@load:shard-lnl: (PASS, PASS, PASS, PASS, PASS,
> PASS, PASS, PASS, PASS, PASS, SKIP, PASS, PASS, PASS, PASS, PASS,
> PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS) (Intel
> XE#378) -> (PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS,
> PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS,
> PASS, PASS, PASS, PASS, PASS)shard-bmg: (PASS, PASS, PASS, PASS,
> PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS,
> PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, SKIP, PASS) (Intel
> XE#2457) -> (PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS,
> PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS,
> PASS, PASS, PASS, PASS)shard-adlp: (PASS, PASS, PASS, PASS, PASS,
> PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS,
> PASS, PASS, PASS, SKIP, PASS, PASS, PASS, PASS, PASS, PASS) (Intel
> XE#378 / Intel XE#5612) -> (PASS, PASS, PASS, PASS, PASS, PASS, PASS,
> PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS,
> PASS, PASS, PASS, PASS, PASS, PASS, PASS)
> Warnings * igt@kms_big_fb@x-tiled-8bpp-rotate-0:shard-adlp: DMESG-
> FAIL (Intel XE#4543) -> DMESG-WARN (Intel XE#4543)
>  * igt@kms_content_protection@atomic:shard-bmg: SKIP (Intel XE#2341)
> -> FAIL (Intel XE#1178)
>  * igt@kms_flip@flip-vs-rmfb:shard-adlp: DMESG-WARN (Intel XE#4543 /
> Intel XE#5208) -> DMESG-WARN (Intel XE#5208)
>  *
> igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-plflip-blt:shard-
> bmg: SKIP (Intel XE#2311) -> SKIP (Intel XE#2312)
>  *
> igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-msflip-blt:shard-
> bmg: SKIP (Intel XE#2312) -> SKIP (Intel XE#2311) +1 other test skip
>  * igt@xe_pm@d3cold-basic-exec:shard-adlp: SKIP (Intel XE#2284 /
> Intel XE#366) -> ABORT (Intel XE#5545)
> {name}: This element is suppressed. This means it is ignored when
> computing
>  the status of the difference (SUCCESS, WARNING, or FAILURE).
> Build changes * Linux: xe-3859-
> 0aa5ad66ed77cd8c3bb9fb01997f68f31200f434 -> xe-pw-155352v1
> IGT_8572: 8572
>  xe-3859-0aa5ad66ed77cd8c3bb9fb01997f68f31200f434:
> 0aa5ad66ed77cd8c3bb9fb01997f68f31200f434
>  xe-pw-155352v1: 155352v1

Re: [PATCH 6/7] drm/xe: Don't send a CLEANUP message on sched pause

[Matthew Brost]

On Thu, Oct 02, 2025 at 11:04:43PM +0000, Stuart Summers wrote:
> When the DRM scheduler has been "paused" (see xe_gpu_scheduler.c),
> if we then send a message to cleanup an exec queue at that time,
> we will never get a response for it if for some reason the
> unpause never happens. This can occur if for some reason during

That is not how this designed. Messages to the queue do get processed
when schedule is paused but should get processed when the queue is
resumed.

> exec queue creation, the device becomes wedged. The wedge event
> will cause that scheduler to become paused and the creation

IIRC wedging the driver shouldn't leave any queues paused. It should
just signal all of the queues job's fences without touching any hardware
state. 

So something else is going on here if memory is leaking after wedging -
i.e., this fix doesn't look right.

Matt

> then leaves a dangling LRC that will never get cleaned up since
> the recovery is a driver rebind. So essentially this change
> fixes a potential memory leak in the event the device is
> wedged during a test unexpectedly (e.g. during an unexpected
> hardware failure).
> 
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_guc_submit.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
> index 55a50c46ea2b..45b72bebfc63 100644
> --- a/drivers/gpu/drm/xe/xe_guc_submit.c
> +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
> @@ -1732,7 +1732,8 @@ static void guc_exec_queue_destroy(struct xe_exec_queue *q)
>  {
>  	struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_CLEANUP;
>  
> -	if (!(q->flags & EXEC_QUEUE_FLAG_PERMANENT) && !exec_queue_wedged(q))
> +	if (!(q->flags & EXEC_QUEUE_FLAG_PERMANENT) && !exec_queue_wedged(q) &&
> +	    !READ_ONCE(q->guc->sched.base.pause_submit))
>  		guc_exec_queue_add_msg(q, msg, CLEANUP);
>  	else
>  		__guc_exec_queue_destroy(exec_queue_to_guc(q), q);
> -- 
> 2.34.1
> 

Re: [PATCH 6/7] drm/xe: Don't send a CLEANUP message on sched pause

[Summers, Stuart]

On Fri, 2025-10-03 at 11:50 -0700, Matthew Brost wrote:
> On Thu, Oct 02, 2025 at 11:04:43PM +0000, Stuart Summers wrote:
> > When the DRM scheduler has been "paused" (see xe_gpu_scheduler.c),
> > if we then send a message to cleanup an exec queue at that time,
> > we will never get a response for it if for some reason the
> > unpause never happens. This can occur if for some reason during
> 
> That is not how this designed. Messages to the queue do get processed
> when schedule is paused but should get processed when the queue is
> resumed.

Right but in the case of a wedge, there is no resume here.

> 
> > exec queue creation, the device becomes wedged. The wedge event
> > will cause that scheduler to become paused and the creation
> 
> IIRC wedging the driver shouldn't leave any queues paused. It should
> just signal all of the queues job's fences without touching any
> hardware
> state. 

Ok so if the recommendation is to make sure the wedge is flushing the
fences properly, let me look there and get back.

Thanks for the feedback!
Stuart

> 
> So something else is going on here if memory is leaking after wedging
> -
> i.e., this fix doesn't look right.
> 
> Matt
> 
> > then leaves a dangling LRC that will never get cleaned up since
> > the recovery is a driver rebind. So essentially this change
> > fixes a potential memory leak in the event the device is
> > wedged during a test unexpectedly (e.g. during an unexpected
> > hardware failure).
> > 
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_guc_submit.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c
> > b/drivers/gpu/drm/xe/xe_guc_submit.c
> > index 55a50c46ea2b..45b72bebfc63 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_submit.c
> > +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
> > @@ -1732,7 +1732,8 @@ static void guc_exec_queue_destroy(struct
> > xe_exec_queue *q)
> >  {
> >         struct xe_sched_msg *msg = q->guc->static_msgs +
> > STATIC_MSG_CLEANUP;
> >  
> > -       if (!(q->flags & EXEC_QUEUE_FLAG_PERMANENT) &&
> > !exec_queue_wedged(q))
> > +       if (!(q->flags & EXEC_QUEUE_FLAG_PERMANENT) &&
> > !exec_queue_wedged(q) &&
> > +           !READ_ONCE(q->guc->sched.base.pause_submit))
> >                 guc_exec_queue_add_msg(q, msg, CLEANUP);
> >         else
> >                 __guc_exec_queue_destroy(exec_queue_to_guc(q), q);
> > -- 
> > 2.34.1
> > 

Re: [PATCH 7/7] drm/xe: Check for GuC responses on disabling scheduling

[Matthew Brost]

On Thu, Oct 02, 2025 at 11:04:44PM +0000, Stuart Summers wrote:
> In the event the GuC becomes unresponsive during a scheduling
> disable event, we still want the driver to be able to recover.
> This patch follows the same methodology we already have in place
> for TLB invalidation requests, where we send a request to GuC
> and wait for that invalidation done response. If the response
> doesn't come back in time we then at least print a message
> indicating the invalidation failed for some reason.
> 
> In this case, we send the schedule disable and the expectation
> is that GuC will respond with a schedule done response. The KMD
> then catches that response and in turn sends a context deregistration
> response. So in the event GuC becomes unresponsive after we send
> the schedule disable, we actually have two g2h responses that
> have been reserved but never received.
> 
> To handle this, make sure the pending disable event in the
> exec queue gets cleared (i.e. we received that response from
> GuC). If it doesn't in a reasonable amount of time, assume
> GuC is dead: ban the exec queue, queue up a GT reset, and
> manually call the schedule done handler. Then in the schedule
> done handler, in turn, check whether the context had been
> banned. If so, manually call the deregistration done handler
> to ensure all resources related to that exec queue get
> cleaned up properly. Without this, if the device becomes
> wedged after an exec queue has been created, the attached
> resources like the LRC will not get feed properly resulting
> in a memory leak.
> 
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_guc_submit.c | 23 ++++++++++++++++++++++-
>  1 file changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
> index 45b72bebfc63..a177d87c8524 100644
> --- a/drivers/gpu/drm/xe/xe_guc_submit.c
> +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
> @@ -939,6 +939,9 @@ int xe_guc_read_stopped(struct xe_guc *guc)
>  		GUC_CONTEXT_##enable_disable,				\
>  	}
>  
> +static void handle_sched_done(struct xe_guc *guc, struct xe_exec_queue *q,
> +			      u32 runnable_state);
> +
>  static void disable_scheduling_deregister(struct xe_guc *guc,
>  					  struct xe_exec_queue *q)
>  {
> @@ -974,6 +977,17 @@ static void disable_scheduling_deregister(struct xe_guc *guc,
>  	xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
>  		       G2H_LEN_DW_SCHED_CONTEXT_MODE_SET +
>  		       G2H_LEN_DW_DEREGISTER_CONTEXT, 2);
> +
> +	ret = wait_event_timeout(guc->ct.wq,
> +				 !exec_queue_pending_disable(q) ||
> +				 xe_guc_read_stopped(guc),
> +				 HZ * 5);

This doesn't look right. Deregister is designed to be fully async. If
this flow stops working for whatever reason the GuC is dead and
eventually somewhere in driver will detect this and trigger a GT reset
which is cleanup all lost H2G.

> +	if (!ret || xe_guc_read_stopped(guc)) {
> +		xe_gt_warn(guc_to_gt(guc), "Schedule disable failed to respond");
> +		set_exec_queue_banned(q);
> +		handle_sched_done(guc, q, 0);
> +		xe_gt_reset_async(q->gt);
> +	}
>  }
>  
>  static void xe_guc_exec_queue_trigger_cleanup(struct xe_exec_queue *q)
> @@ -2117,6 +2131,8 @@ g2h_exec_queue_lookup(struct xe_guc *guc, u32 guc_id)
>  	return q;
>  }
>  
> +static void handle_deregister_done(struct xe_guc *guc, struct xe_exec_queue *q);
> +
>  static void deregister_exec_queue(struct xe_guc *guc, struct xe_exec_queue *q)
>  {
>  	u32 action[] = {
> @@ -2131,7 +2147,12 @@ static void deregister_exec_queue(struct xe_guc *guc, struct xe_exec_queue *q)
>  
>  	trace_xe_exec_queue_deregister(q);
>  
> -	xe_guc_ct_send_g2h_handler(&guc->ct, action, ARRAY_SIZE(action));
> +	if (exec_queue_banned(q)) {
> +		handle_deregister_done(guc, q);

This would leave the GuC with reference to guc_id and subsequent reuse
of the guc_id (i.e., next register) will fall.

Matt

> +	} else {
> +		xe_guc_ct_send_g2h_handler(&guc->ct, action,
> +					   ARRAY_SIZE(action));
> +	}
>  }
>  
>  static void handle_sched_done(struct xe_guc *guc, struct xe_exec_queue *q,
> -- 
> 2.34.1
> 

Re: [PATCH 7/7] drm/xe: Check for GuC responses on disabling scheduling

[Summers, Stuart]

On Fri, 2025-10-03 at 11:54 -0700, Matthew Brost wrote:
> On Thu, Oct 02, 2025 at 11:04:44PM +0000, Stuart Summers wrote:
> > In the event the GuC becomes unresponsive during a scheduling
> > disable event, we still want the driver to be able to recover.
> > This patch follows the same methodology we already have in place
> > for TLB invalidation requests, where we send a request to GuC
> > and wait for that invalidation done response. If the response
> > doesn't come back in time we then at least print a message
> > indicating the invalidation failed for some reason.
> > 
> > In this case, we send the schedule disable and the expectation
> > is that GuC will respond with a schedule done response. The KMD
> > then catches that response and in turn sends a context
> > deregistration
> > response. So in the event GuC becomes unresponsive after we send
> > the schedule disable, we actually have two g2h responses that
> > have been reserved but never received.
> > 
> > To handle this, make sure the pending disable event in the
> > exec queue gets cleared (i.e. we received that response from
> > GuC). If it doesn't in a reasonable amount of time, assume
> > GuC is dead: ban the exec queue, queue up a GT reset, and
> > manually call the schedule done handler. Then in the schedule
> > done handler, in turn, check whether the context had been
> > banned. If so, manually call the deregistration done handler
> > to ensure all resources related to that exec queue get
> > cleaned up properly. Without this, if the device becomes
> > wedged after an exec queue has been created, the attached
> > resources like the LRC will not get feed properly resulting
> > in a memory leak.
> > 
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_guc_submit.c | 23 ++++++++++++++++++++++-
> >  1 file changed, 22 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c
> > b/drivers/gpu/drm/xe/xe_guc_submit.c
> > index 45b72bebfc63..a177d87c8524 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_submit.c
> > +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
> > @@ -939,6 +939,9 @@ int xe_guc_read_stopped(struct xe_guc *guc)
> >                 GUC_CONTEXT_##enable_disable,                      
> >      \
> >         }
> >  
> > +static void handle_sched_done(struct xe_guc *guc, struct
> > xe_exec_queue *q,
> > +                             u32 runnable_state);
> > +
> >  static void disable_scheduling_deregister(struct xe_guc *guc,
> >                                           struct xe_exec_queue *q)
> >  {
> > @@ -974,6 +977,17 @@ static void
> > disable_scheduling_deregister(struct xe_guc *guc,
> >         xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
> >                        G2H_LEN_DW_SCHED_CONTEXT_MODE_SET +
> >                        G2H_LEN_DW_DEREGISTER_CONTEXT, 2);
> > +
> > +       ret = wait_event_timeout(guc->ct.wq,
> > +                                !exec_queue_pending_disable(q) ||
> > +                                xe_guc_read_stopped(guc),
> > +                                HZ * 5);
> 
> This doesn't look right. Deregister is designed to be fully async. If
> this flow stops working for whatever reason the GuC is dead and
> eventually somewhere in driver will detect this and trigger a GT
> reset
> which is cleanup all lost H2G.
> 
> > +       if (!ret || xe_guc_read_stopped(guc)) {
> > +               xe_gt_warn(guc_to_gt(guc), "Schedule disable failed
> > to respond");
> > +               set_exec_queue_banned(q);
> > +               handle_sched_done(guc, q, 0);
> > +               xe_gt_reset_async(q->gt);
> > +       }
> >  }
> >  
> >  static void xe_guc_exec_queue_trigger_cleanup(struct xe_exec_queue
> > *q)
> > @@ -2117,6 +2131,8 @@ g2h_exec_queue_lookup(struct xe_guc *guc, u32
> > guc_id)
> >         return q;
> >  }
> >  
> > +static void handle_deregister_done(struct xe_guc *guc, struct
> > xe_exec_queue *q);
> > +
> >  static void deregister_exec_queue(struct xe_guc *guc, struct
> > xe_exec_queue *q)
> >  {
> >         u32 action[] = {
> > @@ -2131,7 +2147,12 @@ static void deregister_exec_queue(struct
> > xe_guc *guc, struct xe_exec_queue *q)
> >  
> >         trace_xe_exec_queue_deregister(q);
> >  
> > -       xe_guc_ct_send_g2h_handler(&guc->ct, action,
> > ARRAY_SIZE(action));
> > +       if (exec_queue_banned(q)) {
> > +               handle_deregister_done(guc, q);
> 
> This would leave the GuC with reference to guc_id and subsequent
> reuse
> of the guc_id (i.e., next register) will fall.

But again, in this case the GuC is dead and we should be getting that
reset event you had mentioned above. The issue I'm having is
specifically around wedge events. Without a GT wedge, we will normally
go through the GT reset flow and recover like you mentioned. But in the
case of a wedge, we don't redo the software part of the reset (i.e. we
don't reset contexts, etc) per gt_reset():
static int gt_reset(struct xe_gt *gt)
{
        unsigned int fw_ref;
        int err;

        if (xe_device_wedged(gt_to_xe(gt)))
                return -ECANCELED;

Maybe instead of banned I can check for banned and wedged here? Or
maybe we should rethink the software reset flow in the event of a
wedge?

Thanks,
Stuart

> 
> Matt
> 
> > +       } else {
> > +               xe_guc_ct_send_g2h_handler(&guc->ct, action,
> > +                                          ARRAY_SIZE(action));
> > +       }
> >  }
> >  
> >  static void handle_sched_done(struct xe_guc *guc, struct
> > xe_exec_queue *q,
> > -- 
> > 2.34.1
> > 

Re: [PATCH 7/7] drm/xe: Check for GuC responses on disabling scheduling

[Matthew Brost]

On Fri, Oct 03, 2025 at 12:58:37PM -0600, Summers, Stuart wrote:
> On Fri, 2025-10-03 at 11:54 -0700, Matthew Brost wrote:
> > On Thu, Oct 02, 2025 at 11:04:44PM +0000, Stuart Summers wrote:
> > > In the event the GuC becomes unresponsive during a scheduling
> > > disable event, we still want the driver to be able to recover.
> > > This patch follows the same methodology we already have in place
> > > for TLB invalidation requests, where we send a request to GuC
> > > and wait for that invalidation done response. If the response
> > > doesn't come back in time we then at least print a message
> > > indicating the invalidation failed for some reason.
> > > 
> > > In this case, we send the schedule disable and the expectation
> > > is that GuC will respond with a schedule done response. The KMD
> > > then catches that response and in turn sends a context
> > > deregistration
> > > response. So in the event GuC becomes unresponsive after we send
> > > the schedule disable, we actually have two g2h responses that
> > > have been reserved but never received.
> > > 
> > > To handle this, make sure the pending disable event in the
> > > exec queue gets cleared (i.e. we received that response from
> > > GuC). If it doesn't in a reasonable amount of time, assume
> > > GuC is dead: ban the exec queue, queue up a GT reset, and
> > > manually call the schedule done handler. Then in the schedule
> > > done handler, in turn, check whether the context had been
> > > banned. If so, manually call the deregistration done handler
> > > to ensure all resources related to that exec queue get
> > > cleaned up properly. Without this, if the device becomes
> > > wedged after an exec queue has been created, the attached
> > > resources like the LRC will not get feed properly resulting
> > > in a memory leak.
> > > 
> > > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > > ---
> > >  drivers/gpu/drm/xe/xe_guc_submit.c | 23 ++++++++++++++++++++++-
> > >  1 file changed, 22 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c
> > > b/drivers/gpu/drm/xe/xe_guc_submit.c
> > > index 45b72bebfc63..a177d87c8524 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc_submit.c
> > > +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
> > > @@ -939,6 +939,9 @@ int xe_guc_read_stopped(struct xe_guc *guc)
> > >                 GUC_CONTEXT_##enable_disable,                      
> > >      \
> > >         }
> > >  
> > > +static void handle_sched_done(struct xe_guc *guc, struct
> > > xe_exec_queue *q,
> > > +                             u32 runnable_state);
> > > +
> > >  static void disable_scheduling_deregister(struct xe_guc *guc,
> > >                                           struct xe_exec_queue *q)
> > >  {
> > > @@ -974,6 +977,17 @@ static void
> > > disable_scheduling_deregister(struct xe_guc *guc,
> > >         xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
> > >                        G2H_LEN_DW_SCHED_CONTEXT_MODE_SET +
> > >                        G2H_LEN_DW_DEREGISTER_CONTEXT, 2);
> > > +
> > > +       ret = wait_event_timeout(guc->ct.wq,
> > > +                                !exec_queue_pending_disable(q) ||
> > > +                                xe_guc_read_stopped(guc),
> > > +                                HZ * 5);
> > 
> > This doesn't look right. Deregister is designed to be fully async. If
> > this flow stops working for whatever reason the GuC is dead and
> > eventually somewhere in driver will detect this and trigger a GT
> > reset
> > which is cleanup all lost H2G.
> > 
> > > +       if (!ret || xe_guc_read_stopped(guc)) {
> > > +               xe_gt_warn(guc_to_gt(guc), "Schedule disable failed
> > > to respond");
> > > +               set_exec_queue_banned(q);
> > > +               handle_sched_done(guc, q, 0);
> > > +               xe_gt_reset_async(q->gt);
> > > +       }
> > >  }
> > >  
> > >  static void xe_guc_exec_queue_trigger_cleanup(struct xe_exec_queue
> > > *q)
> > > @@ -2117,6 +2131,8 @@ g2h_exec_queue_lookup(struct xe_guc *guc, u32
> > > guc_id)
> > >         return q;
> > >  }
> > >  
> > > +static void handle_deregister_done(struct xe_guc *guc, struct
> > > xe_exec_queue *q);
> > > +
> > >  static void deregister_exec_queue(struct xe_guc *guc, struct
> > > xe_exec_queue *q)
> > >  {
> > >         u32 action[] = {
> > > @@ -2131,7 +2147,12 @@ static void deregister_exec_queue(struct
> > > xe_guc *guc, struct xe_exec_queue *q)
> > >  
> > >         trace_xe_exec_queue_deregister(q);
> > >  
> > > -       xe_guc_ct_send_g2h_handler(&guc->ct, action,
> > > ARRAY_SIZE(action));
> > > +       if (exec_queue_banned(q)) {
> > > +               handle_deregister_done(guc, q);
> > 
> > This would leave the GuC with reference to guc_id and subsequent
> > reuse
> > of the guc_id (i.e., next register) will fall.
> 
> But again, in this case the GuC is dead and we should be getting that
> reset event you had mentioned above. The issue I'm having is

Banned is a per thing queue and more than likely we wont be doing a GT
reset, thus we still need remove references to the queue from the GuC.

> specifically around wedge events. Without a GT wedge, we will normally
> go through the GT reset flow and recover like you mentioned. But in the

No. See above.

> case of a wedge, we don't redo the software part of the reset (i.e. we
> don't reset contexts, etc) per gt_reset():
> static int gt_reset(struct xe_gt *gt)
> {
>         unsigned int fw_ref;
>         int err;
> 
>         if (xe_device_wedged(gt_to_xe(gt)))
>                 return -ECANCELED;
> 
> Maybe instead of banned I can check for banned and wedged here? Or
> maybe we should rethink the software reset flow in the event of a
> wedge?

The idea with wedged is we leave all hardward state, including the GuC,
intacted for inspection. So I think a xe_device_wedged checked here
makes sense. This would cover the case where start a queue teardown via
a CLEANUP message and mid-flow we wedge the device.

Matt

> 
> Thanks,
> Stuart
> 
> > 
> > Matt
> > 
> > > +       } else {
> > > +               xe_guc_ct_send_g2h_handler(&guc->ct, action,
> > > +                                          ARRAY_SIZE(action));
> > > +       }
> > >  }
> > >  
> > >  static void handle_sched_done(struct xe_guc *guc, struct
> > > xe_exec_queue *q,
> > > -- 
> > > 2.34.1
> > > 
> 

Re: [PATCH 7/7] drm/xe: Check for GuC responses on disabling scheduling

[Summers, Stuart]

On Fri, 2025-10-03 at 12:38 -0700, Matthew Brost wrote:
> On Fri, Oct 03, 2025 at 12:58:37PM -0600, Summers, Stuart wrote:
> > On Fri, 2025-10-03 at 11:54 -0700, Matthew Brost wrote:
> > > On Thu, Oct 02, 2025 at 11:04:44PM +0000, Stuart Summers wrote:
> > > > In the event the GuC becomes unresponsive during a scheduling
> > > > disable event, we still want the driver to be able to recover.
> > > > This patch follows the same methodology we already have in
> > > > place
> > > > for TLB invalidation requests, where we send a request to GuC
> > > > and wait for that invalidation done response. If the response
> > > > doesn't come back in time we then at least print a message
> > > > indicating the invalidation failed for some reason.
> > > > 
> > > > In this case, we send the schedule disable and the expectation
> > > > is that GuC will respond with a schedule done response. The KMD
> > > > then catches that response and in turn sends a context
> > > > deregistration
> > > > response. So in the event GuC becomes unresponsive after we
> > > > send
> > > > the schedule disable, we actually have two g2h responses that
> > > > have been reserved but never received.
> > > > 
> > > > To handle this, make sure the pending disable event in the
> > > > exec queue gets cleared (i.e. we received that response from
> > > > GuC). If it doesn't in a reasonable amount of time, assume
> > > > GuC is dead: ban the exec queue, queue up a GT reset, and
> > > > manually call the schedule done handler. Then in the schedule
> > > > done handler, in turn, check whether the context had been
> > > > banned. If so, manually call the deregistration done handler
> > > > to ensure all resources related to that exec queue get
> > > > cleaned up properly. Without this, if the device becomes
> > > > wedged after an exec queue has been created, the attached
> > > > resources like the LRC will not get feed properly resulting
> > > > in a memory leak.
> > > > 
> > > > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/xe/xe_guc_submit.c | 23
> > > > ++++++++++++++++++++++-
> > > >  1 file changed, 22 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c
> > > > b/drivers/gpu/drm/xe/xe_guc_submit.c
> > > > index 45b72bebfc63..a177d87c8524 100644
> > > > --- a/drivers/gpu/drm/xe/xe_guc_submit.c
> > > > +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
> > > > @@ -939,6 +939,9 @@ int xe_guc_read_stopped(struct xe_guc *guc)
> > > >                 GUC_CONTEXT_##enable_disable,                  
> > > >     
> > > >      \
> > > >         }
> > > >  
> > > > +static void handle_sched_done(struct xe_guc *guc, struct
> > > > xe_exec_queue *q,
> > > > +                             u32 runnable_state);
> > > > +
> > > >  static void disable_scheduling_deregister(struct xe_guc *guc,
> > > >                                           struct xe_exec_queue
> > > > *q)
> > > >  {
> > > > @@ -974,6 +977,17 @@ static void
> > > > disable_scheduling_deregister(struct xe_guc *guc,
> > > >         xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
> > > >                        G2H_LEN_DW_SCHED_CONTEXT_MODE_SET +
> > > >                        G2H_LEN_DW_DEREGISTER_CONTEXT, 2);
> > > > +
> > > > +       ret = wait_event_timeout(guc->ct.wq,
> > > > +                                !exec_queue_pending_disable(q)
> > > > ||
> > > > +                                xe_guc_read_stopped(guc),
> > > > +                                HZ * 5);
> > > 
> > > This doesn't look right. Deregister is designed to be fully
> > > async. If
> > > this flow stops working for whatever reason the GuC is dead and
> > > eventually somewhere in driver will detect this and trigger a GT
> > > reset
> > > which is cleanup all lost H2G.
> > > 
> > > > +       if (!ret || xe_guc_read_stopped(guc)) {
> > > > +               xe_gt_warn(guc_to_gt(guc), "Schedule disable
> > > > failed
> > > > to respond");
> > > > +               set_exec_queue_banned(q);
> > > > +               handle_sched_done(guc, q, 0);
> > > > +               xe_gt_reset_async(q->gt);
> > > > +       }
> > > >  }
> > > >  
> > > >  static void xe_guc_exec_queue_trigger_cleanup(struct
> > > > xe_exec_queue
> > > > *q)
> > > > @@ -2117,6 +2131,8 @@ g2h_exec_queue_lookup(struct xe_guc *guc,
> > > > u32
> > > > guc_id)
> > > >         return q;
> > > >  }
> > > >  
> > > > +static void handle_deregister_done(struct xe_guc *guc, struct
> > > > xe_exec_queue *q);
> > > > +
> > > >  static void deregister_exec_queue(struct xe_guc *guc, struct
> > > > xe_exec_queue *q)
> > > >  {
> > > >         u32 action[] = {
> > > > @@ -2131,7 +2147,12 @@ static void deregister_exec_queue(struct
> > > > xe_guc *guc, struct xe_exec_queue *q)
> > > >  
> > > >         trace_xe_exec_queue_deregister(q);
> > > >  
> > > > -       xe_guc_ct_send_g2h_handler(&guc->ct, action,
> > > > ARRAY_SIZE(action));
> > > > +       if (exec_queue_banned(q)) {
> > > > +               handle_deregister_done(guc, q);
> > > 
> > > This would leave the GuC with reference to guc_id and subsequent
> > > reuse
> > > of the guc_id (i.e., next register) will fall.
> > 
> > But again, in this case the GuC is dead and we should be getting
> > that
> > reset event you had mentioned above. The issue I'm having is
> 
> Banned is a per thing queue and more than likely we wont be doing a
> GT
> reset, thus we still need remove references to the queue from the
> GuC.

Yeah this makes sense to me. My use of "banned" here was probably not
ideal.

> 
> > specifically around wedge events. Without a GT wedge, we will
> > normally
> > go through the GT reset flow and recover like you mentioned. But in
> > the
> 
> No. See above.
> 
> > case of a wedge, we don't redo the software part of the reset (i.e.
> > we
> > don't reset contexts, etc) per gt_reset():
> > static int gt_reset(struct xe_gt *gt)
> > {
> >         unsigned int fw_ref;
> >         int err;
> > 
> >         if (xe_device_wedged(gt_to_xe(gt)))
> >                 return -ECANCELED;
> > 
> > Maybe instead of banned I can check for banned and wedged here? Or
> > maybe we should rethink the software reset flow in the event of a
> > wedge?
> 
> The idea with wedged is we leave all hardward state, including the
> GuC,
> intacted for inspection. So I think a xe_device_wedged checked here
> makes sense. This would cover the case where start a queue teardown
> via
> a CLEANUP message and mid-flow we wedge the device.

But hardware state doesn't mean software state. Are you saying when the
device is wedged we want the memory to all be intact as well? And how
do we determine when that gets freed? On unbind?

Thanks,
Stuart

> 
> Matt
> 
> > 
> > Thanks,
> > Stuart
> > 
> > > 
> > > Matt
> > > 
> > > > +       } else {
> > > > +               xe_guc_ct_send_g2h_handler(&guc->ct, action,
> > > > +                                          ARRAY_SIZE(action));
> > > > +       }
> > > >  }
> > > >  
> > > >  static void handle_sched_done(struct xe_guc *guc, struct
> > > > xe_exec_queue *q,
> > > > -- 
> > > > 2.34.1
> > > > 
> > 

Re: [PATCH 7/7] drm/xe: Check for GuC responses on disabling scheduling

[Matthew Brost]

On Fri, Oct 03, 2025 at 01:42:26PM -0600, Summers, Stuart wrote:
> On Fri, 2025-10-03 at 12:38 -0700, Matthew Brost wrote:
> > On Fri, Oct 03, 2025 at 12:58:37PM -0600, Summers, Stuart wrote:
> > > On Fri, 2025-10-03 at 11:54 -0700, Matthew Brost wrote:
> > > > On Thu, Oct 02, 2025 at 11:04:44PM +0000, Stuart Summers wrote:
> > > > > In the event the GuC becomes unresponsive during a scheduling
> > > > > disable event, we still want the driver to be able to recover.
> > > > > This patch follows the same methodology we already have in
> > > > > place
> > > > > for TLB invalidation requests, where we send a request to GuC
> > > > > and wait for that invalidation done response. If the response
> > > > > doesn't come back in time we then at least print a message
> > > > > indicating the invalidation failed for some reason.
> > > > > 
> > > > > In this case, we send the schedule disable and the expectation
> > > > > is that GuC will respond with a schedule done response. The KMD
> > > > > then catches that response and in turn sends a context
> > > > > deregistration
> > > > > response. So in the event GuC becomes unresponsive after we
> > > > > send
> > > > > the schedule disable, we actually have two g2h responses that
> > > > > have been reserved but never received.
> > > > > 
> > > > > To handle this, make sure the pending disable event in the
> > > > > exec queue gets cleared (i.e. we received that response from
> > > > > GuC). If it doesn't in a reasonable amount of time, assume
> > > > > GuC is dead: ban the exec queue, queue up a GT reset, and
> > > > > manually call the schedule done handler. Then in the schedule
> > > > > done handler, in turn, check whether the context had been
> > > > > banned. If so, manually call the deregistration done handler
> > > > > to ensure all resources related to that exec queue get
> > > > > cleaned up properly. Without this, if the device becomes
> > > > > wedged after an exec queue has been created, the attached
> > > > > resources like the LRC will not get feed properly resulting
> > > > > in a memory leak.
> > > > > 
> > > > > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/xe/xe_guc_submit.c | 23
> > > > > ++++++++++++++++++++++-
> > > > >  1 file changed, 22 insertions(+), 1 deletion(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c
> > > > > b/drivers/gpu/drm/xe/xe_guc_submit.c
> > > > > index 45b72bebfc63..a177d87c8524 100644
> > > > > --- a/drivers/gpu/drm/xe/xe_guc_submit.c
> > > > > +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
> > > > > @@ -939,6 +939,9 @@ int xe_guc_read_stopped(struct xe_guc *guc)
> > > > >                 GUC_CONTEXT_##enable_disable,                  
> > > > >     
> > > > >      \
> > > > >         }
> > > > >  
> > > > > +static void handle_sched_done(struct xe_guc *guc, struct
> > > > > xe_exec_queue *q,
> > > > > +                             u32 runnable_state);
> > > > > +
> > > > >  static void disable_scheduling_deregister(struct xe_guc *guc,
> > > > >                                           struct xe_exec_queue
> > > > > *q)
> > > > >  {
> > > > > @@ -974,6 +977,17 @@ static void
> > > > > disable_scheduling_deregister(struct xe_guc *guc,
> > > > >         xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
> > > > >                        G2H_LEN_DW_SCHED_CONTEXT_MODE_SET +
> > > > >                        G2H_LEN_DW_DEREGISTER_CONTEXT, 2);
> > > > > +
> > > > > +       ret = wait_event_timeout(guc->ct.wq,
> > > > > +                                !exec_queue_pending_disable(q)
> > > > > ||
> > > > > +                                xe_guc_read_stopped(guc),
> > > > > +                                HZ * 5);
> > > > 
> > > > This doesn't look right. Deregister is designed to be fully
> > > > async. If
> > > > this flow stops working for whatever reason the GuC is dead and
> > > > eventually somewhere in driver will detect this and trigger a GT
> > > > reset
> > > > which is cleanup all lost H2G.
> > > > 
> > > > > +       if (!ret || xe_guc_read_stopped(guc)) {
> > > > > +               xe_gt_warn(guc_to_gt(guc), "Schedule disable
> > > > > failed
> > > > > to respond");
> > > > > +               set_exec_queue_banned(q);
> > > > > +               handle_sched_done(guc, q, 0);
> > > > > +               xe_gt_reset_async(q->gt);
> > > > > +       }
> > > > >  }
> > > > >  
> > > > >  static void xe_guc_exec_queue_trigger_cleanup(struct
> > > > > xe_exec_queue
> > > > > *q)
> > > > > @@ -2117,6 +2131,8 @@ g2h_exec_queue_lookup(struct xe_guc *guc,
> > > > > u32
> > > > > guc_id)
> > > > >         return q;
> > > > >  }
> > > > >  
> > > > > +static void handle_deregister_done(struct xe_guc *guc, struct
> > > > > xe_exec_queue *q);
> > > > > +
> > > > >  static void deregister_exec_queue(struct xe_guc *guc, struct
> > > > > xe_exec_queue *q)
> > > > >  {
> > > > >         u32 action[] = {
> > > > > @@ -2131,7 +2147,12 @@ static void deregister_exec_queue(struct
> > > > > xe_guc *guc, struct xe_exec_queue *q)
> > > > >  
> > > > >         trace_xe_exec_queue_deregister(q);
> > > > >  
> > > > > -       xe_guc_ct_send_g2h_handler(&guc->ct, action,
> > > > > ARRAY_SIZE(action));
> > > > > +       if (exec_queue_banned(q)) {
> > > > > +               handle_deregister_done(guc, q);
> > > > 
> > > > This would leave the GuC with reference to guc_id and subsequent
> > > > reuse
> > > > of the guc_id (i.e., next register) will fall.
> > > 
> > > But again, in this case the GuC is dead and we should be getting
> > > that
> > > reset event you had mentioned above. The issue I'm having is
> > 
> > Banned is a per thing queue and more than likely we wont be doing a
> > GT
> > reset, thus we still need remove references to the queue from the
> > GuC.
> 
> Yeah this makes sense to me. My use of "banned" here was probably not
> ideal.
> 
> > 
> > > specifically around wedge events. Without a GT wedge, we will
> > > normally
> > > go through the GT reset flow and recover like you mentioned. But in
> > > the
> > 
> > No. See above.
> > 
> > > case of a wedge, we don't redo the software part of the reset (i.e.
> > > we
> > > don't reset contexts, etc) per gt_reset():
> > > static int gt_reset(struct xe_gt *gt)
> > > {
> > >         unsigned int fw_ref;
> > >         int err;
> > > 
> > >         if (xe_device_wedged(gt_to_xe(gt)))
> > >                 return -ECANCELED;
> > > 
> > > Maybe instead of banned I can check for banned and wedged here? Or
> > > maybe we should rethink the software reset flow in the event of a
> > > wedge?
> > 
> > The idea with wedged is we leave all hardward state, including the
> > GuC,
> > intacted for inspection. So I think a xe_device_wedged checked here
> > makes sense. This would cover the case where start a queue teardown
> > via
> > a CLEANUP message and mid-flow we wedge the device.
> 
> But hardware state doesn't mean software state. Are you saying when the
> device is wedged we want the memory to all be intact as well? And how
> do we determine when that gets freed? On unbind?

When we wedge a device we take a reference to all queues which perserves
the software queue state and also prevents any queue cleanup flows
regardless of what a user application does. On driver unbind after wedge
we drop wedge reference which should free all memory in the KMD.

Matt

> 
> Thanks,
> Stuart
> 
> > 
> > Matt
> > 
> > > 
> > > Thanks,
> > > Stuart
> > > 
> > > > 
> > > > Matt
> > > > 
> > > > > +       } else {
> > > > > +               xe_guc_ct_send_g2h_handler(&guc->ct, action,
> > > > > +                                          ARRAY_SIZE(action));
> > > > > +       }
> > > > >  }
> > > > >  
> > > > >  static void handle_sched_done(struct xe_guc *guc, struct
> > > > > xe_exec_queue *q,
> > > > > -- 
> > > > > 2.34.1
> > > > > 
> > > 
> 

Re: [PATCH 7/7] drm/xe: Check for GuC responses on disabling scheduling

[Summers, Stuart]

On Fri, 2025-10-03 at 12:49 -0700, Matthew Brost wrote:
> On Fri, Oct 03, 2025 at 01:42:26PM -0600, Summers, Stuart wrote:
> > On Fri, 2025-10-03 at 12:38 -0700, Matthew Brost wrote:
> > > On Fri, Oct 03, 2025 at 12:58:37PM -0600, Summers, Stuart wrote:
> > > > On Fri, 2025-10-03 at 11:54 -0700, Matthew Brost wrote:
> > > > > On Thu, Oct 02, 2025 at 11:04:44PM +0000, Stuart Summers
> > > > > wrote:
> > > > > > In the event the GuC becomes unresponsive during a
> > > > > > scheduling
> > > > > > disable event, we still want the driver to be able to
> > > > > > recover.
> > > > > > This patch follows the same methodology we already have in
> > > > > > place
> > > > > > for TLB invalidation requests, where we send a request to
> > > > > > GuC
> > > > > > and wait for that invalidation done response. If the
> > > > > > response
> > > > > > doesn't come back in time we then at least print a message
> > > > > > indicating the invalidation failed for some reason.
> > > > > > 
> > > > > > In this case, we send the schedule disable and the
> > > > > > expectation
> > > > > > is that GuC will respond with a schedule done response. The
> > > > > > KMD
> > > > > > then catches that response and in turn sends a context
> > > > > > deregistration
> > > > > > response. So in the event GuC becomes unresponsive after we
> > > > > > send
> > > > > > the schedule disable, we actually have two g2h responses
> > > > > > that
> > > > > > have been reserved but never received.
> > > > > > 
> > > > > > To handle this, make sure the pending disable event in the
> > > > > > exec queue gets cleared (i.e. we received that response
> > > > > > from
> > > > > > GuC). If it doesn't in a reasonable amount of time, assume
> > > > > > GuC is dead: ban the exec queue, queue up a GT reset, and
> > > > > > manually call the schedule done handler. Then in the
> > > > > > schedule
> > > > > > done handler, in turn, check whether the context had been
> > > > > > banned. If so, manually call the deregistration done
> > > > > > handler
> > > > > > to ensure all resources related to that exec queue get
> > > > > > cleaned up properly. Without this, if the device becomes
> > > > > > wedged after an exec queue has been created, the attached
> > > > > > resources like the LRC will not get feed properly resulting
> > > > > > in a memory leak.
> > > > > > 
> > > > > > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > > > > > ---
> > > > > >  drivers/gpu/drm/xe/xe_guc_submit.c | 23
> > > > > > ++++++++++++++++++++++-
> > > > > >  1 file changed, 22 insertions(+), 1 deletion(-)
> > > > > > 
> > > > > > diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c
> > > > > > b/drivers/gpu/drm/xe/xe_guc_submit.c
> > > > > > index 45b72bebfc63..a177d87c8524 100644
> > > > > > --- a/drivers/gpu/drm/xe/xe_guc_submit.c
> > > > > > +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
> > > > > > @@ -939,6 +939,9 @@ int xe_guc_read_stopped(struct xe_guc
> > > > > > *guc)
> > > > > >                 GUC_CONTEXT_##enable_disable,              
> > > > > >     
> > > > > >     
> > > > > >      \
> > > > > >         }
> > > > > >  
> > > > > > +static void handle_sched_done(struct xe_guc *guc, struct
> > > > > > xe_exec_queue *q,
> > > > > > +                             u32 runnable_state);
> > > > > > +
> > > > > >  static void disable_scheduling_deregister(struct xe_guc
> > > > > > *guc,
> > > > > >                                           struct
> > > > > > xe_exec_queue
> > > > > > *q)
> > > > > >  {
> > > > > > @@ -974,6 +977,17 @@ static void
> > > > > > disable_scheduling_deregister(struct xe_guc *guc,
> > > > > >         xe_guc_ct_send(&guc->ct, action,
> > > > > > ARRAY_SIZE(action),
> > > > > >                        G2H_LEN_DW_SCHED_CONTEXT_MODE_SET +
> > > > > >                        G2H_LEN_DW_DEREGISTER_CONTEXT, 2);
> > > > > > +
> > > > > > +       ret = wait_event_timeout(guc->ct.wq,
> > > > > > +                               
> > > > > > !exec_queue_pending_disable(q)
> > > > > > > > 
> > > > > > +                                xe_guc_read_stopped(guc),
> > > > > > +                                HZ * 5);
> > > > > 
> > > > > This doesn't look right. Deregister is designed to be fully
> > > > > async. If
> > > > > this flow stops working for whatever reason the GuC is dead
> > > > > and
> > > > > eventually somewhere in driver will detect this and trigger a
> > > > > GT
> > > > > reset
> > > > > which is cleanup all lost H2G.
> > > > > 
> > > > > > +       if (!ret || xe_guc_read_stopped(guc)) {
> > > > > > +               xe_gt_warn(guc_to_gt(guc), "Schedule
> > > > > > disable
> > > > > > failed
> > > > > > to respond");
> > > > > > +               set_exec_queue_banned(q);
> > > > > > +               handle_sched_done(guc, q, 0);
> > > > > > +               xe_gt_reset_async(q->gt);
> > > > > > +       }
> > > > > >  }
> > > > > >  
> > > > > >  static void xe_guc_exec_queue_trigger_cleanup(struct
> > > > > > xe_exec_queue
> > > > > > *q)
> > > > > > @@ -2117,6 +2131,8 @@ g2h_exec_queue_lookup(struct xe_guc
> > > > > > *guc,
> > > > > > u32
> > > > > > guc_id)
> > > > > >         return q;
> > > > > >  }
> > > > > >  
> > > > > > +static void handle_deregister_done(struct xe_guc *guc,
> > > > > > struct
> > > > > > xe_exec_queue *q);
> > > > > > +
> > > > > >  static void deregister_exec_queue(struct xe_guc *guc,
> > > > > > struct
> > > > > > xe_exec_queue *q)
> > > > > >  {
> > > > > >         u32 action[] = {
> > > > > > @@ -2131,7 +2147,12 @@ static void
> > > > > > deregister_exec_queue(struct
> > > > > > xe_guc *guc, struct xe_exec_queue *q)
> > > > > >  
> > > > > >         trace_xe_exec_queue_deregister(q);
> > > > > >  
> > > > > > -       xe_guc_ct_send_g2h_handler(&guc->ct, action,
> > > > > > ARRAY_SIZE(action));
> > > > > > +       if (exec_queue_banned(q)) {
> > > > > > +               handle_deregister_done(guc, q);
> > > > > 
> > > > > This would leave the GuC with reference to guc_id and
> > > > > subsequent
> > > > > reuse
> > > > > of the guc_id (i.e., next register) will fall.
> > > > 
> > > > But again, in this case the GuC is dead and we should be
> > > > getting
> > > > that
> > > > reset event you had mentioned above. The issue I'm having is
> > > 
> > > Banned is a per thing queue and more than likely we wont be doing
> > > a
> > > GT
> > > reset, thus we still need remove references to the queue from the
> > > GuC.
> > 
> > Yeah this makes sense to me. My use of "banned" here was probably
> > not
> > ideal.
> > 
> > > 
> > > > specifically around wedge events. Without a GT wedge, we will
> > > > normally
> > > > go through the GT reset flow and recover like you mentioned.
> > > > But in
> > > > the
> > > 
> > > No. See above.
> > > 
> > > > case of a wedge, we don't redo the software part of the reset
> > > > (i.e.
> > > > we
> > > > don't reset contexts, etc) per gt_reset():
> > > > static int gt_reset(struct xe_gt *gt)
> > > > {
> > > >         unsigned int fw_ref;
> > > >         int err;
> > > > 
> > > >         if (xe_device_wedged(gt_to_xe(gt)))
> > > >                 return -ECANCELED;
> > > > 
> > > > Maybe instead of banned I can check for banned and wedged here?
> > > > Or
> > > > maybe we should rethink the software reset flow in the event of
> > > > a
> > > > wedge?
> > > 
> > > The idea with wedged is we leave all hardward state, including
> > > the
> > > GuC,
> > > intacted for inspection. So I think a xe_device_wedged checked
> > > here
> > > makes sense. This would cover the case where start a queue
> > > teardown
> > > via
> > > a CLEANUP message and mid-flow we wedge the device.
> > 
> > But hardware state doesn't mean software state. Are you saying when
> > the
> > device is wedged we want the memory to all be intact as well? And
> > how
> > do we determine when that gets freed? On unbind?
> 
> When we wedge a device we take a reference to all queues which
> perserves
> the software queue state and also prevents any queue cleanup flows
> regardless of what a user application does. On driver unbind after
> wedge
> we drop wedge reference which should free all memory in the KMD.

Ok that makes sense then. I don't think this is happening correctly if
that's the case (since we rely on that GT reset for most of this). I'll
fix from this angle here - likely applies to both of these last two
patches...

Thanks,
Stuart

> 
> Matt
> 
> > 
> > Thanks,
> > Stuart
> > 
> > > 
> > > Matt
> > > 
> > > > 
> > > > Thanks,
> > > > Stuart
> > > > 
> > > > > 
> > > > > Matt
> > > > > 
> > > > > > +       } else {
> > > > > > +               xe_guc_ct_send_g2h_handler(&guc->ct,
> > > > > > action,
> > > > > > +                                         
> > > > > > ARRAY_SIZE(action));
> > > > > > +       }
> > > > > >  }
> > > > > >  
> > > > > >  static void handle_sched_done(struct xe_guc *guc, struct
> > > > > > xe_exec_queue *q,
> > > > > > -- 
> > > > > > 2.34.1
> > > > > > 
> > > > 
> >