[PATCH v2 0/4] Add test for G2G communications

[PATCH v2 0/4] Add test for G2G communications

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

Platforms with multiple GuCs (multi-GT and/or multi-tile) have a
mechanism for sending messages from one GuC to another. This relies on
the KMD configuring buffers correctly and informing the GuCs about
them. Support for that was merged a while back. So add a test to go
with it.

Also, improve the firmware CSS header structure and defines to better
match the spec and to add missing fields that are useful.

v2: Tweaks for review feedback from Daniele

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>


John Harrison (4):
  drm/xe/guc: Update CSS header structures
  drm/xe/guc: Add firmware build type to available info
  drm/xe: Allow freeing of a managed bo
  drm/xe/guc: Add test for G2G communications

 drivers/gpu/drm/xe/abi/guc_actions_abi.h    |   2 +
 drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c  | 776 ++++++++++++++++++++
 drivers/gpu/drm/xe/tests/xe_live_test_mod.c |   2 +
 drivers/gpu/drm/xe/xe_bo.c                  |   5 +
 drivers/gpu/drm/xe/xe_bo.h                  |   1 +
 drivers/gpu/drm/xe/xe_device_types.h        |   7 +
 drivers/gpu/drm/xe/xe_guc.c                 |   4 +
 drivers/gpu/drm/xe/xe_guc.h                 |   4 +
 drivers/gpu/drm/xe/xe_guc_ct.c              |   5 +
 drivers/gpu/drm/xe/xe_guc_fwif.h            |   1 +
 drivers/gpu/drm/xe/xe_uc_fw.c               |  25 +-
 drivers/gpu/drm/xe/xe_uc_fw_abi.h           |  64 +-
 drivers/gpu/drm/xe/xe_uc_fw_types.h         |   3 +
 13 files changed, 864 insertions(+), 35 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c

-- 
2.49.0

[PATCH v2 1/4] drm/xe/guc: Update CSS header structures

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

Rework the CSS header structure according to recent updates to the GuC
API spec. Also include more field definitions.

v2: Also pass the new GuC specific structure to a GuC specific
function instead of the higher level, generic structure (review
feedback from Daniele).
Also correct naming of CSS_TIME_* fields.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 drivers/gpu/drm/xe/xe_uc_fw.c     | 24 ++++++------
 drivers/gpu/drm/xe/xe_uc_fw_abi.h | 64 ++++++++++++++++++++-----------
 2 files changed, 53 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
index a236f1d37248..f037571865ad 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw.c
+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
@@ -329,7 +329,7 @@ static void uc_fw_fini(struct drm_device *drm, void *arg)
 	xe_uc_fw_change_status(uc_fw, XE_UC_FIRMWARE_SELECTED);
 }
 
-static int guc_read_css_info(struct xe_uc_fw *uc_fw, struct uc_css_header *css)
+static int guc_read_css_info(struct xe_uc_fw *uc_fw, struct uc_css_guc_info *guc_info)
 {
 	struct xe_gt *gt = uc_fw_to_gt(uc_fw);
 	struct xe_uc_fw_version *release = &uc_fw->versions.found[XE_UC_FW_VER_RELEASE];
@@ -344,11 +344,11 @@ static int guc_read_css_info(struct xe_uc_fw *uc_fw, struct uc_css_header *css)
 		return -EINVAL;
 	}
 
-	compatibility->major = FIELD_GET(CSS_SW_VERSION_UC_MAJOR, css->submission_version);
-	compatibility->minor = FIELD_GET(CSS_SW_VERSION_UC_MINOR, css->submission_version);
-	compatibility->patch = FIELD_GET(CSS_SW_VERSION_UC_PATCH, css->submission_version);
+	compatibility->major = FIELD_GET(CSS_SW_VERSION_UC_MAJOR, guc_info->submission_version);
+	compatibility->minor = FIELD_GET(CSS_SW_VERSION_UC_MINOR, guc_info->submission_version);
+	compatibility->patch = FIELD_GET(CSS_SW_VERSION_UC_PATCH, guc_info->submission_version);
 
-	uc_fw->private_data_size = css->private_data_size;
+	uc_fw->private_data_size = guc_info->private_data_size;
 
 	return 0;
 }
@@ -417,8 +417,8 @@ static int parse_css_header(struct xe_uc_fw *uc_fw, const void *fw_data, size_t
 	css = (struct uc_css_header *)fw_data;
 
 	/* Check integrity of size values inside CSS header */
-	size = (css->header_size_dw - css->key_size_dw - css->modulus_size_dw -
-		css->exponent_size_dw) * sizeof(u32);
+	size = (css->header_size_dw - css->rsa_info.key_size_dw - css->rsa_info.modulus_size_dw -
+		css->rsa_info.exponent_size_dw) * sizeof(u32);
 	if (unlikely(size != sizeof(struct uc_css_header))) {
 		drm_warn(&xe->drm,
 			 "%s firmware %s: unexpected header size: %zu != %zu\n",
@@ -431,7 +431,7 @@ static int parse_css_header(struct xe_uc_fw *uc_fw, const void *fw_data, size_t
 	uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
 
 	/* now RSA */
-	uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
+	uc_fw->rsa_size = css->rsa_info.key_size_dw * sizeof(u32);
 
 	/* At least, it should have header, uCode and RSA. Size of all three. */
 	size = sizeof(struct uc_css_header) + uc_fw->ucode_size +
@@ -444,12 +444,12 @@ static int parse_css_header(struct xe_uc_fw *uc_fw, const void *fw_data, size_t
 	}
 
 	/* Get version numbers from the CSS header */
-	release->major = FIELD_GET(CSS_SW_VERSION_UC_MAJOR, css->sw_version);
-	release->minor = FIELD_GET(CSS_SW_VERSION_UC_MINOR, css->sw_version);
-	release->patch = FIELD_GET(CSS_SW_VERSION_UC_PATCH, css->sw_version);
+	release->major = FIELD_GET(CSS_SW_VERSION_UC_MAJOR, css->guc_info.sw_version);
+	release->minor = FIELD_GET(CSS_SW_VERSION_UC_MINOR, css->guc_info.sw_version);
+	release->patch = FIELD_GET(CSS_SW_VERSION_UC_PATCH, css->guc_info.sw_version);
 
 	if (uc_fw->type == XE_UC_FW_TYPE_GUC)
-		return guc_read_css_info(uc_fw, css);
+		return guc_read_css_info(uc_fw, &css->guc_info);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/xe/xe_uc_fw_abi.h b/drivers/gpu/drm/xe/xe_uc_fw_abi.h
index 87ade41209d0..faceb437fd2f 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw_abi.h
+++ b/drivers/gpu/drm/xe/xe_uc_fw_abi.h
@@ -44,6 +44,39 @@
  *    in fw. So driver will load a truncated firmware in this case.
  */
 
+struct uc_css_rsa_info {
+	u32 key_size_dw;
+	u32 modulus_size_dw;
+	u32 exponent_size_dw;
+} __packed;
+
+struct uc_css_guc_info {
+	u32 time;
+#define CSS_TIME_HOUR				(0xFF << 0)
+#define CSS_TIME_MIN				(0xFF << 8)
+#define CSS_TIME_SEC				(0xFFFF << 16)
+	u32 reserved0[5];
+	u32 sw_version;
+#define CSS_SW_VERSION_UC_MAJOR			(0xFF << 16)
+#define CSS_SW_VERSION_UC_MINOR			(0xFF << 8)
+#define CSS_SW_VERSION_UC_PATCH			(0xFF << 0)
+	u32 submission_version;
+	u32 reserved1[11];
+	u32 header_info;
+#define CSS_HEADER_INFO_SVN			(0xFF)
+#define CSS_HEADER_INFO_COPY_VALID		(0x1 << 31)
+	u32 private_data_size;
+	u32 ukernel_info;
+#define CSS_UKERNEL_INFO_DEVICEID		(0xFFFF << 16)
+#define CSS_UKERNEL_INFO_PRODKEY		(0xFF << 8)
+#define CSS_UKERNEL_INFO_BUILDTYPE		(0x3 << 2)
+#define CSS_UKERNEL_INFO_BUILDTYPE_PROD		0
+#define CSS_UKERNEL_INFO_BUILDTYPE_PREPROD	1
+#define CSS_UKERNEL_INFO_BUILDTYPE_DEBUG	2
+#define CSS_UKERNEL_INFO_ENCSTATUS		(0x1 << 1)
+#define CSS_UKERNEL_INFO_COPY_VALID		(0x1 << 0)
+} __packed;
+
 struct uc_css_header {
 	u32 module_type;
 	/*
@@ -52,36 +85,21 @@ struct uc_css_header {
 	 */
 	u32 header_size_dw;
 	u32 header_version;
-	u32 module_id;
+	u32 reserved0;
 	u32 module_vendor;
 	u32 date;
-#define CSS_DATE_DAY			(0xFF << 0)
-#define CSS_DATE_MONTH			(0xFF << 8)
-#define CSS_DATE_YEAR			(0xFFFF << 16)
+#define CSS_DATE_DAY				(0xFF << 0)
+#define CSS_DATE_MONTH				(0xFF << 8)
+#define CSS_DATE_YEAR				(0xFFFF << 16)
 	u32 size_dw; /* uCode plus header_size_dw */
-	u32 key_size_dw;
-	u32 modulus_size_dw;
-	u32 exponent_size_dw;
-	u32 time;
-#define CSS_TIME_HOUR			(0xFF << 0)
-#define CSS_DATE_MIN			(0xFF << 8)
-#define CSS_DATE_SEC			(0xFFFF << 16)
-	char username[8];
-	char buildnumber[12];
-	u32 sw_version;
-#define CSS_SW_VERSION_UC_MAJOR		(0xFF << 16)
-#define CSS_SW_VERSION_UC_MINOR		(0xFF << 8)
-#define CSS_SW_VERSION_UC_PATCH		(0xFF << 0)
 	union {
-		u32 submission_version; /* only applies to GuC */
-		u32 reserved2;
+		u32 reserved1[3];
+		struct uc_css_rsa_info rsa_info;
 	};
-	u32 reserved0[12];
 	union {
-		u32 private_data_size; /* only applies to GuC */
-		u32 reserved1;
+		u32 reserved2[22];
+		struct uc_css_guc_info guc_info;
 	};
-	u32 header_info;
 } __packed;
 static_assert(sizeof(struct uc_css_header) == 128);
 
-- 
2.49.0

[PATCH v2 2/4] drm/xe/guc: Add firmware build type to available info

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

Some test features are not available in production builds of the GuC
firmware. So add the build type field to the available information
that tests can inspect to decide if they should skip or run.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/xe/xe_uc_fw.c       | 1 +
 drivers/gpu/drm/xe/xe_uc_fw_types.h | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
index f037571865ad..ae8963556c0c 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw.c
+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
@@ -348,6 +348,7 @@ static int guc_read_css_info(struct xe_uc_fw *uc_fw, struct uc_css_guc_info *guc
 	compatibility->minor = FIELD_GET(CSS_SW_VERSION_UC_MINOR, guc_info->submission_version);
 	compatibility->patch = FIELD_GET(CSS_SW_VERSION_UC_PATCH, guc_info->submission_version);
 
+	uc_fw->build_type = FIELD_GET(CSS_UKERNEL_INFO_BUILDTYPE, guc_info->ukernel_info);
 	uc_fw->private_data_size = guc_info->private_data_size;
 
 	return 0;
diff --git a/drivers/gpu/drm/xe/xe_uc_fw_types.h b/drivers/gpu/drm/xe/xe_uc_fw_types.h
index 914026015019..77a1dcf8b4ed 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw_types.h
+++ b/drivers/gpu/drm/xe/xe_uc_fw_types.h
@@ -147,6 +147,9 @@ struct xe_uc_fw {
 
 	/** @private_data_size: size of private data found in uC css header */
 	u32 private_data_size;
+
+	/** @build_type: Firmware build type (see CSS_UKERNEL_INFO_BUILDTYPE for definitions) */
+	u32 build_type;
 };
 
 #endif
-- 
2.49.0

[PATCH v2 3/4] drm/xe: Allow freeing of a managed bo

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

If a bo is created via xe_managed_bo_create_pin_map() then it cannot be
freed by the driver using xe_bo_unpin_map_no_vm(), or indeed any other
existing function. The DRM layer will still have a pointer stashed
away for later freeing, causing a invalid memory access on driver
unload. So add a helper for releasing the DRM action as well.

v2: Drop 'xe' parameter (review feedbak from Michal W)

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 drivers/gpu/drm/xe/xe_bo.c | 5 +++++
 drivers/gpu/drm/xe/xe_bo.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index ffca1cea5585..87aa0f5b2b2a 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -2222,6 +2222,11 @@ struct xe_bo *xe_managed_bo_create_pin_map(struct xe_device *xe, struct xe_tile
 	return bo;
 }
 
+void xe_managed_bo_unpin_map_no_vm(struct xe_bo *bo)
+{
+	devm_release_action(xe_bo_device(bo)->drm.dev, __xe_bo_unpin_map_no_vm, bo);
+}
+
 struct xe_bo *xe_managed_bo_create_from_data(struct xe_device *xe, struct xe_tile *tile,
 					     const void *data, size_t size, u32 flags)
 {
diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h
index 8cce413b5235..298eef403505 100644
--- a/drivers/gpu/drm/xe/xe_bo.h
+++ b/drivers/gpu/drm/xe/xe_bo.h
@@ -122,6 +122,7 @@ struct xe_bo *xe_bo_create_pin_map_at_aligned(struct xe_device *xe,
 					      u64 alignment);
 struct xe_bo *xe_managed_bo_create_pin_map(struct xe_device *xe, struct xe_tile *tile,
 					   size_t size, u32 flags);
+void xe_managed_bo_unpin_map_no_vm(struct xe_bo *bo);
 struct xe_bo *xe_managed_bo_create_from_data(struct xe_device *xe, struct xe_tile *tile,
 					     const void *data, size_t size, u32 flags);
 int xe_managed_bo_reinit_in_vram(struct xe_device *xe, struct xe_tile *tile, struct xe_bo **src);
-- 
2.49.0

[PATCH v2 4/4] drm/xe/guc: Add test for G2G communications

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

Add a test for sending messages from every GuC to every other GuC to
test G2G communications.

Note that, being a debug only feature, the test interface only exists
in pre-production builds of the GuC firmware.

v2: Fix 'default' case to actually use the driver's registration code
as well as allocation. Add comments explaining the different test
types. Fix (C) date and an assert. Review feedback from Daniele.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 drivers/gpu/drm/xe/abi/guc_actions_abi.h    |   2 +
 drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c  | 776 ++++++++++++++++++++
 drivers/gpu/drm/xe/tests/xe_live_test_mod.c |   2 +
 drivers/gpu/drm/xe/xe_device_types.h        |   7 +
 drivers/gpu/drm/xe/xe_guc.c                 |   4 +
 drivers/gpu/drm/xe/xe_guc.h                 |   4 +
 drivers/gpu/drm/xe/xe_guc_ct.c              |   5 +
 drivers/gpu/drm/xe/xe_guc_fwif.h            |   1 +
 8 files changed, 801 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c

diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
index 81eb046aeebf..0395998ca75c 100644
--- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
@@ -154,6 +154,8 @@ enum xe_guc_action {
 	XE_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE = 0x8003,
 	XE_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED = 0x8004,
 	XE_GUC_ACTION_NOTIFY_EXCEPTION = 0x8005,
+	XE_GUC_ACTION_TEST_G2G_SEND = 0xF001,
+	XE_GUC_ACTION_TEST_G2G_RECV = 0xF002,
 	XE_GUC_ACTION_LIMIT
 };
 
diff --git a/drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c b/drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c
new file mode 100644
index 000000000000..3b213fcae916
--- /dev/null
+++ b/drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c
@@ -0,0 +1,776 @@
+// SPDX-License-Identifier: GPL-2.0 AND MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include <linux/delay.h>
+
+#include <kunit/test.h>
+#include <kunit/visibility.h>
+
+#include "tests/xe_kunit_helpers.h"
+#include "tests/xe_pci_test.h"
+#include "tests/xe_test.h"
+
+#include "xe_bo.h"
+#include "xe_device.h"
+#include "xe_pm.h"
+
+/*
+ * There are different ways to allocate the G2G buffers. The plan for this test
+ * is to make sure that all the possible options work. The particular option
+ * chosen by the driver may vary from one platform to another, it may also change
+ * with time. So to ensure consistency of testing, the relevant driver code is
+ * replicated here to guarantee it won't change without the test being updated
+ * to keep testing the other options.
+ *
+ * In order to test the actual code being used by the driver, there is also the
+ * 'default' scheme. That will use the official driver routines to test whatever
+ * method the driver is using on the current platform at the current time.
+ */
+enum {
+	/* Driver defined allocation scheme */
+	G2G_CTB_TYPE_DEFAULT,
+	/* Single buffer in host memory */
+	G2G_CTB_TYPE_HOST,
+	/* Single buffer in a specific tile, loops across all tiles */
+	G2G_CTB_TYPE_TILE,
+};
+
+/*
+ * Payload is opaque to GuC. So KMD can define any structure or size it wants.
+ */
+struct g2g_test_payload  {
+	u32 tx_dev;
+	u32 tx_tile;
+	u32 rx_dev;
+	u32 rx_tile;
+	u32 seqno;
+};
+
+static void g2g_test_send(struct kunit *test, struct xe_guc *guc,
+			  u32 far_tile, u32 far_dev,
+			  struct g2g_test_payload *payload)
+{
+	struct xe_device *xe = guc_to_xe(guc);
+	struct xe_gt *gt = guc_to_gt(guc);
+	u32 *action, total;
+	size_t payload_len;
+	int ret;
+
+	static_assert(IS_ALIGNED(sizeof(*payload), sizeof(u32)));
+	payload_len = sizeof(*payload) / sizeof(u32);
+
+	total = 4 + payload_len;
+	action = kunit_kmalloc_array(test, total, sizeof(*action), GFP_KERNEL);
+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, action);
+
+	action[0] = XE_GUC_ACTION_TEST_G2G_SEND;
+	action[1] = far_tile;
+	action[2] = far_dev;
+	action[3] = payload_len;
+	memcpy(action + 4, payload, payload_len * sizeof(u32));
+
+	atomic_inc(&xe->g2g_test_count);
+
+	/*
+	 * Should specify the expected response notification here. Problem is that
+	 * the response will be coming from a different GuC. By the end, it should
+	 * all add up as long as an equal number of messages are sent from each GuC
+	 * and to each GuC. However, in the middle negative reservation space errors
+	 * and such like can occur. Rather than add intrusive changes to the CT layer
+	 * it is simpler to just not bother counting it at all. The system should be
+	 * idle when running the selftest, and the selftest's notification total size
+	 * is well within the G2H allocation size. So there should be no issues with
+	 * needing to block for space, which is all the tracking code is really for.
+	 */
+	ret = xe_guc_ct_send(&guc->ct, action, total, 0, 0);
+	kunit_kfree(test, action);
+	KUNIT_ASSERT_EQ_MSG(test, 0, ret, "G2G send failed: %d [%d:%d -> %d:%d]\n", ret,
+			    gt_to_tile(gt)->id, G2G_DEV(gt), far_tile, far_dev);
+}
+
+/*
+ * NB: Can't use KUNIT_ASSERT and friends in here as this is called asynchronously
+ * from the G2H notification handler. Need that to actually complete rather than
+ * thread-abort in order to keep the rest of the driver alive!
+ */
+int xe_guc_g2g_test_notification(struct xe_guc *guc, u32 *msg, u32 len)
+{
+	struct xe_device *xe = guc_to_xe(guc);
+	struct xe_gt *rx_gt = guc_to_gt(guc), *test_gt, *tx_gt = NULL;
+	u32 tx_tile, tx_dev, rx_tile, rx_dev, idx, got_len;
+	struct g2g_test_payload *payload;
+	size_t payload_len;
+	int ret = 0, i;
+
+	payload_len = sizeof(*payload) / sizeof(u32);
+
+	if (unlikely(len != (G2H_LEN_DW_G2G_NOTIFY_MIN + payload_len))) {
+		xe_gt_err(rx_gt, "G2G test notification invalid length %u", len);
+		ret = -EPROTO;
+		goto done;
+	}
+
+	tx_tile = msg[0];
+	tx_dev = msg[1];
+	got_len = msg[2];
+	payload = (struct g2g_test_payload *)(msg + 3);
+
+	rx_tile = gt_to_tile(rx_gt)->id;
+	rx_dev = G2G_DEV(rx_gt);
+
+	if (got_len != payload_len) {
+		xe_gt_err(rx_gt, "G2G: Invalid payload length: %u vs %zu\n", got_len, payload_len);
+		ret = -EPROTO;
+		goto done;
+	}
+
+	if (payload->tx_dev != tx_dev || payload->tx_tile != tx_tile ||
+	    payload->rx_dev != rx_dev || payload->rx_tile != rx_tile) {
+		xe_gt_err(rx_gt, "G2G: Invalid payload: %d:%d -> %d:%d vs %d:%d -> %d:%d! [%d]\n",
+			  payload->tx_tile, payload->tx_dev, payload->rx_tile, payload->rx_dev,
+			  tx_tile, tx_dev, rx_tile, rx_dev, payload->seqno);
+		ret = -EPROTO;
+		goto done;
+	}
+
+	if (!xe->g2g_test_array) {
+		xe_gt_err(rx_gt, "G2G: Missing test array!\n");
+		ret = -ENOMEM;
+		goto done;
+	}
+
+	for_each_gt(test_gt, xe, i) {
+		if (gt_to_tile(test_gt)->id != tx_tile)
+			continue;
+
+		if (G2G_DEV(test_gt) != tx_dev)
+			continue;
+
+		if (tx_gt) {
+			xe_gt_err(rx_gt, "G2G: Got duplicate TX GTs: %d vs %d for %d:%d!\n",
+				  tx_gt->info.id, test_gt->info.id, tx_tile, tx_dev);
+			ret = -EINVAL;
+			goto done;
+		}
+
+		tx_gt = test_gt;
+	}
+	if (!tx_gt) {
+		xe_gt_err(rx_gt, "G2G: Failed to find a TX GT for %d:%d!\n", tx_tile, tx_dev);
+		ret = -EINVAL;
+		goto done;
+	}
+
+	idx = (tx_gt->info.id * xe->info.gt_count) + rx_gt->info.id;
+
+	if (xe->g2g_test_array[idx] != payload->seqno - 1) {
+		xe_gt_err(rx_gt, "G2G: Seqno mismatch %d vs %d for %d:%d -> %d:%d!\n",
+			  xe->g2g_test_array[idx], payload->seqno - 1,
+			  tx_tile, tx_dev, rx_tile, rx_dev);
+		ret = -EINVAL;
+		goto done;
+	}
+
+	xe->g2g_test_array[idx] = payload->seqno;
+
+done:
+	atomic_dec(&xe->g2g_test_count);
+	return ret;
+}
+
+/*
+ * Send the given seqno from all GuCs to all other GuCs in tile/GT order
+ */
+static void g2g_test_in_order(struct kunit *test, struct xe_device *xe, u32 seqno)
+{
+	struct xe_gt *near_gt, *far_gt;
+	int i, j;
+
+	for_each_gt(near_gt, xe, i) {
+		u32 near_tile = gt_to_tile(near_gt)->id;
+		u32 near_dev = G2G_DEV(near_gt);
+
+		for_each_gt(far_gt, xe, j) {
+			u32 far_tile = gt_to_tile(far_gt)->id;
+			u32 far_dev = G2G_DEV(far_gt);
+			struct g2g_test_payload payload;
+
+			if (far_gt->info.id == near_gt->info.id)
+				continue;
+
+			payload.tx_dev = near_dev;
+			payload.tx_tile = near_tile;
+			payload.rx_dev = far_dev;
+			payload.rx_tile = far_tile;
+			payload.seqno = seqno;
+			g2g_test_send(test, &near_gt->uc.guc, far_tile, far_dev, &payload);
+		}
+	}
+}
+
+#define WAIT_TIME_MS	100
+#define WAIT_COUNT	(1000 / WAIT_TIME_MS)
+
+static void g2g_wait_for_complete(void *_xe)
+{
+	struct xe_device *xe = (struct xe_device *)_xe;
+	struct kunit *test = kunit_get_current_test();
+	int wait = 0;
+
+	/* Wait for all G2H messages to be received */
+	while (atomic_read(&xe->g2g_test_count)) {
+		if (++wait > WAIT_COUNT)
+			break;
+
+		msleep(WAIT_TIME_MS);
+	}
+
+	KUNIT_ASSERT_EQ_MSG(test, 0, atomic_read(&xe->g2g_test_count),
+			    "Timed out waiting for notifications\n");
+	kunit_info(test, "Got all notifications back\n");
+}
+
+#undef WAIT_TIME_MS
+#undef WAIT_COUNT
+
+static void g2g_clean_array(void *_xe)
+{
+	struct xe_device *xe = (struct xe_device *)_xe;
+
+	xe->g2g_test_array = NULL;
+}
+
+#define NUM_LOOPS	16
+
+static void g2g_run_test(struct kunit *test, struct xe_device *xe)
+{
+	u32 seqno, max_array;
+	int ret, i, j;
+
+	max_array = xe->info.gt_count * xe->info.gt_count;
+	xe->g2g_test_array = kunit_kcalloc(test, max_array, sizeof(u32), GFP_KERNEL);
+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, xe->g2g_test_array);
+
+	ret = kunit_add_action_or_reset(test, g2g_clean_array, xe);
+	KUNIT_ASSERT_EQ_MSG(test, 0, ret, "Failed to register clean up action\n");
+
+	/*
+	 * Send incrementing seqnos from all GuCs to all other GuCs in tile/GT order.
+	 * Tile/GT order doesn't really mean anything to the hardware but it is going
+	 * to be a fixed sequence every time.
+	 *
+	 * Verify that each one comes back having taken the correct route.
+	 */
+	ret = kunit_add_action(test, g2g_wait_for_complete, xe);
+	KUNIT_ASSERT_EQ_MSG(test, 0, ret, "Failed to register clean up action\n");
+	for (seqno = 1; seqno < NUM_LOOPS; seqno++)
+		g2g_test_in_order(test, xe, seqno);
+	seqno--;
+
+	kunit_release_action(test, &g2g_wait_for_complete, xe);
+
+	/* Check for the final seqno in each slot */
+	for (i = 0; i < xe->info.gt_count; i++) {
+		for (j = 0; j < xe->info.gt_count; j++) {
+			u32 idx = (j * xe->info.gt_count) + i;
+
+			if (i == j)
+				KUNIT_ASSERT_EQ_MSG(test, 0, xe->g2g_test_array[idx],
+						    "identity seqno modified: %d for %dx%d!\n",
+						    xe->g2g_test_array[idx], i, j);
+			else
+				KUNIT_ASSERT_EQ_MSG(test, seqno, xe->g2g_test_array[idx],
+						    "invalid seqno: %d vs %d for %dx%d!\n",
+						    xe->g2g_test_array[idx], seqno, i, j);
+		}
+	}
+
+	kunit_kfree(test, xe->g2g_test_array);
+	kunit_release_action(test, &g2g_clean_array, xe);
+
+	kunit_info(test, "Test passed\n");
+}
+
+#undef NUM_LOOPS
+
+static void g2g_ct_stop(struct xe_guc *guc)
+{
+	struct xe_gt *remote_gt, *gt = guc_to_gt(guc);
+	struct xe_device *xe = gt_to_xe(gt);
+	int i, t;
+
+	for_each_gt(remote_gt, xe, i) {
+		u32 tile, dev;
+
+		if (remote_gt->info.id == gt->info.id)
+			continue;
+
+		tile = gt_to_tile(remote_gt)->id;
+		dev = G2G_DEV(remote_gt);
+
+		for (t = 0; t < XE_G2G_TYPE_LIMIT; t++)
+			guc_g2g_deregister(guc, tile, dev, t);
+	}
+}
+
+/* Size of a single allocation that contains all G2G CTBs across all GTs */
+static u32 g2g_ctb_size(struct kunit *test, struct xe_device *xe)
+{
+	unsigned int count = xe->info.gt_count;
+	u32 num_channels = (count * (count - 1)) / 2;
+
+	kunit_info(test, "Size: (%d * %d / 2) * %d * 0x%08X + 0x%08X => 0x%08X [%d]\n",
+		   count, count - 1, XE_G2G_TYPE_LIMIT, G2G_BUFFER_SIZE, G2G_DESC_AREA_SIZE,
+		   num_channels * XE_G2G_TYPE_LIMIT * G2G_BUFFER_SIZE + G2G_DESC_AREA_SIZE,
+		   num_channels * XE_G2G_TYPE_LIMIT);
+
+	return num_channels * XE_G2G_TYPE_LIMIT * G2G_BUFFER_SIZE + G2G_DESC_AREA_SIZE;
+}
+
+/*
+ * Use the driver's regular CTB allocation scheme.
+ */
+static void g2g_alloc_default(struct kunit *test, struct xe_device *xe)
+{
+	struct xe_gt *gt;
+	int i;
+
+	kunit_info(test, "Default [tiles = %d, GTs = %d]\n",
+		   xe->info.tile_count, xe->info.gt_count);
+
+	for_each_gt(gt, xe, i) {
+		struct xe_guc *guc = &gt->uc.guc;
+		int ret;
+
+		ret = guc_g2g_alloc(guc);
+		KUNIT_ASSERT_EQ_MSG(test, 0, ret, "G2G alloc failed: %pe", ERR_PTR(ret));
+		continue;
+	}
+}
+
+static void g2g_distribute(struct kunit *test, struct xe_device *xe, struct xe_bo *bo)
+{
+	struct xe_gt *root_gt, *gt;
+	int i;
+
+	root_gt = xe_device_get_gt(xe, 0);
+	root_gt->uc.guc.g2g.bo = bo;
+	root_gt->uc.guc.g2g.owned = true;
+	kunit_info(test, "[%d.%d] Assigned 0x%p\n", gt_to_tile(root_gt)->id, root_gt->info.id, bo);
+
+	for_each_gt(gt, xe, i) {
+		if (gt->info.id != 0) {
+			gt->uc.guc.g2g.owned = false;
+			gt->uc.guc.g2g.bo = xe_bo_get(bo);
+			kunit_info(test, "[%d.%d] Pinned 0x%p\n",
+				   gt_to_tile(gt)->id, gt->info.id, gt->uc.guc.g2g.bo);
+		}
+
+		KUNIT_ASSERT_NOT_ERR_OR_NULL(test, gt->uc.guc.g2g.bo);
+	}
+}
+
+/*
+ * Allocate a single blob on the host and split between all G2G CTBs.
+ */
+static void g2g_alloc_host(struct kunit *test, struct xe_device *xe)
+{
+	struct xe_bo *bo;
+	u32 g2g_size;
+
+	kunit_info(test, "Host [tiles = %d, GTs = %d]\n", xe->info.tile_count, xe->info.gt_count);
+
+	g2g_size = g2g_ctb_size(test, xe);
+	bo = xe_managed_bo_create_pin_map(xe, xe_device_get_root_tile(xe), g2g_size,
+					  XE_BO_FLAG_SYSTEM |
+					  XE_BO_FLAG_GGTT |
+					  XE_BO_FLAG_GGTT_ALL |
+					  XE_BO_FLAG_GGTT_INVALIDATE);
+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, bo);
+	kunit_info(test, "[HST] G2G buffer create: 0x%p\n", bo);
+
+	xe_map_memset(xe, &bo->vmap, 0, 0, g2g_size);
+
+	g2g_distribute(test, xe, bo);
+}
+
+/*
+ * Allocate a single blob on the given tile and split between all G2G CTBs.
+ */
+static void g2g_alloc_tile(struct kunit *test, struct xe_device *xe, struct xe_tile *tile)
+{
+	struct xe_bo *bo;
+	u32 g2g_size;
+
+	KUNIT_ASSERT_TRUE(test, IS_DGFX(xe));
+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, tile);
+
+	kunit_info(test, "Tile %d [tiles = %d, GTs = %d]\n",
+		   tile->id, xe->info.tile_count, xe->info.gt_count);
+
+	g2g_size = g2g_ctb_size(test, xe);
+	bo = xe_managed_bo_create_pin_map(xe, tile, g2g_size,
+					  XE_BO_FLAG_VRAM_IF_DGFX(tile) |
+					  XE_BO_FLAG_GGTT |
+					  XE_BO_FLAG_GGTT_ALL |
+					  XE_BO_FLAG_GGTT_INVALIDATE);
+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, bo);
+	kunit_info(test, "[%d.*] G2G buffer create: 0x%p\n", tile->id, bo);
+
+	xe_map_memset(xe, &bo->vmap, 0, 0, g2g_size);
+
+	g2g_distribute(test, xe, bo);
+}
+
+static void g2g_free(struct kunit *test, struct xe_device *xe)
+{
+	struct xe_gt *gt;
+	struct xe_bo *bo;
+	int i;
+
+	for_each_gt(gt, xe, i) {
+		bo = gt->uc.guc.g2g.bo;
+		if (!bo)
+			continue;
+
+		if (gt->uc.guc.g2g.owned) {
+			xe_managed_bo_unpin_map_no_vm(bo);
+			kunit_info(test, "[%d.%d] Unmapped 0x%p\n",
+				   gt_to_tile(gt)->id, gt->info.id, bo);
+		} else {
+			xe_bo_put(bo);
+			kunit_info(test, "[%d.%d] Unpinned 0x%p\n",
+				   gt_to_tile(gt)->id, gt->info.id, bo);
+		}
+
+		gt->uc.guc.g2g.bo = NULL;
+	}
+}
+
+static void g2g_stop(struct kunit *test, struct xe_device *xe)
+{
+	struct xe_gt *gt;
+	int i;
+
+	for_each_gt(gt, xe, i) {
+		struct xe_guc *guc = &gt->uc.guc;
+
+		if (!guc->g2g.bo)
+			continue;
+
+		g2g_ct_stop(guc);
+	}
+
+	g2g_free(test, xe);
+}
+
+/*
+ * Generate a unique id for each bi-directional CTB for each pair of
+ * near and far tiles/devices. The id can then be used as an index into
+ * a single allocation that is sub-divided into multiple CTBs.
+ *
+ * For example, with two devices per tile and two tiles, the table should
+ * look like:
+ *           Far <tile>.<dev>
+ *         0.0   0.1   1.0   1.1
+ * N 0.0  --/-- 00/01 02/03 04/05
+ * e 0.1  01/00 --/-- 06/07 08/09
+ * a 1.0  03/02 07/06 --/-- 10/11
+ * r 1.1  05/04 09/08 11/10 --/--
+ *
+ * Where each entry is Rx/Tx channel id.
+ *
+ * So GuC #3 (tile 1, dev 1) talking to GuC #2 (tile 1, dev 0) would
+ * be reading from channel #11 and writing to channel #10. Whereas,
+ * GuC #2 talking to GuC #3 would be read on #10 and write to #11.
+ */
+static int g2g_slot_flat(u32 near_tile, u32 near_dev, u32 far_tile, u32 far_dev,
+			 u32 type, u32 max_inst, bool have_dev)
+{
+	u32 near = near_tile, far = far_tile;
+	u32 idx = 0, x, y, direction;
+	int i;
+
+	if (have_dev) {
+		near = (near << 1) | near_dev;
+		far = (far << 1) | far_dev;
+	}
+
+	/* No need to send to one's self */
+	if (far == near)
+		return -1;
+
+	if (far > near) {
+		/* Top right table half */
+		x = far;
+		y = near;
+
+		/* T/R is 'forwards' direction */
+		direction = type;
+	} else {
+		/* Bottom left table half */
+		x = near;
+		y = far;
+
+		/* B/L is 'backwards' direction */
+		direction = (1 - type);
+	}
+
+	/* Count the rows prior to the target */
+	for (i = y; i > 0; i--)
+		idx += max_inst - i;
+
+	/* Count this row up to the target */
+	idx += (x - 1 - y);
+
+	/* Slots are in Rx/Tx pairs */
+	idx *= 2;
+
+	/* Pick Rx/Tx direction */
+	idx += direction;
+
+	return idx;
+}
+
+static int g2g_register_flat(struct xe_guc *guc, u32 far_tile, u32 far_dev, u32 type, bool have_dev)
+{
+	struct xe_gt *gt = guc_to_gt(guc);
+	struct xe_device *xe = gt_to_xe(gt);
+	u32 near_tile = gt_to_tile(gt)->id;
+	u32 near_dev = G2G_DEV(gt);
+	u32 max = xe->info.gt_count;
+	int idx;
+	u32 base, desc, buf;
+
+	if (!guc->g2g.bo)
+		return -ENODEV;
+
+	idx = g2g_slot_flat(near_tile, near_dev, far_tile, far_dev, type, max, have_dev);
+	xe_assert(xe, idx >= 0);
+
+	base = guc_bo_ggtt_addr(guc, guc->g2g.bo);
+	desc = base + idx * G2G_DESC_SIZE;
+	buf = base + idx * G2G_BUFFER_SIZE + G2G_DESC_AREA_SIZE;
+
+	xe_assert(xe, (desc - base + G2G_DESC_SIZE) <= G2G_DESC_AREA_SIZE);
+	xe_assert(xe, (buf - base + G2G_BUFFER_SIZE) <= xe_bo_size(guc->g2g.bo));
+
+	return guc_action_register_g2g_buffer(guc, type, far_tile, far_dev,
+					      desc, buf, G2G_BUFFER_SIZE);
+}
+
+static void g2g_start(struct kunit *test, struct xe_guc *guc)
+{
+	struct xe_gt *remote_gt, *gt = guc_to_gt(guc);
+	struct xe_device *xe = gt_to_xe(gt);
+	unsigned int i;
+	int t, ret;
+	bool have_dev;
+
+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, guc->g2g.bo);
+
+	/* GuC interface will need extending if more GT device types are ever created. */
+	KUNIT_ASSERT_TRUE(test,
+			  (gt->info.type == XE_GT_TYPE_MAIN) ||
+			  (gt->info.type == XE_GT_TYPE_MEDIA));
+
+	/* Channel numbering depends on whether there are multiple GTs per tile */
+	have_dev = xe->info.gt_count > xe->info.tile_count;
+
+	for_each_gt(remote_gt, xe, i) {
+		u32 tile, dev;
+
+		if (remote_gt->info.id == gt->info.id)
+			continue;
+
+		tile = gt_to_tile(remote_gt)->id;
+		dev = G2G_DEV(remote_gt);
+
+		for (t = 0; t < XE_G2G_TYPE_LIMIT; t++) {
+			ret = g2g_register_flat(guc, tile, dev, t, have_dev);
+			KUNIT_ASSERT_EQ_MSG(test, 0, ret, "G2G register failed: %pe", ERR_PTR(ret));
+		}
+	}
+}
+
+static void g2g_reinit(struct kunit *test, struct xe_device *xe, int ctb_type, struct xe_tile *tile)
+{
+	struct xe_gt *gt;
+	int i, found = 0;
+
+	g2g_stop(test, xe);
+
+	for_each_gt(gt, xe, i) {
+		struct xe_guc *guc = &gt->uc.guc;
+
+		KUNIT_ASSERT_NULL(test, guc->g2g.bo);
+	}
+
+	switch (ctb_type) {
+	case G2G_CTB_TYPE_DEFAULT:
+		g2g_alloc_default(test, xe);
+		break;
+
+	case G2G_CTB_TYPE_HOST:
+		g2g_alloc_host(test, xe);
+		break;
+
+	case G2G_CTB_TYPE_TILE:
+		g2g_alloc_tile(test, xe, tile);
+		break;
+
+	default:
+		KUNIT_ASSERT_TRUE(test, false);
+	}
+
+	for_each_gt(gt, xe, i) {
+		struct xe_guc *guc = &gt->uc.guc;
+
+		if (!guc->g2g.bo)
+			continue;
+
+		if (ctb_type == G2G_CTB_TYPE_DEFAULT)
+			guc_g2g_start(guc);
+		else
+			g2g_start(test, guc);
+		found++;
+	}
+
+	KUNIT_ASSERT_GT_MSG(test, found, 1, "insufficient G2G channels running: %d", found);
+
+	kunit_info(test, "Testing across %d GTs\n", found);
+}
+
+static void g2g_recreate_ctb(void *_xe)
+{
+	struct xe_device *xe = (struct xe_device *)_xe;
+	struct kunit *test = kunit_get_current_test();
+
+	g2g_stop(test, xe);
+
+	if (xe_guc_g2g_wanted(xe))
+		g2g_reinit(test, xe, G2G_CTB_TYPE_DEFAULT, NULL);
+}
+
+static void g2g_pm_runtime_put(void *_xe)
+{
+	struct xe_device *xe = (struct xe_device *)_xe;
+
+	xe_pm_runtime_put(xe);
+}
+
+static void g2g_pm_runtime_get(struct kunit *test)
+{
+	struct xe_device *xe = test->priv;
+	int ret;
+
+	xe_pm_runtime_get(xe);
+	ret = kunit_add_action_or_reset(test, g2g_pm_runtime_put, xe);
+	KUNIT_ASSERT_EQ_MSG(test, 0, ret, "Failed to register runtime PM action\n");
+}
+
+static void g2g_check_skip(struct kunit *test)
+{
+	struct xe_device *xe = test->priv;
+	struct xe_gt *gt;
+	int i;
+
+	if (IS_SRIOV_VF(xe))
+		kunit_skip(test, "not supported from a VF");
+
+	if (xe->info.gt_count <= 1)
+		kunit_skip(test, "not enough GTs");
+
+	for_each_gt(gt, xe, i) {
+		struct xe_guc *guc = &gt->uc.guc;
+
+		if (guc->fw.build_type == CSS_UKERNEL_INFO_BUILDTYPE_PROD)
+			kunit_skip(test,
+				   "G2G test interface not available in production firmware builds\n");
+	}
+}
+
+/*
+ * Simple test that does not try to recreate the CTBs.
+ * Requires that the platform already enables G2G comms
+ * but has no risk of leaving the system in a broken state
+ * afterwards.
+ */
+static void xe_live_guc_g2g_kunit_default(struct kunit *test)
+{
+	struct xe_device *xe = test->priv;
+
+	if (!xe_guc_g2g_wanted(xe))
+		kunit_skip(test, "G2G not enabled");
+
+	g2g_check_skip(test);
+
+	g2g_pm_runtime_get(test);
+
+	kunit_info(test, "Testing default CTBs\n");
+	g2g_run_test(test, xe);
+
+	kunit_release_action(test, &g2g_pm_runtime_put, xe);
+}
+
+/*
+ * More complex test that re-creates the CTBs in various location to
+ * test access to each location from each GuC. Can be run even on
+ * systems that do not enable G2G by default. On the other hand,
+ * because it recreates the CTBs, if something goes wrong it could
+ * leave the system with broken G2G comms.
+ */
+static void xe_live_guc_g2g_kunit_allmem(struct kunit *test)
+{
+	struct xe_device *xe = test->priv;
+	int ret;
+
+	g2g_check_skip(test);
+
+	g2g_pm_runtime_get(test);
+
+	/* Make sure to leave the system as we found it */
+	ret = kunit_add_action_or_reset(test, g2g_recreate_ctb, xe);
+	KUNIT_ASSERT_EQ_MSG(test, 0, ret, "Failed to register CTB re-creation action\n");
+
+	kunit_info(test, "Testing CTB type 'default'...\n");
+	g2g_reinit(test, xe, G2G_CTB_TYPE_DEFAULT, NULL);
+	g2g_run_test(test, xe);
+
+	kunit_info(test, "Testing CTB type 'host'...\n");
+	g2g_reinit(test, xe, G2G_CTB_TYPE_HOST, NULL);
+	g2g_run_test(test, xe);
+
+	if (IS_DGFX(xe)) {
+		struct xe_tile *tile;
+		int id;
+
+		for_each_tile(tile, xe, id) {
+			kunit_info(test, "Testing CTB type 'tile: #%d'...\n", id);
+
+			g2g_reinit(test, xe, G2G_CTB_TYPE_TILE, tile);
+			g2g_run_test(test, xe);
+		}
+	} else {
+		kunit_info(test, "Skipping local memory on integrated platform\n");
+	}
+
+	kunit_release_action(test, g2g_recreate_ctb, xe);
+	kunit_release_action(test, g2g_pm_runtime_put, xe);
+}
+
+static struct kunit_case xe_guc_g2g_tests[] = {
+	KUNIT_CASE_PARAM(xe_live_guc_g2g_kunit_default, xe_pci_live_device_gen_param),
+	KUNIT_CASE_PARAM(xe_live_guc_g2g_kunit_allmem, xe_pci_live_device_gen_param),
+	{}
+};
+
+VISIBLE_IF_KUNIT
+struct kunit_suite xe_guc_g2g_test_suite = {
+	.name = "xe_guc_g2g",
+	.test_cases = xe_guc_g2g_tests,
+	.init = xe_kunit_helper_xe_device_live_test_init,
+};
+EXPORT_SYMBOL_IF_KUNIT(xe_guc_g2g_test_suite);
diff --git a/drivers/gpu/drm/xe/tests/xe_live_test_mod.c b/drivers/gpu/drm/xe/tests/xe_live_test_mod.c
index 81277c77016d..c55e46f1ae92 100644
--- a/drivers/gpu/drm/xe/tests/xe_live_test_mod.c
+++ b/drivers/gpu/drm/xe/tests/xe_live_test_mod.c
@@ -10,12 +10,14 @@ extern struct kunit_suite xe_bo_shrink_test_suite;
 extern struct kunit_suite xe_dma_buf_test_suite;
 extern struct kunit_suite xe_migrate_test_suite;
 extern struct kunit_suite xe_mocs_test_suite;
+extern struct kunit_suite xe_guc_g2g_test_suite;
 
 kunit_test_suite(xe_bo_test_suite);
 kunit_test_suite(xe_bo_shrink_test_suite);
 kunit_test_suite(xe_dma_buf_test_suite);
 kunit_test_suite(xe_migrate_test_suite);
 kunit_test_suite(xe_mocs_test_suite);
+kunit_test_suite(xe_guc_g2g_test_suite);
 
 MODULE_AUTHOR("Intel Corporation");
 MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 38c8329b4d2c..0416b0eba3bf 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -576,6 +576,13 @@ struct xe_device {
 	atomic64_t global_total_pages;
 #endif
 
+#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
+	/** @g2g_test_array: for testing G2G communications */
+	u32 *g2g_test_array;
+	/** @g2g_test_count: for testing G2G communications */
+	atomic_t g2g_test_count;
+#endif
+
 	/* private: */
 
 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index c49feb8ea0c3..aa2e9f761f8f 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -1688,3 +1688,7 @@ void xe_guc_declare_wedged(struct xe_guc *guc)
 	xe_guc_ct_stop(&guc->ct);
 	xe_guc_submit_wedge(guc);
 }
+
+#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
+#include "tests/xe_guc_g2g_test.c"
+#endif
diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h
index 22cf019a11bf..1cca05967e62 100644
--- a/drivers/gpu/drm/xe/xe_guc.h
+++ b/drivers/gpu/drm/xe/xe_guc.h
@@ -53,6 +53,10 @@ void xe_guc_stop(struct xe_guc *guc);
 int xe_guc_start(struct xe_guc *guc);
 void xe_guc_declare_wedged(struct xe_guc *guc);
 
+#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
+int xe_guc_g2g_test_notification(struct xe_guc *guc, u32 *payload, u32 len);
+#endif
+
 static inline u16 xe_engine_class_to_guc_class(enum xe_engine_class class)
 {
 	switch (class) {
diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index 3f4e6a46ff16..f44967f84d30 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -1439,6 +1439,11 @@ static int process_g2h_msg(struct xe_guc_ct *ct, u32 *msg, u32 len)
 	case XE_GUC_ACTION_NOTIFY_EXCEPTION:
 		ret = guc_crash_process_msg(ct, action);
 		break;
+#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
+	case XE_GUC_ACTION_TEST_G2G_RECV:
+		ret = xe_guc_g2g_test_notification(guc, payload, adj_len);
+		break;
+#endif
 	default:
 		xe_gt_err(gt, "unexpected G2H action 0x%04x\n", action);
 	}
diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
index ca9f999d38d1..bc94f8d0f037 100644
--- a/drivers/gpu/drm/xe/xe_guc_fwif.h
+++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
@@ -15,6 +15,7 @@
 #define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET	4
 #define G2H_LEN_DW_DEREGISTER_CONTEXT		3
 #define G2H_LEN_DW_TLB_INVALIDATE		3
+#define G2H_LEN_DW_G2G_NOTIFY_MIN		3
 
 #define GUC_ID_MAX			65535
 #define GUC_ID_UNKNOWN			0xffffffff
-- 
2.49.0

✗ CI.checkpatch: warning for Add test for G2G communications (rev2)

[Patchwork]

== Series Details ==

Series: Add test for G2G communications (rev2)
URL   : https://patchwork.freedesktop.org/series/152101/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
c298eac5978c38dcc62a70c0d73c91765e7cc296
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 14f765983dcdffe55fe11f9a37893552e4106ae4
Author: John Harrison <John.C.Harrison@Intel.com>
Date:   Tue Aug 5 16:42:55 2025 -0700

    drm/xe/guc: Add test for G2G communications
    
    Add a test for sending messages from every GuC to every other GuC to
    test G2G communications.
    
    Note that, being a debug only feature, the test interface only exists
    in pre-production builds of the GuC firmware.
    
    v2: Fix 'default' case to actually use the driver's registration code
    as well as allocation. Add comments explaining the different test
    types. Fix (C) date and an assert. Review feedback from Daniele.
    
    Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
+ /mt/dim checkpatch b61343d3704885afd253795a1e1084febbf7f354 drm-intel
682dfdf09b8a drm/xe/guc: Update CSS header structures
fa7eeb694e3a drm/xe/guc: Add firmware build type to available info
735e9b03785f drm/xe: Allow freeing of a managed bo
14f765983dcd drm/xe/guc: Add test for G2G communications
-:32: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#32: 
new file mode 100644

-:821: WARNING:AVOID_EXTERNS: externs should be avoided in .c files
#821: FILE: drivers/gpu/drm/xe/tests/xe_live_test_mod.c:13:
+extern struct kunit_suite xe_guc_g2g_test_suite;

total: 0 errors, 2 warnings, 0 checks, 846 lines checked

✓ CI.KUnit: success for Add test for G2G communications (rev2)

[Patchwork]

== Series Details ==

Series: Add test for G2G communications (rev2)
URL   : https://patchwork.freedesktop.org/series/152101/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[00:58:14] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[00:58:18] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[00:58:46] Starting KUnit Kernel (1/1)...
[00:58:46] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[00:58:46] ================== guc_buf (11 subtests) ===================
[00:58:46] [PASSED] test_smallest
[00:58:46] [PASSED] test_largest
[00:58:46] [PASSED] test_granular
[00:58:46] [PASSED] test_unique
[00:58:46] [PASSED] test_overlap
[00:58:46] [PASSED] test_reusable
[00:58:46] [PASSED] test_too_big
[00:58:46] [PASSED] test_flush
[00:58:46] [PASSED] test_lookup
[00:58:46] [PASSED] test_data
[00:58:46] [PASSED] test_class
[00:58:46] ===================== [PASSED] guc_buf =====================
[00:58:46] =================== guc_dbm (7 subtests) ===================
[00:58:46] [PASSED] test_empty
[00:58:46] [PASSED] test_default
[00:58:46] ======================== test_size  ========================
[00:58:46] [PASSED] 4
[00:58:46] [PASSED] 8
[00:58:46] [PASSED] 32
[00:58:46] [PASSED] 256
[00:58:46] ==================== [PASSED] test_size ====================
[00:58:46] ======================= test_reuse  ========================
[00:58:46] [PASSED] 4
[00:58:46] [PASSED] 8
[00:58:46] [PASSED] 32
[00:58:46] [PASSED] 256
[00:58:46] =================== [PASSED] test_reuse ====================
[00:58:46] =================== test_range_overlap  ====================
[00:58:46] [PASSED] 4
[00:58:46] [PASSED] 8
[00:58:46] [PASSED] 32
[00:58:46] [PASSED] 256
[00:58:46] =============== [PASSED] test_range_overlap ================
[00:58:46] =================== test_range_compact  ====================
[00:58:46] [PASSED] 4
[00:58:46] [PASSED] 8
[00:58:46] [PASSED] 32
[00:58:46] [PASSED] 256
[00:58:46] =============== [PASSED] test_range_compact ================
[00:58:46] ==================== test_range_spare  =====================
[00:58:46] [PASSED] 4
[00:58:46] [PASSED] 8
[00:58:46] [PASSED] 32
[00:58:46] [PASSED] 256
[00:58:46] ================ [PASSED] test_range_spare =================
[00:58:46] ===================== [PASSED] guc_dbm =====================
[00:58:46] =================== guc_idm (6 subtests) ===================
[00:58:46] [PASSED] bad_init
[00:58:46] [PASSED] no_init
[00:58:46] [PASSED] init_fini
[00:58:46] [PASSED] check_used
[00:58:46] [PASSED] check_quota
[00:58:46] [PASSED] check_all
[00:58:46] ===================== [PASSED] guc_idm =====================
[00:58:46] ================== no_relay (3 subtests) ===================
[00:58:46] [PASSED] xe_drops_guc2pf_if_not_ready
[00:58:46] [PASSED] xe_drops_guc2vf_if_not_ready
[00:58:46] [PASSED] xe_rejects_send_if_not_ready
[00:58:46] ==================== [PASSED] no_relay =====================
[00:58:46] ================== pf_relay (14 subtests) ==================
[00:58:46] [PASSED] pf_rejects_guc2pf_too_short
[00:58:46] [PASSED] pf_rejects_guc2pf_too_long
[00:58:46] [PASSED] pf_rejects_guc2pf_no_payload
[00:58:46] [PASSED] pf_fails_no_payload
[00:58:46] [PASSED] pf_fails_bad_origin
[00:58:46] [PASSED] pf_fails_bad_type
[00:58:46] [PASSED] pf_txn_reports_error
[00:58:46] [PASSED] pf_txn_sends_pf2guc
[00:58:46] [PASSED] pf_sends_pf2guc
[00:58:46] [SKIPPED] pf_loopback_nop
[00:58:46] [SKIPPED] pf_loopback_echo
[00:58:46] [SKIPPED] pf_loopback_fail
[00:58:46] [SKIPPED] pf_loopback_busy
[00:58:46] [SKIPPED] pf_loopback_retry
[00:58:46] ==================== [PASSED] pf_relay =====================
[00:58:46] ================== vf_relay (3 subtests) ===================
[00:58:46] [PASSED] vf_rejects_guc2vf_too_short
[00:58:46] [PASSED] vf_rejects_guc2vf_too_long
[00:58:46] [PASSED] vf_rejects_guc2vf_no_payload
[00:58:46] ==================== [PASSED] vf_relay =====================
[00:58:46] ===================== lmtt (1 subtest) =====================
[00:58:46] ======================== test_ops  =========================
[00:58:46] [PASSED] 2-level
[00:58:46] [PASSED] multi-level
[00:58:46] ==================== [PASSED] test_ops =====================
[00:58:46] ====================== [PASSED] lmtt =======================
[00:58:46] ================= pf_service (11 subtests) =================
[00:58:46] [PASSED] pf_negotiate_any
[00:58:46] [PASSED] pf_negotiate_base_match
[00:58:46] [PASSED] pf_negotiate_base_newer
[00:58:46] [PASSED] pf_negotiate_base_next
[00:58:46] [SKIPPED] pf_negotiate_base_older
[00:58:46] [PASSED] pf_negotiate_base_prev
[00:58:46] [PASSED] pf_negotiate_latest_match
[00:58:46] [PASSED] pf_negotiate_latest_newer
[00:58:46] [PASSED] pf_negotiate_latest_next
[00:58:46] [SKIPPED] pf_negotiate_latest_older
[00:58:46] [SKIPPED] pf_negotiate_latest_prev
[00:58:46] =================== [PASSED] pf_service ====================
[00:58:46] ================= xe_guc_g2g (2 subtests) ==================
[00:58:46] ============== xe_live_guc_g2g_kunit_default  ==============
[00:58:46] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[00:58:46] ============== xe_live_guc_g2g_kunit_allmem  ===============
[00:58:46] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[00:58:46] =================== [SKIPPED] xe_guc_g2g ===================
[00:58:46] =================== xe_mocs (2 subtests) ===================
[00:58:46] ================ xe_live_mocs_kernel_kunit  ================
[00:58:46] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[00:58:46] ================ xe_live_mocs_reset_kunit  =================
[00:58:46] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[00:58:46] ==================== [SKIPPED] xe_mocs =====================
[00:58:46] ================= xe_migrate (2 subtests) ==================
[00:58:46] ================= xe_migrate_sanity_kunit  =================
[00:58:46] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[00:58:46] ================== xe_validate_ccs_kunit  ==================
[00:58:46] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[00:58:46] =================== [SKIPPED] xe_migrate ===================
[00:58:46] ================== xe_dma_buf (1 subtest) ==================
[00:58:46] ==================== xe_dma_buf_kunit  =====================
[00:58:46] ================ [SKIPPED] xe_dma_buf_kunit ================
[00:58:46] =================== [SKIPPED] xe_dma_buf ===================
[00:58:46] ================= xe_bo_shrink (1 subtest) =================
[00:58:46] =================== xe_bo_shrink_kunit  ====================
[00:58:46] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[00:58:46] ================== [SKIPPED] xe_bo_shrink ==================
[00:58:46] ==================== xe_bo (2 subtests) ====================
[00:58:46] ================== xe_ccs_migrate_kunit  ===================
[00:58:46] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[00:58:46] ==================== xe_bo_evict_kunit  ====================
[00:58:46] =============== [SKIPPED] xe_bo_evict_kunit ================
[00:58:46] ===================== [SKIPPED] xe_bo ======================
[00:58:46] ==================== args (11 subtests) ====================
[00:58:46] [PASSED] count_args_test
[00:58:46] [PASSED] call_args_example
[00:58:46] [PASSED] call_args_test
[00:58:46] [PASSED] drop_first_arg_example
[00:58:46] [PASSED] drop_first_arg_test
[00:58:46] [PASSED] first_arg_example
[00:58:46] [PASSED] first_arg_test
[00:58:46] [PASSED] last_arg_example
[00:58:46] [PASSED] last_arg_test
[00:58:46] [PASSED] pick_arg_example
[00:58:46] [PASSED] sep_comma_example
[00:58:46] ====================== [PASSED] args =======================
[00:58:46] =================== xe_pci (3 subtests) ====================
[00:58:46] ==================== check_graphics_ip  ====================
[00:58:46] [PASSED] 12.70 Xe_LPG
[00:58:46] [PASSED] 12.71 Xe_LPG
[00:58:46] [PASSED] 12.74 Xe_LPG+
[00:58:46] [PASSED] 20.01 Xe2_HPG
[00:58:46] [PASSED] 20.02 Xe2_HPG
[00:58:46] [PASSED] 20.04 Xe2_LPG
[00:58:46] [PASSED] 30.00 Xe3_LPG
[00:58:46] [PASSED] 30.01 Xe3_LPG
[00:58:46] [PASSED] 30.03 Xe3_LPG
[00:58:46] ================ [PASSED] check_graphics_ip ================
[00:58:46] ===================== check_media_ip  ======================
[00:58:46] [PASSED] 13.00 Xe_LPM+
[00:58:46] [PASSED] 13.01 Xe2_HPM
[00:58:46] [PASSED] 20.00 Xe2_LPM
[00:58:46] [PASSED] 30.00 Xe3_LPM
[00:58:46] [PASSED] 30.02 Xe3_LPM
[00:58:46] ================= [PASSED] check_media_ip ==================
[00:58:46] ================= check_platform_gt_count  =================
[00:58:46] [PASSED] 0x9A60 (TIGERLAKE)
[00:58:46] [PASSED] 0x9A68 (TIGERLAKE)
[00:58:46] [PASSED] 0x9A70 (TIGERLAKE)
[00:58:46] [PASSED] 0x9A40 (TIGERLAKE)
[00:58:46] [PASSED] 0x9A49 (TIGERLAKE)
[00:58:46] [PASSED] 0x9A59 (TIGERLAKE)
[00:58:46] [PASSED] 0x9A78 (TIGERLAKE)
[00:58:46] [PASSED] 0x9AC0 (TIGERLAKE)
[00:58:46] [PASSED] 0x9AC9 (TIGERLAKE)
[00:58:46] [PASSED] 0x9AD9 (TIGERLAKE)
[00:58:46] [PASSED] 0x9AF8 (TIGERLAKE)
[00:58:46] [PASSED] 0x4C80 (ROCKETLAKE)
[00:58:46] [PASSED] 0x4C8A (ROCKETLAKE)
[00:58:46] [PASSED] 0x4C8B (ROCKETLAKE)
[00:58:46] [PASSED] 0x4C8C (ROCKETLAKE)
[00:58:46] [PASSED] 0x4C90 (ROCKETLAKE)
[00:58:46] [PASSED] 0x4C9A (ROCKETLAKE)
[00:58:46] [PASSED] 0x4680 (ALDERLAKE_S)
[00:58:46] [PASSED] 0x4682 (ALDERLAKE_S)
[00:58:46] [PASSED] 0x4688 (ALDERLAKE_S)
[00:58:46] [PASSED] 0x468A (ALDERLAKE_S)
[00:58:46] [PASSED] 0x468B (ALDERLAKE_S)
[00:58:46] [PASSED] 0x4690 (ALDERLAKE_S)
[00:58:46] [PASSED] 0x4692 (ALDERLAKE_S)
[00:58:46] [PASSED] 0x4693 (ALDERLAKE_S)
[00:58:46] [PASSED] 0x46A0 (ALDERLAKE_P)
[00:58:46] [PASSED] 0x46A1 (ALDERLAKE_P)
[00:58:46] [PASSED] 0x46A2 (ALDERLAKE_P)
[00:58:46] [PASSED] 0x46A3 (ALDERLAKE_P)
[00:58:46] [PASSED] 0x46A6 (ALDERLAKE_P)
[00:58:46] [PASSED] 0x46A8 (ALDERLAKE_P)
[00:58:46] [PASSED] 0x46AA (ALDERLAKE_P)
[00:58:46] [PASSED] 0x462A (ALDERLAKE_P)
[00:58:46] [PASSED] 0x4626 (ALDERLAKE_P)
[00:58:46] [PASSED] 0x4628 (ALDERLAKE_P)
[00:58:46] [PASSED] 0x46B0 (ALDERLAKE_P)
[00:58:46] [PASSED] 0x46B1 (ALDERLAKE_P)
[00:58:46] [PASSED] 0x46B2 (ALDERLAKE_P)
[00:58:46] [PASSED] 0x46B3 (ALDERLAKE_P)
[00:58:46] [PASSED] 0x46C0 (ALDERLAKE_P)
[00:58:46] [PASSED] 0x46C1 (ALDERLAKE_P)
[00:58:46] [PASSED] 0x46C2 (ALDERLAKE_P)
[00:58:46] [PASSED] 0x46C3 (ALDERLAKE_P)
[00:58:46] [PASSED] 0x46D0 (ALDERLAKE_N)
[00:58:46] [PASSED] 0x46D1 (ALDERLAKE_N)
[00:58:46] [PASSED] 0x46D2 (ALDERLAKE_N)
[00:58:46] [PASSED] 0x46D3 (ALDERLAKE_N)
[00:58:46] [PASSED] 0x46D4 (ALDERLAKE_N)
[00:58:46] [PASSED] 0xA721 (ALDERLAKE_P)
[00:58:46] [PASSED] 0xA7A1 (ALDERLAKE_P)
[00:58:46] [PASSED] 0xA7A9 (ALDERLAKE_P)
[00:58:46] [PASSED] 0xA7AC (ALDERLAKE_P)
[00:58:46] [PASSED] 0xA7AD (ALDERLAKE_P)
[00:58:46] [PASSED] 0xA720 (ALDERLAKE_P)
[00:58:46] [PASSED] 0xA7A0 (ALDERLAKE_P)
[00:58:46] [PASSED] 0xA7A8 (ALDERLAKE_P)
[00:58:46] [PASSED] 0xA7AA (ALDERLAKE_P)
[00:58:46] [PASSED] 0xA7AB (ALDERLAKE_P)
[00:58:46] [PASSED] 0xA780 (ALDERLAKE_S)
[00:58:46] [PASSED] 0xA781 (ALDERLAKE_S)
[00:58:46] [PASSED] 0xA782 (ALDERLAKE_S)
[00:58:46] [PASSED] 0xA783 (ALDERLAKE_S)
[00:58:46] [PASSED] 0xA788 (ALDERLAKE_S)
[00:58:46] [PASSED] 0xA789 (ALDERLAKE_S)
[00:58:46] [PASSED] 0xA78A (ALDERLAKE_S)
[00:58:46] [PASSED] 0xA78B (ALDERLAKE_S)
[00:58:46] [PASSED] 0x4905 (DG1)
[00:58:46] [PASSED] 0x4906 (DG1)
[00:58:46] [PASSED] 0x4907 (DG1)
[00:58:46] [PASSED] 0x4908 (DG1)
[00:58:46] [PASSED] 0x4909 (DG1)
[00:58:46] [PASSED] 0x56C0 (DG2)
[00:58:46] [PASSED] 0x56C2 (DG2)
[00:58:46] [PASSED] 0x56C1 (DG2)
[00:58:46] [PASSED] 0x7D51 (METEORLAKE)
[00:58:46] [PASSED] 0x7DD1 (METEORLAKE)
[00:58:46] [PASSED] 0x7D41 (METEORLAKE)
[00:58:46] [PASSED] 0x7D67 (METEORLAKE)
[00:58:46] [PASSED] 0xB640 (METEORLAKE)
[00:58:46] [PASSED] 0x56A0 (DG2)
[00:58:46] [PASSED] 0x56A1 (DG2)
[00:58:46] [PASSED] 0x56A2 (DG2)
[00:58:46] [PASSED] 0x56BE (DG2)
[00:58:46] [PASSED] 0x56BF (DG2)
[00:58:46] [PASSED] 0x5690 (DG2)
[00:58:46] [PASSED] 0x5691 (DG2)
[00:58:46] [PASSED] 0x5692 (DG2)
[00:58:46] [PASSED] 0x56A5 (DG2)
[00:58:46] [PASSED] 0x56A6 (DG2)
[00:58:46] [PASSED] 0x56B0 (DG2)
[00:58:46] [PASSED] 0x56B1 (DG2)
[00:58:46] [PASSED] 0x56BA (DG2)
[00:58:46] [PASSED] 0x56BB (DG2)
[00:58:46] [PASSED] 0x56BC (DG2)
[00:58:46] [PASSED] 0x56BD (DG2)
[00:58:46] [PASSED] 0x5693 (DG2)
[00:58:46] [PASSED] 0x5694 (DG2)
[00:58:46] [PASSED] 0x5695 (DG2)
[00:58:46] [PASSED] 0x56A3 (DG2)
[00:58:46] [PASSED] 0x56A4 (DG2)
[00:58:46] [PASSED] 0x56B2 (DG2)
[00:58:46] [PASSED] 0x56B3 (DG2)
[00:58:46] [PASSED] 0x5696 (DG2)
[00:58:46] [PASSED] 0x5697 (DG2)
[00:58:46] [PASSED] 0xB69 (PVC)
[00:58:46] [PASSED] 0xB6E (PVC)
[00:58:46] [PASSED] 0xBD4 (PVC)
[00:58:46] [PASSED] 0xBD5 (PVC)
[00:58:46] [PASSED] 0xBD6 (PVC)
[00:58:46] [PASSED] 0xBD7 (PVC)
[00:58:46] [PASSED] 0xBD8 (PVC)
[00:58:46] [PASSED] 0xBD9 (PVC)
[00:58:46] [PASSED] 0xBDA (PVC)
[00:58:46] [PASSED] 0xBDB (PVC)
[00:58:46] [PASSED] 0xBE0 (PVC)
[00:58:46] [PASSED] 0xBE1 (PVC)
[00:58:46] [PASSED] 0xBE5 (PVC)
[00:58:46] [PASSED] 0x7D40 (METEORLAKE)
[00:58:46] [PASSED] 0x7D45 (METEORLAKE)
[00:58:46] [PASSED] 0x7D55 (METEORLAKE)
[00:58:46] [PASSED] 0x7D60 (METEORLAKE)
[00:58:46] [PASSED] 0x7DD5 (METEORLAKE)
[00:58:46] [PASSED] 0x6420 (LUNARLAKE)
[00:58:46] [PASSED] 0x64A0 (LUNARLAKE)
[00:58:46] [PASSED] 0x64B0 (LUNARLAKE)
[00:58:46] [PASSED] 0xE202 (BATTLEMAGE)
[00:58:46] [PASSED] 0xE209 (BATTLEMAGE)
[00:58:46] [PASSED] 0xE20B (BATTLEMAGE)
[00:58:46] [PASSED] 0xE20C (BATTLEMAGE)
[00:58:46] [PASSED] 0xE20D (BATTLEMAGE)
[00:58:46] [PASSED] 0xE210 (BATTLEMAGE)
[00:58:46] [PASSED] 0xE211 (BATTLEMAGE)
[00:58:46] [PASSED] 0xE212 (BATTLEMAGE)
[00:58:46] [PASSED] 0xE216 (BATTLEMAGE)
[00:58:46] [PASSED] 0xE220 (BATTLEMAGE)
[00:58:46] [PASSED] 0xE221 (BATTLEMAGE)
[00:58:46] [PASSED] 0xE222 (BATTLEMAGE)
[00:58:46] [PASSED] 0xE223 (BATTLEMAGE)
[00:58:46] [PASSED] 0xB080 (PANTHERLAKE)
[00:58:46] [PASSED] 0xB081 (PANTHERLAKE)
[00:58:46] [PASSED] 0xB082 (PANTHERLAKE)
[00:58:46] [PASSED] 0xB083 (PANTHERLAKE)
[00:58:46] [PASSED] 0xB084 (PANTHERLAKE)
[00:58:46] [PASSED] 0xB085 (PANTHERLAKE)
[00:58:46] [PASSED] 0xB086 (PANTHERLAKE)
[00:58:46] [PASSED] 0xB087 (PANTHERLAKE)
[00:58:46] [PASSED] 0xB08F (PANTHERLAKE)
[00:58:46] [PASSED] 0xB090 (PANTHERLAKE)
[00:58:46] [PASSED] 0xB0A0 (PANTHERLAKE)
[00:58:46] [PASSED] 0xB0B0 (PANTHERLAKE)
[00:58:46] [PASSED] 0xFD80 (PANTHERLAKE)
[00:58:46] [PASSED] 0xFD81 (PANTHERLAKE)
[00:58:46] ============= [PASSED] check_platform_gt_count =============
[00:58:46] ===================== [PASSED] xe_pci ======================
[00:58:46] =================== xe_rtp (2 subtests) ====================
[00:58:46] =============== xe_rtp_process_to_sr_tests  ================
[00:58:46] [PASSED] coalesce-same-reg
[00:58:46] [PASSED] no-match-no-add
[00:58:46] [PASSED] match-or
[00:58:46] [PASSED] match-or-xfail
[00:58:46] [PASSED] no-match-no-add-multiple-rules
[00:58:46] [PASSED] two-regs-two-entries
[00:58:46] [PASSED] clr-one-set-other
[00:58:46] [PASSED] set-field
[00:58:46] [PASSED] conflict-duplicate
[00:58:46] [PASSED] conflict-not-disjoint
[00:58:46] [PASSED] conflict-reg-type
[00:58:46] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[00:58:46] ================== xe_rtp_process_tests  ===================
[00:58:46] [PASSED] active1
[00:58:46] [PASSED] active2
[00:58:46] [PASSED] active-inactive
[00:58:46] [PASSED] inactive-active
[00:58:46] [PASSED] inactive-1st_or_active-inactive
[00:58:46] [PASSED] inactive-2nd_or_active-inactive
[00:58:46] [PASSED] inactive-last_or_active-inactive
[00:58:46] [PASSED] inactive-no_or_active-inactive
[00:58:46] ============== [PASSED] xe_rtp_process_tests ===============
[00:58:46] ===================== [PASSED] xe_rtp ======================
[00:58:46] ==================== xe_wa (1 subtest) =====================
[00:58:46] ======================== xe_wa_gt  =========================
[00:58:46] [PASSED] TIGERLAKE (B0)
[00:58:46] [PASSED] DG1 (A0)
[00:58:46] [PASSED] DG1 (B0)
[00:58:46] [PASSED] ALDERLAKE_S (A0)
[00:58:46] [PASSED] ALDERLAKE_S (B0)
[00:58:46] [PASSED] ALDERLAKE_S (C0)
[00:58:46] [PASSED] ALDERLAKE_S (D0)
[00:58:46] [PASSED] ALDERLAKE_P (A0)
[00:58:46] [PASSED] ALDERLAKE_P (B0)
stty: 'standard input': Inappropriate ioctl for device
[00:58:46] [PASSED] ALDERLAKE_P (C0)
[00:58:46] [PASSED] ALDERLAKE_S_RPLS (D0)
[00:58:46] [PASSED] ALDERLAKE_P_RPLU (E0)
[00:58:46] [PASSED] DG2_G10 (C0)
[00:58:46] [PASSED] DG2_G11 (B1)
[00:58:46] [PASSED] DG2_G12 (A1)
[00:58:46] [PASSED] METEORLAKE (g:A0, m:A0)
[00:58:46] [PASSED] METEORLAKE (g:A0, m:A0)
[00:58:46] [PASSED] METEORLAKE (g:A0, m:A0)
[00:58:46] [PASSED] LUNARLAKE (g:A0, m:A0)
[00:58:46] [PASSED] LUNARLAKE (g:B0, m:A0)
[00:58:46] [PASSED] BATTLEMAGE (g:A0, m:A1)
[00:58:46] ==================== [PASSED] xe_wa_gt =====================
[00:58:46] ====================== [PASSED] xe_wa ======================
[00:58:46] ============================================================
[00:58:46] Testing complete. Ran 299 tests: passed: 281, skipped: 18
[00:58:46] Elapsed time: 32.096s total, 4.176s configuring, 27.553s building, 0.319s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[00:58:46] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[00:58:48] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[00:59:10] Starting KUnit Kernel (1/1)...
[00:59:10] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[00:59:10] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[00:59:10] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[00:59:10] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[00:59:10] =========== drm_validate_clone_mode (2 subtests) ===========
[00:59:10] ============== drm_test_check_in_clone_mode  ===============
[00:59:10] [PASSED] in_clone_mode
[00:59:10] [PASSED] not_in_clone_mode
[00:59:10] ========== [PASSED] drm_test_check_in_clone_mode ===========
[00:59:10] =============== drm_test_check_valid_clones  ===============
[00:59:10] [PASSED] not_in_clone_mode
[00:59:10] [PASSED] valid_clone
[00:59:10] [PASSED] invalid_clone
[00:59:10] =========== [PASSED] drm_test_check_valid_clones ===========
[00:59:10] ============= [PASSED] drm_validate_clone_mode =============
[00:59:10] ============= drm_validate_modeset (1 subtest) =============
[00:59:10] [PASSED] drm_test_check_connector_changed_modeset
[00:59:10] ============== [PASSED] drm_validate_modeset ===============
[00:59:10] ====== drm_test_bridge_get_current_state (2 subtests) ======
[00:59:10] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[00:59:10] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[00:59:10] ======== [PASSED] drm_test_bridge_get_current_state ========
[00:59:10] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[00:59:10] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[00:59:10] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[00:59:10] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[00:59:10] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[00:59:10] ============== drm_bridge_alloc (2 subtests) ===============
[00:59:10] [PASSED] drm_test_drm_bridge_alloc_basic
[00:59:10] [PASSED] drm_test_drm_bridge_alloc_get_put
[00:59:10] ================ [PASSED] drm_bridge_alloc =================
[00:59:10] ================== drm_buddy (7 subtests) ==================
[00:59:10] [PASSED] drm_test_buddy_alloc_limit
[00:59:10] [PASSED] drm_test_buddy_alloc_optimistic
[00:59:10] [PASSED] drm_test_buddy_alloc_pessimistic
[00:59:10] [PASSED] drm_test_buddy_alloc_pathological
[00:59:10] [PASSED] drm_test_buddy_alloc_contiguous
[00:59:10] [PASSED] drm_test_buddy_alloc_clear
[00:59:10] [PASSED] drm_test_buddy_alloc_range_bias
[00:59:10] ==================== [PASSED] drm_buddy ====================
[00:59:10] ============= drm_cmdline_parser (40 subtests) =============
[00:59:10] [PASSED] drm_test_cmdline_force_d_only
[00:59:10] [PASSED] drm_test_cmdline_force_D_only_dvi
[00:59:10] [PASSED] drm_test_cmdline_force_D_only_hdmi
[00:59:10] [PASSED] drm_test_cmdline_force_D_only_not_digital
[00:59:10] [PASSED] drm_test_cmdline_force_e_only
[00:59:10] [PASSED] drm_test_cmdline_res
[00:59:10] [PASSED] drm_test_cmdline_res_vesa
[00:59:10] [PASSED] drm_test_cmdline_res_vesa_rblank
[00:59:10] [PASSED] drm_test_cmdline_res_rblank
[00:59:10] [PASSED] drm_test_cmdline_res_bpp
[00:59:10] [PASSED] drm_test_cmdline_res_refresh
[00:59:10] [PASSED] drm_test_cmdline_res_bpp_refresh
[00:59:10] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[00:59:10] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[00:59:10] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[00:59:10] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[00:59:10] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[00:59:10] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[00:59:10] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[00:59:10] [PASSED] drm_test_cmdline_res_margins_force_on
[00:59:10] [PASSED] drm_test_cmdline_res_vesa_margins
[00:59:10] [PASSED] drm_test_cmdline_name
[00:59:10] [PASSED] drm_test_cmdline_name_bpp
[00:59:10] [PASSED] drm_test_cmdline_name_option
[00:59:10] [PASSED] drm_test_cmdline_name_bpp_option
[00:59:10] [PASSED] drm_test_cmdline_rotate_0
[00:59:10] [PASSED] drm_test_cmdline_rotate_90
[00:59:10] [PASSED] drm_test_cmdline_rotate_180
[00:59:10] [PASSED] drm_test_cmdline_rotate_270
[00:59:10] [PASSED] drm_test_cmdline_hmirror
[00:59:10] [PASSED] drm_test_cmdline_vmirror
[00:59:10] [PASSED] drm_test_cmdline_margin_options
[00:59:10] [PASSED] drm_test_cmdline_multiple_options
[00:59:10] [PASSED] drm_test_cmdline_bpp_extra_and_option
[00:59:10] [PASSED] drm_test_cmdline_extra_and_option
[00:59:10] [PASSED] drm_test_cmdline_freestanding_options
[00:59:10] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[00:59:10] [PASSED] drm_test_cmdline_panel_orientation
[00:59:10] ================ drm_test_cmdline_invalid  =================
[00:59:10] [PASSED] margin_only
[00:59:10] [PASSED] interlace_only
[00:59:10] [PASSED] res_missing_x
[00:59:10] [PASSED] res_missing_y
[00:59:10] [PASSED] res_bad_y
[00:59:10] [PASSED] res_missing_y_bpp
[00:59:10] [PASSED] res_bad_bpp
[00:59:10] [PASSED] res_bad_refresh
[00:59:10] [PASSED] res_bpp_refresh_force_on_off
[00:59:10] [PASSED] res_invalid_mode
[00:59:10] [PASSED] res_bpp_wrong_place_mode
[00:59:10] [PASSED] name_bpp_refresh
[00:59:10] [PASSED] name_refresh
[00:59:10] [PASSED] name_refresh_wrong_mode
[00:59:10] [PASSED] name_refresh_invalid_mode
[00:59:10] [PASSED] rotate_multiple
[00:59:10] [PASSED] rotate_invalid_val
[00:59:10] [PASSED] rotate_truncated
[00:59:10] [PASSED] invalid_option
[00:59:10] [PASSED] invalid_tv_option
[00:59:10] [PASSED] truncated_tv_option
[00:59:10] ============ [PASSED] drm_test_cmdline_invalid =============
[00:59:10] =============== drm_test_cmdline_tv_options  ===============
[00:59:10] [PASSED] NTSC
[00:59:10] [PASSED] NTSC_443
[00:59:10] [PASSED] NTSC_J
[00:59:10] [PASSED] PAL
[00:59:10] [PASSED] PAL_M
[00:59:10] [PASSED] PAL_N
[00:59:10] [PASSED] SECAM
[00:59:10] [PASSED] MONO_525
[00:59:10] [PASSED] MONO_625
[00:59:10] =========== [PASSED] drm_test_cmdline_tv_options ===========
[00:59:10] =============== [PASSED] drm_cmdline_parser ================
[00:59:10] ========== drmm_connector_hdmi_init (20 subtests) ==========
[00:59:10] [PASSED] drm_test_connector_hdmi_init_valid
[00:59:10] [PASSED] drm_test_connector_hdmi_init_bpc_8
[00:59:10] [PASSED] drm_test_connector_hdmi_init_bpc_10
[00:59:10] [PASSED] drm_test_connector_hdmi_init_bpc_12
[00:59:10] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[00:59:10] [PASSED] drm_test_connector_hdmi_init_bpc_null
[00:59:10] [PASSED] drm_test_connector_hdmi_init_formats_empty
[00:59:10] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[00:59:10] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[00:59:10] [PASSED] supported_formats=0x9 yuv420_allowed=1
[00:59:10] [PASSED] supported_formats=0x9 yuv420_allowed=0
[00:59:10] [PASSED] supported_formats=0x3 yuv420_allowed=1
[00:59:10] [PASSED] supported_formats=0x3 yuv420_allowed=0
[00:59:10] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[00:59:10] [PASSED] drm_test_connector_hdmi_init_null_ddc
[00:59:10] [PASSED] drm_test_connector_hdmi_init_null_product
[00:59:10] [PASSED] drm_test_connector_hdmi_init_null_vendor
[00:59:10] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[00:59:10] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[00:59:10] [PASSED] drm_test_connector_hdmi_init_product_valid
[00:59:10] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[00:59:10] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[00:59:10] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[00:59:10] ========= drm_test_connector_hdmi_init_type_valid  =========
[00:59:10] [PASSED] HDMI-A
[00:59:10] [PASSED] HDMI-B
[00:59:10] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[00:59:10] ======== drm_test_connector_hdmi_init_type_invalid  ========
[00:59:10] [PASSED] Unknown
[00:59:10] [PASSED] VGA
[00:59:10] [PASSED] DVI-I
[00:59:10] [PASSED] DVI-D
[00:59:10] [PASSED] DVI-A
[00:59:10] [PASSED] Composite
[00:59:10] [PASSED] SVIDEO
[00:59:10] [PASSED] LVDS
[00:59:10] [PASSED] Component
[00:59:10] [PASSED] DIN
[00:59:10] [PASSED] DP
[00:59:10] [PASSED] TV
[00:59:10] [PASSED] eDP
[00:59:10] [PASSED] Virtual
[00:59:10] [PASSED] DSI
[00:59:10] [PASSED] DPI
[00:59:10] [PASSED] Writeback
[00:59:10] [PASSED] SPI
[00:59:10] [PASSED] USB
[00:59:10] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[00:59:10] ============ [PASSED] drmm_connector_hdmi_init =============
[00:59:10] ============= drmm_connector_init (3 subtests) =============
[00:59:10] [PASSED] drm_test_drmm_connector_init
[00:59:10] [PASSED] drm_test_drmm_connector_init_null_ddc
[00:59:10] ========= drm_test_drmm_connector_init_type_valid  =========
[00:59:10] [PASSED] Unknown
[00:59:10] [PASSED] VGA
[00:59:10] [PASSED] DVI-I
[00:59:10] [PASSED] DVI-D
[00:59:10] [PASSED] DVI-A
[00:59:10] [PASSED] Composite
[00:59:10] [PASSED] SVIDEO
[00:59:10] [PASSED] LVDS
[00:59:10] [PASSED] Component
[00:59:10] [PASSED] DIN
[00:59:10] [PASSED] DP
[00:59:10] [PASSED] HDMI-A
[00:59:10] [PASSED] HDMI-B
[00:59:10] [PASSED] TV
[00:59:10] [PASSED] eDP
[00:59:10] [PASSED] Virtual
[00:59:10] [PASSED] DSI
[00:59:10] [PASSED] DPI
[00:59:10] [PASSED] Writeback
[00:59:10] [PASSED] SPI
[00:59:10] [PASSED] USB
[00:59:10] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[00:59:10] =============== [PASSED] drmm_connector_init ===============
[00:59:10] ========= drm_connector_dynamic_init (6 subtests) ==========
[00:59:10] [PASSED] drm_test_drm_connector_dynamic_init
[00:59:10] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[00:59:10] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[00:59:10] [PASSED] drm_test_drm_connector_dynamic_init_properties
[00:59:10] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[00:59:10] [PASSED] Unknown
[00:59:10] [PASSED] VGA
[00:59:10] [PASSED] DVI-I
[00:59:10] [PASSED] DVI-D
[00:59:10] [PASSED] DVI-A
[00:59:10] [PASSED] Composite
[00:59:10] [PASSED] SVIDEO
[00:59:10] [PASSED] LVDS
[00:59:10] [PASSED] Component
[00:59:10] [PASSED] DIN
[00:59:10] [PASSED] DP
[00:59:10] [PASSED] HDMI-A
[00:59:10] [PASSED] HDMI-B
[00:59:10] [PASSED] TV
[00:59:10] [PASSED] eDP
[00:59:10] [PASSED] Virtual
[00:59:10] [PASSED] DSI
[00:59:10] [PASSED] DPI
[00:59:10] [PASSED] Writeback
[00:59:10] [PASSED] SPI
[00:59:10] [PASSED] USB
[00:59:10] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[00:59:10] ======== drm_test_drm_connector_dynamic_init_name  =========
[00:59:10] [PASSED] Unknown
[00:59:10] [PASSED] VGA
[00:59:10] [PASSED] DVI-I
[00:59:10] [PASSED] DVI-D
[00:59:10] [PASSED] DVI-A
[00:59:10] [PASSED] Composite
[00:59:10] [PASSED] SVIDEO
[00:59:10] [PASSED] LVDS
[00:59:10] [PASSED] Component
[00:59:10] [PASSED] DIN
[00:59:10] [PASSED] DP
[00:59:10] [PASSED] HDMI-A
[00:59:10] [PASSED] HDMI-B
[00:59:10] [PASSED] TV
[00:59:10] [PASSED] eDP
[00:59:10] [PASSED] Virtual
[00:59:10] [PASSED] DSI
[00:59:10] [PASSED] DPI
[00:59:10] [PASSED] Writeback
[00:59:10] [PASSED] SPI
[00:59:10] [PASSED] USB
[00:59:10] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[00:59:10] =========== [PASSED] drm_connector_dynamic_init ============
[00:59:10] ==== drm_connector_dynamic_register_early (4 subtests) =====
[00:59:10] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[00:59:10] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[00:59:10] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[00:59:10] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[00:59:10] ====== [PASSED] drm_connector_dynamic_register_early =======
[00:59:10] ======= drm_connector_dynamic_register (7 subtests) ========
[00:59:10] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[00:59:10] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[00:59:10] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[00:59:10] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[00:59:10] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[00:59:10] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[00:59:10] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[00:59:10] ========= [PASSED] drm_connector_dynamic_register ==========
[00:59:10] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[00:59:10] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[00:59:10] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[00:59:10] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[00:59:10] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[00:59:10] ========== drm_test_get_tv_mode_from_name_valid  ===========
[00:59:10] [PASSED] NTSC
[00:59:10] [PASSED] NTSC-443
[00:59:10] [PASSED] NTSC-J
[00:59:10] [PASSED] PAL
[00:59:10] [PASSED] PAL-M
[00:59:10] [PASSED] PAL-N
[00:59:10] [PASSED] SECAM
[00:59:10] [PASSED] Mono
[00:59:10] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[00:59:10] [PASSED] drm_test_get_tv_mode_from_name_truncated
[00:59:10] ============ [PASSED] drm_get_tv_mode_from_name ============
[00:59:10] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[00:59:10] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[00:59:10] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[00:59:10] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[00:59:10] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[00:59:10] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[00:59:10] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[00:59:10] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[00:59:10] [PASSED] VIC 96
[00:59:10] [PASSED] VIC 97
[00:59:10] [PASSED] VIC 101
[00:59:10] [PASSED] VIC 102
[00:59:10] [PASSED] VIC 106
[00:59:10] [PASSED] VIC 107
[00:59:10] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[00:59:10] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[00:59:10] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[00:59:10] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[00:59:10] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[00:59:10] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[00:59:10] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[00:59:10] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[00:59:10] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[00:59:10] [PASSED] Automatic
[00:59:10] [PASSED] Full
[00:59:10] [PASSED] Limited 16:235
[00:59:10] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[00:59:10] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[00:59:10] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[00:59:10] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[00:59:10] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[00:59:10] [PASSED] RGB
[00:59:10] [PASSED] YUV 4:2:0
[00:59:10] [PASSED] YUV 4:2:2
[00:59:10] [PASSED] YUV 4:4:4
[00:59:10] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[00:59:10] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[00:59:10] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[00:59:10] ============= drm_damage_helper (21 subtests) ==============
[00:59:10] [PASSED] drm_test_damage_iter_no_damage
[00:59:10] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[00:59:10] [PASSED] drm_test_damage_iter_no_damage_src_moved
[00:59:10] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[00:59:10] [PASSED] drm_test_damage_iter_no_damage_not_visible
[00:59:10] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[00:59:10] [PASSED] drm_test_damage_iter_no_damage_no_fb
[00:59:10] [PASSED] drm_test_damage_iter_simple_damage
[00:59:10] [PASSED] drm_test_damage_iter_single_damage
[00:59:10] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[00:59:10] [PASSED] drm_test_damage_iter_single_damage_outside_src
[00:59:10] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[00:59:10] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[00:59:10] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[00:59:10] [PASSED] drm_test_damage_iter_single_damage_src_moved
[00:59:10] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[00:59:10] [PASSED] drm_test_damage_iter_damage
[00:59:10] [PASSED] drm_test_damage_iter_damage_one_intersect
[00:59:10] [PASSED] drm_test_damage_iter_damage_one_outside
[00:59:10] [PASSED] drm_test_damage_iter_damage_src_moved
[00:59:10] [PASSED] drm_test_damage_iter_damage_not_visible
[00:59:10] ================ [PASSED] drm_damage_helper ================
[00:59:10] ============== drm_dp_mst_helper (3 subtests) ==============
[00:59:10] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[00:59:10] [PASSED] Clock 154000 BPP 30 DSC disabled
[00:59:10] [PASSED] Clock 234000 BPP 30 DSC disabled
[00:59:10] [PASSED] Clock 297000 BPP 24 DSC disabled
[00:59:10] [PASSED] Clock 332880 BPP 24 DSC enabled
[00:59:10] [PASSED] Clock 324540 BPP 24 DSC enabled
[00:59:10] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[00:59:10] ============== drm_test_dp_mst_calc_pbn_div  ===============
[00:59:10] [PASSED] Link rate 2000000 lane count 4
[00:59:10] [PASSED] Link rate 2000000 lane count 2
[00:59:10] [PASSED] Link rate 2000000 lane count 1
[00:59:10] [PASSED] Link rate 1350000 lane count 4
[00:59:10] [PASSED] Link rate 1350000 lane count 2
[00:59:10] [PASSED] Link rate 1350000 lane count 1
[00:59:10] [PASSED] Link rate 1000000 lane count 4
[00:59:10] [PASSED] Link rate 1000000 lane count 2
[00:59:10] [PASSED] Link rate 1000000 lane count 1
[00:59:10] [PASSED] Link rate 810000 lane count 4
[00:59:10] [PASSED] Link rate 810000 lane count 2
[00:59:10] [PASSED] Link rate 810000 lane count 1
[00:59:10] [PASSED] Link rate 540000 lane count 4
[00:59:10] [PASSED] Link rate 540000 lane count 2
[00:59:10] [PASSED] Link rate 540000 lane count 1
[00:59:10] [PASSED] Link rate 270000 lane count 4
[00:59:10] [PASSED] Link rate 270000 lane count 2
[00:59:10] [PASSED] Link rate 270000 lane count 1
[00:59:10] [PASSED] Link rate 162000 lane count 4
[00:59:10] [PASSED] Link rate 162000 lane count 2
[00:59:10] [PASSED] Link rate 162000 lane count 1
[00:59:10] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[00:59:10] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[00:59:10] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[00:59:10] [PASSED] DP_POWER_UP_PHY with port number
[00:59:10] [PASSED] DP_POWER_DOWN_PHY with port number
[00:59:10] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[00:59:10] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[00:59:10] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[00:59:10] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[00:59:10] [PASSED] DP_QUERY_PAYLOAD with port number
[00:59:10] [PASSED] DP_QUERY_PAYLOAD with VCPI
[00:59:10] [PASSED] DP_REMOTE_DPCD_READ with port number
[00:59:10] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[00:59:10] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[00:59:10] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[00:59:10] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[00:59:10] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[00:59:10] [PASSED] DP_REMOTE_I2C_READ with port number
[00:59:10] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[00:59:10] [PASSED] DP_REMOTE_I2C_READ with transactions array
[00:59:10] [PASSED] DP_REMOTE_I2C_WRITE with port number
[00:59:10] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[00:59:10] [PASSED] DP_REMOTE_I2C_WRITE with data array
[00:59:10] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[00:59:10] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[00:59:10] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[00:59:10] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[00:59:10] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[00:59:10] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[00:59:10] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[00:59:10] ================ [PASSED] drm_dp_mst_helper ================
[00:59:10] ================== drm_exec (7 subtests) ===================
[00:59:10] [PASSED] sanitycheck
[00:59:10] [PASSED] test_lock
[00:59:10] [PASSED] test_lock_unlock
[00:59:10] [PASSED] test_duplicates
[00:59:10] [PASSED] test_prepare
[00:59:10] [PASSED] test_prepare_array
[00:59:10] [PASSED] test_multiple_loops
[00:59:10] ==================== [PASSED] drm_exec =====================
[00:59:10] =========== drm_format_helper_test (17 subtests) ===========
[00:59:10] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[00:59:10] [PASSED] single_pixel_source_buffer
[00:59:10] [PASSED] single_pixel_clip_rectangle
[00:59:10] [PASSED] well_known_colors
[00:59:10] [PASSED] destination_pitch
[00:59:10] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[00:59:10] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[00:59:10] [PASSED] single_pixel_source_buffer
[00:59:10] [PASSED] single_pixel_clip_rectangle
[00:59:10] [PASSED] well_known_colors
[00:59:10] [PASSED] destination_pitch
[00:59:10] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[00:59:10] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[00:59:10] [PASSED] single_pixel_source_buffer
[00:59:10] [PASSED] single_pixel_clip_rectangle
[00:59:10] [PASSED] well_known_colors
[00:59:10] [PASSED] destination_pitch
[00:59:10] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[00:59:10] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[00:59:10] [PASSED] single_pixel_source_buffer
[00:59:10] [PASSED] single_pixel_clip_rectangle
[00:59:10] [PASSED] well_known_colors
[00:59:10] [PASSED] destination_pitch
[00:59:10] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[00:59:10] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[00:59:10] [PASSED] single_pixel_source_buffer
[00:59:10] [PASSED] single_pixel_clip_rectangle
[00:59:10] [PASSED] well_known_colors
[00:59:10] [PASSED] destination_pitch
[00:59:10] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[00:59:10] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[00:59:10] [PASSED] single_pixel_source_buffer
[00:59:10] [PASSED] single_pixel_clip_rectangle
[00:59:10] [PASSED] well_known_colors
[00:59:10] [PASSED] destination_pitch
[00:59:10] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[00:59:10] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[00:59:10] [PASSED] single_pixel_source_buffer
[00:59:10] [PASSED] single_pixel_clip_rectangle
[00:59:10] [PASSED] well_known_colors
[00:59:10] [PASSED] destination_pitch
[00:59:10] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[00:59:10] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[00:59:10] [PASSED] single_pixel_source_buffer
[00:59:10] [PASSED] single_pixel_clip_rectangle
[00:59:10] [PASSED] well_known_colors
[00:59:10] [PASSED] destination_pitch
[00:59:10] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[00:59:10] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[00:59:10] [PASSED] single_pixel_source_buffer
[00:59:10] [PASSED] single_pixel_clip_rectangle
[00:59:10] [PASSED] well_known_colors
[00:59:10] [PASSED] destination_pitch
[00:59:10] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[00:59:10] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[00:59:10] [PASSED] single_pixel_source_buffer
[00:59:10] [PASSED] single_pixel_clip_rectangle
[00:59:10] [PASSED] well_known_colors
[00:59:10] [PASSED] destination_pitch
[00:59:10] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[00:59:10] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[00:59:10] [PASSED] single_pixel_source_buffer
[00:59:10] [PASSED] single_pixel_clip_rectangle
[00:59:10] [PASSED] well_known_colors
[00:59:10] [PASSED] destination_pitch
[00:59:10] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[00:59:10] ============== drm_test_fb_xrgb8888_to_mono  ===============
[00:59:10] [PASSED] single_pixel_source_buffer
[00:59:10] [PASSED] single_pixel_clip_rectangle
[00:59:10] [PASSED] well_known_colors
[00:59:10] [PASSED] destination_pitch
[00:59:10] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[00:59:10] ==================== drm_test_fb_swab  =====================
[00:59:10] [PASSED] single_pixel_source_buffer
[00:59:10] [PASSED] single_pixel_clip_rectangle
[00:59:10] [PASSED] well_known_colors
[00:59:10] [PASSED] destination_pitch
[00:59:10] ================ [PASSED] drm_test_fb_swab =================
[00:59:10] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[00:59:10] [PASSED] single_pixel_source_buffer
[00:59:10] [PASSED] single_pixel_clip_rectangle
[00:59:10] [PASSED] well_known_colors
[00:59:10] [PASSED] destination_pitch
[00:59:10] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[00:59:10] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[00:59:10] [PASSED] single_pixel_source_buffer
[00:59:10] [PASSED] single_pixel_clip_rectangle
[00:59:10] [PASSED] well_known_colors
[00:59:10] [PASSED] destination_pitch
[00:59:10] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[00:59:10] ================= drm_test_fb_clip_offset  =================
[00:59:10] [PASSED] pass through
[00:59:10] [PASSED] horizontal offset
[00:59:10] [PASSED] vertical offset
[00:59:10] [PASSED] horizontal and vertical offset
[00:59:10] [PASSED] horizontal offset (custom pitch)
[00:59:10] [PASSED] vertical offset (custom pitch)
[00:59:10] [PASSED] horizontal and vertical offset (custom pitch)
[00:59:10] ============= [PASSED] drm_test_fb_clip_offset =============
[00:59:10] =================== drm_test_fb_memcpy  ====================
[00:59:10] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[00:59:10] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[00:59:10] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[00:59:10] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[00:59:10] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[00:59:10] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[00:59:10] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[00:59:10] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[00:59:10] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[00:59:10] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[00:59:10] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[00:59:10] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[00:59:10] =============== [PASSED] drm_test_fb_memcpy ================
[00:59:10] ============= [PASSED] drm_format_helper_test ==============
[00:59:10] ================= drm_format (18 subtests) =================
[00:59:10] [PASSED] drm_test_format_block_width_invalid
[00:59:10] [PASSED] drm_test_format_block_width_one_plane
[00:59:10] [PASSED] drm_test_format_block_width_two_plane
[00:59:10] [PASSED] drm_test_format_block_width_three_plane
[00:59:10] [PASSED] drm_test_format_block_width_tiled
[00:59:10] [PASSED] drm_test_format_block_height_invalid
[00:59:10] [PASSED] drm_test_format_block_height_one_plane
[00:59:10] [PASSED] drm_test_format_block_height_two_plane
[00:59:10] [PASSED] drm_test_format_block_height_three_plane
[00:59:10] [PASSED] drm_test_format_block_height_tiled
[00:59:10] [PASSED] drm_test_format_min_pitch_invalid
[00:59:10] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[00:59:10] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[00:59:10] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[00:59:10] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[00:59:10] [PASSED] drm_test_format_min_pitch_two_plane
[00:59:10] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[00:59:10] [PASSED] drm_test_format_min_pitch_tiled
[00:59:10] =================== [PASSED] drm_format ====================
[00:59:10] ============== drm_framebuffer (10 subtests) ===============
[00:59:10] ========== drm_test_framebuffer_check_src_coords  ==========
[00:59:10] [PASSED] Success: source fits into fb
[00:59:10] [PASSED] Fail: overflowing fb with x-axis coordinate
[00:59:10] [PASSED] Fail: overflowing fb with y-axis coordinate
[00:59:10] [PASSED] Fail: overflowing fb with source width
[00:59:10] [PASSED] Fail: overflowing fb with source height
[00:59:10] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[00:59:10] [PASSED] drm_test_framebuffer_cleanup
[00:59:10] =============== drm_test_framebuffer_create  ===============
[00:59:10] [PASSED] ABGR8888 normal sizes
[00:59:10] [PASSED] ABGR8888 max sizes
[00:59:10] [PASSED] ABGR8888 pitch greater than min required
[00:59:10] [PASSED] ABGR8888 pitch less than min required
[00:59:10] [PASSED] ABGR8888 Invalid width
[00:59:10] [PASSED] ABGR8888 Invalid buffer handle
[00:59:10] [PASSED] No pixel format
[00:59:10] [PASSED] ABGR8888 Width 0
[00:59:10] [PASSED] ABGR8888 Height 0
[00:59:10] [PASSED] ABGR8888 Out of bound height * pitch combination
[00:59:10] [PASSED] ABGR8888 Large buffer offset
[00:59:10] [PASSED] ABGR8888 Buffer offset for inexistent plane
[00:59:10] [PASSED] ABGR8888 Invalid flag
[00:59:10] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[00:59:10] [PASSED] ABGR8888 Valid buffer modifier
[00:59:10] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[00:59:10] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[00:59:10] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[00:59:10] [PASSED] NV12 Normal sizes
[00:59:10] [PASSED] NV12 Max sizes
[00:59:10] [PASSED] NV12 Invalid pitch
[00:59:10] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[00:59:10] [PASSED] NV12 different  modifier per-plane
[00:59:10] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[00:59:10] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[00:59:10] [PASSED] NV12 Modifier for inexistent plane
[00:59:10] [PASSED] NV12 Handle for inexistent plane
[00:59:10] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[00:59:10] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[00:59:10] [PASSED] YVU420 Normal sizes
[00:59:10] [PASSED] YVU420 Max sizes
[00:59:10] [PASSED] YVU420 Invalid pitch
[00:59:10] [PASSED] YVU420 Different pitches
[00:59:10] [PASSED] YVU420 Different buffer offsets/pitches
[00:59:10] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[00:59:10] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[00:59:10] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[00:59:10] [PASSED] YVU420 Valid modifier
[00:59:10] [PASSED] YVU420 Different modifiers per plane
[00:59:10] [PASSED] YVU420 Modifier for inexistent plane
[00:59:10] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[00:59:10] [PASSED] X0L2 Normal sizes
[00:59:10] [PASSED] X0L2 Max sizes
[00:59:10] [PASSED] X0L2 Invalid pitch
[00:59:10] [PASSED] X0L2 Pitch greater than minimum required
[00:59:10] [PASSED] X0L2 Handle for inexistent plane
[00:59:10] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[00:59:10] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[00:59:10] [PASSED] X0L2 Valid modifier
[00:59:10] [PASSED] X0L2 Modifier for inexistent plane
[00:59:10] =========== [PASSED] drm_test_framebuffer_create ===========
[00:59:10] [PASSED] drm_test_framebuffer_free
[00:59:10] [PASSED] drm_test_framebuffer_init
[00:59:10] [PASSED] drm_test_framebuffer_init_bad_format
[00:59:10] [PASSED] drm_test_framebuffer_init_dev_mismatch
[00:59:10] [PASSED] drm_test_framebuffer_lookup
[00:59:10] [PASSED] drm_test_framebuffer_lookup_inexistent
[00:59:10] [PASSED] drm_test_framebuffer_modifiers_not_supported
[00:59:10] ================= [PASSED] drm_framebuffer =================
[00:59:10] ================ drm_gem_shmem (8 subtests) ================
[00:59:10] [PASSED] drm_gem_shmem_test_obj_create
[00:59:10] [PASSED] drm_gem_shmem_test_obj_create_private
[00:59:10] [PASSED] drm_gem_shmem_test_pin_pages
[00:59:10] [PASSED] drm_gem_shmem_test_vmap
[00:59:10] [PASSED] drm_gem_shmem_test_get_pages_sgt
[00:59:10] [PASSED] drm_gem_shmem_test_get_sg_table
[00:59:10] [PASSED] drm_gem_shmem_test_madvise
[00:59:10] [PASSED] drm_gem_shmem_test_purge
[00:59:10] ================== [PASSED] drm_gem_shmem ==================
[00:59:10] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[00:59:10] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[00:59:10] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[00:59:10] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[00:59:10] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[00:59:10] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[00:59:10] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[00:59:10] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[00:59:10] [PASSED] Automatic
[00:59:10] [PASSED] Full
[00:59:10] [PASSED] Limited 16:235
[00:59:10] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[00:59:10] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[00:59:10] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[00:59:10] [PASSED] drm_test_check_disable_connector
[00:59:10] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[00:59:10] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[00:59:10] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[00:59:10] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[00:59:10] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[00:59:10] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[00:59:10] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[00:59:10] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[00:59:10] [PASSED] drm_test_check_output_bpc_dvi
[00:59:10] [PASSED] drm_test_check_output_bpc_format_vic_1
[00:59:10] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[00:59:10] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[00:59:10] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[00:59:10] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[00:59:10] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[00:59:10] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[00:59:10] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[00:59:10] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[00:59:10] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[00:59:10] [PASSED] drm_test_check_broadcast_rgb_value
[00:59:10] [PASSED] drm_test_check_bpc_8_value
[00:59:10] [PASSED] drm_test_check_bpc_10_value
[00:59:10] [PASSED] drm_test_check_bpc_12_value
[00:59:10] [PASSED] drm_test_check_format_value
[00:59:10] [PASSED] drm_test_check_tmds_char_value
[00:59:10] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[00:59:10] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[00:59:10] [PASSED] drm_test_check_mode_valid
[00:59:10] [PASSED] drm_test_check_mode_valid_reject
[00:59:10] [PASSED] drm_test_check_mode_valid_reject_rate
[00:59:10] [PASSED] drm_test_check_mode_valid_reject_max_clock
[00:59:10] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[00:59:10] ================= drm_managed (2 subtests) =================
[00:59:10] [PASSED] drm_test_managed_release_action
[00:59:10] [PASSED] drm_test_managed_run_action
[00:59:10] =================== [PASSED] drm_managed ===================
[00:59:10] =================== drm_mm (6 subtests) ====================
[00:59:10] [PASSED] drm_test_mm_init
[00:59:10] [PASSED] drm_test_mm_debug
[00:59:10] [PASSED] drm_test_mm_align32
[00:59:10] [PASSED] drm_test_mm_align64
[00:59:10] [PASSED] drm_test_mm_lowest
[00:59:10] [PASSED] drm_test_mm_highest
[00:59:10] ===================== [PASSED] drm_mm ======================
[00:59:10] ============= drm_modes_analog_tv (5 subtests) =============
[00:59:10] [PASSED] drm_test_modes_analog_tv_mono_576i
[00:59:10] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[00:59:10] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[00:59:10] [PASSED] drm_test_modes_analog_tv_pal_576i
[00:59:10] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[00:59:10] =============== [PASSED] drm_modes_analog_tv ===============
[00:59:10] ============== drm_plane_helper (2 subtests) ===============
[00:59:10] =============== drm_test_check_plane_state  ================
[00:59:10] [PASSED] clipping_simple
[00:59:10] [PASSED] clipping_rotate_reflect
[00:59:10] [PASSED] positioning_simple
[00:59:10] [PASSED] upscaling
[00:59:10] [PASSED] downscaling
[00:59:10] [PASSED] rounding1
[00:59:10] [PASSED] rounding2
[00:59:10] [PASSED] rounding3
[00:59:10] [PASSED] rounding4
[00:59:10] =========== [PASSED] drm_test_check_plane_state ============
[00:59:10] =========== drm_test_check_invalid_plane_state  ============
[00:59:10] [PASSED] positioning_invalid
[00:59:10] [PASSED] upscaling_invalid
[00:59:10] [PASSED] downscaling_invalid
[00:59:10] ======= [PASSED] drm_test_check_invalid_plane_state ========
[00:59:10] ================ [PASSED] drm_plane_helper =================
[00:59:10] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[00:59:10] ====== drm_test_connector_helper_tv_get_modes_check  =======
[00:59:10] [PASSED] None
[00:59:10] [PASSED] PAL
[00:59:10] [PASSED] NTSC
[00:59:10] [PASSED] Both, NTSC Default
[00:59:10] [PASSED] Both, PAL Default
[00:59:10] [PASSED] Both, NTSC Default, with PAL on command-line
[00:59:10] [PASSED] Both, PAL Default, with NTSC on command-line
[00:59:10] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[00:59:10] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[00:59:10] ================== drm_rect (9 subtests) ===================
[00:59:10] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[00:59:10] [PASSED] drm_test_rect_clip_scaled_not_clipped
[00:59:10] [PASSED] drm_test_rect_clip_scaled_clipped
[00:59:10] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[00:59:10] ================= drm_test_rect_intersect  =================
[00:59:10] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[00:59:10] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[00:59:10] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[00:59:10] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[00:59:10] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[00:59:10] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[00:59:10] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[00:59:10] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[00:59:10] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[00:59:10] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[00:59:10] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[00:59:10] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[00:59:10] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[00:59:10] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[00:59:10] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[00:59:10] ============= [PASSED] drm_test_rect_intersect =============
[00:59:10] ================ drm_test_rect_calc_hscale  ================
[00:59:10] [PASSED] normal use
[00:59:10] [PASSED] out of max range
[00:59:10] [PASSED] out of min range
[00:59:10] [PASSED] zero dst
[00:59:10] [PASSED] negative src
[00:59:10] [PASSED] negative dst
[00:59:10] ============ [PASSED] drm_test_rect_calc_hscale ============
[00:59:10] ================ drm_test_rect_calc_vscale  ================
[00:59:10] [PASSED] normal use
[00:59:10] [PASSED] out of max range
[00:59:10] [PASSED] out of min range
[00:59:10] [PASSED] zero dst
[00:59:10] [PASSED] negative src
[00:59:10] [PASSED] negative dst
[00:59:10] ============ [PASSED] drm_test_rect_calc_vscale ============
[00:59:10] ================== drm_test_rect_rotate  ===================
[00:59:10] [PASSED] reflect-x
[00:59:10] [PASSED] reflect-y
[00:59:10] [PASSED] rotate-0
[00:59:10] [PASSED] rotate-90
[00:59:10] [PASSED] rotate-180
[00:59:10] [PASSED] rotate-270
stty: 'standard input': Inappropriate ioctl for device
[00:59:10] ============== [PASSED] drm_test_rect_rotate ===============
[00:59:10] ================ drm_test_rect_rotate_inv  =================
[00:59:10] [PASSED] reflect-x
[00:59:10] [PASSED] reflect-y
[00:59:10] [PASSED] rotate-0
[00:59:10] [PASSED] rotate-90
[00:59:10] [PASSED] rotate-180
[00:59:10] [PASSED] rotate-270
[00:59:10] ============ [PASSED] drm_test_rect_rotate_inv =============
[00:59:10] ==================== [PASSED] drm_rect =====================
[00:59:10] ============ drm_sysfb_modeset_test (1 subtest) ============
[00:59:10] ============ drm_test_sysfb_build_fourcc_list  =============
[00:59:10] [PASSED] no native formats
[00:59:10] [PASSED] XRGB8888 as native format
[00:59:10] [PASSED] remove duplicates
[00:59:10] [PASSED] convert alpha formats
[00:59:10] [PASSED] random formats
[00:59:10] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[00:59:10] ============= [PASSED] drm_sysfb_modeset_test ==============
[00:59:10] ============================================================
[00:59:10] Testing complete. Ran 616 tests: passed: 616
[00:59:10] Elapsed time: 23.689s total, 1.671s configuring, 21.852s building, 0.139s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[00:59:10] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[00:59:12] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[00:59:19] Starting KUnit Kernel (1/1)...
[00:59:19] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[00:59:19] ================= ttm_device (5 subtests) ==================
[00:59:19] [PASSED] ttm_device_init_basic
[00:59:19] [PASSED] ttm_device_init_multiple
[00:59:19] [PASSED] ttm_device_fini_basic
[00:59:19] [PASSED] ttm_device_init_no_vma_man
[00:59:19] ================== ttm_device_init_pools  ==================
[00:59:19] [PASSED] No DMA allocations, no DMA32 required
[00:59:19] [PASSED] DMA allocations, DMA32 required
[00:59:19] [PASSED] No DMA allocations, DMA32 required
[00:59:19] [PASSED] DMA allocations, no DMA32 required
[00:59:19] ============== [PASSED] ttm_device_init_pools ==============
[00:59:19] =================== [PASSED] ttm_device ====================
[00:59:19] ================== ttm_pool (8 subtests) ===================
[00:59:19] ================== ttm_pool_alloc_basic  ===================
[00:59:19] [PASSED] One page
[00:59:19] [PASSED] More than one page
[00:59:19] [PASSED] Above the allocation limit
[00:59:19] [PASSED] One page, with coherent DMA mappings enabled
[00:59:19] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[00:59:19] ============== [PASSED] ttm_pool_alloc_basic ===============
[00:59:19] ============== ttm_pool_alloc_basic_dma_addr  ==============
[00:59:19] [PASSED] One page
[00:59:19] [PASSED] More than one page
[00:59:19] [PASSED] Above the allocation limit
[00:59:19] [PASSED] One page, with coherent DMA mappings enabled
[00:59:19] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[00:59:19] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[00:59:19] [PASSED] ttm_pool_alloc_order_caching_match
[00:59:19] [PASSED] ttm_pool_alloc_caching_mismatch
[00:59:19] [PASSED] ttm_pool_alloc_order_mismatch
[00:59:19] [PASSED] ttm_pool_free_dma_alloc
[00:59:19] [PASSED] ttm_pool_free_no_dma_alloc
[00:59:19] [PASSED] ttm_pool_fini_basic
[00:59:19] ==================== [PASSED] ttm_pool =====================
[00:59:19] ================ ttm_resource (8 subtests) =================
[00:59:19] ================= ttm_resource_init_basic  =================
[00:59:19] [PASSED] Init resource in TTM_PL_SYSTEM
[00:59:19] [PASSED] Init resource in TTM_PL_VRAM
[00:59:19] [PASSED] Init resource in a private placement
[00:59:19] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[00:59:19] ============= [PASSED] ttm_resource_init_basic =============
[00:59:19] [PASSED] ttm_resource_init_pinned
[00:59:19] [PASSED] ttm_resource_fini_basic
[00:59:19] [PASSED] ttm_resource_manager_init_basic
[00:59:19] [PASSED] ttm_resource_manager_usage_basic
[00:59:19] [PASSED] ttm_resource_manager_set_used_basic
[00:59:19] [PASSED] ttm_sys_man_alloc_basic
[00:59:19] [PASSED] ttm_sys_man_free_basic
[00:59:19] ================== [PASSED] ttm_resource ===================
[00:59:19] =================== ttm_tt (15 subtests) ===================
[00:59:19] ==================== ttm_tt_init_basic  ====================
[00:59:19] [PASSED] Page-aligned size
[00:59:19] [PASSED] Extra pages requested
[00:59:19] ================ [PASSED] ttm_tt_init_basic ================
[00:59:19] [PASSED] ttm_tt_init_misaligned
[00:59:19] [PASSED] ttm_tt_fini_basic
[00:59:19] [PASSED] ttm_tt_fini_sg
[00:59:19] [PASSED] ttm_tt_fini_shmem
[00:59:19] [PASSED] ttm_tt_create_basic
[00:59:19] [PASSED] ttm_tt_create_invalid_bo_type
[00:59:19] [PASSED] ttm_tt_create_ttm_exists
[00:59:19] [PASSED] ttm_tt_create_failed
[00:59:19] [PASSED] ttm_tt_destroy_basic
[00:59:19] [PASSED] ttm_tt_populate_null_ttm
[00:59:19] [PASSED] ttm_tt_populate_populated_ttm
[00:59:19] [PASSED] ttm_tt_unpopulate_basic
[00:59:19] [PASSED] ttm_tt_unpopulate_empty_ttm
[00:59:19] [PASSED] ttm_tt_swapin_basic
[00:59:19] ===================== [PASSED] ttm_tt ======================
[00:59:19] =================== ttm_bo (14 subtests) ===================
[00:59:19] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[00:59:19] [PASSED] Cannot be interrupted and sleeps
[00:59:19] [PASSED] Cannot be interrupted, locks straight away
[00:59:19] [PASSED] Can be interrupted, sleeps
[00:59:19] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[00:59:19] [PASSED] ttm_bo_reserve_locked_no_sleep
[00:59:19] [PASSED] ttm_bo_reserve_no_wait_ticket
[00:59:20] [PASSED] ttm_bo_reserve_double_resv
[00:59:20] [PASSED] ttm_bo_reserve_interrupted
[00:59:20] [PASSED] ttm_bo_reserve_deadlock
[00:59:20] [PASSED] ttm_bo_unreserve_basic
[00:59:20] [PASSED] ttm_bo_unreserve_pinned
[00:59:20] [PASSED] ttm_bo_unreserve_bulk
[00:59:20] [PASSED] ttm_bo_put_basic
[00:59:20] [PASSED] ttm_bo_put_shared_resv
[00:59:20] [PASSED] ttm_bo_pin_basic
[00:59:20] [PASSED] ttm_bo_pin_unpin_resource
[00:59:20] [PASSED] ttm_bo_multiple_pin_one_unpin
[00:59:20] ===================== [PASSED] ttm_bo ======================
[00:59:20] ============== ttm_bo_validate (21 subtests) ===============
[00:59:20] ============== ttm_bo_init_reserved_sys_man  ===============
[00:59:20] [PASSED] Buffer object for userspace
[00:59:20] [PASSED] Kernel buffer object
[00:59:20] [PASSED] Shared buffer object
[00:59:20] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[00:59:20] ============== ttm_bo_init_reserved_mock_man  ==============
[00:59:20] [PASSED] Buffer object for userspace
[00:59:20] [PASSED] Kernel buffer object
[00:59:20] [PASSED] Shared buffer object
[00:59:20] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[00:59:20] [PASSED] ttm_bo_init_reserved_resv
[00:59:20] ================== ttm_bo_validate_basic  ==================
[00:59:20] [PASSED] Buffer object for userspace
[00:59:20] [PASSED] Kernel buffer object
[00:59:20] [PASSED] Shared buffer object
[00:59:20] ============== [PASSED] ttm_bo_validate_basic ==============
[00:59:20] [PASSED] ttm_bo_validate_invalid_placement
[00:59:20] ============= ttm_bo_validate_same_placement  ==============
[00:59:20] [PASSED] System manager
[00:59:20] [PASSED] VRAM manager
[00:59:20] ========= [PASSED] ttm_bo_validate_same_placement ==========
[00:59:20] [PASSED] ttm_bo_validate_failed_alloc
[00:59:20] [PASSED] ttm_bo_validate_pinned
[00:59:20] [PASSED] ttm_bo_validate_busy_placement
[00:59:20] ================ ttm_bo_validate_multihop  =================
[00:59:20] [PASSED] Buffer object for userspace
[00:59:20] [PASSED] Kernel buffer object
[00:59:20] [PASSED] Shared buffer object
[00:59:20] ============ [PASSED] ttm_bo_validate_multihop =============
[00:59:20] ========== ttm_bo_validate_no_placement_signaled  ==========
[00:59:20] [PASSED] Buffer object in system domain, no page vector
[00:59:20] [PASSED] Buffer object in system domain with an existing page vector
[00:59:20] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[00:59:20] ======== ttm_bo_validate_no_placement_not_signaled  ========
[00:59:20] [PASSED] Buffer object for userspace
[00:59:20] [PASSED] Kernel buffer object
[00:59:20] [PASSED] Shared buffer object
[00:59:20] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[00:59:20] [PASSED] ttm_bo_validate_move_fence_signaled
[00:59:20] ========= ttm_bo_validate_move_fence_not_signaled  =========
[00:59:20] [PASSED] Waits for GPU
[00:59:20] [PASSED] Tries to lock straight away
[00:59:20] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[00:59:20] [PASSED] ttm_bo_validate_happy_evict
[00:59:20] [PASSED] ttm_bo_validate_all_pinned_evict
[00:59:20] [PASSED] ttm_bo_validate_allowed_only_evict
[00:59:20] [PASSED] ttm_bo_validate_deleted_evict
[00:59:20] [PASSED] ttm_bo_validate_busy_domain_evict
[00:59:20] [PASSED] ttm_bo_validate_evict_gutting
[00:59:20] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[00:59:20] ================= [PASSED] ttm_bo_validate =================
[00:59:20] ============================================================
[00:59:20] Testing complete. Ran 101 tests: passed: 101
[00:59:20] Elapsed time: 9.568s total, 1.643s configuring, 7.709s building, 0.172s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Add test for G2G communications (rev2)

[Patchwork]

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== Series Details ==

Series: Add test for G2G communications (rev2)
URL   : https://patchwork.freedesktop.org/series/152101/
State : success

== Summary ==

CI Bug Log - changes from xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c_BAT -> xe-pw-152101v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (8 -> 7)
------------------------------

  Missing    (1): bat-adlp-vm 

Known issues
------------

  Here are the changes found in xe-pw-152101v2_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@kms_flip@basic-plain-flip@c-edp1:
    - bat-adlp-7:         [DMESG-WARN][1] ([Intel XE#4543]) -> [PASS][2] +1 other test pass
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/bat-adlp-7/igt@kms_flip@basic-plain-flip@c-edp1.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/bat-adlp-7/igt@kms_flip@basic-plain-flip@c-edp1.html

  
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543


Build changes
-------------

  * Linux: xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c -> xe-pw-152101v2

  IGT_8487: 8487
  xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c: 7b7457e249a1f7db97122bc6b9384e5e2f45475c
  xe-pw-152101v2: 152101v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/index.html

[-- Attachment #2: Type: text/html, Size: 2021 bytes --]

✗ Xe.CI.Full: failure for Add test for G2G communications (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 29133 bytes --]

== Series Details ==

Series: Add test for G2G communications (rev2)
URL   : https://patchwork.freedesktop.org/series/152101/
State : failure

== Summary ==

CI Bug Log - changes from xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c_FULL -> xe-pw-152101v2_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-152101v2_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-152101v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-152101v2_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_feature_discovery@display-1x:
    - shard-bmg:          [PASS][1] -> [DMESG-WARN][2] +2 other tests dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_feature_discovery@display-1x.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-6/igt@kms_feature_discovery@display-1x.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-bmg:          [PASS][3] -> [SKIP][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_hdr@bpc-switch-suspend.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-6/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_hdr@static-toggle@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][5]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-6/igt@kms_hdr@static-toggle@pipe-a-dp-2.html

  * igt@kms_rotation_crc@sprite-rotation-180:
    - shard-bmg:          [PASS][6] -> [INCOMPLETE][7]
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-4/igt@kms_rotation_crc@sprite-rotation-180.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-7/igt@kms_rotation_crc@sprite-rotation-180.html

  
Known issues
------------

  Here are the changes found in xe-pw-152101v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@x-tiled-32bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][8] ([Intel XE#316])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-463/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
    - shard-dg2-set2:     NOTRUN -> [SKIP][9] ([Intel XE#1124])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-463/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-b-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][10] ([Intel XE#787]) +174 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-432/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-b-dp-2.html

  * igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][11] ([Intel XE#455] / [Intel XE#787]) +26 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-432/igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [PASS][12] -> [INCOMPLETE][13] ([Intel XE#3862]) +1 other test incomplete
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-1/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][14] ([Intel XE#4418])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-463/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_cdclk@mode-transition@pipe-a-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][15] ([Intel XE#4417]) +3 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-432/igt@kms_cdclk@mode-transition@pipe-a-dp-2.html

  * igt@kms_chamelium_hpd@dp-hpd-after-hibernate:
    - shard-dg2-set2:     NOTRUN -> [SKIP][16] ([Intel XE#373])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-463/igt@kms_chamelium_hpd@dp-hpd-after-hibernate.html

  * igt@kms_content_protection@srm@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][17] ([Intel XE#1178])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-434/igt@kms_content_protection@srm@pipe-a-dp-4.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
    - shard-dg2-set2:     [PASS][18] -> [INCOMPLETE][19] ([Intel XE#3226])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-dg2-464/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-435/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][20] -> [SKIP][21] ([Intel XE#2291])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-8/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop:
    - shard-bmg:          [PASS][22] -> [SKIP][23] ([Intel XE#2316])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-8/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-on-nop.html

  * igt@kms_flip@flip-vs-blocking-wf-vblank@c-hdmi-a1:
    - shard-adlp:         [PASS][24] -> [DMESG-WARN][25] ([Intel XE#4543]) +7 other tests dmesg-warn
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-adlp-3/igt@kms_flip@flip-vs-blocking-wf-vblank@c-hdmi-a1.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-adlp-4/igt@kms_flip@flip-vs-blocking-wf-vblank@c-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-bmg:          [PASS][26] -> [INCOMPLETE][27] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-2/igt@kms_flip@flip-vs-suspend-interruptible.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-3/igt@kms_flip@flip-vs-suspend-interruptible.html
    - shard-dg2-set2:     [PASS][28] -> [INCOMPLETE][29] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-dg2-463/igt@kms_flip@flip-vs-suspend-interruptible.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-464/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][30] ([Intel XE#651]) +2 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-463/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][31] ([Intel XE#653]) +3 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [PASS][32] -> [SKIP][33] ([Intel XE#1503])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-7/igt@kms_hdr@invalid-hdr.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-5/igt@kms_hdr@invalid-hdr.html

  * igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64:
    - shard-dg2-set2:     NOTRUN -> [FAIL][34] ([Intel XE#616])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-466/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-bmg:          [PASS][35] -> [SKIP][36] ([Intel XE#4596])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-8/igt@kms_plane_multiple@2x-tiling-none.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_psr2_sf@pr-cursor-plane-update-sf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][37] ([Intel XE#1489])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-463/igt@kms_psr2_sf@pr-cursor-plane-update-sf.html

  * igt@kms_psr@fbc-psr-primary-page-flip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][38] ([Intel XE#2850] / [Intel XE#929])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-463/igt@kms_psr@fbc-psr-primary-page-flip.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][39] ([Intel XE#3414])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-463/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-dg2-set2:     NOTRUN -> [SKIP][40] ([Intel XE#1127])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-463/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_vblank@query-forked-busy:
    - shard-bmg:          [PASS][41] -> [INCOMPLETE][42] ([Intel XE#4488]) +1 other test incomplete
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-8/igt@kms_vblank@query-forked-busy.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-1/igt@kms_vblank@query-forked-busy.html

  * igt@kms_vblank@ts-continuation-modeset:
    - shard-adlp:         [PASS][43] -> [DMESG-WARN][44] ([Intel XE#2953] / [Intel XE#4173]) +1 other test dmesg-warn
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-adlp-2/igt@kms_vblank@ts-continuation-modeset.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-adlp-6/igt@kms_vblank@ts-continuation-modeset.html

  * igt@kms_vrr@cmrr@pipe-a-edp-1:
    - shard-lnl:          [PASS][45] -> [FAIL][46] ([Intel XE#4459]) +1 other test fail
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-lnl-1/igt@kms_vrr@cmrr@pipe-a-edp-1.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-lnl-8/igt@kms_vrr@cmrr@pipe-a-edp-1.html

  * igt@xe_eu_stall@invalid-gt-id:
    - shard-dg2-set2:     NOTRUN -> [SKIP][47] ([Intel XE#5626])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-463/igt@xe_eu_stall@invalid-gt-id.html

  * igt@xe_eudebug@basic-vm-bind-ufence-sigint-client:
    - shard-dg2-set2:     NOTRUN -> [SKIP][48] ([Intel XE#4837])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-463/igt@xe_eudebug@basic-vm-bind-ufence-sigint-client.html

  * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind:
    - shard-dg2-set2:     [PASS][49] -> [SKIP][50] ([Intel XE#1392]) +7 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-dg2-433/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind.html

  * igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-prefetch:
    - shard-bmg:          [PASS][51] -> [DMESG-WARN][52] ([Intel XE#3428])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-prefetch.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-6/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-prefetch.html

  * igt@xe_exec_fault_mode@twice-bindexecqueue-rebind-prefetch:
    - shard-dg2-set2:     NOTRUN -> [SKIP][53] ([Intel XE#288]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-463/igt@xe_exec_fault_mode@twice-bindexecqueue-rebind-prefetch.html

  * igt@xe_exec_system_allocator@many-large-execqueues-mmap-free:
    - shard-dg2-set2:     NOTRUN -> [SKIP][54] ([Intel XE#4915]) +29 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-463/igt@xe_exec_system_allocator@many-large-execqueues-mmap-free.html

  * igt@xe_exec_system_allocator@processes-evict-malloc-mix-bo:
    - shard-bmg:          [PASS][55] -> [DMESG-WARN][56] ([Intel XE#3428] / [Intel XE#5215]) +1 other test dmesg-warn
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@xe_exec_system_allocator@processes-evict-malloc-mix-bo.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-6/igt@xe_exec_system_allocator@processes-evict-malloc-mix-bo.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset:
    - shard-lnl:          [PASS][57] -> [FAIL][58] ([Intel XE#5018]) +1 other test fail
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-lnl-2/igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-lnl-5/igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset.html

  * igt@xe_sriov_auto_provisioning@selfconfig-basic:
    - shard-dg2-set2:     NOTRUN -> [SKIP][59] ([Intel XE#4130])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-463/igt@xe_sriov_auto_provisioning@selfconfig-basic.html

  
#### Possible fixes ####

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-adlp:         [DMESG-FAIL][60] ([Intel XE#4543]) -> [PASS][61]
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-adlp-9/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-adlp-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][62] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) -> [PASS][63]
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4:
    - shard-dg2-set2:     [INCOMPLETE][64] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522]) -> [PASS][65]
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
    - shard-bmg:          [SKIP][66] ([Intel XE#2291]) -> [PASS][67]
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-7/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html

  * igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
    - shard-bmg:          [SKIP][68] ([Intel XE#2316]) -> [PASS][69] +1 other test pass
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-7/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html

  * igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][70] ([Intel XE#4543]) -> [PASS][71] +4 other tests pass
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-adlp-6/igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-adlp-3/igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-bmg:          [SKIP][72] ([Intel XE#1503]) -> [PASS][73]
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_hdr@static-toggle-suspend.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-7/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_plane_scaling@2x-scaler-multi-pipe:
    - shard-bmg:          [SKIP][74] ([Intel XE#2571]) -> [PASS][75]
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-7/igt@kms_plane_scaling@2x-scaler-multi-pipe.html

  * igt@kms_setmode@basic:
    - shard-lnl:          [FAIL][76] ([Intel XE#2883]) -> [PASS][77] +1 other test pass
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-lnl-4/igt@kms_setmode@basic.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-lnl-4/igt@kms_setmode@basic.html

  * igt@kms_vblank@query-forked-busy-hang@pipe-a-hdmi-a-1:
    - shard-adlp:         [DMESG-WARN][78] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][79] +2 other tests pass
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-adlp-3/igt@kms_vblank@query-forked-busy-hang@pipe-a-hdmi-a-1.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-adlp-4/igt@kms_vblank@query-forked-busy-hang@pipe-a-hdmi-a-1.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate:
    - shard-dg2-set2:     [SKIP][80] ([Intel XE#1392]) -> [PASS][81] +8 other tests pass
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-dg2-432/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-dg2-463/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_reset@parallel-gt-reset:
    - shard-bmg:          [DMESG-WARN][82] ([Intel XE#3876]) -> [PASS][83]
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-3/igt@xe_exec_reset@parallel-gt-reset.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-3/igt@xe_exec_reset@parallel-gt-reset.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset:
    - shard-lnl:          [FAIL][84] ([Intel XE#5018]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-lnl-5/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-lnl-7/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-bo-map-nomemset:
    - shard-bmg:          [FAIL][86] ([Intel XE#4937]) -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-1/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-bo-map-nomemset.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-2/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-bo-map-nomemset.html

  
#### Warnings ####

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt:
    - shard-bmg:          [SKIP][88] ([Intel XE#2312]) -> [SKIP][89] ([Intel XE#2311]) +9 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move:
    - shard-bmg:          [SKIP][90] ([Intel XE#5390]) -> [SKIP][91] ([Intel XE#2312]) +1 other test skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt:
    - shard-bmg:          [SKIP][92] ([Intel XE#2312]) -> [SKIP][93] ([Intel XE#5390]) +3 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-move:
    - shard-bmg:          [SKIP][94] ([Intel XE#2311]) -> [SKIP][95] ([Intel XE#2312]) +3 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-move.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][96] ([Intel XE#2312]) -> [SKIP][97] ([Intel XE#2313]) +9 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt:
    - shard-bmg:          [SKIP][98] ([Intel XE#2313]) -> [SKIP][99] ([Intel XE#2312]) +1 other test skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [FAIL][100] ([Intel XE#1729]) -> [SKIP][101] ([Intel XE#2426])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2571
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2883]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2883
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#3226]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3226
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3428
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
  [Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4417
  [Intel XE#4418]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4418
  [Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
  [Intel XE#4488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4488
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4937
  [Intel XE#5018]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5018
  [Intel XE#5215]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5215
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929


Build changes
-------------

  * Linux: xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c -> xe-pw-152101v2

  IGT_8487: 8487
  xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c: 7b7457e249a1f7db97122bc6b9384e5e2f45475c
  xe-pw-152101v2: 152101v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152101v2/index.html

[-- Attachment #2: Type: text/html, Size: 32855 bytes --]

Re: [PATCH v2 1/4] drm/xe/guc: Update CSS header structures

[Daniele Ceraolo Spurio]

On 8/5/2025 4:42 PM, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Rework the CSS header structure according to recent updates to the GuC
> API spec. Also include more field definitions.
>
> v2: Also pass the new GuC specific structure to a GuC specific
> function instead of the higher level, generic structure (review
> feedback from Daniele).
> Also correct naming of CSS_TIME_* fields.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele

> ---
>   drivers/gpu/drm/xe/xe_uc_fw.c     | 24 ++++++------
>   drivers/gpu/drm/xe/xe_uc_fw_abi.h | 64 ++++++++++++++++++++-----------
>   2 files changed, 53 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
> index a236f1d37248..f037571865ad 100644
> --- a/drivers/gpu/drm/xe/xe_uc_fw.c
> +++ b/drivers/gpu/drm/xe/xe_uc_fw.c
> @@ -329,7 +329,7 @@ static void uc_fw_fini(struct drm_device *drm, void *arg)
>   	xe_uc_fw_change_status(uc_fw, XE_UC_FIRMWARE_SELECTED);
>   }
>   
> -static int guc_read_css_info(struct xe_uc_fw *uc_fw, struct uc_css_header *css)
> +static int guc_read_css_info(struct xe_uc_fw *uc_fw, struct uc_css_guc_info *guc_info)
>   {
>   	struct xe_gt *gt = uc_fw_to_gt(uc_fw);
>   	struct xe_uc_fw_version *release = &uc_fw->versions.found[XE_UC_FW_VER_RELEASE];
> @@ -344,11 +344,11 @@ static int guc_read_css_info(struct xe_uc_fw *uc_fw, struct uc_css_header *css)
>   		return -EINVAL;
>   	}
>   
> -	compatibility->major = FIELD_GET(CSS_SW_VERSION_UC_MAJOR, css->submission_version);
> -	compatibility->minor = FIELD_GET(CSS_SW_VERSION_UC_MINOR, css->submission_version);
> -	compatibility->patch = FIELD_GET(CSS_SW_VERSION_UC_PATCH, css->submission_version);
> +	compatibility->major = FIELD_GET(CSS_SW_VERSION_UC_MAJOR, guc_info->submission_version);
> +	compatibility->minor = FIELD_GET(CSS_SW_VERSION_UC_MINOR, guc_info->submission_version);
> +	compatibility->patch = FIELD_GET(CSS_SW_VERSION_UC_PATCH, guc_info->submission_version);
>   
> -	uc_fw->private_data_size = css->private_data_size;
> +	uc_fw->private_data_size = guc_info->private_data_size;
>   
>   	return 0;
>   }
> @@ -417,8 +417,8 @@ static int parse_css_header(struct xe_uc_fw *uc_fw, const void *fw_data, size_t
>   	css = (struct uc_css_header *)fw_data;
>   
>   	/* Check integrity of size values inside CSS header */
> -	size = (css->header_size_dw - css->key_size_dw - css->modulus_size_dw -
> -		css->exponent_size_dw) * sizeof(u32);
> +	size = (css->header_size_dw - css->rsa_info.key_size_dw - css->rsa_info.modulus_size_dw -
> +		css->rsa_info.exponent_size_dw) * sizeof(u32);
>   	if (unlikely(size != sizeof(struct uc_css_header))) {
>   		drm_warn(&xe->drm,
>   			 "%s firmware %s: unexpected header size: %zu != %zu\n",
> @@ -431,7 +431,7 @@ static int parse_css_header(struct xe_uc_fw *uc_fw, const void *fw_data, size_t
>   	uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
>   
>   	/* now RSA */
> -	uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
> +	uc_fw->rsa_size = css->rsa_info.key_size_dw * sizeof(u32);
>   
>   	/* At least, it should have header, uCode and RSA. Size of all three. */
>   	size = sizeof(struct uc_css_header) + uc_fw->ucode_size +
> @@ -444,12 +444,12 @@ static int parse_css_header(struct xe_uc_fw *uc_fw, const void *fw_data, size_t
>   	}
>   
>   	/* Get version numbers from the CSS header */
> -	release->major = FIELD_GET(CSS_SW_VERSION_UC_MAJOR, css->sw_version);
> -	release->minor = FIELD_GET(CSS_SW_VERSION_UC_MINOR, css->sw_version);
> -	release->patch = FIELD_GET(CSS_SW_VERSION_UC_PATCH, css->sw_version);
> +	release->major = FIELD_GET(CSS_SW_VERSION_UC_MAJOR, css->guc_info.sw_version);
> +	release->minor = FIELD_GET(CSS_SW_VERSION_UC_MINOR, css->guc_info.sw_version);
> +	release->patch = FIELD_GET(CSS_SW_VERSION_UC_PATCH, css->guc_info.sw_version);
>   
>   	if (uc_fw->type == XE_UC_FW_TYPE_GUC)
> -		return guc_read_css_info(uc_fw, css);
> +		return guc_read_css_info(uc_fw, &css->guc_info);
>   
>   	return 0;
>   }
> diff --git a/drivers/gpu/drm/xe/xe_uc_fw_abi.h b/drivers/gpu/drm/xe/xe_uc_fw_abi.h
> index 87ade41209d0..faceb437fd2f 100644
> --- a/drivers/gpu/drm/xe/xe_uc_fw_abi.h
> +++ b/drivers/gpu/drm/xe/xe_uc_fw_abi.h
> @@ -44,6 +44,39 @@
>    *    in fw. So driver will load a truncated firmware in this case.
>    */
>   
> +struct uc_css_rsa_info {
> +	u32 key_size_dw;
> +	u32 modulus_size_dw;
> +	u32 exponent_size_dw;
> +} __packed;
> +
> +struct uc_css_guc_info {
> +	u32 time;
> +#define CSS_TIME_HOUR				(0xFF << 0)
> +#define CSS_TIME_MIN				(0xFF << 8)
> +#define CSS_TIME_SEC				(0xFFFF << 16)
> +	u32 reserved0[5];
> +	u32 sw_version;
> +#define CSS_SW_VERSION_UC_MAJOR			(0xFF << 16)
> +#define CSS_SW_VERSION_UC_MINOR			(0xFF << 8)
> +#define CSS_SW_VERSION_UC_PATCH			(0xFF << 0)
> +	u32 submission_version;
> +	u32 reserved1[11];
> +	u32 header_info;
> +#define CSS_HEADER_INFO_SVN			(0xFF)
> +#define CSS_HEADER_INFO_COPY_VALID		(0x1 << 31)
> +	u32 private_data_size;
> +	u32 ukernel_info;
> +#define CSS_UKERNEL_INFO_DEVICEID		(0xFFFF << 16)
> +#define CSS_UKERNEL_INFO_PRODKEY		(0xFF << 8)
> +#define CSS_UKERNEL_INFO_BUILDTYPE		(0x3 << 2)
> +#define CSS_UKERNEL_INFO_BUILDTYPE_PROD		0
> +#define CSS_UKERNEL_INFO_BUILDTYPE_PREPROD	1
> +#define CSS_UKERNEL_INFO_BUILDTYPE_DEBUG	2
> +#define CSS_UKERNEL_INFO_ENCSTATUS		(0x1 << 1)
> +#define CSS_UKERNEL_INFO_COPY_VALID		(0x1 << 0)
> +} __packed;
> +
>   struct uc_css_header {
>   	u32 module_type;
>   	/*
> @@ -52,36 +85,21 @@ struct uc_css_header {
>   	 */
>   	u32 header_size_dw;
>   	u32 header_version;
> -	u32 module_id;
> +	u32 reserved0;
>   	u32 module_vendor;
>   	u32 date;
> -#define CSS_DATE_DAY			(0xFF << 0)
> -#define CSS_DATE_MONTH			(0xFF << 8)
> -#define CSS_DATE_YEAR			(0xFFFF << 16)
> +#define CSS_DATE_DAY				(0xFF << 0)
> +#define CSS_DATE_MONTH				(0xFF << 8)
> +#define CSS_DATE_YEAR				(0xFFFF << 16)
>   	u32 size_dw; /* uCode plus header_size_dw */
> -	u32 key_size_dw;
> -	u32 modulus_size_dw;
> -	u32 exponent_size_dw;
> -	u32 time;
> -#define CSS_TIME_HOUR			(0xFF << 0)
> -#define CSS_DATE_MIN			(0xFF << 8)
> -#define CSS_DATE_SEC			(0xFFFF << 16)
> -	char username[8];
> -	char buildnumber[12];
> -	u32 sw_version;
> -#define CSS_SW_VERSION_UC_MAJOR		(0xFF << 16)
> -#define CSS_SW_VERSION_UC_MINOR		(0xFF << 8)
> -#define CSS_SW_VERSION_UC_PATCH		(0xFF << 0)
>   	union {
> -		u32 submission_version; /* only applies to GuC */
> -		u32 reserved2;
> +		u32 reserved1[3];
> +		struct uc_css_rsa_info rsa_info;
>   	};
> -	u32 reserved0[12];
>   	union {
> -		u32 private_data_size; /* only applies to GuC */
> -		u32 reserved1;
> +		u32 reserved2[22];
> +		struct uc_css_guc_info guc_info;
>   	};
> -	u32 header_info;
>   } __packed;
>   static_assert(sizeof(struct uc_css_header) == 128);
>   

Re: [PATCH v2 4/4] drm/xe/guc: Add test for G2G communications

[Daniele Ceraolo Spurio]

On 8/5/2025 4:42 PM, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Add a test for sending messages from every GuC to every other GuC to
> test G2G communications.
>
> Note that, being a debug only feature, the test interface only exists
> in pre-production builds of the GuC firmware.
>
> v2: Fix 'default' case to actually use the driver's registration code
> as well as allocation. Add comments explaining the different test
> types. Fix (C) date and an assert. Review feedback from Daniele.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele

> ---
>   drivers/gpu/drm/xe/abi/guc_actions_abi.h    |   2 +
>   drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c  | 776 ++++++++++++++++++++
>   drivers/gpu/drm/xe/tests/xe_live_test_mod.c |   2 +
>   drivers/gpu/drm/xe/xe_device_types.h        |   7 +
>   drivers/gpu/drm/xe/xe_guc.c                 |   4 +
>   drivers/gpu/drm/xe/xe_guc.h                 |   4 +
>   drivers/gpu/drm/xe/xe_guc_ct.c              |   5 +
>   drivers/gpu/drm/xe/xe_guc_fwif.h            |   1 +
>   8 files changed, 801 insertions(+)
>   create mode 100644 drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c
>
> diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
> index 81eb046aeebf..0395998ca75c 100644
> --- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
> +++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
> @@ -154,6 +154,8 @@ enum xe_guc_action {
>   	XE_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE = 0x8003,
>   	XE_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED = 0x8004,
>   	XE_GUC_ACTION_NOTIFY_EXCEPTION = 0x8005,
> +	XE_GUC_ACTION_TEST_G2G_SEND = 0xF001,
> +	XE_GUC_ACTION_TEST_G2G_RECV = 0xF002,
>   	XE_GUC_ACTION_LIMIT
>   };
>   
> diff --git a/drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c b/drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c
> new file mode 100644
> index 000000000000..3b213fcae916
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/tests/xe_guc_g2g_test.c
> @@ -0,0 +1,776 @@
> +// SPDX-License-Identifier: GPL-2.0 AND MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#include <linux/delay.h>
> +
> +#include <kunit/test.h>
> +#include <kunit/visibility.h>
> +
> +#include "tests/xe_kunit_helpers.h"
> +#include "tests/xe_pci_test.h"
> +#include "tests/xe_test.h"
> +
> +#include "xe_bo.h"
> +#include "xe_device.h"
> +#include "xe_pm.h"
> +
> +/*
> + * There are different ways to allocate the G2G buffers. The plan for this test
> + * is to make sure that all the possible options work. The particular option
> + * chosen by the driver may vary from one platform to another, it may also change
> + * with time. So to ensure consistency of testing, the relevant driver code is
> + * replicated here to guarantee it won't change without the test being updated
> + * to keep testing the other options.
> + *
> + * In order to test the actual code being used by the driver, there is also the
> + * 'default' scheme. That will use the official driver routines to test whatever
> + * method the driver is using on the current platform at the current time.
> + */
> +enum {
> +	/* Driver defined allocation scheme */
> +	G2G_CTB_TYPE_DEFAULT,
> +	/* Single buffer in host memory */
> +	G2G_CTB_TYPE_HOST,
> +	/* Single buffer in a specific tile, loops across all tiles */
> +	G2G_CTB_TYPE_TILE,
> +};
> +
> +/*
> + * Payload is opaque to GuC. So KMD can define any structure or size it wants.
> + */
> +struct g2g_test_payload  {
> +	u32 tx_dev;
> +	u32 tx_tile;
> +	u32 rx_dev;
> +	u32 rx_tile;
> +	u32 seqno;
> +};
> +
> +static void g2g_test_send(struct kunit *test, struct xe_guc *guc,
> +			  u32 far_tile, u32 far_dev,
> +			  struct g2g_test_payload *payload)
> +{
> +	struct xe_device *xe = guc_to_xe(guc);
> +	struct xe_gt *gt = guc_to_gt(guc);
> +	u32 *action, total;
> +	size_t payload_len;
> +	int ret;
> +
> +	static_assert(IS_ALIGNED(sizeof(*payload), sizeof(u32)));
> +	payload_len = sizeof(*payload) / sizeof(u32);
> +
> +	total = 4 + payload_len;
> +	action = kunit_kmalloc_array(test, total, sizeof(*action), GFP_KERNEL);
> +	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, action);
> +
> +	action[0] = XE_GUC_ACTION_TEST_G2G_SEND;
> +	action[1] = far_tile;
> +	action[2] = far_dev;
> +	action[3] = payload_len;
> +	memcpy(action + 4, payload, payload_len * sizeof(u32));
> +
> +	atomic_inc(&xe->g2g_test_count);
> +
> +	/*
> +	 * Should specify the expected response notification here. Problem is that
> +	 * the response will be coming from a different GuC. By the end, it should
> +	 * all add up as long as an equal number of messages are sent from each GuC
> +	 * and to each GuC. However, in the middle negative reservation space errors
> +	 * and such like can occur. Rather than add intrusive changes to the CT layer
> +	 * it is simpler to just not bother counting it at all. The system should be
> +	 * idle when running the selftest, and the selftest's notification total size
> +	 * is well within the G2H allocation size. So there should be no issues with
> +	 * needing to block for space, which is all the tracking code is really for.
> +	 */
> +	ret = xe_guc_ct_send(&guc->ct, action, total, 0, 0);
> +	kunit_kfree(test, action);
> +	KUNIT_ASSERT_EQ_MSG(test, 0, ret, "G2G send failed: %d [%d:%d -> %d:%d]\n", ret,
> +			    gt_to_tile(gt)->id, G2G_DEV(gt), far_tile, far_dev);
> +}
> +
> +/*
> + * NB: Can't use KUNIT_ASSERT and friends in here as this is called asynchronously
> + * from the G2H notification handler. Need that to actually complete rather than
> + * thread-abort in order to keep the rest of the driver alive!
> + */
> +int xe_guc_g2g_test_notification(struct xe_guc *guc, u32 *msg, u32 len)
> +{
> +	struct xe_device *xe = guc_to_xe(guc);
> +	struct xe_gt *rx_gt = guc_to_gt(guc), *test_gt, *tx_gt = NULL;
> +	u32 tx_tile, tx_dev, rx_tile, rx_dev, idx, got_len;
> +	struct g2g_test_payload *payload;
> +	size_t payload_len;
> +	int ret = 0, i;
> +
> +	payload_len = sizeof(*payload) / sizeof(u32);
> +
> +	if (unlikely(len != (G2H_LEN_DW_G2G_NOTIFY_MIN + payload_len))) {
> +		xe_gt_err(rx_gt, "G2G test notification invalid length %u", len);
> +		ret = -EPROTO;
> +		goto done;
> +	}
> +
> +	tx_tile = msg[0];
> +	tx_dev = msg[1];
> +	got_len = msg[2];
> +	payload = (struct g2g_test_payload *)(msg + 3);
> +
> +	rx_tile = gt_to_tile(rx_gt)->id;
> +	rx_dev = G2G_DEV(rx_gt);
> +
> +	if (got_len != payload_len) {
> +		xe_gt_err(rx_gt, "G2G: Invalid payload length: %u vs %zu\n", got_len, payload_len);
> +		ret = -EPROTO;
> +		goto done;
> +	}
> +
> +	if (payload->tx_dev != tx_dev || payload->tx_tile != tx_tile ||
> +	    payload->rx_dev != rx_dev || payload->rx_tile != rx_tile) {
> +		xe_gt_err(rx_gt, "G2G: Invalid payload: %d:%d -> %d:%d vs %d:%d -> %d:%d! [%d]\n",
> +			  payload->tx_tile, payload->tx_dev, payload->rx_tile, payload->rx_dev,
> +			  tx_tile, tx_dev, rx_tile, rx_dev, payload->seqno);
> +		ret = -EPROTO;
> +		goto done;
> +	}
> +
> +	if (!xe->g2g_test_array) {
> +		xe_gt_err(rx_gt, "G2G: Missing test array!\n");
> +		ret = -ENOMEM;
> +		goto done;
> +	}
> +
> +	for_each_gt(test_gt, xe, i) {
> +		if (gt_to_tile(test_gt)->id != tx_tile)
> +			continue;
> +
> +		if (G2G_DEV(test_gt) != tx_dev)
> +			continue;
> +
> +		if (tx_gt) {
> +			xe_gt_err(rx_gt, "G2G: Got duplicate TX GTs: %d vs %d for %d:%d!\n",
> +				  tx_gt->info.id, test_gt->info.id, tx_tile, tx_dev);
> +			ret = -EINVAL;
> +			goto done;
> +		}
> +
> +		tx_gt = test_gt;
> +	}
> +	if (!tx_gt) {
> +		xe_gt_err(rx_gt, "G2G: Failed to find a TX GT for %d:%d!\n", tx_tile, tx_dev);
> +		ret = -EINVAL;
> +		goto done;
> +	}
> +
> +	idx = (tx_gt->info.id * xe->info.gt_count) + rx_gt->info.id;
> +
> +	if (xe->g2g_test_array[idx] != payload->seqno - 1) {
> +		xe_gt_err(rx_gt, "G2G: Seqno mismatch %d vs %d for %d:%d -> %d:%d!\n",
> +			  xe->g2g_test_array[idx], payload->seqno - 1,
> +			  tx_tile, tx_dev, rx_tile, rx_dev);
> +		ret = -EINVAL;
> +		goto done;
> +	}
> +
> +	xe->g2g_test_array[idx] = payload->seqno;
> +
> +done:
> +	atomic_dec(&xe->g2g_test_count);
> +	return ret;
> +}
> +
> +/*
> + * Send the given seqno from all GuCs to all other GuCs in tile/GT order
> + */
> +static void g2g_test_in_order(struct kunit *test, struct xe_device *xe, u32 seqno)
> +{
> +	struct xe_gt *near_gt, *far_gt;
> +	int i, j;
> +
> +	for_each_gt(near_gt, xe, i) {
> +		u32 near_tile = gt_to_tile(near_gt)->id;
> +		u32 near_dev = G2G_DEV(near_gt);
> +
> +		for_each_gt(far_gt, xe, j) {
> +			u32 far_tile = gt_to_tile(far_gt)->id;
> +			u32 far_dev = G2G_DEV(far_gt);
> +			struct g2g_test_payload payload;
> +
> +			if (far_gt->info.id == near_gt->info.id)
> +				continue;
> +
> +			payload.tx_dev = near_dev;
> +			payload.tx_tile = near_tile;
> +			payload.rx_dev = far_dev;
> +			payload.rx_tile = far_tile;
> +			payload.seqno = seqno;
> +			g2g_test_send(test, &near_gt->uc.guc, far_tile, far_dev, &payload);
> +		}
> +	}
> +}
> +
> +#define WAIT_TIME_MS	100
> +#define WAIT_COUNT	(1000 / WAIT_TIME_MS)
> +
> +static void g2g_wait_for_complete(void *_xe)
> +{
> +	struct xe_device *xe = (struct xe_device *)_xe;
> +	struct kunit *test = kunit_get_current_test();
> +	int wait = 0;
> +
> +	/* Wait for all G2H messages to be received */
> +	while (atomic_read(&xe->g2g_test_count)) {
> +		if (++wait > WAIT_COUNT)
> +			break;
> +
> +		msleep(WAIT_TIME_MS);
> +	}
> +
> +	KUNIT_ASSERT_EQ_MSG(test, 0, atomic_read(&xe->g2g_test_count),
> +			    "Timed out waiting for notifications\n");
> +	kunit_info(test, "Got all notifications back\n");
> +}
> +
> +#undef WAIT_TIME_MS
> +#undef WAIT_COUNT
> +
> +static void g2g_clean_array(void *_xe)
> +{
> +	struct xe_device *xe = (struct xe_device *)_xe;
> +
> +	xe->g2g_test_array = NULL;
> +}
> +
> +#define NUM_LOOPS	16
> +
> +static void g2g_run_test(struct kunit *test, struct xe_device *xe)
> +{
> +	u32 seqno, max_array;
> +	int ret, i, j;
> +
> +	max_array = xe->info.gt_count * xe->info.gt_count;
> +	xe->g2g_test_array = kunit_kcalloc(test, max_array, sizeof(u32), GFP_KERNEL);
> +	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, xe->g2g_test_array);
> +
> +	ret = kunit_add_action_or_reset(test, g2g_clean_array, xe);
> +	KUNIT_ASSERT_EQ_MSG(test, 0, ret, "Failed to register clean up action\n");
> +
> +	/*
> +	 * Send incrementing seqnos from all GuCs to all other GuCs in tile/GT order.
> +	 * Tile/GT order doesn't really mean anything to the hardware but it is going
> +	 * to be a fixed sequence every time.
> +	 *
> +	 * Verify that each one comes back having taken the correct route.
> +	 */
> +	ret = kunit_add_action(test, g2g_wait_for_complete, xe);
> +	KUNIT_ASSERT_EQ_MSG(test, 0, ret, "Failed to register clean up action\n");
> +	for (seqno = 1; seqno < NUM_LOOPS; seqno++)
> +		g2g_test_in_order(test, xe, seqno);
> +	seqno--;
> +
> +	kunit_release_action(test, &g2g_wait_for_complete, xe);
> +
> +	/* Check for the final seqno in each slot */
> +	for (i = 0; i < xe->info.gt_count; i++) {
> +		for (j = 0; j < xe->info.gt_count; j++) {
> +			u32 idx = (j * xe->info.gt_count) + i;
> +
> +			if (i == j)
> +				KUNIT_ASSERT_EQ_MSG(test, 0, xe->g2g_test_array[idx],
> +						    "identity seqno modified: %d for %dx%d!\n",
> +						    xe->g2g_test_array[idx], i, j);
> +			else
> +				KUNIT_ASSERT_EQ_MSG(test, seqno, xe->g2g_test_array[idx],
> +						    "invalid seqno: %d vs %d for %dx%d!\n",
> +						    xe->g2g_test_array[idx], seqno, i, j);
> +		}
> +	}
> +
> +	kunit_kfree(test, xe->g2g_test_array);
> +	kunit_release_action(test, &g2g_clean_array, xe);
> +
> +	kunit_info(test, "Test passed\n");
> +}
> +
> +#undef NUM_LOOPS
> +
> +static void g2g_ct_stop(struct xe_guc *guc)
> +{
> +	struct xe_gt *remote_gt, *gt = guc_to_gt(guc);
> +	struct xe_device *xe = gt_to_xe(gt);
> +	int i, t;
> +
> +	for_each_gt(remote_gt, xe, i) {
> +		u32 tile, dev;
> +
> +		if (remote_gt->info.id == gt->info.id)
> +			continue;
> +
> +		tile = gt_to_tile(remote_gt)->id;
> +		dev = G2G_DEV(remote_gt);
> +
> +		for (t = 0; t < XE_G2G_TYPE_LIMIT; t++)
> +			guc_g2g_deregister(guc, tile, dev, t);
> +	}
> +}
> +
> +/* Size of a single allocation that contains all G2G CTBs across all GTs */
> +static u32 g2g_ctb_size(struct kunit *test, struct xe_device *xe)
> +{
> +	unsigned int count = xe->info.gt_count;
> +	u32 num_channels = (count * (count - 1)) / 2;
> +
> +	kunit_info(test, "Size: (%d * %d / 2) * %d * 0x%08X + 0x%08X => 0x%08X [%d]\n",
> +		   count, count - 1, XE_G2G_TYPE_LIMIT, G2G_BUFFER_SIZE, G2G_DESC_AREA_SIZE,
> +		   num_channels * XE_G2G_TYPE_LIMIT * G2G_BUFFER_SIZE + G2G_DESC_AREA_SIZE,
> +		   num_channels * XE_G2G_TYPE_LIMIT);
> +
> +	return num_channels * XE_G2G_TYPE_LIMIT * G2G_BUFFER_SIZE + G2G_DESC_AREA_SIZE;
> +}
> +
> +/*
> + * Use the driver's regular CTB allocation scheme.
> + */
> +static void g2g_alloc_default(struct kunit *test, struct xe_device *xe)
> +{
> +	struct xe_gt *gt;
> +	int i;
> +
> +	kunit_info(test, "Default [tiles = %d, GTs = %d]\n",
> +		   xe->info.tile_count, xe->info.gt_count);
> +
> +	for_each_gt(gt, xe, i) {
> +		struct xe_guc *guc = &gt->uc.guc;
> +		int ret;
> +
> +		ret = guc_g2g_alloc(guc);
> +		KUNIT_ASSERT_EQ_MSG(test, 0, ret, "G2G alloc failed: %pe", ERR_PTR(ret));
> +		continue;
> +	}
> +}
> +
> +static void g2g_distribute(struct kunit *test, struct xe_device *xe, struct xe_bo *bo)
> +{
> +	struct xe_gt *root_gt, *gt;
> +	int i;
> +
> +	root_gt = xe_device_get_gt(xe, 0);
> +	root_gt->uc.guc.g2g.bo = bo;
> +	root_gt->uc.guc.g2g.owned = true;
> +	kunit_info(test, "[%d.%d] Assigned 0x%p\n", gt_to_tile(root_gt)->id, root_gt->info.id, bo);
> +
> +	for_each_gt(gt, xe, i) {
> +		if (gt->info.id != 0) {
> +			gt->uc.guc.g2g.owned = false;
> +			gt->uc.guc.g2g.bo = xe_bo_get(bo);
> +			kunit_info(test, "[%d.%d] Pinned 0x%p\n",
> +				   gt_to_tile(gt)->id, gt->info.id, gt->uc.guc.g2g.bo);
> +		}
> +
> +		KUNIT_ASSERT_NOT_ERR_OR_NULL(test, gt->uc.guc.g2g.bo);
> +	}
> +}
> +
> +/*
> + * Allocate a single blob on the host and split between all G2G CTBs.
> + */
> +static void g2g_alloc_host(struct kunit *test, struct xe_device *xe)
> +{
> +	struct xe_bo *bo;
> +	u32 g2g_size;
> +
> +	kunit_info(test, "Host [tiles = %d, GTs = %d]\n", xe->info.tile_count, xe->info.gt_count);
> +
> +	g2g_size = g2g_ctb_size(test, xe);
> +	bo = xe_managed_bo_create_pin_map(xe, xe_device_get_root_tile(xe), g2g_size,
> +					  XE_BO_FLAG_SYSTEM |
> +					  XE_BO_FLAG_GGTT |
> +					  XE_BO_FLAG_GGTT_ALL |
> +					  XE_BO_FLAG_GGTT_INVALIDATE);
> +	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, bo);
> +	kunit_info(test, "[HST] G2G buffer create: 0x%p\n", bo);
> +
> +	xe_map_memset(xe, &bo->vmap, 0, 0, g2g_size);
> +
> +	g2g_distribute(test, xe, bo);
> +}
> +
> +/*
> + * Allocate a single blob on the given tile and split between all G2G CTBs.
> + */
> +static void g2g_alloc_tile(struct kunit *test, struct xe_device *xe, struct xe_tile *tile)
> +{
> +	struct xe_bo *bo;
> +	u32 g2g_size;
> +
> +	KUNIT_ASSERT_TRUE(test, IS_DGFX(xe));
> +	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, tile);
> +
> +	kunit_info(test, "Tile %d [tiles = %d, GTs = %d]\n",
> +		   tile->id, xe->info.tile_count, xe->info.gt_count);
> +
> +	g2g_size = g2g_ctb_size(test, xe);
> +	bo = xe_managed_bo_create_pin_map(xe, tile, g2g_size,
> +					  XE_BO_FLAG_VRAM_IF_DGFX(tile) |
> +					  XE_BO_FLAG_GGTT |
> +					  XE_BO_FLAG_GGTT_ALL |
> +					  XE_BO_FLAG_GGTT_INVALIDATE);
> +	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, bo);
> +	kunit_info(test, "[%d.*] G2G buffer create: 0x%p\n", tile->id, bo);
> +
> +	xe_map_memset(xe, &bo->vmap, 0, 0, g2g_size);
> +
> +	g2g_distribute(test, xe, bo);
> +}
> +
> +static void g2g_free(struct kunit *test, struct xe_device *xe)
> +{
> +	struct xe_gt *gt;
> +	struct xe_bo *bo;
> +	int i;
> +
> +	for_each_gt(gt, xe, i) {
> +		bo = gt->uc.guc.g2g.bo;
> +		if (!bo)
> +			continue;
> +
> +		if (gt->uc.guc.g2g.owned) {
> +			xe_managed_bo_unpin_map_no_vm(bo);
> +			kunit_info(test, "[%d.%d] Unmapped 0x%p\n",
> +				   gt_to_tile(gt)->id, gt->info.id, bo);
> +		} else {
> +			xe_bo_put(bo);
> +			kunit_info(test, "[%d.%d] Unpinned 0x%p\n",
> +				   gt_to_tile(gt)->id, gt->info.id, bo);
> +		}
> +
> +		gt->uc.guc.g2g.bo = NULL;
> +	}
> +}
> +
> +static void g2g_stop(struct kunit *test, struct xe_device *xe)
> +{
> +	struct xe_gt *gt;
> +	int i;
> +
> +	for_each_gt(gt, xe, i) {
> +		struct xe_guc *guc = &gt->uc.guc;
> +
> +		if (!guc->g2g.bo)
> +			continue;
> +
> +		g2g_ct_stop(guc);
> +	}
> +
> +	g2g_free(test, xe);
> +}
> +
> +/*
> + * Generate a unique id for each bi-directional CTB for each pair of
> + * near and far tiles/devices. The id can then be used as an index into
> + * a single allocation that is sub-divided into multiple CTBs.
> + *
> + * For example, with two devices per tile and two tiles, the table should
> + * look like:
> + *           Far <tile>.<dev>
> + *         0.0   0.1   1.0   1.1
> + * N 0.0  --/-- 00/01 02/03 04/05
> + * e 0.1  01/00 --/-- 06/07 08/09
> + * a 1.0  03/02 07/06 --/-- 10/11
> + * r 1.1  05/04 09/08 11/10 --/--
> + *
> + * Where each entry is Rx/Tx channel id.
> + *
> + * So GuC #3 (tile 1, dev 1) talking to GuC #2 (tile 1, dev 0) would
> + * be reading from channel #11 and writing to channel #10. Whereas,
> + * GuC #2 talking to GuC #3 would be read on #10 and write to #11.
> + */
> +static int g2g_slot_flat(u32 near_tile, u32 near_dev, u32 far_tile, u32 far_dev,
> +			 u32 type, u32 max_inst, bool have_dev)
> +{
> +	u32 near = near_tile, far = far_tile;
> +	u32 idx = 0, x, y, direction;
> +	int i;
> +
> +	if (have_dev) {
> +		near = (near << 1) | near_dev;
> +		far = (far << 1) | far_dev;
> +	}
> +
> +	/* No need to send to one's self */
> +	if (far == near)
> +		return -1;
> +
> +	if (far > near) {
> +		/* Top right table half */
> +		x = far;
> +		y = near;
> +
> +		/* T/R is 'forwards' direction */
> +		direction = type;
> +	} else {
> +		/* Bottom left table half */
> +		x = near;
> +		y = far;
> +
> +		/* B/L is 'backwards' direction */
> +		direction = (1 - type);
> +	}
> +
> +	/* Count the rows prior to the target */
> +	for (i = y; i > 0; i--)
> +		idx += max_inst - i;
> +
> +	/* Count this row up to the target */
> +	idx += (x - 1 - y);
> +
> +	/* Slots are in Rx/Tx pairs */
> +	idx *= 2;
> +
> +	/* Pick Rx/Tx direction */
> +	idx += direction;
> +
> +	return idx;
> +}
> +
> +static int g2g_register_flat(struct xe_guc *guc, u32 far_tile, u32 far_dev, u32 type, bool have_dev)
> +{
> +	struct xe_gt *gt = guc_to_gt(guc);
> +	struct xe_device *xe = gt_to_xe(gt);
> +	u32 near_tile = gt_to_tile(gt)->id;
> +	u32 near_dev = G2G_DEV(gt);
> +	u32 max = xe->info.gt_count;
> +	int idx;
> +	u32 base, desc, buf;
> +
> +	if (!guc->g2g.bo)
> +		return -ENODEV;
> +
> +	idx = g2g_slot_flat(near_tile, near_dev, far_tile, far_dev, type, max, have_dev);
> +	xe_assert(xe, idx >= 0);
> +
> +	base = guc_bo_ggtt_addr(guc, guc->g2g.bo);
> +	desc = base + idx * G2G_DESC_SIZE;
> +	buf = base + idx * G2G_BUFFER_SIZE + G2G_DESC_AREA_SIZE;
> +
> +	xe_assert(xe, (desc - base + G2G_DESC_SIZE) <= G2G_DESC_AREA_SIZE);
> +	xe_assert(xe, (buf - base + G2G_BUFFER_SIZE) <= xe_bo_size(guc->g2g.bo));
> +
> +	return guc_action_register_g2g_buffer(guc, type, far_tile, far_dev,
> +					      desc, buf, G2G_BUFFER_SIZE);
> +}
> +
> +static void g2g_start(struct kunit *test, struct xe_guc *guc)
> +{
> +	struct xe_gt *remote_gt, *gt = guc_to_gt(guc);
> +	struct xe_device *xe = gt_to_xe(gt);
> +	unsigned int i;
> +	int t, ret;
> +	bool have_dev;
> +
> +	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, guc->g2g.bo);
> +
> +	/* GuC interface will need extending if more GT device types are ever created. */
> +	KUNIT_ASSERT_TRUE(test,
> +			  (gt->info.type == XE_GT_TYPE_MAIN) ||
> +			  (gt->info.type == XE_GT_TYPE_MEDIA));
> +
> +	/* Channel numbering depends on whether there are multiple GTs per tile */
> +	have_dev = xe->info.gt_count > xe->info.tile_count;
> +
> +	for_each_gt(remote_gt, xe, i) {
> +		u32 tile, dev;
> +
> +		if (remote_gt->info.id == gt->info.id)
> +			continue;
> +
> +		tile = gt_to_tile(remote_gt)->id;
> +		dev = G2G_DEV(remote_gt);
> +
> +		for (t = 0; t < XE_G2G_TYPE_LIMIT; t++) {
> +			ret = g2g_register_flat(guc, tile, dev, t, have_dev);
> +			KUNIT_ASSERT_EQ_MSG(test, 0, ret, "G2G register failed: %pe", ERR_PTR(ret));
> +		}
> +	}
> +}
> +
> +static void g2g_reinit(struct kunit *test, struct xe_device *xe, int ctb_type, struct xe_tile *tile)
> +{
> +	struct xe_gt *gt;
> +	int i, found = 0;
> +
> +	g2g_stop(test, xe);
> +
> +	for_each_gt(gt, xe, i) {
> +		struct xe_guc *guc = &gt->uc.guc;
> +
> +		KUNIT_ASSERT_NULL(test, guc->g2g.bo);
> +	}
> +
> +	switch (ctb_type) {
> +	case G2G_CTB_TYPE_DEFAULT:
> +		g2g_alloc_default(test, xe);
> +		break;
> +
> +	case G2G_CTB_TYPE_HOST:
> +		g2g_alloc_host(test, xe);
> +		break;
> +
> +	case G2G_CTB_TYPE_TILE:
> +		g2g_alloc_tile(test, xe, tile);
> +		break;
> +
> +	default:
> +		KUNIT_ASSERT_TRUE(test, false);
> +	}
> +
> +	for_each_gt(gt, xe, i) {
> +		struct xe_guc *guc = &gt->uc.guc;
> +
> +		if (!guc->g2g.bo)
> +			continue;
> +
> +		if (ctb_type == G2G_CTB_TYPE_DEFAULT)
> +			guc_g2g_start(guc);
> +		else
> +			g2g_start(test, guc);
> +		found++;
> +	}
> +
> +	KUNIT_ASSERT_GT_MSG(test, found, 1, "insufficient G2G channels running: %d", found);
> +
> +	kunit_info(test, "Testing across %d GTs\n", found);
> +}
> +
> +static void g2g_recreate_ctb(void *_xe)
> +{
> +	struct xe_device *xe = (struct xe_device *)_xe;
> +	struct kunit *test = kunit_get_current_test();
> +
> +	g2g_stop(test, xe);
> +
> +	if (xe_guc_g2g_wanted(xe))
> +		g2g_reinit(test, xe, G2G_CTB_TYPE_DEFAULT, NULL);
> +}
> +
> +static void g2g_pm_runtime_put(void *_xe)
> +{
> +	struct xe_device *xe = (struct xe_device *)_xe;
> +
> +	xe_pm_runtime_put(xe);
> +}
> +
> +static void g2g_pm_runtime_get(struct kunit *test)
> +{
> +	struct xe_device *xe = test->priv;
> +	int ret;
> +
> +	xe_pm_runtime_get(xe);
> +	ret = kunit_add_action_or_reset(test, g2g_pm_runtime_put, xe);
> +	KUNIT_ASSERT_EQ_MSG(test, 0, ret, "Failed to register runtime PM action\n");
> +}
> +
> +static void g2g_check_skip(struct kunit *test)
> +{
> +	struct xe_device *xe = test->priv;
> +	struct xe_gt *gt;
> +	int i;
> +
> +	if (IS_SRIOV_VF(xe))
> +		kunit_skip(test, "not supported from a VF");
> +
> +	if (xe->info.gt_count <= 1)
> +		kunit_skip(test, "not enough GTs");
> +
> +	for_each_gt(gt, xe, i) {
> +		struct xe_guc *guc = &gt->uc.guc;
> +
> +		if (guc->fw.build_type == CSS_UKERNEL_INFO_BUILDTYPE_PROD)
> +			kunit_skip(test,
> +				   "G2G test interface not available in production firmware builds\n");
> +	}
> +}
> +
> +/*
> + * Simple test that does not try to recreate the CTBs.
> + * Requires that the platform already enables G2G comms
> + * but has no risk of leaving the system in a broken state
> + * afterwards.
> + */
> +static void xe_live_guc_g2g_kunit_default(struct kunit *test)
> +{
> +	struct xe_device *xe = test->priv;
> +
> +	if (!xe_guc_g2g_wanted(xe))
> +		kunit_skip(test, "G2G not enabled");
> +
> +	g2g_check_skip(test);
> +
> +	g2g_pm_runtime_get(test);
> +
> +	kunit_info(test, "Testing default CTBs\n");
> +	g2g_run_test(test, xe);
> +
> +	kunit_release_action(test, &g2g_pm_runtime_put, xe);
> +}
> +
> +/*
> + * More complex test that re-creates the CTBs in various location to
> + * test access to each location from each GuC. Can be run even on
> + * systems that do not enable G2G by default. On the other hand,
> + * because it recreates the CTBs, if something goes wrong it could
> + * leave the system with broken G2G comms.
> + */
> +static void xe_live_guc_g2g_kunit_allmem(struct kunit *test)
> +{
> +	struct xe_device *xe = test->priv;
> +	int ret;
> +
> +	g2g_check_skip(test);
> +
> +	g2g_pm_runtime_get(test);
> +
> +	/* Make sure to leave the system as we found it */
> +	ret = kunit_add_action_or_reset(test, g2g_recreate_ctb, xe);
> +	KUNIT_ASSERT_EQ_MSG(test, 0, ret, "Failed to register CTB re-creation action\n");
> +
> +	kunit_info(test, "Testing CTB type 'default'...\n");
> +	g2g_reinit(test, xe, G2G_CTB_TYPE_DEFAULT, NULL);
> +	g2g_run_test(test, xe);
> +
> +	kunit_info(test, "Testing CTB type 'host'...\n");
> +	g2g_reinit(test, xe, G2G_CTB_TYPE_HOST, NULL);
> +	g2g_run_test(test, xe);
> +
> +	if (IS_DGFX(xe)) {
> +		struct xe_tile *tile;
> +		int id;
> +
> +		for_each_tile(tile, xe, id) {
> +			kunit_info(test, "Testing CTB type 'tile: #%d'...\n", id);
> +
> +			g2g_reinit(test, xe, G2G_CTB_TYPE_TILE, tile);
> +			g2g_run_test(test, xe);
> +		}
> +	} else {
> +		kunit_info(test, "Skipping local memory on integrated platform\n");
> +	}
> +
> +	kunit_release_action(test, g2g_recreate_ctb, xe);
> +	kunit_release_action(test, g2g_pm_runtime_put, xe);
> +}
> +
> +static struct kunit_case xe_guc_g2g_tests[] = {
> +	KUNIT_CASE_PARAM(xe_live_guc_g2g_kunit_default, xe_pci_live_device_gen_param),
> +	KUNIT_CASE_PARAM(xe_live_guc_g2g_kunit_allmem, xe_pci_live_device_gen_param),
> +	{}
> +};
> +
> +VISIBLE_IF_KUNIT
> +struct kunit_suite xe_guc_g2g_test_suite = {
> +	.name = "xe_guc_g2g",
> +	.test_cases = xe_guc_g2g_tests,
> +	.init = xe_kunit_helper_xe_device_live_test_init,
> +};
> +EXPORT_SYMBOL_IF_KUNIT(xe_guc_g2g_test_suite);
> diff --git a/drivers/gpu/drm/xe/tests/xe_live_test_mod.c b/drivers/gpu/drm/xe/tests/xe_live_test_mod.c
> index 81277c77016d..c55e46f1ae92 100644
> --- a/drivers/gpu/drm/xe/tests/xe_live_test_mod.c
> +++ b/drivers/gpu/drm/xe/tests/xe_live_test_mod.c
> @@ -10,12 +10,14 @@ extern struct kunit_suite xe_bo_shrink_test_suite;
>   extern struct kunit_suite xe_dma_buf_test_suite;
>   extern struct kunit_suite xe_migrate_test_suite;
>   extern struct kunit_suite xe_mocs_test_suite;
> +extern struct kunit_suite xe_guc_g2g_test_suite;
>   
>   kunit_test_suite(xe_bo_test_suite);
>   kunit_test_suite(xe_bo_shrink_test_suite);
>   kunit_test_suite(xe_dma_buf_test_suite);
>   kunit_test_suite(xe_migrate_test_suite);
>   kunit_test_suite(xe_mocs_test_suite);
> +kunit_test_suite(xe_guc_g2g_test_suite);
>   
>   MODULE_AUTHOR("Intel Corporation");
>   MODULE_LICENSE("GPL");
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 38c8329b4d2c..0416b0eba3bf 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -576,6 +576,13 @@ struct xe_device {
>   	atomic64_t global_total_pages;
>   #endif
>   
> +#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
> +	/** @g2g_test_array: for testing G2G communications */
> +	u32 *g2g_test_array;
> +	/** @g2g_test_count: for testing G2G communications */
> +	atomic_t g2g_test_count;
> +#endif
> +
>   	/* private: */
>   
>   #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index c49feb8ea0c3..aa2e9f761f8f 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -1688,3 +1688,7 @@ void xe_guc_declare_wedged(struct xe_guc *guc)
>   	xe_guc_ct_stop(&guc->ct);
>   	xe_guc_submit_wedge(guc);
>   }
> +
> +#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
> +#include "tests/xe_guc_g2g_test.c"
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h
> index 22cf019a11bf..1cca05967e62 100644
> --- a/drivers/gpu/drm/xe/xe_guc.h
> +++ b/drivers/gpu/drm/xe/xe_guc.h
> @@ -53,6 +53,10 @@ void xe_guc_stop(struct xe_guc *guc);
>   int xe_guc_start(struct xe_guc *guc);
>   void xe_guc_declare_wedged(struct xe_guc *guc);
>   
> +#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
> +int xe_guc_g2g_test_notification(struct xe_guc *guc, u32 *payload, u32 len);
> +#endif
> +
>   static inline u16 xe_engine_class_to_guc_class(enum xe_engine_class class)
>   {
>   	switch (class) {
> diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
> index 3f4e6a46ff16..f44967f84d30 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> @@ -1439,6 +1439,11 @@ static int process_g2h_msg(struct xe_guc_ct *ct, u32 *msg, u32 len)
>   	case XE_GUC_ACTION_NOTIFY_EXCEPTION:
>   		ret = guc_crash_process_msg(ct, action);
>   		break;
> +#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
> +	case XE_GUC_ACTION_TEST_G2G_RECV:
> +		ret = xe_guc_g2g_test_notification(guc, payload, adj_len);
> +		break;
> +#endif
>   	default:
>   		xe_gt_err(gt, "unexpected G2H action 0x%04x\n", action);
>   	}
> diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
> index ca9f999d38d1..bc94f8d0f037 100644
> --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> @@ -15,6 +15,7 @@
>   #define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET	4
>   #define G2H_LEN_DW_DEREGISTER_CONTEXT		3
>   #define G2H_LEN_DW_TLB_INVALIDATE		3
> +#define G2H_LEN_DW_G2G_NOTIFY_MIN		3
>   
>   #define GUC_ID_MAX			65535
>   #define GUC_ID_UNKNOWN			0xffffffff

Re: [PATCH v2 3/4] drm/xe: Allow freeing of a managed bo

[Daniele Ceraolo Spurio]

On 8/5/2025 4:42 PM, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> If a bo is created via xe_managed_bo_create_pin_map() then it cannot be
> freed by the driver using xe_bo_unpin_map_no_vm(), or indeed any other
> existing function. The DRM layer will still have a pointer stashed
> away for later freeing, causing a invalid memory access on driver
> unload. So add a helper for releasing the DRM action as well.
>
> v2: Drop 'xe' parameter (review feedbak from Michal W)
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
>   drivers/gpu/drm/xe/xe_bo.c | 5 +++++
>   drivers/gpu/drm/xe/xe_bo.h | 1 +
>   2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
> index ffca1cea5585..87aa0f5b2b2a 100644
> --- a/drivers/gpu/drm/xe/xe_bo.c
> +++ b/drivers/gpu/drm/xe/xe_bo.c
> @@ -2222,6 +2222,11 @@ struct xe_bo *xe_managed_bo_create_pin_map(struct xe_device *xe, struct xe_tile
>   	return bo;
>   }
>   
> +void xe_managed_bo_unpin_map_no_vm(struct xe_bo *bo)

Not sure if the "_no_vm" postfix is the best choice here, because all 
managed_bo operations are without vm. But maybe better to keep it for 
future-proofing, in case we have a vm-enabled version later?
Since I'm undecided myself I won't block on it.

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele

> +{
> +	devm_release_action(xe_bo_device(bo)->drm.dev, __xe_bo_unpin_map_no_vm, bo);
> +}
> +
>   struct xe_bo *xe_managed_bo_create_from_data(struct xe_device *xe, struct xe_tile *tile,
>   					     const void *data, size_t size, u32 flags)
>   {
> diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h
> index 8cce413b5235..298eef403505 100644
> --- a/drivers/gpu/drm/xe/xe_bo.h
> +++ b/drivers/gpu/drm/xe/xe_bo.h
> @@ -122,6 +122,7 @@ struct xe_bo *xe_bo_create_pin_map_at_aligned(struct xe_device *xe,
>   					      u64 alignment);
>   struct xe_bo *xe_managed_bo_create_pin_map(struct xe_device *xe, struct xe_tile *tile,
>   					   size_t size, u32 flags);
> +void xe_managed_bo_unpin_map_no_vm(struct xe_bo *bo);
>   struct xe_bo *xe_managed_bo_create_from_data(struct xe_device *xe, struct xe_tile *tile,
>   					     const void *data, size_t size, u32 flags);
>   int xe_managed_bo_reinit_in_vram(struct xe_device *xe, struct xe_tile *tile, struct xe_bo **src);