From: sashiko-bot@kernel.org
To: "Ankit Nautiyal" <ankit.k.nautiyal@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Subject: Re: [PATCH v2 02/56] drm/i915/hdmi: Add new data members for FRL configuration
Date: Mon, 12 Oct 2026 04:36:44 +0000 [thread overview]
Message-ID: <sashiko-outbox-167615@kernel.org> (raw)
In-Reply-To: <20261012035806.3361439-3-ankit.k.nautiyal@intel.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] drm: NULL pointer dereference in intel_bios_hdmi_max_frl_rate() via devdata
- [Medium] drm/i915: FRL rate incorrectly clamped to 0 when VBT specifies platform limit
--
commit 7ad38de828b7ee44dcbd47b61d9385aa21e165af
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
drm/i915/hdmi: Add new data members for FRL configuration
This commit adds new members to crtc_state and intel_hdmi to identify
FRL-supporting HDMI sinks. It also tracks the FRL training information
after a successful link training.
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index b6fa1a1558b82..69534eea78a15 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
[ ... ]
> @@ -2545,6 +2547,38 @@ intel_hdmi_dp_dual_mode_detect(struct drm_connector *_connector)
> }
> }
>
> +static void
> +intel_hdmi_reset_frl_config(struct intel_hdmi *intel_hdmi)
> +{
> + intel_hdmi->frl.trained = false;
> + intel_hdmi->frl.lanes = 0;
> + intel_hdmi->frl.rate_gbps = 0;
> + intel_hdmi->frl.ffe_level = 0;
> +}
> +
> +static void
> +intel_hdmi_init_frl_config(struct intel_connector *connector)
> +{
> + struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
> + struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
> + int max_src_frl_rate =
> + DIV_ROUND_UP(intel_bios_hdmi_max_frl_rate(encoder->devdata), 1000000) * 4;
[Severity: High]
Is there a risk of a NULL pointer dereference here?
When intel_hdmi_set_edid() detects a digital display, it calls
intel_hdmi_init_frl_config() which unconditionally evaluates encoder->devdata
in the call to intel_bios_hdmi_max_frl_rate().
However, the devdata field in struct intel_encoder is documented as:
/* VBT information for this encoder (may be NULL for older platforms) */
If devdata is NULL, intel_bios_hdmi_max_frl_rate() will immediately
dereference it:
int intel_bios_hdmi_max_frl_rate(const struct intel_bios_encoder_data *devdata)
{
struct intel_display *display = devdata->display;
...
Could this cause a crash upon connecting an HDMI display on platforms that
lack VBT port data?
> + int max_sink_dsc_frl_rate =
> + intel_hdmi_sink_dsc_max_frl_rate(&connector->base);
> + int max_sink_frl_rate =
> + intel_hdmi_sink_max_frl_rate(&connector->base);
> +
> + intel_hdmi->has_sink_hdmi_21 = max_sink_frl_rate > 0;
> +
> + intel_hdmi->max_frl_rate = min(max_sink_frl_rate,
> + max_src_frl_rate);
[Severity: Medium]
Does this clamp the maximum FRL rate to 0 Gbps for capable platforms?
When the VBT specifies HDMI_MAX_FRL_RATE_PLATFORM, or when no limit is
provided for platforms other than Meteorlake, intel_bios_hdmi_max_frl_rate()
returns 0.
This 0 value is converted to a max_src_frl_rate of 0, which is then passed
into this min() assignment. As a result, intel_hdmi->max_frl_rate becomes 0.
Will this unintentionally disable FRL on capable platforms that rely on the
default platform limit?
> +
> + intel_hdmi->max_dsc_frl_rate = min(max_sink_dsc_frl_rate,
> + max_src_frl_rate);
> +
> + intel_hdmi_reset_frl_config(intel_hdmi);
> +}
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=2
next prev parent reply other threads:[~2026-10-12 4:36 UTC|newest]
Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-12 3:57 [PATCH v2 00/56] Enable HDMI FRL for MTL+ Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 01/56] drm/i915/hdmi: Parse FRL max link rate from VBT Ankit Nautiyal
2026-10-12 4:34 ` sashiko-bot
2026-10-12 8:01 ` Shankar, Uma
2026-10-12 8:10 ` Shankar, Uma
2026-10-12 3:57 ` [PATCH v2 02/56] drm/i915/hdmi: Add new data members for FRL configuration Ankit Nautiyal
2026-10-12 4:36 ` sashiko-bot [this message]
2026-10-12 8:35 ` Shankar, Uma
2026-10-12 3:57 ` [PATCH v2 03/56] drm/i915/hdmi: Add FRL link rate cap Ankit Nautiyal
2026-10-12 8:43 ` Shankar, Uma
2026-10-12 3:57 ` [PATCH v2 04/56] drm/drm_scdc_helper: Add SCDC helper funcs for FRL Ankit Nautiyal
2026-10-12 4:32 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 05/56] drm/i915/display: Add registers for HDMI FRL configuration Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 06/56] drm/i915/display: Add new members in crtc_state for " Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 07/56] drm/i915/intel_cx0_phy_regs: Add HDMI FRL SHIFT EN bit in PORT_BUF_CTL_1 Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 08/56] drm/i915/ddi: Update Transcoder/DDI registers with the frl bits Ankit Nautiyal
2026-10-12 4:35 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 09/56] drm/i915/hdmi: Enable Scrambling only for TMDS mode Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 10/56] drm/i915/ddi: Simplify intel_ddi_enable() Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 11/56] drm/i915/ddi: Factor out common transcoder/vblank enable sequence Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 12/56] drm/i915/ddi: Update HDMI modeset sequence for MTL+ Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 13/56] drm/i915/hdmi: Add function to prepare registers for FRL mode Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 14/56] drm/i915/hdmi: Add functions for FRL training state machine Ankit Nautiyal
2026-10-12 4:49 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 15/56] drm/i915/intel_hdmi: Add helper to disable FRL Ankit Nautiyal
2026-10-12 4:44 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 16/56] drm/i915/hdmi: Reduce FRL rate cap on rate change during training Ankit Nautiyal
2026-10-12 4:47 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 17/56] drm/i915/hdmi: Introduce intel_hdmi_frl_level() for per-lane TxFFE Ankit Nautiyal
2026-10-12 4:49 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 18/56] drm/i915/hdmi: Drive per-lane TxFFE during FRL link training Ankit Nautiyal
2026-10-12 4:34 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 19/56] drm/i915/ltphy: Add PLL tables for HDMI FRL Ankit Nautiyal
2026-10-12 4:26 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 20/56] drm/i915/ltphy: Add safegaurd when calculation HDMI FRL state Ankit Nautiyal
2026-10-12 4:40 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 21/56] drm/i915/ltphy: Calculate port clock for HDMI FRL Ankit Nautiyal
2026-10-12 4:35 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 22/56] drm/i915/ltphy: Verify HDMI FRL tables Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 23/56] drm/i915/ddi_buf: Add Vswing table for HDMI FRL Ankit Nautiyal
2026-10-12 4:33 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 24/56] drm/i915/hdmi: Add provision for FRL mode while computing output format Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 25/56] drm/i915/cx0: Add helper to check if the FRL rate is valid Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 26/56] drm/i915/lt_phy: " Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 27/56] drm/i915/hdmi_frl_dfm_regs: Define DFM registers Ankit Nautiyal
2026-10-12 4:35 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 28/56] drm/i915/hdmi_frl_dfm: Define frl_dfm structure Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 29/56] drm/i915/hdmi_frl_dfm: Add non dsc frl capacity computation helpers Ankit Nautiyal
2026-10-12 4:48 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 30/56] drm/i915/hdmi_frl_dfm: Add support for DFM calculation with DSC Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 31/56] drm/i915/hdmi: Add helper to write FRL CFG register Ankit Nautiyal
2026-10-12 4:33 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 32/56] drm/i915/hdmi_frl_dfm: Add helpers to read/write FRL DFM registers Ankit Nautiyal
2026-10-12 4:42 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 33/56] drm/i915/hdmi: Rename port clock limit to specify tmds clock Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 34/56] drm/i915/hdmi: Rename port clock valid " Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 35/56] drm/i915/hdmi: Rename mode " Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 36/56] drm/i915/hdmi: Validate FRL modes in mode_valid using the FRL DFM Ankit Nautiyal
2026-10-12 4:49 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 37/56] drm/i915/hdmi: Add FRL port clock valid Ankit Nautiyal
2026-10-12 4:56 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 38/56] drm/i915/hdmi: Add FRL clock computation based on DFM Ankit Nautiyal
2026-10-12 4:51 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 39/56] drm/i915/hdmi: Add support for sending uevent to user for FRL training failure Ankit Nautiyal
2026-10-12 4:49 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 40/56] drm/i915/ddi: Wire FRL into the HDMI DDI enable/disable path Ankit Nautiyal
2026-10-12 4:54 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 41/56] drm/i915/ltphy: Fix HDMI FRL per-lane TX mapping Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 42/56] drm/i915/hdmi: Add read out for FRL state Ankit Nautiyal
2026-10-12 4:51 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 43/56] drm/i915/hdmi: Compute FRL Link M/N Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 44/56] drm/i915/hdmi_frl_dfm: Write and read back " Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 45/56] drm/i915/hdmi: Use the real pixel clock as crtc_clock for FRL Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 46/56] drm/i915/display: Add FRL members to the state checker Ankit Nautiyal
2026-10-12 4:54 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 47/56] drm/i915/hdmi: Compute output format for HDMI FRL mode Ankit Nautiyal
2026-10-12 4:53 ` sashiko-bot
2026-10-12 3:57 ` [PATCH v2 48/56] drm/i915/hdmi: Add a helper to check non DSC audio support for HDMI FRL Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 49/56] drm/i915/audio: Add the mode pruning logic " Ankit Nautiyal
2026-10-12 3:57 ` [PATCH v2 50/56] drm/i915/hdmi: Enable FRL based mode clock valid Ankit Nautiyal
2026-10-12 4:58 ` sashiko-bot
2026-10-12 3:58 ` [PATCH v2 51/56] drm/i915/joiner: Prepare to move joiner helpers to a new file Ankit Nautiyal
2026-10-12 3:58 ` [PATCH v2 52/56] drm/i915/joiner: Move joiner candidate helpers to intel_joiner.c Ankit Nautiyal
2026-10-12 3:58 ` [PATCH v2 53/56] drm/i915/joiner: Move joiner pipe mask helper " Ankit Nautiyal
2026-10-12 4:51 ` sashiko-bot
2026-10-12 3:58 ` [PATCH v2 54/56] drm/i915/hdmi: Iterate through joiner candidates in compute_config path Ankit Nautiyal
2026-10-12 3:58 ` [PATCH v2 55/56] drm/i915/hdmi: Iterate through joiner candidates in mode_valid path Ankit Nautiyal
2026-10-12 4:53 ` sashiko-bot
2026-10-12 3:58 ` [PATCH v2 56/56] drm/i915/hdmi: Allow Pipe joiner for HDMI Ankit Nautiyal
2026-10-12 5:01 ` sashiko-bot
2026-10-12 4:59 ` ✗ CI.checkpatch: warning for Enable HDMI FRL for MTL+ (rev2) Patchwork
2026-10-12 5:01 ` ✓ CI.KUnit: success " Patchwork
2026-10-12 5:41 ` ✓ Xe.CI.BAT: " Patchwork
2026-10-12 7:12 ` ✗ Xe.CI.FULL: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=sashiko-outbox-167615@kernel.org \
--to=sashiko-bot@kernel.org \
--cc=ankit.k.nautiyal@intel.com \
--cc=dri-devel@lists.freedesktop.org \
--cc=intel-gfx@lists.freedesktop.org \
--cc=intel-xe@lists.freedesktop.org \
--cc=sashiko-reviews@lists.linux.dev \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox