Re: [PATCH v2 50/56] drm/i915/hdmi: Enable FRL based mode clock valid

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/i915/hdmi: 4K120 4:2:0 bypasses FRL and fails via TMDS
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commit 4c023e7cde26d2644e793aa505b046a46b2d33ef
Author: Vandita Kulkarni <vandita.kulkarni@intel.com>

drm/i915/hdmi: Enable FRL based mode clock valid

Higher resolution modes like 8K@60, 4K@120 need FRL support. Platforms
before MTL do not support FRL, so allow modes requiring more than 600MHz
dotclock to be enumerated only on MTL+ where FRL is supported.

> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index c57d99195ed03..e3dbd71a3652e 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c

[ ... ]

> @@ -2176,12 +2179,10 @@ intel_hdmi_mode_valid(struct drm_connector *_connector,
>  	}
>  
>  	/*
> -	 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be
> -	 * enumerated only if FRL is supported. Current platforms do not support
> -	 * FRL so prune the higher resolution modes that require doctclock more
> -	 * than 600MHz.
> +	 * Platforms < MTL do not support FRL so prune the higher resolution
> +	 * modes that require doctclock more than 600MHz.
>  	 */
> -	if (clock > 600000)
> +	if (!intel_hdmi_can_support_frl(hdmi) && clock > 600000)
>  		return MODE_CLOCK_HIGH;

[Severity: High]
Does this allow high-bandwidth 4:2:0 modes to bypass FRL validation and
fail later during atomic commit?

By restricting the 600MHz dotclock limit to non-FRL platforms here,
dotclocks up to 1200MHz can reach format validation on FRL platforms.
However, when a mode like 4K@120Hz (1188MHz) in YCbCr 4:2:0 format reaches
intel_hdmi_mode_valid_format(), the TMDS clock check executes first:

intel_hdmi_mode_valid_format() {
    ...
    status = intel_hdmi_tmds_mode_clock_valid(&connector->base, clock,
                                              has_hdmi_sink, sink_format);

    if (status != MODE_OK && intel_hdmi_can_support_frl(hdmi))
        status = intel_hdmi_frl_mode_clock_valid(connector, mode,
                                                 sink_format);
    ...
}

For 4:2:0 formats, intel_hdmi_tmds_mode_clock_valid() halves the 1188MHz
dotclock to 594MHz, which successfully passes the TMDS limit check and
returns MODE_OK.

Since the status is MODE_OK, intel_hdmi_frl_mode_clock_valid() is
completely bypassed. The mode is incorrectly validated as TMDS instead of
FRL. Because TMDS configuration does not support pipe joiner, the single-pipe
dotclock limits will be exceeded during compute_config, causing the atomic
commit to fail for advertised modes.

>  
>  	if (drm_mode_is_420_only(info, mode)) {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=50