Re: [PATCH 2/3] drm/xe: Access MMIO after pcode init

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/xe: incomplete mmio deferral fix misses xe_wa_apply_tile_workarounds
--

commit a929401ac9f4b4d8f49c85fe7a5336571b384903
Author: Vinay Belgaumkar <vinay.belgaumkar@intel.com>

drm/xe: Access MMIO after pcode init

This commit delays MMIO space accesses during resume until after pcode
initialization is complete. It achieves this by moving xe_gt_idle_disable_c6()
after the call to xe_pcode_ready().

> diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c
> index daa7ba2df317a..1f5097875bcdf 100644
> --- a/drivers/gpu/drm/xe/xe_pm.c
> +++ b/drivers/gpu/drm/xe/xe_pm.c
> @@ -241,9 +241,6 @@ int xe_pm_resume(struct xe_device *xe)
>  	drm_dbg(&xe->drm, "Resuming device\n");
>  	trace_xe_pm_resume(xe, __builtin_return_address(0));
>  
> -	for_each_gt(gt, xe, id)
> -		xe_gt_idle_disable_c6(gt);
> -
>  	for_each_tile(tile, xe, id)
>  		xe_wa_apply_tile_workarounds(tile);

[Severity: High]
Does this code still access MMIO before pcode initialization completes?

The commit message indicates we shouldn't poke around the MMIO space during
resume before pcode init completes, but xe_wa_apply_tile_workarounds()
performs MMIO accesses via xe_mmio_rmw32() when applying workarounds:

drivers/gpu/drm/xe/xe_wa.c:xe_wa_apply_tile_workarounds() {
	...
	if (XE_DEVICE_WA(tile->xe, 22010954014))
		xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
}

Should the xe_wa_apply_tile_workarounds() call also be moved after
xe_pcode_ready() to fully prevent MMIO access before the synchronization
barrier?

>  
> @@ -251,6 +248,9 @@ int xe_pm_resume(struct xe_device *xe)
>  	if (err)
>  		return err;
>  
> +	for_each_gt(gt, xe, id)
> +		xe_gt_idle_disable_c6(gt);
> +
>  	xe_display_pm_resume_early(xe);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261015165451.154495-5-vinay.belgaumkar@intel.com?part=2