Re: [PATCH v6 04/11] drm/i915/dp_mst: Limit M/N ratio for MST

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/dp_mst: M/N mode_valid and compute_config_limits filter mismatch
--

commit 5b89059b3b94b9fbcca8f03ce951374211a9cdbc
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

drm/i915/dp_mst: Limit M/N ratio for MST

This commit adds a Link M/N ratio check to mst_connector_mode_valid_ctx()
using intel_dp_mode_valid_m_n() to prune modes whose pixel clock exceeds
the hardware Link M/N ratio limit across all link configurations.

> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 7023619aaaba9..f00edfb66a10a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -1565,6 +1565,11 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
>  					   min_link_bpp_x16,
>  					   bw_overhead_flags);
>  
> +	if (!intel_dp_mode_valid_m_n(intel_dp, mode->clock)) {
> +		*status = MODE_CLOCK_HIGH;
> +		return 0;
> +	}
> +
>  	/*
>  	 * TODO:
>  	 * - Also check if compression would allow for the mode

[Severity: Medium]
Could there be a mismatch here between how mst_connector_mode_valid_ctx()
validates the M/N ratio and how intel_dp_compute_config_limits() filters
link configurations for MST?

In drivers/gpu/drm/i915/display/intel_dp_mst.c,
mst_connector_mode_valid_ctx() checks link bandwidth solely against
max_bw_config, whereas intel_dp_mode_valid_m_n() iterates over all link
configurations in INTEL_DP_LINK_CAPS_FILTER_ALL:

drivers/gpu/drm/i915/display/intel_dp.c:intel_dp_mode_valid_m_n() {
	...
	intel_dp_link_caps_iter_start(&iter, intel_dp->link.caps, order,
				      INTEL_DP_LINK_CAPS_FILTER_ALL);
	for_each_dp_link_config(&iter, &link_config) {
		if (intel_dp_can_support_m_n(display, m_n_pixel_clock,
					     link_config.rate)) {
			found = true;

			break;
		}
	}
	...
}

However, during modeset via mst_stream_compute_config() ->
mst_stream_compute_link_for_joined_pipes() ->
mst_stream_compute_config_limits() -> intel_dp_compute_config_limits() in
drivers/gpu/drm/i915/display/intel_dp.c, the MST path narrows
limits->link_config_filter to the single unfiltered max_config before
calling intel_dp_compute_m_n_ratio_limits():

drivers/gpu/drm/i915/display/intel_dp.c:intel_dp_compute_config_limits() {
	...
	if (is_mst || intel_dp->use_max_params) {
		struct intel_dp_link_caps_filter new_filter = INTEL_DP_LINK_CAPS_FILTER_NONE;
		struct intel_dp_link_config max_config;
		...
		if (!intel_dp_get_connector_max_link_config(connector, limits, &max_config))
			return false;

		if (!intel_dp_link_caps_filter_add(link_caps, &new_filter, &max_config))
			return false;

		limits->link_config_filter = new_filter;
	}

	if (!intel_dp_compute_m_n_ratio_limits(intel_dp, conn_state, crtc_state, limits))
		return false;
	...
}

On a DP 2.x MST topology supporting both 128b/132b UHBR rates (where symbol
clock is rate * 10 / 32, e.g. 312.5 MHz for UHBR10 or 421.875 MHz for
UHBR13.5) and 8b/10b rates (where symbol clock is rate / 10, e.g. 810 MHz
for HBR3), a high-pixel-clock mode can exceed the M/N ratio limit at
max_bw_config (such as 4xUHBR10) while still passing
intel_dp_can_support_m_n() at HBR3.

Wouldn't that allow mst_connector_mode_valid_ctx() to return MODE_OK for a
mode that then fails atomic check in intel_dp_compute_config_limits() with
-EINVAL because only max_config was retained in limits->link_config_filter?
Should mst_connector_mode_valid_ctx() either check
intel_dp_can_support_m_n() against max_link_clock, or should
intel_dp_compute_m_n_ratio_limits() run before selecting max_config in
intel_dp_compute_config_limits()?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261021071401.1161586-1-suraj.kandpal@intel.com?part=4