[PATCH v4 00/10] Implement Wa_14021768792 to bypass m_n ratio limit

[PATCH v4 00/10] Implement Wa_14021768792 to bypass m_n ratio limit

[Suraj Kandpal]

For Platforms that support higher link rates, there is a limitation on
Link M /Link N ratio.
If the CEILING( Link M / Link N ) ratio is greater than 10.0, then
hardware cannot support the given resolution / refresh rate at the given
configuration.
For BMG Wa_14021768792 helps to bypass this limitation and allows it to
support the ratio till 15.0.

This series adds the missing restrictions for earlier platforms and adds
the Wa_14021768792 for BMG as per Bspec:49266

Ankit Nautiyal (8):
  drm/i915/display: Add helper to compute link M/N ratio for reuse
  drm/i915/dp_mst: Limit M/N ratio for MST
  drm/i915/dp: Add M/N ratio check for DP link config
  drm/i915/display: Add bits for link_n_extended for DISPLAY >= 14
  drm/i915/display_wa: Add support for Wa_14021768792
  drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10
  drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n
    ratio > 10
  drm/i915/dp: Extend intel_dp_can_support_m_n() for BMG M/N bypass

Suraj Kandpal (2):
  drm/i915/dp: Limit M/N ratio for DP SST
  drm/i915/dp: Bump the max Link M/N ratio to 22 for DISPLAY_VER >= 35

 drivers/gpu/drm/i915/display/intel_display.c  | 124 ++++++++++++-
 drivers/gpu/drm/i915/display/intel_display.h  |   4 +
 .../gpu/drm/i915/display/intel_display_regs.h |  12 ++
 .../drm/i915/display/intel_display_types.h    |   2 +
 .../gpu/drm/i915/display/intel_display_wa.c   |   9 +
 .../gpu/drm/i915/display/intel_display_wa.h   |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 172 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   6 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   7 +
 9 files changed, 326 insertions(+), 11 deletions(-)

-- 
2.34.1

[PATCH v4 01/10] drm/i915/display: Add helper to compute link M/N ratio for reuse

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Introduce intel_display_compute_link_m_n() to compute the link M/N ratio
from the pixel clock and the link symbol clock. This logic was
previously embedded within intel_link_compute_m_n().

The new helper allows reuse of link M/N computation in other contexts
without requiring the full data M/N calculation.

No functional changes intended.

v2:
- Rename function (Jani)
- The link symbol clock is passed in rather than derived here, so that the
DP specific conversion from the link rate stays with the caller. (Jani)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9151ea6c15ab..f04a6f97e05a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2641,13 +2641,20 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
 	intel_reduce_m_n_ratio(ret_m, ret_n);
 }
 
+static void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
+					   int pixel_clock, int link_symbol_clock)
+{
+	compute_m_n(link_m, link_n,
+		    pixel_clock, link_symbol_clock,
+		    0x80000);
+}
+
 void
 intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
 		       int pixel_clock, int link_clock,
 		       int bw_overhead,
 		       struct intel_link_m_n *m_n)
 {
-	u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock);
 	u32 data_m = intel_dp_effective_data_rate(pixel_clock, bits_per_pixel_x16,
 						  bw_overhead);
 	u32 data_n = drm_dp_max_dprx_data_rate(link_clock, nlanes);
@@ -2664,9 +2671,9 @@ intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
 		    data_m, data_n,
 		    0x8000000);
 
-	compute_m_n(&m_n->link_m, &m_n->link_n,
-		    pixel_clock, link_symbol_clock,
-		    0x80000);
+	intel_display_compute_link_m_n(&m_n->link_m, &m_n->link_n,
+				       pixel_clock,
+				       intel_dp_link_symbol_clock(link_clock));
 }
 
 void intel_panel_sanitize_ssc(struct intel_display *display)
-- 
2.34.1

RE: [PATCH v4 01/10] drm/i915/display: Add helper to compute link M/N ratio for reuse

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Suraj
> Kandpal
> Sent: 17 September 2026 10:37
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: [PATCH v4 01/10] drm/i915/display: Add helper to compute link M/N
> ratio for reuse
> 
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> 
> Introduce intel_display_compute_link_m_n() to compute the link M/N ratio from
> the pixel clock and the link symbol clock. This logic was previously embedded
> within intel_link_compute_m_n().
> 
> The new helper allows reuse of link M/N computation in other contexts without
> requiring the full data M/N calculation.

The commit says this helper is for reuse, but it remains static with no caller added, please either
explain the intended upcoming user in the commit message or make the helper non-static when
the caller is introduced.

> 
> No functional changes intended.
> 
> v2:
> - Rename function (Jani)
> - The link symbol clock is passed in rather than derived here, so that the DP
> specific conversion from the link rate stays with the caller. (Jani)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++++----
>  1 file changed, 11 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 9151ea6c15ab..f04a6f97e05a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2641,13 +2641,20 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
>  	intel_reduce_m_n_ratio(ret_m, ret_n);
>  }
> 
> +static void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
> +					   int pixel_clock, int link_symbol_clock)
> {
> +	compute_m_n(link_m, link_n,
> +		    pixel_clock, link_symbol_clock,
> +		    0x80000);


Since this helper may be reused elsewhere, please document here that the fixed N is intentional 
and follows the Windows/BIOS M/N requirement.

> +}
> +
>  void
>  intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
>  		       int pixel_clock, int link_clock,
>  		       int bw_overhead,
>  		       struct intel_link_m_n *m_n)
>  {
> -	u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock);
>  	u32 data_m = intel_dp_effective_data_rate(pixel_clock,
> bits_per_pixel_x16,
>  						  bw_overhead);
>  	u32 data_n = drm_dp_max_dprx_data_rate(link_clock, nlanes); @@ -
> 2664,9 +2671,9 @@ intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
>  		    data_m, data_n,
>  		    0x8000000);
> 
> -	compute_m_n(&m_n->link_m, &m_n->link_n,
> -		    pixel_clock, link_symbol_clock,
> -		    0x80000);
> +	intel_display_compute_link_m_n(&m_n->link_m, &m_n->link_n,
> +				       pixel_clock,
> +				       intel_dp_link_symbol_clock(link_clock));

With mentioned changes addressed,
LGTM
Reviewed-by: Mitul Golani<mitulkumar.ajitkumar.golani@intel.com>

>  }
> 
>  void intel_panel_sanitize_ssc(struct intel_display *display)
> --
> 2.34.1

RE: [PATCH v4 01/10] drm/i915/display: Add helper to compute link M/N ratio for reuse

[Kandpal, Suraj]

> 
> 
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> > Suraj Kandpal
> > Sent: 17 September 2026 10:37
> > To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> > <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> > Subject: [PATCH v4 01/10] drm/i915/display: Add helper to compute link
> > M/N ratio for reuse
> >
> > From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >
> > Introduce intel_display_compute_link_m_n() to compute the link M/N
> > ratio from the pixel clock and the link symbol clock. This logic was
> > previously embedded within intel_link_compute_m_n().
> >
> > The new helper allows reuse of link M/N computation in other contexts
> > without requiring the full data M/N calculation.
> 
> The commit says this helper is for reuse, but it remains static with no caller added,
> please either explain the intended upcoming user in the commit message or make
> the helper non-static when the caller is introduced.

We don't mention in the commit message that this function will be used says in the 4th patch of this patch series.
We have already mentioned that this will be reused later on . I can however add that this function will be used in later commits.


> 
> >
> > No functional changes intended.
> >
> > v2:
> > - Rename function (Jani)
> > - The link symbol clock is passed in rather than derived here, so that
> > the DP specific conversion from the link rate stays with the caller.
> > (Jani)
> >
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++++----
> >  1 file changed, 11 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 9151ea6c15ab..f04a6f97e05a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -2641,13 +2641,20 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
> >  	intel_reduce_m_n_ratio(ret_m, ret_n);  }
> >
> > +static void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
> > +					   int pixel_clock, int link_symbol_clock)
> > {
> > +	compute_m_n(link_m, link_n,
> > +		    pixel_clock, link_symbol_clock,
> > +		    0x80000);
> 
> 
> Since this helper may be reused elsewhere, please document here that the fixed
> N is intentional and follows the Windows/BIOS M/N requirement.

We really don't want to document this here in this commit seeing as this was not documented where it was previously called
Either and this commit only moves that call into a helper function. Other wise we will end up with a lot of unnecessary documentation
In code which is not required.
Ankit Nautiyal what do you think ?

Regards,
Suraj Kandpal
> 
> > +}
> > +
> >  void
> >  intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
> >  		       int pixel_clock, int link_clock,
> >  		       int bw_overhead,
> >  		       struct intel_link_m_n *m_n)
> >  {
> > -	u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock);
> >  	u32 data_m = intel_dp_effective_data_rate(pixel_clock,
> > bits_per_pixel_x16,
> >  						  bw_overhead);
> >  	u32 data_n = drm_dp_max_dprx_data_rate(link_clock, nlanes); @@ -
> > 2664,9 +2671,9 @@ intel_link_compute_m_n(u16 bits_per_pixel_x16, int
> nlanes,
> >  		    data_m, data_n,
> >  		    0x8000000);
> >
> > -	compute_m_n(&m_n->link_m, &m_n->link_n,
> > -		    pixel_clock, link_symbol_clock,
> > -		    0x80000);
> > +	intel_display_compute_link_m_n(&m_n->link_m, &m_n->link_n,
> > +				       pixel_clock,
> > +				       intel_dp_link_symbol_clock(link_clock));
> 
> With mentioned changes addressed,
> LGTM
> Reviewed-by: Mitul Golani<mitulkumar.ajitkumar.golani@intel.com>
> 
> >  }
> >
> >  void intel_panel_sanitize_ssc(struct intel_display *display)
> > --
> > 2.34.1

[PATCH v4 02/10] drm/i915/dp: Limit M/N ratio for DP SST

[Suraj Kandpal]

The hardware cannot support DisplayPort configurations where the
ceiling of the Link M/Link N ratio exceeds the limit the transcoder's
timing generator DDA can track. This limitation has always existed, but
it typically wasn't encountered without the use of joiners and DSC.

With higher resolutions and combinations involving joiners and DSC,
this constraint can now be hit in certain scenarios.

Restrict the link configurations to those satisfying the constraint
while computing the link config limits, so that the SST and the MST
paths both get it, and so that a mode which no link rate can support
fails early rather than deep inside link config selection.

Also prune such modes in mode_valid. Note the ratio is the pixel clock
over the link symbol clock, and the symbol clock is not monotonic in the
link rate: it is the rate divided by 32 for 128b/132b but only by 10 for
8b/10b, so e.g. HBR3 has a higher symbol clock than UHBR20. There is
therefore no single best link rate to evaluate against, and mode_valid
walks the link configurations instead, only rejecting the mode if none
of them can satisfy the ratio.

Note: This change applies the check only for SST. Support for MST will
be added in a subsequent commit.

v2:
-Move the M/N ratio check to the link rate configuration phase instead
of during M/N computation. (Ville)
-Prune modes that cannot be supported even with highest link rate due to
M/N ratio restriction.
v3:
-Rebase on the link caps iterator based link config selection.
-Set the constraint up in intel_dp_compute_config_limits() by narrowing
the link config filter, and fail there if no config qualifies, instead
of skipping configs while iterating them. (Imre)
-Use a limit of 4 on DG2. (Wa_14014191401)
-Walk the link configurations in mode_valid rather than evaluating the
ratio at the highest link rate, which is not the best case for it.
v4:
-Add iterator for all dp configs in intel_dp_mode_valid_m_n() so
that we do not prune any mode that could have been supported (Sashiko)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |   4 +-
 drivers/gpu/drm/i915/display/intel_display.h |   2 +
 drivers/gpu/drm/i915/display/intel_dp.c      | 101 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h      |   2 +
 4 files changed, 107 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f04a6f97e05a..c53163d7c082 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2641,8 +2641,8 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
 	intel_reduce_m_n_ratio(ret_m, ret_n);
 }
 
-static void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
-					   int pixel_clock, int link_symbol_clock)
+void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
+				    int pixel_clock, int link_symbol_clock)
 {
 	compute_m_n(link_m, link_n,
 		    pixel_clock, link_symbol_clock,
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index eecafff167d3..404168f4213b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -523,5 +523,7 @@ bool assert_port_valid(struct intel_display *display, enum port port);
 
 bool intel_scanout_needs_vtd_wa(struct intel_display *display);
 int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
+void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
+				    int pixel_clock, int link_symbol_clock);
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0cd5e6b5034c..f6a2152c4432 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -61,6 +61,7 @@
 #include "intel_cx0_phy.h"
 #include "intel_ddi.h"
 #include "intel_de.h"
+#include "intel_display.h"
 #include "intel_display_driver.h"
 #include "intel_display_jiffies.h"
 #include "intel_display_utils.h"
@@ -1265,6 +1266,34 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
 	return true;
 }
 
+static int
+intel_dp_get_max_m_n_ratio(struct intel_display *display)
+{
+	if (display->platform.dg2)
+		return 4;
+
+	return 10;
+}
+
+static bool
+intel_dp_can_support_m_n(struct intel_display *display,
+			 int pixel_clock, int link_rate)
+{
+	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
+	u32 link_m, link_n;
+	int m_n_ratio;
+
+	intel_display_compute_link_m_n(&link_m, &link_n, pixel_clock,
+				       intel_dp_link_symbol_clock(link_rate));
+
+	if (!link_n)
+		return true;
+
+	m_n_ratio = DIV_ROUND_UP(link_m, link_n);
+
+	return m_n_ratio <= max_m_n_ratio;
+}
+
 static
 bool intel_dp_can_join(struct intel_dp *intel_dp,
 		       int num_joined_pipes)
@@ -1300,6 +1329,31 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
 	return target_clock <= effective_dotclk_limit;
 }
 
+bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	struct intel_dp_link_caps_order order = {
+		.key = INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE,
+		.dir = INTEL_DP_LINK_CAPS_ORDER_DIR_DESC,
+	};
+	struct intel_dp_link_config link_config;
+	struct intel_dp_link_caps_iter iter;
+	bool found = false;
+
+	intel_dp_link_caps_iter_start(&iter, intel_dp->link.caps, order,
+				      INTEL_DP_LINK_CAPS_FILTER_ALL);
+	for_each_dp_link_config(&iter, &link_config) {
+		if (intel_dp_can_support_m_n(display, pixel_clock, link_config.rate)) {
+			found = true;
+
+			break;
+		}
+	}
+	intel_dp_link_caps_iter_end(&iter);
+
+	return found;
+}
+
 static enum drm_mode_status
 intel_dp_mode_valid_format(struct intel_connector *connector,
 			   const struct drm_display_mode *mode,
@@ -1454,6 +1508,9 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 			return status;
 	}
 
+	if (!intel_dp_mode_valid_m_n(intel_dp, target_clock))
+		return MODE_CLOCK_HIGH;
+
 	/*
 	 * TODO: Even when using a 4:2:0 sink_format intel_dp_output_format()
 	 * will always choose a 4:4:4 output_format if the DFP can do the
@@ -2654,6 +2711,47 @@ intel_dp_dsc_compute_pipe_bpp_limits(struct intel_connector *connector,
 	return true;
 }
 
+static bool
+intel_dp_compute_m_n_ratio_limits(struct intel_dp *intel_dp,
+				  struct drm_connector_state *conn_state,
+				  const struct intel_crtc_state *crtc_state,
+				  struct link_config_limits *limits)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
+	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
+	struct intel_dp_link_caps_order order =
+		intel_dp_link_caps_connector_compute_order(connector);
+	struct intel_dp_link_caps_filter new_filter = INTEL_DP_LINK_CAPS_FILTER_NONE;
+	int pixel_clock = intel_dp_mode_clock(crtc_state, conn_state);
+	struct intel_dp_link_config link_config;
+	struct intel_dp_link_caps_iter iter;
+	bool found = false;
+
+	intel_dp_link_caps_iter_start(&iter, link_caps, order, limits->link_config_filter);
+	for_each_dp_link_config(&iter, &link_config) {
+		if (!intel_dp_can_support_m_n(display, pixel_clock, link_config.rate))
+			continue;
+
+		intel_dp_link_caps_filter_add(link_caps, &new_filter, &link_config);
+		found = true;
+	}
+	intel_dp_link_caps_iter_end(&iter);
+
+	if (!found) {
+		drm_dbg_kms(display->drm,
+			    "[CONNECTOR:%d:%s] No link config with a Link M/N ratio <= %d\n",
+			    connector->base.base.id, connector->base.name,
+			    intel_dp_get_max_m_n_ratio(display));
+
+		return false;
+	}
+
+	limits->link_config_filter = new_filter;
+
+	return true;
+}
+
 bool
 intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 			       struct drm_connector_state *conn_state,
@@ -2770,6 +2868,9 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 		limits->link_config_filter = new_filter;
 	}
 
+	if (!intel_dp_compute_m_n_ratio_limits(intel_dp, conn_state, crtc_state, limits))
+		return false;
+
 	if (!intel_dp_test_compute_config(connector, crtc_state, limits))
 		return false;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 04fae203bb69..aa58833a405b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -239,6 +239,8 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
 
 u8 intel_dp_as_sdp_transmission_time(void);
 
+bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock);
+
 int intel_dp_link_init(struct intel_dp *intel_dp);
 void intel_dp_link_cleanup(struct intel_dp *intel_dp);
 
-- 
2.34.1

RE: [PATCH v4 02/10] drm/i915/dp: Limit M/N ratio for DP SST

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Suraj
> Kandpal
> Sent: 17 September 2026 10:37
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: [PATCH v4 02/10] drm/i915/dp: Limit M/N ratio for DP SST
> 
> The hardware cannot support DisplayPort configurations where the ceiling of
> the Link M/Link N ratio exceeds the limit the transcoder's timing generator
> DDA can track. This limitation has always existed, but it typically wasn't
> encountered without the use of joiners and DSC.
> 
> With higher resolutions and combinations involving joiners and DSC, this
> constraint can now be hit in certain scenarios.
> 
> Restrict the link configurations to those satisfying the constraint while
> computing the link config limits, so that the SST and the MST paths both get
> it, and so that a mode which no link rate can support fails early rather than
> deep inside link config selection.

Nit: This check is inside intel_dp_compute_config_limits, which mst_stream_compute_config_limits also calls, so MST compute is already constrained. The subject ("for DP SST") and the "applies only for SST" note contradict that and the "SST and MST paths both get it" sentence. Please say that MST compute is covered and only MST mode_valid is left for the follow-up.

> 
> Also prune such modes in mode_valid. Note the ratio is the pixel clock over
> the link symbol clock, and the symbol clock is not monotonic in the link rate: it
> is the rate divided by 32 for 128b/132b but only by 10 for 8b/10b, so e.g.
> HBR3 has a higher symbol clock than UHBR20. There is therefore no single
> best link rate to evaluate against, and mode_valid walks the link
> configurations instead, only rejecting the mode if none of them can satisfy
> the ratio.
> 
> Note: This change applies the check only for SST. Support for MST will be
> added in a subsequent commit.
> 
> v2:
> -Move the M/N ratio check to the link rate configuration phase instead of
> during M/N computation. (Ville) -Prune modes that cannot be supported
> even with highest link rate due to M/N ratio restriction.
> v3:
> -Rebase on the link caps iterator based link config selection.
> -Set the constraint up in intel_dp_compute_config_limits() by narrowing the
> link config filter, and fail there if no config qualifies, instead of skipping
> configs while iterating them. (Imre) -Use a limit of 4 on DG2.
> (Wa_14014191401) -Walk the link configurations in mode_valid rather than
> evaluating the ratio at the highest link rate, which is not the best case for it.
> v4:
> -Add iterator for all dp configs in intel_dp_mode_valid_m_n() so that we do
> not prune any mode that could have been supported (Sashiko)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |   4 +-
>  drivers/gpu/drm/i915/display/intel_display.h |   2 +
>  drivers/gpu/drm/i915/display/intel_dp.c      | 101 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dp.h      |   2 +
>  4 files changed, 107 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f04a6f97e05a..c53163d7c082 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2641,8 +2641,8 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
>  	intel_reduce_m_n_ratio(ret_m, ret_n);
>  }
> 
> -static void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
> -					   int pixel_clock, int
> link_symbol_clock)
> +void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
> +				    int pixel_clock, int link_symbol_clock)
>  {
>  	compute_m_n(link_m, link_n,
>  		    pixel_clock, link_symbol_clock,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index eecafff167d3..404168f4213b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -523,5 +523,7 @@ bool assert_port_valid(struct intel_display *display,
> enum port port);
> 
>  bool intel_scanout_needs_vtd_wa(struct intel_display *display);  int
> intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
> +void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
> +				    int pixel_clock, int link_symbol_clock);
> 
>  #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0cd5e6b5034c..f6a2152c4432 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -61,6 +61,7 @@
>  #include "intel_cx0_phy.h"
>  #include "intel_ddi.h"
>  #include "intel_de.h"
> +#include "intel_display.h"
>  #include "intel_display_driver.h"
>  #include "intel_display_jiffies.h"
>  #include "intel_display_utils.h"
> @@ -1265,6 +1266,34 @@ bool intel_dp_has_dsc(const struct
> intel_connector *connector)
>  	return true;
>  }
> 
> +static int
> +intel_dp_get_max_m_n_ratio(struct intel_display *display) {
> +	if (display->platform.dg2)
> +		return 4;

Please route the DG2 limit through intel_display_wa() (INTEL_DISPLAY_WA_14014191401) instead of a bare platform check. Right now the Wa ID only appears in the changelog.

> +
> +	return 10;

Also, what's the BSpec reference for the generic limit of 10 ?
> +}
> +
> +static bool
> +intel_dp_can_support_m_n(struct intel_display *display,
> +			 int pixel_clock, int link_rate)
> +{
> +	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
> +	u32 link_m, link_n;
> +	int m_n_ratio;
> +
> +	intel_display_compute_link_m_n(&link_m, &link_n, pixel_clock,
> +				       intel_dp_link_symbol_clock(link_rate));
> +
> +	if (!link_n)
> +		return true;

link_n can't be 0 here: compute_m_n() fixes N at 0x80000 and only halves it while M/N exceed 24 bits. Please drop the check.

> +
> +	m_n_ratio = DIV_ROUND_UP(link_m, link_n);
> +
> +	return m_n_ratio <= max_m_n_ratio;
> +}
> +
>  static
>  bool intel_dp_can_join(struct intel_dp *intel_dp,
>  		       int num_joined_pipes)
> @@ -1300,6 +1329,31 @@ bool intel_dp_dotclk_valid(struct intel_display
> *display,
>  	return target_clock <= effective_dotclk_limit;  }
> 
> +bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int
> +pixel_clock) {
> +	struct intel_display *display = to_intel_display(intel_dp);
> +	struct intel_dp_link_caps_order order = {
> +		.key = INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE,
> +		.dir = INTEL_DP_LINK_CAPS_ORDER_DIR_DESC,
> +	};
> +	struct intel_dp_link_config link_config;
> +	struct intel_dp_link_caps_iter iter;
> +	bool found = false;
> +
> +	intel_dp_link_caps_iter_start(&iter, intel_dp->link.caps, order,
> +				      INTEL_DP_LINK_CAPS_FILTER_ALL);
> +	for_each_dp_link_config(&iter, &link_config) {
> +		if (intel_dp_can_support_m_n(display, pixel_clock,
> link_config.rate)) {
> +			found = true;
> +
> +			break;
> +		}
> +	}
> +	intel_dp_link_caps_iter_end(&iter);
> +
> +	return found;
> +}
> +
>  static enum drm_mode_status
>  intel_dp_mode_valid_format(struct intel_connector *connector,
>  			   const struct drm_display_mode *mode, @@ -
> 1454,6 +1508,9 @@ intel_dp_mode_valid(struct drm_connector
> *_connector,
>  			return status;
>  	}
> 
> +	if (!intel_dp_mode_valid_m_n(intel_dp, target_clock))
> +		return MODE_CLOCK_HIGH;
> +
>  	/*
>  	 * TODO: Even when using a 4:2:0 sink_format
> intel_dp_output_format()
>  	 * will always choose a 4:4:4 output_format if the DFP can do the @@
> -2654,6 +2711,47 @@ intel_dp_dsc_compute_pipe_bpp_limits(struct
> intel_connector *connector,
>  	return true;
>  }
> 
> +static bool
> +intel_dp_compute_m_n_ratio_limits(struct intel_dp *intel_dp,
> +				  struct drm_connector_state *conn_state,
> +				  const struct intel_crtc_state *crtc_state,
> +				  struct link_config_limits *limits) {
> +	struct intel_display *display = to_intel_display(intel_dp);
> +	struct intel_connector *connector = to_intel_connector(conn_state-
> >connector);
> +	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
> +	struct intel_dp_link_caps_order order =
> +		intel_dp_link_caps_connector_compute_order(connector);
> +	struct intel_dp_link_caps_filter new_filter =
> INTEL_DP_LINK_CAPS_FILTER_NONE;
> +	int pixel_clock = intel_dp_mode_clock(crtc_state, conn_state);
> +	struct intel_dp_link_config link_config;
> +	struct intel_dp_link_caps_iter iter;
> +	bool found = false;
> +
> +	intel_dp_link_caps_iter_start(&iter, link_caps, order, limits-
> >link_config_filter);
> +	for_each_dp_link_config(&iter, &link_config) {
> +		if (!intel_dp_can_support_m_n(display, pixel_clock,
> link_config.rate))
> +			continue;
> +
> +		intel_dp_link_caps_filter_add(link_caps, &new_filter,
> &link_config);
> +		found = true;
> +	}
> +	intel_dp_link_caps_iter_end(&iter);
> +
> +	if (!found) {
> +		drm_dbg_kms(display->drm,
> +			    "[CONNECTOR:%d:%s] No link config with a Link
> M/N ratio <= %d\n",
> +			    connector->base.base.id, connector->base.name,
> +			    intel_dp_get_max_m_n_ratio(display));
> +
> +		return false;
> +	}
> +
> +	limits->link_config_filter = new_filter;
> +
> +	return true;
> +}
> +
>  bool
>  intel_dp_compute_config_limits(struct intel_dp *intel_dp,
>  			       struct drm_connector_state *conn_state, @@ -
> 2770,6 +2868,9 @@ intel_dp_compute_config_limits(struct intel_dp
> *intel_dp,
>  		limits->link_config_filter = new_filter;
>  	}
> 
> +	if (!intel_dp_compute_m_n_ratio_limits(intel_dp, conn_state,
> crtc_state, limits))
> +		return false;

For MSO (eDP splitter) this uses the unsplit clock, while the programmed link M/N uses crtc_clock / mso_link_count (computed later in intel_dp_compute_config()). Does the DDA limit apply to the per-segment clock? If so, the check is too strict by a factor of mso_link_count.

> +
>  	if (!intel_dp_test_compute_config(connector, crtc_state, limits))
>  		return false;
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 04fae203bb69..aa58833a405b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -239,6 +239,8 @@ bool intel_dp_joiner_candidate_valid(struct
> intel_connector *connector,
> 
>  u8 intel_dp_as_sdp_transmission_time(void);
> 
> +bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int
> +pixel_clock);

nit: This is only used in intel_dp.c. Make it static unless the MST follow-up needs it, and if it does, say so.

> +
>  int intel_dp_link_init(struct intel_dp *intel_dp);  void
> intel_dp_link_cleanup(struct intel_dp *intel_dp);
> 
> --
> 2.34.1

RE: [PATCH v4 02/10] drm/i915/dp: Limit M/N ratio for DP SST

[Kandpal, Suraj]

> > Subject: [PATCH v4 02/10] drm/i915/dp: Limit M/N ratio for DP SST
> >
> > The hardware cannot support DisplayPort configurations where the
> > ceiling of the Link M/Link N ratio exceeds the limit the transcoder's
> > timing generator DDA can track. This limitation has always existed,
> > but it typically wasn't encountered without the use of joiners and DSC.
> >
> > With higher resolutions and combinations involving joiners and DSC,
> > this constraint can now be hit in certain scenarios.
> >
> > Restrict the link configurations to those satisfying the constraint
> > while computing the link config limits, so that the SST and the MST
> > paths both get it, and so that a mode which no link rate can support
> > fails early rather than deep inside link config selection.
> 
> Nit: This check is inside intel_dp_compute_config_limits, which
> mst_stream_compute_config_limits also calls, so MST compute is already
> constrained. The subject ("for DP SST") and the "applies only for SST" note
> contradict that and the "SST and MST paths both get it" sentence. Please say
> that MST compute is covered and only MST mode_valid is left for the follow-
> up.

Sure will update the commit message

> 
> >
> > Also prune such modes in mode_valid. Note the ratio is the pixel clock
> > over the link symbol clock, and the symbol clock is not monotonic in
> > the link rate: it is the rate divided by 32 for 128b/132b but only by 10 for
> 8b/10b, so e.g.
> > HBR3 has a higher symbol clock than UHBR20. There is therefore no
> > single best link rate to evaluate against, and mode_valid walks the
> > link configurations instead, only rejecting the mode if none of them
> > can satisfy the ratio.
> >
> > Note: This change applies the check only for SST. Support for MST will
> > be added in a subsequent commit.
> >
> > v2:
> > -Move the M/N ratio check to the link rate configuration phase instead
> > of during M/N computation. (Ville) -Prune modes that cannot be
> > supported even with highest link rate due to M/N ratio restriction.
> > v3:
> > -Rebase on the link caps iterator based link config selection.
> > -Set the constraint up in intel_dp_compute_config_limits() by
> > narrowing the link config filter, and fail there if no config
> > qualifies, instead of skipping configs while iterating them. (Imre) -Use a
> limit of 4 on DG2.
> > (Wa_14014191401) -Walk the link configurations in mode_valid rather
> > than evaluating the ratio at the highest link rate, which is not the best case
> for it.
> > v4:
> > -Add iterator for all dp configs in intel_dp_mode_valid_m_n() so that
> > we do not prune any mode that could have been supported (Sashiko)
> >
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c |   4 +-
> >  drivers/gpu/drm/i915/display/intel_display.h |   2 +
> >  drivers/gpu/drm/i915/display/intel_dp.c      | 101 +++++++++++++++++++
> >  drivers/gpu/drm/i915/display/intel_dp.h      |   2 +
> >  4 files changed, 107 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index f04a6f97e05a..c53163d7c082 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -2641,8 +2641,8 @@ static void compute_m_n(u32 *ret_m, u32
> *ret_n,
> >  	intel_reduce_m_n_ratio(ret_m, ret_n);  }
> >
> > -static void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
> > -					   int pixel_clock, int
> > link_symbol_clock)
> > +void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
> > +				    int pixel_clock, int link_symbol_clock)
> >  {
> >  	compute_m_n(link_m, link_n,
> >  		    pixel_clock, link_symbol_clock, diff --git
> > a/drivers/gpu/drm/i915/display/intel_display.h
> > b/drivers/gpu/drm/i915/display/intel_display.h
> > index eecafff167d3..404168f4213b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > @@ -523,5 +523,7 @@ bool assert_port_valid(struct intel_display
> > *display, enum port port);
> >
> >  bool intel_scanout_needs_vtd_wa(struct intel_display *display);  int
> > intel_crtc_num_joined_pipes(const struct intel_crtc_state
> > *crtc_state);
> > +void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
> > +				    int pixel_clock, int link_symbol_clock);
> >
> >  #endif
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 0cd5e6b5034c..f6a2152c4432 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -61,6 +61,7 @@
> >  #include "intel_cx0_phy.h"
> >  #include "intel_ddi.h"
> >  #include "intel_de.h"
> > +#include "intel_display.h"
> >  #include "intel_display_driver.h"
> >  #include "intel_display_jiffies.h"
> >  #include "intel_display_utils.h"
> > @@ -1265,6 +1266,34 @@ bool intel_dp_has_dsc(const struct
> > intel_connector *connector)
> >  	return true;
> >  }
> >
> > +static int
> > +intel_dp_get_max_m_n_ratio(struct intel_display *display) {
> > +	if (display->platform.dg2)
> > +		return 4;
> 
> Please route the DG2 limit through intel_display_wa()
> (INTEL_DISPLAY_WA_14014191401) instead of a bare platform check. Right
> now the Wa ID only appears in the changelog.
> 

Ill add a seprarte patch series moving this into its own display wa framework rather than doing it here
Since this series is already adding a WA

> > +
> > +	return 10;
> 
> Also, what's the BSpec reference for the generic limit of 10 ?

Will add it

> > +}
> > +
> > +static bool
> > +intel_dp_can_support_m_n(struct intel_display *display,
> > +			 int pixel_clock, int link_rate)
> > +{
> > +	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
> > +	u32 link_m, link_n;
> > +	int m_n_ratio;
> > +
> > +	intel_display_compute_link_m_n(&link_m, &link_n, pixel_clock,
> > +				       intel_dp_link_symbol_clock(link_rate));
> > +
> > +	if (!link_n)
> > +		return true;
> 
> link_n can't be 0 here: compute_m_n() fixes N at 0x80000 and only halves it
> while M/N exceed 24 bits. Please drop the check.

Will drop it

> 
> > +
> > +	m_n_ratio = DIV_ROUND_UP(link_m, link_n);
> > +
> > +	return m_n_ratio <= max_m_n_ratio;
> > +}
> > +
> >  static
> >  bool intel_dp_can_join(struct intel_dp *intel_dp,
> >  		       int num_joined_pipes)
> > @@ -1300,6 +1329,31 @@ bool intel_dp_dotclk_valid(struct intel_display
> > *display,
> >  	return target_clock <= effective_dotclk_limit;  }
> >
> > +bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int
> > +pixel_clock) {
> > +	struct intel_display *display = to_intel_display(intel_dp);
> > +	struct intel_dp_link_caps_order order = {
> > +		.key = INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE,
> > +		.dir = INTEL_DP_LINK_CAPS_ORDER_DIR_DESC,
> > +	};
> > +	struct intel_dp_link_config link_config;
> > +	struct intel_dp_link_caps_iter iter;
> > +	bool found = false;
> > +
> > +	intel_dp_link_caps_iter_start(&iter, intel_dp->link.caps, order,
> > +				      INTEL_DP_LINK_CAPS_FILTER_ALL);
> > +	for_each_dp_link_config(&iter, &link_config) {
> > +		if (intel_dp_can_support_m_n(display, pixel_clock,
> > link_config.rate)) {
> > +			found = true;
> > +
> > +			break;
> > +		}
> > +	}
> > +	intel_dp_link_caps_iter_end(&iter);
> > +
> > +	return found;
> > +}
> > +
> >  static enum drm_mode_status
> >  intel_dp_mode_valid_format(struct intel_connector *connector,
> >  			   const struct drm_display_mode *mode, @@ -
> > 1454,6 +1508,9 @@ intel_dp_mode_valid(struct drm_connector
> > *_connector,
> >  			return status;
> >  	}
> >
> > +	if (!intel_dp_mode_valid_m_n(intel_dp, target_clock))
> > +		return MODE_CLOCK_HIGH;
> > +
> >  	/*
> >  	 * TODO: Even when using a 4:2:0 sink_format
> > intel_dp_output_format()
> >  	 * will always choose a 4:4:4 output_format if the DFP can do the
> @@
> > -2654,6 +2711,47 @@ intel_dp_dsc_compute_pipe_bpp_limits(struct
> > intel_connector *connector,
> >  	return true;
> >  }
> >
> > +static bool
> > +intel_dp_compute_m_n_ratio_limits(struct intel_dp *intel_dp,
> > +				  struct drm_connector_state *conn_state,
> > +				  const struct intel_crtc_state *crtc_state,
> > +				  struct link_config_limits *limits) {
> > +	struct intel_display *display = to_intel_display(intel_dp);
> > +	struct intel_connector *connector = to_intel_connector(conn_state-
> > >connector);
> > +	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
> > +	struct intel_dp_link_caps_order order =
> > +		intel_dp_link_caps_connector_compute_order(connector);
> > +	struct intel_dp_link_caps_filter new_filter =
> > INTEL_DP_LINK_CAPS_FILTER_NONE;
> > +	int pixel_clock = intel_dp_mode_clock(crtc_state, conn_state);
> > +	struct intel_dp_link_config link_config;
> > +	struct intel_dp_link_caps_iter iter;
> > +	bool found = false;
> > +
> > +	intel_dp_link_caps_iter_start(&iter, link_caps, order, limits-
> > >link_config_filter);
> > +	for_each_dp_link_config(&iter, &link_config) {
> > +		if (!intel_dp_can_support_m_n(display, pixel_clock,
> > link_config.rate))
> > +			continue;
> > +
> > +		intel_dp_link_caps_filter_add(link_caps, &new_filter,
> > &link_config);
> > +		found = true;
> > +	}
> > +	intel_dp_link_caps_iter_end(&iter);
> > +
> > +	if (!found) {
> > +		drm_dbg_kms(display->drm,
> > +			    "[CONNECTOR:%d:%s] No link config with a Link
> > M/N ratio <= %d\n",
> > +			    connector->base.base.id, connector->base.name,
> > +			    intel_dp_get_max_m_n_ratio(display));
> > +
> > +		return false;
> > +	}
> > +
> > +	limits->link_config_filter = new_filter;
> > +
> > +	return true;
> > +}
> > +
> >  bool
> >  intel_dp_compute_config_limits(struct intel_dp *intel_dp,
> >  			       struct drm_connector_state *conn_state, @@ -
> > 2770,6 +2868,9 @@ intel_dp_compute_config_limits(struct intel_dp
> > *intel_dp,
> >  		limits->link_config_filter = new_filter;
> >  	}
> >
> > +	if (!intel_dp_compute_m_n_ratio_limits(intel_dp, conn_state,
> > crtc_state, limits))
> > +		return false;
> 
> For MSO (eDP splitter) this uses the unsplit clock, while the programmed link
> M/N uses crtc_clock / mso_link_count (computed later in
> intel_dp_compute_config()). Does the DDA limit apply to the per-segment
> clock? If so, the check is too strict by a factor of mso_link_count.

We use unsplit clock here and switch to using mso clock later in patch 4 so its not a problem.

> 
> > +
> >  	if (!intel_dp_test_compute_config(connector, crtc_state, limits))
> >  		return false;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> > b/drivers/gpu/drm/i915/display/intel_dp.h
> > index 04fae203bb69..aa58833a405b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -239,6 +239,8 @@ bool intel_dp_joiner_candidate_valid(struct
> > intel_connector *connector,
> >
> >  u8 intel_dp_as_sdp_transmission_time(void);
> >
> > +bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int
> > +pixel_clock);
> 
> nit: This is only used in intel_dp.c. Make it static unless the MST follow-up
> needs it, and if it does, say so.

This is used in a later commit . will mention in commit message

Regards,
Suraj Kandpal

> 
> > +
> >  int intel_dp_link_init(struct intel_dp *intel_dp);  void
> > intel_dp_link_cleanup(struct intel_dp *intel_dp);
> >
> > --
> > 2.34.1

[PATCH v4 03/10] drm/i915/dp_mst: Limit M/N ratio for MST

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

The hardware does not support DisplayPort configurations where the
ceiling of the Link M/Link N ratio exceeds the limit. Enforce this
constraint for MST as well.

The compute config path needs no change: MST goes through
intel_dp_compute_config_limits() too, so the link config filter set up
there already excludes the configurations violating the ratio limit, and
MST fails there if none is left.

What is still missing is pruning such modes, so add the check to
mst_connector_mode_valid_ctx(), reusing the helper the SST mode_valid
uses. It walks the link configurations and only rejects the mode if none
of them can satisfy the ratio, rather than evaluating it at a single
link rate.

v2:
-Drop the checks in the MST link config helpers, redundant now that the
constraint is applied while computing the link config limits. (Imre)
-Share the mode_valid helper with SST instead of evaluating the ratio at
one link rate, since the link symbol clock is not monotonic in the link
rate and there is no single best case configuration.
v3:
-Now that intel_dp_mode_valid_m_n checks for all configs just call
that (Sashiko)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 0c362784afe4..823fe99ca0a1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1565,6 +1565,11 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 					   min_link_bpp_x16,
 					   bw_overhead_flags);
 
+	if (!intel_dp_mode_valid_m_n(intel_dp, mode->clock)) {
+		*status = MODE_CLOCK_HIGH;
+		return 0;
+	}
+
 	/*
 	 * TODO:
 	 * - Also check if compression would allow for the mode
-- 
2.34.1

RE: [PATCH v4 03/10] drm/i915/dp_mst: Limit M/N ratio for MST

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Suraj
> Kandpal
> Sent: 17 September 2026 10:37
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: [PATCH v4 03/10] drm/i915/dp_mst: Limit M/N ratio for MST
> 
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> 
> The hardware does not support DisplayPort configurations where the ceiling
> of the Link M/Link N ratio exceeds the limit. Enforce this constraint for MST as
> well.
> 
> The compute config path needs no change: MST goes through
> intel_dp_compute_config_limits() too, so the link config filter set up there
> already excludes the configurations violating the ratio limit, and MST fails
> there if none is left.
> 
> What is still missing is pruning such modes, so add the check to
> mst_connector_mode_valid_ctx(), reusing the helper the SST mode_valid
> uses. It walks the link configurations and only rejects the mode if none of
> them can satisfy the ratio, rather than evaluating it at a single link rate.
> 
> v2:
> -Drop the checks in the MST link config helpers, redundant now that the
> constraint is applied while computing the link config limits. (Imre) -Share the
> mode_valid helper with SST instead of evaluating the ratio at one link rate,
> since the link symbol clock is not monotonic in the link rate and there is no
> single best case configuration.
> v3:
> -Now that intel_dp_mode_valid_m_n checks for all configs just call that
> (Sashiko)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 0c362784afe4..823fe99ca0a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -1565,6 +1565,11 @@ mst_connector_mode_valid_ctx(struct
> drm_connector *_connector,
>  					   min_link_bpp_x16,
>  					   bw_overhead_flags);
> 
> +	if (!intel_dp_mode_valid_m_n(intel_dp, mode->clock)) {
> +		*status = MODE_CLOCK_HIGH;
> +		return 0;
> +	}

Since MST appears to use only the max_bw_config for link configuration, should the M/N ratio check in
mode_valid also be performed against that configuration's max_link_clock? Currently, intel_dp_mode_valid_m_n
accepts the mode if any allowed config passes the ratio check.

For example, on DG2 with a UHBR10 MST link, could a ~1.3 GHz stream pass the check using HBR3 but later fail
during config computation because MST uses UHBR10, which does not satisfy the ratio limit? If so, should the
validation use the same link configuration that MST will actually use?

> +
>  	/*
>  	 * TODO:
>  	 * - Also check if compression would allow for the mode
> --
> 2.34.1

RE: [PATCH v4 03/10] drm/i915/dp_mst: Limit M/N ratio for MST

[Kandpal, Suraj]

> -----Original Message-----
> From: Golani, Mitulkumar Ajitkumar
> <mitulkumar.ajitkumar.golani@intel.com>
> Sent: 15 October 2026 22:59
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: RE: [PATCH v4 03/10] drm/i915/dp_mst: Limit M/N ratio for MST
> 
> 
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> > Suraj Kandpal
> > Sent: 17 September 2026 10:37
> > To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> > <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> > Subject: [PATCH v4 03/10] drm/i915/dp_mst: Limit M/N ratio for MST
> >
> > From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >
> > The hardware does not support DisplayPort configurations where the
> > ceiling of the Link M/Link N ratio exceeds the limit. Enforce this
> > constraint for MST as well.
> >
> > The compute config path needs no change: MST goes through
> > intel_dp_compute_config_limits() too, so the link config filter set up
> > there already excludes the configurations violating the ratio limit,
> > and MST fails there if none is left.
> >
> > What is still missing is pruning such modes, so add the check to
> > mst_connector_mode_valid_ctx(), reusing the helper the SST mode_valid
> > uses. It walks the link configurations and only rejects the mode if
> > none of them can satisfy the ratio, rather than evaluating it at a single link
> rate.
> >
> > v2:
> > -Drop the checks in the MST link config helpers, redundant now that
> > the constraint is applied while computing the link config limits.
> > (Imre) -Share the mode_valid helper with SST instead of evaluating the
> > ratio at one link rate, since the link symbol clock is not monotonic
> > in the link rate and there is no single best case configuration.
> > v3:
> > -Now that intel_dp_mode_valid_m_n checks for all configs just call
> > that
> > (Sashiko)
> >
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 0c362784afe4..823fe99ca0a1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -1565,6 +1565,11 @@ mst_connector_mode_valid_ctx(struct
> > drm_connector *_connector,
> >  					   min_link_bpp_x16,
> >  					   bw_overhead_flags);
> >
> > +	if (!intel_dp_mode_valid_m_n(intel_dp, mode->clock)) {
> > +		*status = MODE_CLOCK_HIGH;
> > +		return 0;
> > +	}
> 
> Since MST appears to use only the max_bw_config for link configuration,
> should the M/N ratio check in mode_valid also be performed against that
> configuration's max_link_clock? Currently, intel_dp_mode_valid_m_n
> accepts the mode if any allowed config passes the ratio check.
> 
> For example, on DG2 with a UHBR10 MST link, could a ~1.3 GHz stream pass
> the check using HBR3 but later fail during config computation because MST
> uses UHBR10, which does not satisfy the ratio limit? If so, should the
> validation use the same link configuration that MST will actually use?

Lets start with DG2 does not have UHBR to begin with.
Also compute doesn't actually use max_bw_config. MST goes through
intel_dp_compute_config_limits() too, so configs that fail the ratio are already
filtered out and it picks from what's left. In your example it'd just use HBR3 instead of failing (DG2 has no UHBR anyway).
For mode_valid I didn't want to check only max_bw_config, since the symbol clock
isn't monotonic in link rate and a lower rate can pass where the max one fails.
If something slips through, compute still does the exact check.

Regards,
Suraj Kandpal

> 
> > +
> >  	/*
> >  	 * TODO:
> >  	 * - Also check if compression would allow for the mode
> > --
> > 2.34.1

RE: [PATCH v4 03/10] drm/i915/dp_mst: Limit M/N ratio for MST

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: 21 October 2026 10:39
> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
> intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>
> Subject: RE: [PATCH v4 03/10] drm/i915/dp_mst: Limit M/N ratio for MST
> 
> 
> 
> > -----Original Message-----
> > From: Golani, Mitulkumar Ajitkumar
> > <mitulkumar.ajitkumar.golani@intel.com>
> > Sent: 15 October 2026 22:59
> > To: Kandpal, Suraj <suraj.kandpal@intel.com>;
> > intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> > <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> > Subject: RE: [PATCH v4 03/10] drm/i915/dp_mst: Limit M/N ratio for MST
> >
> >
> >
> > > -----Original Message-----
> > > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> > > Of Suraj Kandpal
> > > Sent: 17 September 2026 10:37
> > > To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> > > <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> > > Subject: [PATCH v4 03/10] drm/i915/dp_mst: Limit M/N ratio for MST
> > >
> > > From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > >
> > > The hardware does not support DisplayPort configurations where the
> > > ceiling of the Link M/Link N ratio exceeds the limit. Enforce this
> > > constraint for MST as well.
> > >
> > > The compute config path needs no change: MST goes through
> > > intel_dp_compute_config_limits() too, so the link config filter set
> > > up there already excludes the configurations violating the ratio
> > > limit, and MST fails there if none is left.
> > >
> > > What is still missing is pruning such modes, so add the check to
> > > mst_connector_mode_valid_ctx(), reusing the helper the SST
> > > mode_valid uses. It walks the link configurations and only rejects
> > > the mode if none of them can satisfy the ratio, rather than
> > > evaluating it at a single link
> > rate.
> > >
> > > v2:
> > > -Drop the checks in the MST link config helpers, redundant now that
> > > the constraint is applied while computing the link config limits.
> > > (Imre) -Share the mode_valid helper with SST instead of evaluating
> > > the ratio at one link rate, since the link symbol clock is not
> > > monotonic in the link rate and there is no single best case configuration.
> > > v3:
> > > -Now that intel_dp_mode_valid_m_n checks for all configs just call
> > > that
> > > (Sashiko)
> > >
> > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++++
> > >  1 file changed, 5 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > index 0c362784afe4..823fe99ca0a1 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > @@ -1565,6 +1565,11 @@ mst_connector_mode_valid_ctx(struct
> > > drm_connector *_connector,
> > >  					   min_link_bpp_x16,
> > >  					   bw_overhead_flags);
> > >
> > > +	if (!intel_dp_mode_valid_m_n(intel_dp, mode->clock)) {
> > > +		*status = MODE_CLOCK_HIGH;
> > > +		return 0;
> > > +	}
> >
> > Since MST appears to use only the max_bw_config for link
> > configuration, should the M/N ratio check in mode_valid also be
> > performed against that configuration's max_link_clock? Currently,
> > intel_dp_mode_valid_m_n accepts the mode if any allowed config passes
> the ratio check.
> >
> > For example, on DG2 with a UHBR10 MST link, could a ~1.3 GHz stream
> > pass the check using HBR3 but later fail during config computation
> > because MST uses UHBR10, which does not satisfy the ratio limit? If
> > so, should the validation use the same link configuration that MST will
> actually use?
> 
> Lets start with DG2 does not have UHBR to begin with.
> Also compute doesn't actually use max_bw_config. MST goes through
> intel_dp_compute_config_limits() too, so configs that fail the ratio are already
> filtered out and it picks from what's left. In your example it'd just use HBR3
> instead of failing (DG2 has no UHBR anyway).
> For mode_valid I didn't want to check only max_bw_config, since the symbol
> clock isn't monotonic in link rate and a lower rate can pass where the max
> one fails.
> If something slips through, compute still does the exact check.
> 
> Regards,
> Suraj Kandpal

Could we double-check the MST path here ?

My understanding is that DG2 supports UHBR, and intel_dp_compute_config_limits
pins link_config_filter to the max-BW config for MST before the M/N ratio filtering runs.
If that config fails the ratio check, would the stream be rejected rather than falling back to HBR3 ?

Also, since mst_stream_compute_link_config uses the same max-BW config for port_clock,
should mode_valid check the ratio against that config as well, rather than accepting the mode
based on any allowed config?

> 
> >
> > > +
> > >  	/*
> > >  	 * TODO:
> > >  	 * - Also check if compression would allow for the mode
> > > --
> > > 2.34.1

RE: [PATCH v4 03/10] drm/i915/dp_mst: Limit M/N ratio for MST

[Kandpal, Suraj]

> -----Original Message-----
> From: Golani, Mitulkumar Ajitkumar
> <mitulkumar.ajitkumar.golani@intel.com>
> Sent: 22 October 2026 22:11
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>
> Subject: RE: [PATCH v4 03/10] drm/i915/dp_mst: Limit M/N ratio for MST
> 
> 
> 
> > -----Original Message-----
> > From: Kandpal, Suraj <suraj.kandpal@intel.com>
> > Sent: 21 October 2026 10:39
> > To: Golani, Mitulkumar Ajitkumar
> > <mitulkumar.ajitkumar.golani@intel.com>;
> > intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> > <arun.r.murthy@intel.com>
> > Subject: RE: [PATCH v4 03/10] drm/i915/dp_mst: Limit M/N ratio for MST
> >
> >
> >
> > > -----Original Message-----
> > > From: Golani, Mitulkumar Ajitkumar
> > > <mitulkumar.ajitkumar.golani@intel.com>
> > > Sent: 15 October 2026 22:59
> > > To: Kandpal, Suraj <suraj.kandpal@intel.com>;
> > > intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> > > <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> > > Subject: RE: [PATCH v4 03/10] drm/i915/dp_mst: Limit M/N ratio for
> > > MST
> > >
> > >
> > >
> > > > -----Original Message-----
> > > > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On
> > > > Behalf Of Suraj Kandpal
> > > > Sent: 17 September 2026 10:37
> > > > To: intel-xe@lists.freedesktop.org;
> > > > intel-gfx@lists.freedesktop.org
> > > > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> > > > <arun.r.murthy@intel.com>; Kandpal, Suraj
> > > > <suraj.kandpal@intel.com>
> > > > Subject: [PATCH v4 03/10] drm/i915/dp_mst: Limit M/N ratio for MST
> > > >
> > > > From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > >
> > > > The hardware does not support DisplayPort configurations where the
> > > > ceiling of the Link M/Link N ratio exceeds the limit. Enforce this
> > > > constraint for MST as well.
> > > >
> > > > The compute config path needs no change: MST goes through
> > > > intel_dp_compute_config_limits() too, so the link config filter
> > > > set up there already excludes the configurations violating the
> > > > ratio limit, and MST fails there if none is left.
> > > >
> > > > What is still missing is pruning such modes, so add the check to
> > > > mst_connector_mode_valid_ctx(), reusing the helper the SST
> > > > mode_valid uses. It walks the link configurations and only rejects
> > > > the mode if none of them can satisfy the ratio, rather than
> > > > evaluating it at a single link
> > > rate.
> > > >
> > > > v2:
> > > > -Drop the checks in the MST link config helpers, redundant now
> > > > that the constraint is applied while computing the link config limits.
> > > > (Imre) -Share the mode_valid helper with SST instead of evaluating
> > > > the ratio at one link rate, since the link symbol clock is not
> > > > monotonic in the link rate and there is no single best case
> configuration.
> > > > v3:
> > > > -Now that intel_dp_mode_valid_m_n checks for all configs just call
> > > > that
> > > > (Sashiko)
> > > >
> > > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++++
> > > >  1 file changed, 5 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > > index 0c362784afe4..823fe99ca0a1 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > > @@ -1565,6 +1565,11 @@ mst_connector_mode_valid_ctx(struct
> > > > drm_connector *_connector,
> > > >  					   min_link_bpp_x16,
> > > >  					   bw_overhead_flags);
> > > >
> > > > +	if (!intel_dp_mode_valid_m_n(intel_dp, mode->clock)) {
> > > > +		*status = MODE_CLOCK_HIGH;
> > > > +		return 0;
> > > > +	}
> > >
> > > Since MST appears to use only the max_bw_config for link
> > > configuration, should the M/N ratio check in mode_valid also be
> > > performed against that configuration's max_link_clock? Currently,
> > > intel_dp_mode_valid_m_n accepts the mode if any allowed config
> > > passes
> > the ratio check.
> > >
> > > For example, on DG2 with a UHBR10 MST link, could a ~1.3 GHz stream
> > > pass the check using HBR3 but later fail during config computation
> > > because MST uses UHBR10, which does not satisfy the ratio limit? If
> > > so, should the validation use the same link configuration that MST
> > > will
> > actually use?
> >
> > Lets start with DG2 does not have UHBR to begin with.
> > Also compute doesn't actually use max_bw_config. MST goes through
> > intel_dp_compute_config_limits() too, so configs that fail the ratio
> > are already filtered out and it picks from what's left. In your
> > example it'd just use HBR3 instead of failing (DG2 has no UHBR anyway).
> > For mode_valid I didn't want to check only max_bw_config, since the
> > symbol clock isn't monotonic in link rate and a lower rate can pass
> > where the max one fails.
> > If something slips through, compute still does the exact check.
> >
> > Regards,
> > Suraj Kandpal
> 
> Could we double-check the MST path here ?
> 
> My understanding is that DG2 supports UHBR, and
> intel_dp_compute_config_limits pins link_config_filter to the max-BW config
> for MST before the M/N ratio filtering runs.
> If that config fails the ratio check, would the stream be rejected rather than
> falling back to HBR3 ?
> 
> Also, since mst_stream_compute_link_config uses the same max-BW config
> for port_clock, should mode_valid check the ratio against that config as well,
> rather than accepting the mode based on any allowed config?
> 

What would you propose as a fix for this.

Regards,
Suraj Kandpal

> >
> > >
> > > > +
> > > >  	/*
> > > >  	 * TODO:
> > > >  	 * - Also check if compression would allow for the mode
> > > > --
> > > > 2.34.1

[PATCH v4 04/10] drm/i915/dp: Add M/N ratio check for DP link config

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Introduce intel_dp_check_m_n_ratio() to validate the computed link M/N
ratio against the maximum allowed value, and log it if the ratio exceeds
the limit.

The link config limits computed in the previous patches only restrict
the configurations that may be selected; this catches anything that
still slips through.

Log it rather than warn about it: the link config filter already
excludes the configurations violating the limit, so the only way to get
here is with link parameters forced through debugfs, which are applied
after that filter. A user triggerable drm_WARN() with its backtrace
would be out of proportion for that.

This check works off the M/N values as actually computed, which exposes
a mismatch with the prediction done while computing the limits: the
pixel clock there is the one before intel_dp_compute_config() divides
adjusted_mode->crtc_clock by the MSO link count. Divide in the
prediction too, so both agree. The joiner needs no such handling, as
intel_joiner_adjust_timings() only rewrites the pipe mode and leaves the
adjusted mode the link M/N is derived from untouched.

For MST the check goes after the bpp loop rather than inside it. The
link M/N is computed from the pixel clock and the link symbol clock, so
it does not depend on the bpp being tried and the result is the same on
every iteration.

v2:
-Use the platform specific ratio limit. (Wa_14014191401)
-Use the MSO adjusted pixel clock when predicting the ratio, matching
what the link M/N is actually computed from. (Imre)
-Drop the check from ilk_fdi_compute_config(): it was passing dp_m_n
rather than the fdi_m_n it had just computed, and an FDI link cannot get
anywhere near the ratio limit anyway.
v3:
-Check the ratio once after the MST bpp loop instead of on every
iteration, the result does not depend on the bpp. (Sashiko)
-Log instead of warning, since the link config filter already excludes
these configurations and only forced link parameters can reach it.
(Sashiko)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c     | 37 +++++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_dp.h     |  4 +++
 drivers/gpu/drm/i915/display/intel_dp_mst.c |  2 ++
 3 files changed, 41 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f6a2152c4432..fbfc00101886 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1294,6 +1294,14 @@ intel_dp_can_support_m_n(struct intel_display *display,
 	return m_n_ratio <= max_m_n_ratio;
 }
 
+static int intel_dp_mso_pixel_clock(struct intel_dp *intel_dp, int pixel_clock)
+{
+	if (!intel_dp->mso_link_count)
+		return pixel_clock;
+
+	return pixel_clock / intel_dp->mso_link_count;
+}
+
 static
 bool intel_dp_can_join(struct intel_dp *intel_dp,
 		       int num_joined_pipes)
@@ -1332,6 +1340,7 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
 bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
+	int m_n_pixel_clock = intel_dp_mso_pixel_clock(intel_dp, pixel_clock);
 	struct intel_dp_link_caps_order order = {
 		.key = INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE,
 		.dir = INTEL_DP_LINK_CAPS_ORDER_DIR_DESC,
@@ -1343,7 +1352,8 @@ bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock)
 	intel_dp_link_caps_iter_start(&iter, intel_dp->link.caps, order,
 				      INTEL_DP_LINK_CAPS_FILTER_ALL);
 	for_each_dp_link_config(&iter, &link_config) {
-		if (intel_dp_can_support_m_n(display, pixel_clock, link_config.rate)) {
+		if (intel_dp_can_support_m_n(display, m_n_pixel_clock,
+					     link_config.rate)) {
 			found = true;
 
 			break;
@@ -2723,7 +2733,8 @@ intel_dp_compute_m_n_ratio_limits(struct intel_dp *intel_dp,
 	struct intel_dp_link_caps_order order =
 		intel_dp_link_caps_connector_compute_order(connector);
 	struct intel_dp_link_caps_filter new_filter = INTEL_DP_LINK_CAPS_FILTER_NONE;
-	int pixel_clock = intel_dp_mode_clock(crtc_state, conn_state);
+	int pixel_clock = intel_dp_mso_pixel_clock(intel_dp,
+						  intel_dp_mode_clock(crtc_state, conn_state));
 	struct intel_dp_link_config link_config;
 	struct intel_dp_link_caps_iter iter;
 	bool found = false;
@@ -3382,6 +3393,24 @@ static bool can_enable_drrs(struct intel_connector *connector,
 		intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
 }
 
+void intel_dp_check_m_n_ratio(struct intel_crtc_state *crtc_state,
+			      struct intel_link_m_n *m_n)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
+	int m_n_ratio;
+
+	if (!m_n || !m_n->link_n)
+		return;
+
+	m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
+
+	if (m_n_ratio > max_m_n_ratio)
+		drm_dbg_kms(display->drm,
+			    "Link M/N ratio (%d) exceeds max allowed (%d)\n",
+			    m_n_ratio, max_m_n_ratio);
+}
+
 static void
 intel_dp_drrs_compute_config(struct intel_connector *connector,
 			     struct intel_crtc_state *pipe_config,
@@ -3420,6 +3449,8 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
 			       intel_dp_bw_fec_overhead(pipe_config->fec_enable),
 			       &pipe_config->dp_m2_n2);
 
+	intel_dp_check_m_n_ratio(pipe_config, &pipe_config->dp_m2_n2);
+
 	/* FIXME: abstract this better */
 	if (pipe_config->splitter.enable)
 		pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
@@ -3739,6 +3770,8 @@ intel_dp_compute_config(struct intel_atomic_state *state,
 				       pipe_config->port_clock,
 				       intel_dp_bw_fec_overhead(pipe_config->fec_enable),
 				       &pipe_config->dp_m_n);
+
+		intel_dp_check_m_n_ratio(pipe_config, &pipe_config->dp_m_n);
 	}
 
 	ret = intel_dp_compute_min_hblank(pipe_config, conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index aa58833a405b..4c975358ab96 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -26,6 +26,7 @@ struct intel_display;
 struct intel_dp;
 struct intel_dp_link_config;
 struct intel_encoder;
+struct intel_link_m_n;
 
 struct link_config_limits {
 	struct intel_dp_link_caps_filter link_config_filter;
@@ -244,4 +245,7 @@ bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock);
 int intel_dp_link_init(struct intel_dp *intel_dp);
 void intel_dp_link_cleanup(struct intel_dp *intel_dp);
 
+void intel_dp_check_m_n_ratio(struct intel_crtc_state *crtc_state,
+			      struct intel_link_m_n *m_n);
+
 #endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 823fe99ca0a1..6d2e234a9e9b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -429,6 +429,8 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
 		return slots;
 	}
 
+	intel_dp_check_m_n_ratio(crtc_state, &crtc_state->dp_m_n);
+
 	if (!dsc)
 		crtc_state->pipe_bpp = fxp_q4_to_int(bpp_x16);
 	else
-- 
2.34.1

RE: [PATCH v4 04/10] drm/i915/dp: Add M/N ratio check for DP link config

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Suraj
> Kandpal
> Sent: 17 September 2026 10:37
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: [PATCH v4 04/10] drm/i915/dp: Add M/N ratio check for DP link
> config
> 
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> 
> Introduce intel_dp_check_m_n_ratio() to validate the computed link M/N
> ratio against the maximum allowed value, and log it if the ratio exceeds the
> limit.
> 
> The link config limits computed in the previous patches only restrict the
> configurations that may be selected; this catches anything that still slips
> through.
> 
> Log it rather than warn about it: the link config filter already excludes the
> configurations violating the limit, so the only way to get here is with link
> parameters forced through debugfs, which are applied after that filter. A user
> triggerable drm_WARN() with its backtrace would be out of proportion for
> that.
> 
> This check works off the M/N values as actually computed, which exposes a
> mismatch with the prediction done while computing the limits: the pixel clock
> there is the one before intel_dp_compute_config() divides adjusted_mode-
> >crtc_clock by the MSO link count. Divide in the prediction too, so both
> agree. The joiner needs no such handling, as
> intel_joiner_adjust_timings() only rewrites the pipe mode and leaves the
> adjusted mode the link M/N is derived from untouched.
> 
> For MST the check goes after the bpp loop rather than inside it. The link M/N
> is computed from the pixel clock and the link symbol clock, so it does not
> depend on the bpp being tried and the result is the same on every iteration.
> 
> v2:
> -Use the platform specific ratio limit. (Wa_14014191401) -Use the MSO
> adjusted pixel clock when predicting the ratio, matching what the link M/N is
> actually computed from. (Imre) -Drop the check from
> ilk_fdi_compute_config(): it was passing dp_m_n rather than the fdi_m_n it
> had just computed, and an FDI link cannot get anywhere near the ratio limit
> anyway.
> v3:
> -Check the ratio once after the MST bpp loop instead of on every iteration,
> the result does not depend on the bpp. (Sashiko) -Log instead of warning,
> since the link config filter already excludes these configurations and only
> forced link parameters can reach it.
> (Sashiko)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c     | 37 +++++++++++++++++++--
>  drivers/gpu/drm/i915/display/intel_dp.h     |  4 +++
>  drivers/gpu/drm/i915/display/intel_dp_mst.c |  2 ++
>  3 files changed, 41 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index f6a2152c4432..fbfc00101886 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1294,6 +1294,14 @@ intel_dp_can_support_m_n(struct intel_display
> *display,
>  	return m_n_ratio <= max_m_n_ratio;
>  }
> 
> +static int intel_dp_mso_pixel_clock(struct intel_dp *intel_dp, int
> +pixel_clock) {
> +	if (!intel_dp->mso_link_count)
> +		return pixel_clock;
> +
> +	return pixel_clock / intel_dp->mso_link_count; }
> +

These hunks fix the prediction added in "drm/i915/dp: Limit M/N ratio for DP SST". On its own that patch over-restricts MSO eDP by mso_link_count . Please squash them, together with the MSO/joiner explanation, into that patch so it is correct on its own, and keep this patch to the debug check.

>  static
>  bool intel_dp_can_join(struct intel_dp *intel_dp,
>  		       int num_joined_pipes)
> @@ -1332,6 +1340,7 @@ bool intel_dp_dotclk_valid(struct intel_display
> *display,  bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int
> pixel_clock)  {
>  	struct intel_display *display = to_intel_display(intel_dp);
> +	int m_n_pixel_clock = intel_dp_mso_pixel_clock(intel_dp,
> pixel_clock);
>  	struct intel_dp_link_caps_order order = {
>  		.key = INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE,
>  		.dir = INTEL_DP_LINK_CAPS_ORDER_DIR_DESC,
> @@ -1343,7 +1352,8 @@ bool intel_dp_mode_valid_m_n(struct intel_dp
> *intel_dp, int pixel_clock)
>  	intel_dp_link_caps_iter_start(&iter, intel_dp->link.caps, order,
>  				      INTEL_DP_LINK_CAPS_FILTER_ALL);
>  	for_each_dp_link_config(&iter, &link_config) {
> -		if (intel_dp_can_support_m_n(display, pixel_clock,
> link_config.rate)) {
> +		if (intel_dp_can_support_m_n(display, m_n_pixel_clock,
> +					     link_config.rate)) {
>  			found = true;
> 
>  			break;
> @@ -2723,7 +2733,8 @@ intel_dp_compute_m_n_ratio_limits(struct
> intel_dp *intel_dp,
>  	struct intel_dp_link_caps_order order =
>  		intel_dp_link_caps_connector_compute_order(connector);
>  	struct intel_dp_link_caps_filter new_filter =
> INTEL_DP_LINK_CAPS_FILTER_NONE;
> -	int pixel_clock = intel_dp_mode_clock(crtc_state, conn_state);
> +	int pixel_clock = intel_dp_mso_pixel_clock(intel_dp,
> +
> intel_dp_mode_clock(crtc_state, conn_state));
>  	struct intel_dp_link_config link_config;
>  	struct intel_dp_link_caps_iter iter;
>  	bool found = false;
> @@ -3382,6 +3393,24 @@ static bool can_enable_drrs(struct
> intel_connector *connector,
>  		intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
> }
> 
> +void intel_dp_check_m_n_ratio(struct intel_crtc_state *crtc_state,
> +			      struct intel_link_m_n *m_n)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
> +	int m_n_ratio;
> +
> +	if (!m_n || !m_n->link_n)
> +		return;
> +
> +	m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
> +
> +	if (m_n_ratio > max_m_n_ratio)
> +		drm_dbg_kms(display->drm,
> +			    "Link M/N ratio (%d) exceeds max allowed (%d)\n",
> +			    m_n_ratio, max_m_n_ratio);
> +}

Could we reuse a small helper here, since the DIV_ROUND_UP(link_m, link_n) <= max check appears to duplicate intel_dp_can_support_m_n? Also, are the !m_n and !m_n->link_n checks necessary, given that callers pass struct members and link_n is fixed at 0x80000? Could the parameters be const as well? Finally, would it make sense to place this helper next to intel_dp_can_support_m_n ?

> +
>  static void
>  intel_dp_drrs_compute_config(struct intel_connector *connector,
>  			     struct intel_crtc_state *pipe_config, @@ -3420,6
> +3449,8 @@ intel_dp_drrs_compute_config(struct intel_connector
> *connector,
>  			       intel_dp_bw_fec_overhead(pipe_config-
> >fec_enable),
>  			       &pipe_config->dp_m2_n2);
> 
> +	intel_dp_check_m_n_ratio(pipe_config, &pipe_config->dp_m2_n2);

Could we drop this check since dp_m2_n2 is computed using the same port_clock and its ratio should already be covered by the dp_m_n check? Or is this intended as a defensive check?

> +
>  	/* FIXME: abstract this better */
>  	if (pipe_config->splitter.enable)
>  		pipe_config->dp_m2_n2.data_m *= pipe_config-
> >splitter.link_count; @@ -3739,6 +3770,8 @@
> intel_dp_compute_config(struct intel_atomic_state *state,
>  				       pipe_config->port_clock,
>  				       intel_dp_bw_fec_overhead(pipe_config-
> >fec_enable),
>  				       &pipe_config->dp_m_n);
> +
> +		intel_dp_check_m_n_ratio(pipe_config, &pipe_config-
> >dp_m_n);
>  	}
> 
>  	ret = intel_dp_compute_min_hblank(pipe_config, conn_state); diff --
> git a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index aa58833a405b..4c975358ab96 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -26,6 +26,7 @@ struct intel_display;
>  struct intel_dp;
>  struct intel_dp_link_config;
>  struct intel_encoder;
> +struct intel_link_m_n;
> 
>  struct link_config_limits {
>  	struct intel_dp_link_caps_filter link_config_filter; @@ -244,4 +245,7
> @@ bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int
> pixel_clock);  int intel_dp_link_init(struct intel_dp *intel_dp);  void
> intel_dp_link_cleanup(struct intel_dp *intel_dp);
> 
> +void intel_dp_check_m_n_ratio(struct intel_crtc_state *crtc_state,
> +			      struct intel_link_m_n *m_n);
> +
>  #endif /* __INTEL_DP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 823fe99ca0a1..6d2e234a9e9b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -429,6 +429,8 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp
> *intel_dp,
>  		return slots;
>  	}
> 
> +	intel_dp_check_m_n_ratio(crtc_state, &crtc_state->dp_m_n);
> +
>  	if (!dsc)
>  		crtc_state->pipe_bpp = fxp_q4_to_int(bpp_x16);
>  	else
> --
> 2.34.1

RE: [PATCH v4 04/10] drm/i915/dp: Add M/N ratio check for DP link config

[Kandpal, Suraj]

> -----Original Message-----
> From: Golani, Mitulkumar Ajitkumar
> <mitulkumar.ajitkumar.golani@intel.com>
> Sent: 16 October 2026 00:27
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: RE: [PATCH v4 04/10] drm/i915/dp: Add M/N ratio check for DP link
> config
> 
> 
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> > Suraj Kandpal
> > Sent: 17 September 2026 10:37
> > To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> > <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> > Subject: [PATCH v4 04/10] drm/i915/dp: Add M/N ratio check for DP link
> > config
> >
> > From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >
> > Introduce intel_dp_check_m_n_ratio() to validate the computed link M/N
> > ratio against the maximum allowed value, and log it if the ratio
> > exceeds the limit.
> >
> > The link config limits computed in the previous patches only restrict
> > the configurations that may be selected; this catches anything that
> > still slips through.
> >
> > Log it rather than warn about it: the link config filter already
> > excludes the configurations violating the limit, so the only way to
> > get here is with link parameters forced through debugfs, which are
> > applied after that filter. A user triggerable drm_WARN() with its
> > backtrace would be out of proportion for that.
> >
> > This check works off the M/N values as actually computed, which
> > exposes a mismatch with the prediction done while computing the
> > limits: the pixel clock there is the one before
> > intel_dp_compute_config() divides adjusted_mode-
> > >crtc_clock by the MSO link count. Divide in the prediction too, so
> > >both
> > agree. The joiner needs no such handling, as
> > intel_joiner_adjust_timings() only rewrites the pipe mode and leaves
> > the adjusted mode the link M/N is derived from untouched.
> >
> > For MST the check goes after the bpp loop rather than inside it. The
> > link M/N is computed from the pixel clock and the link symbol clock,
> > so it does not depend on the bpp being tried and the result is the same on
> every iteration.
> >
> > v2:
> > -Use the platform specific ratio limit. (Wa_14014191401) -Use the MSO
> > adjusted pixel clock when predicting the ratio, matching what the link
> > M/N is actually computed from. (Imre) -Drop the check from
> > ilk_fdi_compute_config(): it was passing dp_m_n rather than the
> > fdi_m_n it had just computed, and an FDI link cannot get anywhere near
> > the ratio limit anyway.
> > v3:
> > -Check the ratio once after the MST bpp loop instead of on every
> > iteration, the result does not depend on the bpp. (Sashiko) -Log
> > instead of warning, since the link config filter already excludes
> > these configurations and only forced link parameters can reach it.
> > (Sashiko)
> >
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c     | 37 +++++++++++++++++++--
> >  drivers/gpu/drm/i915/display/intel_dp.h     |  4 +++
> >  drivers/gpu/drm/i915/display/intel_dp_mst.c |  2 ++
> >  3 files changed, 41 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index f6a2152c4432..fbfc00101886 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1294,6 +1294,14 @@ intel_dp_can_support_m_n(struct intel_display
> > *display,
> >  	return m_n_ratio <= max_m_n_ratio;
> >  }
> >
> > +static int intel_dp_mso_pixel_clock(struct intel_dp *intel_dp, int
> > +pixel_clock) {
> > +	if (!intel_dp->mso_link_count)
> > +		return pixel_clock;
> > +
> > +	return pixel_clock / intel_dp->mso_link_count; }
> > +
> 
> These hunks fix the prediction added in "drm/i915/dp: Limit M/N ratio for DP
> SST". On its own that patch over-restricts MSO eDP by mso_link_count .
> Please squash them, together with the MSO/joiner explanation, into that
> patch so it is correct on its own, and keep this patch to the debug check.

Sure

> 
> >  static
> >  bool intel_dp_can_join(struct intel_dp *intel_dp,
> >  		       int num_joined_pipes)
> > @@ -1332,6 +1340,7 @@ bool intel_dp_dotclk_valid(struct intel_display
> > *display,  bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int
> > pixel_clock)  {
> >  	struct intel_display *display = to_intel_display(intel_dp);
> > +	int m_n_pixel_clock = intel_dp_mso_pixel_clock(intel_dp,
> > pixel_clock);
> >  	struct intel_dp_link_caps_order order = {
> >  		.key = INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE,
> >  		.dir = INTEL_DP_LINK_CAPS_ORDER_DIR_DESC,
> > @@ -1343,7 +1352,8 @@ bool intel_dp_mode_valid_m_n(struct intel_dp
> > *intel_dp, int pixel_clock)
> >  	intel_dp_link_caps_iter_start(&iter, intel_dp->link.caps, order,
> >  				      INTEL_DP_LINK_CAPS_FILTER_ALL);
> >  	for_each_dp_link_config(&iter, &link_config) {
> > -		if (intel_dp_can_support_m_n(display, pixel_clock,
> > link_config.rate)) {
> > +		if (intel_dp_can_support_m_n(display, m_n_pixel_clock,
> > +					     link_config.rate)) {
> >  			found = true;
> >
> >  			break;
> > @@ -2723,7 +2733,8 @@ intel_dp_compute_m_n_ratio_limits(struct
> > intel_dp *intel_dp,
> >  	struct intel_dp_link_caps_order order =
> >  		intel_dp_link_caps_connector_compute_order(connector);
> >  	struct intel_dp_link_caps_filter new_filter =
> > INTEL_DP_LINK_CAPS_FILTER_NONE;
> > -	int pixel_clock = intel_dp_mode_clock(crtc_state, conn_state);
> > +	int pixel_clock = intel_dp_mso_pixel_clock(intel_dp,
> > +
> > intel_dp_mode_clock(crtc_state, conn_state));
> >  	struct intel_dp_link_config link_config;
> >  	struct intel_dp_link_caps_iter iter;
> >  	bool found = false;
> > @@ -3382,6 +3393,24 @@ static bool can_enable_drrs(struct
> > intel_connector *connector,
> >  		intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
> }
> >
> > +void intel_dp_check_m_n_ratio(struct intel_crtc_state *crtc_state,
> > +			      struct intel_link_m_n *m_n)
> > +{
> > +	struct intel_display *display = to_intel_display(crtc_state);
> > +	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
> > +	int m_n_ratio;
> > +
> > +	if (!m_n || !m_n->link_n)
> > +		return;
> > +
> > +	m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
> > +
> > +	if (m_n_ratio > max_m_n_ratio)
> > +		drm_dbg_kms(display->drm,
> > +			    "Link M/N ratio (%d) exceeds max allowed (%d)\n",
> > +			    m_n_ratio, max_m_n_ratio);
> > +}
> 
> Could we reuse a small helper here, since the DIV_ROUND_UP(link_m,
> link_n) <= max check appears to duplicate intel_dp_can_support_m_n? 

I can do that.

> Also,
> are the !m_n and !m_n->link_n checks necessary, given that callers pass
> struct members and link_n is fixed at 0x80000?

Sure will drop the check

 Could the parameters be
> const as well? 

Finally, would it make sense to place this helper next to
> intel_dp_can_support_m_n ?

Can do 
> 
> > +
> >  static void
> >  intel_dp_drrs_compute_config(struct intel_connector *connector,
> >  			     struct intel_crtc_state *pipe_config, @@ -3420,6
> > +3449,8 @@ intel_dp_drrs_compute_config(struct intel_connector
> > *connector,
> >  			       intel_dp_bw_fec_overhead(pipe_config-
> > >fec_enable),
> >  			       &pipe_config->dp_m2_n2);
> >
> > +	intel_dp_check_m_n_ratio(pipe_config, &pipe_config->dp_m2_n2);
> 
> Could we drop this check since dp_m2_n2 is computed using the same
> port_clock and its ratio should already be covered by the dp_m_n check? Or
> is this intended as a defensive check?

Sure will drop it.

> 
> > +
> >  	/* FIXME: abstract this better */
> >  	if (pipe_config->splitter.enable)
> >  		pipe_config->dp_m2_n2.data_m *= pipe_config-
> > >splitter.link_count; @@ -3739,6 +3770,8 @@
> > intel_dp_compute_config(struct intel_atomic_state *state,
> >  				       pipe_config->port_clock,
> >  				       intel_dp_bw_fec_overhead(pipe_config-
> > >fec_enable),
> >  				       &pipe_config->dp_m_n);
> > +
> > +		intel_dp_check_m_n_ratio(pipe_config, &pipe_config-
> > >dp_m_n);
> >  	}
> >
> >  	ret = intel_dp_compute_min_hblank(pipe_config, conn_state); diff --
> > git a/drivers/gpu/drm/i915/display/intel_dp.h
> > b/drivers/gpu/drm/i915/display/intel_dp.h
> > index aa58833a405b..4c975358ab96 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -26,6 +26,7 @@ struct intel_display;  struct intel_dp;  struct
> > intel_dp_link_config;  struct intel_encoder;
> > +struct intel_link_m_n;
> >
> >  struct link_config_limits {
> >  	struct intel_dp_link_caps_filter link_config_filter; @@ -244,4 +245,7
> > @@ bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int
> > pixel_clock);  int intel_dp_link_init(struct intel_dp *intel_dp);  void
> > intel_dp_link_cleanup(struct intel_dp *intel_dp);
> >
> > +void intel_dp_check_m_n_ratio(struct intel_crtc_state *crtc_state,
> > +			      struct intel_link_m_n *m_n);
> > +
> >  #endif /* __INTEL_DP_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 823fe99ca0a1..6d2e234a9e9b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -429,6 +429,8 @@ int intel_dp_mtp_tu_compute_config(struct
> intel_dp
> > *intel_dp,
> >  		return slots;
> >  	}
> >
> > +	intel_dp_check_m_n_ratio(crtc_state, &crtc_state->dp_m_n);
> > +
> >  	if (!dsc)
> >  		crtc_state->pipe_bpp = fxp_q4_to_int(bpp_x16);
> >  	else
> > --
> > 2.34.1

[PATCH v4 05/10] drm/i915/display: Add bits for link_n_extended for DISPLAY >= 14

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

LINK_N register has bits 31:24 for extended link N value used for
HDMI2.1 and for an alternate mode of operation of DP TG DDA.

Add support for these extra bits.

For displays with version 14 or higher, PIPE_LINK_N1_EXTENDED_MASK
(bits 31:24) is used to handle the extended link N bits. For older
platforms, DATA_LINK_M_N_MASK (bits 23:0) is used to handle the
standard link N bits. This distinction ensures clarity and maintains
the semantics for platforms that support the extended bits. In
subsequent changes the logic is updated to conditionally apply the
extended link N bits.

v2: Drop extra link_n_ext member. (Jani)
v3: Avoid link_n_ext in set_m_n helper. (Jani)
v4: Rebase, and update commit message.
v5: Drop a stale changelog entry, the DISPLAY_VER split here is
    intentional. (Sashiko)

Bspec:50488
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c   | 18 ++++++++++++++++--
 .../gpu/drm/i915/display/intel_display_regs.h  |  2 ++
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c53163d7c082..6d2025e10995 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2711,14 +2711,22 @@ void intel_set_m_n(struct intel_display *display,
 		   intel_reg_t data_m_reg, intel_reg_t data_n_reg,
 		   intel_reg_t link_m_reg, intel_reg_t link_n_reg)
 {
+	u32 link_n = m_n->link_n;
+
 	intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
 	intel_de_write(display, data_n_reg, m_n->data_n);
 	intel_de_write(display, link_m_reg, m_n->link_m);
+
+	if (DISPLAY_VER(display) >= 14)
+		link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
+	else
+		link_n &= DATA_LINK_M_N_MASK;
+
 	/*
 	 * On BDW+ writing LINK_N arms the double buffered update
 	 * of all the M/N registers, so it must be written last.
 	 */
-	intel_de_write(display, link_n_reg, m_n->link_n);
+	intel_de_write(display, link_n_reg, link_n);
 }
 
 bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
@@ -3475,7 +3483,13 @@ void intel_get_m_n(struct intel_display *display,
 		   intel_reg_t link_m_reg, intel_reg_t link_n_reg)
 {
 	m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK;
-	m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK;
+	m_n->link_n = intel_de_read(display, link_n_reg);
+
+	if (DISPLAY_VER(display) >= 14)
+		m_n->link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
+	else
+		m_n->link_n &= DATA_LINK_M_N_MASK;
+
 	m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK;
 	m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK;
 	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 8251ec15190b..57f388c958b4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1190,6 +1190,8 @@
 
 #define _PIPEA_LINK_N1		0x60044
 #define _PIPEB_LINK_N1		0x61044
+#define  PIPE_LINK_N1_EXTENDED_MASK	REG_GENMASK(31, 24)
+#define  PIPE_LINK_N1_EXTENDED(val)	REG_FIELD_PREP(PIPE_LINK_N1_EXTENDED_MASK, (val))
 #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
 
 #define _PIPEA_LINK_M2		0x60048
-- 
2.34.1

RE: [PATCH v4 05/10] drm/i915/display: Add bits for link_n_extended for DISPLAY >= 14

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Suraj
> Kandpal
> Sent: 17 September 2026 10:37
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: [PATCH v4 05/10] drm/i915/display: Add bits for link_n_extended for
> DISPLAY >= 14
> 
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> 
> LINK_N register has bits 31:24 for extended link N value used for
> HDMI2.1 and for an alternate mode of operation of DP TG DDA.
> 
> Add support for these extra bits.
> 
> For displays with version 14 or higher, PIPE_LINK_N1_EXTENDED_MASK (bits
> 31:24) is used to handle the extended link N bits. For older platforms,
> DATA_LINK_M_N_MASK (bits 23:0) is used to handle the standard link N bits.
> This distinction ensures clarity and maintains the semantics for platforms that
> support the extended bits. In subsequent changes the logic is updated to
> conditionally apply the extended link N bits.
> 
> v2: Drop extra link_n_ext member. (Jani)
> v3: Avoid link_n_ext in set_m_n helper. (Jani)
> v4: Rebase, and update commit message.
> v5: Drop a stale changelog entry, the DISPLAY_VER split here is
>     intentional. (Sashiko)
> 
> Bspec:50488
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c   | 18 ++++++++++++++++--
>  .../gpu/drm/i915/display/intel_display_regs.h  |  2 ++
>  2 files changed, 18 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index c53163d7c082..6d2025e10995 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2711,14 +2711,22 @@ void intel_set_m_n(struct intel_display *display,
>  		   intel_reg_t data_m_reg, intel_reg_t data_n_reg,
>  		   intel_reg_t link_m_reg, intel_reg_t link_n_reg)  {
> +	u32 link_n = m_n->link_n;
> +
>  	intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n-
> >data_m);
>  	intel_de_write(display, data_n_reg, m_n->data_n);
>  	intel_de_write(display, link_m_reg, m_n->link_m);
> +
> +	if (DISPLAY_VER(display) >= 14)
> +		link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
> +	else
> +		link_n &= DATA_LINK_M_N_MASK;
> +
>  	/*
>  	 * On BDW+ writing LINK_N arms the double buffered update
>  	 * of all the M/N registers, so it must be written last.
>  	 */
> -	intel_de_write(display, link_n_reg, m_n->link_n);
> +	intel_de_write(display, link_n_reg, link_n);
>  }
> 
>  bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display, @@ -
> 3475,7 +3483,13 @@ void intel_get_m_n(struct intel_display *display,
>  		   intel_reg_t link_m_reg, intel_reg_t link_n_reg)  {
>  	m_n->link_m = intel_de_read(display, link_m_reg) &
> DATA_LINK_M_N_MASK;
> -	m_n->link_n = intel_de_read(display, link_n_reg) &
> DATA_LINK_M_N_MASK;
> +	m_n->link_n = intel_de_read(display, link_n_reg);
> +
> +	if (DISPLAY_VER(display) >= 14)
> +		m_n->link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
> +	else
> +		m_n->link_n &= DATA_LINK_M_N_MASK;
> +
>  	m_n->data_m = intel_de_read(display, data_m_reg) &
> DATA_LINK_M_N_MASK;
>  	m_n->data_n = intel_de_read(display, data_n_reg) &
> DATA_LINK_M_N_MASK;
>  	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display,
> data_m_reg)) + 1; diff --git
> a/drivers/gpu/drm/i915/display/intel_display_regs.h
> b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 8251ec15190b..57f388c958b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -1190,6 +1190,8 @@
> 
>  #define _PIPEA_LINK_N1		0x60044
>  #define _PIPEB_LINK_N1		0x61044
> +#define  PIPE_LINK_N1_EXTENDED_MASK	REG_GENMASK(31, 24)
> +#define  PIPE_LINK_N1_EXTENDED(val)
> 	REG_FIELD_PREP(PIPE_LINK_N1_EXTENDED_MASK, (val))

LGTM
Reviewed-by: Mitul Golani<mitulkumar.ajitkumar.golani@intel.com>

>  #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
> _PIPEA_LINK_N1)
> 
>  #define _PIPEA_LINK_M2		0x60048
> --
> 2.34.1

[PATCH v4 06/10] drm/i915/display_wa: Add support for Wa_14021768792

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Some BMG ultrajoiner configurations require support for Link M/N ratios
between 10.0 and 15.0. This range is not natively supported and requires
a workaround.

Wa_14021768792 enables this support by utilizing HDMI_EMP_DATA,
CHICKEN_TRANS and the extended bits in the LINK_N register.

Add the necessary logic to enable the workaround on applicable platforms.
The underlying mechanism comes from the display C0,
so it is gated on display stepping C0 and later.

v2:
-Don't include i915_drv.h and don't use struct drm_i915_private under
display/. Use display->platform.battlemage, which names the affected
platform directly, instead of IS_DGFX() combined with a display version
check. (Jani)
-Rebase on the reworked display WA framework, where the condition goes
directly into the __intel_display_wa() switch.

Bspec: 49266
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_wa.c | 9 +++++++++
 drivers/gpu/drm/i915/display/intel_display_wa.h | 1 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index 888676693f5e..7456194216be 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -111,6 +111,15 @@ bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa,
 		return DISPLAY_VERx100(display) == 3000 ||
 			DISPLAY_VERx100(display) == 2000 ||
 			DISPLAY_VERx100(display) == 1401;
+	/*
+	 * Wa_14021768792:
+	 * Fixes: Limitation of Link M/N ratio > 10 for specific Xe2HPD platforms.
+	 * Workaround: Use HDMI_EMP_DATA, CHICKEN_BITs and extended bits in LINK_N
+	 * registers to support LINK M/N ratios from > 10 but < 15.
+	 */
+	case INTEL_DISPLAY_WA_14021768792:
+		return display->platform.battlemage &&
+			IS_DISPLAY_STEP(display, STEP_C0, STEP_FOREVER);
 	case INTEL_DISPLAY_WA_14025769978:
 		return DISPLAY_VER(display) == 35;
 	case INTEL_DISPLAY_WA_14026643300:
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h
index 425a300840aa..b8f2f9363498 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.h
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
@@ -33,6 +33,7 @@ enum intel_display_wa {
 	INTEL_DISPLAY_WA_14014143976,
 	INTEL_DISPLAY_WA_14016740474,
 	INTEL_DISPLAY_WA_14020863754,
+	INTEL_DISPLAY_WA_14021768792,
 	INTEL_DISPLAY_WA_14025769978,
 	INTEL_DISPLAY_WA_14026643300,
 	INTEL_DISPLAY_WA_15013987218,
-- 
2.34.1

RE: [PATCH v4 06/10] drm/i915/display_wa: Add support for Wa_14021768792

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Suraj
> Kandpal
> Sent: 17 September 2026 10:37
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: [PATCH v4 06/10] drm/i915/display_wa: Add support for
> Wa_14021768792
> 
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> 
> Some BMG ultrajoiner configurations require support for Link M/N ratios
> between 10.0 and 15.0. This range is not natively supported and requires a
> workaround.
> 
> Wa_14021768792 enables this support by utilizing HDMI_EMP_DATA,
> CHICKEN_TRANS and the extended bits in the LINK_N register.
> 
> Add the necessary logic to enable the workaround on applicable platforms.
> The underlying mechanism comes from the display C0, so it is gated on
> display stepping C0 and later.
> 
> v2:
> -Don't include i915_drv.h and don't use struct drm_i915_private under
> display/. Use display->platform.battlemage, which names the affected
> platform directly, instead of IS_DGFX() combined with a display version check.
> (Jani) -Rebase on the reworked display WA framework, where the condition
> goes directly into the __intel_display_wa() switch.
> 
> Bspec: 49266
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_wa.c | 9 +++++++++
> drivers/gpu/drm/i915/display/intel_display_wa.h | 1 +
>  2 files changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c
> b/drivers/gpu/drm/i915/display/intel_display_wa.c
> index 888676693f5e..7456194216be 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_wa.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
> @@ -111,6 +111,15 @@ bool __intel_display_wa(struct intel_display
> *display, enum intel_display_wa wa,
>  		return DISPLAY_VERx100(display) == 3000 ||
>  			DISPLAY_VERx100(display) == 2000 ||
>  			DISPLAY_VERx100(display) == 1401;
> +	/*
> +	 * Wa_14021768792:
> +	 * Fixes: Limitation of Link M/N ratio > 10 for specific Xe2HPD
> platforms.
> +	 * Workaround: Use HDMI_EMP_DATA, CHICKEN_BITs and extended
> bits in LINK_N
> +	 * registers to support LINK M/N ratios from > 10 but < 15.
> +	 */
> +	case INTEL_DISPLAY_WA_14021768792:
> +		return display->platform.battlemage &&
> +			IS_DISPLAY_STEP(display, STEP_C0, STEP_FOREVER);
>  	case INTEL_DISPLAY_WA_14025769978:
>  		return DISPLAY_VER(display) == 35;
>  	case INTEL_DISPLAY_WA_14026643300:
> diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h
> b/drivers/gpu/drm/i915/display/intel_display_wa.h
> index 425a300840aa..b8f2f9363498 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_wa.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
> @@ -33,6 +33,7 @@ enum intel_display_wa {
>  	INTEL_DISPLAY_WA_14014143976,
>  	INTEL_DISPLAY_WA_14016740474,
>  	INTEL_DISPLAY_WA_14020863754,
> +	INTEL_DISPLAY_WA_14021768792,

LGTM
Reviewed-by: Mitul Golani<mitulkumar.ajitkumar.golani@intel.com>

>  	INTEL_DISPLAY_WA_14025769978,
>  	INTEL_DISPLAY_WA_14026643300,
>  	INTEL_DISPLAY_WA_15013987218,
> --
> 2.34.1

[PATCH v4 07/10] drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

To support a Link M/N ratio between 10.0 and 15.0, for some BMG
ultrajoiner cases we need Wa_14021768792.

To bypass the hardware limitation within the Timing Generator DDA
(TGDDA), we need to program the LINKM and LINKN registers as defined in
the WA. Along with this we also need the relevant bits in HDMI_EMP_DATA
and CHICKEN_TRANS.

Add the bits for the WA and a new member 'bypass_m_n_ratio_limit' to
track if we need to bypass the Link M/N ratio limit in the
intel_link_m_n structure.

Per Bspec the extended LINK_N field is two nibbles: bits 27:24 hold
INT(Link M / Link N) and bits 31:28 hold CEIL(Link M / Link N).

CHICKEN_TRANS and HDMI_EMP_DATA are programmed before LINK_N, since
writing LINK_N arms the double buffered update of the M/N registers, and
all of the programming has to be done before the transcoder is enabled.
Both are also explicitly cleared when the mechanism is not in use, so
that state cannot leak from a previous modeset.

Only bypass_m_n_ratio_limit is compared by the state checker, not the
ratio integer and fraction themselves. That is deliberate: both are
derived from Link M and Link N, which are compared already, so the thing
worth verifying is whether the workaround ended up being applied or not.

Unlike the rest of the M/N registers, CHICKEN_TRANS and HDMI_EMP_DATA
are not double buffered, so the flag has to be compared outside the
fastset exemption that PIPE_CONF_CHECK_M_N() has for update_m_n.
Otherwise a seamless M/N update could switch the DDA out of the
workaround on a live transcoder, with the Link M/N values only following
at the next MSA.

v2:
-Drop the drm_WARN_ON() on the extended LINK_N field in intel_get_m_n():
it is derived from Link M and Link N, so the state checker comparison of
those and of bypass_m_n_ratio_limit already covers it. (Sashiko)
-Compare bypass_m_n_ratio_limit unconditionally, so that a change to it
forces a full modeset instead of being applied during a seamless M/N
fastset. (Sashiko)

Bspec: 49266
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 93 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_display.h  |  2 +
 .../gpu/drm/i915/display/intel_display_regs.h | 10 ++
 .../drm/i915/display/intel_display_types.h    |  2 +
 4 files changed, 102 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6d2025e10995..1e9d8943626a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2706,6 +2706,15 @@ void intel_zero_m_n(struct intel_link_m_n *m_n)
 	m_n->tu = 1;
 }
 
+static u8 bmg_get_link_n_ext(const struct intel_link_m_n *m_n)
+{
+	if (!m_n->link_n)
+		return 0;
+
+	return PIPE_LINK_N1_EXT_INT(m_n->link_m / m_n->link_n) |
+		PIPE_LINK_N1_EXT_CEIL(DIV_ROUND_UP(m_n->link_m, m_n->link_n));
+}
+
 void intel_set_m_n(struct intel_display *display,
 		   const struct intel_link_m_n *m_n,
 		   intel_reg_t data_m_reg, intel_reg_t data_n_reg,
@@ -2717,7 +2726,9 @@ void intel_set_m_n(struct intel_display *display,
 	intel_de_write(display, data_n_reg, m_n->data_n);
 	intel_de_write(display, link_m_reg, m_n->link_m);
 
-	if (DISPLAY_VER(display) >= 14)
+	if (DISPLAY_VER(display) >= 14 && m_n->bypass_m_n_ratio_limit)
+		link_n |= PIPE_LINK_N1_EXTENDED(bmg_get_link_n_ext(m_n));
+	else if (DISPLAY_VER(display) >= 14)
 		link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
 	else
 		link_n &= DATA_LINK_M_N_MASK;
@@ -2738,6 +2749,26 @@ bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
 	return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview;
 }
 
+static void bmg_enhanced_tgdda_write(struct intel_crtc *crtc,
+				     enum transcoder transcoder,
+				     const struct intel_link_m_n *m_n)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	bool enable = m_n->bypass_m_n_ratio_limit && m_n->link_n;
+	u32 link_m_frac = enable ? m_n->link_m % m_n->link_n : 0;
+
+	if (!intel_display_wa(display, INTEL_DISPLAY_WA_14021768792))
+		return;
+
+	intel_de_rmw(display, HDMI_EMP_DATA(display, transcoder),
+		     HDMI_EMP_DATA_LINK_M_FRAC_MASK,
+		     REG_FIELD_PREP(HDMI_EMP_DATA_LINK_M_FRAC_MASK, link_m_frac));
+
+	intel_de_rmw(display, CHICKEN_TRANS(display, transcoder),
+		     DP_ENHANCED_TGDDA_ENABLE,
+		     enable ? DP_ENHANCED_TGDDA_ENABLE : 0);
+}
+
 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
 				    enum transcoder transcoder,
 				    const struct intel_link_m_n *m_n)
@@ -2745,6 +2776,8 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
 	struct intel_display *display = to_intel_display(crtc);
 	enum pipe pipe = crtc->pipe;
 
+	bmg_enhanced_tgdda_write(crtc, transcoder, m_n);
+
 	if (DISPLAY_VER(display) >= 5)
 		intel_set_m_n(display, m_n,
 			      PIPE_DATA_M1(display, transcoder),
@@ -3495,6 +3528,49 @@ void intel_get_m_n(struct intel_display *display,
 	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;
 }
 
+bool intel_display_can_bypass_m_n_limit(struct intel_display *display,
+					int m_n_ratio,
+					enum pipe pipe)
+{
+	if (!intel_display_wa(display, INTEL_DISPLAY_WA_14021768792))
+		return false;
+
+	if (m_n_ratio > 15)
+		return false;
+
+	if (pipe != PIPE_A)
+		return false;
+
+	return true;
+}
+
+static void bmg_enhanced_tgdda_read(struct intel_crtc *crtc,
+				    enum transcoder transcoder,
+				    struct intel_link_m_n *m_n)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	u32 link_m_frac;
+	int m_n_ratio;
+
+	if (!m_n->link_n)
+		return;
+
+	m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
+
+	if (!intel_display_can_bypass_m_n_limit(display, m_n_ratio, crtc->pipe))
+		return;
+
+	if (!(intel_de_read(display, CHICKEN_TRANS(display, transcoder)) &
+	      DP_ENHANCED_TGDDA_ENABLE))
+		return;
+
+	link_m_frac = REG_FIELD_GET(HDMI_EMP_DATA_LINK_M_FRAC_MASK,
+				    intel_de_read(display, HDMI_EMP_DATA(display, transcoder)));
+
+	if (link_m_frac == m_n->link_m % m_n->link_n)
+		m_n->bypass_m_n_ratio_limit = true;
+}
+
 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
 				    enum transcoder transcoder,
 				    struct intel_link_m_n *m_n)
@@ -3512,6 +3588,8 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
 		intel_get_m_n(display, m_n,
 			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
 			      PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
+
+	bmg_enhanced_tgdda_read(crtc, transcoder, m_n);
 }
 
 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
@@ -5002,7 +5080,8 @@ intel_compare_link_m_n(const struct intel_link_m_n *m_n,
 		m_n->data_m == m2_n2->data_m &&
 		m_n->data_n == m2_n2->data_n &&
 		m_n->link_m == m2_n2->link_m &&
-		m_n->link_n == m2_n2->link_n;
+		m_n->link_n == m2_n2->link_n &&
+		m_n->bypass_m_n_ratio_limit == m2_n2->bypass_m_n_ratio_limit;
 }
 
 static bool
@@ -5277,18 +5356,20 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	if (!intel_compare_link_m_n(&current_config->name, \
 				    &pipe_config->name)) { \
 		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
-				     "(expected tu %i data %i/%i link %i/%i, " \
-				     "found tu %i, data %i/%i link %i/%i)", \
+				     "(expected tu %i data %i/%i link %i/%i m_n_bypass %s, " \
+				     "found tu %i, data %i/%i link %i/%i m_n_bypass %s)", \
 				     current_config->name.tu, \
 				     current_config->name.data_m, \
 				     current_config->name.data_n, \
 				     current_config->name.link_m, \
 				     current_config->name.link_n, \
+				     str_yes_no(current_config->name.bypass_m_n_ratio_limit), \
 				     pipe_config->name.tu, \
 				     pipe_config->name.data_m, \
 				     pipe_config->name.data_n, \
 				     pipe_config->name.link_m, \
-				     pipe_config->name.link_n); \
+				     pipe_config->name.link_n, \
+				     str_yes_no(pipe_config->name.bypass_m_n_ratio_limit)); \
 		ret = false; \
 	} \
 } while (0)
@@ -5436,6 +5517,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_M_N(dp_m2_n2);
 	}
 
+	PIPE_CONF_CHECK_BOOL(dp_m_n.bypass_m_n_ratio_limit);
+
 	PIPE_CONF_CHECK_X(output_types);
 
 	PIPE_CONF_CHECK_I(framestart_delay);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 404168f4213b..55e676655120 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -525,5 +525,7 @@ bool intel_scanout_needs_vtd_wa(struct intel_display *display);
 int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
 void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
 				    int pixel_clock, int link_symbol_clock);
+bool intel_display_can_bypass_m_n_limit(struct intel_display *display,
+					int m_n_ratio, enum pipe pipe);
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 57f388c958b4..81f9661357b6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -550,6 +550,11 @@
 #define _TRANS_MULT_B		0x6102c
 #define TRANS_MULT(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
 
+#define _HDMI_EMP_DATA_A	0x600d8
+#define _HDMI_EMP_DATA_B	0x610d8
+#define  HDMI_EMP_DATA_LINK_M_FRAC_MASK	REG_GENMASK(23, 0)
+#define HDMI_EMP_DATA(display, trans)	_MMIO_TRANS2((display), (trans), _HDMI_EMP_DATA_A)
+
 /* Hotplug control (945+ only) */
 #define PORT_HOTPLUG_EN(dev_priv)		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
 #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
@@ -1192,6 +1197,10 @@
 #define _PIPEB_LINK_N1		0x61044
 #define  PIPE_LINK_N1_EXTENDED_MASK	REG_GENMASK(31, 24)
 #define  PIPE_LINK_N1_EXTENDED(val)	REG_FIELD_PREP(PIPE_LINK_N1_EXTENDED_MASK, (val))
+#define  PIPE_LINK_N1_EXT_CEIL_MASK	REG_GENMASK(7, 4)
+#define  PIPE_LINK_N1_EXT_CEIL(val)	REG_FIELD_PREP(PIPE_LINK_N1_EXT_CEIL_MASK, (val))
+#define  PIPE_LINK_N1_EXT_INT_MASK	REG_GENMASK(3, 0)
+#define  PIPE_LINK_N1_EXT_INT(val)	REG_FIELD_PREP(PIPE_LINK_N1_EXT_INT_MASK, (val))
 #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
 
 #define _PIPEA_LINK_M2		0x60048
@@ -1710,6 +1719,7 @@
 #define   PSR2_ADD_VERTICAL_LINE_COUNT	REG_BIT(15)
 #define   DP_FEC_BS_JITTER_WA		REG_BIT(15)
 #define   PSR2_VSC_ENABLE_PROG_HEADER	REG_BIT(12)
+#define   DP_ENHANCED_TGDDA_ENABLE	REG_BIT(11)
 #define   DP_DSC_INSERT_SF_AT_EOL_WA	REG_BIT(4)
 #define   HDCP_LINE_REKEY_DISABLE	REG_BIT(0)
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index a5f18ac8a7d0..7a5286db977e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -985,6 +985,8 @@ struct intel_link_m_n {
 	u32 data_n;
 	u32 link_m;
 	u32 link_n;
+	/* Wa_14021768792 for linkm/n ratio > 10 */
+	bool bypass_m_n_ratio_limit;
 };
 
 struct intel_csc_matrix {
-- 
2.34.1

Re: [PATCH v4 07/10] drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/display: TGDDA workaround state leaks to HDMI modesets
--

commit 7ca764c5b58c7f2901c9b7de8005ba2561ae1426
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

    drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10
    
    To support a Link M/N ratio between 10.0 and 15.0, for some BMG
    ultrajoiner cases we need Wa_14021768792.
    
    To bypass the hardware limitation within the Timing Generator DDA
    (TGDDA), we need to program the LINKM and LINKN registers as defined in
    the WA. Along with this we also need the relevant bits in HDMI_EMP_DATA
    and CHICKEN_TRANS.

> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 6d2025e109956..1e9d8943626a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
[ ... ]
> @@ -2738,6 +2749,26 @@ bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
>  	return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview;
>  }
>  
> +static void bmg_enhanced_tgdda_write(struct intel_crtc *crtc,
> +				     enum transcoder transcoder,
> +				     const struct intel_link_m_n *m_n)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	bool enable = m_n->bypass_m_n_ratio_limit && m_n->link_n;
> +	u32 link_m_frac = enable ? m_n->link_m % m_n->link_n : 0;
> +
> +	if (!intel_display_wa(display, INTEL_DISPLAY_WA_14021768792))
> +		return;
> +
> +	intel_de_rmw(display, HDMI_EMP_DATA(display, transcoder),
> +		     HDMI_EMP_DATA_LINK_M_FRAC_MASK,
> +		     REG_FIELD_PREP(HDMI_EMP_DATA_LINK_M_FRAC_MASK, link_m_frac));
> +
> +	intel_de_rmw(display, CHICKEN_TRANS(display, transcoder),
> +		     DP_ENHANCED_TGDDA_ENABLE,
> +		     enable ? DP_ENHANCED_TGDDA_ENABLE : 0);
> +}
> +
>  void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
>  				    enum transcoder transcoder,
>  				    const struct intel_link_m_n *m_n)
> @@ -2745,6 +2776,8 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
>  	struct intel_display *display = to_intel_display(crtc);
>  	enum pipe pipe = crtc->pipe;
>  
> +	bmg_enhanced_tgdda_write(crtc, transcoder, m_n);
> +
>  	if (DISPLAY_VER(display) >= 5)

[Severity: Medium]
The commit message states that CHICKEN_TRANS and HDMI_EMP_DATA "are explicitly
cleared when the mechanism is not in use, so that state cannot leak from a
previous modeset." Does this clearing logic work if the transcoder is repurposed
for HDMI?

The clearing logic is placed in bmg_enhanced_tgdda_write(), which is called
exclusively from intel_cpu_transcoder_set_m1_n1().

Looking at hsw_configure_cpu_transcoder(), intel_cpu_transcoder_set_m1_n1() is
only called for DP and FDI encoders:

    } else if (intel_crtc_has_dp_encoder(crtc_state)) {
        intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
                                       &crtc_state->dp_m_n);
        intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
                                       &crtc_state->dp_m2_n2);
    }

If a transcoder is first used for DisplayPort (triggering the workaround and
setting DP_ENHANCED_TGDDA_ENABLE) and subsequently repurposed for HDMI,
intel_cpu_transcoder_set_m1_n1() is completely skipped.

Will the Transcoder's Timing Generator DDA remain in the enhanced DP workaround
mode and potentially corrupt HDMI timings?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260917050649.871960-1-suraj.kandpal@intel.com?part=7

RE: [PATCH v4 07/10] drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10

[Kandpal, Suraj]

> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 6d2025e109956..1e9d8943626a7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> [ ... ]
> > @@ -2738,6 +2749,26 @@ bool intel_cpu_transcoder_has_m2_n2(struct
> intel_display *display,
> >  	return IS_DISPLAY_VER(display, 5, 7) ||
> > display->platform.cherryview;  }
> >
> > +static void bmg_enhanced_tgdda_write(struct intel_crtc *crtc,
> > +				     enum transcoder transcoder,
> > +				     const struct intel_link_m_n *m_n) {
> > +	struct intel_display *display = to_intel_display(crtc);
> > +	bool enable = m_n->bypass_m_n_ratio_limit && m_n->link_n;
> > +	u32 link_m_frac = enable ? m_n->link_m % m_n->link_n : 0;
> > +
> > +	if (!intel_display_wa(display, INTEL_DISPLAY_WA_14021768792))
> > +		return;
> > +
> > +	intel_de_rmw(display, HDMI_EMP_DATA(display, transcoder),
> > +		     HDMI_EMP_DATA_LINK_M_FRAC_MASK,
> > +		     REG_FIELD_PREP(HDMI_EMP_DATA_LINK_M_FRAC_MASK,
> link_m_frac));
> > +
> > +	intel_de_rmw(display, CHICKEN_TRANS(display, transcoder),
> > +		     DP_ENHANCED_TGDDA_ENABLE,
> > +		     enable ? DP_ENHANCED_TGDDA_ENABLE : 0); }
> > +
> >  void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
> >  				    enum transcoder transcoder,
> >  				    const struct intel_link_m_n *m_n) @@ -
> 2745,6 +2776,8 @@ void
> > intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
> >  	struct intel_display *display = to_intel_display(crtc);
> >  	enum pipe pipe = crtc->pipe;
> >
> > +	bmg_enhanced_tgdda_write(crtc, transcoder, m_n);
> > +
> >  	if (DISPLAY_VER(display) >= 5)
> 
> [Severity: Medium]
> The commit message states that CHICKEN_TRANS and HDMI_EMP_DATA "are
> explicitly cleared when the mechanism is not in use, so that state cannot leak
> from a previous modeset." Does this clearing logic work if the transcoder is
> repurposed for HDMI?
> 
> The clearing logic is placed in bmg_enhanced_tgdda_write(), which is called
> exclusively from intel_cpu_transcoder_set_m1_n1().
> 
> Looking at hsw_configure_cpu_transcoder(),
> intel_cpu_transcoder_set_m1_n1() is only called for DP and FDI encoders:
> 
>     } else if (intel_crtc_has_dp_encoder(crtc_state)) {
>         intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
>                                        &crtc_state->dp_m_n);
>         intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
>                                        &crtc_state->dp_m2_n2);
>     }
> 
> If a transcoder is first used for DisplayPort (triggering the workaround and
> setting DP_ENHANCED_TGDDA_ENABLE) and subsequently repurposed for
> HDMI,
> intel_cpu_transcoder_set_m1_n1() is completely skipped.
> 
> Will the Transcoder's Timing Generator DDA remain in the enhanced DP
> workaround mode and potentially corrupt HDMI timings?
> 

Nothing to corrupt though. Bit 11 is only applicable to the DP transcoder, and
HDMI_EMP_DATA only matters when EMP transmission is enabled via HDMI_EMP_CTL,
which we never do - there's no FRL/EMP support in the driver.
It isn't observable in software either, intel_cpu_transcoder_get_m1_n1() is only
called from the DP and DP MST readout paths, so a stale bit never reaches the
crtc state. And the next DP modeset on that transcoder clears it anyway.

Regards,
Suraj Kandpal

> --
> Sashiko AI review · https://sashiko.dev/#/patchset/20260917050649.871960-1-
> suraj.kandpal@intel.com?part=7

RE: [PATCH v4 07/10] drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Suraj
> Kandpal
> Sent: 17 September 2026 10:37
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: [PATCH v4 07/10] drm/i915/display: Add bits for Wa_14021768792
> for linkm/n ratio > 10
> 
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> 
> To support a Link M/N ratio between 10.0 and 15.0, for some BMG ultrajoiner
> cases we need Wa_14021768792.
> 
> To bypass the hardware limitation within the Timing Generator DDA (TGDDA),
> we need to program the LINKM and LINKN registers as defined in the WA.
> Along with this we also need the relevant bits in HDMI_EMP_DATA and
> CHICKEN_TRANS.
> 
> Add the bits for the WA and a new member 'bypass_m_n_ratio_limit' to track
> if we need to bypass the Link M/N ratio limit in the intel_link_m_n structure.
> 
> Per Bspec the extended LINK_N field is two nibbles: bits 27:24 hold INT(Link
> M / Link N) and bits 31:28 hold CEIL(Link M / Link N).
> 
> CHICKEN_TRANS and HDMI_EMP_DATA are programmed before LINK_N,
> since writing LINK_N arms the double buffered update of the M/N registers,
> and all of the programming has to be done before the transcoder is enabled.
> Both are also explicitly cleared when the mechanism is not in use, so that
> state cannot leak from a previous modeset.
> 
> Only bypass_m_n_ratio_limit is compared by the state checker, not the ratio
> integer and fraction themselves. That is deliberate: both are derived from Link
> M and Link N, which are compared already, so the thing worth verifying is
> whether the workaround ended up being applied or not.
> 
> Unlike the rest of the M/N registers, CHICKEN_TRANS and HDMI_EMP_DATA
> are not double buffered, so the flag has to be compared outside the fastset
> exemption that PIPE_CONF_CHECK_M_N() has for update_m_n.
> Otherwise a seamless M/N update could switch the DDA out of the
> workaround on a live transcoder, with the Link M/N values only following at
> the next MSA.
> 
> v2:
> -Drop the drm_WARN_ON() on the extended LINK_N field in intel_get_m_n():
> it is derived from Link M and Link N, so the state checker comparison of those
> and of bypass_m_n_ratio_limit already covers it. (Sashiko) -Compare
> bypass_m_n_ratio_limit unconditionally, so that a change to it forces a full
> modeset instead of being applied during a seamless M/N fastset. (Sashiko)
> 
> Bspec: 49266
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 93 ++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_display.h  |  2 +
> .../gpu/drm/i915/display/intel_display_regs.h | 10 ++
>  .../drm/i915/display/intel_display_types.h    |  2 +
>  4 files changed, 102 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 6d2025e10995..1e9d8943626a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2706,6 +2706,15 @@ void intel_zero_m_n(struct intel_link_m_n *m_n)
>  	m_n->tu = 1;
>  }
> 
> +static u8 bmg_get_link_n_ext(const struct intel_link_m_n *m_n) {
> +	if (!m_n->link_n)
> +		return 0;
> +
> +	return PIPE_LINK_N1_EXT_INT(m_n->link_m / m_n->link_n) |
> +		PIPE_LINK_N1_EXT_CEIL(DIV_ROUND_UP(m_n->link_m,
> m_n->link_n)); }
> +
>  void intel_set_m_n(struct intel_display *display,
>  		   const struct intel_link_m_n *m_n,
>  		   intel_reg_t data_m_reg, intel_reg_t data_n_reg, @@ -
> 2717,7 +2726,9 @@ void intel_set_m_n(struct intel_display *display,
>  	intel_de_write(display, data_n_reg, m_n->data_n);
>  	intel_de_write(display, link_m_reg, m_n->link_m);
> 
> -	if (DISPLAY_VER(display) >= 14)
> +	if (DISPLAY_VER(display) >= 14 && m_n->bypass_m_n_ratio_limit)
> +		link_n |=
> PIPE_LINK_N1_EXTENDED(bmg_get_link_n_ext(m_n));
> +	else if (DISPLAY_VER(display) >= 14)
>  		link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
>  	else
>  		link_n &= DATA_LINK_M_N_MASK;
> @@ -2738,6 +2749,26 @@ bool intel_cpu_transcoder_has_m2_n2(struct
> intel_display *display,
>  	return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview;
> }
> 
> +static void bmg_enhanced_tgdda_write(struct intel_crtc *crtc,
> +				     enum transcoder transcoder,
> +				     const struct intel_link_m_n *m_n) {
> +	struct intel_display *display = to_intel_display(crtc);
> +	bool enable = m_n->bypass_m_n_ratio_limit && m_n->link_n;
> +	u32 link_m_frac = enable ? m_n->link_m % m_n->link_n : 0;
> +
> +	if (!intel_display_wa(display, INTEL_DISPLAY_WA_14021768792))
> +		return;
> +
> +	intel_de_rmw(display, HDMI_EMP_DATA(display, transcoder),
> +		     HDMI_EMP_DATA_LINK_M_FRAC_MASK,
> +		     REG_FIELD_PREP(HDMI_EMP_DATA_LINK_M_FRAC_MASK,
> link_m_frac));
> +
> +	intel_de_rmw(display, CHICKEN_TRANS(display, transcoder),
> +		     DP_ENHANCED_TGDDA_ENABLE,
> +		     enable ? DP_ENHANCED_TGDDA_ENABLE : 0); }
> +
>  void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
>  				    enum transcoder transcoder,
>  				    const struct intel_link_m_n *m_n) @@ -
> 2745,6 +2776,8 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc
> *crtc,
>  	struct intel_display *display = to_intel_display(crtc);
>  	enum pipe pipe = crtc->pipe;
> 
> +	bmg_enhanced_tgdda_write(crtc, transcoder, m_n);
> +
>  	if (DISPLAY_VER(display) >= 5)
>  		intel_set_m_n(display, m_n,
>  			      PIPE_DATA_M1(display, transcoder), @@ -3495,6
> +3528,49 @@ void intel_get_m_n(struct intel_display *display,
>  	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display,
> data_m_reg)) + 1;  }
> 
> +bool intel_display_can_bypass_m_n_limit(struct intel_display *display,
> +					int m_n_ratio,
> +					enum pipe pipe)
> +{
> +	if (!intel_display_wa(display, INTEL_DISPLAY_WA_14021768792))
> +		return false;
> +
> +	if (m_n_ratio > 15)
> +		return false;
> +
> +	if (pipe != PIPE_A)
> +		return false;

Could we check whether this should use the transcoder (TRANSCODER_A) instead of crtc->pipe ?
For ultrajoiner, could the secondary pipes report bypass=false even though their computed state,
copied from the primary, has bypass=true ?

> +
> +	return true;
> +}
> +
> +static void bmg_enhanced_tgdda_read(struct intel_crtc *crtc,
> +				    enum transcoder transcoder,
> +				    struct intel_link_m_n *m_n)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	u32 link_m_frac;
> +	int m_n_ratio;
> +
> +	if (!m_n->link_n)
> +		return;
> +
> +	m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
> +
> +	if (!intel_display_can_bypass_m_n_limit(display, m_n_ratio, crtc-
> >pipe))
> +		return;
> +
> +	if (!(intel_de_read(display, CHICKEN_TRANS(display, transcoder)) &
> +	      DP_ENHANCED_TGDDA_ENABLE))
> +		return;
> +
> +	link_m_frac =
> REG_FIELD_GET(HDMI_EMP_DATA_LINK_M_FRAC_MASK,
> +				    intel_de_read(display,
> HDMI_EMP_DATA(display, transcoder)));
> +
> +	if (link_m_frac == m_n->link_m % m_n->link_n)
> +		m_n->bypass_m_n_ratio_limit = true;
> +}
> +
>  void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
>  				    enum transcoder transcoder,
>  				    struct intel_link_m_n *m_n)
> @@ -3512,6 +3588,8 @@ void intel_cpu_transcoder_get_m1_n1(struct
> intel_crtc *crtc,
>  		intel_get_m_n(display, m_n,
>  			      PIPE_DATA_M_G4X(pipe),
> PIPE_DATA_N_G4X(pipe),
>  			      PIPE_LINK_M_G4X(pipe),
> PIPE_LINK_N_G4X(pipe));
> +
> +	bmg_enhanced_tgdda_read(crtc, transcoder, m_n);
>  }
> 
>  void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, @@ -5002,7
> +5080,8 @@ intel_compare_link_m_n(const struct intel_link_m_n *m_n,
>  		m_n->data_m == m2_n2->data_m &&
>  		m_n->data_n == m2_n2->data_n &&
>  		m_n->link_m == m2_n2->link_m &&
> -		m_n->link_n == m2_n2->link_n;
> +		m_n->link_n == m2_n2->link_n &&
> +		m_n->bypass_m_n_ratio_limit == m2_n2-
> >bypass_m_n_ratio_limit;
>  }
> 
>  static bool
> @@ -5277,18 +5356,20 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>  	if (!intel_compare_link_m_n(&current_config->name, \
>  				    &pipe_config->name)) { \
>  		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
> -				     "(expected tu %i data %i/%i link %i/%i, " \
> -				     "found tu %i, data %i/%i link %i/%i)", \
> +				     "(expected tu %i data %i/%i link %i/%i
> m_n_bypass %s, " \
> +				     "found tu %i, data %i/%i link %i/%i
> m_n_bypass %s)", \
>  				     current_config->name.tu, \
>  				     current_config->name.data_m, \
>  				     current_config->name.data_n, \
>  				     current_config->name.link_m, \
>  				     current_config->name.link_n, \
> +				     str_yes_no(current_config-
> >name.bypass_m_n_ratio_limit), \
>  				     pipe_config->name.tu, \
>  				     pipe_config->name.data_m, \
>  				     pipe_config->name.data_n, \
>  				     pipe_config->name.link_m, \
> -				     pipe_config->name.link_n); \
> +				     pipe_config->name.link_n, \
> +				     str_yes_no(pipe_config-
> >name.bypass_m_n_ratio_limit)); \
>  		ret = false; \
>  	} \
>  } while (0)
> @@ -5436,6 +5517,8 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>  		PIPE_CONF_CHECK_M_N(dp_m2_n2);
>  	}
> 
> +	PIPE_CONF_CHECK_BOOL(dp_m_n.bypass_m_n_ratio_limit);

The flag is compared twice. The unconditional BOOL check is enough.

Please also print it in intel_crtc_state_dump().

> +
>  	PIPE_CONF_CHECK_X(output_types);
> 
>  	PIPE_CONF_CHECK_I(framestart_delay);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 404168f4213b..55e676655120 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -525,5 +525,7 @@ bool intel_scanout_needs_vtd_wa(struct
> intel_display *display);  int intel_crtc_num_joined_pipes(const struct
> intel_crtc_state *crtc_state);  void intel_display_compute_link_m_n(u32
> *link_m, u32 *link_n,
>  				    int pixel_clock, int link_symbol_clock);
> +bool intel_display_can_bypass_m_n_limit(struct intel_display *display,
> +					int m_n_ratio, enum pipe pipe);
> 
>  #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 57f388c958b4..81f9661357b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -550,6 +550,11 @@
>  #define _TRANS_MULT_B		0x6102c
>  #define TRANS_MULT(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans),
> _TRANS_MULT_A)
> 
> +#define _HDMI_EMP_DATA_A	0x600d8
> +#define _HDMI_EMP_DATA_B	0x610d8
> +#define  HDMI_EMP_DATA_LINK_M_FRAC_MASK	REG_GENMASK(23, 0)
> +#define HDMI_EMP_DATA(display, trans)	_MMIO_TRANS2((display),
> (trans), _HDMI_EMP_DATA_A)
> +
>  /* Hotplug control (945+ only) */
>  #define PORT_HOTPLUG_EN(dev_priv)
> 	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
>  #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
> @@ -1192,6 +1197,10 @@
>  #define _PIPEB_LINK_N1		0x61044
>  #define  PIPE_LINK_N1_EXTENDED_MASK	REG_GENMASK(31, 24)
>  #define  PIPE_LINK_N1_EXTENDED(val)
> 	REG_FIELD_PREP(PIPE_LINK_N1_EXTENDED_MASK, (val))
> +#define  PIPE_LINK_N1_EXT_CEIL_MASK	REG_GENMASK(7, 4)
> +#define  PIPE_LINK_N1_EXT_CEIL(val)
> 	REG_FIELD_PREP(PIPE_LINK_N1_EXT_CEIL_MASK, (val))
> +#define  PIPE_LINK_N1_EXT_INT_MASK	REG_GENMASK(3, 0)
> +#define  PIPE_LINK_N1_EXT_INT(val)
> 	REG_FIELD_PREP(PIPE_LINK_N1_EXT_INT_MASK, (val))
>  #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
> _PIPEA_LINK_N1)
> 
>  #define _PIPEA_LINK_M2		0x60048
> @@ -1710,6 +1719,7 @@
>  #define   PSR2_ADD_VERTICAL_LINE_COUNT	REG_BIT(15)
>  #define   DP_FEC_BS_JITTER_WA		REG_BIT(15)
>  #define   PSR2_VSC_ENABLE_PROG_HEADER	REG_BIT(12)
> +#define   DP_ENHANCED_TGDDA_ENABLE	REG_BIT(11)
>  #define   DP_DSC_INSERT_SF_AT_EOL_WA	REG_BIT(4)
>  #define   HDCP_LINE_REKEY_DISABLE	REG_BIT(0)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index a5f18ac8a7d0..7a5286db977e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -985,6 +985,8 @@ struct intel_link_m_n {
>  	u32 data_n;
>  	u32 link_m;
>  	u32 link_n;
> +	/* Wa_14021768792 for linkm/n ratio > 10 */
> +	bool bypass_m_n_ratio_limit;
>  };
> 
>  struct intel_csc_matrix {
> --
> 2.34.1

RE: [PATCH v4 07/10] drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10

[Kandpal, Suraj]

> -----Original Message-----
> From: Golani, Mitulkumar Ajitkumar
> <mitulkumar.ajitkumar.golani@intel.com>
> Sent: 16 October 2026 02:08
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: RE: [PATCH v4 07/10] drm/i915/display: Add bits for
> Wa_14021768792 for linkm/n ratio > 10
> 
> 
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> > Suraj Kandpal
> > Sent: 17 September 2026 10:37
> > To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> > <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> > Subject: [PATCH v4 07/10] drm/i915/display: Add bits for
> > Wa_14021768792 for linkm/n ratio > 10
> >
> > From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >
> > To support a Link M/N ratio between 10.0 and 15.0, for some BMG
> > ultrajoiner cases we need Wa_14021768792.
> >
> > To bypass the hardware limitation within the Timing Generator DDA
> > (TGDDA), we need to program the LINKM and LINKN registers as defined in
> the WA.
> > Along with this we also need the relevant bits in HDMI_EMP_DATA and
> > CHICKEN_TRANS.
> >
> > Add the bits for the WA and a new member 'bypass_m_n_ratio_limit' to
> > track if we need to bypass the Link M/N ratio limit in the intel_link_m_n
> structure.
> >
> > Per Bspec the extended LINK_N field is two nibbles: bits 27:24 hold
> > INT(Link M / Link N) and bits 31:28 hold CEIL(Link M / Link N).
> >
> > CHICKEN_TRANS and HDMI_EMP_DATA are programmed before LINK_N,
> since
> > writing LINK_N arms the double buffered update of the M/N registers,
> > and all of the programming has to be done before the transcoder is
> enabled.
> > Both are also explicitly cleared when the mechanism is not in use, so
> > that state cannot leak from a previous modeset.
> >
> > Only bypass_m_n_ratio_limit is compared by the state checker, not the
> > ratio integer and fraction themselves. That is deliberate: both are
> > derived from Link M and Link N, which are compared already, so the
> > thing worth verifying is whether the workaround ended up being applied
> or not.
> >
> > Unlike the rest of the M/N registers, CHICKEN_TRANS and
> HDMI_EMP_DATA
> > are not double buffered, so the flag has to be compared outside the
> > fastset exemption that PIPE_CONF_CHECK_M_N() has for update_m_n.
> > Otherwise a seamless M/N update could switch the DDA out of the
> > workaround on a live transcoder, with the Link M/N values only
> > following at the next MSA.
> >
> > v2:
> > -Drop the drm_WARN_ON() on the extended LINK_N field in
> intel_get_m_n():
> > it is derived from Link M and Link N, so the state checker comparison
> > of those and of bypass_m_n_ratio_limit already covers it. (Sashiko)
> > -Compare bypass_m_n_ratio_limit unconditionally, so that a change to
> > it forces a full modeset instead of being applied during a seamless
> > M/N fastset. (Sashiko)
> >
> > Bspec: 49266
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c  | 93
> > ++++++++++++++++++- drivers/gpu/drm/i915/display/intel_display.h  |  2
> > + .../gpu/drm/i915/display/intel_display_regs.h | 10 ++
> >  .../drm/i915/display/intel_display_types.h    |  2 +
> >  4 files changed, 102 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 6d2025e10995..1e9d8943626a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -2706,6 +2706,15 @@ void intel_zero_m_n(struct intel_link_m_n
> *m_n)
> >  	m_n->tu = 1;
> >  }
> >
> > +static u8 bmg_get_link_n_ext(const struct intel_link_m_n *m_n) {
> > +	if (!m_n->link_n)
> > +		return 0;
> > +
> > +	return PIPE_LINK_N1_EXT_INT(m_n->link_m / m_n->link_n) |
> > +		PIPE_LINK_N1_EXT_CEIL(DIV_ROUND_UP(m_n->link_m,
> > m_n->link_n)); }
> > +
> >  void intel_set_m_n(struct intel_display *display,
> >  		   const struct intel_link_m_n *m_n,
> >  		   intel_reg_t data_m_reg, intel_reg_t data_n_reg, @@ -
> > 2717,7 +2726,9 @@ void intel_set_m_n(struct intel_display *display,
> >  	intel_de_write(display, data_n_reg, m_n->data_n);
> >  	intel_de_write(display, link_m_reg, m_n->link_m);
> >
> > -	if (DISPLAY_VER(display) >= 14)
> > +	if (DISPLAY_VER(display) >= 14 && m_n->bypass_m_n_ratio_limit)
> > +		link_n |=
> > PIPE_LINK_N1_EXTENDED(bmg_get_link_n_ext(m_n));
> > +	else if (DISPLAY_VER(display) >= 14)
> >  		link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
> >  	else
> >  		link_n &= DATA_LINK_M_N_MASK;
> > @@ -2738,6 +2749,26 @@ bool intel_cpu_transcoder_has_m2_n2(struct
> > intel_display *display,
> >  	return IS_DISPLAY_VER(display, 5, 7) ||
> > display->platform.cherryview; }
> >
> > +static void bmg_enhanced_tgdda_write(struct intel_crtc *crtc,
> > +				     enum transcoder transcoder,
> > +				     const struct intel_link_m_n *m_n) {
> > +	struct intel_display *display = to_intel_display(crtc);
> > +	bool enable = m_n->bypass_m_n_ratio_limit && m_n->link_n;
> > +	u32 link_m_frac = enable ? m_n->link_m % m_n->link_n : 0;
> > +
> > +	if (!intel_display_wa(display, INTEL_DISPLAY_WA_14021768792))
> > +		return;
> > +
> > +	intel_de_rmw(display, HDMI_EMP_DATA(display, transcoder),
> > +		     HDMI_EMP_DATA_LINK_M_FRAC_MASK,
> > +		     REG_FIELD_PREP(HDMI_EMP_DATA_LINK_M_FRAC_MASK,
> > link_m_frac));
> > +
> > +	intel_de_rmw(display, CHICKEN_TRANS(display, transcoder),
> > +		     DP_ENHANCED_TGDDA_ENABLE,
> > +		     enable ? DP_ENHANCED_TGDDA_ENABLE : 0); }
> > +
> >  void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
> >  				    enum transcoder transcoder,
> >  				    const struct intel_link_m_n *m_n) @@ -
> > 2745,6 +2776,8 @@ void intel_cpu_transcoder_set_m1_n1(struct
> > intel_crtc *crtc,
> >  	struct intel_display *display = to_intel_display(crtc);
> >  	enum pipe pipe = crtc->pipe;
> >
> > +	bmg_enhanced_tgdda_write(crtc, transcoder, m_n);
> > +
> >  	if (DISPLAY_VER(display) >= 5)
> >  		intel_set_m_n(display, m_n,
> >  			      PIPE_DATA_M1(display, transcoder), @@ -3495,6
> > +3528,49 @@ void intel_get_m_n(struct intel_display *display,
> >  	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display,
> > data_m_reg)) + 1;  }
> >
> > +bool intel_display_can_bypass_m_n_limit(struct intel_display *display,
> > +					int m_n_ratio,
> > +					enum pipe pipe)
> > +{
> > +	if (!intel_display_wa(display, INTEL_DISPLAY_WA_14021768792))
> > +		return false;
> > +
> > +	if (m_n_ratio > 15)
> > +		return false;
> > +
> > +	if (pipe != PIPE_A)
> > +		return false;
> 
> Could we check whether this should use the transcoder (TRANSCODER_A)
> instead of crtc->pipe ?

Sure will move check t
> For ultrajoiner, could the secondary pipes report bypass=false even though
> their computed state, copied from the primary, has bypass=true ?
> 
> > +
> > +	return true;
> > +}
> > +
> > +static void bmg_enhanced_tgdda_read(struct intel_crtc *crtc,
> > +				    enum transcoder transcoder,
> > +				    struct intel_link_m_n *m_n)
> > +{
> > +	struct intel_display *display = to_intel_display(crtc);
> > +	u32 link_m_frac;
> > +	int m_n_ratio;
> > +
> > +	if (!m_n->link_n)
> > +		return;
> > +
> > +	m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
> > +
> > +	if (!intel_display_can_bypass_m_n_limit(display, m_n_ratio, crtc-
> > >pipe))
> > +		return;
> > +
> > +	if (!(intel_de_read(display, CHICKEN_TRANS(display, transcoder)) &
> > +	      DP_ENHANCED_TGDDA_ENABLE))
> > +		return;
> > +
> > +	link_m_frac =
> > REG_FIELD_GET(HDMI_EMP_DATA_LINK_M_FRAC_MASK,
> > +				    intel_de_read(display,
> > HDMI_EMP_DATA(display, transcoder)));
> > +
> > +	if (link_m_frac == m_n->link_m % m_n->link_n)
> > +		m_n->bypass_m_n_ratio_limit = true; }
> > +
> >  void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
> >  				    enum transcoder transcoder,
> >  				    struct intel_link_m_n *m_n)
> > @@ -3512,6 +3588,8 @@ void intel_cpu_transcoder_get_m1_n1(struct
> > intel_crtc *crtc,
> >  		intel_get_m_n(display, m_n,
> >  			      PIPE_DATA_M_G4X(pipe),
> > PIPE_DATA_N_G4X(pipe),
> >  			      PIPE_LINK_M_G4X(pipe),
> > PIPE_LINK_N_G4X(pipe));
> > +
> > +	bmg_enhanced_tgdda_read(crtc, transcoder, m_n);
> >  }
> >
> >  void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, @@
> > -5002,7
> > +5080,8 @@ intel_compare_link_m_n(const struct intel_link_m_n *m_n,
> >  		m_n->data_m == m2_n2->data_m &&
> >  		m_n->data_n == m2_n2->data_n &&
> >  		m_n->link_m == m2_n2->link_m &&
> > -		m_n->link_n == m2_n2->link_n;
> > +		m_n->link_n == m2_n2->link_n &&
> > +		m_n->bypass_m_n_ratio_limit == m2_n2-
> > >bypass_m_n_ratio_limit;
> >  }
> >
> >  static bool
> > @@ -5277,18 +5356,20 @@ intel_pipe_config_compare(const struct
> > intel_crtc_state *current_config,
> >  	if (!intel_compare_link_m_n(&current_config->name, \
> >  				    &pipe_config->name)) { \
> >  		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
> > -				     "(expected tu %i data %i/%i link %i/%i, " \
> > -				     "found tu %i, data %i/%i link %i/%i)", \
> > +				     "(expected tu %i data %i/%i link %i/%i
> > m_n_bypass %s, " \
> > +				     "found tu %i, data %i/%i link %i/%i
> > m_n_bypass %s)", \
> >  				     current_config->name.tu, \
> >  				     current_config->name.data_m, \
> >  				     current_config->name.data_n, \
> >  				     current_config->name.link_m, \
> >  				     current_config->name.link_n, \
> > +				     str_yes_no(current_config-
> > >name.bypass_m_n_ratio_limit), \
> >  				     pipe_config->name.tu, \
> >  				     pipe_config->name.data_m, \
> >  				     pipe_config->name.data_n, \
> >  				     pipe_config->name.link_m, \
> > -				     pipe_config->name.link_n); \
> > +				     pipe_config->name.link_n, \
> > +				     str_yes_no(pipe_config-
> > >name.bypass_m_n_ratio_limit)); \
> >  		ret = false; \
> >  	} \
> >  } while (0)
> > @@ -5436,6 +5517,8 @@ intel_pipe_config_compare(const struct
> > intel_crtc_state *current_config,
> >  		PIPE_CONF_CHECK_M_N(dp_m2_n2);
> >  	}
> >
> > +	PIPE_CONF_CHECK_BOOL(dp_m_n.bypass_m_n_ratio_limit);
> 
> The flag is compared twice. The unconditional BOOL check is enough.

Sure will do it 

> 
> Please also print it in intel_crtc_state_dump().

Will add it.

Regards,
Suraj Kandpal

> 
> > +
> >  	PIPE_CONF_CHECK_X(output_types);
> >
> >  	PIPE_CONF_CHECK_I(framestart_delay);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> > b/drivers/gpu/drm/i915/display/intel_display.h
> > index 404168f4213b..55e676655120 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > @@ -525,5 +525,7 @@ bool intel_scanout_needs_vtd_wa(struct
> > intel_display *display);  int intel_crtc_num_joined_pipes(const struct
> > intel_crtc_state *crtc_state);  void
> > intel_display_compute_link_m_n(u32
> > *link_m, u32 *link_n,
> >  				    int pixel_clock, int link_symbol_clock);
> > +bool intel_display_can_bypass_m_n_limit(struct intel_display *display,
> > +					int m_n_ratio, enum pipe pipe);
> >
> >  #endif
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 57f388c958b4..81f9661357b6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -550,6 +550,11 @@
> >  #define _TRANS_MULT_B		0x6102c
> >  #define TRANS_MULT(dev_priv, trans)	_MMIO_TRANS2(dev_priv,
> (trans),
> > _TRANS_MULT_A)
> >
> > +#define _HDMI_EMP_DATA_A	0x600d8
> > +#define _HDMI_EMP_DATA_B	0x610d8
> > +#define  HDMI_EMP_DATA_LINK_M_FRAC_MASK	REG_GENMASK(23, 0)
> > +#define HDMI_EMP_DATA(display, trans)	_MMIO_TRANS2((display),
> > (trans), _HDMI_EMP_DATA_A)
> > +
> >  /* Hotplug control (945+ only) */
> >  #define PORT_HOTPLUG_EN(dev_priv)
> > 	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
> >  #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
> > @@ -1192,6 +1197,10 @@
> >  #define _PIPEB_LINK_N1		0x61044
> >  #define  PIPE_LINK_N1_EXTENDED_MASK	REG_GENMASK(31, 24)
> >  #define  PIPE_LINK_N1_EXTENDED(val)
> > 	REG_FIELD_PREP(PIPE_LINK_N1_EXTENDED_MASK, (val))
> > +#define  PIPE_LINK_N1_EXT_CEIL_MASK	REG_GENMASK(7, 4)
> > +#define  PIPE_LINK_N1_EXT_CEIL(val)
> > 	REG_FIELD_PREP(PIPE_LINK_N1_EXT_CEIL_MASK, (val))
> > +#define  PIPE_LINK_N1_EXT_INT_MASK	REG_GENMASK(3, 0)
> > +#define  PIPE_LINK_N1_EXT_INT(val)
> > 	REG_FIELD_PREP(PIPE_LINK_N1_EXT_INT_MASK, (val))  #define
> > PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
> > _PIPEA_LINK_N1)
> >
> >  #define _PIPEA_LINK_M2		0x60048
> > @@ -1710,6 +1719,7 @@
> >  #define   PSR2_ADD_VERTICAL_LINE_COUNT	REG_BIT(15)
> >  #define   DP_FEC_BS_JITTER_WA		REG_BIT(15)
> >  #define   PSR2_VSC_ENABLE_PROG_HEADER	REG_BIT(12)
> > +#define   DP_ENHANCED_TGDDA_ENABLE	REG_BIT(11)
> >  #define   DP_DSC_INSERT_SF_AT_EOL_WA	REG_BIT(4)
> >  #define   HDCP_LINE_REKEY_DISABLE	REG_BIT(0)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index a5f18ac8a7d0..7a5286db977e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -985,6 +985,8 @@ struct intel_link_m_n {
> >  	u32 data_n;
> >  	u32 link_m;
> >  	u32 link_n;
> > +	/* Wa_14021768792 for linkm/n ratio > 10 */
> > +	bool bypass_m_n_ratio_limit;
> >  };
> >
> >  struct intel_csc_matrix {
> > --
> > 2.34.1

[PATCH v4 08/10] drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n ratio > 10

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Handle the bypass logic for the M/N ratio limit for DP.
Calculate the M/N ratio, check if it can bypass the limit, and set the
appropriate flags for the workaround.

v2:
-Restrict the workaround to 128b/132b links.
-Clear bypass_m_n_ratio_limit on entry, so a rejected link rate cannot
leave it set for the rate that gets used. (Sashiko)

Bspec: 49266
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 31 +++++++++++++++++++++----
 1 file changed, 26 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index fbfc00101886..9c327008b733 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3373,6 +3373,9 @@ static bool can_enable_drrs(struct intel_connector *connector,
 	if (pipe_config->vrr.enable)
 		return false;
 
+	if (pipe_config->dp_m_n.bypass_m_n_ratio_limit)
+		return false;
+
 	/*
 	 * DRRS and PSR can't be enable together, so giving preference to PSR
 	 * as it allows more power-savings by complete shutting down display,
@@ -3397,18 +3400,35 @@ void intel_dp_check_m_n_ratio(struct intel_crtc_state *crtc_state,
 			      struct intel_link_m_n *m_n)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
 	int m_n_ratio;
 
-	if (!m_n || !m_n->link_n)
+	if (!m_n)
+		return;
+
+	m_n->bypass_m_n_ratio_limit = false;
+
+	if (!m_n->link_n)
 		return;
 
 	m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
 
-	if (m_n_ratio > max_m_n_ratio)
+	if (m_n_ratio <= max_m_n_ratio)
+		return;
+
+	if (intel_dp_is_uhbr(crtc_state) &&
+	    intel_display_can_bypass_m_n_limit(display, m_n_ratio, crtc->pipe)) {
+		m_n->bypass_m_n_ratio_limit = true;
 		drm_dbg_kms(display->drm,
-			    "Link M/N ratio (%d) exceeds max allowed (%d)\n",
-			    m_n_ratio, max_m_n_ratio);
+			    "Bypassing Link_m/Link_n ratio limit (ratio %d)\n",
+			    m_n_ratio);
+		return;
+	}
+
+	drm_dbg_kms(display->drm,
+		    "Link M/N ratio (%d) exceeds max allowed (%d)\n",
+		    m_n_ratio, max_m_n_ratio);
 }
 
 static void
@@ -3425,7 +3445,8 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
 	 * FIXME all joined pipes share the same transcoder.
 	 * Need to account for that when updating M/N live.
 	 */
-	if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes)
+	if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes &&
+	    !pipe_config->dp_m_n.bypass_m_n_ratio_limit)
 		pipe_config->update_m_n = true;
 
 	if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
-- 
2.34.1

RE: [PATCH v4 08/10] drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n ratio > 10

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Suraj
> Kandpal
> Sent: 17 September 2026 10:37
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: [PATCH v4 08/10] drm/i915/display: Implement Wa_14021768792 for
> BMG DP for link_m/n ratio > 10
> 
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> 
> Handle the bypass logic for the M/N ratio limit for DP.
> Calculate the M/N ratio, check if it can bypass the limit, and set the
> appropriate flags for the workaround.
> 
> v2:
> -Restrict the workaround to 128b/132b links.
> -Clear bypass_m_n_ratio_limit on entry, so a rejected link rate cannot leave it
> set for the rate that gets used. (Sashiko)
> 
> Bspec: 49266
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 31 +++++++++++++++++++++----
>  1 file changed, 26 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index fbfc00101886..9c327008b733 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3373,6 +3373,9 @@ static bool can_enable_drrs(struct intel_connector
> *connector,
>  	if (pipe_config->vrr.enable)
>  		return false;
> 
> +	if (pipe_config->dp_m_n.bypass_m_n_ratio_limit)
> +		return false;
> +
>  	/*
>  	 * DRRS and PSR can't be enable together, so giving preference to PSR
>  	 * as it allows more power-savings by complete shutting down
> display, @@ -3397,18 +3400,35 @@ void intel_dp_check_m_n_ratio(struct
> intel_crtc_state *crtc_state,
>  			      struct intel_link_m_n *m_n)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
>  	int m_n_ratio;
> 
> -	if (!m_n || !m_n->link_n)
> +	if (!m_n)
> +		return;
> +
> +	m_n->bypass_m_n_ratio_limit = false;
> +
> +	if (!m_n->link_n)
>  		return;

Should bypass_m_n_ratio_limit be set where the link M/N and limits are computed,
keeping this function log-only? Also, as noted in the previous patch review, could the
if (!m_n) check be dead code?
> 
>  	m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
> 
> -	if (m_n_ratio > max_m_n_ratio)
> +	if (m_n_ratio <= max_m_n_ratio)
> +		return;
> +
> +	if (intel_dp_is_uhbr(crtc_state) &&
> +	    intel_display_can_bypass_m_n_limit(display, m_n_ratio, crtc-
> >pipe)) {
> +		m_n->bypass_m_n_ratio_limit = true;
>  		drm_dbg_kms(display->drm,
> -			    "Link M/N ratio (%d) exceeds max allowed (%d)\n",
> -			    m_n_ratio, max_m_n_ratio);
> +			    "Bypassing Link_m/Link_n ratio limit (ratio %d)\n",
> +			    m_n_ratio);
> +		return;
> +	}
> +
> +	drm_dbg_kms(display->drm,
> +		    "Link M/N ratio (%d) exceeds max allowed (%d)\n",
> +		    m_n_ratio, max_m_n_ratio);
>  }

Could the ratio limit also be adjusted in the prediction and mode validation paths when
Wa_14021768792 applies? Otherwise, won't configurations with ratios above 10 be
rejected before this workaround can take effect?

> 
>  static void
> @@ -3425,7 +3445,8 @@ intel_dp_drrs_compute_config(struct
> intel_connector *connector,
>  	 * FIXME all joined pipes share the same transcoder.
>  	 * Need to account for that when updating M/N live.
>  	 */
> -	if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes)
> +	if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes &&
> +	    !pipe_config->dp_m_n.bypass_m_n_ratio_limit)
>  		pipe_config->update_m_n = true;
> 
>  	if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
> --
> 2.34.1

RE: [PATCH v4 08/10] drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n ratio > 10

[Kandpal, Suraj]

> -----Original Message-----
> From: Golani, Mitulkumar Ajitkumar
> <mitulkumar.ajitkumar.golani@intel.com>
> Sent: 16 October 2026 01:54
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: RE: [PATCH v4 08/10] drm/i915/display: Implement
> Wa_14021768792 for BMG DP for link_m/n ratio > 10
> 
> 
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> > Suraj Kandpal
> > Sent: 17 September 2026 10:37
> > To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> > <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> > Subject: [PATCH v4 08/10] drm/i915/display: Implement Wa_14021768792
> > for BMG DP for link_m/n ratio > 10
> >
> > From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >
> > Handle the bypass logic for the M/N ratio limit for DP.
> > Calculate the M/N ratio, check if it can bypass the limit, and set the
> > appropriate flags for the workaround.
> >
> > v2:
> > -Restrict the workaround to 128b/132b links.
> > -Clear bypass_m_n_ratio_limit on entry, so a rejected link rate cannot
> > leave it set for the rate that gets used. (Sashiko)
> >
> > Bspec: 49266
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 31
> > +++++++++++++++++++++----
> >  1 file changed, 26 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index fbfc00101886..9c327008b733 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -3373,6 +3373,9 @@ static bool can_enable_drrs(struct
> > intel_connector *connector,
> >  	if (pipe_config->vrr.enable)
> >  		return false;
> >
> > +	if (pipe_config->dp_m_n.bypass_m_n_ratio_limit)
> > +		return false;
> > +
> >  	/*
> >  	 * DRRS and PSR can't be enable together, so giving preference to PSR
> >  	 * as it allows more power-savings by complete shutting down
> > display, @@ -3397,18 +3400,35 @@ void intel_dp_check_m_n_ratio(struct
> > intel_crtc_state *crtc_state,
> >  			      struct intel_link_m_n *m_n)
> >  {
> >  	struct intel_display *display = to_intel_display(crtc_state);
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >  	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
> >  	int m_n_ratio;
> >
> > -	if (!m_n || !m_n->link_n)
> > +	if (!m_n)
> > +		return;
> > +
> > +	m_n->bypass_m_n_ratio_limit = false;
> > +
> > +	if (!m_n->link_n)
> >  		return;
> 
> Should bypass_m_n_ratio_limit be set where the link M/N and limits are
> computed, keeping this function log-only? 

The final link rate isn't known when the limits are computed, the filter only
narrows the options. And intel_link_compute_m_n()
has no crtc_state, so I'd rather not put DP/WA logic in there. The check is
called right after each DP link M/N compute (SST and MTP), so it's effectively
in the same place.


> Also, as noted in the previous
> patch review, could the if (!m_n) check be dead code?

Sure will remove that 


> >
> >  	m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
> >
> > -	if (m_n_ratio > max_m_n_ratio)
> > +	if (m_n_ratio <= max_m_n_ratio)
> > +		return;
> > +
> > +	if (intel_dp_is_uhbr(crtc_state) &&
> > +	    intel_display_can_bypass_m_n_limit(display, m_n_ratio, crtc-
> > >pipe)) {
> > +		m_n->bypass_m_n_ratio_limit = true;
> >  		drm_dbg_kms(display->drm,
> > -			    "Link M/N ratio (%d) exceeds max allowed (%d)\n",
> > -			    m_n_ratio, max_m_n_ratio);
> > +			    "Bypassing Link_m/Link_n ratio limit (ratio %d)\n",
> > +			    m_n_ratio);
> > +		return;
> > +	}
> > +
> > +	drm_dbg_kms(display->drm,
> > +		    "Link M/N ratio (%d) exceeds max allowed (%d)\n",
> > +		    m_n_ratio, max_m_n_ratio);
> >  }
> 
> Could the ratio limit also be adjusted in the prediction and mode validation
> paths when
> Wa_14021768792 applies? Otherwise, won't configurations with ratios above
> 10 be rejected before this workaround can take effect?

Done in the next patch, which extends intel_dp_can_support_m_n() for
the WA. Kept it in that order on purpose so the programming is in place before
the filter lets ratios above 10 through, otherwise a bisect could land on a
config that's programmed without the WA.

Regards,
Suraj Kandpal

> 
> >
> >  static void
> > @@ -3425,7 +3445,8 @@ intel_dp_drrs_compute_config(struct
> > intel_connector *connector,
> >  	 * FIXME all joined pipes share the same transcoder.
> >  	 * Need to account for that when updating M/N live.
> >  	 */
> > -	if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes)
> > +	if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes &&
> > +	    !pipe_config->dp_m_n.bypass_m_n_ratio_limit)
> >  		pipe_config->update_m_n = true;
> >
> >  	if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
> > --
> > 2.34.1

[PATCH v4 09/10] drm/i915/dp: Extend intel_dp_can_support_m_n() for BMG M/N bypass

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

On BMG platforms, the standard M/N ratio limit of 10 can be bypassed
under specific conditions, as permitted by hardware capabilities.

Modify the helper intel_dp_can_support_m_n() to account for this by
checking whether the platform supports bypassing the limit. The
workaround is only intended for 128b/132b links, so restrict it to
those.

During the mode_valid phase, the check assumes that PIPE_A will be used,
to allow the mode where the M/N ratio is within the limits for the
workaround.

v2:
-Keep the helper static: the MST mode_valid now goes through the shared
intel_dp_mode_valid_m_n() rather than calling it directly, so it no
longer needs to be exported.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9c327008b733..9af525e9b58d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1277,9 +1277,11 @@ intel_dp_get_max_m_n_ratio(struct intel_display *display)
 
 static bool
 intel_dp_can_support_m_n(struct intel_display *display,
+			 const struct intel_crtc_state *crtc_state,
 			 int pixel_clock, int link_rate)
 {
 	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
+	enum pipe pipe = PIPE_A;
 	u32 link_m, link_n;
 	int m_n_ratio;
 
@@ -1291,7 +1293,16 @@ intel_dp_can_support_m_n(struct intel_display *display,
 
 	m_n_ratio = DIV_ROUND_UP(link_m, link_n);
 
-	return m_n_ratio <= max_m_n_ratio;
+	if (m_n_ratio <= max_m_n_ratio)
+		return true;
+
+	if (!drm_dp_is_uhbr_rate(link_rate))
+		return false;
+
+	if (crtc_state)
+		pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
+
+	return intel_display_can_bypass_m_n_limit(display, m_n_ratio, pipe);
 }
 
 static int intel_dp_mso_pixel_clock(struct intel_dp *intel_dp, int pixel_clock)
@@ -1352,7 +1363,7 @@ bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock)
 	intel_dp_link_caps_iter_start(&iter, intel_dp->link.caps, order,
 				      INTEL_DP_LINK_CAPS_FILTER_ALL);
 	for_each_dp_link_config(&iter, &link_config) {
-		if (intel_dp_can_support_m_n(display, m_n_pixel_clock,
+		if (intel_dp_can_support_m_n(display, NULL, m_n_pixel_clock,
 					     link_config.rate)) {
 			found = true;
 
@@ -2741,7 +2752,8 @@ intel_dp_compute_m_n_ratio_limits(struct intel_dp *intel_dp,
 
 	intel_dp_link_caps_iter_start(&iter, link_caps, order, limits->link_config_filter);
 	for_each_dp_link_config(&iter, &link_config) {
-		if (!intel_dp_can_support_m_n(display, pixel_clock, link_config.rate))
+		if (!intel_dp_can_support_m_n(display, crtc_state, pixel_clock,
+					      link_config.rate))
 			continue;
 
 		intel_dp_link_caps_filter_add(link_caps, &new_filter, &link_config);
-- 
2.34.1

[PATCH v4 10/10] drm/i915/dp: Bump the max Link M/N ratio to 22 for DISPLAY_VER >= 35

[Suraj Kandpal]

Starting Xe3p max M/N ratio has been increased to 22.

Bspec: 68922
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9af525e9b58d..2f1b7e481d31 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1269,6 +1269,9 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
 static int
 intel_dp_get_max_m_n_ratio(struct intel_display *display)
 {
+	if (DISPLAY_VER(display) >= 35)
+		return 22;
+
 	if (display->platform.dg2)
 		return 4;
 
-- 
2.34.1

✓ CI.KUnit: success for Implement Wa_14021768792 to bypass m_n ratio limit (rev9)

[Patchwork]

== Series Details ==

Series: Implement Wa_14021768792 to bypass m_n ratio limit (rev9)
URL   : https://patchwork.freedesktop.org/series/138256/
State : success

== Summary ==

+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[05:13:46] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:13:50] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:14:11] Starting KUnit Kernel (1/1)...
[05:14:11] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:14:11] ============= refcount_interrupt (4 subtests) ==============
[05:14:11] [PASSED] test_single_irq_change
[05:14:11] [PASSED] test_nested_irq_change
[05:14:11] [PASSED] test_multiple_irq_change
[05:14:11] [PASSED] test_irq_save
[05:14:11] =============== [PASSED] refcount_interrupt ================
[05:14:11] ================= gpu_buddy (14 subtests) ==================
[05:14:11] [PASSED] gpu_test_buddy_alloc_limit
[05:14:11] [PASSED] gpu_test_buddy_alloc_optimistic
[05:14:11] [PASSED] gpu_test_buddy_alloc_pessimistic
[05:14:11] [PASSED] gpu_test_buddy_alloc_pathological
[05:14:11] [PASSED] gpu_test_buddy_alloc_contiguous
[05:14:11] [PASSED] gpu_test_buddy_alloc_clear
[05:14:11] [PASSED] gpu_test_buddy_alloc_range
[05:14:11] [PASSED] gpu_test_buddy_alloc_range_bias
[05:14:12] [PASSED] gpu_test_buddy_fragmentation_performance
[05:14:12] [PASSED] gpu_test_buddy_dirty_tracker_performance
[05:14:12] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[05:14:12] [PASSED] gpu_test_buddy_offset_aligned_allocation
[05:14:12] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[05:14:12] [PASSED] gpu_test_buddy_addr_to_block
[05:14:12] ==================== [PASSED] gpu_buddy ====================
[05:14:12] ============================================================
[05:14:12] Testing complete. Ran 18 tests: passed: 18
[05:14:13] Elapsed time: 26.715s total, 4.431s configuring, 20.367s building, 1.868s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[05:14:13] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:14:15] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:14:48] Starting KUnit Kernel (1/1)...
[05:14:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:14:48] ============= refcount_interrupt (4 subtests) ==============
[05:14:48] [PASSED] test_single_irq_change
[05:14:48] [PASSED] test_nested_irq_change
[05:14:48] [PASSED] test_multiple_irq_change
[05:14:48] [PASSED] test_irq_save
[05:14:48] =============== [PASSED] refcount_interrupt ================
[05:14:48] ================== guc_buf (11 subtests) ===================
[05:14:48] [PASSED] test_smallest
[05:14:48] [PASSED] test_largest
[05:14:48] [PASSED] test_granular
[05:14:48] [PASSED] test_unique
[05:14:48] [PASSED] test_overlap
[05:14:48] [PASSED] test_reusable
[05:14:48] [PASSED] test_too_big
[05:14:48] [PASSED] test_flush
[05:14:48] [PASSED] test_lookup
[05:14:48] [PASSED] test_data
[05:14:48] [PASSED] test_class
[05:14:48] ===================== [PASSED] guc_buf =====================
[05:14:48] =================== guc_dbm (7 subtests) ===================
[05:14:48] [PASSED] test_empty
[05:14:48] [PASSED] test_default
[05:14:48] ======================== test_size  ========================
[05:14:48] [PASSED] 4
[05:14:48] [PASSED] 8
[05:14:48] [PASSED] 32
[05:14:48] [PASSED] 256
[05:14:48] ==================== [PASSED] test_size ====================
[05:14:48] ======================= test_reuse  ========================
[05:14:48] [PASSED] 4
[05:14:48] [PASSED] 8
[05:14:48] [PASSED] 32
[05:14:48] [PASSED] 256
[05:14:48] =================== [PASSED] test_reuse ====================
[05:14:48] =================== test_range_overlap  ====================
[05:14:48] [PASSED] 4
[05:14:48] [PASSED] 8
[05:14:48] [PASSED] 32
[05:14:48] [PASSED] 256
[05:14:48] =============== [PASSED] test_range_overlap ================
[05:14:49] =================== test_range_compact  ====================
[05:14:49] [PASSED] 4
[05:14:49] [PASSED] 8
[05:14:49] [PASSED] 32
[05:14:49] [PASSED] 256
[05:14:49] =============== [PASSED] test_range_compact ================
[05:14:49] ==================== test_range_spare  =====================
[05:14:49] [PASSED] 4
[05:14:49] [PASSED] 8
[05:14:49] [PASSED] 32
[05:14:49] [PASSED] 256
[05:14:49] ================ [PASSED] test_range_spare =================
[05:14:49] ===================== [PASSED] guc_dbm =====================
[05:14:49] =================== guc_idm (6 subtests) ===================
[05:14:49] [PASSED] bad_init
[05:14:49] [PASSED] no_init
[05:14:49] [PASSED] init_fini
[05:14:49] [PASSED] check_used
[05:14:49] [PASSED] check_quota
[05:14:49] [PASSED] check_all
[05:14:49] ===================== [PASSED] guc_idm =====================
[05:14:49] =============== guc_klv_helpers (9 subtests) ===============
[05:14:49] [PASSED] test_count
[05:14:49] [PASSED] test_encode_u32
[05:14:49] [PASSED] test_encode_u64
[05:14:49] [PASSED] test_encode_string
[05:14:49] [PASSED] test_encode_object_raw
[05:14:49] [PASSED] test_encode_object_klv
[05:14:49] [PASSED] test_encode_object_nested
[05:14:49] [PASSED] test_encode_object_basic
[05:14:49] [PASSED] test_print
[05:14:49] ================= [PASSED] guc_klv_helpers =================
[05:14:49] =================== xe_log (4 subtests) ====================
[05:14:49] [PASSED] demo_cper
[05:14:49] [PASSED] demo_dmesg
[05:14:49] ======================= test_dmesg  ========================
[05:14:49] [PASSED] test_fatal
[05:14:49] [PASSED] test_fatal_tile
[05:14:49] [PASSED] test_fatal_gt
[05:14:49] [PASSED] test_fatal_comp
[05:14:49] [PASSED] test_fatal_comp_tile
[05:14:49] [PASSED] test_fatal_comp_gt
[05:14:49] [PASSED] test_fatal_all
[05:14:49] [PASSED] test_recoverable
[05:14:49] [PASSED] test_recoverable_tile
[05:14:49] [PASSED] test_recoverable_gt
[05:14:49] [PASSED] test_recoverable_comp
[05:14:49] [PASSED] test_recoverable_comp_tile
[05:14:49] [PASSED] test_recoverable_comp_gt
[05:14:49] [PASSED] test_recoverable_all
[05:14:49] [PASSED] test_info
[05:14:49] [PASSED] test_info_tile
[05:14:49] [PASSED] test_info_gt
[05:14:49] [PASSED] test_info_err
[05:14:49] [PASSED] test_info_comp
[05:14:49] [PASSED] test_info_comp_tile
[05:14:49] [PASSED] test_info_comp_gt
[05:14:49] [PASSED] test_info_all
[05:14:49] [PASSED] test_hw_fatal
[05:14:49] [PASSED] test_hw_recoverable
[05:14:49] [PASSED] test_hw_corrected
[05:14:49] [PASSED] test_hw_informational
[05:14:49] =================== [PASSED] test_dmesg ====================
[05:14:49] ====================== test_invalid  =======================
[05:14:49] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[05:14:49] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[05:14:49] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[05:14:49] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[05:14:49] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[05:14:49] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[05:14:49] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[05:14:49] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[05:14:49] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[05:14:49] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[05:14:49] ================== [SKIPPED] test_invalid ==================
[05:14:49] ===================== [PASSED] xe_log ======================
[05:14:49] ================== no_relay (3 subtests) ===================
[05:14:49] [PASSED] xe_drops_guc2pf_if_not_ready
[05:14:49] [PASSED] xe_drops_guc2vf_if_not_ready
[05:14:49] [PASSED] xe_rejects_send_if_not_ready
[05:14:49] ==================== [PASSED] no_relay =====================
[05:14:49] ================== pf_relay (14 subtests) ==================
[05:14:49] [PASSED] pf_rejects_guc2pf_too_short
[05:14:49] [PASSED] pf_rejects_guc2pf_too_long
[05:14:49] [PASSED] pf_rejects_guc2pf_no_payload
[05:14:49] [PASSED] pf_fails_no_payload
[05:14:49] [PASSED] pf_fails_bad_origin
[05:14:49] [PASSED] pf_fails_bad_type
[05:14:49] [PASSED] pf_txn_reports_error
[05:14:49] [PASSED] pf_txn_sends_pf2guc
[05:14:49] [PASSED] pf_sends_pf2guc
[05:14:49] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[05:14:49] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[05:14:49] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[05:14:49] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[05:14:49] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[05:14:49] ==================== [PASSED] pf_relay =====================
[05:14:49] ================== vf_relay (3 subtests) ===================
[05:14:49] [PASSED] vf_rejects_guc2vf_too_short
[05:14:49] [PASSED] vf_rejects_guc2vf_too_long
[05:14:49] [PASSED] vf_rejects_guc2vf_no_payload
[05:14:49] ==================== [PASSED] vf_relay =====================
[05:14:49] ================ pf_gt_config (9 subtests) =================
[05:14:49] [PASSED] fair_contexts_1vf
[05:14:49] [PASSED] fair_doorbells_1vf
[05:14:49] [PASSED] fair_ggtt_1vf
[05:14:49] ====================== fair_vram_1vf  ======================
[05:14:49] [PASSED] 3.50 GiB
[05:14:49] [PASSED] 11.5 GiB
[05:14:49] [PASSED] 15.5 GiB
[05:14:49] [PASSED] 31.5 GiB
[05:14:49] [PASSED] 63.5 GiB
[05:14:49] [PASSED] 1.91 GiB
[05:14:49] ================== [PASSED] fair_vram_1vf ==================
[05:14:49] ================ fair_vram_1vf_admin_only  =================
[05:14:49] [PASSED] 3.50 GiB
[05:14:49] [PASSED] 11.5 GiB
[05:14:49] [PASSED] 15.5 GiB
[05:14:49] [PASSED] 31.5 GiB
[05:14:49] [PASSED] 63.5 GiB
[05:14:49] [PASSED] 1.91 GiB
[05:14:49] ============ [PASSED] fair_vram_1vf_admin_only =============
[05:14:49] ====================== fair_contexts  ======================
[05:14:49] [PASSED] 1 VF
[05:14:49] [PASSED] 2 VFs
[05:14:49] [PASSED] 3 VFs
[05:14:49] [PASSED] 4 VFs
[05:14:49] [PASSED] 5 VFs
[05:14:49] [PASSED] 6 VFs
[05:14:49] [PASSED] 7 VFs
[05:14:49] [PASSED] 8 VFs
[05:14:49] [PASSED] 9 VFs
[05:14:49] [PASSED] 10 VFs
[05:14:49] [PASSED] 11 VFs
[05:14:49] [PASSED] 12 VFs
[05:14:49] [PASSED] 13 VFs
[05:14:49] [PASSED] 14 VFs
[05:14:49] [PASSED] 15 VFs
[05:14:49] [PASSED] 16 VFs
[05:14:49] [PASSED] 17 VFs
[05:14:49] [PASSED] 18 VFs
[05:14:49] [PASSED] 19 VFs
[05:14:49] [PASSED] 20 VFs
[05:14:49] [PASSED] 21 VFs
[05:14:49] [PASSED] 22 VFs
[05:14:49] [PASSED] 23 VFs
[05:14:49] [PASSED] 24 VFs
[05:14:49] [PASSED] 25 VFs
[05:14:49] [PASSED] 26 VFs
[05:14:49] [PASSED] 27 VFs
[05:14:49] [PASSED] 28 VFs
[05:14:49] [PASSED] 29 VFs
[05:14:49] [PASSED] 30 VFs
[05:14:49] [PASSED] 31 VFs
[05:14:49] [PASSED] 32 VFs
[05:14:49] [PASSED] 33 VFs
[05:14:49] [PASSED] 34 VFs
[05:14:49] [PASSED] 35 VFs
[05:14:49] [PASSED] 36 VFs
[05:14:49] [PASSED] 37 VFs
[05:14:49] [PASSED] 38 VFs
[05:14:49] [PASSED] 39 VFs
[05:14:49] [PASSED] 40 VFs
[05:14:49] [PASSED] 41 VFs
[05:14:49] [PASSED] 42 VFs
[05:14:49] [PASSED] 43 VFs
[05:14:49] [PASSED] 44 VFs
[05:14:49] [PASSED] 45 VFs
[05:14:49] [PASSED] 46 VFs
[05:14:49] [PASSED] 47 VFs
[05:14:49] [PASSED] 48 VFs
[05:14:49] [PASSED] 49 VFs
[05:14:49] [PASSED] 50 VFs
[05:14:49] [PASSED] 51 VFs
[05:14:49] [PASSED] 52 VFs
[05:14:49] [PASSED] 53 VFs
[05:14:49] [PASSED] 54 VFs
[05:14:49] [PASSED] 55 VFs
[05:14:49] [PASSED] 56 VFs
[05:14:49] [PASSED] 57 VFs
[05:14:49] [PASSED] 58 VFs
[05:14:49] [PASSED] 59 VFs
[05:14:49] [PASSED] 60 VFs
[05:14:49] [PASSED] 61 VFs
[05:14:49] [PASSED] 62 VFs
[05:14:49] [PASSED] 63 VFs
[05:14:49] ================== [PASSED] fair_contexts ==================
[05:14:49] ===================== fair_doorbells  ======================
[05:14:49] [PASSED] 1 VF
[05:14:49] [PASSED] 2 VFs
[05:14:49] [PASSED] 3 VFs
[05:14:49] [PASSED] 4 VFs
[05:14:49] [PASSED] 5 VFs
[05:14:49] [PASSED] 6 VFs
[05:14:49] [PASSED] 7 VFs
[05:14:49] [PASSED] 8 VFs
[05:14:49] [PASSED] 9 VFs
[05:14:49] [PASSED] 10 VFs
[05:14:49] [PASSED] 11 VFs
[05:14:49] [PASSED] 12 VFs
[05:14:49] [PASSED] 13 VFs
[05:14:49] [PASSED] 14 VFs
[05:14:49] [PASSED] 15 VFs
[05:14:49] [PASSED] 16 VFs
[05:14:49] [PASSED] 17 VFs
[05:14:49] [PASSED] 18 VFs
[05:14:49] [PASSED] 19 VFs
[05:14:49] [PASSED] 20 VFs
[05:14:49] [PASSED] 21 VFs
[05:14:49] [PASSED] 22 VFs
[05:14:49] [PASSED] 23 VFs
[05:14:49] [PASSED] 24 VFs
[05:14:49] [PASSED] 25 VFs
[05:14:49] [PASSED] 26 VFs
[05:14:49] [PASSED] 27 VFs
[05:14:49] [PASSED] 28 VFs
[05:14:49] [PASSED] 29 VFs
[05:14:49] [PASSED] 30 VFs
[05:14:49] [PASSED] 31 VFs
[05:14:49] [PASSED] 32 VFs
[05:14:49] [PASSED] 33 VFs
[05:14:49] [PASSED] 34 VFs
[05:14:49] [PASSED] 35 VFs
[05:14:49] [PASSED] 36 VFs
[05:14:49] [PASSED] 37 VFs
[05:14:49] [PASSED] 38 VFs
[05:14:49] [PASSED] 39 VFs
[05:14:49] [PASSED] 40 VFs
[05:14:49] [PASSED] 41 VFs
[05:14:49] [PASSED] 42 VFs
[05:14:49] [PASSED] 43 VFs
[05:14:49] [PASSED] 44 VFs
[05:14:49] [PASSED] 45 VFs
[05:14:49] [PASSED] 46 VFs
[05:14:49] [PASSED] 47 VFs
[05:14:49] [PASSED] 48 VFs
[05:14:49] [PASSED] 49 VFs
[05:14:49] [PASSED] 50 VFs
[05:14:49] [PASSED] 51 VFs
[05:14:49] [PASSED] 52 VFs
[05:14:49] [PASSED] 53 VFs
[05:14:49] [PASSED] 54 VFs
[05:14:49] [PASSED] 55 VFs
[05:14:49] [PASSED] 56 VFs
[05:14:49] [PASSED] 57 VFs
[05:14:49] [PASSED] 58 VFs
[05:14:49] [PASSED] 59 VFs
[05:14:49] [PASSED] 60 VFs
[05:14:49] [PASSED] 61 VFs
[05:14:49] [PASSED] 62 VFs
[05:14:49] [PASSED] 63 VFs
[05:14:49] ================= [PASSED] fair_doorbells ==================
[05:14:49] ======================== fair_ggtt  ========================
[05:14:49] [PASSED] 1 VF
[05:14:49] [PASSED] 2 VFs
[05:14:49] [PASSED] 3 VFs
[05:14:49] [PASSED] 4 VFs
[05:14:49] [PASSED] 5 VFs
[05:14:49] [PASSED] 6 VFs
[05:14:49] [PASSED] 7 VFs
[05:14:49] [PASSED] 8 VFs
[05:14:49] [PASSED] 9 VFs
[05:14:49] [PASSED] 10 VFs
[05:14:49] [PASSED] 11 VFs
[05:14:49] [PASSED] 12 VFs
[05:14:49] [PASSED] 13 VFs
[05:14:49] [PASSED] 14 VFs
[05:14:49] [PASSED] 15 VFs
[05:14:49] [PASSED] 16 VFs
[05:14:49] [PASSED] 17 VFs
[05:14:49] [PASSED] 18 VFs
[05:14:49] [PASSED] 19 VFs
[05:14:49] [PASSED] 20 VFs
[05:14:49] [PASSED] 21 VFs
[05:14:49] [PASSED] 22 VFs
[05:14:49] [PASSED] 23 VFs
[05:14:49] [PASSED] 24 VFs
[05:14:49] [PASSED] 25 VFs
[05:14:49] [PASSED] 26 VFs
[05:14:49] [PASSED] 27 VFs
[05:14:49] [PASSED] 28 VFs
[05:14:49] [PASSED] 29 VFs
[05:14:49] [PASSED] 30 VFs
[05:14:49] [PASSED] 31 VFs
[05:14:49] [PASSED] 32 VFs
[05:14:49] [PASSED] 33 VFs
[05:14:49] [PASSED] 34 VFs
[05:14:49] [PASSED] 35 VFs
[05:14:49] [PASSED] 36 VFs
[05:14:49] [PASSED] 37 VFs
[05:14:49] [PASSED] 38 VFs
[05:14:49] [PASSED] 39 VFs
[05:14:49] [PASSED] 40 VFs
[05:14:49] [PASSED] 41 VFs
[05:14:49] [PASSED] 42 VFs
[05:14:49] [PASSED] 43 VFs
[05:14:49] [PASSED] 44 VFs
[05:14:49] [PASSED] 45 VFs
[05:14:49] [PASSED] 46 VFs
[05:14:49] [PASSED] 47 VFs
[05:14:49] [PASSED] 48 VFs
[05:14:49] [PASSED] 49 VFs
[05:14:49] [PASSED] 50 VFs
[05:14:49] [PASSED] 51 VFs
[05:14:49] [PASSED] 52 VFs
[05:14:49] [PASSED] 53 VFs
[05:14:49] [PASSED] 54 VFs
[05:14:49] [PASSED] 55 VFs
[05:14:49] [PASSED] 56 VFs
[05:14:49] [PASSED] 57 VFs
[05:14:49] [PASSED] 58 VFs
[05:14:49] [PASSED] 59 VFs
[05:14:49] [PASSED] 60 VFs
[05:14:49] [PASSED] 61 VFs
[05:14:49] [PASSED] 62 VFs
[05:14:49] [PASSED] 63 VFs
[05:14:49] ==================== [PASSED] fair_ggtt ====================
[05:14:49] ======================== fair_vram  ========================
[05:14:49] [PASSED] 1 VF
[05:14:49] [PASSED] 2 VFs
[05:14:49] [PASSED] 3 VFs
[05:14:49] [PASSED] 4 VFs
[05:14:49] [PASSED] 5 VFs
[05:14:49] [PASSED] 6 VFs
[05:14:49] [PASSED] 7 VFs
[05:14:49] [PASSED] 8 VFs
[05:14:49] [PASSED] 9 VFs
[05:14:49] [PASSED] 10 VFs
[05:14:49] [PASSED] 11 VFs
[05:14:49] [PASSED] 12 VFs
[05:14:49] [PASSED] 13 VFs
[05:14:49] [PASSED] 14 VFs
[05:14:49] [PASSED] 15 VFs
[05:14:49] [PASSED] 16 VFs
[05:14:49] [PASSED] 17 VFs
[05:14:49] [PASSED] 18 VFs
[05:14:49] [PASSED] 19 VFs
[05:14:49] [PASSED] 20 VFs
[05:14:49] [PASSED] 21 VFs
[05:14:49] [PASSED] 22 VFs
[05:14:49] [PASSED] 23 VFs
[05:14:49] [PASSED] 24 VFs
[05:14:49] [PASSED] 25 VFs
[05:14:49] [PASSED] 26 VFs
[05:14:49] [PASSED] 27 VFs
[05:14:49] [PASSED] 28 VFs
[05:14:49] [PASSED] 29 VFs
[05:14:49] [PASSED] 30 VFs
[05:14:49] [PASSED] 31 VFs
[05:14:49] [PASSED] 32 VFs
[05:14:49] [PASSED] 33 VFs
[05:14:49] [PASSED] 34 VFs
[05:14:49] [PASSED] 35 VFs
[05:14:49] [PASSED] 36 VFs
[05:14:49] [PASSED] 37 VFs
[05:14:49] [PASSED] 38 VFs
[05:14:49] [PASSED] 39 VFs
[05:14:49] [PASSED] 40 VFs
[05:14:49] [PASSED] 41 VFs
[05:14:49] [PASSED] 42 VFs
[05:14:49] [PASSED] 43 VFs
[05:14:49] [PASSED] 44 VFs
[05:14:49] [PASSED] 45 VFs
[05:14:49] [PASSED] 46 VFs
[05:14:49] [PASSED] 47 VFs
[05:14:49] [PASSED] 48 VFs
[05:14:49] [PASSED] 49 VFs
[05:14:49] [PASSED] 50 VFs
[05:14:49] [PASSED] 51 VFs
[05:14:49] [PASSED] 52 VFs
[05:14:49] [PASSED] 53 VFs
[05:14:49] [PASSED] 54 VFs
[05:14:49] [PASSED] 55 VFs
[05:14:49] [PASSED] 56 VFs
[05:14:49] [PASSED] 57 VFs
[05:14:49] [PASSED] 58 VFs
[05:14:49] [PASSED] 59 VFs
[05:14:49] [PASSED] 60 VFs
[05:14:49] [PASSED] 61 VFs
[05:14:49] [PASSED] 62 VFs
[05:14:49] [PASSED] 63 VFs
[05:14:49] ==================== [PASSED] fair_vram ====================
[05:14:49] ================== [PASSED] pf_gt_config ===================
[05:14:49] ===================== lmtt (1 subtest) =====================
[05:14:49] ======================== test_ops  =========================
[05:14:49] [PASSED] 2-level
[05:14:49] [PASSED] multi-level
[05:14:49] ==================== [PASSED] test_ops =====================
[05:14:49] ====================== [PASSED] lmtt =======================
[05:14:49] ================= sriov_packet (1 subtest) =================
[05:14:49] [PASSED] test_descriptor_init
[05:14:49] ================== [PASSED] sriov_packet ===================
[05:14:49] ================= pf_service (11 subtests) =================
[05:14:49] [PASSED] pf_negotiate_any
[05:14:49] [PASSED] pf_negotiate_base_match
[05:14:49] [PASSED] pf_negotiate_base_newer
[05:14:49] [PASSED] pf_negotiate_base_next
[05:14:49] [SKIPPED] pf_negotiate_base_older (no older minor)
[05:14:49] [PASSED] pf_negotiate_base_prev
[05:14:49] [PASSED] pf_negotiate_latest_match
[05:14:49] [PASSED] pf_negotiate_latest_newer
[05:14:49] [PASSED] pf_negotiate_latest_next
[05:14:49] [SKIPPED] pf_negotiate_latest_older (no older minor)
[05:14:49] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[05:14:49] =================== [PASSED] pf_service ====================
[05:14:49] ================= xe_guc_g2g (2 subtests) ==================
[05:14:49] ============== xe_live_guc_g2g_kunit_default  ==============
[05:14:49] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[05:14:49] ============== xe_live_guc_g2g_kunit_allmem  ===============
[05:14:49] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[05:14:49] =================== [SKIPPED] xe_guc_g2g ===================
[05:14:49] =================== xe_mocs (2 subtests) ===================
[05:14:49] ================ xe_live_mocs_kernel_kunit  ================
[05:14:49] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[05:14:49] ================ xe_live_mocs_reset_kunit  =================
[05:14:49] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[05:14:49] ==================== [SKIPPED] xe_mocs =====================
[05:14:49] ================= xe_migrate (2 subtests) ==================
[05:14:49] ================= xe_migrate_sanity_kunit  =================
[05:14:49] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[05:14:49] ================== xe_validate_ccs_kunit  ==================
[05:14:49] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[05:14:49] =================== [SKIPPED] xe_migrate ===================
[05:14:49] ================== xe_dma_buf (1 subtest) ==================
[05:14:49] ==================== xe_dma_buf_kunit  =====================
[05:14:49] ================ [SKIPPED] xe_dma_buf_kunit ================
[05:14:49] =================== [SKIPPED] xe_dma_buf ===================
[05:14:49] ================= xe_bo_shrink (1 subtest) =================
[05:14:49] =================== xe_bo_shrink_kunit  ====================
[05:14:49] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[05:14:49] ================== [SKIPPED] xe_bo_shrink ==================
[05:14:49] ==================== xe_bo (2 subtests) ====================
[05:14:49] ================== xe_ccs_migrate_kunit  ===================
[05:14:49] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[05:14:49] ==================== xe_bo_evict_kunit  ====================
[05:14:49] =============== [SKIPPED] xe_bo_evict_kunit ================
[05:14:49] ===================== [SKIPPED] xe_bo ======================
[05:14:49] =================== xe_any (9 subtests) ====================
[05:14:49] [PASSED] test_to_xe
[05:14:49] [PASSED] test_to_dev
[05:14:49] [PASSED] test_to_pdev
[05:14:49] [PASSED] test_to_drm
[05:14:49] [PASSED] test_if_pdev
[05:14:49] [PASSED] test_if_xe
[05:14:49] [PASSED] test_if_tile
[05:14:49] [PASSED] test_if_gt
[05:14:49] [PASSED] test_to_id
[05:14:49] ===================== [PASSED] xe_any ======================
[05:14:49] ==================== args (13 subtests) ====================
[05:14:49] [PASSED] count_args_test
[05:14:49] [PASSED] call_args_example
[05:14:49] [PASSED] call_args_test
[05:14:49] [PASSED] drop_first_arg_example
[05:14:49] [PASSED] drop_first_arg_test
[05:14:49] [PASSED] first_arg_example
[05:14:49] [PASSED] first_arg_test
[05:14:49] [PASSED] last_arg_example
[05:14:49] [PASSED] last_arg_test
[05:14:49] [PASSED] pick_arg_example
[05:14:49] [PASSED] if_args_example
[05:14:49] [PASSED] if_args_test
[05:14:49] [PASSED] sep_comma_example
[05:14:49] ====================== [PASSED] args =======================
[05:14:49] =================== xe_pci (3 subtests) ====================
[05:14:49] ==================== check_graphics_ip  ====================
[05:14:49] [PASSED] 12.00 Xe_LP
[05:14:49] [PASSED] 12.10 Xe_LP+
[05:14:49] [PASSED] 12.55 Xe_HPG
[05:14:49] [PASSED] 12.60 Xe_HPC
[05:14:49] [PASSED] 12.70 Xe_LPG
[05:14:49] [PASSED] 12.71 Xe_LPG
[05:14:49] [PASSED] 12.74 Xe_LPG+
[05:14:49] [PASSED] 20.01 Xe2_HPG
[05:14:49] [PASSED] 20.02 Xe2_HPG
[05:14:49] [PASSED] 20.04 Xe2_LPG
[05:14:49] [PASSED] 30.00 Xe3_LPG
[05:14:49] [PASSED] 30.01 Xe3_LPG
[05:14:49] [PASSED] 30.03 Xe3_LPG
[05:14:49] [PASSED] 30.04 Xe3_LPG
[05:14:49] [PASSED] 30.05 Xe3_LPG
[05:14:49] [PASSED] 35.10 Xe3p_LPG
[05:14:49] [PASSED] 35.11 Xe3p_XPC
[05:14:49] ================ [PASSED] check_graphics_ip ================
[05:14:49] ===================== check_media_ip  ======================
[05:14:49] [PASSED] 12.00 Xe_M
[05:14:49] [PASSED] 12.55 Xe_HPM
[05:14:49] [PASSED] 13.00 Xe_LPM+
[05:14:49] [PASSED] 13.01 Xe2_HPM
[05:14:49] [PASSED] 20.00 Xe2_LPM
[05:14:49] [PASSED] 30.00 Xe3_LPM
[05:14:49] [PASSED] 30.02 Xe3_LPM
[05:14:49] [PASSED] 35.00 Xe3p_LPM
[05:14:49] [PASSED] 35.03 Xe3p_HPM
[05:14:49] ================= [PASSED] check_media_ip ==================
[05:14:49] =================== check_platform_desc  ===================
[05:14:49] [PASSED] 0x9A60 (TIGERLAKE)
[05:14:49] [PASSED] 0x9A68 (TIGERLAKE)
[05:14:49] [PASSED] 0x9A70 (TIGERLAKE)
[05:14:49] [PASSED] 0x9A40 (TIGERLAKE)
[05:14:49] [PASSED] 0x9A49 (TIGERLAKE)
[05:14:49] [PASSED] 0x9A59 (TIGERLAKE)
[05:14:49] [PASSED] 0x9A78 (TIGERLAKE)
[05:14:49] [PASSED] 0x9AC0 (TIGERLAKE)
[05:14:49] [PASSED] 0x9AC9 (TIGERLAKE)
[05:14:49] [PASSED] 0x9AD9 (TIGERLAKE)
[05:14:49] [PASSED] 0x9AF8 (TIGERLAKE)
[05:14:49] [PASSED] 0x4C80 (ROCKETLAKE)
[05:14:49] [PASSED] 0x4C8A (ROCKETLAKE)
[05:14:49] [PASSED] 0x4C8B (ROCKETLAKE)
[05:14:49] [PASSED] 0x4C8C (ROCKETLAKE)
[05:14:49] [PASSED] 0x4C90 (ROCKETLAKE)
[05:14:49] [PASSED] 0x4C9A (ROCKETLAKE)
[05:14:49] [PASSED] 0x4680 (ALDERLAKE_S)
[05:14:49] [PASSED] 0x4682 (ALDERLAKE_S)
[05:14:49] [PASSED] 0x4688 (ALDERLAKE_S)
[05:14:49] [PASSED] 0x468A (ALDERLAKE_S)
[05:14:49] [PASSED] 0x468B (ALDERLAKE_S)
[05:14:49] [PASSED] 0x4690 (ALDERLAKE_S)
[05:14:49] [PASSED] 0x4692 (ALDERLAKE_S)
[05:14:49] [PASSED] 0x4693 (ALDERLAKE_S)
[05:14:49] [PASSED] 0x46A0 (ALDERLAKE_P)
[05:14:49] [PASSED] 0x46A1 (ALDERLAKE_P)
[05:14:49] [PASSED] 0x46A2 (ALDERLAKE_P)
[05:14:49] [PASSED] 0x46A3 (ALDERLAKE_P)
[05:14:49] [PASSED] 0x46A6 (ALDERLAKE_P)
[05:14:49] [PASSED] 0x46A8 (ALDERLAKE_P)
[05:14:49] [PASSED] 0x46AA (ALDERLAKE_P)
[05:14:49] [PASSED] 0x462A (ALDERLAKE_P)
[05:14:49] [PASSED] 0x4626 (ALDERLAKE_P)
[05:14:49] [PASSED] 0x4628 (ALDERLAKE_P)
[05:14:49] [PASSED] 0x46B0 (ALDERLAKE_P)
[05:14:49] [PASSED] 0x46B1 (ALDERLAKE_P)
[05:14:49] [PASSED] 0x46B2 (ALDERLAKE_P)
[05:14:49] [PASSED] 0x46B3 (ALDERLAKE_P)
[05:14:49] [PASSED] 0x46C0 (ALDERLAKE_P)
[05:14:49] [PASSED] 0x46C1 (ALDERLAKE_P)
[05:14:49] [PASSED] 0x46C2 (ALDERLAKE_P)
[05:14:49] [PASSED] 0x46C3 (ALDERLAKE_P)
[05:14:49] [PASSED] 0x46D0 (ALDERLAKE_N)
[05:14:49] [PASSED] 0x46D1 (ALDERLAKE_N)
[05:14:49] [PASSED] 0x46D2 (ALDERLAKE_N)
[05:14:49] [PASSED] 0x46D3 (ALDERLAKE_N)
[05:14:49] [PASSED] 0x46D4 (ALDERLAKE_N)
[05:14:49] [PASSED] 0xA721 (ALDERLAKE_P)
[05:14:49] [PASSED] 0xA7A1 (ALDERLAKE_P)
[05:14:49] [PASSED] 0xA7A9 (ALDERLAKE_P)
[05:14:49] [PASSED] 0xA7AC (ALDERLAKE_P)
[05:14:49] [PASSED] 0xA7AD (ALDERLAKE_P)
[05:14:49] [PASSED] 0xA720 (ALDERLAKE_P)
[05:14:49] [PASSED] 0xA7A0 (ALDERLAKE_P)
[05:14:49] [PASSED] 0xA7A8 (ALDERLAKE_P)
[05:14:49] [PASSED] 0xA7AA (ALDERLAKE_P)
[05:14:49] [PASSED] 0xA7AB (ALDERLAKE_P)
[05:14:49] [PASSED] 0xA780 (ALDERLAKE_S)
[05:14:49] [PASSED] 0xA781 (ALDERLAKE_S)
[05:14:49] [PASSED] 0xA782 (ALDERLAKE_S)
[05:14:49] [PASSED] 0xA783 (ALDERLAKE_S)
[05:14:49] [PASSED] 0xA788 (ALDERLAKE_S)
[05:14:49] [PASSED] 0xA789 (ALDERLAKE_S)
[05:14:49] [PASSED] 0xA78A (ALDERLAKE_S)
[05:14:49] [PASSED] 0xA78B (ALDERLAKE_S)
[05:14:49] [PASSED] 0x4905 (DG1)
[05:14:49] [PASSED] 0x4906 (DG1)
[05:14:49] [PASSED] 0x4907 (DG1)
[05:14:49] [PASSED] 0x4908 (DG1)
[05:14:49] [PASSED] 0x4909 (DG1)
[05:14:49] [PASSED] 0x56C0 (DG2)
[05:14:49] [PASSED] 0x56C2 (DG2)
[05:14:49] [PASSED] 0x56C1 (DG2)
[05:14:49] [PASSED] 0x7D51 (METEORLAKE)
[05:14:49] [PASSED] 0x7DD1 (METEORLAKE)
[05:14:49] [PASSED] 0x7D41 (METEORLAKE)
[05:14:49] [PASSED] 0x7D67 (METEORLAKE)
[05:14:49] [PASSED] 0xB640 (METEORLAKE)
[05:14:49] [PASSED] 0x56A0 (DG2)
[05:14:49] [PASSED] 0x56A1 (DG2)
[05:14:49] [PASSED] 0x56A2 (DG2)
[05:14:49] [PASSED] 0x56BE (DG2)
[05:14:49] [PASSED] 0x56BF (DG2)
[05:14:49] [PASSED] 0x5690 (DG2)
[05:14:49] [PASSED] 0x5691 (DG2)
[05:14:49] [PASSED] 0x5692 (DG2)
[05:14:49] [PASSED] 0x56A5 (DG2)
[05:14:49] [PASSED] 0x56A6 (DG2)
[05:14:49] [PASSED] 0x56B0 (DG2)
[05:14:49] [PASSED] 0x56B1 (DG2)
[05:14:49] [PASSED] 0x56BA (DG2)
[05:14:49] [PASSED] 0x56BB (DG2)
[05:14:49] [PASSED] 0x56BC (DG2)
[05:14:49] [PASSED] 0x56BD (DG2)
[05:14:49] [PASSED] 0x5693 (DG2)
[05:14:49] [PASSED] 0x5694 (DG2)
[05:14:49] [PASSED] 0x5695 (DG2)
[05:14:49] [PASSED] 0x56A3 (DG2)
[05:14:49] [PASSED] 0x56A4 (DG2)
[05:14:49] [PASSED] 0x56B2 (DG2)
[05:14:49] [PASSED] 0x56B3 (DG2)
[05:14:49] [PASSED] 0x5696 (DG2)
[05:14:49] [PASSED] 0x5697 (DG2)
[05:14:49] [PASSED] 0xB69 (PVC)
[05:14:49] [PASSED] 0xB6E (PVC)
[05:14:49] [PASSED] 0xBD4 (PVC)
[05:14:49] [PASSED] 0xBD5 (PVC)
[05:14:49] [PASSED] 0xBD6 (PVC)
[05:14:49] [PASSED] 0xBD7 (PVC)
[05:14:49] [PASSED] 0xBD8 (PVC)
[05:14:49] [PASSED] 0xBD9 (PVC)
[05:14:49] [PASSED] 0xBDA (PVC)
[05:14:49] [PASSED] 0xBDB (PVC)
[05:14:49] [PASSED] 0xBE0 (PVC)
[05:14:49] [PASSED] 0xBE1 (PVC)
[05:14:49] [PASSED] 0xBE5 (PVC)
[05:14:49] [PASSED] 0x7D40 (METEORLAKE)
[05:14:49] [PASSED] 0x7D45 (METEORLAKE)
[05:14:49] [PASSED] 0x7D55 (METEORLAKE)
[05:14:49] [PASSED] 0x7D60 (METEORLAKE)
[05:14:49] [PASSED] 0x7DD5 (METEORLAKE)
[05:14:49] [PASSED] 0x6420 (LUNARLAKE)
[05:14:49] [PASSED] 0x64A0 (LUNARLAKE)
[05:14:49] [PASSED] 0x64B0 (LUNARLAKE)
[05:14:49] [PASSED] 0xE202 (BATTLEMAGE)
[05:14:49] [PASSED] 0xE209 (BATTLEMAGE)
[05:14:49] [PASSED] 0xE20B (BATTLEMAGE)
[05:14:49] [PASSED] 0xE20C (BATTLEMAGE)
[05:14:49] [PASSED] 0xE20D (BATTLEMAGE)
[05:14:49] [PASSED] 0xE210 (BATTLEMAGE)
[05:14:49] [PASSED] 0xE211 (BATTLEMAGE)
[05:14:49] [PASSED] 0xE212 (BATTLEMAGE)
[05:14:49] [PASSED] 0xE216 (BATTLEMAGE)
[05:14:49] [PASSED] 0xE220 (BATTLEMAGE)
[05:14:49] [PASSED] 0xE221 (BATTLEMAGE)
[05:14:49] [PASSED] 0xE222 (BATTLEMAGE)
[05:14:49] [PASSED] 0xE223 (BATTLEMAGE)
[05:14:49] [PASSED] 0xB080 (PANTHERLAKE)
[05:14:49] [PASSED] 0xB081 (PANTHERLAKE)
[05:14:49] [PASSED] 0xB082 (PANTHERLAKE)
[05:14:49] [PASSED] 0xB083 (PANTHERLAKE)
[05:14:49] [PASSED] 0xB084 (PANTHERLAKE)
[05:14:49] [PASSED] 0xB085 (PANTHERLAKE)
[05:14:49] [PASSED] 0xB086 (PANTHERLAKE)
[05:14:49] [PASSED] 0xB087 (PANTHERLAKE)
[05:14:49] [PASSED] 0xB08F (PANTHERLAKE)
[05:14:49] [PASSED] 0xB090 (PANTHERLAKE)
[05:14:49] [PASSED] 0xB0A0 (PANTHERLAKE)
[05:14:49] [PASSED] 0xB0B0 (PANTHERLAKE)
[05:14:49] [PASSED] 0xFD80 (PANTHERLAKE)
[05:14:49] [PASSED] 0xFD81 (PANTHERLAKE)
[05:14:49] [PASSED] 0xD740 (NOVALAKE_S)
[05:14:49] [PASSED] 0xD741 (NOVALAKE_S)
[05:14:49] [PASSED] 0xD742 (NOVALAKE_S)
[05:14:49] [PASSED] 0xD743 (NOVALAKE_S)
[05:14:49] [PASSED] 0xD745 (NOVALAKE_S)
[05:14:49] [PASSED] 0xD74A (NOVALAKE_S)
[05:14:49] [PASSED] 0xD74B (NOVALAKE_S)
[05:14:49] [PASSED] 0x674C (CRESCENTISLAND)
[05:14:49] [PASSED] 0x674D (CRESCENTISLAND)
[05:14:49] [PASSED] 0x674E (CRESCENTISLAND)
[05:14:49] [PASSED] 0x674F (CRESCENTISLAND)
[05:14:49] [PASSED] 0x6750 (CRESCENTISLAND)
[05:14:49] [PASSED] 0xD750 (NOVALAKE_P)
[05:14:49] [PASSED] 0xD751 (NOVALAKE_P)
[05:14:49] [PASSED] 0xD752 (NOVALAKE_P)
[05:14:49] [PASSED] 0xD753 (NOVALAKE_P)
[05:14:49] [PASSED] 0xD754 (NOVALAKE_P)
[05:14:49] [PASSED] 0xD755 (NOVALAKE_P)
[05:14:49] [PASSED] 0xD756 (NOVALAKE_P)
[05:14:49] [PASSED] 0xD757 (NOVALAKE_P)
[05:14:49] [PASSED] 0xD75F (NOVALAKE_P)
[05:14:49] =============== [PASSED] check_platform_desc ===============
[05:14:49] ===================== [PASSED] xe_pci ======================
[05:14:49] ============= xe_rtp_tables_test (5 subtests) ==============
[05:14:49] ================== xe_rtp_table_gt_test  ===================
[05:14:49] [PASSED] gt_was/14011060649
[05:14:49] [PASSED] gt_was/14011059788
[05:14:49] [PASSED] gt_was/14015795083
[05:14:49] [PASSED] gt_was/16021867713
[05:14:49] [PASSED] gt_was/14019449301
[05:14:49] [PASSED] gt_was/16028005424
[05:14:49] [PASSED] gt_was/14026578760
[05:14:49] [PASSED] gt_was/1409420604
[05:14:49] [PASSED] gt_was/1408615072
[05:14:49] [PASSED] gt_was/22010523718
[05:14:49] [PASSED] gt_was/14011006942
[05:14:49] [PASSED] gt_was/14014830051
[05:14:49] [PASSED] gt_was/18018781329
[05:14:49] [PASSED] gt_was/1509235366
[05:14:49] [PASSED] gt_was/18018781329
[05:14:49] [PASSED] gt_was/16016694945
[05:14:49] [PASSED] gt_was/14018575942
[05:14:49] [PASSED] gt_was/22016670082
[05:14:49] [PASSED] gt_was/22016670082
[05:14:49] [PASSED] gt_was/14017421178
[05:14:49] [PASSED] gt_was/16025250150
[05:14:49] [PASSED] gt_was/14021871409
[05:14:49] [PASSED] gt_was/16021865536
[05:14:49] [PASSED] gt_was/14021486841
[05:14:49] [PASSED] gt_was/14025160223
[05:14:49] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[05:14:49] [PASSED] gt_was/14025635424
[05:14:49] [PASSED] gt_was/16028005424
[05:14:49] ============== [PASSED] xe_rtp_table_gt_test ===============
[05:14:49] ================== xe_rtp_table_gt_test  ===================
[05:14:49] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[05:14:49] [PASSED] gt_tunings/Tuning: 32B Access Enable
[05:14:49] [PASSED] gt_tunings/Tuning: L3 cache
[05:14:49] [PASSED] gt_tunings/Tuning: L3 cache - media
[05:14:49] [PASSED] gt_tunings/Tuning: Compression Overfetch
[05:14:49] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[05:14:49] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[05:14:49] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[05:14:49] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[05:14:49] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[05:14:49] [PASSED] gt_tunings/Tuning: Stateless compression control
[05:14:49] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[05:14:49] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[05:14:49] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[05:14:49] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[05:14:49] ============== [PASSED] xe_rtp_table_gt_test ===============
[05:14:49] ================== xe_rtp_table_oob_test  ==================
[05:14:49] [PASSED] oob_was/1607983814
[05:14:49] [PASSED] oob_was/16010904313
[05:14:49] [PASSED] oob_was/18022495364
[05:14:49] [PASSED] oob_was/22012773006
[05:14:49] [PASSED] oob_was/14014475959
[05:14:49] [PASSED] oob_was/22011391025
[05:14:49] [PASSED] oob_was/22012727170
[05:14:49] [PASSED] oob_was/22012727685
[05:14:49] [PASSED] oob_was/22016596838
[05:14:49] [PASSED] oob_was/18020744125
[05:14:49] [PASSED] oob_was/1409600907
[05:14:49] [PASSED] oob_was/22014953428
[05:14:49] [PASSED] oob_was/16017236439
[05:14:49] [PASSED] oob_was/14019821291
[05:14:49] [PASSED] oob_was/14015076503
[05:14:49] [PASSED] oob_was/14018913170
[05:14:49] [PASSED] oob_was/14018094691
[05:14:49] [PASSED] oob_was/18024947630
[05:14:49] [PASSED] oob_was/16022287689
[05:14:49] [PASSED] oob_was/13011645652
[05:14:49] [PASSED] oob_was/14022293748
[05:14:49] [PASSED] oob_was/22019794406
[05:14:49] [PASSED] oob_was/22019338487
[05:14:49] [PASSED] oob_was/16023588340
[05:14:49] [PASSED] oob_was/14019789679
[05:14:49] [PASSED] oob_was/14022866841
[05:14:49] [PASSED] oob_was/16021333562
[05:14:49] [PASSED] oob_was/14016712196
[05:14:49] [PASSED] oob_was/14015568240
[05:14:49] [PASSED] oob_was/18013179988
[05:14:49] [PASSED] oob_was/1508761755
[05:14:49] [PASSED] oob_was/16023105232
[05:14:49] [PASSED] oob_was/16026508708
[05:14:49] [PASSED] oob_was/14020001231
[05:14:49] [PASSED] oob_was/16023683509
[05:14:49] [PASSED] oob_was/14025515070
[05:14:49] [PASSED] oob_was/15015404425_disable
[05:14:49] [PASSED] oob_was/16026007364
[05:14:49] [PASSED] oob_was/14020316580
[05:14:49] [PASSED] oob_was/14025883347
[05:14:49] [PASSED] oob_was/16029380221
[05:14:49] [PASSED] oob_was/22022079272
[05:14:49] [PASSED] oob_was/16029897822
[05:14:49] [PASSED] oob_was/14027054324
[05:14:49] ============== [PASSED] xe_rtp_table_oob_test ==============
[05:14:49] ================ xe_rtp_table_dev_oob_test  ================
[05:14:49] [PASSED] device_oob_was/22010954014
[05:14:49] [PASSED] device_oob_was/15015404425
[05:14:49] [PASSED] device_oob_was/22019338487_display
[05:14:49] [PASSED] device_oob_was/14022085890
[05:14:49] [PASSED] device_oob_was/14026539277
[05:14:49] [PASSED] device_oob_was/14026633728
[05:14:49] [PASSED] device_oob_was/14026746987
[05:14:49] [PASSED] device_oob_was/14026779378
[05:14:49] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[05:14:49] ========== xe_rtp_table_missing_upper_bound_test  ==========
[05:14:49] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[05:14:49] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[05:14:49] [PASSED] register_whitelist/1806527549
[05:14:49] [PASSED] register_whitelist/allow_read_ctx_timestamp
[05:14:49] [PASSED] register_whitelist/allow_read_queue_timestamp
[05:14:49] [PASSED] register_whitelist/16014440446
[05:14:49] [PASSED] register_whitelist/16017236439
[05:14:49] [PASSED] register_whitelist/16020183090
[05:14:49] [PASSED] register_whitelist/14024997852
[05:14:49] [PASSED] register_whitelist/14024997852
[05:14:49] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[05:14:49] =============== [PASSED] xe_rtp_tables_test ================
[05:14:49] =================== xe_rtp (3 subtests) ====================
[05:14:49] =================== xe_rtp_rules_tests  ====================
[05:14:49] [PASSED] no
[05:14:49] [PASSED] yes
[05:14:49] [PASSED] no-and-no
[05:14:49] [PASSED] no-and-yes
[05:14:49] [PASSED] yes-and-no
[05:14:49] [PASSED] yes-and-yes
[05:14:49] [PASSED] no-or-no
[05:14:49] [PASSED] no-or-yes
[05:14:49] [PASSED] yes-or-no
[05:14:49] [PASSED] yes-or-yes
[05:14:49] [PASSED] no-yes-or-yes-no
[05:14:49] [PASSED] no-yes-or-yes-yes
[05:14:49] [PASSED] yes-yes-or-no-yes
[05:14:49] [PASSED] yes-yes-or-yes-yes
[05:14:49] [PASSED] no-no-or-yes-or-no
[05:14:49] [PASSED] or
[05:14:49] [PASSED] or-yes
[05:14:49] [PASSED] or-no
[05:14:49] [PASSED] yes-or
[05:14:49] [PASSED] no-or
[05:14:49] [PASSED] no-or-or-yes
[05:14:49] [PASSED] yes-or-or-no
[05:14:49] [PASSED] no-or-or-no
[05:14:49] [PASSED] missing-context-engine-class
[05:14:49] [PASSED] missing-context-engine-class-or-yes
[05:14:49] [PASSED] missing-context-engine-class-or-or-yes
[05:14:49] =============== [PASSED] xe_rtp_rules_tests ================
[05:14:49] =============== xe_rtp_process_to_sr_tests  ================
[05:14:49] [PASSED] coalesce-same-reg
[05:14:49] [PASSED] coalesce-same-reg-literal-and-func
[05:14:49] [PASSED] no-match-no-add
[05:14:49] [PASSED] two-regs-two-entries
[05:14:49] [PASSED] clr-one-set-other
[05:14:49] [PASSED] set-field
[05:14:49] [PASSED] conflict-duplicate
[05:14:49] [PASSED] conflict-not-disjoint
[05:14:49] [PASSED] conflict-not-disjoint-literal-and-func
[05:14:49] [PASSED] conflict-reg-type
[05:14:49] [PASSED] bad-mcr-reg-forced-to-regular
[05:14:49] [PASSED] bad-regular-reg-forced-to-mcr
[05:14:49] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[05:14:49] ================== xe_rtp_process_tests  ===================
[05:14:49] [PASSED] active1
[05:14:49] [PASSED] active2
[05:14:49] [PASSED] active-inactive
[05:14:49] [PASSED] inactive-active
[05:14:49] [PASSED] inactive-active-inactive
[05:14:49] [PASSED] inactive-inactive-inactive
[05:14:49] ============== [PASSED] xe_rtp_process_tests ===============
[05:14:49] ===================== [PASSED] xe_rtp ======================
[05:14:49] ==================== xe_wa (1 subtest) =====================
[05:14:49] ======================== xe_wa_gt  =========================
[05:14:49] [PASSED] TIGERLAKE B0
[05:14:49] [PASSED] DG1 A0
[05:14:49] [PASSED] DG1 B0
[05:14:49] [PASSED] ALDERLAKE_S A0
[05:14:49] [PASSED] ALDERLAKE_S B0
[05:14:49] [PASSED] ALDERLAKE_S C0
[05:14:49] [PASSED] ALDERLAKE_S D0
[05:14:49] [PASSED] ALDERLAKE_P A0
[05:14:49] [PASSED] ALDERLAKE_P B0
[05:14:49] [PASSED] ALDERLAKE_P C0
[05:14:49] [PASSED] ALDERLAKE_S RPLS D0
[05:14:49] [PASSED] ALDERLAKE_P RPLU E0
[05:14:49] [PASSED] DG2 G10 C0
[05:14:49] [PASSED] DG2 G11 B1
[05:14:49] [PASSED] DG2 G12 A1
[05:14:49] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[05:14:49] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[05:14:49] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[05:14:49] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[05:14:49] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[05:14:49] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[05:14:49] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[05:14:49] ==================== [PASSED] xe_wa_gt =====================
[05:14:49] ====================== [PASSED] xe_wa ======================
[05:14:49] ============================================================
[05:14:49] Testing complete. Ran 793 tests: passed: 765, skipped: 28
[05:14:49] Elapsed time: 36.306s total, 1.844s configuring, 33.745s building, 0.708s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[05:14:49] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:14:51] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:15:15] Starting KUnit Kernel (1/1)...
[05:15:15] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:15:15] ============= refcount_interrupt (4 subtests) ==============
[05:15:15] [PASSED] test_single_irq_change
[05:15:15] [PASSED] test_nested_irq_change
[05:15:15] [PASSED] test_multiple_irq_change
[05:15:15] [PASSED] test_irq_save
[05:15:15] =============== [PASSED] refcount_interrupt ================
[05:15:15] ============ drm_test_pick_cmdline (2 subtests) ============
[05:15:15] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[05:15:15] =============== drm_test_pick_cmdline_named  ===============
[05:15:15] [PASSED] NTSC
[05:15:15] [PASSED] NTSC-J
[05:15:15] [PASSED] PAL
[05:15:15] [PASSED] PAL-M
[05:15:15] =========== [PASSED] drm_test_pick_cmdline_named ===========
[05:15:15] ============== [PASSED] drm_test_pick_cmdline ==============
[05:15:15] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[05:15:15] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[05:15:15] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[05:15:15] =========== drm_validate_clone_mode (2 subtests) ===========
[05:15:15] ============== drm_test_check_in_clone_mode  ===============
[05:15:15] [PASSED] in_clone_mode
[05:15:15] [PASSED] not_in_clone_mode
[05:15:15] ========== [PASSED] drm_test_check_in_clone_mode ===========
[05:15:15] =============== drm_test_check_valid_clones  ===============
[05:15:15] [PASSED] not_in_clone_mode
[05:15:15] [PASSED] valid_clone
[05:15:15] [PASSED] invalid_clone
[05:15:15] =========== [PASSED] drm_test_check_valid_clones ===========
[05:15:15] ============= [PASSED] drm_validate_clone_mode =============
[05:15:15] ============= drm_validate_modeset (1 subtest) =============
[05:15:15] [PASSED] drm_test_check_connector_changed_modeset
[05:15:15] ============== [PASSED] drm_validate_modeset ===============
[05:15:15] ====== drm_test_bridge_get_current_state (1 subtest) =======
[05:15:15] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[05:15:15] ======== [PASSED] drm_test_bridge_get_current_state ========
[05:15:15] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[05:15:15] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[05:15:15] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[05:15:15] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[05:15:15] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[05:15:15] ============== drm_bridge_alloc (2 subtests) ===============
[05:15:15] [PASSED] drm_test_drm_bridge_alloc_basic
[05:15:15] [PASSED] drm_test_drm_bridge_alloc_get_put
[05:15:15] ================ [PASSED] drm_bridge_alloc =================
[05:15:15] ============= drm_bridge_bus_fmt (5 subtests) ==============
[05:15:15] [PASSED] drm_test_bridge_rgb_yuv_rgb
[05:15:15] [PASSED] drm_test_bridge_must_convert_to_yuv444
[05:15:15] [PASSED] drm_test_bridge_hdmi_auto_rgb
[05:15:15] [PASSED] drm_test_bridge_auto_first
[05:15:15] [PASSED] drm_test_bridge_rgb_yuv_no_path
[05:15:15] =============== [PASSED] drm_bridge_bus_fmt ================
[05:15:15] ============= drm_cmdline_parser (40 subtests) =============
[05:15:15] [PASSED] drm_test_cmdline_force_d_only
[05:15:15] [PASSED] drm_test_cmdline_force_D_only_dvi
[05:15:15] [PASSED] drm_test_cmdline_force_D_only_hdmi
[05:15:15] [PASSED] drm_test_cmdline_force_D_only_not_digital
[05:15:15] [PASSED] drm_test_cmdline_force_e_only
[05:15:15] [PASSED] drm_test_cmdline_res
[05:15:15] [PASSED] drm_test_cmdline_res_vesa
[05:15:15] [PASSED] drm_test_cmdline_res_vesa_rblank
[05:15:15] [PASSED] drm_test_cmdline_res_rblank
[05:15:15] [PASSED] drm_test_cmdline_res_bpp
[05:15:15] [PASSED] drm_test_cmdline_res_refresh
[05:15:15] [PASSED] drm_test_cmdline_res_bpp_refresh
[05:15:15] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[05:15:15] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[05:15:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[05:15:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[05:15:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[05:15:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[05:15:15] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[05:15:15] [PASSED] drm_test_cmdline_res_margins_force_on
[05:15:15] [PASSED] drm_test_cmdline_res_vesa_margins
[05:15:15] [PASSED] drm_test_cmdline_name
[05:15:15] [PASSED] drm_test_cmdline_name_bpp
[05:15:15] [PASSED] drm_test_cmdline_name_option
[05:15:15] [PASSED] drm_test_cmdline_name_bpp_option
[05:15:15] [PASSED] drm_test_cmdline_rotate_0
[05:15:15] [PASSED] drm_test_cmdline_rotate_90
[05:15:15] [PASSED] drm_test_cmdline_rotate_180
[05:15:15] [PASSED] drm_test_cmdline_rotate_270
[05:15:15] [PASSED] drm_test_cmdline_hmirror
[05:15:15] [PASSED] drm_test_cmdline_vmirror
[05:15:15] [PASSED] drm_test_cmdline_margin_options
[05:15:15] [PASSED] drm_test_cmdline_multiple_options
[05:15:15] [PASSED] drm_test_cmdline_bpp_extra_and_option
[05:15:15] [PASSED] drm_test_cmdline_extra_and_option
[05:15:15] [PASSED] drm_test_cmdline_freestanding_options
[05:15:15] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[05:15:15] [PASSED] drm_test_cmdline_panel_orientation
[05:15:15] ================ drm_test_cmdline_invalid  =================
[05:15:15] [PASSED] margin_only
[05:15:15] [PASSED] interlace_only
[05:15:15] [PASSED] res_missing_x
[05:15:15] [PASSED] res_missing_y
[05:15:15] [PASSED] res_bad_y
[05:15:15] [PASSED] res_missing_y_bpp
[05:15:15] [PASSED] res_bad_bpp
[05:15:15] [PASSED] res_bad_refresh
[05:15:15] [PASSED] res_bpp_refresh_force_on_off
[05:15:15] [PASSED] res_invalid_mode
[05:15:15] [PASSED] res_bpp_wrong_place_mode
[05:15:15] [PASSED] name_bpp_refresh
[05:15:15] [PASSED] name_refresh
[05:15:15] [PASSED] name_refresh_wrong_mode
[05:15:15] [PASSED] name_refresh_invalid_mode
[05:15:15] [PASSED] rotate_multiple
[05:15:15] [PASSED] rotate_invalid_val
[05:15:15] [PASSED] rotate_truncated
[05:15:15] [PASSED] invalid_option
[05:15:15] [PASSED] invalid_tv_option
[05:15:15] [PASSED] truncated_tv_option
[05:15:15] ============ [PASSED] drm_test_cmdline_invalid =============
[05:15:15] =============== drm_test_cmdline_tv_options  ===============
[05:15:15] [PASSED] NTSC
[05:15:15] [PASSED] NTSC_443
[05:15:15] [PASSED] NTSC_J
[05:15:15] [PASSED] PAL
[05:15:15] [PASSED] PAL_M
[05:15:15] [PASSED] PAL_N
[05:15:15] [PASSED] SECAM
[05:15:15] [PASSED] MONO_525
[05:15:15] [PASSED] MONO_625
[05:15:15] =========== [PASSED] drm_test_cmdline_tv_options ===========
[05:15:15] =============== [PASSED] drm_cmdline_parser ================
[05:15:15] ========== drmm_connector_hdmi_init (20 subtests) ==========
[05:15:15] [PASSED] drm_test_connector_hdmi_init_valid
[05:15:15] [PASSED] drm_test_connector_hdmi_init_bpc_8
[05:15:15] [PASSED] drm_test_connector_hdmi_init_bpc_10
[05:15:15] [PASSED] drm_test_connector_hdmi_init_bpc_12
[05:15:15] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[05:15:15] [PASSED] drm_test_connector_hdmi_init_bpc_null
[05:15:15] [PASSED] drm_test_connector_hdmi_init_formats_empty
[05:15:15] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[05:15:15] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[05:15:15] [PASSED] supported_formats=0x9 yuv420_allowed=1
[05:15:15] [PASSED] supported_formats=0x9 yuv420_allowed=0
[05:15:15] [PASSED] supported_formats=0x5 yuv420_allowed=1
[05:15:15] [PASSED] supported_formats=0x5 yuv420_allowed=0
[05:15:15] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[05:15:15] [PASSED] drm_test_connector_hdmi_init_null_ddc
[05:15:15] [PASSED] drm_test_connector_hdmi_init_null_product
[05:15:15] [PASSED] drm_test_connector_hdmi_init_null_vendor
[05:15:15] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[05:15:15] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[05:15:15] [PASSED] drm_test_connector_hdmi_init_product_valid
[05:15:15] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[05:15:15] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[05:15:15] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[05:15:15] ========= drm_test_connector_hdmi_init_type_valid  =========
[05:15:15] [PASSED] HDMI-A
[05:15:15] [PASSED] HDMI-B
[05:15:15] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[05:15:15] ======== drm_test_connector_hdmi_init_type_invalid  ========
[05:15:15] [PASSED] Unknown
[05:15:15] [PASSED] VGA
[05:15:15] [PASSED] DVI-I
[05:15:15] [PASSED] DVI-D
[05:15:15] [PASSED] DVI-A
[05:15:15] [PASSED] Composite
[05:15:15] [PASSED] SVIDEO
[05:15:15] [PASSED] LVDS
[05:15:15] [PASSED] Component
[05:15:15] [PASSED] DIN
[05:15:15] [PASSED] DP
[05:15:15] [PASSED] TV
[05:15:15] [PASSED] eDP
[05:15:15] [PASSED] Virtual
[05:15:15] [PASSED] DSI
[05:15:15] [PASSED] DPI
[05:15:15] [PASSED] Writeback
[05:15:15] [PASSED] SPI
[05:15:15] [PASSED] USB
[05:15:15] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[05:15:15] ============ [PASSED] drmm_connector_hdmi_init =============
[05:15:15] ============= drmm_connector_init (3 subtests) =============
[05:15:15] [PASSED] drm_test_drmm_connector_init
[05:15:15] [PASSED] drm_test_drmm_connector_init_null_ddc
[05:15:15] ========= drm_test_drmm_connector_init_type_valid  =========
[05:15:15] [PASSED] Unknown
[05:15:15] [PASSED] VGA
[05:15:15] [PASSED] DVI-I
[05:15:15] [PASSED] DVI-D
[05:15:15] [PASSED] DVI-A
[05:15:15] [PASSED] Composite
[05:15:15] [PASSED] SVIDEO
[05:15:15] [PASSED] LVDS
[05:15:15] [PASSED] Component
[05:15:15] [PASSED] DIN
[05:15:15] [PASSED] DP
[05:15:15] [PASSED] HDMI-A
[05:15:15] [PASSED] HDMI-B
[05:15:15] [PASSED] TV
[05:15:15] [PASSED] eDP
[05:15:15] [PASSED] Virtual
[05:15:15] [PASSED] DSI
[05:15:15] [PASSED] DPI
[05:15:15] [PASSED] Writeback
[05:15:15] [PASSED] SPI
[05:15:15] [PASSED] USB
[05:15:15] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[05:15:15] =============== [PASSED] drmm_connector_init ===============
[05:15:15] ========= drm_connector_dynamic_init (6 subtests) ==========
[05:15:15] [PASSED] drm_test_drm_connector_dynamic_init
[05:15:15] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[05:15:15] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[05:15:15] [PASSED] drm_test_drm_connector_dynamic_init_properties
[05:15:15] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[05:15:15] [PASSED] Unknown
[05:15:15] [PASSED] VGA
[05:15:15] [PASSED] DVI-I
[05:15:15] [PASSED] DVI-D
[05:15:15] [PASSED] DVI-A
[05:15:15] [PASSED] Composite
[05:15:15] [PASSED] SVIDEO
[05:15:15] [PASSED] LVDS
[05:15:15] [PASSED] Component
[05:15:15] [PASSED] DIN
[05:15:15] [PASSED] DP
[05:15:15] [PASSED] HDMI-A
[05:15:15] [PASSED] HDMI-B
[05:15:15] [PASSED] TV
[05:15:15] [PASSED] eDP
[05:15:15] [PASSED] Virtual
[05:15:15] [PASSED] DSI
[05:15:15] [PASSED] DPI
[05:15:15] [PASSED] Writeback
[05:15:15] [PASSED] SPI
[05:15:15] [PASSED] USB
[05:15:15] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[05:15:15] ======== drm_test_drm_connector_dynamic_init_name  =========
[05:15:15] [PASSED] Unknown
[05:15:15] [PASSED] VGA
[05:15:15] [PASSED] DVI-I
[05:15:15] [PASSED] DVI-D
[05:15:15] [PASSED] DVI-A
[05:15:15] [PASSED] Composite
[05:15:15] [PASSED] SVIDEO
[05:15:15] [PASSED] LVDS
[05:15:15] [PASSED] Component
[05:15:15] [PASSED] DIN
[05:15:15] [PASSED] DP
[05:15:15] [PASSED] HDMI-A
[05:15:15] [PASSED] HDMI-B
[05:15:15] [PASSED] TV
[05:15:15] [PASSED] eDP
[05:15:15] [PASSED] Virtual
[05:15:15] [PASSED] DSI
[05:15:15] [PASSED] DPI
[05:15:15] [PASSED] Writeback
[05:15:15] [PASSED] SPI
[05:15:15] [PASSED] USB
[05:15:15] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[05:15:15] =========== [PASSED] drm_connector_dynamic_init ============
[05:15:15] ==== drm_connector_dynamic_register_early (4 subtests) =====
[05:15:15] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[05:15:15] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[05:15:15] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[05:15:15] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[05:15:15] ====== [PASSED] drm_connector_dynamic_register_early =======
[05:15:15] ======= drm_connector_dynamic_register (7 subtests) ========
[05:15:15] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[05:15:15] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[05:15:15] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[05:15:15] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[05:15:15] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[05:15:15] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[05:15:15] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[05:15:15] ========= [PASSED] drm_connector_dynamic_register ==========
[05:15:15] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[05:15:15] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[05:15:15] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[05:15:15] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[05:15:15] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[05:15:15] ========== drm_test_get_tv_mode_from_name_valid  ===========
[05:15:15] [PASSED] NTSC
[05:15:15] [PASSED] NTSC-443
[05:15:15] [PASSED] NTSC-J
[05:15:15] [PASSED] PAL
[05:15:15] [PASSED] PAL-M
[05:15:15] [PASSED] PAL-N
[05:15:15] [PASSED] SECAM
[05:15:15] [PASSED] Mono
[05:15:15] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[05:15:15] [PASSED] drm_test_get_tv_mode_from_name_truncated
[05:15:15] ============ [PASSED] drm_get_tv_mode_from_name ============
[05:15:15] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[05:15:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[05:15:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[05:15:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[05:15:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[05:15:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[05:15:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[05:15:15] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[05:15:15] [PASSED] VIC 96
[05:15:15] [PASSED] VIC 97
[05:15:15] [PASSED] VIC 101
[05:15:15] [PASSED] VIC 102
[05:15:15] [PASSED] VIC 106
[05:15:15] [PASSED] VIC 107
[05:15:15] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[05:15:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[05:15:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[05:15:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[05:15:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[05:15:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[05:15:15] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[05:15:15] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[05:15:15] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[05:15:15] [PASSED] Automatic
[05:15:15] [PASSED] Full
[05:15:15] [PASSED] Limited 16:235
[05:15:15] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[05:15:15] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[05:15:15] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[05:15:15] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[05:15:15] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[05:15:15] [PASSED] RGB
[05:15:15] [PASSED] YUV 4:2:0
[05:15:15] [PASSED] YUV 4:2:2
[05:15:15] [PASSED] YUV 4:4:4
[05:15:15] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[05:15:15] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[05:15:15] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[05:15:15] ============= drm_damage_helper (21 subtests) ==============
[05:15:15] [PASSED] drm_test_damage_iter_no_damage
[05:15:15] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[05:15:15] [PASSED] drm_test_damage_iter_no_damage_src_moved
[05:15:15] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[05:15:15] [PASSED] drm_test_damage_iter_no_damage_not_visible
[05:15:15] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[05:15:15] [PASSED] drm_test_damage_iter_no_damage_no_fb
[05:15:15] [PASSED] drm_test_damage_iter_simple_damage
[05:15:15] [PASSED] drm_test_damage_iter_single_damage
[05:15:15] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[05:15:15] [PASSED] drm_test_damage_iter_single_damage_outside_src
[05:15:16] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[05:15:16] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[05:15:16] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[05:15:16] [PASSED] drm_test_damage_iter_single_damage_src_moved
[05:15:16] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[05:15:16] [PASSED] drm_test_damage_iter_damage
[05:15:16] [PASSED] drm_test_damage_iter_damage_one_intersect
[05:15:16] [PASSED] drm_test_damage_iter_damage_one_outside
[05:15:16] [PASSED] drm_test_damage_iter_damage_src_moved
[05:15:16] [PASSED] drm_test_damage_iter_damage_not_visible
[05:15:16] ================ [PASSED] drm_damage_helper ================
[05:15:16] ============== drm_dp_mst_helper (3 subtests) ==============
[05:15:16] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[05:15:16] [PASSED] Clock 154000 BPP 30 DSC disabled
[05:15:16] [PASSED] Clock 234000 BPP 30 DSC disabled
[05:15:16] [PASSED] Clock 297000 BPP 24 DSC disabled
[05:15:16] [PASSED] Clock 332880 BPP 24 DSC enabled
[05:15:16] [PASSED] Clock 324540 BPP 24 DSC enabled
[05:15:16] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[05:15:16] ============== drm_test_dp_mst_calc_pbn_div  ===============
[05:15:16] [PASSED] Link rate 2000000 lane count 4
[05:15:16] [PASSED] Link rate 2000000 lane count 2
[05:15:16] [PASSED] Link rate 2000000 lane count 1
[05:15:16] [PASSED] Link rate 1350000 lane count 4
[05:15:16] [PASSED] Link rate 1350000 lane count 2
[05:15:16] [PASSED] Link rate 1350000 lane count 1
[05:15:16] [PASSED] Link rate 1000000 lane count 4
[05:15:16] [PASSED] Link rate 1000000 lane count 2
[05:15:16] [PASSED] Link rate 1000000 lane count 1
[05:15:16] [PASSED] Link rate 810000 lane count 4
[05:15:16] [PASSED] Link rate 810000 lane count 2
[05:15:16] [PASSED] Link rate 810000 lane count 1
[05:15:16] [PASSED] Link rate 540000 lane count 4
[05:15:16] [PASSED] Link rate 540000 lane count 2
[05:15:16] [PASSED] Link rate 540000 lane count 1
[05:15:16] [PASSED] Link rate 270000 lane count 4
[05:15:16] [PASSED] Link rate 270000 lane count 2
[05:15:16] [PASSED] Link rate 270000 lane count 1
[05:15:16] [PASSED] Link rate 162000 lane count 4
[05:15:16] [PASSED] Link rate 162000 lane count 2
[05:15:16] [PASSED] Link rate 162000 lane count 1
[05:15:16] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[05:15:16] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[05:15:16] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[05:15:16] [PASSED] DP_POWER_UP_PHY with port number
[05:15:16] [PASSED] DP_POWER_DOWN_PHY with port number
[05:15:16] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[05:15:16] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[05:15:16] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[05:15:16] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[05:15:16] [PASSED] DP_QUERY_PAYLOAD with port number
[05:15:16] [PASSED] DP_QUERY_PAYLOAD with VCPI
[05:15:16] [PASSED] DP_REMOTE_DPCD_READ with port number
[05:15:16] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[05:15:16] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[05:15:16] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[05:15:16] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[05:15:16] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[05:15:16] [PASSED] DP_REMOTE_I2C_READ with port number
[05:15:16] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[05:15:16] [PASSED] DP_REMOTE_I2C_READ with transactions array
[05:15:16] [PASSED] DP_REMOTE_I2C_WRITE with port number
[05:15:16] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[05:15:16] [PASSED] DP_REMOTE_I2C_WRITE with data array
[05:15:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[05:15:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[05:15:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[05:15:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[05:15:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[05:15:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[05:15:16] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[05:15:16] ================ [PASSED] drm_dp_mst_helper ================
[05:15:16] ================== drm_exec (7 subtests) ===================
[05:15:16] [PASSED] sanitycheck
[05:15:16] [PASSED] test_lock
[05:15:16] [PASSED] test_lock_unlock
[05:15:16] [PASSED] test_duplicates
[05:15:16] [PASSED] test_prepare
[05:15:16] [PASSED] test_prepare_array
[05:15:16] [PASSED] test_multiple_loops
[05:15:16] ==================== [PASSED] drm_exec =====================
[05:15:16] =========== drm_format_helper_test (17 subtests) ===========
[05:15:16] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[05:15:16] [PASSED] single_pixel_source_buffer
[05:15:16] [PASSED] single_pixel_clip_rectangle
[05:15:16] [PASSED] well_known_colors
[05:15:16] [PASSED] destination_pitch
[05:15:16] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[05:15:16] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[05:15:16] [PASSED] single_pixel_source_buffer
[05:15:16] [PASSED] single_pixel_clip_rectangle
[05:15:16] [PASSED] well_known_colors
[05:15:16] [PASSED] destination_pitch
[05:15:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[05:15:16] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[05:15:16] [PASSED] single_pixel_source_buffer
[05:15:16] [PASSED] single_pixel_clip_rectangle
[05:15:16] [PASSED] well_known_colors
[05:15:16] [PASSED] destination_pitch
[05:15:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[05:15:16] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[05:15:16] [PASSED] single_pixel_source_buffer
[05:15:16] [PASSED] single_pixel_clip_rectangle
[05:15:16] [PASSED] well_known_colors
[05:15:16] [PASSED] destination_pitch
[05:15:16] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[05:15:16] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[05:15:16] [PASSED] single_pixel_source_buffer
[05:15:16] [PASSED] single_pixel_clip_rectangle
[05:15:16] [PASSED] well_known_colors
[05:15:16] [PASSED] destination_pitch
[05:15:16] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[05:15:16] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[05:15:16] [PASSED] single_pixel_source_buffer
[05:15:16] [PASSED] single_pixel_clip_rectangle
[05:15:16] [PASSED] well_known_colors
[05:15:16] [PASSED] destination_pitch
[05:15:16] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[05:15:16] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[05:15:16] [PASSED] single_pixel_source_buffer
[05:15:16] [PASSED] single_pixel_clip_rectangle
[05:15:16] [PASSED] well_known_colors
[05:15:16] [PASSED] destination_pitch
[05:15:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[05:15:16] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[05:15:16] [PASSED] single_pixel_source_buffer
[05:15:16] [PASSED] single_pixel_clip_rectangle
[05:15:16] [PASSED] well_known_colors
[05:15:16] [PASSED] destination_pitch
[05:15:16] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[05:15:16] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[05:15:16] [PASSED] single_pixel_source_buffer
[05:15:16] [PASSED] single_pixel_clip_rectangle
[05:15:16] [PASSED] well_known_colors
[05:15:16] [PASSED] destination_pitch
[05:15:16] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[05:15:16] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[05:15:16] [PASSED] single_pixel_source_buffer
[05:15:16] [PASSED] single_pixel_clip_rectangle
[05:15:16] [PASSED] well_known_colors
[05:15:16] [PASSED] destination_pitch
[05:15:16] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[05:15:16] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[05:15:16] [PASSED] single_pixel_source_buffer
[05:15:16] [PASSED] single_pixel_clip_rectangle
[05:15:16] [PASSED] well_known_colors
[05:15:16] [PASSED] destination_pitch
[05:15:16] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[05:15:16] ============== drm_test_fb_xrgb8888_to_mono  ===============
[05:15:16] [PASSED] single_pixel_source_buffer
[05:15:16] [PASSED] single_pixel_clip_rectangle
[05:15:16] [PASSED] well_known_colors
[05:15:16] [PASSED] destination_pitch
[05:15:16] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[05:15:16] ==================== drm_test_fb_swab  =====================
[05:15:16] [PASSED] single_pixel_source_buffer
[05:15:16] [PASSED] single_pixel_clip_rectangle
[05:15:16] [PASSED] well_known_colors
[05:15:16] [PASSED] destination_pitch
[05:15:16] ================ [PASSED] drm_test_fb_swab =================
[05:15:16] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[05:15:16] [PASSED] single_pixel_source_buffer
[05:15:16] [PASSED] single_pixel_clip_rectangle
[05:15:16] [PASSED] well_known_colors
[05:15:16] [PASSED] destination_pitch
[05:15:16] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[05:15:16] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[05:15:16] [PASSED] single_pixel_source_buffer
[05:15:16] [PASSED] single_pixel_clip_rectangle
[05:15:16] [PASSED] well_known_colors
[05:15:16] [PASSED] destination_pitch
[05:15:16] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[05:15:16] ================= drm_test_fb_clip_offset  =================
[05:15:16] [PASSED] pass through
[05:15:16] [PASSED] horizontal offset
[05:15:16] [PASSED] vertical offset
[05:15:16] [PASSED] horizontal and vertical offset
[05:15:16] [PASSED] horizontal offset (custom pitch)
[05:15:16] [PASSED] vertical offset (custom pitch)
[05:15:16] [PASSED] horizontal and vertical offset (custom pitch)
[05:15:16] ============= [PASSED] drm_test_fb_clip_offset =============
[05:15:16] =================== drm_test_fb_memcpy  ====================
[05:15:16] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[05:15:16] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[05:15:16] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[05:15:16] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[05:15:16] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[05:15:16] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[05:15:16] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[05:15:16] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[05:15:16] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[05:15:16] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[05:15:16] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[05:15:16] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[05:15:16] =============== [PASSED] drm_test_fb_memcpy ================
[05:15:16] ============= [PASSED] drm_format_helper_test ==============
[05:15:16] ================= drm_format (18 subtests) =================
[05:15:16] [PASSED] drm_test_format_block_width_invalid
[05:15:16] [PASSED] drm_test_format_block_width_one_plane
[05:15:16] [PASSED] drm_test_format_block_width_two_plane
[05:15:16] [PASSED] drm_test_format_block_width_three_plane
[05:15:16] [PASSED] drm_test_format_block_width_tiled
[05:15:16] [PASSED] drm_test_format_block_height_invalid
[05:15:16] [PASSED] drm_test_format_block_height_one_plane
[05:15:16] [PASSED] drm_test_format_block_height_two_plane
[05:15:16] [PASSED] drm_test_format_block_height_three_plane
[05:15:16] [PASSED] drm_test_format_block_height_tiled
[05:15:16] [PASSED] drm_test_format_min_pitch_invalid
[05:15:16] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[05:15:16] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[05:15:16] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[05:15:16] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[05:15:16] [PASSED] drm_test_format_min_pitch_two_plane
[05:15:16] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[05:15:16] [PASSED] drm_test_format_min_pitch_tiled
[05:15:16] =================== [PASSED] drm_format ====================
[05:15:16] ============== drm_framebuffer (10 subtests) ===============
[05:15:16] ========== drm_test_framebuffer_check_src_coords  ==========
[05:15:16] [PASSED] Success: source fits into fb
[05:15:16] [PASSED] Fail: overflowing fb with x-axis coordinate
[05:15:16] [PASSED] Fail: overflowing fb with y-axis coordinate
[05:15:16] [PASSED] Fail: overflowing fb with source width
[05:15:16] [PASSED] Fail: overflowing fb with source height
[05:15:16] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[05:15:16] [PASSED] drm_test_framebuffer_cleanup
[05:15:16] =============== drm_test_framebuffer_create  ===============
[05:15:16] [PASSED] ABGR8888 normal sizes
[05:15:16] [PASSED] ABGR8888 max sizes
[05:15:16] [PASSED] ABGR8888 pitch greater than min required
[05:15:16] [PASSED] ABGR8888 pitch less than min required
[05:15:16] [PASSED] ABGR8888 Invalid width
[05:15:16] [PASSED] ABGR8888 Invalid buffer handle
[05:15:16] [PASSED] No pixel format
[05:15:16] [PASSED] ABGR8888 Width 0
[05:15:16] [PASSED] ABGR8888 Height 0
[05:15:16] [PASSED] ABGR8888 Out of bound height * pitch combination
[05:15:16] [PASSED] ABGR8888 Large buffer offset
[05:15:16] [PASSED] ABGR8888 Buffer offset for inexistent plane
[05:15:16] [PASSED] ABGR8888 Invalid flag
[05:15:16] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[05:15:16] [PASSED] ABGR8888 Valid buffer modifier
[05:15:16] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[05:15:16] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[05:15:16] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[05:15:16] [PASSED] NV12 Normal sizes
[05:15:16] [PASSED] NV12 Max sizes
[05:15:16] [PASSED] NV12 Invalid pitch
[05:15:16] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[05:15:16] [PASSED] NV12 different  modifier per-plane
[05:15:16] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[05:15:16] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[05:15:16] [PASSED] NV12 Modifier for inexistent plane
[05:15:16] [PASSED] NV12 Handle for inexistent plane
[05:15:16] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[05:15:16] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[05:15:16] [PASSED] YVU420 Normal sizes
[05:15:16] [PASSED] YVU420 Max sizes
[05:15:16] [PASSED] YVU420 Invalid pitch
[05:15:16] [PASSED] YVU420 Different pitches
[05:15:16] [PASSED] YVU420 Different buffer offsets/pitches
[05:15:16] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[05:15:16] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[05:15:16] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[05:15:16] [PASSED] YVU420 Valid modifier
[05:15:16] [PASSED] YVU420 Different modifiers per plane
[05:15:16] [PASSED] YVU420 Modifier for inexistent plane
[05:15:16] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[05:15:16] [PASSED] X0L2 Normal sizes
[05:15:16] [PASSED] X0L2 Max sizes
[05:15:16] [PASSED] X0L2 Invalid pitch
[05:15:16] [PASSED] X0L2 Pitch greater than minimum required
[05:15:16] [PASSED] X0L2 Handle for inexistent plane
[05:15:16] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[05:15:16] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[05:15:16] [PASSED] X0L2 Valid modifier
[05:15:16] [PASSED] X0L2 Modifier for inexistent plane
[05:15:16] =========== [PASSED] drm_test_framebuffer_create ===========
[05:15:16] [PASSED] drm_test_framebuffer_free
[05:15:16] [PASSED] drm_test_framebuffer_init
[05:15:16] [PASSED] drm_test_framebuffer_init_bad_format
[05:15:16] [PASSED] drm_test_framebuffer_init_dev_mismatch
[05:15:16] [PASSED] drm_test_framebuffer_lookup
[05:15:16] [PASSED] drm_test_framebuffer_lookup_inexistent
[05:15:16] [PASSED] drm_test_framebuffer_modifiers_not_supported
[05:15:16] ================= [PASSED] drm_framebuffer =================
[05:15:16] ================ drm_gem_shmem (8 subtests) ================
[05:15:16] [PASSED] drm_gem_shmem_test_obj_create
[05:15:16] [PASSED] drm_gem_shmem_test_obj_create_private
[05:15:16] [PASSED] drm_gem_shmem_test_pin_pages
[05:15:16] [PASSED] drm_gem_shmem_test_vmap
[05:15:16] [PASSED] drm_gem_shmem_test_get_sg_table
[05:15:16] [PASSED] drm_gem_shmem_test_get_pages_sgt
[05:15:16] [PASSED] drm_gem_shmem_test_madvise
[05:15:16] [PASSED] drm_gem_shmem_test_purge
[05:15:16] ================== [PASSED] drm_gem_shmem ==================
[05:15:16] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[05:15:16] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[05:15:16] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[05:15:16] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[05:15:16] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[05:15:16] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[05:15:16] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[05:15:16] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[05:15:16] [PASSED] Automatic
[05:15:16] [PASSED] Full
[05:15:16] [PASSED] Limited 16:235
[05:15:16] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[05:15:16] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[05:15:16] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[05:15:16] [PASSED] drm_test_check_disable_connector
[05:15:16] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[05:15:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[05:15:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[05:15:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[05:15:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[05:15:16] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[05:15:16] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[05:15:16] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[05:15:16] [PASSED] drm_test_check_output_bpc_dvi
[05:15:16] [PASSED] drm_test_check_output_bpc_format_vic_1
[05:15:16] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[05:15:16] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[05:15:16] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[05:15:16] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[05:15:16] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[05:15:16] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[05:15:16] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[05:15:16] ============ drm_test_check_hdmi_color_format  =============
[05:15:16] [PASSED] AUTO -> RGB
[05:15:16] [PASSED] YCBCR422 -> YUV422
[05:15:16] [PASSED] YCBCR420 -> YUV420
[05:15:16] [PASSED] YCBCR444 -> YUV444
[05:15:16] [PASSED] RGB -> RGB
[05:15:16] ======== [PASSED] drm_test_check_hdmi_color_format =========
[05:15:16] ======== drm_test_check_hdmi_color_format_420_only  ========
[05:15:16] [PASSED] RGB should fail
[05:15:16] [PASSED] YUV444 should fail
[05:15:16] [PASSED] YUV422 should fail
[05:15:16] [PASSED] YUV420 should work
[05:15:16] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[05:15:16] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[05:15:16] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[05:15:16] [PASSED] drm_test_check_broadcast_rgb_value
[05:15:16] [PASSED] drm_test_check_bpc_8_value
[05:15:16] [PASSED] drm_test_check_bpc_10_value
[05:15:16] [PASSED] drm_test_check_bpc_12_value
[05:15:16] [PASSED] drm_test_check_format_value
[05:15:16] [PASSED] drm_test_check_tmds_char_value
[05:15:16] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[05:15:16] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[05:15:16] [PASSED] drm_test_check_mode_valid
[05:15:16] [PASSED] drm_test_check_mode_valid_reject
[05:15:16] [PASSED] drm_test_check_mode_valid_reject_rate
[05:15:16] [PASSED] drm_test_check_mode_valid_reject_max_clock
[05:15:16] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[05:15:16] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[05:15:16] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[05:15:16] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[05:15:16] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[05:15:16] [PASSED] drm_test_check_infoframes
[05:15:16] [PASSED] drm_test_check_reject_avi_infoframe
[05:15:16] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[05:15:16] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[05:15:16] [PASSED] drm_test_check_reject_audio_infoframe
[05:15:16] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[05:15:16] ================= drm_managed (2 subtests) =================
[05:15:16] [PASSED] drm_test_managed_release_action
[05:15:16] [PASSED] drm_test_managed_run_action
[05:15:16] =================== [PASSED] drm_managed ===================
[05:15:16] =================== drm_mm (6 subtests) ====================
[05:15:16] [PASSED] drm_test_mm_init
[05:15:16] [PASSED] drm_test_mm_debug
[05:15:16] [PASSED] drm_test_mm_align32
[05:15:16] [PASSED] drm_test_mm_align64
[05:15:16] [PASSED] drm_test_mm_lowest
[05:15:16] [PASSED] drm_test_mm_highest
[05:15:16] ===================== [PASSED] drm_mm ======================
[05:15:16] ============= drm_modes_analog_tv (5 subtests) =============
[05:15:16] [PASSED] drm_test_modes_analog_tv_mono_576i
[05:15:16] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[05:15:16] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[05:15:16] [PASSED] drm_test_modes_analog_tv_pal_576i
[05:15:16] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[05:15:16] =============== [PASSED] drm_modes_analog_tv ===============
[05:15:16] ============== drm_plane_helper (2 subtests) ===============
[05:15:16] =============== drm_test_check_plane_state  ================
[05:15:16] [PASSED] clipping_simple
[05:15:16] [PASSED] clipping_rotate_reflect
[05:15:16] [PASSED] positioning_simple
[05:15:16] [PASSED] upscaling
[05:15:16] [PASSED] downscaling
[05:15:16] [PASSED] rounding1
[05:15:16] [PASSED] rounding2
[05:15:16] [PASSED] rounding3
[05:15:16] [PASSED] rounding4
[05:15:16] =========== [PASSED] drm_test_check_plane_state ============
[05:15:16] =========== drm_test_check_invalid_plane_state  ============
[05:15:16] [PASSED] positioning_invalid
[05:15:16] [PASSED] upscaling_invalid
[05:15:16] [PASSED] downscaling_invalid
[05:15:16] ======= [PASSED] drm_test_check_invalid_plane_state ========
[05:15:16] ================ [PASSED] drm_plane_helper =================
[05:15:16] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[05:15:16] ====== drm_test_connector_helper_tv_get_modes_check  =======
[05:15:16] [PASSED] None
[05:15:16] [PASSED] PAL
[05:15:16] [PASSED] NTSC
[05:15:16] [PASSED] Both, NTSC Default
[05:15:16] [PASSED] Both, PAL Default
[05:15:16] [PASSED] Both, NTSC Default, with PAL on command-line
[05:15:16] [PASSED] Both, PAL Default, with NTSC on command-line
[05:15:16] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[05:15:16] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[05:15:16] ================== drm_rect (9 subtests) ===================
[05:15:16] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[05:15:16] [PASSED] drm_test_rect_clip_scaled_not_clipped
[05:15:16] [PASSED] drm_test_rect_clip_scaled_clipped
[05:15:16] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[05:15:16] ================= drm_test_rect_intersect  =================
[05:15:16] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[05:15:16] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[05:15:16] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[05:15:16] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[05:15:16] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[05:15:16] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[05:15:16] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[05:15:16] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[05:15:16] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[05:15:16] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[05:15:16] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[05:15:16] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[05:15:16] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[05:15:16] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[05:15:16] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[05:15:16] ============= [PASSED] drm_test_rect_intersect =============
[05:15:16] ================ drm_test_rect_calc_hscale  ================
[05:15:16] [PASSED] normal use
[05:15:16] [PASSED] out of max range
[05:15:16] [PASSED] out of min range
[05:15:16] [PASSED] zero dst
[05:15:16] [PASSED] negative src
[05:15:16] [PASSED] negative dst
[05:15:16] ============ [PASSED] drm_test_rect_calc_hscale ============
[05:15:16] ================ drm_test_rect_calc_vscale  ================
[05:15:16] [PASSED] normal use
[05:15:16] [PASSED] out of max range
[05:15:16] [PASSED] out of min range
[05:15:16] [PASSED] zero dst
[05:15:16] [PASSED] negative src
[05:15:16] [PASSED] negative dst
[05:15:16] ============ [PASSED] drm_test_rect_calc_vscale ============
[05:15:16] ================== drm_test_rect_rotate  ===================
[05:15:16] [PASSED] reflect-x
[05:15:16] [PASSED] reflect-y
[05:15:16] [PASSED] rotate-0
[05:15:16] [PASSED] rotate-90
[05:15:16] [PASSED] rotate-180
[05:15:16] [PASSED] rotate-270
[05:15:16] ============== [PASSED] drm_test_rect_rotate ===============
[05:15:16] ================ drm_test_rect_rotate_inv  =================
[05:15:16] [PASSED] reflect-x
[05:15:16] [PASSED] reflect-y
[05:15:16] [PASSED] rotate-0
[05:15:16] [PASSED] rotate-90
[05:15:16] [PASSED] rotate-180
[05:15:16] [PASSED] rotate-270
[05:15:16] ============ [PASSED] drm_test_rect_rotate_inv =============
[05:15:16] ==================== [PASSED] drm_rect =====================
[05:15:16] ============ drm_sysfb_modeset_test (1 subtest) ============
[05:15:16] ============ drm_test_sysfb_build_fourcc_list  =============
[05:15:16] [PASSED] no native formats
[05:15:16] [PASSED] XRGB8888 as native format
[05:15:16] [PASSED] remove duplicates
[05:15:16] [PASSED] convert alpha formats
[05:15:16] [PASSED] random formats
[05:15:16] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[05:15:16] ============= [PASSED] drm_sysfb_modeset_test ==============
[05:15:16] ================== drm_fixp (2 subtests) ===================
[05:15:16] [PASSED] drm_test_int2fixp
[05:15:16] [PASSED] drm_test_sm2fixp
[05:15:16] ==================== [PASSED] drm_fixp =====================
[05:15:16] ============================================================
[05:15:16] Testing complete. Ran 641 tests: passed: 641
[05:15:16] Elapsed time: 26.466s total, 1.803s configuring, 24.494s building, 0.143s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[05:15:16] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:15:18] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:15:28] Starting KUnit Kernel (1/1)...
[05:15:28] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:15:28] ============= refcount_interrupt (4 subtests) ==============
[05:15:28] [PASSED] test_single_irq_change
[05:15:28] [PASSED] test_nested_irq_change
[05:15:28] [PASSED] test_multiple_irq_change
[05:15:28] [PASSED] test_irq_save
[05:15:28] =============== [PASSED] refcount_interrupt ================
[05:15:28] ================= ttm_device (5 subtests) ==================
[05:15:28] [PASSED] ttm_device_init_basic
[05:15:28] [PASSED] ttm_device_init_multiple
[05:15:28] [PASSED] ttm_device_fini_basic
[05:15:28] [PASSED] ttm_device_init_no_vma_man
[05:15:28] ================== ttm_device_init_pools  ==================
[05:15:28] [PASSED] No DMA allocations, no DMA32 required
[05:15:28] [PASSED] DMA allocations, DMA32 required
[05:15:28] [PASSED] No DMA allocations, DMA32 required
[05:15:28] [PASSED] DMA allocations, no DMA32 required
[05:15:28] ============== [PASSED] ttm_device_init_pools ==============
[05:15:28] =================== [PASSED] ttm_device ====================
[05:15:28] ================== ttm_pool (8 subtests) ===================
[05:15:28] ================== ttm_pool_alloc_basic  ===================
[05:15:28] [PASSED] One page
[05:15:28] [PASSED] More than one page
[05:15:28] [PASSED] Above the allocation limit
[05:15:28] [PASSED] One page, with coherent DMA mappings enabled
[05:15:28] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[05:15:28] ============== [PASSED] ttm_pool_alloc_basic ===============
[05:15:28] ============== ttm_pool_alloc_basic_dma_addr  ==============
[05:15:28] [PASSED] One page
[05:15:28] [PASSED] More than one page
[05:15:28] [PASSED] Above the allocation limit
[05:15:28] [PASSED] One page, with coherent DMA mappings enabled
[05:15:28] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[05:15:28] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[05:15:28] [PASSED] ttm_pool_alloc_order_caching_match
[05:15:28] [PASSED] ttm_pool_alloc_caching_mismatch
[05:15:28] [PASSED] ttm_pool_alloc_order_mismatch
[05:15:28] [PASSED] ttm_pool_free_dma_alloc
[05:15:28] [PASSED] ttm_pool_free_no_dma_alloc
[05:15:28] [PASSED] ttm_pool_fini_basic
[05:15:28] ==================== [PASSED] ttm_pool =====================
[05:15:28] ================ ttm_resource (8 subtests) =================
[05:15:28] ================= ttm_resource_init_basic  =================
[05:15:28] [PASSED] Init resource in TTM_PL_SYSTEM
[05:15:28] [PASSED] Init resource in TTM_PL_VRAM
[05:15:28] [PASSED] Init resource in a private placement
[05:15:28] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[05:15:28] ============= [PASSED] ttm_resource_init_basic =============
[05:15:28] [PASSED] ttm_resource_init_pinned
[05:15:28] [PASSED] ttm_resource_fini_basic
[05:15:28] [PASSED] ttm_resource_manager_init_basic
[05:15:28] [PASSED] ttm_resource_manager_usage_basic
[05:15:28] [PASSED] ttm_resource_manager_set_used_basic
[05:15:28] [PASSED] ttm_sys_man_alloc_basic
[05:15:28] [PASSED] ttm_sys_man_free_basic
[05:15:28] ================== [PASSED] ttm_resource ===================
[05:15:28] =================== ttm_tt (15 subtests) ===================
[05:15:28] ==================== ttm_tt_init_basic  ====================
[05:15:28] [PASSED] Page-aligned size
[05:15:28] [PASSED] Extra pages requested
[05:15:28] ================ [PASSED] ttm_tt_init_basic ================
[05:15:28] [PASSED] ttm_tt_init_misaligned
[05:15:28] [PASSED] ttm_tt_fini_basic
[05:15:28] [PASSED] ttm_tt_fini_sg
[05:15:28] [PASSED] ttm_tt_fini_shmem
[05:15:28] [PASSED] ttm_tt_create_basic
[05:15:28] [PASSED] ttm_tt_create_invalid_bo_type
[05:15:28] [PASSED] ttm_tt_create_ttm_exists
[05:15:28] [PASSED] ttm_tt_create_failed
[05:15:28] [PASSED] ttm_tt_destroy_basic
[05:15:28] [PASSED] ttm_tt_populate_null_ttm
[05:15:28] [PASSED] ttm_tt_populate_populated_ttm
[05:15:28] [PASSED] ttm_tt_unpopulate_basic
[05:15:28] [PASSED] ttm_tt_unpopulate_empty_ttm
[05:15:28] [PASSED] ttm_tt_swapin_basic
[05:15:28] ===================== [PASSED] ttm_tt ======================
[05:15:28] =================== ttm_bo (14 subtests) ===================
[05:15:28] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[05:15:28] [PASSED] Cannot be interrupted and sleeps
[05:15:28] [PASSED] Cannot be interrupted, locks straight away
[05:15:28] [PASSED] Can be interrupted, sleeps
[05:15:28] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[05:15:28] [PASSED] ttm_bo_reserve_locked_no_sleep
[05:15:28] [PASSED] ttm_bo_reserve_no_wait_ticket
[05:15:28] [PASSED] ttm_bo_reserve_double_resv
[05:15:28] [PASSED] ttm_bo_reserve_interrupted
[05:15:28] [PASSED] ttm_bo_reserve_deadlock
[05:15:28] [PASSED] ttm_bo_unreserve_basic
[05:15:28] [PASSED] ttm_bo_unreserve_pinned
[05:15:28] [PASSED] ttm_bo_unreserve_bulk
[05:15:28] [PASSED] ttm_bo_fini_basic
[05:15:28] [PASSED] ttm_bo_fini_shared_resv
[05:15:28] [PASSED] ttm_bo_pin_basic
[05:15:28] [PASSED] ttm_bo_pin_unpin_resource
[05:15:28] [PASSED] ttm_bo_multiple_pin_one_unpin
[05:15:28] ===================== [PASSED] ttm_bo ======================
[05:15:28] ============== ttm_bo_validate (22 subtests) ===============
[05:15:28] ============== ttm_bo_init_reserved_sys_man  ===============
[05:15:28] [PASSED] Buffer object for userspace
[05:15:28] [PASSED] Kernel buffer object
[05:15:28] [PASSED] Shared buffer object
[05:15:28] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[05:15:28] ============== ttm_bo_init_reserved_mock_man  ==============
[05:15:28] [PASSED] Buffer object for userspace
[05:15:28] [PASSED] Kernel buffer object
[05:15:28] [PASSED] Shared buffer object
[05:15:28] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[05:15:28] [PASSED] ttm_bo_init_reserved_resv
[05:15:28] ================== ttm_bo_validate_basic  ==================
[05:15:28] [PASSED] Buffer object for userspace
[05:15:28] [PASSED] Kernel buffer object
[05:15:28] [PASSED] Shared buffer object
[05:15:28] ============== [PASSED] ttm_bo_validate_basic ==============
[05:15:28] [PASSED] ttm_bo_validate_invalid_placement
[05:15:28] ============= ttm_bo_validate_same_placement  ==============
[05:15:28] [PASSED] System manager
[05:15:28] [PASSED] VRAM manager
[05:15:28] ========= [PASSED] ttm_bo_validate_same_placement ==========
[05:15:28] [PASSED] ttm_bo_validate_failed_alloc
[05:15:28] [PASSED] ttm_bo_validate_pinned
[05:15:28] [PASSED] ttm_bo_validate_busy_placement
[05:15:28] ================ ttm_bo_validate_multihop  =================
[05:15:28] [PASSED] Buffer object for userspace
[05:15:28] [PASSED] Kernel buffer object
[05:15:28] [PASSED] Shared buffer object
[05:15:28] ============ [PASSED] ttm_bo_validate_multihop =============
[05:15:28] ========== ttm_bo_validate_no_placement_signaled  ==========
[05:15:28] [PASSED] Buffer object in system domain, no page vector
[05:15:28] [PASSED] Buffer object in system domain with an existing page vector
[05:15:28] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[05:15:28] ======== ttm_bo_validate_no_placement_not_signaled  ========
[05:15:28] [PASSED] Buffer object for userspace
[05:15:28] [PASSED] Kernel buffer object
[05:15:28] [PASSED] Shared buffer object
[05:15:28] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[05:15:28] [PASSED] ttm_bo_validate_move_fence_signaled
[05:15:28] ========= ttm_bo_validate_move_fence_not_signaled  =========
[05:15:28] [PASSED] Waits for GPU
[05:15:28] [PASSED] Tries to lock straight away
[05:15:28] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[05:15:28] [PASSED] ttm_bo_validate_swapout
[05:15:28] [PASSED] ttm_bo_validate_happy_evict
[05:15:28] [PASSED] ttm_bo_validate_all_pinned_evict
[05:15:28] [PASSED] ttm_bo_validate_allowed_only_evict
[05:15:28] [PASSED] ttm_bo_validate_deleted_evict
[05:15:28] [PASSED] ttm_bo_validate_busy_domain_evict
[05:15:28] [PASSED] ttm_bo_validate_evict_gutting
[05:15:28] [PASSED] ttm_bo_validate_recrusive_evict
[05:15:28] ================= [PASSED] ttm_bo_validate =================
[05:15:28] ============================================================
[05:15:28] Testing complete. Ran 106 tests: passed: 106
[05:15:28] Elapsed time: 12.105s total, 1.845s configuring, 10.045s building, 0.184s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[05:15:28] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:15:30] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:15:39] Starting KUnit Kernel (1/1)...
[05:15:39] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:15:39] ============= refcount_interrupt (4 subtests) ==============
[05:15:39] [PASSED] test_single_irq_change
[05:15:39] [PASSED] test_nested_irq_change
[05:15:39] [PASSED] test_multiple_irq_change
[05:15:39] [PASSED] test_irq_save
[05:15:39] =============== [PASSED] refcount_interrupt ================
[05:15:39] =============== dma-buf-fence (12 subtests) ================
[05:15:39] [PASSED] test_sanitycheck
[05:15:39] [PASSED] test_signaling
[05:15:39] [PASSED] test_add_callback
[05:15:39] [PASSED] test_late_add_callback
[05:15:39] [PASSED] test_rm_callback
[05:15:39] [PASSED] test_late_rm_callback
[05:15:39] [PASSED] test_status
[05:15:39] [PASSED] test_error
[05:15:39] [PASSED] test_wait
[05:15:39] [PASSED] test_wait_timeout
[05:15:39] [PASSED] test_stub
[05:15:39] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[05:15:39] ================== [PASSED] dma-buf-fence ==================
[05:15:39] ============ dma-buf-fence-chain (11 subtests) =============
[05:15:39] [PASSED] test_sanitycheck
[05:15:39] [PASSED] test_find_seqno
[05:15:39] [PASSED] test_find_signaled
[05:15:39] [PASSED] test_find_out_of_order
[05:15:44] [PASSED] test_find_gap
[05:15:44] [PASSED] test_find_race
[05:15:44] [PASSED] test_signal_forward
[05:15:44] [PASSED] test_signal_backward
[05:15:44] [PASSED] test_wait_forward
[05:15:44] [PASSED] test_wait_backward
[05:15:44] [PASSED] test_wait_random
[05:15:44] =============== [PASSED] dma-buf-fence-chain ===============
[05:15:44] ============ dma-buf-fence-unwrap (10 subtests) ============
[05:15:44] [PASSED] test_sanitycheck
[05:15:44] [PASSED] test_unwrap_array
[05:15:44] [PASSED] test_unwrap_chain
[05:15:44] [PASSED] test_unwrap_chain_array
[05:15:44] [PASSED] test_unwrap_merge
[05:15:44] [PASSED] test_unwrap_merge_duplicate
[05:15:44] [PASSED] test_unwrap_merge_seqno
[05:15:44] [PASSED] test_unwrap_merge_order
[05:15:44] [PASSED] test_unwrap_merge_complex
[05:15:44] [PASSED] test_unwrap_merge_complex_seqno
[05:15:44] ============== [PASSED] dma-buf-fence-unwrap ===============
[05:15:44] ================ dma-buf-resv (5 subtests) =================
[05:15:44] [PASSED] test_sanitycheck
[05:15:44] ===================== test_signaling  ======================
[05:15:44] [PASSED] kernel
[05:15:44] [PASSED] write
[05:15:44] [PASSED] read
[05:15:44] [PASSED] bookkeep
[05:15:44] ================= [PASSED] test_signaling ==================
[05:15:44] ====================== test_for_each  ======================
[05:15:44] [PASSED] kernel
[05:15:44] [PASSED] write
[05:15:44] [PASSED] read
[05:15:44] [PASSED] bookkeep
[05:15:44] ================== [PASSED] test_for_each ==================
[05:15:44] ================= test_for_each_unlocked  ==================
[05:15:44] [PASSED] kernel
[05:15:44] [PASSED] write
[05:15:44] [PASSED] read
[05:15:44] [PASSED] bookkeep
[05:15:44] ============= [PASSED] test_for_each_unlocked ==============
[05:15:44] ===================== test_get_fences  =====================
[05:15:44] [PASSED] kernel
[05:15:44] [PASSED] write
[05:15:44] [PASSED] read
[05:15:44] [PASSED] bookkeep
[05:15:44] ================= [PASSED] test_get_fences =================
[05:15:44] ================== [PASSED] dma-buf-resv ===================
[05:15:44] ============================================================
[05:15:44] Testing complete. Ran 54 tests: passed: 53, skipped: 1
[05:15:44] Elapsed time: 15.932s total, 1.858s configuring, 8.702s building, 5.334s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Implement Wa_14021768792 to bypass m_n ratio limit (rev9)

[Patchwork]

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== Series Details ==

Series: Implement Wa_14021768792 to bypass m_n ratio limit (rev9)
URL   : https://patchwork.freedesktop.org/series/138256/
State : success

== Summary ==

CI Bug Log - changes from xe-5759-bb38af66c2f21340a7c081afbb7ace249357fbb5_BAT -> xe-pw-138256v9_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (15 -> 15)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-138256v9_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_waitfence@reltime:
    - bat-ptl-2:          [PASS][1] -> [FAIL][2] ([Intel XE#9115])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5759-bb38af66c2f21340a7c081afbb7ace249357fbb5/bat-ptl-2/igt@xe_waitfence@reltime.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/bat-ptl-2/igt@xe_waitfence@reltime.html

  
  [Intel XE#9115]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9115


Build changes
-------------

  * Linux: xe-5759-bb38af66c2f21340a7c081afbb7ace249357fbb5 -> xe-pw-138256v9

  IGT_9099: 9099
  xe-5759-bb38af66c2f21340a7c081afbb7ace249357fbb5: bb38af66c2f21340a7c081afbb7ace249357fbb5
  xe-pw-138256v9: 138256v9

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/index.html

[-- Attachment #2: Type: text/html, Size: 1980 bytes --]

✓ Xe.CI.FULL: success for Implement Wa_14021768792 to bypass m_n ratio limit (rev9)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 38663 bytes --]

== Series Details ==

Series: Implement Wa_14021768792 to bypass m_n ratio limit (rev9)
URL   : https://patchwork.freedesktop.org/series/138256/
State : success

== Summary ==

CI Bug Log - changes from xe-5759-bb38af66c2f21340a7c081afbb7ace249357fbb5_FULL -> xe-pw-138256v9_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-138256v9_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_async_flips@async-flip-with-page-flip-events-tiled-atomic:
    - shard-lnl:          [PASS][1] -> [DMESG-FAIL][2] ([Intel XE#1727]) +1 other test dmesg-fail
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5759-bb38af66c2f21340a7c081afbb7ace249357fbb5/shard-lnl-6/igt@kms_async_flips@async-flip-with-page-flip-events-tiled-atomic.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-2/igt@kms_async_flips@async-flip-with-page-flip-events-tiled-atomic.html

  * igt@kms_async_flips@async-flip-with-page-flip-events-tiled-atomic@pipe-a-edp-1-4:
    - shard-lnl:          [PASS][3] -> [DMESG-WARN][4] ([Intel XE#1727])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5759-bb38af66c2f21340a7c081afbb7ace249357fbb5/shard-lnl-6/igt@kms_async_flips@async-flip-with-page-flip-events-tiled-atomic@pipe-a-edp-1-4.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-2/igt@kms_async_flips@async-flip-with-page-flip-events-tiled-atomic@pipe-a-edp-1-4.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2327])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-10/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][6] ([Intel XE#7059] / [Intel XE#7085])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
    - shard-lnl:          NOTRUN -> [SKIP][7] ([Intel XE#1124]) +2 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#1124]) +2 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-target-2560x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#7679])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_bw@connected-linear-tiling-2-displays-target-2560x1440p.html

  * igt@kms_bw@linear-tiling-4-displays-target-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#367]) +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@kms_bw@linear-tiling-4-displays-target-3840x2160p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#2887]) +7 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][12] ([Intel XE#2887]) +4 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#3432])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_cdclk@plane-scaling:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#2724] / [Intel XE#7449])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_color@ctm-blue-to-red:
    - shard-lnl:          NOTRUN -> [SKIP][15] ([Intel XE#306] / [Intel XE#7358])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_chamelium_color@ctm-blue-to-red.html

  * igt@kms_chamelium_color@ctm-red-to-blue:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#2325] / [Intel XE#7358])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-10/igt@kms_chamelium_color@ctm-red-to-blue.html

  * igt@kms_chamelium_color_pipeline@plane-lut1d:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#7358]) +1 other test skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@kms_chamelium_color_pipeline@plane-lut1d.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2252]) +2 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-8/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_chamelium_hpd@dp-hpd-after-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][19] ([Intel XE#373]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html

  * igt@kms_content_protection@atomic-hdcp14:
    - shard-bmg:          NOTRUN -> [FAIL][20] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@kms_content_protection@atomic-hdcp14.html

  * igt@kms_content_protection@legacy-hdcp14:
    - shard-lnl:          NOTRUN -> [SKIP][21] ([Intel XE#7642]) +1 other test skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_content_protection@legacy-hdcp14.html

  * igt@kms_cursor_crc@cursor-onscreen-512x170:
    - shard-lnl:          NOTRUN -> [SKIP][22] ([Intel XE#2321] / [Intel XE#7355])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_cursor_crc@cursor-onscreen-512x170.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2321] / [Intel XE#7355])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-8/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
    - shard-lnl:          NOTRUN -> [SKIP][24] ([Intel XE#309] / [Intel XE#7343])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#1340] / [Intel XE#7435])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#4354] / [Intel XE#5882])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-8/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-lnl:          NOTRUN -> [SKIP][27] ([Intel XE#8265])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#8265])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_fbcon_fbt@psr:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#8680])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-2/igt@kms_fbcon_fbt@psr.html

  * igt@kms_feature_discovery@psr2:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#2374] / [Intel XE#6128])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-8/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop:
    - shard-lnl:          NOTRUN -> [SKIP][31] ([Intel XE#1421]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_flip@2x-flip-vs-dpms-on-nop.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [PASS][32] -> [FAIL][33] ([Intel XE#301]) +1 other test fail
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5759-bb38af66c2f21340a7c081afbb7ace249357fbb5/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          NOTRUN -> [FAIL][34] ([Intel XE#301]) +2 other tests fail
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#7178] / [Intel XE#7351]) +1 other test skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][36] ([Intel XE#1397] / [Intel XE#1745] / [Intel XE#7385] / [Intel XE#9144]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][37] ([Intel XE#1397] / [Intel XE#7385] / [Intel XE#9144]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#6312] / [Intel XE#651]) +1 other test skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#2311]) +21 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-10/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrshdr-argb161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#7061]) +3 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-8/igt@kms_frontbuffer_tracking@drrshdr-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrshdr-rgb101010-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][41] ([Intel XE#6312]) +3 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_frontbuffer_tracking@drrshdr-rgb101010-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][42] ([Intel XE#656] / [Intel XE#7905]) +12 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#4141]) +5 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-offscreen-pri-shrfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#7865]) +6 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_frontbuffer_tracking@fbchdr-1p-offscreen-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-shrfb-msflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][45] ([Intel XE#7905]) +12 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#2313]) +22 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#7061] / [Intel XE#7356]) +2 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@hdr-argb161616f-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][48] ([Intel XE#7061])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_frontbuffer_tracking@hdr-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@plane-fbc-rte:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#2350] / [Intel XE#7503])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@kms_frontbuffer_tracking@plane-fbc-rte.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#1503])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#6901])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier-source-clamping:
    - shard-lnl:          NOTRUN -> [SKIP][52] ([Intel XE#7283]) +1 other test skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier-source-clamping.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-a:
    - shard-lnl:          NOTRUN -> [SKIP][53] ([Intel XE#2763] / [Intel XE#6886]) +3 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-a.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#2499])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-2/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_psr2_sf@pr-cursor-plane-update-sf:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#2893] / [Intel XE#7304])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_psr2_sf@pr-cursor-plane-update-sf.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#1489]) +1 other test skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-2/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr@fbc-pr-primary-render:
    - shard-lnl:          NOTRUN -> [SKIP][57] ([Intel XE#1406])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_psr@fbc-pr-primary-render.html

  * igt@kms_psr@psr2-sprite-blt:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#2234] / [Intel XE#2850]) +6 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@kms_psr@psr2-sprite-blt.html

  * igt@kms_rotation_crc@bad-pixel-format:
    - shard-lnl:          NOTRUN -> [SKIP][59] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_rotation_crc@bad-pixel-format.html

  * igt@kms_rotation_crc@primary-rotation-270:
    - shard-bmg:          NOTRUN -> [SKIP][60] ([Intel XE#3904] / [Intel XE#7342]) +1 other test skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@kms_rotation_crc@primary-rotation-270.html

  * igt@kms_scaling_modes@scaling-mode-full-aspect:
    - shard-bmg:          NOTRUN -> [SKIP][61] ([Intel XE#2413])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-2/igt@kms_scaling_modes@scaling-mode-full-aspect.html

  * igt@kms_sharpness_filter@filter-strength:
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#6503])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@kms_sharpness_filter@filter-strength.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-lnl:          NOTRUN -> [SKIP][63] ([Intel XE#1499] / [Intel XE#9271])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@kms_vrr@seamless-rr-switch-vrr:
    - shard-bmg:          NOTRUN -> [SKIP][64] ([Intel XE#1499] / [Intel XE#9271])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-8/igt@kms_vrr@seamless-rr-switch-vrr.html

  * igt@xe_compute_preempt@compute-preempt-many-vram:
    - shard-lnl:          NOTRUN -> [SKIP][65] ([Intel XE#5191] / [Intel XE#7316] / [Intel XE#7346])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@xe_compute_preempt@compute-preempt-many-vram.html

  * igt@xe_evict@evict-large-external:
    - shard-lnl:          NOTRUN -> [SKIP][66] ([Intel XE#6540] / [Intel XE#688]) +1 other test skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@xe_evict@evict-large-external.html

  * igt@xe_exec_balancer@no-exec-cm-parallel-userptr-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][67] ([Intel XE#7482]) +4 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@xe_exec_balancer@no-exec-cm-parallel-userptr-rebind.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap:
    - shard-lnl:          NOTRUN -> [SKIP][68] ([Intel XE#1392]) +1 other test skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap.html

  * igt@xe_exec_basic@multigpu-no-exec-null:
    - shard-bmg:          NOTRUN -> [SKIP][69] ([Intel XE#2322] / [Intel XE#7372]) +1 other test skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@xe_exec_basic@multigpu-no-exec-null.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-imm:
    - shard-lnl:          NOTRUN -> [SKIP][70] ([Intel XE#8374]) +2 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-imm.html

  * igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate-race-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][71] ([Intel XE#8374]) +5 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate-race-prefetch.html

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-basic:
    - shard-bmg:          NOTRUN -> [SKIP][72] ([Intel XE#8364]) +14 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-basic.html

  * igt@xe_exec_multi_queue@one-queue-dyn-priority-smem:
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#8364]) +6 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@xe_exec_multi_queue@one-queue-dyn-priority-smem.html

  * igt@xe_exec_reset@cm-multi-queue-cat-error:
    - shard-bmg:          NOTRUN -> [SKIP][74] ([Intel XE#8369]) +1 other test skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-10/igt@xe_exec_reset@cm-multi-queue-cat-error.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#8378]) +3 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-mixed-userptr-rebind.html

  * igt@xe_exec_threads@threads-multi-queue-shared-vm-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][76] ([Intel XE#8378]) +1 other test skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@xe_exec_threads@threads-multi-queue-shared-vm-userptr-invalidate-race.html

  * igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit:
    - shard-bmg:          NOTRUN -> [SKIP][77] ([Intel XE#2229])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-8/igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit.html

  * igt@xe_mmap@small-bar:
    - shard-bmg:          NOTRUN -> [SKIP][78] ([Intel XE#586] / [Intel XE#7323] / [Intel XE#7384])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-10/igt@xe_mmap@small-bar.html

  * igt@xe_page_reclaim@binds-large-split:
    - shard-lnl:          NOTRUN -> [SKIP][79] ([Intel XE#7793])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@xe_page_reclaim@binds-large-split.html

  * igt@xe_page_reclaim@boundary-split:
    - shard-bmg:          NOTRUN -> [SKIP][80] ([Intel XE#7793])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@xe_page_reclaim@boundary-split.html

  * igt@xe_pat@xa-app-transient-media-on:
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#7590] / [Intel XE#7772])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@xe_pat@xa-app-transient-media-on.html

  * igt@xe_pm@d3cold-basic-exec:
    - shard-lnl:          NOTRUN -> [SKIP][82] ([Intel XE#2284] / [Intel XE#366] / [Intel XE#7370])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@xe_pm@d3cold-basic-exec.html

  * igt@xe_pm@s3-vm-bind-unbind-all:
    - shard-lnl:          NOTRUN -> [SKIP][83] ([Intel XE#584] / [Intel XE#7369]) +1 other test skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@xe_pm@s3-vm-bind-unbind-all.html

  * igt@xe_pmu@all-fn-engine-activity-load:
    - shard-bmg:          [PASS][84] -> [FAIL][85] ([Intel XE#7992])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5759-bb38af66c2f21340a7c081afbb7ace249357fbb5/shard-bmg-7/igt@xe_pmu@all-fn-engine-activity-load.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@xe_pmu@all-fn-engine-activity-load.html

  * igt@xe_prefetch_fault@prefetch-fault-svm:
    - shard-bmg:          NOTRUN -> [SKIP][86] ([Intel XE#7599])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-2/igt@xe_prefetch_fault@prefetch-fault-svm.html

  * igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq:
    - shard-bmg:          NOTRUN -> [SKIP][87] ([Intel XE#4733] / [Intel XE#7417]) +1 other test skip
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-10/igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq.html

  * igt@xe_query@multigpu-query-oa-units:
    - shard-bmg:          NOTRUN -> [SKIP][88] ([Intel XE#944])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@xe_query@multigpu-query-oa-units.html

  * igt@xe_query@multigpu-query-pxp-status:
    - shard-lnl:          NOTRUN -> [SKIP][89] ([Intel XE#944])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@xe_query@multigpu-query-pxp-status.html

  * igt@xe_sriov_flr@flr-twice:
    - shard-lnl:          NOTRUN -> [SKIP][90] ([Intel XE#4273])
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@xe_sriov_flr@flr-twice.html

  * igt@xe_survivability@i2c-functionality:
    - shard-bmg:          [PASS][91] -> [ABORT][92] ([Intel XE#8007]) +1 other test abort
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5759-bb38af66c2f21340a7c081afbb7ace249357fbb5/shard-bmg-4/igt@xe_survivability@i2c-functionality.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-7/igt@xe_survivability@i2c-functionality.html

  * igt@xe_vm@overcommit-nonfault-vram-lr-external-nodefer:
    - shard-lnl:          NOTRUN -> [SKIP][93] ([Intel XE#7892])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@xe_vm@overcommit-nonfault-vram-lr-external-nodefer.html

  
#### Possible fixes ####

  * igt@kms_flip@dpms-vs-vblank-race-interruptible@d-dp2:
    - shard-bmg:          [FAIL][94] ([Intel XE#3098]) -> [PASS][95] +1 other test pass
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5759-bb38af66c2f21340a7c081afbb7ace249357fbb5/shard-bmg-5/igt@kms_flip@dpms-vs-vblank-race-interruptible@d-dp2.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-9/igt@kms_flip@dpms-vs-vblank-race-interruptible@d-dp2.html

  * igt@xe_exec_threads@threads-hang-fd-userptr-invalidate-race:
    - shard-bmg:          [FAIL][96] ([Intel XE#9096]) -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5759-bb38af66c2f21340a7c081afbb7ace249357fbb5/shard-bmg-3/igt@xe_exec_threads@threads-hang-fd-userptr-invalidate-race.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-8/igt@xe_exec_threads@threads-hang-fd-userptr-invalidate-race.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv:
    - shard-bmg:          [ABORT][98] ([Intel XE#8007]) -> [PASS][99]
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5759-bb38af66c2f21340a7c081afbb7ace249357fbb5/shard-bmg-7/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-3/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html

  * igt@xe_pm@s3-multiple-execs:
    - shard-bmg:          [INCOMPLETE][100] ([Intel XE#8175]) -> [PASS][101]
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5759-bb38af66c2f21340a7c081afbb7ace249357fbb5/shard-bmg-6/igt@xe_pm@s3-multiple-execs.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-8/igt@xe_pm@s3-multiple-execs.html

  * igt@xe_vm@mmap-style-bind-userptr-either-side-full:
    - shard-bmg:          [ABORT][102] ([Intel XE#9281]) -> [PASS][103]
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5759-bb38af66c2f21340a7c081afbb7ace249357fbb5/shard-bmg-1/igt@xe_vm@mmap-style-bind-userptr-either-side-full.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-2/igt@xe_vm@mmap-style-bind-userptr-either-side-full.html

  
#### Warnings ####

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
    - shard-lnl:          [SKIP][104] ([Intel XE#309] / [Intel XE#7343] / [Intel XE#7935]) -> [SKIP][105] ([Intel XE#309] / [Intel XE#7343])
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5759-bb38af66c2f21340a7c081afbb7ace249357fbb5/shard-lnl-8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [FAIL][106] ([Intel XE#1729] / [Intel XE#7424]) -> [SKIP][107] ([Intel XE#2426] / [Intel XE#5848])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5759-bb38af66c2f21340a7c081afbb7ace249357fbb5/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][108] ([Intel XE#2426] / [Intel XE#5848]) -> [SKIP][109] ([Intel XE#2509] / [Intel XE#7437])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5759-bb38af66c2f21340a7c081afbb7ace249357fbb5/shard-bmg-9/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_exec_reset@gt-reset-fault-injection:
    - shard-lnl:          [DMESG-WARN][110] ([Intel XE#9130]) -> [ABORT][111] ([Intel XE#9145])
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5759-bb38af66c2f21340a7c081afbb7ace249357fbb5/shard-lnl-4/igt@xe_exec_reset@gt-reset-fault-injection.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/shard-lnl-7/igt@xe_exec_reset@gt-reset-fault-injection.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2350]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2350
  [Intel XE#2374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2374
  [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2499
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4273]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4273
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#5191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5191
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#586]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/586
  [Intel XE#5882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5882
  [Intel XE#6128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6128
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7316
  [Intel XE#7323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7323
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7346
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7369
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7384]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7384
  [Intel XE#7385]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7385
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7435
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7449]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7449
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7503
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7599
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#7772]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7772
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7892]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7892
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#7935]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7935
  [Intel XE#7992]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7992
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8175]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8175
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8680]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8680
  [Intel XE#9096]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9096
  [Intel XE#9130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9130
  [Intel XE#9144]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9144
  [Intel XE#9145]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9145
  [Intel XE#9271]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9271
  [Intel XE#9281]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9281
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-5759-bb38af66c2f21340a7c081afbb7ace249357fbb5 -> xe-pw-138256v9

  IGT_9099: 9099
  xe-5759-bb38af66c2f21340a7c081afbb7ace249357fbb5: bb38af66c2f21340a7c081afbb7ace249357fbb5
  xe-pw-138256v9: 138256v9

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v9/index.html

[-- Attachment #2: Type: text/html, Size: 43414 bytes --]

[PATCH v5 00/10] Implement Wa_14021768792 to bypass m_n ratio limit

[Suraj Kandpal]

For Platforms that support higher link rates, there is a limitation on
Link M /Link N ratio.
If the CEILING( Link M / Link N ) ratio is greater than 10.0, then
hardware cannot support the given resolution / refresh rate at the given
configuration.
For BMG Wa_14021768792 helps to bypass this limitation and allows it to
support the ratio till 15.0.

This series adds the missing restrictions for earlier platforms and adds
the Wa_14021768792 for BMG as per Bspec:49266

Ankit Nautiyal (8):
  drm/i915/display: Add helper to compute link M/N ratio for reuse
  drm/i915/dp_mst: Limit M/N ratio for MST
  drm/i915/dp: Add M/N ratio check for DP link config
  drm/i915/display: Add bits for link_n_extended for DISPLAY >= 14
  drm/i915/display_wa: Add support for Wa_14021768792
  drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10
  drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n
    ratio > 10
  drm/i915/dp: Extend intel_dp_can_support_m_n() for BMG M/N bypass

Suraj Kandpal (3):
  drm/i915/dp: Limit M/N ratio for DP
  drm/i915/display_wa: Add support for Wa_14014191401
  drm/i915/dp: Bump the max Link M/N ratio to 22 for DISPLAY_VER >= 35

 .../drm/i915/display/intel_crtc_state_dump.c  |   6 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 113 +++++++++++-
 drivers/gpu/drm/i915/display/intel_display.h  |   4 +
 .../gpu/drm/i915/display/intel_display_regs.h |  12 ++
 .../drm/i915/display/intel_display_types.h    |   2 +
 .../gpu/drm/i915/display/intel_display_wa.c   |  11 ++
 .../gpu/drm/i915/display/intel_display_wa.h   |   2 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 167 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   6 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   7 +
 10 files changed, 321 insertions(+), 9 deletions(-)

-- 
2.34.1

[PATCH v5 01/11] drm/i915/display: Add helper to compute link M/N ratio for reuse

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Introduce intel_display_compute_link_m_n() to compute the link M/N ratio
from the pixel clock and the link symbol clock. This logic was
previously embedded within intel_link_compute_m_n().
The new helper allows reuse of link M/N computation in other contexts
without requiring the full data M/N calculation and will be used in
later commits.

No functional changes intended.

v2:
- Rename function (Jani)
- The link symbol clock is passed in rather than derived here, so that the
DP specific conversion from the link rate stays with the caller. (Jani)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7602f633f49d..580c36a52921 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2650,13 +2650,20 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
 	intel_reduce_m_n_ratio(ret_m, ret_n);
 }
 
+static void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
+					   int pixel_clock, int link_symbol_clock)
+{
+	compute_m_n(link_m, link_n,
+		    pixel_clock, link_symbol_clock,
+		    0x80000);
+}
+
 void
 intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
 		       int pixel_clock, int link_clock,
 		       int bw_overhead,
 		       struct intel_link_m_n *m_n)
 {
-	u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock);
 	u32 data_m = intel_dp_effective_data_rate(pixel_clock, bits_per_pixel_x16,
 						  bw_overhead);
 	u32 data_n = drm_dp_max_dprx_data_rate(link_clock, nlanes);
@@ -2673,9 +2680,9 @@ intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
 		    data_m, data_n,
 		    0x8000000);
 
-	compute_m_n(&m_n->link_m, &m_n->link_n,
-		    pixel_clock, link_symbol_clock,
-		    0x80000);
+	intel_display_compute_link_m_n(&m_n->link_m, &m_n->link_n,
+				       pixel_clock,
+				       intel_dp_link_symbol_clock(link_clock));
 }
 
 void intel_panel_sanitize_ssc(struct intel_display *display)
-- 
2.34.1

[PATCH v5 02/11] drm/i915/dp: Limit M/N ratio for DP

[Suraj Kandpal]

The hardware cannot support DisplayPort configurations where the
ceiling of the Link M/Link N ratio exceeds the limit the transcoder's
timing generator DDA can track. This limitation has always existed, but
it typically wasn't encountered without the use of joiners and DSC.
With higher resolutions and combinations involving joiners and DSC,
this constraint can now be hit in certain scenarios.

Restrict the link configurations to those satisfying the constraint
while computing the link config limits, so that the SST and the MST
paths both get it, and so that a mode which no link rate can support
fails early rather than deep inside link config selection.

Also prune such modes in mode_valid. Note the ratio is the pixel clock
over the link symbol clock, and the symbol clock is not monotonic in the
link rate: it is the rate divided by 32 for 128b/132b but only by 10 for
8b/10b, so e.g. HBR3 has a higher symbol clock than UHBR20. There is
therefore no single best link rate to evaluate against, and mode_valid
walks the link configurations instead, only rejecting the mode if none
of them can satisfy the ratio.

For MSO, intel_dp_compute_config() divides adjusted_mode->crtc_clock by
the MSO link count before computing the link M/N. The limits and
mode_valid are evaluated before that, so divide the pixel clock by the
link count there as well, otherwise the check would be too strict by
that factor. The joiner needs no such handling, as
intel_joiner_adjust_timings() only rewrites the pipe mode and leaves the
adjusted mode the link M/N is derived from untouched.

Note: MST goes through intel_dp_compute_config_limits() as well, so its
compute config is already covered here. Only pruning the modes in the
MST mode_valid is left, which is added in a subsequent commit.

v2:
-Move the M/N ratio check to the link rate configuration phase instead
of during M/N computation. (Ville)
-Prune modes that cannot be supported even with highest link rate due to
M/N ratio restriction.
v3:
-Rebase on the link caps iterator based link config selection.
-Set the constraint up in intel_dp_compute_config_limits() by narrowing
the link config filter, and fail there if no config qualifies, instead
of skipping configs while iterating them. (Imre)
-Use a limit of 4 on DG2. (Wa_14014191401)
-Walk the link configurations in mode_valid rather than evaluating the
ratio at the highest link rate, which is not the best case for it.
v4:
-Add iterator for all dp configs in intel_dp_mode_valid_m_n() so
that we do not prune any mode that could have been supported (Sashiko)
v5:
-Drop "SST" from the subject and fix the note, MST compute is already
covered by the shared limits, only the MST mode_valid is left. (Mitul)
-Add the Bspec reference. (Mitul)
-Drop the link_n check, compute_m_n() fixes N at 0x80000 and only halves
it, so it cannot be 0. (Mitul)
-Fold in the MSO adjusted pixel clock from the M/N ratio check commit, so
this commit is correct on its own. (Mitul)
-Add intel_dp_link_m_n_ratio(), so that the M/N ratio check can share
it. (Mitul)

Bspec: 49266
Co-developed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |   4 +-
 drivers/gpu/drm/i915/display/intel_display.h |   2 +
 drivers/gpu/drm/i915/display/intel_dp.c      | 114 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h      |   2 +
 4 files changed, 120 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 580c36a52921..f74e7ddf0e41 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2650,8 +2650,8 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
 	intel_reduce_m_n_ratio(ret_m, ret_n);
 }
 
-static void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
-					   int pixel_clock, int link_symbol_clock)
+void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
+				    int pixel_clock, int link_symbol_clock)
 {
 	compute_m_n(link_m, link_n,
 		    pixel_clock, link_symbol_clock,
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index eecafff167d3..404168f4213b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -523,5 +523,7 @@ bool assert_port_valid(struct intel_display *display, enum port port);
 
 bool intel_scanout_needs_vtd_wa(struct intel_display *display);
 int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
+void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
+				    int pixel_clock, int link_symbol_clock);
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d8c0d9381471..7ceb7c02b597 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -63,6 +63,7 @@
 #include "intel_de.h"
 #include "intel_dip.h"
 #include "intel_dip_regs.h"
+#include "intel_display.h"
 #include "intel_display_driver.h"
 #include "intel_display_jiffies.h"
 #include "intel_display_utils.h"
@@ -1267,6 +1268,44 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
 	return true;
 }
 
+static int
+intel_dp_get_max_m_n_ratio(struct intel_display *display)
+{
+	if (display->platform.dg2)
+		return 4;
+
+	return 10;
+}
+
+static int intel_dp_link_m_n_ratio(u32 link_m, u32 link_n)
+{
+	return DIV_ROUND_UP(link_m, link_n);
+}
+
+static bool
+intel_dp_can_support_m_n(struct intel_display *display,
+			 int pixel_clock, int link_rate)
+{
+	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
+	u32 link_m, link_n;
+	int m_n_ratio;
+
+	intel_display_compute_link_m_n(&link_m, &link_n, pixel_clock,
+				       intel_dp_link_symbol_clock(link_rate));
+
+	m_n_ratio = intel_dp_link_m_n_ratio(link_m, link_n);
+
+	return m_n_ratio <= max_m_n_ratio;
+}
+
+static int intel_dp_mso_pixel_clock(struct intel_dp *intel_dp, int pixel_clock)
+{
+	if (!intel_dp->mso_link_count)
+		return pixel_clock;
+
+	return pixel_clock / intel_dp->mso_link_count;
+}
+
 static
 bool intel_dp_can_join(struct intel_dp *intel_dp,
 		       int num_joined_pipes)
@@ -1302,6 +1341,33 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
 	return target_clock <= effective_dotclk_limit;
 }
 
+bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	int m_n_pixel_clock = intel_dp_mso_pixel_clock(intel_dp, pixel_clock);
+	struct intel_dp_link_caps_order order = {
+		.key = INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE,
+		.dir = INTEL_DP_LINK_CAPS_ORDER_DIR_DESC,
+	};
+	struct intel_dp_link_config link_config;
+	struct intel_dp_link_caps_iter iter;
+	bool found = false;
+
+	intel_dp_link_caps_iter_start(&iter, intel_dp->link.caps, order,
+				      INTEL_DP_LINK_CAPS_FILTER_ALL);
+	for_each_dp_link_config(&iter, &link_config) {
+		if (intel_dp_can_support_m_n(display, m_n_pixel_clock,
+					     link_config.rate)) {
+			found = true;
+
+			break;
+		}
+	}
+	intel_dp_link_caps_iter_end(&iter);
+
+	return found;
+}
+
 static enum drm_mode_status
 intel_dp_mode_valid_format(struct intel_connector *connector,
 			   const struct drm_display_mode *mode,
@@ -1456,6 +1522,9 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 			return status;
 	}
 
+	if (!intel_dp_mode_valid_m_n(intel_dp, target_clock))
+		return MODE_CLOCK_HIGH;
+
 	/*
 	 * TODO: Even when using a 4:2:0 sink_format intel_dp_output_format()
 	 * will always choose a 4:4:4 output_format if the DFP can do the
@@ -2656,6 +2725,48 @@ intel_dp_dsc_compute_pipe_bpp_limits(struct intel_connector *connector,
 	return true;
 }
 
+static bool
+intel_dp_compute_m_n_ratio_limits(struct intel_dp *intel_dp,
+				  struct drm_connector_state *conn_state,
+				  const struct intel_crtc_state *crtc_state,
+				  struct link_config_limits *limits)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
+	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
+	struct intel_dp_link_caps_order order =
+		intel_dp_link_caps_connector_compute_order(connector);
+	struct intel_dp_link_caps_filter new_filter = INTEL_DP_LINK_CAPS_FILTER_NONE;
+	int pixel_clock = intel_dp_mso_pixel_clock(intel_dp,
+						  intel_dp_mode_clock(crtc_state, conn_state));
+	struct intel_dp_link_config link_config;
+	struct intel_dp_link_caps_iter iter;
+	bool found = false;
+
+	intel_dp_link_caps_iter_start(&iter, link_caps, order, limits->link_config_filter);
+	for_each_dp_link_config(&iter, &link_config) {
+		if (!intel_dp_can_support_m_n(display, pixel_clock, link_config.rate))
+			continue;
+
+		intel_dp_link_caps_filter_add(link_caps, &new_filter, &link_config);
+		found = true;
+	}
+	intel_dp_link_caps_iter_end(&iter);
+
+	if (!found) {
+		drm_dbg_kms(display->drm,
+			    "[CONNECTOR:%d:%s] No link config with a Link M/N ratio <= %d\n",
+			    connector->base.base.id, connector->base.name,
+			    intel_dp_get_max_m_n_ratio(display));
+
+		return false;
+	}
+
+	limits->link_config_filter = new_filter;
+
+	return true;
+}
+
 bool
 intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 			       struct drm_connector_state *conn_state,
@@ -2772,6 +2883,9 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 		limits->link_config_filter = new_filter;
 	}
 
+	if (!intel_dp_compute_m_n_ratio_limits(intel_dp, conn_state, crtc_state, limits))
+		return false;
+
 	if (!intel_dp_test_compute_config(connector, crtc_state, limits))
 		return false;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 04fae203bb69..aa58833a405b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -239,6 +239,8 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
 
 u8 intel_dp_as_sdp_transmission_time(void);
 
+bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock);
+
 int intel_dp_link_init(struct intel_dp *intel_dp);
 void intel_dp_link_cleanup(struct intel_dp *intel_dp);
 
-- 
2.34.1

[PATCH v5 03/11] drm/i915/display_wa: Add support for Wa_14014191401

[Suraj Kandpal]

The DG2 transcoder timing generator DDA only supports a Link M/N ratio
of up to 4. The Link M/N ratio limit uses a bare platform check for it.

Add Wa_14014191401 for DG2 and use it for the limit instead.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_wa.c | 2 ++
 drivers/gpu/drm/i915/display/intel_display_wa.h | 1 +
 drivers/gpu/drm/i915/display/intel_dp.c         | 3 ++-
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index 2e3ff4861ef4..91395076e903 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -94,6 +94,8 @@ bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa,
 			IS_DISPLAY_STEP(display, STEP_A0, STEP_A2);
 	case INTEL_DISPLAY_WA_14014143976:
 		return IS_DISPLAY_STEP(display, STEP_E0, STEP_FOREVER);
+	case INTEL_DISPLAY_WA_14014191401:
+		return display->platform.dg2;
 	case INTEL_DISPLAY_WA_14016740474:
 		return IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_C0);
 	case INTEL_DISPLAY_WA_14020863754:
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h
index b707147a7587..f41e58d1d6e7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.h
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
@@ -31,6 +31,7 @@ enum intel_display_wa {
 	INTEL_DISPLAY_WA_14011508470,
 	INTEL_DISPLAY_WA_14011765242,
 	INTEL_DISPLAY_WA_14014143976,
+	INTEL_DISPLAY_WA_14014191401,
 	INTEL_DISPLAY_WA_14016740474,
 	INTEL_DISPLAY_WA_14020863754,
 	INTEL_DISPLAY_WA_14025769978,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7ceb7c02b597..f3a79ae49b18 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -70,6 +70,7 @@
 #include "intel_display_regs.h"
 #include "intel_display_rpm.h"
 #include "intel_display_types.h"
+#include "intel_display_wa.h"
 #include "intel_dp.h"
 #include "intel_dp_aux.h"
 #include "intel_dp_hdcp.h"
@@ -1271,7 +1272,7 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
 static int
 intel_dp_get_max_m_n_ratio(struct intel_display *display)
 {
-	if (display->platform.dg2)
+	if (intel_display_wa(display, INTEL_DISPLAY_WA_14014191401))
 		return 4;
 
 	return 10;
-- 
2.34.1

[PATCH v5 04/11] drm/i915/dp_mst: Limit M/N ratio for MST

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

The hardware does not support DisplayPort configurations where the
ceiling of the Link M/Link N ratio exceeds the limit. Enforce this
constraint for MST as well.

The compute config path needs no change: MST goes through
intel_dp_compute_config_limits() too, so the link config filter set up
there already excludes the configurations violating the ratio limit, and
MST fails there if none is left.

What is still missing is pruning such modes, so add the check to
mst_connector_mode_valid_ctx(), reusing the helper the SST mode_valid
uses. It walks the link configurations and only rejects the mode if none
of them can satisfy the ratio, rather than evaluating it at a single
link rate.

v2:
-Drop the checks in the MST link config helpers, redundant now that the
constraint is applied while computing the link config limits. (Imre)
-Share the mode_valid helper with SST instead of evaluating the ratio at
one link rate, since the link symbol clock is not monotonic in the link
rate and there is no single best case configuration.
v3:
-Now that intel_dp_mode_valid_m_n checks for all configs just call
that (Sashiko)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 7023619aaaba..f00edfb66a10 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1565,6 +1565,11 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 					   min_link_bpp_x16,
 					   bw_overhead_flags);
 
+	if (!intel_dp_mode_valid_m_n(intel_dp, mode->clock)) {
+		*status = MODE_CLOCK_HIGH;
+		return 0;
+	}
+
 	/*
 	 * TODO:
 	 * - Also check if compression would allow for the mode
-- 
2.34.1

[PATCH v5 05/11] drm/i915/dp: Add M/N ratio check for DP link config

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Introduce intel_dp_check_m_n_ratio() to validate the computed link M/N
ratio against the maximum allowed value, and log it if the ratio exceeds
the limit.

The link config limits computed in the previous commits only restrict
the configurations that may be selected; this catches anything that
still slips through.

Log it rather than warn about it: the link config filter already
excludes the configurations violating the limit, so the only way to get
here is with link parameters forced through debugfs, which are applied
after that filter. A user triggerable drm_WARN() with its backtrace
would be out of proportion for that.

For MST the check goes after the bpp loop rather than inside it. The
link M/N is computed from the pixel clock and the link symbol clock, so
it does not depend on the bpp being tried and the result is the same on
every iteration.

v2:
-Use the platform specific ratio limit. (Wa_14014191401)
-Use the MSO adjusted pixel clock when predicting the ratio, matching
what the link M/N is actually computed from. (Imre)
-Drop the check from ilk_fdi_compute_config(): it was passing dp_m_n
rather than the fdi_m_n it had just computed, and an FDI link cannot get
anywhere near the ratio limit anyway.
v3:
-Check the ratio once after the MST bpp loop instead of on every
iteration, the result does not depend on the bpp. (Sashiko)
-Log instead of warning, since the link config filter already excludes
these configurations and only forced link parameters can reach it.
(Sashiko)
v4:
-Move the MSO adjusted pixel clock to the commit adding the prediction,
so that one is correct on its own. (Mitul)
-Reuse intel_dp_link_m_n_ratio() instead of open coding the ratio.
(Mitul)
-Drop the m_n and link_n checks, neither can be NULL or 0. Make the
parameters const and move it next to intel_dp_can_support_m_n().
(Mitul)
-Drop the check on dp_m2_n2, the dp_m_n one already covers it. (Mitul)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c     | 17 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h     |  4 ++++
 drivers/gpu/drm/i915/display/intel_dp_mst.c |  2 ++
 3 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f3a79ae49b18..8ef6b4c4fc8e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1299,6 +1299,21 @@ intel_dp_can_support_m_n(struct intel_display *display,
 	return m_n_ratio <= max_m_n_ratio;
 }
 
+void intel_dp_check_m_n_ratio(const struct intel_crtc_state *crtc_state,
+			      const struct intel_link_m_n *m_n)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
+	int m_n_ratio;
+
+	m_n_ratio = intel_dp_link_m_n_ratio(m_n->link_m, m_n->link_n);
+
+	if (m_n_ratio > max_m_n_ratio)
+		drm_dbg_kms(display->drm,
+			    "Link M/N ratio (%d) exceeds max allowed (%d)\n",
+			    m_n_ratio, max_m_n_ratio);
+}
+
 static int intel_dp_mso_pixel_clock(struct intel_dp *intel_dp, int pixel_clock)
 {
 	if (!intel_dp->mso_link_count)
@@ -3755,6 +3770,8 @@ intel_dp_compute_config(struct intel_atomic_state *state,
 				       pipe_config->port_clock,
 				       intel_dp_bw_fec_overhead(pipe_config->fec_enable),
 				       &pipe_config->dp_m_n);
+
+		intel_dp_check_m_n_ratio(pipe_config, &pipe_config->dp_m_n);
 	}
 
 	ret = intel_dp_compute_min_hblank(pipe_config, conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index aa58833a405b..1e3da678c9b6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -26,6 +26,7 @@ struct intel_display;
 struct intel_dp;
 struct intel_dp_link_config;
 struct intel_encoder;
+struct intel_link_m_n;
 
 struct link_config_limits {
 	struct intel_dp_link_caps_filter link_config_filter;
@@ -244,4 +245,7 @@ bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock);
 int intel_dp_link_init(struct intel_dp *intel_dp);
 void intel_dp_link_cleanup(struct intel_dp *intel_dp);
 
+void intel_dp_check_m_n_ratio(const struct intel_crtc_state *crtc_state,
+			      const struct intel_link_m_n *m_n);
+
 #endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index f00edfb66a10..8db84975f36b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -429,6 +429,8 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
 		return slots;
 	}
 
+	intel_dp_check_m_n_ratio(crtc_state, &crtc_state->dp_m_n);
+
 	if (!dsc)
 		crtc_state->pipe_bpp = fxp_q4_to_int(bpp_x16);
 	else
-- 
2.34.1

[PATCH v5 06/11] drm/i915/display: Add bits for link_n_extended for DISPLAY >= 14

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

LINK_N register has bits 31:24 for extended link N value used for
HDMI2.1 and for an alternate mode of operation of DP TG DDA.

Add support for these extra bits.

For displays with version 14 or higher, PIPE_LINK_N1_EXTENDED_MASK
(bits 31:24) is used to handle the extended link N bits. For older
platforms, DATA_LINK_M_N_MASK (bits 23:0) is used to handle the
standard link N bits. This distinction ensures clarity and maintains
the semantics for platforms that support the extended bits. In
subsequent changes the logic is updated to conditionally apply the
extended link N bits.

v2: Drop extra link_n_ext member. (Jani)
v3: Avoid link_n_ext in set_m_n helper. (Jani)
v4: Rebase, and update commit message.
v5: Drop a stale changelog entry, the DISPLAY_VER split here is
    intentional. (Sashiko)

Bspec: 50488
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c   | 18 ++++++++++++++++--
 .../gpu/drm/i915/display/intel_display_regs.h  |  2 ++
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f74e7ddf0e41..461b81bf8341 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2720,14 +2720,22 @@ void intel_set_m_n(struct intel_display *display,
 		   intel_reg_t data_m_reg, intel_reg_t data_n_reg,
 		   intel_reg_t link_m_reg, intel_reg_t link_n_reg)
 {
+	u32 link_n = m_n->link_n;
+
 	intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
 	intel_de_write(display, data_n_reg, m_n->data_n);
 	intel_de_write(display, link_m_reg, m_n->link_m);
+
+	if (DISPLAY_VER(display) >= 14)
+		link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
+	else
+		link_n &= DATA_LINK_M_N_MASK;
+
 	/*
 	 * On BDW+ writing LINK_N arms the double buffered update
 	 * of all the M/N registers, so it must be written last.
 	 */
-	intel_de_write(display, link_n_reg, m_n->link_n);
+	intel_de_write(display, link_n_reg, link_n);
 }
 
 bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
@@ -3484,7 +3492,13 @@ void intel_get_m_n(struct intel_display *display,
 		   intel_reg_t link_m_reg, intel_reg_t link_n_reg)
 {
 	m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK;
-	m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK;
+	m_n->link_n = intel_de_read(display, link_n_reg);
+
+	if (DISPLAY_VER(display) >= 14)
+		m_n->link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
+	else
+		m_n->link_n &= DATA_LINK_M_N_MASK;
+
 	m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK;
 	m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK;
 	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 2f509bd06557..983a0d9dcb9c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1190,6 +1190,8 @@
 
 #define _PIPEA_LINK_N1		0x60044
 #define _PIPEB_LINK_N1		0x61044
+#define  PIPE_LINK_N1_EXTENDED_MASK	REG_GENMASK(31, 24)
+#define  PIPE_LINK_N1_EXTENDED(val)	REG_FIELD_PREP(PIPE_LINK_N1_EXTENDED_MASK, (val))
 #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
 
 #define _PIPEA_LINK_M2		0x60048
-- 
2.34.1

[PATCH v5 07/11] drm/i915/display_wa: Add support for Wa_14021768792

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Some BMG ultrajoiner configurations require support for Link M/N ratios
between 10.0 and 15.0. This range is not natively supported and requires
a workaround.

Wa_14021768792 enables this support by utilizing HDMI_EMP_DATA,
CHICKEN_TRANS and the extended bits in the LINK_N register.

Add the necessary logic to enable the workaround on applicable platforms.
The underlying mechanism comes from the display C0,
so it is gated on display stepping C0 and later.

v2:
-Don't include i915_drv.h and don't use struct drm_i915_private under
display/. Use display->platform.battlemage, which names the affected
platform directly, instead of IS_DGFX() combined with a display version
check. (Jani)
-Rebase on the reworked display WA framework, where the condition goes
directly into the __intel_display_wa() switch.

Bspec: 49266
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_wa.c | 9 +++++++++
 drivers/gpu/drm/i915/display/intel_display_wa.h | 1 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index 91395076e903..e6f84dffdeb7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -102,6 +102,15 @@ bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa,
 		return DISPLAY_VERx100(display) == 3000 ||
 			DISPLAY_VERx100(display) == 2000 ||
 			DISPLAY_VERx100(display) == 1401;
+	/*
+	 * Wa_14021768792:
+	 * Fixes: Limitation of Link M/N ratio > 10 for specific Xe2HPD platforms.
+	 * Workaround: Use HDMI_EMP_DATA, CHICKEN_BITs and extended bits in LINK_N
+	 * registers to support LINK M/N ratios from > 10 but < 15.
+	 */
+	case INTEL_DISPLAY_WA_14021768792:
+		return display->platform.battlemage &&
+			IS_DISPLAY_STEP(display, STEP_C0, STEP_FOREVER);
 	case INTEL_DISPLAY_WA_14025769978:
 		return DISPLAY_VER(display) == 35;
 	case INTEL_DISPLAY_WA_14026643300:
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h
index f41e58d1d6e7..0b43c2144dcc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.h
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
@@ -34,6 +34,7 @@ enum intel_display_wa {
 	INTEL_DISPLAY_WA_14014191401,
 	INTEL_DISPLAY_WA_14016740474,
 	INTEL_DISPLAY_WA_14020863754,
+	INTEL_DISPLAY_WA_14021768792,
 	INTEL_DISPLAY_WA_14025769978,
 	INTEL_DISPLAY_WA_14026643300,
 	INTEL_DISPLAY_WA_15013987218,
-- 
2.34.1

[PATCH v5 08/11] drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

To support a Link M/N ratio between 10.0 and 15.0, for some BMG
ultrajoiner cases we need Wa_14021768792.

To bypass the hardware limitation within the Timing Generator DDA
(TGDDA), we need to program the LINKM and LINKN registers as defined in
the WA. Along with this we also need the relevant bits in HDMI_EMP_DATA
and CHICKEN_TRANS.

Add the bits for the WA and a new member 'bypass_m_n_ratio_limit' to
track if we need to bypass the Link M/N ratio limit in the
intel_link_m_n structure.

Per Bspec the extended LINK_N field is two nibbles: bits 27:24 hold
INT(Link M / Link N) and bits 31:28 hold CEIL(Link M / Link N).

The workaround is limited to transcoder A. Check the transcoder rather
than the pipe: for a single pipe the two are the same, but the joiner
secondaries read the M/N back through the primary's transcoder, so a
pipe check would have them report the workaround as not applied while
their state, copied from the primary, has it applied.

CHICKEN_TRANS and HDMI_EMP_DATA are programmed before LINK_N, since
writing LINK_N arms the double buffered update of the M/N registers, and
all of the programming has to be done before the transcoder is enabled.
Both are also explicitly cleared when the mechanism is not in use, so
that state cannot leak from a previous modeset.

Only bypass_m_n_ratio_limit is compared by the state checker, not the
ratio integer and fraction themselves. That is deliberate: both are
derived from Link M and Link N, which are compared already, so the thing
worth verifying is whether the workaround ended up being applied or not.

Unlike the rest of the M/N registers, CHICKEN_TRANS and HDMI_EMP_DATA
are not double buffered, so the flag has to be compared outside the
fastset exemption that PIPE_CONF_CHECK_M_N() has for update_m_n.
Otherwise a seamless M/N update could switch the DDA out of the
workaround on a live transcoder, with the Link M/N values only following
at the next MSA.

v2:
-Drop the drm_WARN_ON() on the extended LINK_N field in intel_get_m_n():
it is derived from Link M and Link N, so the state checker comparison of
those and of bypass_m_n_ratio_limit already covers it. (Sashiko)
-Compare bypass_m_n_ratio_limit unconditionally, so that a change to it
forces a full modeset instead of being applied during a seamless M/N
fastset. (Sashiko)
v3:
-Check for transcoder A instead of pipe A, so that the joiner secondaries
read the flag back the same as the primary. (Mitul)
-Drop bypass_m_n_ratio_limit from intel_compare_link_m_n(), the
unconditional PIPE_CONF_CHECK_BOOL() already compares it. (Mitul)
-Print bypass_m_n_ratio_limit in the crtc state dump. (Mitul)

Bspec: 49266
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 .../drm/i915/display/intel_crtc_state_dump.c  |  6 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 82 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_display.h  |  2 +
 .../gpu/drm/i915/display/intel_display_regs.h | 10 +++
 .../drm/i915/display/intel_display_types.h    |  2 +
 5 files changed, 99 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 92675a88b969..c51b21222dc6 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -36,10 +36,12 @@ intel_dump_m_n_config(struct drm_printer *p,
 		      const char *id, unsigned int lane_count,
 		      const struct intel_link_m_n *m_n)
 {
-	drm_printf(p, "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n",
+	drm_printf(p,
+		   "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u, bypass_m_n_ratio_limit: %s\n",
 		   id, lane_count,
 		   m_n->data_m, m_n->data_n,
-		   m_n->link_m, m_n->link_n, m_n->tu);
+		   m_n->link_m, m_n->link_n, m_n->tu,
+		   str_yes_no(m_n->bypass_m_n_ratio_limit));
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 461b81bf8341..ecc0e5ec181a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2715,6 +2715,15 @@ void intel_zero_m_n(struct intel_link_m_n *m_n)
 	m_n->tu = 1;
 }
 
+static u8 bmg_get_link_n_ext(const struct intel_link_m_n *m_n)
+{
+	if (!m_n->link_n)
+		return 0;
+
+	return PIPE_LINK_N1_EXT_INT(m_n->link_m / m_n->link_n) |
+		PIPE_LINK_N1_EXT_CEIL(DIV_ROUND_UP(m_n->link_m, m_n->link_n));
+}
+
 void intel_set_m_n(struct intel_display *display,
 		   const struct intel_link_m_n *m_n,
 		   intel_reg_t data_m_reg, intel_reg_t data_n_reg,
@@ -2726,7 +2735,9 @@ void intel_set_m_n(struct intel_display *display,
 	intel_de_write(display, data_n_reg, m_n->data_n);
 	intel_de_write(display, link_m_reg, m_n->link_m);
 
-	if (DISPLAY_VER(display) >= 14)
+	if (DISPLAY_VER(display) >= 14 && m_n->bypass_m_n_ratio_limit)
+		link_n |= PIPE_LINK_N1_EXTENDED(bmg_get_link_n_ext(m_n));
+	else if (DISPLAY_VER(display) >= 14)
 		link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
 	else
 		link_n &= DATA_LINK_M_N_MASK;
@@ -2747,6 +2758,26 @@ bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
 	return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview;
 }
 
+static void bmg_enhanced_tgdda_write(struct intel_crtc *crtc,
+				     enum transcoder transcoder,
+				     const struct intel_link_m_n *m_n)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	bool enable = m_n->bypass_m_n_ratio_limit && m_n->link_n;
+	u32 link_m_frac = enable ? m_n->link_m % m_n->link_n : 0;
+
+	if (!intel_display_wa(display, INTEL_DISPLAY_WA_14021768792))
+		return;
+
+	intel_de_rmw(display, HDMI_EMP_DATA(display, transcoder),
+		     HDMI_EMP_DATA_LINK_M_FRAC_MASK,
+		     REG_FIELD_PREP(HDMI_EMP_DATA_LINK_M_FRAC_MASK, link_m_frac));
+
+	intel_de_rmw(display, CHICKEN_TRANS(display, transcoder),
+		     DP_ENHANCED_TGDDA_ENABLE,
+		     enable ? DP_ENHANCED_TGDDA_ENABLE : 0);
+}
+
 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
 				    enum transcoder transcoder,
 				    const struct intel_link_m_n *m_n)
@@ -2754,6 +2785,8 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
 	struct intel_display *display = to_intel_display(crtc);
 	enum pipe pipe = crtc->pipe;
 
+	bmg_enhanced_tgdda_write(crtc, transcoder, m_n);
+
 	if (DISPLAY_VER(display) >= 5)
 		intel_set_m_n(display, m_n,
 			      PIPE_DATA_M1(display, transcoder),
@@ -3504,6 +3537,49 @@ void intel_get_m_n(struct intel_display *display,
 	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;
 }
 
+bool intel_display_can_bypass_m_n_limit(struct intel_display *display,
+					int m_n_ratio,
+					enum transcoder transcoder)
+{
+	if (!intel_display_wa(display, INTEL_DISPLAY_WA_14021768792))
+		return false;
+
+	if (m_n_ratio > 15)
+		return false;
+
+	if (transcoder != TRANSCODER_A)
+		return false;
+
+	return true;
+}
+
+static void bmg_enhanced_tgdda_read(struct intel_crtc *crtc,
+				    enum transcoder transcoder,
+				    struct intel_link_m_n *m_n)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	u32 link_m_frac;
+	int m_n_ratio;
+
+	if (!m_n->link_n)
+		return;
+
+	m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
+
+	if (!intel_display_can_bypass_m_n_limit(display, m_n_ratio, transcoder))
+		return;
+
+	if (!(intel_de_read(display, CHICKEN_TRANS(display, transcoder)) &
+	      DP_ENHANCED_TGDDA_ENABLE))
+		return;
+
+	link_m_frac = REG_FIELD_GET(HDMI_EMP_DATA_LINK_M_FRAC_MASK,
+				    intel_de_read(display, HDMI_EMP_DATA(display, transcoder)));
+
+	if (link_m_frac == m_n->link_m % m_n->link_n)
+		m_n->bypass_m_n_ratio_limit = true;
+}
+
 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
 				    enum transcoder transcoder,
 				    struct intel_link_m_n *m_n)
@@ -3521,6 +3597,8 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
 		intel_get_m_n(display, m_n,
 			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
 			      PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
+
+	bmg_enhanced_tgdda_read(crtc, transcoder, m_n);
 }
 
 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
@@ -5445,6 +5523,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_M_N(dp_m2_n2);
 	}
 
+	PIPE_CONF_CHECK_BOOL(dp_m_n.bypass_m_n_ratio_limit);
+
 	PIPE_CONF_CHECK_X(output_types);
 
 	PIPE_CONF_CHECK_I(framestart_delay);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 404168f4213b..d53b7b4a80e7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -525,5 +525,7 @@ bool intel_scanout_needs_vtd_wa(struct intel_display *display);
 int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
 void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
 				    int pixel_clock, int link_symbol_clock);
+bool intel_display_can_bypass_m_n_limit(struct intel_display *display,
+					int m_n_ratio, enum transcoder transcoder);
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 983a0d9dcb9c..bbdbc27629d7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -550,6 +550,11 @@
 #define _TRANS_MULT_B		0x6102c
 #define TRANS_MULT(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
 
+#define _HDMI_EMP_DATA_A	0x600d8
+#define _HDMI_EMP_DATA_B	0x610d8
+#define  HDMI_EMP_DATA_LINK_M_FRAC_MASK	REG_GENMASK(23, 0)
+#define HDMI_EMP_DATA(display, trans)	_MMIO_TRANS2((display), (trans), _HDMI_EMP_DATA_A)
+
 /* Hotplug control (945+ only) */
 #define PORT_HOTPLUG_EN(dev_priv)		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
 #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
@@ -1192,6 +1197,10 @@
 #define _PIPEB_LINK_N1		0x61044
 #define  PIPE_LINK_N1_EXTENDED_MASK	REG_GENMASK(31, 24)
 #define  PIPE_LINK_N1_EXTENDED(val)	REG_FIELD_PREP(PIPE_LINK_N1_EXTENDED_MASK, (val))
+#define  PIPE_LINK_N1_EXT_CEIL_MASK	REG_GENMASK(7, 4)
+#define  PIPE_LINK_N1_EXT_CEIL(val)	REG_FIELD_PREP(PIPE_LINK_N1_EXT_CEIL_MASK, (val))
+#define  PIPE_LINK_N1_EXT_INT_MASK	REG_GENMASK(3, 0)
+#define  PIPE_LINK_N1_EXT_INT(val)	REG_FIELD_PREP(PIPE_LINK_N1_EXT_INT_MASK, (val))
 #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
 
 #define _PIPEA_LINK_M2		0x60048
@@ -1710,6 +1719,7 @@
 #define   PSR2_ADD_VERTICAL_LINE_COUNT	REG_BIT(15)
 #define   DP_FEC_BS_JITTER_WA		REG_BIT(15)
 #define   PSR2_VSC_ENABLE_PROG_HEADER	REG_BIT(12)
+#define   DP_ENHANCED_TGDDA_ENABLE	REG_BIT(11)
 #define   DP_DSC_INSERT_SF_AT_EOL_WA	REG_BIT(4)
 #define   HDCP_LINE_REKEY_DISABLE	REG_BIT(0)
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8f9fb2603638..d0748837ce97 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -985,6 +985,8 @@ struct intel_link_m_n {
 	u32 data_n;
 	u32 link_m;
 	u32 link_n;
+	/* Wa_14021768792 for linkm/n ratio > 10 */
+	bool bypass_m_n_ratio_limit;
 };
 
 struct intel_csc_matrix {
-- 
2.34.1

[PATCH v5 09/11] drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n ratio > 10

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Handle the bypass logic for the M/N ratio limit for DP.
Calculate the M/N ratio, check if it can bypass the limit, and set the
appropriate flags for the workaround.

v2:
-Restrict the workaround to 128b/132b links.
-Clear bypass_m_n_ratio_limit on entry, so a rejected link rate cannot
leave it set for the rate that gets used. (Sashiko)
v3:
-Rebase on the reworked M/N ratio check, which no longer checks m_n and
link_n. m_n is no longer const, as the flag is set through it. (Mitul)
-Pass the cpu transcoder to intel_display_can_bypass_m_n_limit() instead
of the pipe. (Mitul)

Bspec: 49266
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 28 ++++++++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_dp.h |  2 +-
 2 files changed, 24 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8ef6b4c4fc8e..8e6ba5b9fde6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1300,18 +1300,32 @@ intel_dp_can_support_m_n(struct intel_display *display,
 }
 
 void intel_dp_check_m_n_ratio(const struct intel_crtc_state *crtc_state,
-			      const struct intel_link_m_n *m_n)
+			      struct intel_link_m_n *m_n)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
 	int m_n_ratio;
 
+	m_n->bypass_m_n_ratio_limit = false;
+
 	m_n_ratio = intel_dp_link_m_n_ratio(m_n->link_m, m_n->link_n);
 
-	if (m_n_ratio > max_m_n_ratio)
+	if (m_n_ratio <= max_m_n_ratio)
+		return;
+
+	if (intel_dp_is_uhbr(crtc_state) &&
+	    intel_display_can_bypass_m_n_limit(display, m_n_ratio,
+					       crtc_state->cpu_transcoder)) {
+		m_n->bypass_m_n_ratio_limit = true;
 		drm_dbg_kms(display->drm,
-			    "Link M/N ratio (%d) exceeds max allowed (%d)\n",
-			    m_n_ratio, max_m_n_ratio);
+			    "Bypassing Link_m/Link_n ratio limit (ratio %d)\n",
+			    m_n_ratio);
+		return;
+	}
+
+	drm_dbg_kms(display->drm,
+		    "Link M/N ratio (%d) exceeds max allowed (%d)\n",
+		    m_n_ratio, max_m_n_ratio);
 }
 
 static int intel_dp_mso_pixel_clock(struct intel_dp *intel_dp, int pixel_clock)
@@ -3393,6 +3407,9 @@ static bool can_enable_drrs(struct intel_connector *connector,
 	if (pipe_config->vrr.enable)
 		return false;
 
+	if (pipe_config->dp_m_n.bypass_m_n_ratio_limit)
+		return false;
+
 	/*
 	 * DRRS and PSR can't be enable together, so giving preference to PSR
 	 * as it allows more power-savings by complete shutting down display,
@@ -3427,7 +3444,8 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
 	 * FIXME all joined pipes share the same transcoder.
 	 * Need to account for that when updating M/N live.
 	 */
-	if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes)
+	if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes &&
+	    !pipe_config->dp_m_n.bypass_m_n_ratio_limit)
 		pipe_config->update_m_n = true;
 
 	if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 1e3da678c9b6..c834d90a1f81 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -246,6 +246,6 @@ int intel_dp_link_init(struct intel_dp *intel_dp);
 void intel_dp_link_cleanup(struct intel_dp *intel_dp);
 
 void intel_dp_check_m_n_ratio(const struct intel_crtc_state *crtc_state,
-			      const struct intel_link_m_n *m_n);
+			      struct intel_link_m_n *m_n);
 
 #endif /* __INTEL_DP_H__ */
-- 
2.34.1

[PATCH v5 10/11] drm/i915/dp: Extend intel_dp_can_support_m_n() for BMG M/N bypass

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

On BMG platforms, the standard M/N ratio limit of 10 can be bypassed
under specific conditions, as permitted by hardware capabilities.

Modify the helper intel_dp_can_support_m_n() to account for this by
checking whether the platform supports bypassing the limit. The
workaround is only intended for 128b/132b links, so restrict it to
those.

During the mode_valid phase, the check assumes that TRANSCODER_A will be
used, to allow the mode where the M/N ratio is within the limits for the
workaround.

v2:
-Keep the helper static: the MST mode_valid now goes through the shared
intel_dp_mode_valid_m_n() rather than calling it directly, so it no
longer needs to be exported.
v3:
-Use the cpu transcoder instead of the pipe, following the change to
intel_display_can_bypass_m_n_limit(). (Mitul)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8e6ba5b9fde6..045524994d85 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1285,9 +1285,11 @@ static int intel_dp_link_m_n_ratio(u32 link_m, u32 link_n)
 
 static bool
 intel_dp_can_support_m_n(struct intel_display *display,
+			 const struct intel_crtc_state *crtc_state,
 			 int pixel_clock, int link_rate)
 {
 	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
+	enum transcoder cpu_transcoder = TRANSCODER_A;
 	u32 link_m, link_n;
 	int m_n_ratio;
 
@@ -1296,7 +1298,16 @@ intel_dp_can_support_m_n(struct intel_display *display,
 
 	m_n_ratio = intel_dp_link_m_n_ratio(link_m, link_n);
 
-	return m_n_ratio <= max_m_n_ratio;
+	if (m_n_ratio <= max_m_n_ratio)
+		return true;
+
+	if (!drm_dp_is_uhbr_rate(link_rate))
+		return false;
+
+	if (crtc_state)
+		cpu_transcoder = crtc_state->cpu_transcoder;
+
+	return intel_display_can_bypass_m_n_limit(display, m_n_ratio, cpu_transcoder);
 }
 
 void intel_dp_check_m_n_ratio(const struct intel_crtc_state *crtc_state,
@@ -1386,7 +1397,7 @@ bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock)
 	intel_dp_link_caps_iter_start(&iter, intel_dp->link.caps, order,
 				      INTEL_DP_LINK_CAPS_FILTER_ALL);
 	for_each_dp_link_config(&iter, &link_config) {
-		if (intel_dp_can_support_m_n(display, m_n_pixel_clock,
+		if (intel_dp_can_support_m_n(display, NULL, m_n_pixel_clock,
 					     link_config.rate)) {
 			found = true;
 
@@ -2775,7 +2786,8 @@ intel_dp_compute_m_n_ratio_limits(struct intel_dp *intel_dp,
 
 	intel_dp_link_caps_iter_start(&iter, link_caps, order, limits->link_config_filter);
 	for_each_dp_link_config(&iter, &link_config) {
-		if (!intel_dp_can_support_m_n(display, pixel_clock, link_config.rate))
+		if (!intel_dp_can_support_m_n(display, crtc_state, pixel_clock,
+					      link_config.rate))
 			continue;
 
 		intel_dp_link_caps_filter_add(link_caps, &new_filter, &link_config);
-- 
2.34.1

[PATCH v5 11/11] drm/i915/dp: Bump the max Link M/N ratio to 22 for DISPLAY_VER >= 35

[Suraj Kandpal]

Starting Xe3p max M/N ratio has been increased to 22.

Bspec: 68922
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 045524994d85..5864e33456a7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1272,6 +1272,9 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
 static int
 intel_dp_get_max_m_n_ratio(struct intel_display *display)
 {
+	if (DISPLAY_VER(display) >= 35)
+		return 22;
+
 	if (intel_display_wa(display, INTEL_DISPLAY_WA_14014191401))
 		return 4;
 
-- 
2.34.1

[PATCH v5 00/11] Implement Wa_14021768792 to bypass m_n ratio limit

[Suraj Kandpal]

For Platforms that support higher link rates, there is a limitation on
Link M /Link N ratio.
If the CEILING( Link M / Link N ) ratio is greater than 10.0, then
hardware cannot support the given resolution / refresh rate at the given
configuration.
For BMG Wa_14021768792 helps to bypass this limitation and allows it to
support the ratio till 15.0.

This series adds the missing restrictions for earlier platforms and adds
the Wa_14021768792 for BMG as per Bspec:49266

Ankit Nautiyal (8):
  drm/i915/display: Add helper to compute link M/N ratio for reuse
  drm/i915/dp_mst: Limit M/N ratio for MST
  drm/i915/dp: Add M/N ratio check for DP link config
  drm/i915/display: Add bits for link_n_extended for DISPLAY >= 14
  drm/i915/display_wa: Add support for Wa_14021768792
  drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10
  drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n
    ratio > 10
  drm/i915/dp: Extend intel_dp_can_support_m_n() for BMG M/N bypass

Suraj Kandpal (3):
  drm/i915/dp: Limit M/N ratio for DP
  drm/i915/display_wa: Add support for Wa_14014191401
  drm/i915/dp: Bump the max Link M/N ratio to 22 for DISPLAY_VER >= 35

 .../drm/i915/display/intel_crtc_state_dump.c  |   6 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 113 +++++++++++-
 drivers/gpu/drm/i915/display/intel_display.h  |   4 +
 .../gpu/drm/i915/display/intel_display_regs.h |  12 ++
 .../drm/i915/display/intel_display_types.h    |   2 +
 .../gpu/drm/i915/display/intel_display_wa.c   |  11 ++
 .../gpu/drm/i915/display/intel_display_wa.h   |   2 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 167 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   6 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   7 +
 10 files changed, 321 insertions(+), 9 deletions(-)

-- 
2.34.1

[PATCH v5 01/11] drm/i915/display: Add helper to compute link M/N ratio for reuse

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Introduce intel_display_compute_link_m_n() to compute the link M/N ratio
from the pixel clock and the link symbol clock. This logic was
previously embedded within intel_link_compute_m_n().
The new helper allows reuse of link M/N computation in other contexts
without requiring the full data M/N calculation and will be used in
later commits.

No functional changes intended.

v2:
- Rename function (Jani)
- The link symbol clock is passed in rather than derived here, so that the
DP specific conversion from the link rate stays with the caller. (Jani)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7602f633f49d..580c36a52921 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2650,13 +2650,20 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
 	intel_reduce_m_n_ratio(ret_m, ret_n);
 }
 
+static void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
+					   int pixel_clock, int link_symbol_clock)
+{
+	compute_m_n(link_m, link_n,
+		    pixel_clock, link_symbol_clock,
+		    0x80000);
+}
+
 void
 intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
 		       int pixel_clock, int link_clock,
 		       int bw_overhead,
 		       struct intel_link_m_n *m_n)
 {
-	u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock);
 	u32 data_m = intel_dp_effective_data_rate(pixel_clock, bits_per_pixel_x16,
 						  bw_overhead);
 	u32 data_n = drm_dp_max_dprx_data_rate(link_clock, nlanes);
@@ -2673,9 +2680,9 @@ intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
 		    data_m, data_n,
 		    0x8000000);
 
-	compute_m_n(&m_n->link_m, &m_n->link_n,
-		    pixel_clock, link_symbol_clock,
-		    0x80000);
+	intel_display_compute_link_m_n(&m_n->link_m, &m_n->link_n,
+				       pixel_clock,
+				       intel_dp_link_symbol_clock(link_clock));
 }
 
 void intel_panel_sanitize_ssc(struct intel_display *display)
-- 
2.34.1

[PATCH v5 02/11] drm/i915/dp: Limit M/N ratio for DP

[Suraj Kandpal]

The hardware cannot support DisplayPort configurations where the
ceiling of the Link M/Link N ratio exceeds the limit the transcoder's
timing generator DDA can track. This limitation has always existed, but
it typically wasn't encountered without the use of joiners and DSC.
With higher resolutions and combinations involving joiners and DSC,
this constraint can now be hit in certain scenarios.

Restrict the link configurations to those satisfying the constraint
while computing the link config limits, so that the SST and the MST
paths both get it, and so that a mode which no link rate can support
fails early rather than deep inside link config selection.

Also prune such modes in mode_valid. Note the ratio is the pixel clock
over the link symbol clock, and the symbol clock is not monotonic in the
link rate: it is the rate divided by 32 for 128b/132b but only by 10 for
8b/10b, so e.g. HBR3 has a higher symbol clock than UHBR20. There is
therefore no single best link rate to evaluate against, and mode_valid
walks the link configurations instead, only rejecting the mode if none
of them can satisfy the ratio.

For MSO, intel_dp_compute_config() divides adjusted_mode->crtc_clock by
the MSO link count before computing the link M/N. The limits and
mode_valid are evaluated before that, so divide the pixel clock by the
link count there as well, otherwise the check would be too strict by
that factor. The joiner needs no such handling, as
intel_joiner_adjust_timings() only rewrites the pipe mode and leaves the
adjusted mode the link M/N is derived from untouched.

Note: MST goes through intel_dp_compute_config_limits() as well, so its
compute config is already covered here. Only pruning the modes in the
MST mode_valid is left, which is added in a subsequent commit.

v2:
-Move the M/N ratio check to the link rate configuration phase instead
of during M/N computation. (Ville)
-Prune modes that cannot be supported even with highest link rate due to
M/N ratio restriction.
v3:
-Rebase on the link caps iterator based link config selection.
-Set the constraint up in intel_dp_compute_config_limits() by narrowing
the link config filter, and fail there if no config qualifies, instead
of skipping configs while iterating them. (Imre)
-Use a limit of 4 on DG2. (Wa_14014191401)
-Walk the link configurations in mode_valid rather than evaluating the
ratio at the highest link rate, which is not the best case for it.
v4:
-Add iterator for all dp configs in intel_dp_mode_valid_m_n() so
that we do not prune any mode that could have been supported (Sashiko)
v5:
-Drop "SST" from the subject and fix the note, MST compute is already
covered by the shared limits, only the MST mode_valid is left. (Mitul)
-Add the Bspec reference. (Mitul)
-Drop the link_n check, compute_m_n() fixes N at 0x80000 and only halves
it, so it cannot be 0. (Mitul)
-Fold in the MSO adjusted pixel clock from the M/N ratio check commit, so
this commit is correct on its own. (Mitul)
-Add intel_dp_link_m_n_ratio(), so that the M/N ratio check can share
it. (Mitul)

Bspec: 49266
Co-developed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |   4 +-
 drivers/gpu/drm/i915/display/intel_display.h |   2 +
 drivers/gpu/drm/i915/display/intel_dp.c      | 114 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h      |   2 +
 4 files changed, 120 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 580c36a52921..f74e7ddf0e41 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2650,8 +2650,8 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
 	intel_reduce_m_n_ratio(ret_m, ret_n);
 }
 
-static void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
-					   int pixel_clock, int link_symbol_clock)
+void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
+				    int pixel_clock, int link_symbol_clock)
 {
 	compute_m_n(link_m, link_n,
 		    pixel_clock, link_symbol_clock,
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index eecafff167d3..404168f4213b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -523,5 +523,7 @@ bool assert_port_valid(struct intel_display *display, enum port port);
 
 bool intel_scanout_needs_vtd_wa(struct intel_display *display);
 int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
+void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
+				    int pixel_clock, int link_symbol_clock);
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d8c0d9381471..7ceb7c02b597 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -63,6 +63,7 @@
 #include "intel_de.h"
 #include "intel_dip.h"
 #include "intel_dip_regs.h"
+#include "intel_display.h"
 #include "intel_display_driver.h"
 #include "intel_display_jiffies.h"
 #include "intel_display_utils.h"
@@ -1267,6 +1268,44 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
 	return true;
 }
 
+static int
+intel_dp_get_max_m_n_ratio(struct intel_display *display)
+{
+	if (display->platform.dg2)
+		return 4;
+
+	return 10;
+}
+
+static int intel_dp_link_m_n_ratio(u32 link_m, u32 link_n)
+{
+	return DIV_ROUND_UP(link_m, link_n);
+}
+
+static bool
+intel_dp_can_support_m_n(struct intel_display *display,
+			 int pixel_clock, int link_rate)
+{
+	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
+	u32 link_m, link_n;
+	int m_n_ratio;
+
+	intel_display_compute_link_m_n(&link_m, &link_n, pixel_clock,
+				       intel_dp_link_symbol_clock(link_rate));
+
+	m_n_ratio = intel_dp_link_m_n_ratio(link_m, link_n);
+
+	return m_n_ratio <= max_m_n_ratio;
+}
+
+static int intel_dp_mso_pixel_clock(struct intel_dp *intel_dp, int pixel_clock)
+{
+	if (!intel_dp->mso_link_count)
+		return pixel_clock;
+
+	return pixel_clock / intel_dp->mso_link_count;
+}
+
 static
 bool intel_dp_can_join(struct intel_dp *intel_dp,
 		       int num_joined_pipes)
@@ -1302,6 +1341,33 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
 	return target_clock <= effective_dotclk_limit;
 }
 
+bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	int m_n_pixel_clock = intel_dp_mso_pixel_clock(intel_dp, pixel_clock);
+	struct intel_dp_link_caps_order order = {
+		.key = INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE,
+		.dir = INTEL_DP_LINK_CAPS_ORDER_DIR_DESC,
+	};
+	struct intel_dp_link_config link_config;
+	struct intel_dp_link_caps_iter iter;
+	bool found = false;
+
+	intel_dp_link_caps_iter_start(&iter, intel_dp->link.caps, order,
+				      INTEL_DP_LINK_CAPS_FILTER_ALL);
+	for_each_dp_link_config(&iter, &link_config) {
+		if (intel_dp_can_support_m_n(display, m_n_pixel_clock,
+					     link_config.rate)) {
+			found = true;
+
+			break;
+		}
+	}
+	intel_dp_link_caps_iter_end(&iter);
+
+	return found;
+}
+
 static enum drm_mode_status
 intel_dp_mode_valid_format(struct intel_connector *connector,
 			   const struct drm_display_mode *mode,
@@ -1456,6 +1522,9 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 			return status;
 	}
 
+	if (!intel_dp_mode_valid_m_n(intel_dp, target_clock))
+		return MODE_CLOCK_HIGH;
+
 	/*
 	 * TODO: Even when using a 4:2:0 sink_format intel_dp_output_format()
 	 * will always choose a 4:4:4 output_format if the DFP can do the
@@ -2656,6 +2725,48 @@ intel_dp_dsc_compute_pipe_bpp_limits(struct intel_connector *connector,
 	return true;
 }
 
+static bool
+intel_dp_compute_m_n_ratio_limits(struct intel_dp *intel_dp,
+				  struct drm_connector_state *conn_state,
+				  const struct intel_crtc_state *crtc_state,
+				  struct link_config_limits *limits)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
+	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
+	struct intel_dp_link_caps_order order =
+		intel_dp_link_caps_connector_compute_order(connector);
+	struct intel_dp_link_caps_filter new_filter = INTEL_DP_LINK_CAPS_FILTER_NONE;
+	int pixel_clock = intel_dp_mso_pixel_clock(intel_dp,
+						  intel_dp_mode_clock(crtc_state, conn_state));
+	struct intel_dp_link_config link_config;
+	struct intel_dp_link_caps_iter iter;
+	bool found = false;
+
+	intel_dp_link_caps_iter_start(&iter, link_caps, order, limits->link_config_filter);
+	for_each_dp_link_config(&iter, &link_config) {
+		if (!intel_dp_can_support_m_n(display, pixel_clock, link_config.rate))
+			continue;
+
+		intel_dp_link_caps_filter_add(link_caps, &new_filter, &link_config);
+		found = true;
+	}
+	intel_dp_link_caps_iter_end(&iter);
+
+	if (!found) {
+		drm_dbg_kms(display->drm,
+			    "[CONNECTOR:%d:%s] No link config with a Link M/N ratio <= %d\n",
+			    connector->base.base.id, connector->base.name,
+			    intel_dp_get_max_m_n_ratio(display));
+
+		return false;
+	}
+
+	limits->link_config_filter = new_filter;
+
+	return true;
+}
+
 bool
 intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 			       struct drm_connector_state *conn_state,
@@ -2772,6 +2883,9 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 		limits->link_config_filter = new_filter;
 	}
 
+	if (!intel_dp_compute_m_n_ratio_limits(intel_dp, conn_state, crtc_state, limits))
+		return false;
+
 	if (!intel_dp_test_compute_config(connector, crtc_state, limits))
 		return false;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 04fae203bb69..aa58833a405b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -239,6 +239,8 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
 
 u8 intel_dp_as_sdp_transmission_time(void);
 
+bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock);
+
 int intel_dp_link_init(struct intel_dp *intel_dp);
 void intel_dp_link_cleanup(struct intel_dp *intel_dp);
 
-- 
2.34.1

[PATCH v5 03/11] drm/i915/display_wa: Add support for Wa_14014191401

[Suraj Kandpal]

The DG2 transcoder timing generator DDA only supports a Link M/N ratio
of up to 4. The Link M/N ratio limit uses a bare platform check for it.

Add Wa_14014191401 for DG2 and use it for the limit instead.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_wa.c | 2 ++
 drivers/gpu/drm/i915/display/intel_display_wa.h | 1 +
 drivers/gpu/drm/i915/display/intel_dp.c         | 3 ++-
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index 2e3ff4861ef4..91395076e903 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -94,6 +94,8 @@ bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa,
 			IS_DISPLAY_STEP(display, STEP_A0, STEP_A2);
 	case INTEL_DISPLAY_WA_14014143976:
 		return IS_DISPLAY_STEP(display, STEP_E0, STEP_FOREVER);
+	case INTEL_DISPLAY_WA_14014191401:
+		return display->platform.dg2;
 	case INTEL_DISPLAY_WA_14016740474:
 		return IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_C0);
 	case INTEL_DISPLAY_WA_14020863754:
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h
index b707147a7587..f41e58d1d6e7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.h
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
@@ -31,6 +31,7 @@ enum intel_display_wa {
 	INTEL_DISPLAY_WA_14011508470,
 	INTEL_DISPLAY_WA_14011765242,
 	INTEL_DISPLAY_WA_14014143976,
+	INTEL_DISPLAY_WA_14014191401,
 	INTEL_DISPLAY_WA_14016740474,
 	INTEL_DISPLAY_WA_14020863754,
 	INTEL_DISPLAY_WA_14025769978,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7ceb7c02b597..f3a79ae49b18 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -70,6 +70,7 @@
 #include "intel_display_regs.h"
 #include "intel_display_rpm.h"
 #include "intel_display_types.h"
+#include "intel_display_wa.h"
 #include "intel_dp.h"
 #include "intel_dp_aux.h"
 #include "intel_dp_hdcp.h"
@@ -1271,7 +1272,7 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
 static int
 intel_dp_get_max_m_n_ratio(struct intel_display *display)
 {
-	if (display->platform.dg2)
+	if (intel_display_wa(display, INTEL_DISPLAY_WA_14014191401))
 		return 4;
 
 	return 10;
-- 
2.34.1

[PATCH v5 04/11] drm/i915/dp_mst: Limit M/N ratio for MST

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

The hardware does not support DisplayPort configurations where the
ceiling of the Link M/Link N ratio exceeds the limit. Enforce this
constraint for MST as well.

The compute config path needs no change: MST goes through
intel_dp_compute_config_limits() too, so the link config filter set up
there already excludes the configurations violating the ratio limit, and
MST fails there if none is left.

What is still missing is pruning such modes, so add the check to
mst_connector_mode_valid_ctx(), reusing the helper the SST mode_valid
uses. It walks the link configurations and only rejects the mode if none
of them can satisfy the ratio, rather than evaluating it at a single
link rate.

v2:
-Drop the checks in the MST link config helpers, redundant now that the
constraint is applied while computing the link config limits. (Imre)
-Share the mode_valid helper with SST instead of evaluating the ratio at
one link rate, since the link symbol clock is not monotonic in the link
rate and there is no single best case configuration.
v3:
-Now that intel_dp_mode_valid_m_n checks for all configs just call
that (Sashiko)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 7023619aaaba..f00edfb66a10 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1565,6 +1565,11 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 					   min_link_bpp_x16,
 					   bw_overhead_flags);
 
+	if (!intel_dp_mode_valid_m_n(intel_dp, mode->clock)) {
+		*status = MODE_CLOCK_HIGH;
+		return 0;
+	}
+
 	/*
 	 * TODO:
 	 * - Also check if compression would allow for the mode
-- 
2.34.1

[PATCH v5 05/11] drm/i915/dp: Add M/N ratio check for DP link config

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Introduce intel_dp_check_m_n_ratio() to validate the computed link M/N
ratio against the maximum allowed value, and log it if the ratio exceeds
the limit.

The link config limits computed in the previous commits only restrict
the configurations that may be selected; this catches anything that
still slips through.

Log it rather than warn about it: the link config filter already
excludes the configurations violating the limit, so the only way to get
here is with link parameters forced through debugfs, which are applied
after that filter. A user triggerable drm_WARN() with its backtrace
would be out of proportion for that.

For MST the check goes after the bpp loop rather than inside it. The
link M/N is computed from the pixel clock and the link symbol clock, so
it does not depend on the bpp being tried and the result is the same on
every iteration.

v2:
-Use the platform specific ratio limit. (Wa_14014191401)
-Use the MSO adjusted pixel clock when predicting the ratio, matching
what the link M/N is actually computed from. (Imre)
-Drop the check from ilk_fdi_compute_config(): it was passing dp_m_n
rather than the fdi_m_n it had just computed, and an FDI link cannot get
anywhere near the ratio limit anyway.
v3:
-Check the ratio once after the MST bpp loop instead of on every
iteration, the result does not depend on the bpp. (Sashiko)
-Log instead of warning, since the link config filter already excludes
these configurations and only forced link parameters can reach it.
(Sashiko)
v4:
-Move the MSO adjusted pixel clock to the commit adding the prediction,
so that one is correct on its own. (Mitul)
-Reuse intel_dp_link_m_n_ratio() instead of open coding the ratio.
(Mitul)
-Drop the m_n and link_n checks, neither can be NULL or 0. Make the
parameters const and move it next to intel_dp_can_support_m_n().
(Mitul)
-Drop the check on dp_m2_n2, the dp_m_n one already covers it. (Mitul)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c     | 17 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h     |  4 ++++
 drivers/gpu/drm/i915/display/intel_dp_mst.c |  2 ++
 3 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f3a79ae49b18..8ef6b4c4fc8e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1299,6 +1299,21 @@ intel_dp_can_support_m_n(struct intel_display *display,
 	return m_n_ratio <= max_m_n_ratio;
 }
 
+void intel_dp_check_m_n_ratio(const struct intel_crtc_state *crtc_state,
+			      const struct intel_link_m_n *m_n)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
+	int m_n_ratio;
+
+	m_n_ratio = intel_dp_link_m_n_ratio(m_n->link_m, m_n->link_n);
+
+	if (m_n_ratio > max_m_n_ratio)
+		drm_dbg_kms(display->drm,
+			    "Link M/N ratio (%d) exceeds max allowed (%d)\n",
+			    m_n_ratio, max_m_n_ratio);
+}
+
 static int intel_dp_mso_pixel_clock(struct intel_dp *intel_dp, int pixel_clock)
 {
 	if (!intel_dp->mso_link_count)
@@ -3755,6 +3770,8 @@ intel_dp_compute_config(struct intel_atomic_state *state,
 				       pipe_config->port_clock,
 				       intel_dp_bw_fec_overhead(pipe_config->fec_enable),
 				       &pipe_config->dp_m_n);
+
+		intel_dp_check_m_n_ratio(pipe_config, &pipe_config->dp_m_n);
 	}
 
 	ret = intel_dp_compute_min_hblank(pipe_config, conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index aa58833a405b..1e3da678c9b6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -26,6 +26,7 @@ struct intel_display;
 struct intel_dp;
 struct intel_dp_link_config;
 struct intel_encoder;
+struct intel_link_m_n;
 
 struct link_config_limits {
 	struct intel_dp_link_caps_filter link_config_filter;
@@ -244,4 +245,7 @@ bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock);
 int intel_dp_link_init(struct intel_dp *intel_dp);
 void intel_dp_link_cleanup(struct intel_dp *intel_dp);
 
+void intel_dp_check_m_n_ratio(const struct intel_crtc_state *crtc_state,
+			      const struct intel_link_m_n *m_n);
+
 #endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index f00edfb66a10..8db84975f36b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -429,6 +429,8 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
 		return slots;
 	}
 
+	intel_dp_check_m_n_ratio(crtc_state, &crtc_state->dp_m_n);
+
 	if (!dsc)
 		crtc_state->pipe_bpp = fxp_q4_to_int(bpp_x16);
 	else
-- 
2.34.1

[PATCH v5 06/11] drm/i915/display: Add bits for link_n_extended for DISPLAY >= 14

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

LINK_N register has bits 31:24 for extended link N value used for
HDMI2.1 and for an alternate mode of operation of DP TG DDA.

Add support for these extra bits.

For displays with version 14 or higher, PIPE_LINK_N1_EXTENDED_MASK
(bits 31:24) is used to handle the extended link N bits. For older
platforms, DATA_LINK_M_N_MASK (bits 23:0) is used to handle the
standard link N bits. This distinction ensures clarity and maintains
the semantics for platforms that support the extended bits. In
subsequent changes the logic is updated to conditionally apply the
extended link N bits.

v2: Drop extra link_n_ext member. (Jani)
v3: Avoid link_n_ext in set_m_n helper. (Jani)
v4: Rebase, and update commit message.
v5: Drop a stale changelog entry, the DISPLAY_VER split here is
    intentional. (Sashiko)

Bspec: 50488
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c   | 18 ++++++++++++++++--
 .../gpu/drm/i915/display/intel_display_regs.h  |  2 ++
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f74e7ddf0e41..461b81bf8341 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2720,14 +2720,22 @@ void intel_set_m_n(struct intel_display *display,
 		   intel_reg_t data_m_reg, intel_reg_t data_n_reg,
 		   intel_reg_t link_m_reg, intel_reg_t link_n_reg)
 {
+	u32 link_n = m_n->link_n;
+
 	intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
 	intel_de_write(display, data_n_reg, m_n->data_n);
 	intel_de_write(display, link_m_reg, m_n->link_m);
+
+	if (DISPLAY_VER(display) >= 14)
+		link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
+	else
+		link_n &= DATA_LINK_M_N_MASK;
+
 	/*
 	 * On BDW+ writing LINK_N arms the double buffered update
 	 * of all the M/N registers, so it must be written last.
 	 */
-	intel_de_write(display, link_n_reg, m_n->link_n);
+	intel_de_write(display, link_n_reg, link_n);
 }
 
 bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
@@ -3484,7 +3492,13 @@ void intel_get_m_n(struct intel_display *display,
 		   intel_reg_t link_m_reg, intel_reg_t link_n_reg)
 {
 	m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK;
-	m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK;
+	m_n->link_n = intel_de_read(display, link_n_reg);
+
+	if (DISPLAY_VER(display) >= 14)
+		m_n->link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
+	else
+		m_n->link_n &= DATA_LINK_M_N_MASK;
+
 	m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK;
 	m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK;
 	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 2f509bd06557..983a0d9dcb9c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1190,6 +1190,8 @@
 
 #define _PIPEA_LINK_N1		0x60044
 #define _PIPEB_LINK_N1		0x61044
+#define  PIPE_LINK_N1_EXTENDED_MASK	REG_GENMASK(31, 24)
+#define  PIPE_LINK_N1_EXTENDED(val)	REG_FIELD_PREP(PIPE_LINK_N1_EXTENDED_MASK, (val))
 #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
 
 #define _PIPEA_LINK_M2		0x60048
-- 
2.34.1

[PATCH v5 07/11] drm/i915/display_wa: Add support for Wa_14021768792

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Some BMG ultrajoiner configurations require support for Link M/N ratios
between 10.0 and 15.0. This range is not natively supported and requires
a workaround.

Wa_14021768792 enables this support by utilizing HDMI_EMP_DATA,
CHICKEN_TRANS and the extended bits in the LINK_N register.

Add the necessary logic to enable the workaround on applicable platforms.
The underlying mechanism comes from the display C0,
so it is gated on display stepping C0 and later.

v2:
-Don't include i915_drv.h and don't use struct drm_i915_private under
display/. Use display->platform.battlemage, which names the affected
platform directly, instead of IS_DGFX() combined with a display version
check. (Jani)
-Rebase on the reworked display WA framework, where the condition goes
directly into the __intel_display_wa() switch.

Bspec: 49266
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_wa.c | 9 +++++++++
 drivers/gpu/drm/i915/display/intel_display_wa.h | 1 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index 91395076e903..e6f84dffdeb7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -102,6 +102,15 @@ bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa,
 		return DISPLAY_VERx100(display) == 3000 ||
 			DISPLAY_VERx100(display) == 2000 ||
 			DISPLAY_VERx100(display) == 1401;
+	/*
+	 * Wa_14021768792:
+	 * Fixes: Limitation of Link M/N ratio > 10 for specific Xe2HPD platforms.
+	 * Workaround: Use HDMI_EMP_DATA, CHICKEN_BITs and extended bits in LINK_N
+	 * registers to support LINK M/N ratios from > 10 but < 15.
+	 */
+	case INTEL_DISPLAY_WA_14021768792:
+		return display->platform.battlemage &&
+			IS_DISPLAY_STEP(display, STEP_C0, STEP_FOREVER);
 	case INTEL_DISPLAY_WA_14025769978:
 		return DISPLAY_VER(display) == 35;
 	case INTEL_DISPLAY_WA_14026643300:
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h
index f41e58d1d6e7..0b43c2144dcc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.h
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
@@ -34,6 +34,7 @@ enum intel_display_wa {
 	INTEL_DISPLAY_WA_14014191401,
 	INTEL_DISPLAY_WA_14016740474,
 	INTEL_DISPLAY_WA_14020863754,
+	INTEL_DISPLAY_WA_14021768792,
 	INTEL_DISPLAY_WA_14025769978,
 	INTEL_DISPLAY_WA_14026643300,
 	INTEL_DISPLAY_WA_15013987218,
-- 
2.34.1

[PATCH v5 08/11] drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

To support a Link M/N ratio between 10.0 and 15.0, for some BMG
ultrajoiner cases we need Wa_14021768792.

To bypass the hardware limitation within the Timing Generator DDA
(TGDDA), we need to program the LINKM and LINKN registers as defined in
the WA. Along with this we also need the relevant bits in HDMI_EMP_DATA
and CHICKEN_TRANS.

Add the bits for the WA and a new member 'bypass_m_n_ratio_limit' to
track if we need to bypass the Link M/N ratio limit in the
intel_link_m_n structure.

Per Bspec the extended LINK_N field is two nibbles: bits 27:24 hold
INT(Link M / Link N) and bits 31:28 hold CEIL(Link M / Link N).

The workaround is limited to transcoder A. Check the transcoder rather
than the pipe: for a single pipe the two are the same, but the joiner
secondaries read the M/N back through the primary's transcoder, so a
pipe check would have them report the workaround as not applied while
their state, copied from the primary, has it applied.

CHICKEN_TRANS and HDMI_EMP_DATA are programmed before LINK_N, since
writing LINK_N arms the double buffered update of the M/N registers, and
all of the programming has to be done before the transcoder is enabled.
Both are also explicitly cleared when the mechanism is not in use, so
that state cannot leak from a previous modeset.

Only bypass_m_n_ratio_limit is compared by the state checker, not the
ratio integer and fraction themselves. That is deliberate: both are
derived from Link M and Link N, which are compared already, so the thing
worth verifying is whether the workaround ended up being applied or not.

Unlike the rest of the M/N registers, CHICKEN_TRANS and HDMI_EMP_DATA
are not double buffered, so the flag has to be compared outside the
fastset exemption that PIPE_CONF_CHECK_M_N() has for update_m_n.
Otherwise a seamless M/N update could switch the DDA out of the
workaround on a live transcoder, with the Link M/N values only following
at the next MSA.

v2:
-Drop the drm_WARN_ON() on the extended LINK_N field in intel_get_m_n():
it is derived from Link M and Link N, so the state checker comparison of
those and of bypass_m_n_ratio_limit already covers it. (Sashiko)
-Compare bypass_m_n_ratio_limit unconditionally, so that a change to it
forces a full modeset instead of being applied during a seamless M/N
fastset. (Sashiko)
v3:
-Check for transcoder A instead of pipe A, so that the joiner secondaries
read the flag back the same as the primary. (Mitul)
-Drop bypass_m_n_ratio_limit from intel_compare_link_m_n(), the
unconditional PIPE_CONF_CHECK_BOOL() already compares it. (Mitul)
-Print bypass_m_n_ratio_limit in the crtc state dump. (Mitul)

Bspec: 49266
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 .../drm/i915/display/intel_crtc_state_dump.c  |  6 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 82 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_display.h  |  2 +
 .../gpu/drm/i915/display/intel_display_regs.h | 10 +++
 .../drm/i915/display/intel_display_types.h    |  2 +
 5 files changed, 99 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 92675a88b969..c51b21222dc6 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -36,10 +36,12 @@ intel_dump_m_n_config(struct drm_printer *p,
 		      const char *id, unsigned int lane_count,
 		      const struct intel_link_m_n *m_n)
 {
-	drm_printf(p, "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n",
+	drm_printf(p,
+		   "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u, bypass_m_n_ratio_limit: %s\n",
 		   id, lane_count,
 		   m_n->data_m, m_n->data_n,
-		   m_n->link_m, m_n->link_n, m_n->tu);
+		   m_n->link_m, m_n->link_n, m_n->tu,
+		   str_yes_no(m_n->bypass_m_n_ratio_limit));
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 461b81bf8341..ecc0e5ec181a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2715,6 +2715,15 @@ void intel_zero_m_n(struct intel_link_m_n *m_n)
 	m_n->tu = 1;
 }
 
+static u8 bmg_get_link_n_ext(const struct intel_link_m_n *m_n)
+{
+	if (!m_n->link_n)
+		return 0;
+
+	return PIPE_LINK_N1_EXT_INT(m_n->link_m / m_n->link_n) |
+		PIPE_LINK_N1_EXT_CEIL(DIV_ROUND_UP(m_n->link_m, m_n->link_n));
+}
+
 void intel_set_m_n(struct intel_display *display,
 		   const struct intel_link_m_n *m_n,
 		   intel_reg_t data_m_reg, intel_reg_t data_n_reg,
@@ -2726,7 +2735,9 @@ void intel_set_m_n(struct intel_display *display,
 	intel_de_write(display, data_n_reg, m_n->data_n);
 	intel_de_write(display, link_m_reg, m_n->link_m);
 
-	if (DISPLAY_VER(display) >= 14)
+	if (DISPLAY_VER(display) >= 14 && m_n->bypass_m_n_ratio_limit)
+		link_n |= PIPE_LINK_N1_EXTENDED(bmg_get_link_n_ext(m_n));
+	else if (DISPLAY_VER(display) >= 14)
 		link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
 	else
 		link_n &= DATA_LINK_M_N_MASK;
@@ -2747,6 +2758,26 @@ bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
 	return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview;
 }
 
+static void bmg_enhanced_tgdda_write(struct intel_crtc *crtc,
+				     enum transcoder transcoder,
+				     const struct intel_link_m_n *m_n)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	bool enable = m_n->bypass_m_n_ratio_limit && m_n->link_n;
+	u32 link_m_frac = enable ? m_n->link_m % m_n->link_n : 0;
+
+	if (!intel_display_wa(display, INTEL_DISPLAY_WA_14021768792))
+		return;
+
+	intel_de_rmw(display, HDMI_EMP_DATA(display, transcoder),
+		     HDMI_EMP_DATA_LINK_M_FRAC_MASK,
+		     REG_FIELD_PREP(HDMI_EMP_DATA_LINK_M_FRAC_MASK, link_m_frac));
+
+	intel_de_rmw(display, CHICKEN_TRANS(display, transcoder),
+		     DP_ENHANCED_TGDDA_ENABLE,
+		     enable ? DP_ENHANCED_TGDDA_ENABLE : 0);
+}
+
 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
 				    enum transcoder transcoder,
 				    const struct intel_link_m_n *m_n)
@@ -2754,6 +2785,8 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
 	struct intel_display *display = to_intel_display(crtc);
 	enum pipe pipe = crtc->pipe;
 
+	bmg_enhanced_tgdda_write(crtc, transcoder, m_n);
+
 	if (DISPLAY_VER(display) >= 5)
 		intel_set_m_n(display, m_n,
 			      PIPE_DATA_M1(display, transcoder),
@@ -3504,6 +3537,49 @@ void intel_get_m_n(struct intel_display *display,
 	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;
 }
 
+bool intel_display_can_bypass_m_n_limit(struct intel_display *display,
+					int m_n_ratio,
+					enum transcoder transcoder)
+{
+	if (!intel_display_wa(display, INTEL_DISPLAY_WA_14021768792))
+		return false;
+
+	if (m_n_ratio > 15)
+		return false;
+
+	if (transcoder != TRANSCODER_A)
+		return false;
+
+	return true;
+}
+
+static void bmg_enhanced_tgdda_read(struct intel_crtc *crtc,
+				    enum transcoder transcoder,
+				    struct intel_link_m_n *m_n)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	u32 link_m_frac;
+	int m_n_ratio;
+
+	if (!m_n->link_n)
+		return;
+
+	m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
+
+	if (!intel_display_can_bypass_m_n_limit(display, m_n_ratio, transcoder))
+		return;
+
+	if (!(intel_de_read(display, CHICKEN_TRANS(display, transcoder)) &
+	      DP_ENHANCED_TGDDA_ENABLE))
+		return;
+
+	link_m_frac = REG_FIELD_GET(HDMI_EMP_DATA_LINK_M_FRAC_MASK,
+				    intel_de_read(display, HDMI_EMP_DATA(display, transcoder)));
+
+	if (link_m_frac == m_n->link_m % m_n->link_n)
+		m_n->bypass_m_n_ratio_limit = true;
+}
+
 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
 				    enum transcoder transcoder,
 				    struct intel_link_m_n *m_n)
@@ -3521,6 +3597,8 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
 		intel_get_m_n(display, m_n,
 			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
 			      PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
+
+	bmg_enhanced_tgdda_read(crtc, transcoder, m_n);
 }
 
 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
@@ -5445,6 +5523,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_M_N(dp_m2_n2);
 	}
 
+	PIPE_CONF_CHECK_BOOL(dp_m_n.bypass_m_n_ratio_limit);
+
 	PIPE_CONF_CHECK_X(output_types);
 
 	PIPE_CONF_CHECK_I(framestart_delay);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 404168f4213b..d53b7b4a80e7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -525,5 +525,7 @@ bool intel_scanout_needs_vtd_wa(struct intel_display *display);
 int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
 void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
 				    int pixel_clock, int link_symbol_clock);
+bool intel_display_can_bypass_m_n_limit(struct intel_display *display,
+					int m_n_ratio, enum transcoder transcoder);
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 983a0d9dcb9c..bbdbc27629d7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -550,6 +550,11 @@
 #define _TRANS_MULT_B		0x6102c
 #define TRANS_MULT(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
 
+#define _HDMI_EMP_DATA_A	0x600d8
+#define _HDMI_EMP_DATA_B	0x610d8
+#define  HDMI_EMP_DATA_LINK_M_FRAC_MASK	REG_GENMASK(23, 0)
+#define HDMI_EMP_DATA(display, trans)	_MMIO_TRANS2((display), (trans), _HDMI_EMP_DATA_A)
+
 /* Hotplug control (945+ only) */
 #define PORT_HOTPLUG_EN(dev_priv)		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
 #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
@@ -1192,6 +1197,10 @@
 #define _PIPEB_LINK_N1		0x61044
 #define  PIPE_LINK_N1_EXTENDED_MASK	REG_GENMASK(31, 24)
 #define  PIPE_LINK_N1_EXTENDED(val)	REG_FIELD_PREP(PIPE_LINK_N1_EXTENDED_MASK, (val))
+#define  PIPE_LINK_N1_EXT_CEIL_MASK	REG_GENMASK(7, 4)
+#define  PIPE_LINK_N1_EXT_CEIL(val)	REG_FIELD_PREP(PIPE_LINK_N1_EXT_CEIL_MASK, (val))
+#define  PIPE_LINK_N1_EXT_INT_MASK	REG_GENMASK(3, 0)
+#define  PIPE_LINK_N1_EXT_INT(val)	REG_FIELD_PREP(PIPE_LINK_N1_EXT_INT_MASK, (val))
 #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
 
 #define _PIPEA_LINK_M2		0x60048
@@ -1710,6 +1719,7 @@
 #define   PSR2_ADD_VERTICAL_LINE_COUNT	REG_BIT(15)
 #define   DP_FEC_BS_JITTER_WA		REG_BIT(15)
 #define   PSR2_VSC_ENABLE_PROG_HEADER	REG_BIT(12)
+#define   DP_ENHANCED_TGDDA_ENABLE	REG_BIT(11)
 #define   DP_DSC_INSERT_SF_AT_EOL_WA	REG_BIT(4)
 #define   HDCP_LINE_REKEY_DISABLE	REG_BIT(0)
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8f9fb2603638..d0748837ce97 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -985,6 +985,8 @@ struct intel_link_m_n {
 	u32 data_n;
 	u32 link_m;
 	u32 link_n;
+	/* Wa_14021768792 for linkm/n ratio > 10 */
+	bool bypass_m_n_ratio_limit;
 };
 
 struct intel_csc_matrix {
-- 
2.34.1

[PATCH v5 09/11] drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n ratio > 10

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Handle the bypass logic for the M/N ratio limit for DP.
Calculate the M/N ratio, check if it can bypass the limit, and set the
appropriate flags for the workaround.

v2:
-Restrict the workaround to 128b/132b links.
-Clear bypass_m_n_ratio_limit on entry, so a rejected link rate cannot
leave it set for the rate that gets used. (Sashiko)
v3:
-Rebase on the reworked M/N ratio check, which no longer checks m_n and
link_n. m_n is no longer const, as the flag is set through it. (Mitul)
-Pass the cpu transcoder to intel_display_can_bypass_m_n_limit() instead
of the pipe. (Mitul)

Bspec: 49266
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 28 ++++++++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_dp.h |  2 +-
 2 files changed, 24 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8ef6b4c4fc8e..8e6ba5b9fde6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1300,18 +1300,32 @@ intel_dp_can_support_m_n(struct intel_display *display,
 }
 
 void intel_dp_check_m_n_ratio(const struct intel_crtc_state *crtc_state,
-			      const struct intel_link_m_n *m_n)
+			      struct intel_link_m_n *m_n)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
 	int m_n_ratio;
 
+	m_n->bypass_m_n_ratio_limit = false;
+
 	m_n_ratio = intel_dp_link_m_n_ratio(m_n->link_m, m_n->link_n);
 
-	if (m_n_ratio > max_m_n_ratio)
+	if (m_n_ratio <= max_m_n_ratio)
+		return;
+
+	if (intel_dp_is_uhbr(crtc_state) &&
+	    intel_display_can_bypass_m_n_limit(display, m_n_ratio,
+					       crtc_state->cpu_transcoder)) {
+		m_n->bypass_m_n_ratio_limit = true;
 		drm_dbg_kms(display->drm,
-			    "Link M/N ratio (%d) exceeds max allowed (%d)\n",
-			    m_n_ratio, max_m_n_ratio);
+			    "Bypassing Link_m/Link_n ratio limit (ratio %d)\n",
+			    m_n_ratio);
+		return;
+	}
+
+	drm_dbg_kms(display->drm,
+		    "Link M/N ratio (%d) exceeds max allowed (%d)\n",
+		    m_n_ratio, max_m_n_ratio);
 }
 
 static int intel_dp_mso_pixel_clock(struct intel_dp *intel_dp, int pixel_clock)
@@ -3393,6 +3407,9 @@ static bool can_enable_drrs(struct intel_connector *connector,
 	if (pipe_config->vrr.enable)
 		return false;
 
+	if (pipe_config->dp_m_n.bypass_m_n_ratio_limit)
+		return false;
+
 	/*
 	 * DRRS and PSR can't be enable together, so giving preference to PSR
 	 * as it allows more power-savings by complete shutting down display,
@@ -3427,7 +3444,8 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
 	 * FIXME all joined pipes share the same transcoder.
 	 * Need to account for that when updating M/N live.
 	 */
-	if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes)
+	if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes &&
+	    !pipe_config->dp_m_n.bypass_m_n_ratio_limit)
 		pipe_config->update_m_n = true;
 
 	if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 1e3da678c9b6..c834d90a1f81 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -246,6 +246,6 @@ int intel_dp_link_init(struct intel_dp *intel_dp);
 void intel_dp_link_cleanup(struct intel_dp *intel_dp);
 
 void intel_dp_check_m_n_ratio(const struct intel_crtc_state *crtc_state,
-			      const struct intel_link_m_n *m_n);
+			      struct intel_link_m_n *m_n);
 
 #endif /* __INTEL_DP_H__ */
-- 
2.34.1

[PATCH v5 10/11] drm/i915/dp: Extend intel_dp_can_support_m_n() for BMG M/N bypass

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

On BMG platforms, the standard M/N ratio limit of 10 can be bypassed
under specific conditions, as permitted by hardware capabilities.

Modify the helper intel_dp_can_support_m_n() to account for this by
checking whether the platform supports bypassing the limit. The
workaround is only intended for 128b/132b links, so restrict it to
those.

During the mode_valid phase, the check assumes that TRANSCODER_A will be
used, to allow the mode where the M/N ratio is within the limits for the
workaround.

v2:
-Keep the helper static: the MST mode_valid now goes through the shared
intel_dp_mode_valid_m_n() rather than calling it directly, so it no
longer needs to be exported.
v3:
-Use the cpu transcoder instead of the pipe, following the change to
intel_display_can_bypass_m_n_limit(). (Mitul)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8e6ba5b9fde6..045524994d85 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1285,9 +1285,11 @@ static int intel_dp_link_m_n_ratio(u32 link_m, u32 link_n)
 
 static bool
 intel_dp_can_support_m_n(struct intel_display *display,
+			 const struct intel_crtc_state *crtc_state,
 			 int pixel_clock, int link_rate)
 {
 	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
+	enum transcoder cpu_transcoder = TRANSCODER_A;
 	u32 link_m, link_n;
 	int m_n_ratio;
 
@@ -1296,7 +1298,16 @@ intel_dp_can_support_m_n(struct intel_display *display,
 
 	m_n_ratio = intel_dp_link_m_n_ratio(link_m, link_n);
 
-	return m_n_ratio <= max_m_n_ratio;
+	if (m_n_ratio <= max_m_n_ratio)
+		return true;
+
+	if (!drm_dp_is_uhbr_rate(link_rate))
+		return false;
+
+	if (crtc_state)
+		cpu_transcoder = crtc_state->cpu_transcoder;
+
+	return intel_display_can_bypass_m_n_limit(display, m_n_ratio, cpu_transcoder);
 }
 
 void intel_dp_check_m_n_ratio(const struct intel_crtc_state *crtc_state,
@@ -1386,7 +1397,7 @@ bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock)
 	intel_dp_link_caps_iter_start(&iter, intel_dp->link.caps, order,
 				      INTEL_DP_LINK_CAPS_FILTER_ALL);
 	for_each_dp_link_config(&iter, &link_config) {
-		if (intel_dp_can_support_m_n(display, m_n_pixel_clock,
+		if (intel_dp_can_support_m_n(display, NULL, m_n_pixel_clock,
 					     link_config.rate)) {
 			found = true;
 
@@ -2775,7 +2786,8 @@ intel_dp_compute_m_n_ratio_limits(struct intel_dp *intel_dp,
 
 	intel_dp_link_caps_iter_start(&iter, link_caps, order, limits->link_config_filter);
 	for_each_dp_link_config(&iter, &link_config) {
-		if (!intel_dp_can_support_m_n(display, pixel_clock, link_config.rate))
+		if (!intel_dp_can_support_m_n(display, crtc_state, pixel_clock,
+					      link_config.rate))
 			continue;
 
 		intel_dp_link_caps_filter_add(link_caps, &new_filter, &link_config);
-- 
2.34.1

[PATCH v5 11/11] drm/i915/dp: Bump the max Link M/N ratio to 22 for DISPLAY_VER >= 35

[Suraj Kandpal]

Starting Xe3p max M/N ratio has been increased to 22.

Bspec: 68922
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 045524994d85..5864e33456a7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1272,6 +1272,9 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
 static int
 intel_dp_get_max_m_n_ratio(struct intel_display *display)
 {
+	if (DISPLAY_VER(display) >= 35)
+		return 22;
+
 	if (intel_display_wa(display, INTEL_DISPLAY_WA_14014191401))
 		return 4;
 
-- 
2.34.1

[PATCH v6 00/11] Implement Wa_14021768792 to bypass m_n ratio limit

[Suraj Kandpal]

For Platforms that support higher link rates, there is a limitation on
Link M /Link N ratio.
If the CEILING( Link M / Link N ) ratio is greater than 10.0, then
hardware cannot support the given resolution / refresh rate at the given
configuration.
For BMG Wa_14021768792 helps to bypass this limitation and allows it to
support the ratio till 15.0.

This series adds the missing restrictions for earlier platforms and adds
the Wa_14021768792 for BMG as per Bspec:49266

Ankit Nautiyal (8):
  drm/i915/display: Add helper to compute link M/N ratio for reuse
  drm/i915/dp_mst: Limit M/N ratio for MST
  drm/i915/dp: Add M/N ratio check for DP link config
  drm/i915/display: Add bits for link_n_extended for DISPLAY >= 14
  drm/i915/display_wa: Add support for Wa_14021768792
  drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10
  drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n
    ratio > 10
  drm/i915/dp: Extend intel_dp_can_support_m_n() for BMG M/N bypass

Suraj Kandpal (3):
  drm/i915/dp: Limit M/N ratio for DP
  drm/i915/display_wa: Add support for Wa_14014191401
  drm/i915/dp: Bump the max Link M/N ratio to 22 for DISPLAY_VER >= 35

 .../drm/i915/display/intel_crtc_state_dump.c  |   6 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 113 +++++++++++-
 drivers/gpu/drm/i915/display/intel_display.h  |   4 +
 .../gpu/drm/i915/display/intel_display_regs.h |  12 ++
 .../drm/i915/display/intel_display_types.h    |   2 +
 .../gpu/drm/i915/display/intel_display_wa.c   |  11 ++
 .../gpu/drm/i915/display/intel_display_wa.h   |   2 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 167 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   6 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   7 +
 10 files changed, 321 insertions(+), 9 deletions(-)

-- 
2.34.1

[PATCH v6 01/11] drm/i915/display: Add helper to compute link M/N ratio for reuse

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Introduce intel_display_compute_link_m_n() to compute the link M/N ratio
from the pixel clock and the link symbol clock. This logic was
previously embedded within intel_link_compute_m_n().
The new helper allows reuse of link M/N computation in other contexts
without requiring the full data M/N calculation and will be used in
later commits.

No functional changes intended.

v2:
- Rename function (Jani)
- The link symbol clock is passed in rather than derived here, so that the
DP specific conversion from the link rate stays with the caller. (Jani)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7602f633f49d..580c36a52921 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2650,13 +2650,20 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
 	intel_reduce_m_n_ratio(ret_m, ret_n);
 }
 
+static void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
+					   int pixel_clock, int link_symbol_clock)
+{
+	compute_m_n(link_m, link_n,
+		    pixel_clock, link_symbol_clock,
+		    0x80000);
+}
+
 void
 intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
 		       int pixel_clock, int link_clock,
 		       int bw_overhead,
 		       struct intel_link_m_n *m_n)
 {
-	u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock);
 	u32 data_m = intel_dp_effective_data_rate(pixel_clock, bits_per_pixel_x16,
 						  bw_overhead);
 	u32 data_n = drm_dp_max_dprx_data_rate(link_clock, nlanes);
@@ -2673,9 +2680,9 @@ intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
 		    data_m, data_n,
 		    0x8000000);
 
-	compute_m_n(&m_n->link_m, &m_n->link_n,
-		    pixel_clock, link_symbol_clock,
-		    0x80000);
+	intel_display_compute_link_m_n(&m_n->link_m, &m_n->link_n,
+				       pixel_clock,
+				       intel_dp_link_symbol_clock(link_clock));
 }
 
 void intel_panel_sanitize_ssc(struct intel_display *display)
-- 
2.34.1

[PATCH v6 02/11] drm/i915/dp: Limit M/N ratio for DP

[Suraj Kandpal]

The hardware cannot support DisplayPort configurations where the
ceiling of the Link M/Link N ratio exceeds the limit the transcoder's
timing generator DDA can track. This limitation has always existed, but
it typically wasn't encountered without the use of joiners and DSC.
With higher resolutions and combinations involving joiners and DSC,
this constraint can now be hit in certain scenarios.

Restrict the link configurations to those satisfying the constraint
while computing the link config limits, so that the SST and the MST
paths both get it, and so that a mode which no link rate can support
fails early rather than deep inside link config selection.

Also prune such modes in mode_valid. Note the ratio is the pixel clock
over the link symbol clock, and the symbol clock is not monotonic in the
link rate: it is the rate divided by 32 for 128b/132b but only by 10 for
8b/10b, so e.g. HBR3 has a higher symbol clock than UHBR20. There is
therefore no single best link rate to evaluate against, and mode_valid
walks the link configurations instead, only rejecting the mode if none
of them can satisfy the ratio.

For MSO, intel_dp_compute_config() divides adjusted_mode->crtc_clock by
the MSO link count before computing the link M/N. The limits and
mode_valid are evaluated before that, so divide the pixel clock by the
link count there as well, otherwise the check would be too strict by
that factor. The joiner needs no such handling, as
intel_joiner_adjust_timings() only rewrites the pipe mode and leaves the
adjusted mode the link M/N is derived from untouched.

Note: MST goes through intel_dp_compute_config_limits() as well, so its
compute config is already covered here. Only pruning the modes in the
MST mode_valid is left, which is added in a subsequent commit.

v2:
-Move the M/N ratio check to the link rate configuration phase instead
of during M/N computation. (Ville)
-Prune modes that cannot be supported even with highest link rate due to
M/N ratio restriction.
v3:
-Rebase on the link caps iterator based link config selection.
-Set the constraint up in intel_dp_compute_config_limits() by narrowing
the link config filter, and fail there if no config qualifies, instead
of skipping configs while iterating them. (Imre)
-Use a limit of 4 on DG2. (Wa_14014191401)
-Walk the link configurations in mode_valid rather than evaluating the
ratio at the highest link rate, which is not the best case for it.
v4:
-Add iterator for all dp configs in intel_dp_mode_valid_m_n() so
that we do not prune any mode that could have been supported (Sashiko)
v5:
-Drop "SST" from the subject and fix the note, MST compute is already
covered by the shared limits, only the MST mode_valid is left. (Mitul)
-Add the Bspec reference. (Mitul)
-Drop the link_n check, compute_m_n() fixes N at 0x80000 and only halves
it, so it cannot be 0. (Mitul)
-Fold in the MSO adjusted pixel clock from the M/N ratio check commit, so
this commit is correct on its own. (Mitul)
-Add intel_dp_link_m_n_ratio(), so that the M/N ratio check can share
it. (Mitul)

Bspec: 49266
Co-developed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |   4 +-
 drivers/gpu/drm/i915/display/intel_display.h |   2 +
 drivers/gpu/drm/i915/display/intel_dp.c      | 114 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h      |   2 +
 4 files changed, 120 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 580c36a52921..f74e7ddf0e41 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2650,8 +2650,8 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
 	intel_reduce_m_n_ratio(ret_m, ret_n);
 }
 
-static void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
-					   int pixel_clock, int link_symbol_clock)
+void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
+				    int pixel_clock, int link_symbol_clock)
 {
 	compute_m_n(link_m, link_n,
 		    pixel_clock, link_symbol_clock,
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index eecafff167d3..404168f4213b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -523,5 +523,7 @@ bool assert_port_valid(struct intel_display *display, enum port port);
 
 bool intel_scanout_needs_vtd_wa(struct intel_display *display);
 int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
+void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
+				    int pixel_clock, int link_symbol_clock);
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d8c0d9381471..7ceb7c02b597 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -63,6 +63,7 @@
 #include "intel_de.h"
 #include "intel_dip.h"
 #include "intel_dip_regs.h"
+#include "intel_display.h"
 #include "intel_display_driver.h"
 #include "intel_display_jiffies.h"
 #include "intel_display_utils.h"
@@ -1267,6 +1268,44 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
 	return true;
 }
 
+static int
+intel_dp_get_max_m_n_ratio(struct intel_display *display)
+{
+	if (display->platform.dg2)
+		return 4;
+
+	return 10;
+}
+
+static int intel_dp_link_m_n_ratio(u32 link_m, u32 link_n)
+{
+	return DIV_ROUND_UP(link_m, link_n);
+}
+
+static bool
+intel_dp_can_support_m_n(struct intel_display *display,
+			 int pixel_clock, int link_rate)
+{
+	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
+	u32 link_m, link_n;
+	int m_n_ratio;
+
+	intel_display_compute_link_m_n(&link_m, &link_n, pixel_clock,
+				       intel_dp_link_symbol_clock(link_rate));
+
+	m_n_ratio = intel_dp_link_m_n_ratio(link_m, link_n);
+
+	return m_n_ratio <= max_m_n_ratio;
+}
+
+static int intel_dp_mso_pixel_clock(struct intel_dp *intel_dp, int pixel_clock)
+{
+	if (!intel_dp->mso_link_count)
+		return pixel_clock;
+
+	return pixel_clock / intel_dp->mso_link_count;
+}
+
 static
 bool intel_dp_can_join(struct intel_dp *intel_dp,
 		       int num_joined_pipes)
@@ -1302,6 +1341,33 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
 	return target_clock <= effective_dotclk_limit;
 }
 
+bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	int m_n_pixel_clock = intel_dp_mso_pixel_clock(intel_dp, pixel_clock);
+	struct intel_dp_link_caps_order order = {
+		.key = INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE,
+		.dir = INTEL_DP_LINK_CAPS_ORDER_DIR_DESC,
+	};
+	struct intel_dp_link_config link_config;
+	struct intel_dp_link_caps_iter iter;
+	bool found = false;
+
+	intel_dp_link_caps_iter_start(&iter, intel_dp->link.caps, order,
+				      INTEL_DP_LINK_CAPS_FILTER_ALL);
+	for_each_dp_link_config(&iter, &link_config) {
+		if (intel_dp_can_support_m_n(display, m_n_pixel_clock,
+					     link_config.rate)) {
+			found = true;
+
+			break;
+		}
+	}
+	intel_dp_link_caps_iter_end(&iter);
+
+	return found;
+}
+
 static enum drm_mode_status
 intel_dp_mode_valid_format(struct intel_connector *connector,
 			   const struct drm_display_mode *mode,
@@ -1456,6 +1522,9 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 			return status;
 	}
 
+	if (!intel_dp_mode_valid_m_n(intel_dp, target_clock))
+		return MODE_CLOCK_HIGH;
+
 	/*
 	 * TODO: Even when using a 4:2:0 sink_format intel_dp_output_format()
 	 * will always choose a 4:4:4 output_format if the DFP can do the
@@ -2656,6 +2725,48 @@ intel_dp_dsc_compute_pipe_bpp_limits(struct intel_connector *connector,
 	return true;
 }
 
+static bool
+intel_dp_compute_m_n_ratio_limits(struct intel_dp *intel_dp,
+				  struct drm_connector_state *conn_state,
+				  const struct intel_crtc_state *crtc_state,
+				  struct link_config_limits *limits)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
+	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
+	struct intel_dp_link_caps_order order =
+		intel_dp_link_caps_connector_compute_order(connector);
+	struct intel_dp_link_caps_filter new_filter = INTEL_DP_LINK_CAPS_FILTER_NONE;
+	int pixel_clock = intel_dp_mso_pixel_clock(intel_dp,
+						  intel_dp_mode_clock(crtc_state, conn_state));
+	struct intel_dp_link_config link_config;
+	struct intel_dp_link_caps_iter iter;
+	bool found = false;
+
+	intel_dp_link_caps_iter_start(&iter, link_caps, order, limits->link_config_filter);
+	for_each_dp_link_config(&iter, &link_config) {
+		if (!intel_dp_can_support_m_n(display, pixel_clock, link_config.rate))
+			continue;
+
+		intel_dp_link_caps_filter_add(link_caps, &new_filter, &link_config);
+		found = true;
+	}
+	intel_dp_link_caps_iter_end(&iter);
+
+	if (!found) {
+		drm_dbg_kms(display->drm,
+			    "[CONNECTOR:%d:%s] No link config with a Link M/N ratio <= %d\n",
+			    connector->base.base.id, connector->base.name,
+			    intel_dp_get_max_m_n_ratio(display));
+
+		return false;
+	}
+
+	limits->link_config_filter = new_filter;
+
+	return true;
+}
+
 bool
 intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 			       struct drm_connector_state *conn_state,
@@ -2772,6 +2883,9 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 		limits->link_config_filter = new_filter;
 	}
 
+	if (!intel_dp_compute_m_n_ratio_limits(intel_dp, conn_state, crtc_state, limits))
+		return false;
+
 	if (!intel_dp_test_compute_config(connector, crtc_state, limits))
 		return false;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 04fae203bb69..aa58833a405b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -239,6 +239,8 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
 
 u8 intel_dp_as_sdp_transmission_time(void);
 
+bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock);
+
 int intel_dp_link_init(struct intel_dp *intel_dp);
 void intel_dp_link_cleanup(struct intel_dp *intel_dp);
 
-- 
2.34.1

[PATCH v6 03/11] drm/i915/display_wa: Add support for Wa_14014191401

[Suraj Kandpal]

The DG2 transcoder timing generator DDA only supports a Link M/N ratio
of up to 4. The Link M/N ratio limit uses a bare platform check for it.

Add Wa_14014191401 for DG2 and use it for the limit instead.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_wa.c | 2 ++
 drivers/gpu/drm/i915/display/intel_display_wa.h | 1 +
 drivers/gpu/drm/i915/display/intel_dp.c         | 3 ++-
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index 2e3ff4861ef4..91395076e903 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -94,6 +94,8 @@ bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa,
 			IS_DISPLAY_STEP(display, STEP_A0, STEP_A2);
 	case INTEL_DISPLAY_WA_14014143976:
 		return IS_DISPLAY_STEP(display, STEP_E0, STEP_FOREVER);
+	case INTEL_DISPLAY_WA_14014191401:
+		return display->platform.dg2;
 	case INTEL_DISPLAY_WA_14016740474:
 		return IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_C0);
 	case INTEL_DISPLAY_WA_14020863754:
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h
index b707147a7587..f41e58d1d6e7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.h
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
@@ -31,6 +31,7 @@ enum intel_display_wa {
 	INTEL_DISPLAY_WA_14011508470,
 	INTEL_DISPLAY_WA_14011765242,
 	INTEL_DISPLAY_WA_14014143976,
+	INTEL_DISPLAY_WA_14014191401,
 	INTEL_DISPLAY_WA_14016740474,
 	INTEL_DISPLAY_WA_14020863754,
 	INTEL_DISPLAY_WA_14025769978,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7ceb7c02b597..f3a79ae49b18 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -70,6 +70,7 @@
 #include "intel_display_regs.h"
 #include "intel_display_rpm.h"
 #include "intel_display_types.h"
+#include "intel_display_wa.h"
 #include "intel_dp.h"
 #include "intel_dp_aux.h"
 #include "intel_dp_hdcp.h"
@@ -1271,7 +1272,7 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
 static int
 intel_dp_get_max_m_n_ratio(struct intel_display *display)
 {
-	if (display->platform.dg2)
+	if (intel_display_wa(display, INTEL_DISPLAY_WA_14014191401))
 		return 4;
 
 	return 10;
-- 
2.34.1

RE: [PATCH v6 03/11] drm/i915/display_wa: Add support for Wa_14014191401

[Golani, Mitulkumar Ajitkumar]

I think the patch order may need to be adjusted: swap this patch with patch 2 and move the current patch 2 to position 3.

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: 21 October 2026 12:44
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
> Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: [PATCH v6 03/11] drm/i915/display_wa: Add support for
> Wa_14014191401
> 
> The DG2 transcoder timing generator DDA only supports a Link M/N ratio of
> up to 4. The Link M/N ratio limit uses a bare platform check for it.
> 
> Add Wa_14014191401 for DG2 and use it for the limit instead.
> 
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_wa.c | 2 ++
> drivers/gpu/drm/i915/display/intel_display_wa.h | 1 +
>  drivers/gpu/drm/i915/display/intel_dp.c         | 3 ++-
>  3 files changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c
> b/drivers/gpu/drm/i915/display/intel_display_wa.c
> index 2e3ff4861ef4..91395076e903 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_wa.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
> @@ -94,6 +94,8 @@ bool __intel_display_wa(struct intel_display *display,
> enum intel_display_wa wa,
>  			IS_DISPLAY_STEP(display, STEP_A0, STEP_A2);
>  	case INTEL_DISPLAY_WA_14014143976:
>  		return IS_DISPLAY_STEP(display, STEP_E0, STEP_FOREVER);
> +	case INTEL_DISPLAY_WA_14014191401:
> +		return display->platform.dg2;
>  	case INTEL_DISPLAY_WA_14016740474:
>  		return IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0,
> STEP_C0);
>  	case INTEL_DISPLAY_WA_14020863754:
> diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h
> b/drivers/gpu/drm/i915/display/intel_display_wa.h
> index b707147a7587..f41e58d1d6e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_wa.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
> @@ -31,6 +31,7 @@ enum intel_display_wa {
>  	INTEL_DISPLAY_WA_14011508470,
>  	INTEL_DISPLAY_WA_14011765242,
>  	INTEL_DISPLAY_WA_14014143976,
> +	INTEL_DISPLAY_WA_14014191401,
>  	INTEL_DISPLAY_WA_14016740474,
>  	INTEL_DISPLAY_WA_14020863754,
>  	INTEL_DISPLAY_WA_14025769978,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7ceb7c02b597..f3a79ae49b18 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -70,6 +70,7 @@
>  #include "intel_display_regs.h"
>  #include "intel_display_rpm.h"
>  #include "intel_display_types.h"
> +#include "intel_display_wa.h"
>  #include "intel_dp.h"
>  #include "intel_dp_aux.h"
>  #include "intel_dp_hdcp.h"
> @@ -1271,7 +1272,7 @@ bool intel_dp_has_dsc(const struct intel_connector
> *connector)  static int  intel_dp_get_max_m_n_ratio(struct intel_display
> *display)  {
> -	if (display->platform.dg2)
> +	if (intel_display_wa(display, INTEL_DISPLAY_WA_14014191401))

With above suggested change is done, 
LGTM
Reviewed-by: Mitul Golani<mitulkumar.ajitkumar.golani@intel.com>

>  		return 4;
> 
>  	return 10;
> --
> 2.34.1

RE: [PATCH v6 03/11] drm/i915/display_wa: Add support for Wa_14014191401

[Kandpal, Suraj]

> I think the patch order may need to be adjusted: swap this patch with patch 2
> and move the current patch 2 to position 3.

The patch ordering cannot be changed because  the function in which 
if (intel_display_wa(display, INTEL_DISPLAY_WA_14014191401))
was called was introduced in patch 2, hence the patch 2 needs to comes first

Regards,
Suraj Kandpal

> 
> > -----Original Message-----
> > From: Kandpal, Suraj <suraj.kandpal@intel.com>
> > Sent: 21 October 2026 12:44
> > To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > Cc: Golani, Mitulkumar Ajitkumar
> > <mitulkumar.ajitkumar.golani@intel.com>;
> > Kandpal, Suraj <suraj.kandpal@intel.com>
> > Subject: [PATCH v6 03/11] drm/i915/display_wa: Add support for
> > Wa_14014191401
> >
> > The DG2 transcoder timing generator DDA only supports a Link M/N ratio
> > of up to 4. The Link M/N ratio limit uses a bare platform check for it.
> >
> > Add Wa_14014191401 for DG2 and use it for the limit instead.
> >
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display_wa.c | 2 ++
> > drivers/gpu/drm/i915/display/intel_display_wa.h | 1 +
> >  drivers/gpu/drm/i915/display/intel_dp.c         | 3 ++-
> >  3 files changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c
> > b/drivers/gpu/drm/i915/display/intel_display_wa.c
> > index 2e3ff4861ef4..91395076e903 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_wa.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
> > @@ -94,6 +94,8 @@ bool __intel_display_wa(struct intel_display
> > *display, enum intel_display_wa wa,
> >  			IS_DISPLAY_STEP(display, STEP_A0, STEP_A2);
> >  	case INTEL_DISPLAY_WA_14014143976:
> >  		return IS_DISPLAY_STEP(display, STEP_E0, STEP_FOREVER);
> > +	case INTEL_DISPLAY_WA_14014191401:
> > +		return display->platform.dg2;
> >  	case INTEL_DISPLAY_WA_14016740474:
> >  		return IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0,
> STEP_C0);
> >  	case INTEL_DISPLAY_WA_14020863754:
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h
> > b/drivers/gpu/drm/i915/display/intel_display_wa.h
> > index b707147a7587..f41e58d1d6e7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_wa.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
> > @@ -31,6 +31,7 @@ enum intel_display_wa {
> >  	INTEL_DISPLAY_WA_14011508470,
> >  	INTEL_DISPLAY_WA_14011765242,
> >  	INTEL_DISPLAY_WA_14014143976,
> > +	INTEL_DISPLAY_WA_14014191401,
> >  	INTEL_DISPLAY_WA_14016740474,
> >  	INTEL_DISPLAY_WA_14020863754,
> >  	INTEL_DISPLAY_WA_14025769978,
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 7ceb7c02b597..f3a79ae49b18 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -70,6 +70,7 @@
> >  #include "intel_display_regs.h"
> >  #include "intel_display_rpm.h"
> >  #include "intel_display_types.h"
> > +#include "intel_display_wa.h"
> >  #include "intel_dp.h"
> >  #include "intel_dp_aux.h"
> >  #include "intel_dp_hdcp.h"
> > @@ -1271,7 +1272,7 @@ bool intel_dp_has_dsc(const struct
> > intel_connector
> > *connector)  static int  intel_dp_get_max_m_n_ratio(struct
> > intel_display
> > *display)  {
> > -	if (display->platform.dg2)
> > +	if (intel_display_wa(display, INTEL_DISPLAY_WA_14014191401))
> 
> With above suggested change is done,
> LGTM
> Reviewed-by: Mitul Golani<mitulkumar.ajitkumar.golani@intel.com>
> 
> >  		return 4;
> >
> >  	return 10;
> > --
> > 2.34.1

[PATCH v6 04/11] drm/i915/dp_mst: Limit M/N ratio for MST

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

The hardware does not support DisplayPort configurations where the
ceiling of the Link M/Link N ratio exceeds the limit. Enforce this
constraint for MST as well.

The compute config path needs no change: MST goes through
intel_dp_compute_config_limits() too, so the link config filter set up
there already excludes the configurations violating the ratio limit, and
MST fails there if none is left.

What is still missing is pruning such modes, so add the check to
mst_connector_mode_valid_ctx(), reusing the helper the SST mode_valid
uses. It walks the link configurations and only rejects the mode if none
of them can satisfy the ratio, rather than evaluating it at a single
link rate.

v2:
-Drop the checks in the MST link config helpers, redundant now that the
constraint is applied while computing the link config limits. (Imre)
-Share the mode_valid helper with SST instead of evaluating the ratio at
one link rate, since the link symbol clock is not monotonic in the link
rate and there is no single best case configuration.
v3:
-Now that intel_dp_mode_valid_m_n checks for all configs just call
that (Sashiko)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 7023619aaaba..f00edfb66a10 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1565,6 +1565,11 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 					   min_link_bpp_x16,
 					   bw_overhead_flags);
 
+	if (!intel_dp_mode_valid_m_n(intel_dp, mode->clock)) {
+		*status = MODE_CLOCK_HIGH;
+		return 0;
+	}
+
 	/*
 	 * TODO:
 	 * - Also check if compression would allow for the mode
-- 
2.34.1

Re: [PATCH v6 04/11] drm/i915/dp_mst: Limit M/N ratio for MST

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/dp_mst: M/N mode_valid and compute_config_limits filter mismatch
--

commit 5b89059b3b94b9fbcca8f03ce951374211a9cdbc
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

drm/i915/dp_mst: Limit M/N ratio for MST

This commit adds a Link M/N ratio check to mst_connector_mode_valid_ctx()
using intel_dp_mode_valid_m_n() to prune modes whose pixel clock exceeds
the hardware Link M/N ratio limit across all link configurations.

> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 7023619aaaba9..f00edfb66a10a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -1565,6 +1565,11 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
>  					   min_link_bpp_x16,
>  					   bw_overhead_flags);
>  
> +	if (!intel_dp_mode_valid_m_n(intel_dp, mode->clock)) {
> +		*status = MODE_CLOCK_HIGH;
> +		return 0;
> +	}
> +
>  	/*
>  	 * TODO:
>  	 * - Also check if compression would allow for the mode

[Severity: Medium]
Could there be a mismatch here between how mst_connector_mode_valid_ctx()
validates the M/N ratio and how intel_dp_compute_config_limits() filters
link configurations for MST?

In drivers/gpu/drm/i915/display/intel_dp_mst.c,
mst_connector_mode_valid_ctx() checks link bandwidth solely against
max_bw_config, whereas intel_dp_mode_valid_m_n() iterates over all link
configurations in INTEL_DP_LINK_CAPS_FILTER_ALL:

drivers/gpu/drm/i915/display/intel_dp.c:intel_dp_mode_valid_m_n() {
	...
	intel_dp_link_caps_iter_start(&iter, intel_dp->link.caps, order,
				      INTEL_DP_LINK_CAPS_FILTER_ALL);
	for_each_dp_link_config(&iter, &link_config) {
		if (intel_dp_can_support_m_n(display, m_n_pixel_clock,
					     link_config.rate)) {
			found = true;

			break;
		}
	}
	...
}

However, during modeset via mst_stream_compute_config() ->
mst_stream_compute_link_for_joined_pipes() ->
mst_stream_compute_config_limits() -> intel_dp_compute_config_limits() in
drivers/gpu/drm/i915/display/intel_dp.c, the MST path narrows
limits->link_config_filter to the single unfiltered max_config before
calling intel_dp_compute_m_n_ratio_limits():

drivers/gpu/drm/i915/display/intel_dp.c:intel_dp_compute_config_limits() {
	...
	if (is_mst || intel_dp->use_max_params) {
		struct intel_dp_link_caps_filter new_filter = INTEL_DP_LINK_CAPS_FILTER_NONE;
		struct intel_dp_link_config max_config;
		...
		if (!intel_dp_get_connector_max_link_config(connector, limits, &max_config))
			return false;

		if (!intel_dp_link_caps_filter_add(link_caps, &new_filter, &max_config))
			return false;

		limits->link_config_filter = new_filter;
	}

	if (!intel_dp_compute_m_n_ratio_limits(intel_dp, conn_state, crtc_state, limits))
		return false;
	...
}

On a DP 2.x MST topology supporting both 128b/132b UHBR rates (where symbol
clock is rate * 10 / 32, e.g. 312.5 MHz for UHBR10 or 421.875 MHz for
UHBR13.5) and 8b/10b rates (where symbol clock is rate / 10, e.g. 810 MHz
for HBR3), a high-pixel-clock mode can exceed the M/N ratio limit at
max_bw_config (such as 4xUHBR10) while still passing
intel_dp_can_support_m_n() at HBR3.

Wouldn't that allow mst_connector_mode_valid_ctx() to return MODE_OK for a
mode that then fails atomic check in intel_dp_compute_config_limits() with
-EINVAL because only max_config was retained in limits->link_config_filter?
Should mst_connector_mode_valid_ctx() either check
intel_dp_can_support_m_n() against max_link_clock, or should
intel_dp_compute_m_n_ratio_limits() run before selecting max_config in
intel_dp_compute_config_limits()?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261021071401.1161586-1-suraj.kandpal@intel.com?part=4

[PATCH v6 05/11] drm/i915/dp: Add M/N ratio check for DP link config

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Introduce intel_dp_check_m_n_ratio() to validate the computed link M/N
ratio against the maximum allowed value, and log it if the ratio exceeds
the limit.

The link config limits computed in the previous commits only restrict
the configurations that may be selected; this catches anything that
still slips through.

Log it rather than warn about it: the link config filter already
excludes the configurations violating the limit, so the only way to get
here is with link parameters forced through debugfs, which are applied
after that filter. A user triggerable drm_WARN() with its backtrace
would be out of proportion for that.

For MST the check goes after the bpp loop rather than inside it. The
link M/N is computed from the pixel clock and the link symbol clock, so
it does not depend on the bpp being tried and the result is the same on
every iteration.

v2:
-Use the platform specific ratio limit. (Wa_14014191401)
-Use the MSO adjusted pixel clock when predicting the ratio, matching
what the link M/N is actually computed from. (Imre)
-Drop the check from ilk_fdi_compute_config(): it was passing dp_m_n
rather than the fdi_m_n it had just computed, and an FDI link cannot get
anywhere near the ratio limit anyway.
v3:
-Check the ratio once after the MST bpp loop instead of on every
iteration, the result does not depend on the bpp. (Sashiko)
-Log instead of warning, since the link config filter already excludes
these configurations and only forced link parameters can reach it.
(Sashiko)
v4:
-Move the MSO adjusted pixel clock to the commit adding the prediction,
so that one is correct on its own. (Mitul)
-Reuse intel_dp_link_m_n_ratio() instead of open coding the ratio.
(Mitul)
-Drop the m_n and link_n checks, neither can be NULL or 0. Make the
parameters const and move it next to intel_dp_can_support_m_n().
(Mitul)
-Drop the check on dp_m2_n2, the dp_m_n one already covers it. (Mitul)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c     | 17 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h     |  4 ++++
 drivers/gpu/drm/i915/display/intel_dp_mst.c |  2 ++
 3 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f3a79ae49b18..8ef6b4c4fc8e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1299,6 +1299,21 @@ intel_dp_can_support_m_n(struct intel_display *display,
 	return m_n_ratio <= max_m_n_ratio;
 }
 
+void intel_dp_check_m_n_ratio(const struct intel_crtc_state *crtc_state,
+			      const struct intel_link_m_n *m_n)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
+	int m_n_ratio;
+
+	m_n_ratio = intel_dp_link_m_n_ratio(m_n->link_m, m_n->link_n);
+
+	if (m_n_ratio > max_m_n_ratio)
+		drm_dbg_kms(display->drm,
+			    "Link M/N ratio (%d) exceeds max allowed (%d)\n",
+			    m_n_ratio, max_m_n_ratio);
+}
+
 static int intel_dp_mso_pixel_clock(struct intel_dp *intel_dp, int pixel_clock)
 {
 	if (!intel_dp->mso_link_count)
@@ -3755,6 +3770,8 @@ intel_dp_compute_config(struct intel_atomic_state *state,
 				       pipe_config->port_clock,
 				       intel_dp_bw_fec_overhead(pipe_config->fec_enable),
 				       &pipe_config->dp_m_n);
+
+		intel_dp_check_m_n_ratio(pipe_config, &pipe_config->dp_m_n);
 	}
 
 	ret = intel_dp_compute_min_hblank(pipe_config, conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index aa58833a405b..1e3da678c9b6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -26,6 +26,7 @@ struct intel_display;
 struct intel_dp;
 struct intel_dp_link_config;
 struct intel_encoder;
+struct intel_link_m_n;
 
 struct link_config_limits {
 	struct intel_dp_link_caps_filter link_config_filter;
@@ -244,4 +245,7 @@ bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock);
 int intel_dp_link_init(struct intel_dp *intel_dp);
 void intel_dp_link_cleanup(struct intel_dp *intel_dp);
 
+void intel_dp_check_m_n_ratio(const struct intel_crtc_state *crtc_state,
+			      const struct intel_link_m_n *m_n);
+
 #endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index f00edfb66a10..8db84975f36b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -429,6 +429,8 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
 		return slots;
 	}
 
+	intel_dp_check_m_n_ratio(crtc_state, &crtc_state->dp_m_n);
+
 	if (!dsc)
 		crtc_state->pipe_bpp = fxp_q4_to_int(bpp_x16);
 	else
-- 
2.34.1

[PATCH v6 06/11] drm/i915/display: Add bits for link_n_extended for DISPLAY >= 14

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

LINK_N register has bits 31:24 for extended link N value used for
HDMI2.1 and for an alternate mode of operation of DP TG DDA.

Add support for these extra bits.

For displays with version 14 or higher, PIPE_LINK_N1_EXTENDED_MASK
(bits 31:24) is used to handle the extended link N bits. For older
platforms, DATA_LINK_M_N_MASK (bits 23:0) is used to handle the
standard link N bits. This distinction ensures clarity and maintains
the semantics for platforms that support the extended bits. In
subsequent changes the logic is updated to conditionally apply the
extended link N bits.

v2: Drop extra link_n_ext member. (Jani)
v3: Avoid link_n_ext in set_m_n helper. (Jani)
v4: Rebase, and update commit message.
v5: Drop a stale changelog entry, the DISPLAY_VER split here is
    intentional. (Sashiko)

Bspec: 50488
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c   | 18 ++++++++++++++++--
 .../gpu/drm/i915/display/intel_display_regs.h  |  2 ++
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f74e7ddf0e41..461b81bf8341 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2720,14 +2720,22 @@ void intel_set_m_n(struct intel_display *display,
 		   intel_reg_t data_m_reg, intel_reg_t data_n_reg,
 		   intel_reg_t link_m_reg, intel_reg_t link_n_reg)
 {
+	u32 link_n = m_n->link_n;
+
 	intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
 	intel_de_write(display, data_n_reg, m_n->data_n);
 	intel_de_write(display, link_m_reg, m_n->link_m);
+
+	if (DISPLAY_VER(display) >= 14)
+		link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
+	else
+		link_n &= DATA_LINK_M_N_MASK;
+
 	/*
 	 * On BDW+ writing LINK_N arms the double buffered update
 	 * of all the M/N registers, so it must be written last.
 	 */
-	intel_de_write(display, link_n_reg, m_n->link_n);
+	intel_de_write(display, link_n_reg, link_n);
 }
 
 bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
@@ -3484,7 +3492,13 @@ void intel_get_m_n(struct intel_display *display,
 		   intel_reg_t link_m_reg, intel_reg_t link_n_reg)
 {
 	m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK;
-	m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK;
+	m_n->link_n = intel_de_read(display, link_n_reg);
+
+	if (DISPLAY_VER(display) >= 14)
+		m_n->link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
+	else
+		m_n->link_n &= DATA_LINK_M_N_MASK;
+
 	m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK;
 	m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK;
 	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 2f509bd06557..983a0d9dcb9c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1190,6 +1190,8 @@
 
 #define _PIPEA_LINK_N1		0x60044
 #define _PIPEB_LINK_N1		0x61044
+#define  PIPE_LINK_N1_EXTENDED_MASK	REG_GENMASK(31, 24)
+#define  PIPE_LINK_N1_EXTENDED(val)	REG_FIELD_PREP(PIPE_LINK_N1_EXTENDED_MASK, (val))
 #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
 
 #define _PIPEA_LINK_M2		0x60048
-- 
2.34.1

[PATCH v6 07/11] drm/i915/display_wa: Add support for Wa_14021768792

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Some BMG ultrajoiner configurations require support for Link M/N ratios
between 10.0 and 15.0. This range is not natively supported and requires
a workaround.

Wa_14021768792 enables this support by utilizing HDMI_EMP_DATA,
CHICKEN_TRANS and the extended bits in the LINK_N register.

Add the necessary logic to enable the workaround on applicable platforms.
The underlying mechanism comes from the display C0,
so it is gated on display stepping C0 and later.

v2:
-Don't include i915_drv.h and don't use struct drm_i915_private under
display/. Use display->platform.battlemage, which names the affected
platform directly, instead of IS_DGFX() combined with a display version
check. (Jani)
-Rebase on the reworked display WA framework, where the condition goes
directly into the __intel_display_wa() switch.

Bspec: 49266
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_wa.c | 9 +++++++++
 drivers/gpu/drm/i915/display/intel_display_wa.h | 1 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index 91395076e903..e6f84dffdeb7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -102,6 +102,15 @@ bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa,
 		return DISPLAY_VERx100(display) == 3000 ||
 			DISPLAY_VERx100(display) == 2000 ||
 			DISPLAY_VERx100(display) == 1401;
+	/*
+	 * Wa_14021768792:
+	 * Fixes: Limitation of Link M/N ratio > 10 for specific Xe2HPD platforms.
+	 * Workaround: Use HDMI_EMP_DATA, CHICKEN_BITs and extended bits in LINK_N
+	 * registers to support LINK M/N ratios from > 10 but < 15.
+	 */
+	case INTEL_DISPLAY_WA_14021768792:
+		return display->platform.battlemage &&
+			IS_DISPLAY_STEP(display, STEP_C0, STEP_FOREVER);
 	case INTEL_DISPLAY_WA_14025769978:
 		return DISPLAY_VER(display) == 35;
 	case INTEL_DISPLAY_WA_14026643300:
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h
index f41e58d1d6e7..0b43c2144dcc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.h
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
@@ -34,6 +34,7 @@ enum intel_display_wa {
 	INTEL_DISPLAY_WA_14014191401,
 	INTEL_DISPLAY_WA_14016740474,
 	INTEL_DISPLAY_WA_14020863754,
+	INTEL_DISPLAY_WA_14021768792,
 	INTEL_DISPLAY_WA_14025769978,
 	INTEL_DISPLAY_WA_14026643300,
 	INTEL_DISPLAY_WA_15013987218,
-- 
2.34.1

[PATCH v6 08/11] drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

To support a Link M/N ratio between 10.0 and 15.0, for some BMG
ultrajoiner cases we need Wa_14021768792.

To bypass the hardware limitation within the Timing Generator DDA
(TGDDA), we need to program the LINKM and LINKN registers as defined in
the WA. Along with this we also need the relevant bits in HDMI_EMP_DATA
and CHICKEN_TRANS.

Add the bits for the WA and a new member 'bypass_m_n_ratio_limit' to
track if we need to bypass the Link M/N ratio limit in the
intel_link_m_n structure.

Per Bspec the extended LINK_N field is two nibbles: bits 27:24 hold
INT(Link M / Link N) and bits 31:28 hold CEIL(Link M / Link N).

The workaround is limited to transcoder A. Check the transcoder rather
than the pipe: for a single pipe the two are the same, but the joiner
secondaries read the M/N back through the primary's transcoder, so a
pipe check would have them report the workaround as not applied while
their state, copied from the primary, has it applied.

CHICKEN_TRANS and HDMI_EMP_DATA are programmed before LINK_N, since
writing LINK_N arms the double buffered update of the M/N registers, and
all of the programming has to be done before the transcoder is enabled.
Both are also explicitly cleared when the mechanism is not in use, so
that state cannot leak from a previous modeset.

Only bypass_m_n_ratio_limit is compared by the state checker, not the
ratio integer and fraction themselves. That is deliberate: both are
derived from Link M and Link N, which are compared already, so the thing
worth verifying is whether the workaround ended up being applied or not.

Unlike the rest of the M/N registers, CHICKEN_TRANS and HDMI_EMP_DATA
are not double buffered, so the flag has to be compared outside the
fastset exemption that PIPE_CONF_CHECK_M_N() has for update_m_n.
Otherwise a seamless M/N update could switch the DDA out of the
workaround on a live transcoder, with the Link M/N values only following
at the next MSA.

v2:
-Drop the drm_WARN_ON() on the extended LINK_N field in intel_get_m_n():
it is derived from Link M and Link N, so the state checker comparison of
those and of bypass_m_n_ratio_limit already covers it. (Sashiko)
-Compare bypass_m_n_ratio_limit unconditionally, so that a change to it
forces a full modeset instead of being applied during a seamless M/N
fastset. (Sashiko)
v3:
-Check for transcoder A instead of pipe A, so that the joiner secondaries
read the flag back the same as the primary. (Mitul)
-Drop bypass_m_n_ratio_limit from intel_compare_link_m_n(), the
unconditional PIPE_CONF_CHECK_BOOL() already compares it. (Mitul)
-Print bypass_m_n_ratio_limit in the crtc state dump. (Mitul)

Bspec: 49266
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 .../drm/i915/display/intel_crtc_state_dump.c  |  6 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 82 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_display.h  |  2 +
 .../gpu/drm/i915/display/intel_display_regs.h | 10 +++
 .../drm/i915/display/intel_display_types.h    |  2 +
 5 files changed, 99 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 92675a88b969..c51b21222dc6 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -36,10 +36,12 @@ intel_dump_m_n_config(struct drm_printer *p,
 		      const char *id, unsigned int lane_count,
 		      const struct intel_link_m_n *m_n)
 {
-	drm_printf(p, "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n",
+	drm_printf(p,
+		   "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u, bypass_m_n_ratio_limit: %s\n",
 		   id, lane_count,
 		   m_n->data_m, m_n->data_n,
-		   m_n->link_m, m_n->link_n, m_n->tu);
+		   m_n->link_m, m_n->link_n, m_n->tu,
+		   str_yes_no(m_n->bypass_m_n_ratio_limit));
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 461b81bf8341..ecc0e5ec181a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2715,6 +2715,15 @@ void intel_zero_m_n(struct intel_link_m_n *m_n)
 	m_n->tu = 1;
 }
 
+static u8 bmg_get_link_n_ext(const struct intel_link_m_n *m_n)
+{
+	if (!m_n->link_n)
+		return 0;
+
+	return PIPE_LINK_N1_EXT_INT(m_n->link_m / m_n->link_n) |
+		PIPE_LINK_N1_EXT_CEIL(DIV_ROUND_UP(m_n->link_m, m_n->link_n));
+}
+
 void intel_set_m_n(struct intel_display *display,
 		   const struct intel_link_m_n *m_n,
 		   intel_reg_t data_m_reg, intel_reg_t data_n_reg,
@@ -2726,7 +2735,9 @@ void intel_set_m_n(struct intel_display *display,
 	intel_de_write(display, data_n_reg, m_n->data_n);
 	intel_de_write(display, link_m_reg, m_n->link_m);
 
-	if (DISPLAY_VER(display) >= 14)
+	if (DISPLAY_VER(display) >= 14 && m_n->bypass_m_n_ratio_limit)
+		link_n |= PIPE_LINK_N1_EXTENDED(bmg_get_link_n_ext(m_n));
+	else if (DISPLAY_VER(display) >= 14)
 		link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
 	else
 		link_n &= DATA_LINK_M_N_MASK;
@@ -2747,6 +2758,26 @@ bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
 	return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview;
 }
 
+static void bmg_enhanced_tgdda_write(struct intel_crtc *crtc,
+				     enum transcoder transcoder,
+				     const struct intel_link_m_n *m_n)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	bool enable = m_n->bypass_m_n_ratio_limit && m_n->link_n;
+	u32 link_m_frac = enable ? m_n->link_m % m_n->link_n : 0;
+
+	if (!intel_display_wa(display, INTEL_DISPLAY_WA_14021768792))
+		return;
+
+	intel_de_rmw(display, HDMI_EMP_DATA(display, transcoder),
+		     HDMI_EMP_DATA_LINK_M_FRAC_MASK,
+		     REG_FIELD_PREP(HDMI_EMP_DATA_LINK_M_FRAC_MASK, link_m_frac));
+
+	intel_de_rmw(display, CHICKEN_TRANS(display, transcoder),
+		     DP_ENHANCED_TGDDA_ENABLE,
+		     enable ? DP_ENHANCED_TGDDA_ENABLE : 0);
+}
+
 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
 				    enum transcoder transcoder,
 				    const struct intel_link_m_n *m_n)
@@ -2754,6 +2785,8 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
 	struct intel_display *display = to_intel_display(crtc);
 	enum pipe pipe = crtc->pipe;
 
+	bmg_enhanced_tgdda_write(crtc, transcoder, m_n);
+
 	if (DISPLAY_VER(display) >= 5)
 		intel_set_m_n(display, m_n,
 			      PIPE_DATA_M1(display, transcoder),
@@ -3504,6 +3537,49 @@ void intel_get_m_n(struct intel_display *display,
 	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;
 }
 
+bool intel_display_can_bypass_m_n_limit(struct intel_display *display,
+					int m_n_ratio,
+					enum transcoder transcoder)
+{
+	if (!intel_display_wa(display, INTEL_DISPLAY_WA_14021768792))
+		return false;
+
+	if (m_n_ratio > 15)
+		return false;
+
+	if (transcoder != TRANSCODER_A)
+		return false;
+
+	return true;
+}
+
+static void bmg_enhanced_tgdda_read(struct intel_crtc *crtc,
+				    enum transcoder transcoder,
+				    struct intel_link_m_n *m_n)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	u32 link_m_frac;
+	int m_n_ratio;
+
+	if (!m_n->link_n)
+		return;
+
+	m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
+
+	if (!intel_display_can_bypass_m_n_limit(display, m_n_ratio, transcoder))
+		return;
+
+	if (!(intel_de_read(display, CHICKEN_TRANS(display, transcoder)) &
+	      DP_ENHANCED_TGDDA_ENABLE))
+		return;
+
+	link_m_frac = REG_FIELD_GET(HDMI_EMP_DATA_LINK_M_FRAC_MASK,
+				    intel_de_read(display, HDMI_EMP_DATA(display, transcoder)));
+
+	if (link_m_frac == m_n->link_m % m_n->link_n)
+		m_n->bypass_m_n_ratio_limit = true;
+}
+
 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
 				    enum transcoder transcoder,
 				    struct intel_link_m_n *m_n)
@@ -3521,6 +3597,8 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
 		intel_get_m_n(display, m_n,
 			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
 			      PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
+
+	bmg_enhanced_tgdda_read(crtc, transcoder, m_n);
 }
 
 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
@@ -5445,6 +5523,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_M_N(dp_m2_n2);
 	}
 
+	PIPE_CONF_CHECK_BOOL(dp_m_n.bypass_m_n_ratio_limit);
+
 	PIPE_CONF_CHECK_X(output_types);
 
 	PIPE_CONF_CHECK_I(framestart_delay);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 404168f4213b..d53b7b4a80e7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -525,5 +525,7 @@ bool intel_scanout_needs_vtd_wa(struct intel_display *display);
 int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
 void intel_display_compute_link_m_n(u32 *link_m, u32 *link_n,
 				    int pixel_clock, int link_symbol_clock);
+bool intel_display_can_bypass_m_n_limit(struct intel_display *display,
+					int m_n_ratio, enum transcoder transcoder);
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 983a0d9dcb9c..bbdbc27629d7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -550,6 +550,11 @@
 #define _TRANS_MULT_B		0x6102c
 #define TRANS_MULT(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
 
+#define _HDMI_EMP_DATA_A	0x600d8
+#define _HDMI_EMP_DATA_B	0x610d8
+#define  HDMI_EMP_DATA_LINK_M_FRAC_MASK	REG_GENMASK(23, 0)
+#define HDMI_EMP_DATA(display, trans)	_MMIO_TRANS2((display), (trans), _HDMI_EMP_DATA_A)
+
 /* Hotplug control (945+ only) */
 #define PORT_HOTPLUG_EN(dev_priv)		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
 #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
@@ -1192,6 +1197,10 @@
 #define _PIPEB_LINK_N1		0x61044
 #define  PIPE_LINK_N1_EXTENDED_MASK	REG_GENMASK(31, 24)
 #define  PIPE_LINK_N1_EXTENDED(val)	REG_FIELD_PREP(PIPE_LINK_N1_EXTENDED_MASK, (val))
+#define  PIPE_LINK_N1_EXT_CEIL_MASK	REG_GENMASK(7, 4)
+#define  PIPE_LINK_N1_EXT_CEIL(val)	REG_FIELD_PREP(PIPE_LINK_N1_EXT_CEIL_MASK, (val))
+#define  PIPE_LINK_N1_EXT_INT_MASK	REG_GENMASK(3, 0)
+#define  PIPE_LINK_N1_EXT_INT(val)	REG_FIELD_PREP(PIPE_LINK_N1_EXT_INT_MASK, (val))
 #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
 
 #define _PIPEA_LINK_M2		0x60048
@@ -1710,6 +1719,7 @@
 #define   PSR2_ADD_VERTICAL_LINE_COUNT	REG_BIT(15)
 #define   DP_FEC_BS_JITTER_WA		REG_BIT(15)
 #define   PSR2_VSC_ENABLE_PROG_HEADER	REG_BIT(12)
+#define   DP_ENHANCED_TGDDA_ENABLE	REG_BIT(11)
 #define   DP_DSC_INSERT_SF_AT_EOL_WA	REG_BIT(4)
 #define   HDCP_LINE_REKEY_DISABLE	REG_BIT(0)
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8f9fb2603638..d0748837ce97 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -985,6 +985,8 @@ struct intel_link_m_n {
 	u32 data_n;
 	u32 link_m;
 	u32 link_n;
+	/* Wa_14021768792 for linkm/n ratio > 10 */
+	bool bypass_m_n_ratio_limit;
 };
 
 struct intel_csc_matrix {
-- 
2.34.1

[PATCH v6 09/11] drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n ratio > 10

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Handle the bypass logic for the M/N ratio limit for DP.
Calculate the M/N ratio, check if it can bypass the limit, and set the
appropriate flags for the workaround.

v2:
-Restrict the workaround to 128b/132b links.
-Clear bypass_m_n_ratio_limit on entry, so a rejected link rate cannot
leave it set for the rate that gets used. (Sashiko)
v3:
-Rebase on the reworked M/N ratio check, which no longer checks m_n and
link_n. m_n is no longer const, as the flag is set through it. (Mitul)
-Pass the cpu transcoder to intel_display_can_bypass_m_n_limit() instead
of the pipe. (Mitul)

Bspec: 49266
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 28 ++++++++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_dp.h |  2 +-
 2 files changed, 24 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8ef6b4c4fc8e..8e6ba5b9fde6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1300,18 +1300,32 @@ intel_dp_can_support_m_n(struct intel_display *display,
 }
 
 void intel_dp_check_m_n_ratio(const struct intel_crtc_state *crtc_state,
-			      const struct intel_link_m_n *m_n)
+			      struct intel_link_m_n *m_n)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
 	int m_n_ratio;
 
+	m_n->bypass_m_n_ratio_limit = false;
+
 	m_n_ratio = intel_dp_link_m_n_ratio(m_n->link_m, m_n->link_n);
 
-	if (m_n_ratio > max_m_n_ratio)
+	if (m_n_ratio <= max_m_n_ratio)
+		return;
+
+	if (intel_dp_is_uhbr(crtc_state) &&
+	    intel_display_can_bypass_m_n_limit(display, m_n_ratio,
+					       crtc_state->cpu_transcoder)) {
+		m_n->bypass_m_n_ratio_limit = true;
 		drm_dbg_kms(display->drm,
-			    "Link M/N ratio (%d) exceeds max allowed (%d)\n",
-			    m_n_ratio, max_m_n_ratio);
+			    "Bypassing Link_m/Link_n ratio limit (ratio %d)\n",
+			    m_n_ratio);
+		return;
+	}
+
+	drm_dbg_kms(display->drm,
+		    "Link M/N ratio (%d) exceeds max allowed (%d)\n",
+		    m_n_ratio, max_m_n_ratio);
 }
 
 static int intel_dp_mso_pixel_clock(struct intel_dp *intel_dp, int pixel_clock)
@@ -3393,6 +3407,9 @@ static bool can_enable_drrs(struct intel_connector *connector,
 	if (pipe_config->vrr.enable)
 		return false;
 
+	if (pipe_config->dp_m_n.bypass_m_n_ratio_limit)
+		return false;
+
 	/*
 	 * DRRS and PSR can't be enable together, so giving preference to PSR
 	 * as it allows more power-savings by complete shutting down display,
@@ -3427,7 +3444,8 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
 	 * FIXME all joined pipes share the same transcoder.
 	 * Need to account for that when updating M/N live.
 	 */
-	if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes)
+	if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes &&
+	    !pipe_config->dp_m_n.bypass_m_n_ratio_limit)
 		pipe_config->update_m_n = true;
 
 	if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 1e3da678c9b6..c834d90a1f81 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -246,6 +246,6 @@ int intel_dp_link_init(struct intel_dp *intel_dp);
 void intel_dp_link_cleanup(struct intel_dp *intel_dp);
 
 void intel_dp_check_m_n_ratio(const struct intel_crtc_state *crtc_state,
-			      const struct intel_link_m_n *m_n);
+			      struct intel_link_m_n *m_n);
 
 #endif /* __INTEL_DP_H__ */
-- 
2.34.1

[PATCH v6 10/11] drm/i915/dp: Extend intel_dp_can_support_m_n() for BMG M/N bypass

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

On BMG platforms, the standard M/N ratio limit of 10 can be bypassed
under specific conditions, as permitted by hardware capabilities.

Modify the helper intel_dp_can_support_m_n() to account for this by
checking whether the platform supports bypassing the limit. The
workaround is only intended for 128b/132b links, so restrict it to
those.

During the mode_valid phase, the check assumes that TRANSCODER_A will be
used, to allow the mode where the M/N ratio is within the limits for the
workaround.

v2:
-Keep the helper static: the MST mode_valid now goes through the shared
intel_dp_mode_valid_m_n() rather than calling it directly, so it no
longer needs to be exported.
v3:
-Use the cpu transcoder instead of the pipe, following the change to
intel_display_can_bypass_m_n_limit(). (Mitul)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8e6ba5b9fde6..045524994d85 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1285,9 +1285,11 @@ static int intel_dp_link_m_n_ratio(u32 link_m, u32 link_n)
 
 static bool
 intel_dp_can_support_m_n(struct intel_display *display,
+			 const struct intel_crtc_state *crtc_state,
 			 int pixel_clock, int link_rate)
 {
 	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
+	enum transcoder cpu_transcoder = TRANSCODER_A;
 	u32 link_m, link_n;
 	int m_n_ratio;
 
@@ -1296,7 +1298,16 @@ intel_dp_can_support_m_n(struct intel_display *display,
 
 	m_n_ratio = intel_dp_link_m_n_ratio(link_m, link_n);
 
-	return m_n_ratio <= max_m_n_ratio;
+	if (m_n_ratio <= max_m_n_ratio)
+		return true;
+
+	if (!drm_dp_is_uhbr_rate(link_rate))
+		return false;
+
+	if (crtc_state)
+		cpu_transcoder = crtc_state->cpu_transcoder;
+
+	return intel_display_can_bypass_m_n_limit(display, m_n_ratio, cpu_transcoder);
 }
 
 void intel_dp_check_m_n_ratio(const struct intel_crtc_state *crtc_state,
@@ -1386,7 +1397,7 @@ bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock)
 	intel_dp_link_caps_iter_start(&iter, intel_dp->link.caps, order,
 				      INTEL_DP_LINK_CAPS_FILTER_ALL);
 	for_each_dp_link_config(&iter, &link_config) {
-		if (intel_dp_can_support_m_n(display, m_n_pixel_clock,
+		if (intel_dp_can_support_m_n(display, NULL, m_n_pixel_clock,
 					     link_config.rate)) {
 			found = true;
 
@@ -2775,7 +2786,8 @@ intel_dp_compute_m_n_ratio_limits(struct intel_dp *intel_dp,
 
 	intel_dp_link_caps_iter_start(&iter, link_caps, order, limits->link_config_filter);
 	for_each_dp_link_config(&iter, &link_config) {
-		if (!intel_dp_can_support_m_n(display, pixel_clock, link_config.rate))
+		if (!intel_dp_can_support_m_n(display, crtc_state, pixel_clock,
+					      link_config.rate))
 			continue;
 
 		intel_dp_link_caps_filter_add(link_caps, &new_filter, &link_config);
-- 
2.34.1

[PATCH v6 11/11] drm/i915/dp: Bump the max Link M/N ratio to 22 for DISPLAY_VER >= 35

[Suraj Kandpal]

Starting Xe3p max M/N ratio has been increased to 22.

Bspec: 68922
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 045524994d85..5864e33456a7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1272,6 +1272,9 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
 static int
 intel_dp_get_max_m_n_ratio(struct intel_display *display)
 {
+	if (DISPLAY_VER(display) >= 35)
+		return 22;
+
 	if (intel_display_wa(display, INTEL_DISPLAY_WA_14014191401))
 		return 4;
 
-- 
2.34.1

[PATCH v6 00/11] Implement Wa_14021768792 to bypass m_n ratio limit

[Suraj Kandpal]

For Platforms that support higher link rates, there is a limitation on
Link M /Link N ratio.
If the CEILING( Link M / Link N ) ratio is greater than 10.0, then
hardware cannot support the given resolution / refresh rate at the given
configuration.
For BMG Wa_14021768792 helps to bypass this limitation and allows it to
support the ratio till 15.0.

This series adds the missing restrictions for earlier platforms and adds
the Wa_14021768792 for BMG as per Bspec:49266

Ankit Nautiyal (8):
  drm/i915/display: Add helper to compute link M/N ratio for reuse
  drm/i915/dp_mst: Limit M/N ratio for MST
  drm/i915/dp: Add M/N ratio check for DP link config
  drm/i915/display: Add bits for link_n_extended for DISPLAY >= 14
  drm/i915/display_wa: Add support for Wa_14021768792
  drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10
  drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n
    ratio > 10
  drm/i915/dp: Extend intel_dp_can_support_m_n() for BMG M/N bypass

Suraj Kandpal (3):
  drm/i915/dp: Limit M/N ratio for DP
  drm/i915/display_wa: Add support for Wa_14014191401
  drm/i915/dp: Bump the max Link M/N ratio to 22 for DISPLAY_VER >= 35

 .../drm/i915/display/intel_crtc_state_dump.c  |   6 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 113 +++++++++++-
 drivers/gpu/drm/i915/display/intel_display.h  |   4 +
 .../gpu/drm/i915/display/intel_display_regs.h |  12 ++
 .../drm/i915/display/intel_display_types.h    |   2 +
 .../gpu/drm/i915/display/intel_display_wa.c   |  11 ++
 .../gpu/drm/i915/display/intel_display_wa.h   |   2 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 167 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   6 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   7 +
 10 files changed, 321 insertions(+), 9 deletions(-)

-- 
2.34.1

[PATCH v6 04/11] drm/i915/dp_mst: Limit M/N ratio for MST

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

The hardware does not support DisplayPort configurations where the
ceiling of the Link M/Link N ratio exceeds the limit. Enforce this
constraint for MST as well.

The compute config path needs no change: MST goes through
intel_dp_compute_config_limits() too, so the link config filter set up
there already excludes the configurations violating the ratio limit, and
MST fails there if none is left.

What is still missing is pruning such modes, so add the check to
mst_connector_mode_valid_ctx(), reusing the helper the SST mode_valid
uses. It walks the link configurations and only rejects the mode if none
of them can satisfy the ratio, rather than evaluating it at a single
link rate.

v2:
-Drop the checks in the MST link config helpers, redundant now that the
constraint is applied while computing the link config limits. (Imre)
-Share the mode_valid helper with SST instead of evaluating the ratio at
one link rate, since the link symbol clock is not monotonic in the link
rate and there is no single best case configuration.
v3:
-Now that intel_dp_mode_valid_m_n checks for all configs just call
that (Sashiko)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Co-developed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 7023619aaaba..f00edfb66a10 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1565,6 +1565,11 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 					   min_link_bpp_x16,
 					   bw_overhead_flags);
 
+	if (!intel_dp_mode_valid_m_n(intel_dp, mode->clock)) {
+		*status = MODE_CLOCK_HIGH;
+		return 0;
+	}
+
 	/*
 	 * TODO:
 	 * - Also check if compression would allow for the mode
-- 
2.34.1