[PATCH 00/10] drm/xe: Clean up adjust_idledly() and implement Wa_16031259911

[PATCH 00/10] drm/xe: Clean up adjust_idledly() and implement Wa_16031259911

[Gustavo Sousa]

There is a new workaround, namely Wa_16031259911, to be added to the
xe driver that applies to graphics IP versions 35.10 and 35.11.  The
workaround is similar to existing ones that apply adjustments to
RING_IDLEDLY.

The current implementation can be improved though: adjust_idledly()
can be cleaned up and refactored to make the code easier to follow
sequentially as well as to add new workarounds (such as
Wa_16031259911); the GuC ADS regset accounting has a subtle issue
where the addition of RING_IDLEDLY is not accounted for.

This series addresses those issues first and then adds the
implementation of Wa_16031259911 as the final step.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
Gustavo Sousa (10):
      drm/xe: Bail from adjust_idledly() if in VF mode
      drm/xe: Sync Wa_16023105232 in xe_was to match OOB rule
      drm/xe: Use picosecond as common unit in adjust_idledly()
      drm/xe: Factor out {min,max}_idledly_ps in adjust_idledly()
      drm/xe: Bail from adjust_idledly() if no applicable workaround
      drm/xe: Drop early and redundant workaround checks in adjust_idledly()
      drm/xe: Drop comment about MAXCNT when calling adjust_idledly()
      drm/xe/guc: Increment regset size for Wa_1607983814 inside hwe loop
      drm/xe/guc: Increment regset size for RING_IDLEDLY workarounds
      drm/xe: Implement Wa_16031259911

 drivers/gpu/drm/xe/xe_guc_ads.c    |  16 ++--
 drivers/gpu/drm/xe/xe_hw_engine.c  | 153 +++++++++++++++++--------------------
 drivers/gpu/drm/xe/xe_wa.c         |   5 +-
 drivers/gpu/drm/xe/xe_wa_oob.rules |   6 +-
 4 files changed, 89 insertions(+), 91 deletions(-)
---
base-commit: a4c732aca52a51c32227b9a9a1364e1e533d275c
change-id: 20261021-wa_16031259911-3a83c69d8570

Best regards,
--  
Gustavo Sousa <gustavo.sousa@intel.com>

[PATCH 01/10] drm/xe: Bail from adjust_idledly() if in VF mode

[Gustavo Sousa]

Both Wa_14025941587 and Wa_16023105232 apply adjustments to
RING_IDLEDLY and take different approaches to avoid SRIOV VF mode.

Let's converge them into a consistent approach.  Since
adjust_idledly() should avoid SRIOV VF irrespective of what
workarounds are enabled, choose to add an early return in that
function instead of having each related workaround add
FUNC(xe_rtp_match_not_sriov_vf) to their rules.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_engine.c  | 6 ++++--
 drivers/gpu/drm/xe/xe_wa_oob.rules | 4 ++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 55ee0c892c1e..50e8c5103bdc 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -611,8 +611,10 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 	bool wa_applied = false;
 	bool clamped_below_maxcnt = false;
 
-	if ((!IS_SRIOV_VF(gt_to_xe(gt)) && XE_GT_WA(gt, 16023105232)) ||
-	    XE_GT_WA(gt, 14025941587)) {
+	if (IS_SRIOV_VF(gt_to_xe(gt)))
+		return;
+
+	if (XE_GT_WA(gt, 16023105232) || XE_GT_WA(gt, 14025941587)) {
 		u32 mincnt_idledly_ns = 5000;
 
 		/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index f35181fc4e49..6a1d5250ba1b 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -73,6 +73,6 @@
 16029897822	MEDIA_VERSION(3500)
 		GRAPHICS_VERSION(3510)
 14027054324	GRAPHICS_VERSION(3511)
-14025941587	GRAPHICS_VERSION_RANGE(2001, 3511), FUNC(xe_rtp_match_not_sriov_vf)
-		MEDIA_VERSION_RANGE(1301, 3503), FUNC(xe_rtp_match_not_sriov_vf)
+14025941587	GRAPHICS_VERSION_RANGE(2001, 3511)
+		MEDIA_VERSION_RANGE(1301, 3503)
 16030224309	GRAPHICS_VERSION(3510)

-- 
2.56.0

[PATCH 02/10] drm/xe: Sync Wa_16023105232 in xe_was to match OOB rule

[Gustavo Sousa]

Wa_16023105232 was extended in xe_wa_oob.rules to match extra IP
releases while the respective entry in xe_was[] was overlooked.
Update the latter to be in sync with the former.

Also add comments in the code so that we don't forget to update both
places if new IP versions are added.

Fixes: c96e0df4e9f5 ("drm/xe/xe3: Add support for media IP version 30.02")
Fixes: 4fde66699f1c ("drm/xe/xe3: Add support for graphics IP versions 30.04 & 30.05")
Cc: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_wa.c         | 5 +++--
 drivers/gpu/drm/xe/xe_wa_oob.rules | 1 +
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index c94fe7753f9a..bbe1696a57bc 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -581,8 +581,9 @@ static const struct xe_rtp_table_sr engine_was = XE_RTP_TABLE_SR(
 	  XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE))
 	},
 	{ XE_RTP_NAME("16023105232"),
-	  XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3000), OR,
-		       GRAPHICS_VERSION_RANGE(2001, 3001)),
+	  /* IP versions need to be in sync with the respective entry in xe_wa_oob.rules. */
+	  XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3002), OR,
+		       GRAPHICS_VERSION_RANGE(2001, 3005)),
 	  XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE,
 			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
 	},
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index 6a1d5250ba1b..9be392bce969 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -44,6 +44,7 @@
 18013179988	GRAPHICS_VERSION(1255)
 		GRAPHICS_VERSION_RANGE(1270, 1274)
 1508761755	GRAPHICS_VERSION(1255)
+# IP versions need to be in sync with the respective entry in xe_wa.c.
 16023105232	GRAPHICS_VERSION_RANGE(2001, 3005)
 		MEDIA_VERSION_RANGE(1301, 3002)
 16026508708	GRAPHICS_VERSION_RANGE(1200, 3005)

-- 
2.56.0

[PATCH 03/10] drm/xe: Use picosecond as common unit in adjust_idledly()

[Gustavo Sousa]

Because gt->info.timestamp_base is given in picoseconds, we lose
precision when calculating the current idle delay in nanoseconds.
Let's avoid that by using picosecond as the common unit of time in
adjust_idledly().

A good side effect of this is that we avoid issuing some integer
divisions.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_engine.c | 53 +++++++++++++++++++--------------------
 1 file changed, 26 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 50e8c5103bdc..f8019fdf8257 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -596,17 +596,19 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
 	xe_reg_whitelist_process_engine(hwe);
 }
 
-static u32 idledly_floor_ticks(u32 idledly_ns, u32 idledly_units_ps)
+static u32 idledly_floor_ticks(u64 idledly_ps, u32 idledly_units_ps)
 {
-	return DIV_ROUND_DOWN_ULL((u64)idledly_ns * 1000, idledly_units_ps);
+	return DIV_ROUND_DOWN_ULL(idledly_ps, idledly_units_ps);
 }
 
 static void adjust_idledly(struct xe_hw_engine *hwe)
 {
 	struct xe_gt *gt = hwe->gt;
-	u32 idledly, idledly_hw, idledly_reg_val, maxcnt;
+	u32 idledly_reg_val, maxcnt_reg_val;
 	u32 idledly_units_ps = 8 * gt->info.timestamp_base;
-	u32 maxcnt_units_ns = 640;
+	u32 maxcnt_units_ps = 640000;
+	u64 idledly_ps, idledly_hw_ps;
+	u64 maxcnt_ps;
 	bool inhibit_switch = false;
 	bool wa_applied = false;
 	bool clamped_below_maxcnt = false;
@@ -615,29 +617,27 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 		return;
 
 	if (XE_GT_WA(gt, 16023105232) || XE_GT_WA(gt, 14025941587)) {
-		u32 mincnt_idledly_ns = 5000;
+		u32 mincnt_idledly_ps = 5000000;
 
 		/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
 		if (!idledly_units_ps)
 			return;
 
 		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
-		maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
-
 		inhibit_switch = idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED;
-		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
-		idledly = DIV_ROUND_CLOSEST_ULL((u64)idledly * idledly_units_ps, 1000);
-		idledly_hw = idledly;
-		maxcnt = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt);
-		maxcnt *= maxcnt_units_ns;
+		idledly_ps = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val) * idledly_units_ps;
+		idledly_hw_ps = idledly_ps;
+
+		maxcnt_reg_val = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
+		maxcnt_ps = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt_reg_val) * maxcnt_units_ps;
 
 		/*
 		 * Wa_14025941587 is applied before Wa_16023105232, which takes
 		 * priority if the two ever conflict (not expected in practice).
 		 */
 		if (XE_GT_WA(gt, 14025941587) &&
-		    idledly < mincnt_idledly_ns) {
-			idledly = mincnt_idledly_ns;
+		    idledly_ps < mincnt_idledly_ps) {
+			idledly_ps = mincnt_idledly_ps;
 			wa_applied = true;
 		}
 
@@ -649,11 +649,11 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 			}
 
 			/* Warn only on the value read from hardware. */
-			xe_gt_WARN_ON(gt, idledly_hw >= maxcnt);
+			xe_gt_WARN_ON(gt, idledly_hw_ps >= maxcnt_ps);
 
-			if (idledly >= maxcnt) {
+			if (idledly_ps >= maxcnt_ps) {
 				/* maxcnt may be 0 if IDLE_WAIT_TIME is unprogrammed. */
-				idledly = maxcnt ? maxcnt - 1 : 0;
+				idledly_ps = maxcnt_ps ? maxcnt_ps - 1 : 0;
 				clamped_below_maxcnt = true;
 				wa_applied = true;
 			}
@@ -668,10 +668,9 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 			 * Wa_14025941587 minimum survives tick quantization.
 			 */
 			if (clamped_below_maxcnt)
-				idledly_ticks = idledly_floor_ticks(idledly, idledly_units_ps);
+				idledly_ticks = idledly_floor_ticks(idledly_ps, idledly_units_ps);
 			else
-				idledly_ticks = DIV_ROUND_UP_ULL((u64)idledly * 1000,
-								 idledly_units_ps);
+				idledly_ticks = DIV_ROUND_UP_ULL(idledly_ps, idledly_units_ps);
 
 			/*
 			 * Tick quantization can still push the rounded-up value
@@ -679,17 +678,17 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 			 * priority even in that case.
 			 */
 			if (!clamped_below_maxcnt && XE_GT_WA(gt, 16023105232) &&
-			    (u64)idledly_ticks * idledly_units_ps >= (u64)maxcnt * 1000) {
-				xe_gt_dbg(gt, "idledly %s: %u ticks would exceed maxcnt=%u, so flooring\n",
-					  hwe->name, idledly_ticks, maxcnt);
-				idledly = maxcnt ? maxcnt - 1 : 0;
-				idledly_ticks = idledly_floor_ticks(idledly, idledly_units_ps);
+			    (u64)idledly_ticks * idledly_units_ps >= maxcnt_ps) {
+				xe_gt_dbg(gt, "idledly %s: %u ticks would exceed maxcnt=%llups, so flooring\n",
+					  hwe->name, idledly_ticks, maxcnt_ps);
+				idledly_ps = maxcnt_ps ? maxcnt_ps - 1 : 0;
+				idledly_ticks = idledly_floor_ticks(idledly_ps, idledly_units_ps);
 			}
 
 			idledly_reg_val &= ~IDLE_DELAY;
 			idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY, idledly_ticks);
-			xe_gt_dbg(gt, "idledly %s: set %u max=%u inh=%u ts=%u\n",
-				  hwe->name, idledly, maxcnt,
+			xe_gt_dbg(gt, "idledly %s: set %llups max=%llups inh=%u ts=%ups\n",
+				  hwe->name, idledly_ps, maxcnt_ps,
 				  !!inhibit_switch, gt->info.timestamp_base);
 			xe_mmio_write32(&gt->mmio,
 					RING_IDLEDLY(hwe->mmio_base),

-- 
2.56.0

[PATCH 04/10] drm/xe: Factor out {min,max}_idledly_ps in adjust_idledly()

[Gustavo Sousa]

The function adjust_idledly() currently does the following adjustments
to the IDLEDLY register:

- Wa_14025941587 defines a minimum value for the idle delay.

- Wa_16023105232 defines a maximum value for the idle delay and also
  unsets INHIBIT_SWITCH_UNTIL_PREEMPTED.

We have an upcoming workaround that will also define a minimum idle
delay.

Let's reorganize the logic in adjust_idledly() in a way to make it
easier to reason about and also easier to extend.

Do that by having the workaround-specific logic only responsible for
defining min_idledly_ps or max_idledly_ps, and then keeping the logic of
how to apply them to the register field (with the right rounding up or
down) separate.

This separation drops the helper function idledly_floor_ticks(), the
clamped_below_maxcnt variable, and the extra quantization check,
arguably making the code easier to follow.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_engine.c | 100 ++++++++++++++++----------------------
 1 file changed, 41 insertions(+), 59 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index f8019fdf8257..0c9b510e7cac 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -596,99 +596,81 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
 	xe_reg_whitelist_process_engine(hwe);
 }
 
-static u32 idledly_floor_ticks(u64 idledly_ps, u32 idledly_units_ps)
-{
-	return DIV_ROUND_DOWN_ULL(idledly_ps, idledly_units_ps);
-}
-
 static void adjust_idledly(struct xe_hw_engine *hwe)
 {
 	struct xe_gt *gt = hwe->gt;
-	u32 idledly_reg_val, maxcnt_reg_val;
+	u32 idledly_reg_val;
+	u32 idledly;
 	u32 idledly_units_ps = 8 * gt->info.timestamp_base;
-	u32 maxcnt_units_ps = 640000;
 	u64 idledly_ps, idledly_hw_ps;
-	u64 maxcnt_ps;
+	u64 min_idledly_ps = 0;
+	u64 max_idledly_ps = -1;
 	bool inhibit_switch = false;
 	bool wa_applied = false;
-	bool clamped_below_maxcnt = false;
 
 	if (IS_SRIOV_VF(gt_to_xe(gt)))
 		return;
 
 	if (XE_GT_WA(gt, 16023105232) || XE_GT_WA(gt, 14025941587)) {
-		u32 mincnt_idledly_ps = 5000000;
-
 		/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
 		if (!idledly_units_ps)
 			return;
 
 		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
 		inhibit_switch = idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED;
-		idledly_ps = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val) * idledly_units_ps;
+		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
+		idledly_ps = idledly * idledly_units_ps;
 		idledly_hw_ps = idledly_ps;
 
-		maxcnt_reg_val = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
-		maxcnt_ps = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt_reg_val) * maxcnt_units_ps;
-
-		/*
-		 * Wa_14025941587 is applied before Wa_16023105232, which takes
-		 * priority if the two ever conflict (not expected in practice).
-		 */
-		if (XE_GT_WA(gt, 14025941587) &&
-		    idledly_ps < mincnt_idledly_ps) {
-			idledly_ps = mincnt_idledly_ps;
-			wa_applied = true;
-		}
+		if (XE_GT_WA(gt, 14025941587))
+			min_idledly_ps = max(min_idledly_ps, 5000000);
 
 		if (XE_GT_WA(gt, 16023105232)) {
+			u32 maxcnt_units_ps = 640000;
+			u32 maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
+
+			max_idledly_ps = min_t(u64,
+					       max_idledly_ps,
+					       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
+
 			/* Clear the inhibit switch without disturbing a valid delay. */
 			if (inhibit_switch) {
 				idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
 				wa_applied = true;
 			}
+		}
 
-			/* Warn only on the value read from hardware. */
-			xe_gt_WARN_ON(gt, idledly_hw_ps >= maxcnt_ps);
+		/*
+		 * min_idledly_ps is applied before max_idledly_ps, which takes
+		 * priority if the two ever conflict (not expected in practice).
+		 */
+		if (idledly_ps < min_idledly_ps) {
+			idledly = DIV_ROUND_UP_ULL(min_idledly_ps, idledly_units_ps);
+			idledly_ps = idledly * idledly_units_ps;
+			wa_applied = true;
+		}
 
-			if (idledly_ps >= maxcnt_ps) {
-				/* maxcnt may be 0 if IDLE_WAIT_TIME is unprogrammed. */
-				idledly_ps = maxcnt_ps ? maxcnt_ps - 1 : 0;
-				clamped_below_maxcnt = true;
-				wa_applied = true;
+		if (idledly_ps >= max_idledly_ps) {
+			if (max_idledly_ps) {
+				idledly = DIV_ROUND_DOWN_ULL(max_idledly_ps - 1, idledly_units_ps);
+				idledly_ps = idledly * idledly_units_ps;
+			} else {
+				idledly = 0;
+				idledly_ps = 0;
 			}
+
+			wa_applied = true;
 		}
 
-		if (wa_applied) {
-			u32 idledly_ticks;
-
-			/*
-			 * Wa_16023105232 requires idledly < maxcnt, so floor
-			 * that clamp; otherwise round up to guarantee the
-			 * Wa_14025941587 minimum survives tick quantization.
-			 */
-			if (clamped_below_maxcnt)
-				idledly_ticks = idledly_floor_ticks(idledly_ps, idledly_units_ps);
-			else
-				idledly_ticks = DIV_ROUND_UP_ULL(idledly_ps, idledly_units_ps);
-
-			/*
-			 * Tick quantization can still push the rounded-up value
-			 * to/above maxcnt; re-floor here so Wa_16023105232 keeps
-			 * priority even in that case.
-			 */
-			if (!clamped_below_maxcnt && XE_GT_WA(gt, 16023105232) &&
-			    (u64)idledly_ticks * idledly_units_ps >= maxcnt_ps) {
-				xe_gt_dbg(gt, "idledly %s: %u ticks would exceed maxcnt=%llups, so flooring\n",
-					  hwe->name, idledly_ticks, maxcnt_ps);
-				idledly_ps = maxcnt_ps ? maxcnt_ps - 1 : 0;
-				idledly_ticks = idledly_floor_ticks(idledly_ps, idledly_units_ps);
-			}
+		/* Warn only if the value read from *hardware* exceeds the maximum. */
+		xe_gt_WARN_ON(gt, idledly_hw_ps >= max_idledly_ps);
 
+		if (wa_applied) {
 			idledly_reg_val &= ~IDLE_DELAY;
-			idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY, idledly_ticks);
-			xe_gt_dbg(gt, "idledly %s: set %llups max=%llups inh=%u ts=%ups\n",
-				  hwe->name, idledly_ps, maxcnt_ps,
+			idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY, idledly);
+
+			xe_gt_dbg(gt, "idledly %s: set %llups min=%llups max=%llups inh=%u ts=%ups\n",
+				  hwe->name, idledly_ps, min_idledly_ps, max_idledly_ps,
 				  !!inhibit_switch, gt->info.timestamp_base);
 			xe_mmio_write32(&gt->mmio,
 					RING_IDLEDLY(hwe->mmio_base),

-- 
2.56.0

[PATCH 05/10] drm/xe: Bail from adjust_idledly() if no applicable workaround

[Gustavo Sousa]

Re-organize adjust_idledly() so that we return and avoid touching the
hardware if no applicable workaround was found.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_engine.c | 32 +++++++++++++++++++-------------
 1 file changed, 19 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 0c9b510e7cac..9f0fd10afd4e 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -605,7 +605,7 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 	u64 idledly_ps, idledly_hw_ps;
 	u64 min_idledly_ps = 0;
 	u64 max_idledly_ps = -1;
-	bool inhibit_switch = false;
+	bool clear_inhibit_switch = false;
 	bool wa_applied = false;
 
 	if (IS_SRIOV_VF(gt_to_xe(gt)))
@@ -616,12 +616,6 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 		if (!idledly_units_ps)
 			return;
 
-		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
-		inhibit_switch = idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED;
-		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
-		idledly_ps = idledly * idledly_units_ps;
-		idledly_hw_ps = idledly_ps;
-
 		if (XE_GT_WA(gt, 14025941587))
 			min_idledly_ps = max(min_idledly_ps, 5000000);
 
@@ -633,13 +627,24 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 					       max_idledly_ps,
 					       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
 
-			/* Clear the inhibit switch without disturbing a valid delay. */
-			if (inhibit_switch) {
-				idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
-				wa_applied = true;
-			}
+			clear_inhibit_switch = true;
 		}
 
+		/* No applicable workaround found. */
+		if (min_idledly_ps == 0 && max_idledly_ps == -1 && !clear_inhibit_switch)
+			return;
+
+		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
+
+		if (clear_inhibit_switch && idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED) {
+			idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
+			wa_applied = true;
+		}
+
+		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
+		idledly_ps = idledly * idledly_units_ps;
+		idledly_hw_ps = idledly_ps;
+
 		/*
 		 * min_idledly_ps is applied before max_idledly_ps, which takes
 		 * priority if the two ever conflict (not expected in practice).
@@ -671,7 +676,8 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 
 			xe_gt_dbg(gt, "idledly %s: set %llups min=%llups max=%llups inh=%u ts=%ups\n",
 				  hwe->name, idledly_ps, min_idledly_ps, max_idledly_ps,
-				  !!inhibit_switch, gt->info.timestamp_base);
+				  !!(idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED),
+				  gt->info.timestamp_base);
 			xe_mmio_write32(&gt->mmio,
 					RING_IDLEDLY(hwe->mmio_base),
 					idledly_reg_val);

-- 
2.56.0

[PATCH 06/10] drm/xe: Drop early and redundant workaround checks in adjust_idledly()

[Gustavo Sousa]

With the latest change, adjust_idledly() now only touches hardware
when necessary and has workaround-specific logic well scoped into
individual "if" statements.  The early workaround checks are now
redundant and can be dropped.  Do that.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_engine.c | 108 +++++++++++++++++++-------------------
 1 file changed, 53 insertions(+), 55 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 9f0fd10afd4e..ffd6ef9f96f4 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -611,77 +611,75 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 	if (IS_SRIOV_VF(gt_to_xe(gt)))
 		return;
 
-	if (XE_GT_WA(gt, 16023105232) || XE_GT_WA(gt, 14025941587)) {
-		/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
-		if (!idledly_units_ps)
-			return;
+	/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
+	if (!idledly_units_ps)
+		return;
 
-		if (XE_GT_WA(gt, 14025941587))
-			min_idledly_ps = max(min_idledly_ps, 5000000);
+	if (XE_GT_WA(gt, 14025941587))
+		min_idledly_ps = max(min_idledly_ps, 5000000);
 
-		if (XE_GT_WA(gt, 16023105232)) {
-			u32 maxcnt_units_ps = 640000;
-			u32 maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
+	if (XE_GT_WA(gt, 16023105232)) {
+		u32 maxcnt_units_ps = 640000;
+		u32 maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
 
-			max_idledly_ps = min_t(u64,
-					       max_idledly_ps,
-					       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
+		max_idledly_ps = min_t(u64,
+				       max_idledly_ps,
+				       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
 
-			clear_inhibit_switch = true;
-		}
+		clear_inhibit_switch = true;
+	}
 
-		/* No applicable workaround found. */
-		if (min_idledly_ps == 0 && max_idledly_ps == -1 && !clear_inhibit_switch)
-			return;
+	/* No applicable workaround found. */
+	if (min_idledly_ps == 0 && max_idledly_ps == -1 && !clear_inhibit_switch)
+		return;
 
-		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
+	idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
 
-		if (clear_inhibit_switch && idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED) {
-			idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
-			wa_applied = true;
-		}
+	if (clear_inhibit_switch && idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED) {
+		idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
+		wa_applied = true;
+	}
+
+	idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
+	idledly_ps = idledly * idledly_units_ps;
+	idledly_hw_ps = idledly_ps;
 
-		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
+	/*
+	 * min_idledly_ps is applied before max_idledly_ps, which takes
+	 * priority if the two ever conflict (not expected in practice).
+	 */
+	if (idledly_ps < min_idledly_ps) {
+		idledly = DIV_ROUND_UP_ULL(min_idledly_ps, idledly_units_ps);
 		idledly_ps = idledly * idledly_units_ps;
-		idledly_hw_ps = idledly_ps;
+		wa_applied = true;
+	}
 
-		/*
-		 * min_idledly_ps is applied before max_idledly_ps, which takes
-		 * priority if the two ever conflict (not expected in practice).
-		 */
-		if (idledly_ps < min_idledly_ps) {
-			idledly = DIV_ROUND_UP_ULL(min_idledly_ps, idledly_units_ps);
+	if (idledly_ps >= max_idledly_ps) {
+		if (max_idledly_ps) {
+			idledly = DIV_ROUND_DOWN_ULL(max_idledly_ps - 1, idledly_units_ps);
 			idledly_ps = idledly * idledly_units_ps;
-			wa_applied = true;
+		} else {
+			idledly = 0;
+			idledly_ps = 0;
 		}
 
-		if (idledly_ps >= max_idledly_ps) {
-			if (max_idledly_ps) {
-				idledly = DIV_ROUND_DOWN_ULL(max_idledly_ps - 1, idledly_units_ps);
-				idledly_ps = idledly * idledly_units_ps;
-			} else {
-				idledly = 0;
-				idledly_ps = 0;
-			}
-
-			wa_applied = true;
-		}
+		wa_applied = true;
+	}
 
-		/* Warn only if the value read from *hardware* exceeds the maximum. */
-		xe_gt_WARN_ON(gt, idledly_hw_ps >= max_idledly_ps);
+	/* Warn only if the value read from *hardware* exceeds the maximum. */
+	xe_gt_WARN_ON(gt, idledly_hw_ps >= max_idledly_ps);
 
-		if (wa_applied) {
-			idledly_reg_val &= ~IDLE_DELAY;
-			idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY, idledly);
+	if (wa_applied) {
+		idledly_reg_val &= ~IDLE_DELAY;
+		idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY, idledly);
 
-			xe_gt_dbg(gt, "idledly %s: set %llups min=%llups max=%llups inh=%u ts=%ups\n",
-				  hwe->name, idledly_ps, min_idledly_ps, max_idledly_ps,
-				  !!(idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED),
-				  gt->info.timestamp_base);
-			xe_mmio_write32(&gt->mmio,
-					RING_IDLEDLY(hwe->mmio_base),
-					idledly_reg_val);
-		}
+		xe_gt_dbg(gt, "idledly %s: set %llups min=%llups max=%llups inh=%u ts=%ups\n",
+			  hwe->name, idledly_ps, min_idledly_ps, max_idledly_ps,
+			  !!(idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED),
+			  gt->info.timestamp_base);
+		xe_mmio_write32(&gt->mmio,
+				RING_IDLEDLY(hwe->mmio_base),
+				idledly_reg_val);
 	}
 }
 

-- 
2.56.0

[PATCH 07/10] drm/xe: Drop comment about MAXCNT when calling adjust_idledly()

[Gustavo Sousa]

The adjust_idledly() function does more than what the comment on the
call site says.  Furthermore, that comment seems unnecessary; if
anything, some documentation at the function definition would be
better, but even that doesn't seem terribly necessary.  Let's just
drop the comment.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_engine.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index ffd6ef9f96f4..18c8f88739d5 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -719,7 +719,6 @@ static int hw_engine_init(struct xe_gt *gt, struct xe_hw_engine *hwe,
 			xe_hw_engine_enable_ring(hwe);
 	}
 
-	/* Ensure IDLEDLY is lower than MAXCNT */
 	adjust_idledly(hwe);
 
 	return devm_add_action_or_reset(xe->drm.dev, hw_engine_fini, hwe);

-- 
2.56.0

[PATCH 08/10] drm/xe/guc: Increment regset size for Wa_1607983814 inside hwe loop

[Gustavo Sousa]

The regset size increment for Wa_1607983814 is correct with today's
hardware, because the maximum number RCS per GT is one.  That said, it
is arguably more accurate to make that calculation inside the
for_each_hw_engine() loop, where we can mimic the same conditions used
by guc_mmio_regset_write().

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_ads.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 43a2951a66d6..a67d3405b10f 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -220,14 +220,15 @@ static size_t calculate_regset_size(struct xe_gt *gt)
 	enum xe_hw_engine_id id;
 	unsigned int count = 0;
 
-	for_each_hw_engine(hwe, gt, id)
+	for_each_hw_engine(hwe, gt, id) {
 		xa_for_each(&hwe->reg_sr.xa, sr_idx, sr_entry)
 			count++;
 
-	count += ADS_REGSET_EXTRA_MAX * XE_NUM_HW_ENGINES;
+		if (XE_GT_WA(gt, 1607983814) && hwe->class == XE_ENGINE_CLASS_RENDER)
+			count += LNCFCMOCS_REG_COUNT;
+	}
 
-	if (XE_GT_WA(gt, 1607983814))
-		count += LNCFCMOCS_REG_COUNT;
+	count += ADS_REGSET_EXTRA_MAX * XE_NUM_HW_ENGINES;
 
 	return count * sizeof(struct guc_mmio_reg);
 }

-- 
2.56.0

[PATCH 09/10] drm/xe/guc: Increment regset size for RING_IDLEDLY workarounds

[Gustavo Sousa]

We need to keep calculate_regset_size() in sync with
guc_mmio_regset_write(). They became out of sync when RING_IDLEDLY was
added.

This likely went unnoticed because ADS_REGSET_EXTRA_MAX - being
greater than the current size of extra_regs - inadvertently provided
some extra room in the regset, which ended up being used for
RING_IDLEDLY.

However, we should not rely on that. We should make
ADS_REGSET_EXTRA_MAX strictly about extra_regs, and explicitly account
for the RING_IDLEDLY register.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_ads.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index a67d3405b10f..2e738d205738 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -226,6 +226,9 @@ static size_t calculate_regset_size(struct xe_gt *gt)
 
 		if (XE_GT_WA(gt, 1607983814) && hwe->class == XE_ENGINE_CLASS_RENDER)
 			count += LNCFCMOCS_REG_COUNT;
+
+		if (XE_GT_WA(hwe->gt, 16023105232) || XE_GT_WA(hwe->gt, 14025941587))
+			count++; /* RING_IDLEDLY */
 	}
 
 	count += ADS_REGSET_EXTRA_MAX * XE_NUM_HW_ENGINES;

-- 
2.56.0

[PATCH 10/10] drm/xe: Implement Wa_16031259911

[Gustavo Sousa]

Implement Wa_16031259911, which applies to graphics version 35.10 and
35.11.  The workaround definition instructs us to set the minimum idle
delay value to 2 times the memory read delay, and tells that using 1
unit of the IDLE_DELAY field covers that minimum.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_ads.c    | 6 ++++--
 drivers/gpu/drm/xe/xe_hw_engine.c  | 3 +++
 drivers/gpu/drm/xe/xe_wa_oob.rules | 1 +
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 2e738d205738..7f830122ae16 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -227,7 +227,8 @@ static size_t calculate_regset_size(struct xe_gt *gt)
 		if (XE_GT_WA(gt, 1607983814) && hwe->class == XE_ENGINE_CLASS_RENDER)
 			count += LNCFCMOCS_REG_COUNT;
 
-		if (XE_GT_WA(hwe->gt, 16023105232) || XE_GT_WA(hwe->gt, 14025941587))
+		if (XE_GT_WA(hwe->gt, 16023105232) || XE_GT_WA(hwe->gt, 14025941587) ||
+		    (XE_GT_WA(hwe->gt, 16031259911) && xe_gt_supports_multi_queue(hwe->gt, hwe->class)))
 			count++; /* RING_IDLEDLY */
 	}
 
@@ -875,7 +876,8 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
 		}
 	}
 
-	if (XE_GT_WA(hwe->gt, 16023105232) || XE_GT_WA(hwe->gt, 14025941587))
+	if (XE_GT_WA(hwe->gt, 16023105232) || XE_GT_WA(hwe->gt, 14025941587) ||
+	    (XE_GT_WA(hwe->gt, 16031259911) && xe_gt_supports_multi_queue(hwe->gt, hwe->class)))
 		guc_mmio_regset_write_one(ads, regset_map,
 					  RING_IDLEDLY(hwe->mmio_base),
 					  count++);
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 18c8f88739d5..96741d3050c5 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -618,6 +618,9 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 	if (XE_GT_WA(gt, 14025941587))
 		min_idledly_ps = max(min_idledly_ps, 5000000);
 
+	if (XE_GT_WA(gt, 16031259911) && xe_gt_supports_multi_queue(gt, hwe->class))
+		min_idledly_ps = max(min_idledly_ps, idledly_units_ps);
+
 	if (XE_GT_WA(gt, 16023105232)) {
 		u32 maxcnt_units_ps = 640000;
 		u32 maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index 9be392bce969..a28552c09019 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -77,3 +77,4 @@
 14025941587	GRAPHICS_VERSION_RANGE(2001, 3511)
 		MEDIA_VERSION_RANGE(1301, 3503)
 16030224309	GRAPHICS_VERSION(3510)
+16031259911	GRAPHICS_VERSION_RANGE(3510, 3511)

-- 
2.56.0

Re: [PATCH 03/10] drm/xe: Use picosecond as common unit in adjust_idledly()

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/xe: 32-bit multiplication overflow in adjust_idledly()
--

commit 6274ddb08f811b772af3c2cc759b8be4b565872c
Author: Gustavo Sousa <gustavo.sousa@intel.com>

drm/xe: Use picosecond as common unit in adjust_idledly()

This commit changes adjust_idledly() to use picoseconds instead of
nanoseconds as the common unit of time to avoid precision loss and
eliminate extra integer divisions.

> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 6872d1ca656e2..dcc8a6d53c5d0 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -585,17 +585,19 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
>  	xe_reg_whitelist_process_engine(hwe);
>  }
>  
> -static u32 idledly_floor_ticks(u32 idledly_ns, u32 idledly_units_ps)
> +static u32 idledly_floor_ticks(u64 idledly_ps, u32 idledly_units_ps)
>  {
> -	return DIV_ROUND_DOWN_ULL((u64)idledly_ns * 1000, idledly_units_ps);
> +	return DIV_ROUND_DOWN_ULL(idledly_ps, idledly_units_ps);
>  }
>  
>  static void adjust_idledly(struct xe_hw_engine *hwe)
>  {
>  	struct xe_gt *gt = hwe->gt;
> -	u32 idledly, idledly_hw, idledly_reg_val, maxcnt;
> +	u32 idledly_reg_val, maxcnt_reg_val;
>  	u32 idledly_units_ps = 8 * gt->info.timestamp_base;
> -	u32 maxcnt_units_ns = 640;
> +	u32 maxcnt_units_ps = 640000;
> +	u64 idledly_ps, idledly_hw_ps;
> +	u64 maxcnt_ps;
>  	bool inhibit_switch = false;
>  	bool wa_applied = false;
>  	bool clamped_below_maxcnt = false;
> @@ -604,29 +606,27 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>  		return;
>  
>  	if (XE_GT_WA(gt, 16023105232) || XE_GT_WA(gt, 14025941587)) {
> -		u32 mincnt_idledly_ns = 5000;
> +		u32 mincnt_idledly_ps = 5000000;
>  
>  		/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
>  		if (!idledly_units_ps)
>  			return;
>  
>  		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
> -		maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
> -
>  		inhibit_switch = idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED;
> -		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
> -		idledly = DIV_ROUND_CLOSEST_ULL((u64)idledly * idledly_units_ps, 1000);
> -		idledly_hw = idledly;
> -		maxcnt = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt);
> -		maxcnt *= maxcnt_units_ns;
> +		idledly_ps = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val) * idledly_units_ps;
> +		idledly_hw_ps = idledly_ps;
> +
> +		maxcnt_reg_val = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
> +		maxcnt_ps = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt_reg_val) * maxcnt_units_ps;

[Severity: High]
Can the multiplications computing idledly_ps and maxcnt_ps in
adjust_idledly() overflow 32-bit unsigned arithmetic before being widened
to u64?

In include/drm/intel/reg_bits.h, REG_FIELD_GET() returns a u32:

    #define REG_FIELD_GET(__mask, __val)	((u32)FIELD_GET(__mask, __val))

Because idledly_units_ps and maxcnt_units_ps are both declared as u32,
both multiplications are evaluated in 32-bit arithmetic before assignment
to u64 idledly_ps and u64 maxcnt_ps.

For idledly_ps, dropping the (u64) cast that was added in commit
d864065ea25e ("drm/xe: harden adjust_idledly() against divide-by-zero and
overflow") means IDLE_DELAY (a 21-bit field, REG_GENMASK(20, 0)) multiplied
by idledly_units_ps (up to 666,664 ps) wraps around U32_MAX whenever
IDLE_DELAY is >= 6443 ticks.

Similarly, for maxcnt_ps, scaling the unit multiplier from 640 ns to
640,000 ps in u32 means IDLE_WAIT_TIME (a 20-bit field, REG_GENMASK(19, 0))
multiplied by maxcnt_units_ps wraps around U32_MAX whenever IDLE_WAIT_TIME
is >= 6711 ticks (~4.29 ms out of its ~671 ms range).

When either product wraps, xe_gt_WARN_ON(gt, idledly_hw_ps >= maxcnt_ps)
can trigger spuriously, and the Wa_14025941587 and Wa_16023105232 checks
can program a corrupted IDLE_DELAY tick count into RING_IDLEDLY.

Should idledly_units_ps and maxcnt_units_ps be declared as u64 (or the
operands cast to u64 before multiplying)?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261023-wa_16031259911-v1-0-b0453f79c4e1@intel.com?part=3

✗ CI.checkpatch: warning for drm/xe: Clean up adjust_idledly() and implement Wa_16031259911

[Patchwork]

== Series Details ==

Series: drm/xe: Clean up adjust_idledly() and implement Wa_16031259911
URL   : https://patchwork.freedesktop.org/series/176761/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
3009867cd31863246e4afc138520a7a8bd37bb11
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 5247c9a4bf536feb23d18dc73874d4e5371a7961
Author: Gustavo Sousa <gustavo.sousa@intel.com>
Date:   Fri Oct 23 18:09:38 2026 -0300

    drm/xe: Implement Wa_16031259911
    
    Implement Wa_16031259911, which applies to graphics version 35.10 and
    35.11.  The workaround definition instructs us to set the minimum idle
    delay value to 2 times the memory read delay, and tells that using 1
    unit of the IDLE_DELAY field covers that minimum.
    
    Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
+ /mt/dim checkpatch b255dd13059988fddde9ea187d1dd1017c9a5766 drm-intel
54c306f7e5b8 drm/xe: Bail from adjust_idledly() if in VF mode
e4185b45d7ba drm/xe: Sync Wa_16023105232 in xe_was to match OOB rule
ac4de2d1c1ea drm/xe: Use picosecond as common unit in adjust_idledly()
cd14ce970f15 drm/xe: Factor out {min,max}_idledly_ps in adjust_idledly()
-:98: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#98: FILE: drivers/gpu/drm/xe/xe_hw_engine.c:634:
+					       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);

total: 0 errors, 1 warnings, 0 checks, 140 lines checked
22e1b230a901 drm/xe: Bail from adjust_idledly() if no applicable workaround
c88016f894f5 drm/xe: Drop early and redundant workaround checks in adjust_idledly()
66e42acbc1a6 drm/xe: Drop comment about MAXCNT when calling adjust_idledly()
8838effa0ca7 drm/xe/guc: Increment regset size for Wa_1607983814 inside hwe loop
b3792ca4a1db drm/xe/guc: Increment regset size for RING_IDLEDLY workarounds
5247c9a4bf53 drm/xe: Implement Wa_16031259911
-:23: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#23: FILE: drivers/gpu/drm/xe/xe_guc_ads.c:231:
+		    (XE_GT_WA(hwe->gt, 16031259911) && xe_gt_supports_multi_queue(hwe->gt, hwe->class)))

total: 0 errors, 1 warnings, 0 checks, 31 lines checked

Re: [PATCH 06/10] drm/xe: Drop early and redundant workaround checks in adjust_idledly()

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/xe: 32-bit multiplication overflow in adjust_idledly()
--

commit 1632f9f2c26646be902e4438963fff43c54e34fd
Author: Gustavo Sousa <gustavo.sousa@intel.com>

drm/xe: Drop early and redundant workaround checks in adjust_idledly()

This commit removes the outer workaround check in adjust_idledly() and
unindents the body now that each workaround check is scoped to its own
conditional block and the function returns early when no workaround
applies.

> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index e201fa96ee867..00af7344067d3 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -600,77 +600,75 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>  	if (IS_SRIOV_VF(gt_to_xe(gt)))
>  		return;
>  
> -	if (XE_GT_WA(gt, 16023105232) || XE_GT_WA(gt, 14025941587)) {
> -		/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
> -		if (!idledly_units_ps)
> -			return;
> +	/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
> +	if (!idledly_units_ps)
> +		return;
>  
> -		if (XE_GT_WA(gt, 14025941587))
> -			min_idledly_ps = max(min_idledly_ps, 5000000);
> +	if (XE_GT_WA(gt, 14025941587))
> +		min_idledly_ps = max(min_idledly_ps, 5000000);
>  
> -		if (XE_GT_WA(gt, 16023105232)) {
> -			u32 maxcnt_units_ps = 640000;
> -			u32 maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
> +	if (XE_GT_WA(gt, 16023105232)) {
> +		u32 maxcnt_units_ps = 640000;
> +		u32 maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
>  
> -			max_idledly_ps = min_t(u64,
> -					       max_idledly_ps,
> -					       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
> +		max_idledly_ps = min_t(u64,
> +				       max_idledly_ps,
> +				       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
>  
> -			clear_inhibit_switch = true;
> -		}
> +		clear_inhibit_switch = true;
> +	}
>  
> -		/* No applicable workaround found. */
> -		if (min_idledly_ps == 0 && max_idledly_ps == -1 && !clear_inhibit_switch)
> -			return;
> +	/* No applicable workaround found. */
> +	if (min_idledly_ps == 0 && max_idledly_ps == -1 && !clear_inhibit_switch)
> +		return;
>  
> -		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
> +	idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
>  
> -		if (clear_inhibit_switch && idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED) {
> -			idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
> -			wa_applied = true;
> -		}
> +	if (clear_inhibit_switch && idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED) {
> +		idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
> +		wa_applied = true;
> +	}
> +
> +	idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
> +	idledly_ps = idledly * idledly_units_ps;
> +	idledly_hw_ps = idledly_ps;
>  
> -		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
> +	/*
> +	 * min_idledly_ps is applied before max_idledly_ps, which takes
> +	 * priority if the two ever conflict (not expected in practice).
> +	 */
> +	if (idledly_ps < min_idledly_ps) {
> +		idledly = DIV_ROUND_UP_ULL(min_idledly_ps, idledly_units_ps);
>  		idledly_ps = idledly * idledly_units_ps;
> -		idledly_hw_ps = idledly_ps;
> +		wa_applied = true;
> +	}
>  
> -		/*
> -		 * min_idledly_ps is applied before max_idledly_ps, which takes
> -		 * priority if the two ever conflict (not expected in practice).
> -		 */
> -		if (idledly_ps < min_idledly_ps) {
> -			idledly = DIV_ROUND_UP_ULL(min_idledly_ps, idledly_units_ps);
> +	if (idledly_ps >= max_idledly_ps) {
> +		if (max_idledly_ps) {
> +			idledly = DIV_ROUND_DOWN_ULL(max_idledly_ps - 1, idledly_units_ps);
>  			idledly_ps = idledly * idledly_units_ps;

[Severity: Medium]
Can the picosecond multiplications in adjust_idledly() overflow 32 bits?

In the Wa_16023105232 check:

	max_idledly_ps = min_t(u64,
			       max_idledly_ps,
			       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);

both REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) and maxcnt_units_ps (640000)
have type u32. The multiplication is evaluated in 32-bit unsigned
arithmetic before min_t(u64, ...) widens the result to u64. Since
IDLE_WAIT_TIME is REG_GENMASK(19, 0), any register value of 6711 ticks or
greater (~4.295 ms out of the ~671 ms range) exceeds U32_MAX when
multiplied by 640000 and wraps around.

Similarly, idledly (extracted from the 21-bit IDLE_DELAY field) and
idledly_units_ps (8 * gt->info.timestamp_base) are both u32:

	idledly_ps = idledly * idledly_units_ps;

At all three assignments of idledly_ps in adjust_idledly(), the product is
computed in 32-bit arithmetic before being assigned to the u64 idledly_ps
variable, which overflows whenever the delay exceeds ~4.295 ms.

When reached during GT initialization via:

  xe_gt_init()
    -> gt_init_with_all_forcewake()
      -> xe_hw_engines_init()
        -> hw_engine_init()
          -> adjust_idledly()

this truncation can trigger a spurious xe_gt_WARN_ON(gt, idledly_hw_ps >=
max_idledly_ps) warning and program an improperly clamped IDLE_DELAY value
into RING_IDLEDLY.

Should maxcnt_units_ps and idledly_units_ps be declared as u64 (or the
multiplications use mul_u32_u32() / a u64 cast) so the products are
evaluated in 64-bit arithmetic?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261023-wa_16031259911-v1-0-b0453f79c4e1@intel.com?part=6

✓ CI.KUnit: success for drm/xe: Clean up adjust_idledly() and implement Wa_16031259911

[Patchwork]

== Series Details ==

Series: drm/xe: Clean up adjust_idledly() and implement Wa_16031259911
URL   : https://patchwork.freedesktop.org/series/176761/
State : success

== Summary ==

+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[21:20:07] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:20:12] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:20:32] Starting KUnit Kernel (1/1)...
[21:20:32] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:20:32] ================= gpu_buddy (14 subtests) ==================
[21:20:32] [PASSED] gpu_test_buddy_alloc_limit
[21:20:32] [PASSED] gpu_test_buddy_alloc_optimistic
[21:20:32] [PASSED] gpu_test_buddy_alloc_pessimistic
[21:20:32] [PASSED] gpu_test_buddy_alloc_pathological
[21:20:32] [PASSED] gpu_test_buddy_alloc_contiguous
[21:20:32] [PASSED] gpu_test_buddy_alloc_clear
[21:20:32] [PASSED] gpu_test_buddy_alloc_range
[21:20:32] [PASSED] gpu_test_buddy_alloc_range_bias
[21:20:33] [PASSED] gpu_test_buddy_fragmentation_performance
[21:20:34] [PASSED] gpu_test_buddy_dirty_tracker_performance
[21:20:34] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[21:20:34] [PASSED] gpu_test_buddy_offset_aligned_allocation
[21:20:34] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[21:20:34] [PASSED] gpu_test_buddy_addr_to_block
[21:20:34] ==================== [PASSED] gpu_buddy ====================
[21:20:34] ============================================================
[21:20:34] Testing complete. Ran 14 tests: passed: 14
[21:20:34] Elapsed time: 26.450s total, 4.480s configuring, 20.053s building, 1.850s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[21:20:34] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:20:36] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:21:14] Starting KUnit Kernel (1/1)...
[21:21:14] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:21:14] ================== guc_buf (11 subtests) ===================
[21:21:14] [PASSED] test_smallest
[21:21:14] [PASSED] test_largest
[21:21:14] [PASSED] test_granular
[21:21:14] [PASSED] test_unique
[21:21:14] [PASSED] test_overlap
[21:21:14] [PASSED] test_reusable
[21:21:14] [PASSED] test_too_big
[21:21:14] [PASSED] test_flush
[21:21:14] [PASSED] test_lookup
[21:21:14] [PASSED] test_data
[21:21:14] [PASSED] test_class
[21:21:14] ===================== [PASSED] guc_buf =====================
[21:21:14] =================== guc_dbm (7 subtests) ===================
[21:21:14] [PASSED] test_empty
[21:21:14] [PASSED] test_default
[21:21:14] ======================== test_size  ========================
[21:21:14] [PASSED] 4
[21:21:14] [PASSED] 8
[21:21:14] [PASSED] 32
[21:21:14] [PASSED] 256
[21:21:14] ==================== [PASSED] test_size ====================
[21:21:14] ======================= test_reuse  ========================
[21:21:14] [PASSED] 4
[21:21:14] [PASSED] 8
[21:21:14] [PASSED] 32
[21:21:14] [PASSED] 256
[21:21:14] =================== [PASSED] test_reuse ====================
[21:21:14] =================== test_range_overlap  ====================
[21:21:14] [PASSED] 4
[21:21:14] [PASSED] 8
[21:21:14] [PASSED] 32
[21:21:14] [PASSED] 256
[21:21:14] =============== [PASSED] test_range_overlap ================
[21:21:14] =================== test_range_compact  ====================
[21:21:14] [PASSED] 4
[21:21:14] [PASSED] 8
[21:21:14] [PASSED] 32
[21:21:14] [PASSED] 256
[21:21:14] =============== [PASSED] test_range_compact ================
[21:21:14] ==================== test_range_spare  =====================
[21:21:14] [PASSED] 4
[21:21:14] [PASSED] 8
[21:21:14] [PASSED] 32
[21:21:14] [PASSED] 256
[21:21:14] ================ [PASSED] test_range_spare =================
[21:21:14] ===================== [PASSED] guc_dbm =====================
[21:21:14] ================== guc_idm (22 subtests) ===================
[21:21:14] [PASSED] bad_init
[21:21:14] [PASSED] no_init
[21:21:14] [PASSED] init_fini
[21:21:14] [PASSED] check_init_small
[21:21:14] [PASSED] check_init_shared
[21:21:14] [PASSED] check_used
[21:21:14] [PASSED] check_quota
[21:21:14] [PASSED] check_all
[21:21:14] [PASSED] check_limits
[21:21:14] [PASSED] check_overlap
[21:21:14] [PASSED] check_overlap_alloc
[21:21:14] [PASSED] check_overlap_release
[21:21:14] [PASSED] check_overlap_partial_init
[21:21:14] [PASSED] check_overlap_partial_shared_range_blocking
[21:21:14] [PASSED] check_used_usable
[21:21:14] [PASSED] check_used_shareable
[21:21:14] [PASSED] check_used_mixed
[21:21:14] [PASSED] check_release_usable_range
[21:21:14] [PASSED] check_release_shareable_range
[21:21:14] [PASSED] check_split_boundaries
[21:21:14] [PASSED] check_shareable_spare
[21:21:14] [PASSED] check_shareable_spare_fragmented_tail
[21:21:14] ===================== [PASSED] guc_idm =====================
[21:21:14] ============== guc_klv_helpers (13 subtests) ===============
[21:21:14] [PASSED] test_count
[21:21:14] [PASSED] test_encode_u32
[21:21:14] [PASSED] test_encode_u64
[21:21:14] [PASSED] test_encode_string
[21:21:14] [PASSED] test_encode_object_raw
[21:21:14] [PASSED] test_encode_object_klv
[21:21:14] [PASSED] test_encode_object_nested
[21:21:14] [PASSED] test_encode_object_basic
[21:21:14] ===================== test_decode_u16  =====================
[21:21:14] [PASSED] empty
[21:21:14] [PASSED] valid
[21:21:14] [PASSED] max
[21:21:14] [PASSED] big
[21:21:14] [PASSED] long
[21:21:14] ================= [PASSED] test_decode_u16 =================
[21:21:14] ===================== test_decode_u32  =====================
[21:21:14] [PASSED] empty
[21:21:14] [PASSED] valid
[21:21:14] [PASSED] max
[21:21:14] [PASSED] long
[21:21:14] ================= [PASSED] test_decode_u32 =================
[21:21:14] ===================== test_decode_u64  =====================
[21:21:14] [PASSED] empty
[21:21:14] [PASSED] short
[21:21:14] [PASSED] valid
[21:21:14] [PASSED] max
[21:21:14] [PASSED] long
[21:21:14] ================= [PASSED] test_decode_u64 =================
[21:21:14] ===================== test_decode_str  =====================
[21:21:14] [PASSED] empty
[21:21:14] [PASSED] one
[21:21:14] [PASSED] one_trash
[21:21:14] [PASSED] two
[21:21:14] [PASSED] two_trash
[21:21:14] [PASSED] three
[21:21:14] [PASSED] dword
[21:21:14] [PASSED] four
[21:21:14] [PASSED] five
[21:21:14] [PASSED] six
[21:21:14] [PASSED] seven
[21:21:14] [PASSED] qword
[21:21:14] ================= [PASSED] test_decode_str =================
[21:21:14] [PASSED] test_print
[21:21:14] ================= [PASSED] guc_klv_helpers =================
[21:21:14] =================== xe_log (4 subtests) ====================
[21:21:14] [PASSED] demo_cper
[21:21:14] [PASSED] demo_dmesg
[21:21:14] ======================= test_dmesg  ========================
[21:21:14] [PASSED] test_fatal
[21:21:14] [PASSED] test_fatal_tile
[21:21:14] [PASSED] test_fatal_gt
[21:21:14] [PASSED] test_fatal_comp
[21:21:14] [PASSED] test_fatal_comp_tile
[21:21:14] [PASSED] test_fatal_comp_gt
[21:21:14] [PASSED] test_fatal_all
[21:21:14] [PASSED] test_recoverable
[21:21:14] [PASSED] test_recoverable_tile
[21:21:14] [PASSED] test_recoverable_gt
[21:21:14] [PASSED] test_recoverable_comp
[21:21:14] [PASSED] test_recoverable_comp_tile
[21:21:14] [PASSED] test_recoverable_comp_gt
[21:21:14] [PASSED] test_recoverable_all
[21:21:14] [PASSED] test_info
[21:21:14] [PASSED] test_info_tile
[21:21:14] [PASSED] test_info_gt
[21:21:14] [PASSED] test_info_err
[21:21:14] [PASSED] test_info_comp
[21:21:14] [PASSED] test_info_comp_tile
[21:21:14] [PASSED] test_info_comp_gt
[21:21:14] [PASSED] test_info_all
[21:21:14] [PASSED] test_hw_fatal
[21:21:14] [PASSED] test_hw_recoverable
[21:21:14] [PASSED] test_hw_corrected
[21:21:14] [PASSED] test_hw_informational
[21:21:14] =================== [PASSED] test_dmesg ====================
[21:21:14] ====================== test_invalid  =======================
[21:21:14] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[21:21:14] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[21:21:14] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[21:21:14] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[21:21:14] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[21:21:14] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[21:21:14] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[21:21:14] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[21:21:14] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[21:21:14] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[21:21:14] ================== [SKIPPED] test_invalid ==================
[21:21:14] ===================== [PASSED] xe_log ======================
[21:21:14] ================== no_relay (3 subtests) ===================
[21:21:14] [PASSED] xe_drops_guc2pf_if_not_ready
[21:21:14] [PASSED] xe_drops_guc2vf_if_not_ready
[21:21:14] [PASSED] xe_rejects_send_if_not_ready
[21:21:14] ==================== [PASSED] no_relay =====================
[21:21:14] ================== pf_relay (14 subtests) ==================
[21:21:14] [PASSED] pf_rejects_guc2pf_too_short
[21:21:14] [PASSED] pf_rejects_guc2pf_too_long
[21:21:14] [PASSED] pf_rejects_guc2pf_no_payload
[21:21:14] [PASSED] pf_fails_no_payload
[21:21:14] [PASSED] pf_fails_bad_origin
[21:21:14] [PASSED] pf_fails_bad_type
[21:21:14] [PASSED] pf_txn_reports_error
[21:21:14] [PASSED] pf_txn_sends_pf2guc
[21:21:14] [PASSED] pf_sends_pf2guc
[21:21:14] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:21:14] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:21:14] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:21:14] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:21:14] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:21:14] ==================== [PASSED] pf_relay =====================
[21:21:14] ================== vf_relay (3 subtests) ===================
[21:21:14] [PASSED] vf_rejects_guc2vf_too_short
[21:21:14] [PASSED] vf_rejects_guc2vf_too_long
[21:21:14] [PASSED] vf_rejects_guc2vf_no_payload
[21:21:14] ==================== [PASSED] vf_relay =====================
[21:21:14] ================ pf_gt_config (9 subtests) =================
[21:21:14] [PASSED] fair_contexts_1vf
[21:21:14] [PASSED] fair_doorbells_1vf
[21:21:14] [PASSED] fair_ggtt_1vf
[21:21:14] ====================== fair_vram_1vf  ======================
[21:21:14] [PASSED] 3.50 GiB
[21:21:14] [PASSED] 11.5 GiB
[21:21:14] [PASSED] 15.5 GiB
[21:21:14] [PASSED] 31.5 GiB
[21:21:14] [PASSED] 63.5 GiB
[21:21:14] [PASSED] 1.91 GiB
[21:21:14] ================== [PASSED] fair_vram_1vf ==================
[21:21:14] ================ fair_vram_1vf_admin_only  =================
[21:21:14] [PASSED] 3.50 GiB
[21:21:14] [PASSED] 11.5 GiB
[21:21:14] [PASSED] 15.5 GiB
[21:21:14] [PASSED] 31.5 GiB
[21:21:14] [PASSED] 63.5 GiB
[21:21:14] [PASSED] 1.91 GiB
[21:21:14] ============ [PASSED] fair_vram_1vf_admin_only =============
[21:21:14] ====================== fair_contexts  ======================
[21:21:14] [PASSED] 1 VF
[21:21:14] [PASSED] 2 VFs
[21:21:14] [PASSED] 3 VFs
[21:21:14] [PASSED] 4 VFs
[21:21:14] [PASSED] 5 VFs
[21:21:14] [PASSED] 6 VFs
[21:21:14] [PASSED] 7 VFs
[21:21:14] [PASSED] 8 VFs
[21:21:14] [PASSED] 9 VFs
[21:21:14] [PASSED] 10 VFs
[21:21:14] [PASSED] 11 VFs
[21:21:14] [PASSED] 12 VFs
[21:21:14] [PASSED] 13 VFs
[21:21:14] [PASSED] 14 VFs
[21:21:14] [PASSED] 15 VFs
[21:21:14] [PASSED] 16 VFs
[21:21:14] [PASSED] 17 VFs
[21:21:14] [PASSED] 18 VFs
[21:21:14] [PASSED] 19 VFs
[21:21:14] [PASSED] 20 VFs
[21:21:14] [PASSED] 21 VFs
[21:21:14] [PASSED] 22 VFs
[21:21:14] [PASSED] 23 VFs
[21:21:14] [PASSED] 24 VFs
[21:21:14] [PASSED] 25 VFs
[21:21:14] [PASSED] 26 VFs
[21:21:14] [PASSED] 27 VFs
[21:21:14] [PASSED] 28 VFs
[21:21:14] [PASSED] 29 VFs
[21:21:14] [PASSED] 30 VFs
[21:21:14] [PASSED] 31 VFs
[21:21:14] [PASSED] 32 VFs
[21:21:14] [PASSED] 33 VFs
[21:21:14] [PASSED] 34 VFs
[21:21:14] [PASSED] 35 VFs
[21:21:15] [PASSED] 36 VFs
[21:21:15] [PASSED] 37 VFs
[21:21:15] [PASSED] 38 VFs
[21:21:15] [PASSED] 39 VFs
[21:21:15] [PASSED] 40 VFs
[21:21:15] [PASSED] 41 VFs
[21:21:15] [PASSED] 42 VFs
[21:21:15] [PASSED] 43 VFs
[21:21:15] [PASSED] 44 VFs
[21:21:15] [PASSED] 45 VFs
[21:21:15] [PASSED] 46 VFs
[21:21:15] [PASSED] 47 VFs
[21:21:15] [PASSED] 48 VFs
[21:21:15] [PASSED] 49 VFs
[21:21:15] [PASSED] 50 VFs
[21:21:15] [PASSED] 51 VFs
[21:21:15] [PASSED] 52 VFs
[21:21:15] [PASSED] 53 VFs
[21:21:15] [PASSED] 54 VFs
[21:21:15] [PASSED] 55 VFs
[21:21:15] [PASSED] 56 VFs
[21:21:15] [PASSED] 57 VFs
[21:21:15] [PASSED] 58 VFs
[21:21:15] [PASSED] 59 VFs
[21:21:15] [PASSED] 60 VFs
[21:21:15] [PASSED] 61 VFs
[21:21:15] [PASSED] 62 VFs
[21:21:15] [PASSED] 63 VFs
[21:21:15] ================== [PASSED] fair_contexts ==================
[21:21:15] ===================== fair_doorbells  ======================
[21:21:15] [PASSED] 1 VF
[21:21:15] [PASSED] 2 VFs
[21:21:15] [PASSED] 3 VFs
[21:21:15] [PASSED] 4 VFs
[21:21:15] [PASSED] 5 VFs
[21:21:15] [PASSED] 6 VFs
[21:21:15] [PASSED] 7 VFs
[21:21:15] [PASSED] 8 VFs
[21:21:15] [PASSED] 9 VFs
[21:21:15] [PASSED] 10 VFs
[21:21:15] [PASSED] 11 VFs
[21:21:15] [PASSED] 12 VFs
[21:21:15] [PASSED] 13 VFs
[21:21:15] [PASSED] 14 VFs
[21:21:15] [PASSED] 15 VFs
[21:21:15] [PASSED] 16 VFs
[21:21:15] [PASSED] 17 VFs
[21:21:15] [PASSED] 18 VFs
[21:21:15] [PASSED] 19 VFs
[21:21:15] [PASSED] 20 VFs
[21:21:15] [PASSED] 21 VFs
[21:21:15] [PASSED] 22 VFs
[21:21:15] [PASSED] 23 VFs
[21:21:15] [PASSED] 24 VFs
[21:21:15] [PASSED] 25 VFs
[21:21:15] [PASSED] 26 VFs
[21:21:15] [PASSED] 27 VFs
[21:21:15] [PASSED] 28 VFs
[21:21:15] [PASSED] 29 VFs
[21:21:15] [PASSED] 30 VFs
[21:21:15] [PASSED] 31 VFs
[21:21:15] [PASSED] 32 VFs
[21:21:15] [PASSED] 33 VFs
[21:21:15] [PASSED] 34 VFs
[21:21:15] [PASSED] 35 VFs
[21:21:15] [PASSED] 36 VFs
[21:21:15] [PASSED] 37 VFs
[21:21:15] [PASSED] 38 VFs
[21:21:15] [PASSED] 39 VFs
[21:21:15] [PASSED] 40 VFs
[21:21:15] [PASSED] 41 VFs
[21:21:15] [PASSED] 42 VFs
[21:21:15] [PASSED] 43 VFs
[21:21:15] [PASSED] 44 VFs
[21:21:15] [PASSED] 45 VFs
[21:21:15] [PASSED] 46 VFs
[21:21:15] [PASSED] 47 VFs
[21:21:15] [PASSED] 48 VFs
[21:21:15] [PASSED] 49 VFs
[21:21:15] [PASSED] 50 VFs
[21:21:15] [PASSED] 51 VFs
[21:21:15] [PASSED] 52 VFs
[21:21:15] [PASSED] 53 VFs
[21:21:15] [PASSED] 54 VFs
[21:21:15] [PASSED] 55 VFs
[21:21:15] [PASSED] 56 VFs
[21:21:15] [PASSED] 57 VFs
[21:21:15] [PASSED] 58 VFs
[21:21:15] [PASSED] 59 VFs
[21:21:15] [PASSED] 60 VFs
[21:21:15] [PASSED] 61 VFs
[21:21:15] [PASSED] 62 VFs
[21:21:15] [PASSED] 63 VFs
[21:21:15] ================= [PASSED] fair_doorbells ==================
[21:21:15] ======================== fair_ggtt  ========================
[21:21:15] [PASSED] 1 VF
[21:21:15] [PASSED] 2 VFs
[21:21:15] [PASSED] 3 VFs
[21:21:15] [PASSED] 4 VFs
[21:21:15] [PASSED] 5 VFs
[21:21:15] [PASSED] 6 VFs
[21:21:15] [PASSED] 7 VFs
[21:21:15] [PASSED] 8 VFs
[21:21:15] [PASSED] 9 VFs
[21:21:15] [PASSED] 10 VFs
[21:21:15] [PASSED] 11 VFs
[21:21:15] [PASSED] 12 VFs
[21:21:15] [PASSED] 13 VFs
[21:21:15] [PASSED] 14 VFs
[21:21:15] [PASSED] 15 VFs
[21:21:15] [PASSED] 16 VFs
[21:21:15] [PASSED] 17 VFs
[21:21:15] [PASSED] 18 VFs
[21:21:15] [PASSED] 19 VFs
[21:21:15] [PASSED] 20 VFs
[21:21:15] [PASSED] 21 VFs
[21:21:15] [PASSED] 22 VFs
[21:21:15] [PASSED] 23 VFs
[21:21:15] [PASSED] 24 VFs
[21:21:15] [PASSED] 25 VFs
[21:21:15] [PASSED] 26 VFs
[21:21:15] [PASSED] 27 VFs
[21:21:15] [PASSED] 28 VFs
[21:21:15] [PASSED] 29 VFs
[21:21:15] [PASSED] 30 VFs
[21:21:15] [PASSED] 31 VFs
[21:21:15] [PASSED] 32 VFs
[21:21:15] [PASSED] 33 VFs
[21:21:15] [PASSED] 34 VFs
[21:21:15] [PASSED] 35 VFs
[21:21:15] [PASSED] 36 VFs
[21:21:15] [PASSED] 37 VFs
[21:21:15] [PASSED] 38 VFs
[21:21:15] [PASSED] 39 VFs
[21:21:15] [PASSED] 40 VFs
[21:21:15] [PASSED] 41 VFs
[21:21:15] [PASSED] 42 VFs
[21:21:15] [PASSED] 43 VFs
[21:21:15] [PASSED] 44 VFs
[21:21:15] [PASSED] 45 VFs
[21:21:15] [PASSED] 46 VFs
[21:21:15] [PASSED] 47 VFs
[21:21:15] [PASSED] 48 VFs
[21:21:15] [PASSED] 49 VFs
[21:21:15] [PASSED] 50 VFs
[21:21:15] [PASSED] 51 VFs
[21:21:15] [PASSED] 52 VFs
[21:21:15] [PASSED] 53 VFs
[21:21:15] [PASSED] 54 VFs
[21:21:15] [PASSED] 55 VFs
[21:21:15] [PASSED] 56 VFs
[21:21:15] [PASSED] 57 VFs
[21:21:15] [PASSED] 58 VFs
[21:21:15] [PASSED] 59 VFs
[21:21:15] [PASSED] 60 VFs
[21:21:15] [PASSED] 61 VFs
[21:21:15] [PASSED] 62 VFs
[21:21:15] [PASSED] 63 VFs
[21:21:15] ==================== [PASSED] fair_ggtt ====================
[21:21:15] ======================== fair_vram  ========================
[21:21:15] [PASSED] 1 VF
[21:21:15] [PASSED] 2 VFs
[21:21:15] [PASSED] 3 VFs
[21:21:15] [PASSED] 4 VFs
[21:21:15] [PASSED] 5 VFs
[21:21:15] [PASSED] 6 VFs
[21:21:15] [PASSED] 7 VFs
[21:21:15] [PASSED] 8 VFs
[21:21:15] [PASSED] 9 VFs
[21:21:15] [PASSED] 10 VFs
[21:21:15] [PASSED] 11 VFs
[21:21:15] [PASSED] 12 VFs
[21:21:15] [PASSED] 13 VFs
[21:21:15] [PASSED] 14 VFs
[21:21:15] [PASSED] 15 VFs
[21:21:15] [PASSED] 16 VFs
[21:21:15] [PASSED] 17 VFs
[21:21:15] [PASSED] 18 VFs
[21:21:15] [PASSED] 19 VFs
[21:21:15] [PASSED] 20 VFs
[21:21:15] [PASSED] 21 VFs
[21:21:15] [PASSED] 22 VFs
[21:21:15] [PASSED] 23 VFs
[21:21:15] [PASSED] 24 VFs
[21:21:15] [PASSED] 25 VFs
[21:21:15] [PASSED] 26 VFs
[21:21:15] [PASSED] 27 VFs
[21:21:15] [PASSED] 28 VFs
[21:21:15] [PASSED] 29 VFs
[21:21:15] [PASSED] 30 VFs
[21:21:15] [PASSED] 31 VFs
[21:21:15] [PASSED] 32 VFs
[21:21:15] [PASSED] 33 VFs
[21:21:15] [PASSED] 34 VFs
[21:21:15] [PASSED] 35 VFs
[21:21:15] [PASSED] 36 VFs
[21:21:15] [PASSED] 37 VFs
[21:21:15] [PASSED] 38 VFs
[21:21:15] [PASSED] 39 VFs
[21:21:15] [PASSED] 40 VFs
[21:21:15] [PASSED] 41 VFs
[21:21:15] [PASSED] 42 VFs
[21:21:15] [PASSED] 43 VFs
[21:21:15] [PASSED] 44 VFs
[21:21:15] [PASSED] 45 VFs
[21:21:15] [PASSED] 46 VFs
[21:21:15] [PASSED] 47 VFs
[21:21:15] [PASSED] 48 VFs
[21:21:15] [PASSED] 49 VFs
[21:21:15] [PASSED] 50 VFs
[21:21:15] [PASSED] 51 VFs
[21:21:15] [PASSED] 52 VFs
[21:21:15] [PASSED] 53 VFs
[21:21:15] [PASSED] 54 VFs
[21:21:15] [PASSED] 55 VFs
[21:21:15] [PASSED] 56 VFs
[21:21:15] [PASSED] 57 VFs
[21:21:15] [PASSED] 58 VFs
[21:21:15] [PASSED] 59 VFs
[21:21:15] [PASSED] 60 VFs
[21:21:15] [PASSED] 61 VFs
[21:21:15] [PASSED] 62 VFs
[21:21:15] [PASSED] 63 VFs
[21:21:15] ==================== [PASSED] fair_vram ====================
[21:21:15] ================== [PASSED] pf_gt_config ===================
[21:21:15] ===================== lmtt (1 subtest) =====================
[21:21:15] ======================== test_ops  =========================
[21:21:15] [PASSED] 2-level
[21:21:15] [PASSED] multi-level
[21:21:15] ==================== [PASSED] test_ops =====================
[21:21:15] ====================== [PASSED] lmtt =======================
[21:21:15] ================= sriov_packet (1 subtest) =================
[21:21:15] [PASSED] test_descriptor_init
[21:21:15] ================== [PASSED] sriov_packet ===================
[21:21:15] ================= pf_service (11 subtests) =================
[21:21:15] [PASSED] pf_negotiate_any
[21:21:15] [PASSED] pf_negotiate_base_match
[21:21:15] [PASSED] pf_negotiate_base_newer
[21:21:15] [PASSED] pf_negotiate_base_next
[21:21:15] [SKIPPED] pf_negotiate_base_older (no older minor)
[21:21:15] [PASSED] pf_negotiate_base_prev
[21:21:15] [PASSED] pf_negotiate_latest_match
[21:21:15] [PASSED] pf_negotiate_latest_newer
[21:21:15] [PASSED] pf_negotiate_latest_next
[21:21:15] [SKIPPED] pf_negotiate_latest_older (no older minor)
[21:21:15] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[21:21:15] =================== [PASSED] pf_service ====================
[21:21:15] ================= xe_guc_g2g (2 subtests) ==================
[21:21:15] ============== xe_live_guc_g2g_kunit_default  ==============
[21:21:15] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[21:21:15] ============== xe_live_guc_g2g_kunit_allmem  ===============
[21:21:15] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[21:21:15] =================== [SKIPPED] xe_guc_g2g ===================
[21:21:15] =================== xe_mocs (2 subtests) ===================
[21:21:15] ================ xe_live_mocs_kernel_kunit  ================
[21:21:15] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[21:21:15] ================ xe_live_mocs_reset_kunit  =================
[21:21:15] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[21:21:15] ==================== [SKIPPED] xe_mocs =====================
[21:21:15] ================= xe_migrate (3 subtests) ==================
[21:21:15] ================= xe_migrate_sanity_kunit  =================
[21:21:15] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[21:21:15] ================== xe_validate_ccs_kunit  ==================
[21:21:15] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[21:21:15] ============= xe_migrate_access_memory_kunit  ==============
[21:21:15] ========= [SKIPPED] xe_migrate_access_memory_kunit =========
[21:21:15] =================== [SKIPPED] xe_migrate ===================
[21:21:15] ================== xe_dma_buf (1 subtest) ==================
[21:21:15] ==================== xe_dma_buf_kunit  =====================
[21:21:15] ================ [SKIPPED] xe_dma_buf_kunit ================
[21:21:15] =================== [SKIPPED] xe_dma_buf ===================
[21:21:15] ================= xe_bo_shrink (1 subtest) =================
[21:21:15] =================== xe_bo_shrink_kunit  ====================
[21:21:15] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[21:21:15] ================== [SKIPPED] xe_bo_shrink ==================
[21:21:15] ==================== xe_bo (2 subtests) ====================
[21:21:15] ================== xe_ccs_migrate_kunit  ===================
[21:21:15] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[21:21:15] ==================== xe_bo_evict_kunit  ====================
[21:21:15] =============== [SKIPPED] xe_bo_evict_kunit ================
[21:21:15] ===================== [SKIPPED] xe_bo ======================
[21:21:15] =================== xe_any (9 subtests) ====================
[21:21:15] [PASSED] test_to_xe
[21:21:15] [PASSED] test_to_dev
[21:21:15] [PASSED] test_to_pdev
[21:21:15] [PASSED] test_to_drm
[21:21:15] [PASSED] test_if_pdev
[21:21:15] [PASSED] test_if_xe
[21:21:15] [PASSED] test_if_tile
[21:21:15] [PASSED] test_if_gt
[21:21:15] [PASSED] test_to_id
[21:21:15] ===================== [PASSED] xe_any ======================
[21:21:15] ==================== args (13 subtests) ====================
[21:21:15] [PASSED] count_args_test
[21:21:15] [PASSED] call_args_example
[21:21:15] [PASSED] call_args_test
[21:21:15] [PASSED] drop_first_arg_example
[21:21:15] [PASSED] drop_first_arg_test
[21:21:15] [PASSED] first_arg_example
[21:21:15] [PASSED] first_arg_test
[21:21:15] [PASSED] last_arg_example
[21:21:15] [PASSED] last_arg_test
[21:21:15] [PASSED] pick_arg_example
[21:21:15] [PASSED] if_args_example
[21:21:15] [PASSED] if_args_test
[21:21:15] [PASSED] sep_comma_example
[21:21:15] ====================== [PASSED] args =======================
[21:21:15] =================== xe_pci (3 subtests) ====================
[21:21:15] ==================== check_graphics_ip  ====================
[21:21:15] [PASSED] 12.00 Xe_LP
[21:21:15] [PASSED] 12.10 Xe_LP+
[21:21:15] [PASSED] 12.55 Xe_HPG
[21:21:15] [PASSED] 12.60 Xe_HPC
[21:21:15] [PASSED] 12.70 Xe_LPG
[21:21:15] [PASSED] 12.71 Xe_LPG
[21:21:15] [PASSED] 12.74 Xe_LPG+
[21:21:15] [PASSED] 20.01 Xe2_HPG
[21:21:15] [PASSED] 20.02 Xe2_HPG
[21:21:15] [PASSED] 20.04 Xe2_LPG
[21:21:15] [PASSED] 30.00 Xe3_LPG
[21:21:15] [PASSED] 30.01 Xe3_LPG
[21:21:15] [PASSED] 30.03 Xe3_LPG
[21:21:15] [PASSED] 30.04 Xe3_LPG
[21:21:15] [PASSED] 30.05 Xe3_LPG
[21:21:15] [PASSED] 35.10 Xe3p_LPG
[21:21:15] [PASSED] 35.11 Xe3p_XPC
[21:21:15] ================ [PASSED] check_graphics_ip ================
[21:21:15] ===================== check_media_ip  ======================
[21:21:15] [PASSED] 12.00 Xe_M
[21:21:15] [PASSED] 12.55 Xe_HPM
[21:21:15] [PASSED] 13.00 Xe_LPM+
[21:21:15] [PASSED] 13.01 Xe2_HPM
[21:21:15] [PASSED] 20.00 Xe2_LPM
[21:21:15] [PASSED] 30.00 Xe3_LPM
[21:21:15] [PASSED] 30.02 Xe3_LPM
[21:21:15] [PASSED] 35.00 Xe3p_LPM
[21:21:15] [PASSED] 35.03 Xe3p_HPM
[21:21:15] ================= [PASSED] check_media_ip ==================
[21:21:15] =================== check_platform_desc  ===================
[21:21:15] [PASSED] 0x9A60 (TIGERLAKE)
[21:21:15] [PASSED] 0x9A68 (TIGERLAKE)
[21:21:15] [PASSED] 0x9A70 (TIGERLAKE)
[21:21:15] [PASSED] 0x9A40 (TIGERLAKE)
[21:21:15] [PASSED] 0x9A49 (TIGERLAKE)
[21:21:15] [PASSED] 0x9A59 (TIGERLAKE)
[21:21:15] [PASSED] 0x9A78 (TIGERLAKE)
[21:21:15] [PASSED] 0x9AC0 (TIGERLAKE)
[21:21:15] [PASSED] 0x9AC9 (TIGERLAKE)
[21:21:15] [PASSED] 0x9AD9 (TIGERLAKE)
[21:21:15] [PASSED] 0x9AF8 (TIGERLAKE)
[21:21:15] [PASSED] 0x4C80 (ROCKETLAKE)
[21:21:15] [PASSED] 0x4C8A (ROCKETLAKE)
[21:21:15] [PASSED] 0x4C8B (ROCKETLAKE)
[21:21:15] [PASSED] 0x4C8C (ROCKETLAKE)
[21:21:15] [PASSED] 0x4C90 (ROCKETLAKE)
[21:21:15] [PASSED] 0x4C9A (ROCKETLAKE)
[21:21:15] [PASSED] 0x4680 (ALDERLAKE_S)
[21:21:15] [PASSED] 0x4682 (ALDERLAKE_S)
[21:21:15] [PASSED] 0x4688 (ALDERLAKE_S)
[21:21:15] [PASSED] 0x468A (ALDERLAKE_S)
[21:21:15] [PASSED] 0x468B (ALDERLAKE_S)
[21:21:15] [PASSED] 0x4690 (ALDERLAKE_S)
[21:21:15] [PASSED] 0x4692 (ALDERLAKE_S)
[21:21:15] [PASSED] 0x4693 (ALDERLAKE_S)
[21:21:15] [PASSED] 0x46A0 (ALDERLAKE_P)
[21:21:15] [PASSED] 0x46A1 (ALDERLAKE_P)
[21:21:15] [PASSED] 0x46A2 (ALDERLAKE_P)
[21:21:15] [PASSED] 0x46A3 (ALDERLAKE_P)
[21:21:15] [PASSED] 0x46A6 (ALDERLAKE_P)
[21:21:15] [PASSED] 0x46A8 (ALDERLAKE_P)
[21:21:15] [PASSED] 0x46AA (ALDERLAKE_P)
[21:21:15] [PASSED] 0x462A (ALDERLAKE_P)
[21:21:15] [PASSED] 0x4626 (ALDERLAKE_P)
[21:21:15] [PASSED] 0x4628 (ALDERLAKE_P)
[21:21:15] [PASSED] 0x46B0 (ALDERLAKE_P)
[21:21:15] [PASSED] 0x46B1 (ALDERLAKE_P)
[21:21:15] [PASSED] 0x46B2 (ALDERLAKE_P)
[21:21:15] [PASSED] 0x46B3 (ALDERLAKE_P)
[21:21:15] [PASSED] 0x46C0 (ALDERLAKE_P)
[21:21:15] [PASSED] 0x46C1 (ALDERLAKE_P)
[21:21:15] [PASSED] 0x46C2 (ALDERLAKE_P)
[21:21:15] [PASSED] 0x46C3 (ALDERLAKE_P)
[21:21:15] [PASSED] 0x46D0 (ALDERLAKE_N)
[21:21:15] [PASSED] 0x46D1 (ALDERLAKE_N)
[21:21:15] [PASSED] 0x46D2 (ALDERLAKE_N)
[21:21:15] [PASSED] 0x46D3 (ALDERLAKE_N)
[21:21:15] [PASSED] 0x46D4 (ALDERLAKE_N)
[21:21:15] [PASSED] 0xA721 (ALDERLAKE_P)
[21:21:15] [PASSED] 0xA7A1 (ALDERLAKE_P)
[21:21:15] [PASSED] 0xA7A9 (ALDERLAKE_P)
[21:21:15] [PASSED] 0xA7AC (ALDERLAKE_P)
[21:21:15] [PASSED] 0xA7AD (ALDERLAKE_P)
[21:21:15] [PASSED] 0xA720 (ALDERLAKE_P)
[21:21:15] [PASSED] 0xA7A0 (ALDERLAKE_P)
[21:21:15] [PASSED] 0xA7A8 (ALDERLAKE_P)
[21:21:15] [PASSED] 0xA7AA (ALDERLAKE_P)
[21:21:15] [PASSED] 0xA7AB (ALDERLAKE_P)
[21:21:15] [PASSED] 0xA780 (ALDERLAKE_S)
[21:21:15] [PASSED] 0xA781 (ALDERLAKE_S)
[21:21:15] [PASSED] 0xA782 (ALDERLAKE_S)
[21:21:15] [PASSED] 0xA783 (ALDERLAKE_S)
[21:21:15] [PASSED] 0xA788 (ALDERLAKE_S)
[21:21:15] [PASSED] 0xA789 (ALDERLAKE_S)
[21:21:15] [PASSED] 0xA78A (ALDERLAKE_S)
[21:21:15] [PASSED] 0xA78B (ALDERLAKE_S)
[21:21:15] [PASSED] 0x4905 (DG1)
[21:21:15] [PASSED] 0x4906 (DG1)
[21:21:15] [PASSED] 0x4907 (DG1)
[21:21:15] [PASSED] 0x4908 (DG1)
[21:21:15] [PASSED] 0x4909 (DG1)
[21:21:15] [PASSED] 0x56C0 (DG2)
[21:21:15] [PASSED] 0x56C2 (DG2)
[21:21:15] [PASSED] 0x56C1 (DG2)
[21:21:15] [PASSED] 0x7D51 (METEORLAKE)
[21:21:15] [PASSED] 0x7DD1 (METEORLAKE)
[21:21:15] [PASSED] 0x7D41 (METEORLAKE)
[21:21:15] [PASSED] 0x7D67 (METEORLAKE)
[21:21:15] [PASSED] 0xB640 (METEORLAKE)
[21:21:15] [PASSED] 0x56A0 (DG2)
[21:21:15] [PASSED] 0x56A1 (DG2)
[21:21:15] [PASSED] 0x56A2 (DG2)
[21:21:15] [PASSED] 0x56BE (DG2)
[21:21:15] [PASSED] 0x56BF (DG2)
[21:21:15] [PASSED] 0x5690 (DG2)
[21:21:15] [PASSED] 0x5691 (DG2)
[21:21:15] [PASSED] 0x5692 (DG2)
[21:21:15] [PASSED] 0x56A5 (DG2)
[21:21:15] [PASSED] 0x56A6 (DG2)
[21:21:15] [PASSED] 0x56B0 (DG2)
[21:21:15] [PASSED] 0x56B1 (DG2)
[21:21:15] [PASSED] 0x56BA (DG2)
[21:21:15] [PASSED] 0x56BB (DG2)
[21:21:15] [PASSED] 0x56BC (DG2)
[21:21:15] [PASSED] 0x56BD (DG2)
[21:21:15] [PASSED] 0x5693 (DG2)
[21:21:15] [PASSED] 0x5694 (DG2)
[21:21:15] [PASSED] 0x5695 (DG2)
[21:21:15] [PASSED] 0x56A3 (DG2)
[21:21:15] [PASSED] 0x56A4 (DG2)
[21:21:15] [PASSED] 0x56B2 (DG2)
[21:21:15] [PASSED] 0x56B3 (DG2)
[21:21:15] [PASSED] 0x5696 (DG2)
[21:21:15] [PASSED] 0x5697 (DG2)
[21:21:15] [PASSED] 0xB69 (PVC)
[21:21:15] [PASSED] 0xB6E (PVC)
[21:21:15] [PASSED] 0xBD4 (PVC)
[21:21:15] [PASSED] 0xBD5 (PVC)
[21:21:15] [PASSED] 0xBD6 (PVC)
[21:21:15] [PASSED] 0xBD7 (PVC)
[21:21:15] [PASSED] 0xBD8 (PVC)
[21:21:15] [PASSED] 0xBD9 (PVC)
[21:21:15] [PASSED] 0xBDA (PVC)
[21:21:15] [PASSED] 0xBDB (PVC)
[21:21:15] [PASSED] 0xBE0 (PVC)
[21:21:15] [PASSED] 0xBE1 (PVC)
[21:21:15] [PASSED] 0xBE5 (PVC)
[21:21:15] [PASSED] 0x7D40 (METEORLAKE)
[21:21:15] [PASSED] 0x7D45 (METEORLAKE)
[21:21:15] [PASSED] 0x7D55 (METEORLAKE)
[21:21:15] [PASSED] 0x7D60 (METEORLAKE)
[21:21:15] [PASSED] 0x7DD5 (METEORLAKE)
[21:21:15] [PASSED] 0x6420 (LUNARLAKE)
[21:21:15] [PASSED] 0x64A0 (LUNARLAKE)
[21:21:15] [PASSED] 0x64B0 (LUNARLAKE)
[21:21:15] [PASSED] 0xE202 (BATTLEMAGE)
[21:21:15] [PASSED] 0xE209 (BATTLEMAGE)
[21:21:15] [PASSED] 0xE20B (BATTLEMAGE)
[21:21:15] [PASSED] 0xE20C (BATTLEMAGE)
[21:21:15] [PASSED] 0xE20D (BATTLEMAGE)
[21:21:15] [PASSED] 0xE210 (BATTLEMAGE)
[21:21:15] [PASSED] 0xE211 (BATTLEMAGE)
[21:21:15] [PASSED] 0xE212 (BATTLEMAGE)
[21:21:15] [PASSED] 0xE216 (BATTLEMAGE)
[21:21:15] [PASSED] 0xE220 (BATTLEMAGE)
[21:21:15] [PASSED] 0xE221 (BATTLEMAGE)
[21:21:15] [PASSED] 0xE222 (BATTLEMAGE)
[21:21:15] [PASSED] 0xE223 (BATTLEMAGE)
[21:21:15] [PASSED] 0xB080 (PANTHERLAKE)
[21:21:15] [PASSED] 0xB081 (PANTHERLAKE)
[21:21:15] [PASSED] 0xB082 (PANTHERLAKE)
[21:21:15] [PASSED] 0xB083 (PANTHERLAKE)
[21:21:15] [PASSED] 0xB084 (PANTHERLAKE)
[21:21:15] [PASSED] 0xB085 (PANTHERLAKE)
[21:21:15] [PASSED] 0xB086 (PANTHERLAKE)
[21:21:15] [PASSED] 0xB087 (PANTHERLAKE)
[21:21:15] [PASSED] 0xB08F (PANTHERLAKE)
[21:21:15] [PASSED] 0xB090 (PANTHERLAKE)
[21:21:15] [PASSED] 0xB0A0 (PANTHERLAKE)
[21:21:15] [PASSED] 0xB0A1 (PANTHERLAKE)
[21:21:15] [PASSED] 0xB0B0 (PANTHERLAKE)
[21:21:15] [PASSED] 0xFD80 (PANTHERLAKE)
[21:21:15] [PASSED] 0xFD81 (PANTHERLAKE)
[21:21:15] [PASSED] 0xD740 (NOVALAKE_S)
[21:21:15] [PASSED] 0xD741 (NOVALAKE_S)
[21:21:15] [PASSED] 0xD742 (NOVALAKE_S)
[21:21:15] [PASSED] 0xD743 (NOVALAKE_S)
[21:21:15] [PASSED] 0xD745 (NOVALAKE_S)
[21:21:15] [PASSED] 0xD74A (NOVALAKE_S)
[21:21:15] [PASSED] 0xD74B (NOVALAKE_S)
[21:21:15] [PASSED] 0x674C (CRESCENTISLAND)
[21:21:15] [PASSED] 0x674D (CRESCENTISLAND)
[21:21:15] [PASSED] 0x674E (CRESCENTISLAND)
[21:21:15] [PASSED] 0x674F (CRESCENTISLAND)
[21:21:15] [PASSED] 0x6750 (CRESCENTISLAND)
[21:21:15] [PASSED] 0x6751 (CRESCENTISLAND)
[21:21:15] [PASSED] 0xD750 (NOVALAKE_P)
[21:21:15] [PASSED] 0xD751 (NOVALAKE_P)
[21:21:15] [PASSED] 0xD752 (NOVALAKE_P)
[21:21:15] [PASSED] 0xD753 (NOVALAKE_P)
[21:21:15] [PASSED] 0xD754 (NOVALAKE_P)
[21:21:15] [PASSED] 0xD755 (NOVALAKE_P)
[21:21:15] [PASSED] 0xD756 (NOVALAKE_P)
[21:21:15] [PASSED] 0xD757 (NOVALAKE_P)
[21:21:15] [PASSED] 0xD75F (NOVALAKE_P)
[21:21:15] =============== [PASSED] check_platform_desc ===============
[21:21:15] ===================== [PASSED] xe_pci ======================
[21:21:15] ============= xe_rtp_tables_test (5 subtests) ==============
[21:21:15] ================== xe_rtp_table_gt_test  ===================
[21:21:15] [PASSED] gt_was/14011060649
[21:21:15] [PASSED] gt_was/14011059788
[21:21:15] [PASSED] gt_was/14015795083
[21:21:15] [PASSED] gt_was/16021867713
[21:21:15] [PASSED] gt_was/14019449301
[21:21:15] [PASSED] gt_was/16028005424
[21:21:15] [PASSED] gt_was/14026578760
[21:21:15] [PASSED] gt_was/1409420604
[21:21:15] [PASSED] gt_was/1408615072
[21:21:15] [PASSED] gt_was/22010523718
[21:21:15] [PASSED] gt_was/14011006942
[21:21:15] [PASSED] gt_was/14014830051
[21:21:15] [PASSED] gt_was/18018781329
[21:21:15] [PASSED] gt_was/1509235366
[21:21:15] [PASSED] gt_was/18018781329
[21:21:15] [PASSED] gt_was/16016694945
[21:21:15] [PASSED] gt_was/14018575942
[21:21:15] [PASSED] gt_was/22016670082
[21:21:15] [PASSED] gt_was/22016670082
[21:21:15] [PASSED] gt_was/14017421178
[21:21:15] [PASSED] gt_was/16025250150
[21:21:15] [PASSED] gt_was/14021871409
[21:21:15] [PASSED] gt_was/16021865536
[21:21:15] [PASSED] gt_was/14021486841
[21:21:15] [PASSED] gt_was/14025160223
[21:21:15] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[21:21:15] [PASSED] gt_was/14025635424
[21:21:15] [PASSED] gt_was/16028005424
[21:21:15] ============== [PASSED] xe_rtp_table_gt_test ===============
[21:21:15] ================== xe_rtp_table_gt_test  ===================
[21:21:15] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[21:21:15] [PASSED] gt_tunings/Tuning: 32B Access Enable
[21:21:15] [PASSED] gt_tunings/Tuning: L3 cache
[21:21:15] [PASSED] gt_tunings/Tuning: L3 cache - media
[21:21:15] [PASSED] gt_tunings/Tuning: Compression Overfetch
[21:21:15] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[21:21:15] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[21:21:15] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[21:21:15] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[21:21:15] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[21:21:15] [PASSED] gt_tunings/Tuning: Stateless compression control
[21:21:15] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[21:21:15] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[21:21:15] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[21:21:15] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[21:21:15] [PASSED] gt_tunings/Tuning: Force All Non-Compressible Memory Reads to be 256B Overfetches
[21:21:15] ============== [PASSED] xe_rtp_table_gt_test ===============
[21:21:15] ================== xe_rtp_table_oob_test  ==================
[21:21:15] [PASSED] oob_was/1607983814
[21:21:15] [PASSED] oob_was/16010904313
[21:21:15] [PASSED] oob_was/18022495364
[21:21:15] [PASSED] oob_was/22012773006
[21:21:15] [PASSED] oob_was/14014475959
[21:21:15] [PASSED] oob_was/22011391025
[21:21:15] [PASSED] oob_was/22012727170
[21:21:15] [PASSED] oob_was/22012727685
[21:21:15] [PASSED] oob_was/22016596838
[21:21:15] [PASSED] oob_was/18020744125
[21:21:15] [PASSED] oob_was/1409600907
[21:21:15] [PASSED] oob_was/22014953428
[21:21:15] [PASSED] oob_was/16017236439
[21:21:15] [PASSED] oob_was/14019821291
[21:21:15] [PASSED] oob_was/14015076503
[21:21:15] [PASSED] oob_was/22016122933
[21:21:15] [PASSED] oob_was/14018913170
[21:21:15] [PASSED] oob_was/14018094691
[21:21:15] [PASSED] oob_was/18024947630
[21:21:15] [PASSED] oob_was/16022287689
[21:21:15] [PASSED] oob_was/13011645652
[21:21:15] [PASSED] oob_was/14022293748
[21:21:15] [PASSED] oob_was/22019794406
[21:21:15] [PASSED] oob_was/22019338487
[21:21:15] [PASSED] oob_was/16023588340
[21:21:15] [PASSED] oob_was/14019789679
[21:21:15] [PASSED] oob_was/14022866841
[21:21:15] [PASSED] oob_was/16021333562
[21:21:15] [PASSED] oob_was/14016712196
[21:21:15] [PASSED] oob_was/14015568240
[21:21:15] [PASSED] oob_was/18013179988
[21:21:15] [PASSED] oob_was/1508761755
[21:21:15] [PASSED] oob_was/16023105232
[21:21:15] [PASSED] oob_was/16026508708
[21:21:15] [PASSED] oob_was/14020001231
[21:21:15] [PASSED] oob_was/16023683509
[21:21:15] [PASSED] oob_was/14025515070
[21:21:15] [PASSED] oob_was/15015404425_disable
[21:21:15] [PASSED] oob_was/16026007364
[21:21:15] [PASSED] oob_was/14020316580
[21:21:15] [PASSED] oob_was/14025883347
[21:21:15] [PASSED] oob_was/16029380221
[21:21:15] [PASSED] oob_was/22022079272
[21:21:15] [PASSED] oob_was/16029897822
[21:21:15] [PASSED] oob_was/14027054324
[21:21:15] [PASSED] oob_was/14025941587
[21:21:15] [PASSED] oob_was/16030224309
[21:21:15] [PASSED] oob_was/16031259911
[21:21:15] ============== [PASSED] xe_rtp_table_oob_test ==============
[21:21:15] ================ xe_rtp_table_dev_oob_test  ================
[21:21:15] [PASSED] device_oob_was/22010954014
[21:21:15] [PASSED] device_oob_was/15015404425
[21:21:15] [PASSED] device_oob_was/22019338487_display
[21:21:15] [PASSED] device_oob_was/14022085890
[21:21:15] [PASSED] device_oob_was/14026539277
[21:21:15] [PASSED] device_oob_was/14026633728
[21:21:15] [PASSED] device_oob_was/14026746987
[21:21:15] [PASSED] device_oob_was/14026779378
[21:21:15] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[21:21:15] ========== xe_rtp_table_missing_upper_bound_test  ==========
[21:21:15] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[21:21:15] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[21:21:15] [PASSED] register_whitelist/1806527549
[21:21:15] [PASSED] register_whitelist/allow_read_ctx_timestamp
[21:21:15] [PASSED] register_whitelist/allow_read_queue_timestamp
[21:21:15] [PASSED] register_whitelist/16014440446
[21:21:15] [PASSED] register_whitelist/16017236439
[21:21:15] [PASSED] register_whitelist/16020183090
[21:21:15] [PASSED] register_whitelist/14024997852
[21:21:15] [PASSED] register_whitelist/14024997852
[21:21:15] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[21:21:15] =============== [PASSED] xe_rtp_tables_test ================
[21:21:15] =================== xe_rtp (3 subtests) ====================
[21:21:15] =================== xe_rtp_rules_tests  ====================
[21:21:15] [PASSED] no
[21:21:15] [PASSED] yes
[21:21:15] [PASSED] no-and-no
[21:21:15] [PASSED] no-and-yes
[21:21:15] [PASSED] yes-and-no
[21:21:15] [PASSED] yes-and-yes
[21:21:15] [PASSED] no-or-no
[21:21:15] [PASSED] no-or-yes
[21:21:15] [PASSED] yes-or-no
[21:21:15] [PASSED] yes-or-yes
[21:21:15] [PASSED] no-yes-or-yes-no
[21:21:15] [PASSED] no-yes-or-yes-yes
[21:21:15] [PASSED] yes-yes-or-no-yes
[21:21:15] [PASSED] yes-yes-or-yes-yes
[21:21:15] [PASSED] no-no-or-yes-or-no
[21:21:15] [PASSED] or
[21:21:15] [PASSED] or-yes
[21:21:15] [PASSED] or-no
[21:21:15] [PASSED] yes-or
[21:21:15] [PASSED] no-or
[21:21:15] [PASSED] no-or-or-yes
[21:21:15] [PASSED] yes-or-or-no
[21:21:15] [PASSED] no-or-or-no
[21:21:15] [PASSED] missing-context-engine-class
[21:21:15] [PASSED] missing-context-engine-class-or-yes
[21:21:15] [PASSED] missing-context-engine-class-or-or-yes
[21:21:15] =============== [PASSED] xe_rtp_rules_tests ================
[21:21:15] =============== xe_rtp_process_to_sr_tests  ================
[21:21:15] [PASSED] coalesce-same-reg
[21:21:15] [PASSED] coalesce-same-reg-literal-and-func
[21:21:15] [PASSED] no-match-no-add
[21:21:15] [PASSED] two-regs-two-entries
[21:21:15] [PASSED] clr-one-set-other
[21:21:15] [PASSED] set-field
[21:21:15] [PASSED] conflict-duplicate
[21:21:15] [PASSED] conflict-not-disjoint
[21:21:15] [PASSED] conflict-not-disjoint-literal-and-func
[21:21:15] [PASSED] conflict-reg-type
[21:21:15] [PASSED] bad-mcr-reg-forced-to-regular
[21:21:15] [PASSED] bad-regular-reg-forced-to-mcr
[21:21:15] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[21:21:15] ================== xe_rtp_process_tests  ===================
[21:21:15] [PASSED] active1
[21:21:15] [PASSED] active2
[21:21:15] [PASSED] active-inactive
[21:21:15] [PASSED] inactive-active
[21:21:15] [PASSED] inactive-active-inactive
[21:21:15] [PASSED] inactive-inactive-inactive
[21:21:15] ============== [PASSED] xe_rtp_process_tests ===============
[21:21:15] ===================== [PASSED] xe_rtp ======================
[21:21:15] ==================== xe_wa (1 subtest) =====================
[21:21:15] ======================== xe_wa_gt  =========================
[21:21:15] [PASSED] TIGERLAKE B0
[21:21:15] [PASSED] DG1 A0
[21:21:15] [PASSED] DG1 B0
[21:21:15] [PASSED] ALDERLAKE_S A0
[21:21:15] [PASSED] ALDERLAKE_S B0
[21:21:15] [PASSED] ALDERLAKE_S C0
[21:21:15] [PASSED] ALDERLAKE_S D0
[21:21:15] [PASSED] ALDERLAKE_P A0
[21:21:15] [PASSED] ALDERLAKE_P B0
[21:21:15] [PASSED] ALDERLAKE_P C0
[21:21:15] [PASSED] ALDERLAKE_S RPLS D0
[21:21:15] [PASSED] ALDERLAKE_P RPLU E0
[21:21:15] [PASSED] DG2 G10 C0
[21:21:15] [PASSED] DG2 G11 B1
[21:21:15] [PASSED] DG2 G12 A1
[21:21:15] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:21:15] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:21:15] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[21:21:15] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[21:21:15] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[21:21:15] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[21:21:15] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[21:21:15] ==================== [PASSED] xe_wa_gt =====================
[21:21:15] ====================== [PASSED] xe_wa ======================
[21:21:15] ============================================================
[21:21:15] Testing complete. Ran 839 tests: passed: 810, skipped: 29
[21:21:15] Elapsed time: 40.882s total, 1.847s configuring, 38.269s building, 0.727s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[21:21:15] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:21:17] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:21:42] Starting KUnit Kernel (1/1)...
[21:21:42] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:21:42] ============ drm_test_pick_cmdline (2 subtests) ============
[21:21:42] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[21:21:42] =============== drm_test_pick_cmdline_named  ===============
[21:21:42] [PASSED] NTSC
[21:21:42] [PASSED] NTSC-J
[21:21:42] [PASSED] PAL
[21:21:42] [PASSED] PAL-M
[21:21:42] =========== [PASSED] drm_test_pick_cmdline_named ===========
[21:21:42] ============== [PASSED] drm_test_pick_cmdline ==============
[21:21:42] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[21:21:42] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[21:21:42] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[21:21:42] =========== drm_validate_clone_mode (2 subtests) ===========
[21:21:42] ============== drm_test_check_in_clone_mode  ===============
[21:21:42] [PASSED] in_clone_mode
[21:21:42] [PASSED] not_in_clone_mode
[21:21:42] ========== [PASSED] drm_test_check_in_clone_mode ===========
[21:21:42] =============== drm_test_check_valid_clones  ===============
[21:21:42] [PASSED] not_in_clone_mode
[21:21:42] [PASSED] valid_clone
[21:21:42] [PASSED] invalid_clone
[21:21:42] =========== [PASSED] drm_test_check_valid_clones ===========
[21:21:42] ============= [PASSED] drm_validate_clone_mode =============
[21:21:42] ============= drm_validate_modeset (1 subtest) =============
[21:21:42] [PASSED] drm_test_check_connector_changed_modeset
[21:21:42] ============== [PASSED] drm_validate_modeset ===============
[21:21:42] ====== drm_test_bridge_get_current_state (1 subtest) =======
[21:21:42] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[21:21:42] ======== [PASSED] drm_test_bridge_get_current_state ========
[21:21:42] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[21:21:42] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[21:21:42] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[21:21:42] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[21:21:42] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[21:21:42] ============== drm_bridge_alloc (2 subtests) ===============
[21:21:42] [PASSED] drm_test_drm_bridge_alloc_basic
[21:21:42] [PASSED] drm_test_drm_bridge_alloc_get_put
[21:21:42] ================ [PASSED] drm_bridge_alloc =================
[21:21:42] ============= drm_bridge_bus_fmt (5 subtests) ==============
[21:21:42] [PASSED] drm_test_bridge_rgb_yuv_rgb
[21:21:42] [PASSED] drm_test_bridge_must_convert_to_yuv444
[21:21:42] [PASSED] drm_test_bridge_hdmi_auto_rgb
[21:21:42] [PASSED] drm_test_bridge_auto_first
[21:21:42] [PASSED] drm_test_bridge_rgb_yuv_no_path
[21:21:42] =============== [PASSED] drm_bridge_bus_fmt ================
[21:21:42] ============= drm_cmdline_parser (40 subtests) =============
[21:21:42] [PASSED] drm_test_cmdline_force_d_only
[21:21:42] [PASSED] drm_test_cmdline_force_D_only_dvi
[21:21:42] [PASSED] drm_test_cmdline_force_D_only_hdmi
[21:21:42] [PASSED] drm_test_cmdline_force_D_only_not_digital
[21:21:42] [PASSED] drm_test_cmdline_force_e_only
[21:21:42] [PASSED] drm_test_cmdline_res
[21:21:42] [PASSED] drm_test_cmdline_res_vesa
[21:21:42] [PASSED] drm_test_cmdline_res_vesa_rblank
[21:21:42] [PASSED] drm_test_cmdline_res_rblank
[21:21:42] [PASSED] drm_test_cmdline_res_bpp
[21:21:42] [PASSED] drm_test_cmdline_res_refresh
[21:21:42] [PASSED] drm_test_cmdline_res_bpp_refresh
[21:21:42] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[21:21:42] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[21:21:42] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[21:21:42] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[21:21:42] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[21:21:42] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[21:21:42] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[21:21:42] [PASSED] drm_test_cmdline_res_margins_force_on
[21:21:42] [PASSED] drm_test_cmdline_res_vesa_margins
[21:21:42] [PASSED] drm_test_cmdline_name
[21:21:42] [PASSED] drm_test_cmdline_name_bpp
[21:21:42] [PASSED] drm_test_cmdline_name_option
[21:21:42] [PASSED] drm_test_cmdline_name_bpp_option
[21:21:42] [PASSED] drm_test_cmdline_rotate_0
[21:21:42] [PASSED] drm_test_cmdline_rotate_90
[21:21:42] [PASSED] drm_test_cmdline_rotate_180
[21:21:42] [PASSED] drm_test_cmdline_rotate_270
[21:21:42] [PASSED] drm_test_cmdline_hmirror
[21:21:42] [PASSED] drm_test_cmdline_vmirror
[21:21:42] [PASSED] drm_test_cmdline_margin_options
[21:21:42] [PASSED] drm_test_cmdline_multiple_options
[21:21:42] [PASSED] drm_test_cmdline_bpp_extra_and_option
[21:21:42] [PASSED] drm_test_cmdline_extra_and_option
[21:21:42] [PASSED] drm_test_cmdline_freestanding_options
[21:21:42] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[21:21:42] [PASSED] drm_test_cmdline_panel_orientation
[21:21:42] ================ drm_test_cmdline_invalid  =================
[21:21:42] [PASSED] margin_only
[21:21:42] [PASSED] interlace_only
[21:21:42] [PASSED] res_missing_x
[21:21:42] [PASSED] res_missing_y
[21:21:42] [PASSED] res_bad_y
[21:21:42] [PASSED] res_missing_y_bpp
[21:21:42] [PASSED] res_bad_bpp
[21:21:42] [PASSED] res_bad_refresh
[21:21:42] [PASSED] res_bpp_refresh_force_on_off
[21:21:42] [PASSED] res_invalid_mode
[21:21:42] [PASSED] res_bpp_wrong_place_mode
[21:21:42] [PASSED] name_bpp_refresh
[21:21:42] [PASSED] name_refresh
[21:21:42] [PASSED] name_refresh_wrong_mode
[21:21:42] [PASSED] name_refresh_invalid_mode
[21:21:42] [PASSED] rotate_multiple
[21:21:42] [PASSED] rotate_invalid_val
[21:21:42] [PASSED] rotate_truncated
[21:21:42] [PASSED] invalid_option
[21:21:42] [PASSED] invalid_tv_option
[21:21:42] [PASSED] truncated_tv_option
[21:21:42] ============ [PASSED] drm_test_cmdline_invalid =============
[21:21:42] =============== drm_test_cmdline_tv_options  ===============
[21:21:42] [PASSED] NTSC
[21:21:42] [PASSED] NTSC_443
[21:21:42] [PASSED] NTSC_J
[21:21:42] [PASSED] PAL
[21:21:42] [PASSED] PAL_M
[21:21:42] [PASSED] PAL_N
[21:21:42] [PASSED] SECAM
[21:21:42] [PASSED] MONO_525
[21:21:42] [PASSED] MONO_625
[21:21:42] =========== [PASSED] drm_test_cmdline_tv_options ===========
[21:21:42] =============== [PASSED] drm_cmdline_parser ================
[21:21:42] ========== drmm_connector_hdmi_init (20 subtests) ==========
[21:21:42] [PASSED] drm_test_connector_hdmi_init_valid
[21:21:42] [PASSED] drm_test_connector_hdmi_init_bpc_8
[21:21:42] [PASSED] drm_test_connector_hdmi_init_bpc_10
[21:21:42] [PASSED] drm_test_connector_hdmi_init_bpc_12
[21:21:42] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[21:21:42] [PASSED] drm_test_connector_hdmi_init_bpc_null
[21:21:42] [PASSED] drm_test_connector_hdmi_init_formats_empty
[21:21:42] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[21:21:42] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[21:21:42] [PASSED] supported_formats=0x9 yuv420_allowed=1
[21:21:42] [PASSED] supported_formats=0x9 yuv420_allowed=0
[21:21:42] [PASSED] supported_formats=0x5 yuv420_allowed=1
[21:21:42] [PASSED] supported_formats=0x5 yuv420_allowed=0
[21:21:42] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[21:21:42] [PASSED] drm_test_connector_hdmi_init_null_ddc
[21:21:42] [PASSED] drm_test_connector_hdmi_init_null_product
[21:21:42] [PASSED] drm_test_connector_hdmi_init_null_vendor
[21:21:42] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[21:21:42] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[21:21:42] [PASSED] drm_test_connector_hdmi_init_product_valid
[21:21:42] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[21:21:42] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[21:21:42] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[21:21:42] ========= drm_test_connector_hdmi_init_type_valid  =========
[21:21:42] [PASSED] HDMI-A
[21:21:42] [PASSED] HDMI-B
[21:21:42] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[21:21:42] ======== drm_test_connector_hdmi_init_type_invalid  ========
[21:21:42] [PASSED] Unknown
[21:21:42] [PASSED] VGA
[21:21:42] [PASSED] DVI-I
[21:21:42] [PASSED] DVI-D
[21:21:42] [PASSED] DVI-A
[21:21:42] [PASSED] Composite
[21:21:42] [PASSED] SVIDEO
[21:21:42] [PASSED] LVDS
[21:21:42] [PASSED] Component
[21:21:42] [PASSED] DIN
[21:21:42] [PASSED] DP
[21:21:42] [PASSED] TV
[21:21:42] [PASSED] eDP
[21:21:42] [PASSED] Virtual
[21:21:42] [PASSED] DSI
[21:21:42] [PASSED] DPI
[21:21:42] [PASSED] Writeback
[21:21:42] [PASSED] SPI
[21:21:42] [PASSED] USB
[21:21:42] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[21:21:42] ============ [PASSED] drmm_connector_hdmi_init =============
[21:21:42] ============= drmm_connector_init (3 subtests) =============
[21:21:42] [PASSED] drm_test_drmm_connector_init
[21:21:42] [PASSED] drm_test_drmm_connector_init_null_ddc
[21:21:42] ========= drm_test_drmm_connector_init_type_valid  =========
[21:21:42] [PASSED] Unknown
[21:21:42] [PASSED] VGA
[21:21:42] [PASSED] DVI-I
[21:21:42] [PASSED] DVI-D
[21:21:42] [PASSED] DVI-A
[21:21:42] [PASSED] Composite
[21:21:42] [PASSED] SVIDEO
[21:21:42] [PASSED] LVDS
[21:21:42] [PASSED] Component
[21:21:42] [PASSED] DIN
[21:21:42] [PASSED] DP
[21:21:42] [PASSED] HDMI-A
[21:21:42] [PASSED] HDMI-B
[21:21:42] [PASSED] TV
[21:21:42] [PASSED] eDP
[21:21:42] [PASSED] Virtual
[21:21:42] [PASSED] DSI
[21:21:42] [PASSED] DPI
[21:21:42] [PASSED] Writeback
[21:21:42] [PASSED] SPI
[21:21:42] [PASSED] USB
[21:21:42] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[21:21:42] =============== [PASSED] drmm_connector_init ===============
[21:21:42] ========= drm_connector_dynamic_init (6 subtests) ==========
[21:21:42] [PASSED] drm_test_drm_connector_dynamic_init
[21:21:42] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[21:21:42] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[21:21:42] [PASSED] drm_test_drm_connector_dynamic_init_properties
[21:21:42] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[21:21:42] [PASSED] Unknown
[21:21:42] [PASSED] VGA
[21:21:42] [PASSED] DVI-I
[21:21:42] [PASSED] DVI-D
[21:21:42] [PASSED] DVI-A
[21:21:42] [PASSED] Composite
[21:21:42] [PASSED] SVIDEO
[21:21:42] [PASSED] LVDS
[21:21:42] [PASSED] Component
[21:21:42] [PASSED] DIN
[21:21:42] [PASSED] DP
[21:21:42] [PASSED] HDMI-A
[21:21:42] [PASSED] HDMI-B
[21:21:42] [PASSED] TV
[21:21:42] [PASSED] eDP
[21:21:42] [PASSED] Virtual
[21:21:42] [PASSED] DSI
[21:21:42] [PASSED] DPI
[21:21:42] [PASSED] Writeback
[21:21:42] [PASSED] SPI
[21:21:42] [PASSED] USB
[21:21:42] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[21:21:42] ======== drm_test_drm_connector_dynamic_init_name  =========
[21:21:42] [PASSED] Unknown
[21:21:42] [PASSED] VGA
[21:21:42] [PASSED] DVI-I
[21:21:42] [PASSED] DVI-D
[21:21:42] [PASSED] DVI-A
[21:21:42] [PASSED] Composite
[21:21:42] [PASSED] SVIDEO
[21:21:42] [PASSED] LVDS
[21:21:42] [PASSED] Component
[21:21:42] [PASSED] DIN
[21:21:42] [PASSED] DP
[21:21:42] [PASSED] HDMI-A
[21:21:42] [PASSED] HDMI-B
[21:21:42] [PASSED] TV
[21:21:42] [PASSED] eDP
[21:21:42] [PASSED] Virtual
[21:21:42] [PASSED] DSI
[21:21:42] [PASSED] DPI
[21:21:42] [PASSED] Writeback
[21:21:42] [PASSED] SPI
[21:21:42] [PASSED] USB
[21:21:42] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[21:21:42] =========== [PASSED] drm_connector_dynamic_init ============
[21:21:42] ==== drm_connector_dynamic_register_early (4 subtests) =====
[21:21:42] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[21:21:42] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[21:21:42] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[21:21:42] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[21:21:42] ====== [PASSED] drm_connector_dynamic_register_early =======
[21:21:42] ======= drm_connector_dynamic_register (7 subtests) ========
[21:21:42] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[21:21:42] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[21:21:42] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[21:21:42] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[21:21:42] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[21:21:42] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[21:21:42] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[21:21:42] ========= [PASSED] drm_connector_dynamic_register ==========
[21:21:42] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[21:21:42] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[21:21:42] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[21:21:42] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[21:21:42] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[21:21:42] ========== drm_test_get_tv_mode_from_name_valid  ===========
[21:21:42] [PASSED] NTSC
[21:21:42] [PASSED] NTSC-443
[21:21:42] [PASSED] NTSC-J
[21:21:42] [PASSED] PAL
[21:21:42] [PASSED] PAL-M
[21:21:42] [PASSED] PAL-N
[21:21:42] [PASSED] SECAM
[21:21:42] [PASSED] Mono
[21:21:42] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[21:21:42] [PASSED] drm_test_get_tv_mode_from_name_truncated
[21:21:42] ============ [PASSED] drm_get_tv_mode_from_name ============
[21:21:42] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[21:21:42] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[21:21:42] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[21:21:42] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[21:21:42] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[21:21:42] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[21:21:42] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[21:21:42] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[21:21:42] [PASSED] VIC 96
[21:21:42] [PASSED] VIC 97
[21:21:42] [PASSED] VIC 101
[21:21:42] [PASSED] VIC 102
[21:21:42] [PASSED] VIC 106
[21:21:42] [PASSED] VIC 107
[21:21:42] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[21:21:42] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[21:21:42] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[21:21:42] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[21:21:42] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[21:21:42] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[21:21:42] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[21:21:42] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[21:21:42] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[21:21:42] [PASSED] Automatic
[21:21:42] [PASSED] Full
[21:21:42] [PASSED] Limited 16:235
[21:21:42] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[21:21:42] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[21:21:42] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[21:21:42] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[21:21:42] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[21:21:42] [PASSED] RGB
[21:21:42] [PASSED] YUV 4:2:0
[21:21:42] [PASSED] YUV 4:2:2
[21:21:42] [PASSED] YUV 4:4:4
[21:21:42] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[21:21:42] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[21:21:42] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[21:21:42] ============= drm_damage_helper (21 subtests) ==============
[21:21:42] [PASSED] drm_test_damage_iter_no_damage
[21:21:42] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[21:21:42] [PASSED] drm_test_damage_iter_no_damage_src_moved
[21:21:42] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[21:21:42] [PASSED] drm_test_damage_iter_no_damage_not_visible
[21:21:42] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[21:21:42] [PASSED] drm_test_damage_iter_no_damage_no_fb
[21:21:42] [PASSED] drm_test_damage_iter_simple_damage
[21:21:42] [PASSED] drm_test_damage_iter_single_damage
[21:21:42] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[21:21:42] [PASSED] drm_test_damage_iter_single_damage_outside_src
[21:21:42] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[21:21:42] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[21:21:42] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[21:21:42] [PASSED] drm_test_damage_iter_single_damage_src_moved
[21:21:42] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[21:21:42] [PASSED] drm_test_damage_iter_damage
[21:21:42] [PASSED] drm_test_damage_iter_damage_one_intersect
[21:21:42] [PASSED] drm_test_damage_iter_damage_one_outside
[21:21:42] [PASSED] drm_test_damage_iter_damage_src_moved
[21:21:42] [PASSED] drm_test_damage_iter_damage_not_visible
[21:21:42] ================ [PASSED] drm_damage_helper ================
[21:21:42] ============== drm_dp_mst_helper (3 subtests) ==============
[21:21:42] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[21:21:42] [PASSED] Clock 154000 BPP 30 DSC disabled
[21:21:42] [PASSED] Clock 234000 BPP 30 DSC disabled
[21:21:42] [PASSED] Clock 297000 BPP 24 DSC disabled
[21:21:42] [PASSED] Clock 332880 BPP 24 DSC enabled
[21:21:42] [PASSED] Clock 324540 BPP 24 DSC enabled
[21:21:42] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[21:21:42] ============== drm_test_dp_mst_calc_pbn_div  ===============
[21:21:42] [PASSED] Link rate 2000000 lane count 4
[21:21:42] [PASSED] Link rate 2000000 lane count 2
[21:21:42] [PASSED] Link rate 2000000 lane count 1
[21:21:42] [PASSED] Link rate 1350000 lane count 4
[21:21:42] [PASSED] Link rate 1350000 lane count 2
[21:21:42] [PASSED] Link rate 1350000 lane count 1
[21:21:42] [PASSED] Link rate 1000000 lane count 4
[21:21:42] [PASSED] Link rate 1000000 lane count 2
[21:21:42] [PASSED] Link rate 1000000 lane count 1
[21:21:42] [PASSED] Link rate 810000 lane count 4
[21:21:42] [PASSED] Link rate 810000 lane count 2
[21:21:42] [PASSED] Link rate 810000 lane count 1
[21:21:42] [PASSED] Link rate 540000 lane count 4
[21:21:42] [PASSED] Link rate 540000 lane count 2
[21:21:42] [PASSED] Link rate 540000 lane count 1
[21:21:42] [PASSED] Link rate 270000 lane count 4
[21:21:42] [PASSED] Link rate 270000 lane count 2
[21:21:42] [PASSED] Link rate 270000 lane count 1
[21:21:42] [PASSED] Link rate 162000 lane count 4
[21:21:42] [PASSED] Link rate 162000 lane count 2
[21:21:42] [PASSED] Link rate 162000 lane count 1
[21:21:42] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[21:21:42] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[21:21:42] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[21:21:42] [PASSED] DP_POWER_UP_PHY with port number
[21:21:42] [PASSED] DP_POWER_DOWN_PHY with port number
[21:21:42] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[21:21:42] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[21:21:42] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[21:21:42] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[21:21:42] [PASSED] DP_QUERY_PAYLOAD with port number
[21:21:42] [PASSED] DP_QUERY_PAYLOAD with VCPI
[21:21:42] [PASSED] DP_REMOTE_DPCD_READ with port number
[21:21:42] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[21:21:42] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[21:21:42] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[21:21:42] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[21:21:42] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[21:21:42] [PASSED] DP_REMOTE_I2C_READ with port number
[21:21:42] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[21:21:42] [PASSED] DP_REMOTE_I2C_READ with transactions array
[21:21:42] [PASSED] DP_REMOTE_I2C_WRITE with port number
[21:21:42] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[21:21:42] [PASSED] DP_REMOTE_I2C_WRITE with data array
[21:21:42] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[21:21:42] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[21:21:42] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[21:21:42] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[21:21:42] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[21:21:42] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[21:21:42] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[21:21:42] ================ [PASSED] drm_dp_mst_helper ================
[21:21:42] ================== drm_exec (7 subtests) ===================
[21:21:42] [PASSED] sanitycheck
[21:21:42] [PASSED] test_lock
[21:21:42] [PASSED] test_lock_unlock
[21:21:42] [PASSED] test_duplicates
[21:21:42] [PASSED] test_prepare
[21:21:42] [PASSED] test_prepare_array
[21:21:42] [PASSED] test_multiple_loops
[21:21:42] ==================== [PASSED] drm_exec =====================
[21:21:42] =========== drm_format_helper_test (17 subtests) ===========
[21:21:42] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[21:21:42] [PASSED] single_pixel_source_buffer
[21:21:42] [PASSED] single_pixel_clip_rectangle
[21:21:42] [PASSED] well_known_colors
[21:21:42] [PASSED] destination_pitch
[21:21:42] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[21:21:42] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[21:21:42] [PASSED] single_pixel_source_buffer
[21:21:42] [PASSED] single_pixel_clip_rectangle
[21:21:42] [PASSED] well_known_colors
[21:21:42] [PASSED] destination_pitch
[21:21:42] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[21:21:42] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[21:21:42] [PASSED] single_pixel_source_buffer
[21:21:42] [PASSED] single_pixel_clip_rectangle
[21:21:42] [PASSED] well_known_colors
[21:21:42] [PASSED] destination_pitch
[21:21:42] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[21:21:42] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[21:21:42] [PASSED] single_pixel_source_buffer
[21:21:42] [PASSED] single_pixel_clip_rectangle
[21:21:42] [PASSED] well_known_colors
[21:21:42] [PASSED] destination_pitch
[21:21:42] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[21:21:42] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[21:21:42] [PASSED] single_pixel_source_buffer
[21:21:42] [PASSED] single_pixel_clip_rectangle
[21:21:42] [PASSED] well_known_colors
[21:21:42] [PASSED] destination_pitch
[21:21:42] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[21:21:42] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[21:21:42] [PASSED] single_pixel_source_buffer
[21:21:42] [PASSED] single_pixel_clip_rectangle
[21:21:42] [PASSED] well_known_colors
[21:21:42] [PASSED] destination_pitch
[21:21:42] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[21:21:42] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[21:21:42] [PASSED] single_pixel_source_buffer
[21:21:42] [PASSED] single_pixel_clip_rectangle
[21:21:42] [PASSED] well_known_colors
[21:21:42] [PASSED] destination_pitch
[21:21:42] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[21:21:42] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[21:21:42] [PASSED] single_pixel_source_buffer
[21:21:42] [PASSED] single_pixel_clip_rectangle
[21:21:42] [PASSED] well_known_colors
[21:21:42] [PASSED] destination_pitch
[21:21:42] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[21:21:42] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[21:21:42] [PASSED] single_pixel_source_buffer
[21:21:42] [PASSED] single_pixel_clip_rectangle
[21:21:42] [PASSED] well_known_colors
[21:21:42] [PASSED] destination_pitch
[21:21:42] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[21:21:42] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[21:21:42] [PASSED] single_pixel_source_buffer
[21:21:42] [PASSED] single_pixel_clip_rectangle
[21:21:42] [PASSED] well_known_colors
[21:21:42] [PASSED] destination_pitch
[21:21:42] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[21:21:42] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[21:21:42] [PASSED] single_pixel_source_buffer
[21:21:42] [PASSED] single_pixel_clip_rectangle
[21:21:42] [PASSED] well_known_colors
[21:21:42] [PASSED] destination_pitch
[21:21:42] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[21:21:42] ============== drm_test_fb_xrgb8888_to_mono  ===============
[21:21:42] [PASSED] single_pixel_source_buffer
[21:21:42] [PASSED] single_pixel_clip_rectangle
[21:21:42] [PASSED] well_known_colors
[21:21:42] [PASSED] destination_pitch
[21:21:42] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[21:21:42] ==================== drm_test_fb_swab  =====================
[21:21:42] [PASSED] single_pixel_source_buffer
[21:21:42] [PASSED] single_pixel_clip_rectangle
[21:21:42] [PASSED] well_known_colors
[21:21:42] [PASSED] destination_pitch
[21:21:42] ================ [PASSED] drm_test_fb_swab =================
[21:21:42] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[21:21:42] [PASSED] single_pixel_source_buffer
[21:21:42] [PASSED] single_pixel_clip_rectangle
[21:21:42] [PASSED] well_known_colors
[21:21:42] [PASSED] destination_pitch
[21:21:42] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[21:21:42] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[21:21:42] [PASSED] single_pixel_source_buffer
[21:21:42] [PASSED] single_pixel_clip_rectangle
[21:21:42] [PASSED] well_known_colors
[21:21:42] [PASSED] destination_pitch
[21:21:42] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[21:21:42] ================= drm_test_fb_clip_offset  =================
[21:21:42] [PASSED] pass through
[21:21:42] [PASSED] horizontal offset
[21:21:42] [PASSED] vertical offset
[21:21:42] [PASSED] horizontal and vertical offset
[21:21:42] [PASSED] horizontal offset (custom pitch)
[21:21:42] [PASSED] vertical offset (custom pitch)
[21:21:42] [PASSED] horizontal and vertical offset (custom pitch)
[21:21:42] ============= [PASSED] drm_test_fb_clip_offset =============
[21:21:42] =================== drm_test_fb_memcpy  ====================
[21:21:42] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[21:21:42] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[21:21:42] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[21:21:42] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[21:21:42] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[21:21:42] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[21:21:42] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[21:21:42] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[21:21:42] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[21:21:42] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[21:21:42] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[21:21:42] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[21:21:42] =============== [PASSED] drm_test_fb_memcpy ================
[21:21:42] ============= [PASSED] drm_format_helper_test ==============
[21:21:42] ================= drm_format (18 subtests) =================
[21:21:42] [PASSED] drm_test_format_block_width_invalid
[21:21:42] [PASSED] drm_test_format_block_width_one_plane
[21:21:42] [PASSED] drm_test_format_block_width_two_plane
[21:21:42] [PASSED] drm_test_format_block_width_three_plane
[21:21:42] [PASSED] drm_test_format_block_width_tiled
[21:21:42] [PASSED] drm_test_format_block_height_invalid
[21:21:42] [PASSED] drm_test_format_block_height_one_plane
[21:21:42] [PASSED] drm_test_format_block_height_two_plane
[21:21:42] [PASSED] drm_test_format_block_height_three_plane
[21:21:42] [PASSED] drm_test_format_block_height_tiled
[21:21:42] [PASSED] drm_test_format_min_pitch_invalid
[21:21:42] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[21:21:42] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[21:21:42] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[21:21:42] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[21:21:42] [PASSED] drm_test_format_min_pitch_two_plane
[21:21:42] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[21:21:42] [PASSED] drm_test_format_min_pitch_tiled
[21:21:42] =================== [PASSED] drm_format ====================
[21:21:42] ============== drm_framebuffer (10 subtests) ===============
[21:21:42] ========== drm_test_framebuffer_check_src_coords  ==========
[21:21:42] [PASSED] Success: source fits into fb
[21:21:42] [PASSED] Fail: overflowing fb with x-axis coordinate
[21:21:42] [PASSED] Fail: overflowing fb with y-axis coordinate
[21:21:42] [PASSED] Fail: overflowing fb with source width
[21:21:42] [PASSED] Fail: overflowing fb with source height
[21:21:42] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[21:21:42] [PASSED] drm_test_framebuffer_cleanup
[21:21:42] =============== drm_test_framebuffer_create  ===============
[21:21:42] [PASSED] ABGR8888 normal sizes
[21:21:42] [PASSED] ABGR8888 max sizes
[21:21:42] [PASSED] ABGR8888 pitch greater than min required
[21:21:42] [PASSED] ABGR8888 pitch less than min required
[21:21:42] [PASSED] ABGR8888 Invalid width
[21:21:42] [PASSED] ABGR8888 Invalid buffer handle
[21:21:42] [PASSED] No pixel format
[21:21:42] [PASSED] ABGR8888 Width 0
[21:21:42] [PASSED] ABGR8888 Height 0
[21:21:42] [PASSED] ABGR8888 Out of bound height * pitch combination
[21:21:42] [PASSED] ABGR8888 Large buffer offset
[21:21:42] [PASSED] ABGR8888 Buffer offset for inexistent plane
[21:21:42] [PASSED] ABGR8888 Invalid flag
[21:21:42] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[21:21:42] [PASSED] ABGR8888 Valid buffer modifier
[21:21:42] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[21:21:42] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[21:21:42] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[21:21:42] [PASSED] NV12 Normal sizes
[21:21:42] [PASSED] NV12 Max sizes
[21:21:42] [PASSED] NV12 Invalid pitch
[21:21:42] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[21:21:42] [PASSED] NV12 different  modifier per-plane
[21:21:42] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[21:21:42] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[21:21:42] [PASSED] NV12 Modifier for inexistent plane
[21:21:42] [PASSED] NV12 Handle for inexistent plane
[21:21:42] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[21:21:42] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[21:21:42] [PASSED] YVU420 Normal sizes
[21:21:42] [PASSED] YVU420 Max sizes
[21:21:42] [PASSED] YVU420 Invalid pitch
[21:21:42] [PASSED] YVU420 Different pitches
[21:21:42] [PASSED] YVU420 Different buffer offsets/pitches
[21:21:42] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[21:21:42] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[21:21:42] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[21:21:42] [PASSED] YVU420 Valid modifier
[21:21:42] [PASSED] YVU420 Different modifiers per plane
[21:21:42] [PASSED] YVU420 Modifier for inexistent plane
[21:21:42] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[21:21:42] [PASSED] X0L2 Normal sizes
[21:21:42] [PASSED] X0L2 Max sizes
[21:21:42] [PASSED] X0L2 Invalid pitch
[21:21:42] [PASSED] X0L2 Pitch greater than minimum required
[21:21:42] [PASSED] X0L2 Handle for inexistent plane
[21:21:42] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[21:21:42] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[21:21:42] [PASSED] X0L2 Valid modifier
[21:21:42] [PASSED] X0L2 Modifier for inexistent plane
[21:21:42] =========== [PASSED] drm_test_framebuffer_create ===========
[21:21:42] [PASSED] drm_test_framebuffer_free
[21:21:42] [PASSED] drm_test_framebuffer_init
[21:21:42] [PASSED] drm_test_framebuffer_init_bad_format
[21:21:42] [PASSED] drm_test_framebuffer_init_dev_mismatch
[21:21:42] [PASSED] drm_test_framebuffer_lookup
[21:21:42] [PASSED] drm_test_framebuffer_lookup_inexistent
[21:21:42] [PASSED] drm_test_framebuffer_modifiers_not_supported
[21:21:42] ================= [PASSED] drm_framebuffer =================
[21:21:42] ================ drm_gem_shmem (8 subtests) ================
[21:21:42] [PASSED] drm_gem_shmem_test_obj_create
[21:21:42] [PASSED] drm_gem_shmem_test_obj_create_private
[21:21:42] [PASSED] drm_gem_shmem_test_pin_pages
[21:21:42] [PASSED] drm_gem_shmem_test_vmap
[21:21:42] [PASSED] drm_gem_shmem_test_get_sg_table
[21:21:42] [PASSED] drm_gem_shmem_test_get_pages_sgt
[21:21:42] [PASSED] drm_gem_shmem_test_madvise
[21:21:42] [PASSED] drm_gem_shmem_test_purge
[21:21:42] ================== [PASSED] drm_gem_shmem ==================
[21:21:42] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[21:21:42] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[21:21:42] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[21:21:42] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[21:21:42] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[21:21:42] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[21:21:42] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[21:21:42] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[21:21:42] [PASSED] Automatic
[21:21:42] [PASSED] Full
[21:21:42] [PASSED] Limited 16:235
[21:21:42] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[21:21:42] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[21:21:42] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[21:21:42] [PASSED] drm_test_check_disable_connector
[21:21:42] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[21:21:42] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[21:21:42] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[21:21:42] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[21:21:42] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[21:21:42] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[21:21:42] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[21:21:42] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[21:21:42] [PASSED] drm_test_check_output_bpc_dvi
[21:21:42] [PASSED] drm_test_check_output_bpc_format_vic_1
[21:21:42] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[21:21:42] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[21:21:42] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[21:21:42] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[21:21:42] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[21:21:42] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[21:21:42] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[21:21:42] ============ drm_test_check_hdmi_color_format  =============
[21:21:42] [PASSED] AUTO -> RGB
[21:21:42] [PASSED] YCBCR422 -> YUV422
[21:21:42] [PASSED] YCBCR420 -> YUV420
[21:21:42] [PASSED] YCBCR444 -> YUV444
[21:21:42] [PASSED] RGB -> RGB
[21:21:42] ======== [PASSED] drm_test_check_hdmi_color_format =========
[21:21:42] ======== drm_test_check_hdmi_color_format_420_only  ========
[21:21:42] [PASSED] RGB should fail
[21:21:42] [PASSED] YUV444 should fail
[21:21:42] [PASSED] YUV422 should fail
[21:21:42] [PASSED] YUV420 should work
[21:21:42] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[21:21:42] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[21:21:42] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[21:21:42] [PASSED] drm_test_check_broadcast_rgb_value
[21:21:42] [PASSED] drm_test_check_bpc_8_value
[21:21:42] [PASSED] drm_test_check_bpc_10_value
[21:21:42] [PASSED] drm_test_check_bpc_12_value
[21:21:42] [PASSED] drm_test_check_format_value
[21:21:42] [PASSED] drm_test_check_tmds_char_value
[21:21:42] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[21:21:42] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[21:21:42] [PASSED] drm_test_check_mode_valid
[21:21:42] [PASSED] drm_test_check_mode_valid_reject
[21:21:42] [PASSED] drm_test_check_mode_valid_reject_rate
[21:21:42] [PASSED] drm_test_check_mode_valid_reject_max_clock
[21:21:42] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[21:21:42] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[21:21:42] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[21:21:42] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[21:21:42] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[21:21:42] [PASSED] drm_test_check_infoframes
[21:21:42] [PASSED] drm_test_check_reject_avi_infoframe
[21:21:42] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[21:21:42] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[21:21:42] [PASSED] drm_test_check_reject_audio_infoframe
[21:21:42] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[21:21:42] ================= drm_managed (2 subtests) =================
[21:21:42] [PASSED] drm_test_managed_release_action
[21:21:42] [PASSED] drm_test_managed_run_action
[21:21:42] =================== [PASSED] drm_managed ===================
[21:21:42] =================== drm_mm (6 subtests) ====================
[21:21:42] [PASSED] drm_test_mm_init
[21:21:42] [PASSED] drm_test_mm_debug
[21:21:42] [PASSED] drm_test_mm_align32
[21:21:42] [PASSED] drm_test_mm_align64
[21:21:42] [PASSED] drm_test_mm_lowest
[21:21:42] [PASSED] drm_test_mm_highest
[21:21:42] ===================== [PASSED] drm_mm ======================
[21:21:42] ============= drm_modes_analog_tv (5 subtests) =============
[21:21:42] [PASSED] drm_test_modes_analog_tv_mono_576i
[21:21:42] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[21:21:42] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[21:21:42] [PASSED] drm_test_modes_analog_tv_pal_576i
[21:21:42] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[21:21:42] =============== [PASSED] drm_modes_analog_tv ===============
[21:21:42] ============== drm_panic_helper (3 subtests) ===============
[21:21:42] ============= drm_test_panic_screen_user_map  ==============
[21:21:42] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[21:21:42] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[21:21:42] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[21:21:42] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[21:21:42] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[21:21:42] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[21:21:42] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[21:21:42] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[21:21:42] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[21:21:42] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[21:21:42] ========= [PASSED] drm_test_panic_screen_user_map ==========
[21:21:42] ============= drm_test_panic_screen_user_page  =============
[21:21:42] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[21:21:42] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[21:21:42] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[21:21:42] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[21:21:42] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[21:21:42] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[21:21:42] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[21:21:42] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[21:21:42] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[21:21:42] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[21:21:42] ========= [PASSED] drm_test_panic_screen_user_page =========
[21:21:42] ========== drm_test_panic_screen_user_set_pixel  ===========
[21:21:42] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[21:21:42] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[21:21:42] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[21:21:42] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[21:21:42] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[21:21:42] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[21:21:42] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[21:21:42] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[21:21:42] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[21:21:42] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[21:21:42] ====== [PASSED] drm_test_panic_screen_user_set_pixel =======
[21:21:42] ================ [PASSED] drm_panic_helper =================
[21:21:42] ============== drm_plane_helper (2 subtests) ===============
[21:21:42] =============== drm_test_check_plane_state  ================
[21:21:42] [PASSED] clipping_simple
[21:21:42] [PASSED] clipping_rotate_reflect
[21:21:42] [PASSED] positioning_simple
[21:21:42] [PASSED] upscaling
[21:21:42] [PASSED] downscaling
[21:21:42] [PASSED] rounding1
[21:21:42] [PASSED] rounding2
[21:21:42] [PASSED] rounding3
[21:21:42] [PASSED] rounding4
[21:21:42] =========== [PASSED] drm_test_check_plane_state ============
[21:21:42] =========== drm_test_check_invalid_plane_state  ============
[21:21:42] [PASSED] positioning_invalid
[21:21:42] [PASSED] upscaling_invalid
[21:21:42] [PASSED] downscaling_invalid
[21:21:42] ======= [PASSED] drm_test_check_invalid_plane_state ========
[21:21:42] ================ [PASSED] drm_plane_helper =================
[21:21:42] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[21:21:42] ====== drm_test_connector_helper_tv_get_modes_check  =======
[21:21:42] [PASSED] None
[21:21:42] [PASSED] PAL
[21:21:42] [PASSED] NTSC
[21:21:42] [PASSED] Both, NTSC Default
[21:21:42] [PASSED] Both, PAL Default
[21:21:42] [PASSED] Both, NTSC Default, with PAL on command-line
[21:21:42] [PASSED] Both, PAL Default, with NTSC on command-line
[21:21:42] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[21:21:42] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[21:21:42] ================== drm_rect (9 subtests) ===================
[21:21:42] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[21:21:42] [PASSED] drm_test_rect_clip_scaled_not_clipped
[21:21:42] [PASSED] drm_test_rect_clip_scaled_clipped
[21:21:42] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[21:21:42] ================= drm_test_rect_intersect  =================
[21:21:42] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[21:21:42] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[21:21:42] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[21:21:42] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[21:21:42] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[21:21:42] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[21:21:42] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[21:21:42] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[21:21:42] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[21:21:42] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[21:21:42] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[21:21:42] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[21:21:42] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[21:21:42] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[21:21:42] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[21:21:42] ============= [PASSED] drm_test_rect_intersect =============
[21:21:42] ================ drm_test_rect_calc_hscale  ================
[21:21:42] [PASSED] normal use
[21:21:42] [PASSED] out of max range
[21:21:42] [PASSED] out of min range
[21:21:42] [PASSED] zero dst
[21:21:42] [PASSED] negative src
[21:21:42] [PASSED] negative dst
[21:21:42] ============ [PASSED] drm_test_rect_calc_hscale ============
[21:21:42] ================ drm_test_rect_calc_vscale  ================
[21:21:42] [PASSED] normal use
[21:21:42] [PASSED] out of max range
[21:21:42] [PASSED] out of min range
[21:21:42] [PASSED] zero dst
[21:21:42] [PASSED] negative src
[21:21:42] [PASSED] negative dst
[21:21:42] ============ [PASSED] drm_test_rect_calc_vscale ============
[21:21:42] ================== drm_test_rect_rotate  ===================
[21:21:42] [PASSED] reflect-x
[21:21:42] [PASSED] reflect-y
[21:21:42] [PASSED] rotate-0
[21:21:42] [PASSED] rotate-90
[21:21:42] [PASSED] rotate-180
[21:21:42] [PASSED] rotate-270
[21:21:42] ============== [PASSED] drm_test_rect_rotate ===============
[21:21:42] ================ drm_test_rect_rotate_inv  =================
[21:21:42] [PASSED] reflect-x
[21:21:42] [PASSED] reflect-y
[21:21:42] [PASSED] rotate-0
[21:21:42] [PASSED] rotate-90
[21:21:42] [PASSED] rotate-180
[21:21:42] [PASSED] rotate-270
[21:21:42] ============ [PASSED] drm_test_rect_rotate_inv =============
[21:21:42] ==================== [PASSED] drm_rect =====================
[21:21:42] ============ drm_sysfb_modeset_test (1 subtest) ============
[21:21:42] ============ drm_test_sysfb_build_fourcc_list  =============
[21:21:42] [PASSED] no native formats
[21:21:42] [PASSED] XRGB8888 as native format
[21:21:42] [PASSED] remove duplicates
[21:21:42] [PASSED] convert alpha formats
[21:21:42] [PASSED] random formats
[21:21:42] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[21:21:42] ============= [PASSED] drm_sysfb_modeset_test ==============
[21:21:42] ================== drm_fixp (2 subtests) ===================
[21:21:42] [PASSED] drm_test_int2fixp
[21:21:42] [PASSED] drm_test_sm2fixp
[21:21:42] ==================== [PASSED] drm_fixp =====================
[21:21:42] ============================================================
[21:21:42] Testing complete. Ran 667 tests: passed: 667
[21:21:43] Elapsed time: 27.528s total, 1.866s configuring, 25.138s building, 0.469s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[21:21:43] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:21:45] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:21:55] Starting KUnit Kernel (1/1)...
[21:21:55] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:21:55] ================= ttm_device (5 subtests) ==================
[21:21:55] [PASSED] ttm_device_init_basic
[21:21:55] [PASSED] ttm_device_init_multiple
[21:21:55] [PASSED] ttm_device_fini_basic
[21:21:55] [PASSED] ttm_device_init_no_vma_man
[21:21:55] ================== ttm_device_init_pools  ==================
[21:21:55] [PASSED] No DMA allocations, no DMA32 required
[21:21:55] [PASSED] DMA allocations, DMA32 required
[21:21:55] [PASSED] No DMA allocations, DMA32 required
[21:21:55] [PASSED] DMA allocations, no DMA32 required
[21:21:55] ============== [PASSED] ttm_device_init_pools ==============
[21:21:55] =================== [PASSED] ttm_device ====================
[21:21:55] ================== ttm_pool (8 subtests) ===================
[21:21:55] ================== ttm_pool_alloc_basic  ===================
[21:21:55] [PASSED] One page
[21:21:55] [PASSED] More than one page
[21:21:55] [PASSED] Above the allocation limit
[21:21:55] [PASSED] One page, with coherent DMA mappings enabled
[21:21:55] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:21:55] ============== [PASSED] ttm_pool_alloc_basic ===============
[21:21:55] ============== ttm_pool_alloc_basic_dma_addr  ==============
[21:21:55] [PASSED] One page
[21:21:55] [PASSED] More than one page
[21:21:55] [PASSED] Above the allocation limit
[21:21:55] [PASSED] One page, with coherent DMA mappings enabled
[21:21:55] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:21:55] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[21:21:55] [PASSED] ttm_pool_alloc_order_caching_match
[21:21:55] [PASSED] ttm_pool_alloc_caching_mismatch
[21:21:55] [PASSED] ttm_pool_alloc_order_mismatch
[21:21:55] [PASSED] ttm_pool_free_dma_alloc
[21:21:55] [PASSED] ttm_pool_free_no_dma_alloc
[21:21:55] [PASSED] ttm_pool_fini_basic
[21:21:55] ==================== [PASSED] ttm_pool =====================
[21:21:55] ================ ttm_resource (8 subtests) =================
[21:21:55] ================= ttm_resource_init_basic  =================
[21:21:55] [PASSED] Init resource in TTM_PL_SYSTEM
[21:21:55] [PASSED] Init resource in TTM_PL_VRAM
[21:21:55] [PASSED] Init resource in a private placement
[21:21:55] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[21:21:55] ============= [PASSED] ttm_resource_init_basic =============
[21:21:55] [PASSED] ttm_resource_init_pinned
[21:21:55] [PASSED] ttm_resource_fini_basic
[21:21:55] [PASSED] ttm_resource_manager_init_basic
[21:21:55] [PASSED] ttm_resource_manager_usage_basic
[21:21:55] [PASSED] ttm_resource_manager_set_used_basic
[21:21:55] [PASSED] ttm_sys_man_alloc_basic
[21:21:55] [PASSED] ttm_sys_man_free_basic
[21:21:55] ================== [PASSED] ttm_resource ===================
[21:21:55] =================== ttm_tt (15 subtests) ===================
[21:21:55] ==================== ttm_tt_init_basic  ====================
[21:21:55] [PASSED] Page-aligned size
[21:21:55] [PASSED] Extra pages requested
[21:21:55] ================ [PASSED] ttm_tt_init_basic ================
[21:21:55] [PASSED] ttm_tt_init_misaligned
[21:21:55] [PASSED] ttm_tt_fini_basic
[21:21:55] [PASSED] ttm_tt_fini_sg
[21:21:55] [PASSED] ttm_tt_fini_shmem
[21:21:55] [PASSED] ttm_tt_create_basic
[21:21:55] [PASSED] ttm_tt_create_invalid_bo_type
[21:21:55] [PASSED] ttm_tt_create_ttm_exists
[21:21:55] [PASSED] ttm_tt_create_failed
[21:21:55] [PASSED] ttm_tt_destroy_basic
[21:21:55] [PASSED] ttm_tt_populate_null_ttm
[21:21:55] [PASSED] ttm_tt_populate_populated_ttm
[21:21:55] [PASSED] ttm_tt_unpopulate_basic
[21:21:55] [PASSED] ttm_tt_unpopulate_empty_ttm
[21:21:55] [PASSED] ttm_tt_swapin_basic
[21:21:55] ===================== [PASSED] ttm_tt ======================
[21:21:55] =================== ttm_bo (14 subtests) ===================
[21:21:55] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[21:21:55] [PASSED] Cannot be interrupted and sleeps
[21:21:55] [PASSED] Cannot be interrupted, locks straight away
[21:21:55] [PASSED] Can be interrupted, sleeps
[21:21:55] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[21:21:55] [PASSED] ttm_bo_reserve_locked_no_sleep
[21:21:55] [PASSED] ttm_bo_reserve_no_wait_ticket
[21:21:55] [PASSED] ttm_bo_reserve_double_resv
[21:21:55] [PASSED] ttm_bo_reserve_interrupted
[21:21:55] [PASSED] ttm_bo_reserve_deadlock
[21:21:55] [PASSED] ttm_bo_unreserve_basic
[21:21:55] [PASSED] ttm_bo_unreserve_pinned
[21:21:55] [PASSED] ttm_bo_unreserve_bulk
[21:21:55] [PASSED] ttm_bo_fini_basic
[21:21:55] [PASSED] ttm_bo_fini_shared_resv
[21:21:55] [PASSED] ttm_bo_pin_basic
[21:21:55] [PASSED] ttm_bo_pin_unpin_resource
[21:21:55] [PASSED] ttm_bo_multiple_pin_one_unpin
[21:21:55] ===================== [PASSED] ttm_bo ======================
[21:21:55] ============== ttm_bo_validate (22 subtests) ===============
[21:21:55] ============== ttm_bo_init_reserved_sys_man  ===============
[21:21:55] [PASSED] Buffer object for userspace
[21:21:55] [PASSED] Kernel buffer object
[21:21:55] [PASSED] Shared buffer object
[21:21:55] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[21:21:55] ============== ttm_bo_init_reserved_mock_man  ==============
[21:21:55] [PASSED] Buffer object for userspace
[21:21:55] [PASSED] Kernel buffer object
[21:21:55] [PASSED] Shared buffer object
[21:21:55] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[21:21:55] [PASSED] ttm_bo_init_reserved_resv
[21:21:55] ================== ttm_bo_validate_basic  ==================
[21:21:55] [PASSED] Buffer object for userspace
[21:21:55] [PASSED] Kernel buffer object
[21:21:55] [PASSED] Shared buffer object
[21:21:55] ============== [PASSED] ttm_bo_validate_basic ==============
[21:21:55] [PASSED] ttm_bo_validate_invalid_placement
[21:21:55] ============= ttm_bo_validate_same_placement  ==============
[21:21:55] [PASSED] System manager
[21:21:55] [PASSED] VRAM manager
[21:21:55] ========= [PASSED] ttm_bo_validate_same_placement ==========
[21:21:55] [PASSED] ttm_bo_validate_failed_alloc
[21:21:55] [PASSED] ttm_bo_validate_pinned
[21:21:55] [PASSED] ttm_bo_validate_busy_placement
[21:21:55] ================ ttm_bo_validate_multihop  =================
[21:21:55] [PASSED] Buffer object for userspace
[21:21:55] [PASSED] Kernel buffer object
[21:21:55] [PASSED] Shared buffer object
[21:21:55] ============ [PASSED] ttm_bo_validate_multihop =============
[21:21:55] ========== ttm_bo_validate_no_placement_signaled  ==========
[21:21:55] [PASSED] Buffer object in system domain, no page vector
[21:21:55] [PASSED] Buffer object in system domain with an existing page vector
[21:21:55] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[21:21:55] ======== ttm_bo_validate_no_placement_not_signaled  ========
[21:21:55] [PASSED] Buffer object for userspace
[21:21:55] [PASSED] Kernel buffer object
[21:21:55] [PASSED] Shared buffer object
[21:21:55] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[21:21:55] [PASSED] ttm_bo_validate_move_fence_signaled
[21:21:55] ========= ttm_bo_validate_move_fence_not_signaled  =========
[21:21:55] [PASSED] Waits for GPU
[21:21:55] [PASSED] Tries to lock straight away
[21:21:55] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[21:21:55] [PASSED] ttm_bo_validate_swapout
[21:21:55] [PASSED] ttm_bo_validate_happy_evict
[21:21:55] [PASSED] ttm_bo_validate_all_pinned_evict
[21:21:55] [PASSED] ttm_bo_validate_allowed_only_evict
[21:21:55] [PASSED] ttm_bo_validate_deleted_evict
[21:21:55] [PASSED] ttm_bo_validate_busy_domain_evict
[21:21:55] [PASSED] ttm_bo_validate_evict_gutting
[21:21:55] [PASSED] ttm_bo_validate_recrusive_evict
[21:21:55] ================= [PASSED] ttm_bo_validate =================
[21:21:55] ============================================================
[21:21:55] Testing complete. Ran 102 tests: passed: 102
[21:21:55] Elapsed time: 12.166s total, 1.897s configuring, 10.055s building, 0.178s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[21:21:55] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:21:57] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:22:06] Starting KUnit Kernel (1/1)...
[21:22:06] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:22:06] =============== dma-buf-fence (12 subtests) ================
[21:22:06] [PASSED] test_sanitycheck
[21:22:06] [PASSED] test_signaling
[21:22:06] [PASSED] test_add_callback
[21:22:06] [PASSED] test_late_add_callback
[21:22:06] [PASSED] test_rm_callback
[21:22:06] [PASSED] test_late_rm_callback
[21:22:06] [PASSED] test_status
[21:22:06] [PASSED] test_error
[21:22:06] [PASSED] test_wait
[21:22:06] [PASSED] test_wait_timeout
[21:22:06] [PASSED] test_stub
[21:22:06] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[21:22:06] ================== [PASSED] dma-buf-fence ==================
[21:22:06] ============ dma-buf-fence-chain (11 subtests) =============
[21:22:06] [PASSED] test_sanitycheck
[21:22:06] [PASSED] test_find_seqno
[21:22:06] [PASSED] test_find_signaled
[21:22:06] [PASSED] test_find_out_of_order
[21:22:11] [PASSED] test_find_gap
[21:22:11] [PASSED] test_find_race
[21:22:11] [PASSED] test_signal_forward
[21:22:11] [PASSED] test_signal_backward
[21:22:11] [PASSED] test_wait_forward
[21:22:11] [PASSED] test_wait_backward
[21:22:11] [PASSED] test_wait_random
[21:22:11] =============== [PASSED] dma-buf-fence-chain ===============
[21:22:11] ============ dma-buf-fence-unwrap (11 subtests) ============
[21:22:11] [PASSED] test_sanitycheck
[21:22:11] [PASSED] test_unwrap_array
[21:22:11] [PASSED] test_unwrap_chain
[21:22:11] [PASSED] test_unwrap_chain_array
[21:22:11] [PASSED] test_unwrap_merge
[21:22:11] [PASSED] test_unwrap_merge_duplicate
[21:22:11] [PASSED] test_unwrap_merge_seqno
[21:22:11] [PASSED] test_unwrap_merge_order
[21:22:11] [PASSED] test_unwrap_merge_complex
[21:22:11] [PASSED] test_unwrap_merge_complex_seqno
[21:22:11] [PASSED] test_dedup_empty
[21:22:11] ============== [PASSED] dma-buf-fence-unwrap ===============
[21:22:11] ================ dma-buf-resv (5 subtests) =================
[21:22:11] [PASSED] test_sanitycheck
[21:22:11] ===================== test_signaling  ======================
[21:22:11] [PASSED] kernel
[21:22:11] [PASSED] write
[21:22:11] [PASSED] read
[21:22:11] [PASSED] bookkeep
[21:22:11] ================= [PASSED] test_signaling ==================
[21:22:11] ====================== test_for_each  ======================
[21:22:11] [PASSED] kernel
[21:22:11] [PASSED] write
[21:22:11] [PASSED] read
[21:22:11] [PASSED] bookkeep
[21:22:11] ================== [PASSED] test_for_each ==================
[21:22:11] ================= test_for_each_unlocked  ==================
[21:22:11] [PASSED] kernel
[21:22:11] [PASSED] write
[21:22:11] [PASSED] read
[21:22:11] [PASSED] bookkeep
[21:22:11] ============= [PASSED] test_for_each_unlocked ==============
[21:22:11] ===================== test_get_fences  =====================
[21:22:11] [PASSED] kernel
[21:22:11] [PASSED] write
[21:22:11] [PASSED] read
[21:22:11] [PASSED] bookkeep
[21:22:11] ================= [PASSED] test_get_fences =================
[21:22:11] ================== [PASSED] dma-buf-resv ===================
[21:22:11] ============================================================
[21:22:11] Testing complete. Ran 51 tests: passed: 50, skipped: 1
[21:22:11] Elapsed time: 15.828s total, 1.824s configuring, 8.733s building, 5.257s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

Re: [PATCH 04/10] drm/xe: Factor out {min,max}_idledly_ps in adjust_idledly()

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/xe: 32-bit multiplication overflow in adjust_idledly()
--

commit 032b173104de210ca0228dd31e057951f3cde20d
Author: Gustavo Sousa <gustavo.sousa@intel.com>

drm/xe: Factor out {min,max}_idledly_ps in adjust_idledly()

This commit reorganizes adjust_idledly() so that workaround-specific logic
computes min_idledly_ps and max_idledly_ps before applying and rounding
those limits to the RING_IDLEDLY register field.

> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index dcc8a6d53c5d0..2d2a80cc2da35 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -585,99 +585,81 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
>  	xe_reg_whitelist_process_engine(hwe);
>  }
>  
> -static u32 idledly_floor_ticks(u64 idledly_ps, u32 idledly_units_ps)
> -{
> -	return DIV_ROUND_DOWN_ULL(idledly_ps, idledly_units_ps);
> -}
> -
>  static void adjust_idledly(struct xe_hw_engine *hwe)
>  {
>  	struct xe_gt *gt = hwe->gt;
> -	u32 idledly_reg_val, maxcnt_reg_val;
> +	u32 idledly_reg_val;
> +	u32 idledly;
>  	u32 idledly_units_ps = 8 * gt->info.timestamp_base;
> -	u32 maxcnt_units_ps = 640000;
>  	u64 idledly_ps, idledly_hw_ps;
> -	u64 maxcnt_ps;
> +	u64 min_idledly_ps = 0;
> +	u64 max_idledly_ps = -1;
>  	bool inhibit_switch = false;
>  	bool wa_applied = false;
> -	bool clamped_below_maxcnt = false;
>  
>  	if (IS_SRIOV_VF(gt_to_xe(gt)))
>  		return;
>  
>  	if (XE_GT_WA(gt, 16023105232) || XE_GT_WA(gt, 14025941587)) {
> -		u32 mincnt_idledly_ps = 5000000;
> -
>  		/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
>  		if (!idledly_units_ps)
>  			return;
>  
>  		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
>  		inhibit_switch = idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED;
> -		idledly_ps = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val) * idledly_units_ps;
> +		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
> +		idledly_ps = idledly * idledly_units_ps;
>  		idledly_hw_ps = idledly_ps;
>  
> -		maxcnt_reg_val = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
> -		maxcnt_ps = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt_reg_val) * maxcnt_units_ps;
> -
> -		/*
> -		 * Wa_14025941587 is applied before Wa_16023105232, which takes
> -		 * priority if the two ever conflict (not expected in practice).
> -		 */
> -		if (XE_GT_WA(gt, 14025941587) &&
> -		    idledly_ps < mincnt_idledly_ps) {
> -			idledly_ps = mincnt_idledly_ps;
> -			wa_applied = true;
> -		}
> +		if (XE_GT_WA(gt, 14025941587))
> +			min_idledly_ps = max(min_idledly_ps, 5000000);
>  
>  		if (XE_GT_WA(gt, 16023105232)) {
> +			u32 maxcnt_units_ps = 640000;
> +			u32 maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
> +
> +			max_idledly_ps = min_t(u64,
> +					       max_idledly_ps,
> +					       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
> +
>  			/* Clear the inhibit switch without disturbing a valid delay. */
>  			if (inhibit_switch) {
>  				idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
>  				wa_applied = true;
>  			}
> +		}
>  
> -			/* Warn only on the value read from hardware. */
> -			xe_gt_WARN_ON(gt, idledly_hw_ps >= maxcnt_ps);
> +		/*
> +		 * min_idledly_ps is applied before max_idledly_ps, which takes
> +		 * priority if the two ever conflict (not expected in practice).
> +		 */
> +		if (idledly_ps < min_idledly_ps) {
> +			idledly = DIV_ROUND_UP_ULL(min_idledly_ps, idledly_units_ps);
> +			idledly_ps = idledly * idledly_units_ps;
> +			wa_applied = true;
> +		}
>  
> -			if (idledly_ps >= maxcnt_ps) {
> -				/* maxcnt may be 0 if IDLE_WAIT_TIME is unprogrammed. */
> -				idledly_ps = maxcnt_ps ? maxcnt_ps - 1 : 0;
> -				clamped_below_maxcnt = true;
> -				wa_applied = true;
> +		if (idledly_ps >= max_idledly_ps) {
> +			if (max_idledly_ps) {
> +				idledly = DIV_ROUND_DOWN_ULL(max_idledly_ps - 1, idledly_units_ps);
> +				idledly_ps = idledly * idledly_units_ps;

[Severity: Medium]
Can these tick-to-picosecond multiplications in adjust_idledly() in
drivers/gpu/drm/xe/xe_hw_engine.c overflow 32 bits before being widened to
u64?

When hw_engine_init() calls adjust_idledly() on non-VF platforms where
Wa_16023105232 or Wa_14025941587 is active, idledly, idledly_units_ps (up to
8 * 83333 = 666,664 ps), maxcnt_units_ps (640,000 ps), and the return value
of REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) are all u32.

In the three assignments:

	idledly_ps = idledly * idledly_units_ps;

both operands are u32. Since IDLE_DELAY is a 21-bit field (REG_GENMASK(20, 0),
up to 2,097,151 ticks), the product can reach ~1.398e12 ps and wraps modulo
2^32 for idledly >= 6443 ticks before assignment to u64 idledly_ps.

Similarly, in:

	max_idledly_ps = min_t(u64,
			       max_idledly_ps,
			       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);

REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps is evaluated in 32-bit
unsigned arithmetic before min_t(u64, ...) casts the result to u64. Because
IDLE_WAIT_TIME is a 20-bit field (REG_GENMASK(19, 0), up to 1,048,575 ticks),
the product can reach ~6.71e11 ps and wraps 32 bits for IDLE_WAIT_TIME >= 6711
ticks, which can misprogram RING_IDLEDLY or trigger false
xe_gt_WARN_ON(gt, idledly_hw_ps >= max_idledly_ps) warnings.

Commit d864065ea25e ("drm/xe: harden adjust_idledly() against divide-by-zero
and overflow") previously added explicit (u64) casts to prevent 32-bit
truncation when converting ticks to time units. Should idledly_units_ps and
maxcnt_units_ps (or the multiplication operands) be promoted to u64 here as
well?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261023-wa_16031259911-v1-0-b0453f79c4e1@intel.com?part=4

✓ Xe.CI.BAT: success for drm/xe: Clean up adjust_idledly() and implement Wa_16031259911

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1595 bytes --]

== Series Details ==

Series: drm/xe: Clean up adjust_idledly() and implement Wa_16031259911
URL   : https://patchwork.freedesktop.org/series/176761/
State : success

== Summary ==

CI Bug Log - changes from xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766_BAT -> xe-pw-176761v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (15 -> 15)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-176761v1_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_live_ktest@xe_migrate@xe_migrate_access_memory_kunit:
    - bat-atsm-2:         [PASS][1] -> [ABORT][2] ([Intel XE#9663]) +1 other test abort
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/bat-atsm-2/igt@xe_live_ktest@xe_migrate@xe_migrate_access_memory_kunit.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/bat-atsm-2/igt@xe_live_ktest@xe_migrate@xe_migrate_access_memory_kunit.html

  
  [Intel XE#9663]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9663


Build changes
-------------

  * IGT: IGT_9161 -> IGT_9162
  * Linux: xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766 -> xe-pw-176761v1

  IGT_9161: 9161
  IGT_9162: 9162
  xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766: b255dd13059988fddde9ea187d1dd1017c9a5766
  xe-pw-176761v1: 176761v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/index.html

[-- Attachment #2: Type: text/html, Size: 2174 bytes --]

Re: [PATCH 03/10] drm/xe: Use picosecond as common unit in adjust_idledly()

[Gustavo Sousa]

sashiko-bot@kernel.org writes:

> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [High] drm/xe: 32-bit multiplication overflow in adjust_idledly()
> --
>
> commit 6274ddb08f811b772af3c2cc759b8be4b565872c
> Author: Gustavo Sousa <gustavo.sousa@intel.com>
>
> drm/xe: Use picosecond as common unit in adjust_idledly()
>
> This commit changes adjust_idledly() to use picoseconds instead of
> nanoseconds as the common unit of time to avoid precision loss and
> eliminate extra integer divisions.
>
>> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
>> index 6872d1ca656e2..dcc8a6d53c5d0 100644
>> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
>> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
>> @@ -585,17 +585,19 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
>>  	xe_reg_whitelist_process_engine(hwe);
>>  }
>>  
>> -static u32 idledly_floor_ticks(u32 idledly_ns, u32 idledly_units_ps)
>> +static u32 idledly_floor_ticks(u64 idledly_ps, u32 idledly_units_ps)
>>  {
>> -	return DIV_ROUND_DOWN_ULL((u64)idledly_ns * 1000, idledly_units_ps);
>> +	return DIV_ROUND_DOWN_ULL(idledly_ps, idledly_units_ps);
>>  }
>>  
>>  static void adjust_idledly(struct xe_hw_engine *hwe)
>>  {
>>  	struct xe_gt *gt = hwe->gt;
>> -	u32 idledly, idledly_hw, idledly_reg_val, maxcnt;
>> +	u32 idledly_reg_val, maxcnt_reg_val;
>>  	u32 idledly_units_ps = 8 * gt->info.timestamp_base;
>> -	u32 maxcnt_units_ns = 640;
>> +	u32 maxcnt_units_ps = 640000;
>> +	u64 idledly_ps, idledly_hw_ps;
>> +	u64 maxcnt_ps;
>>  	bool inhibit_switch = false;
>>  	bool wa_applied = false;
>>  	bool clamped_below_maxcnt = false;
>> @@ -604,29 +606,27 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>>  		return;
>>  
>>  	if (XE_GT_WA(gt, 16023105232) || XE_GT_WA(gt, 14025941587)) {
>> -		u32 mincnt_idledly_ns = 5000;
>> +		u32 mincnt_idledly_ps = 5000000;
>>  
>>  		/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
>>  		if (!idledly_units_ps)
>>  			return;
>>  
>>  		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
>> -		maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
>> -
>>  		inhibit_switch = idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED;
>> -		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
>> -		idledly = DIV_ROUND_CLOSEST_ULL((u64)idledly * idledly_units_ps, 1000);
>> -		idledly_hw = idledly;
>> -		maxcnt = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt);
>> -		maxcnt *= maxcnt_units_ns;
>> +		idledly_ps = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val) * idledly_units_ps;
>> +		idledly_hw_ps = idledly_ps;
>> +
>> +		maxcnt_reg_val = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
>> +		maxcnt_ps = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt_reg_val) * maxcnt_units_ps;
>
> [Severity: High]
> Can the multiplications computing idledly_ps and maxcnt_ps in
> adjust_idledly() overflow 32-bit unsigned arithmetic before being widened
> to u64?
>
> In include/drm/intel/reg_bits.h, REG_FIELD_GET() returns a u32:
>
>     #define REG_FIELD_GET(__mask, __val)	((u32)FIELD_GET(__mask, __val))
>
> Because idledly_units_ps and maxcnt_units_ps are both declared as u32,
> both multiplications are evaluated in 32-bit arithmetic before assignment
> to u64 idledly_ps and u64 maxcnt_ps.
>
> For idledly_ps, dropping the (u64) cast that was added in commit
> d864065ea25e ("drm/xe: harden adjust_idledly() against divide-by-zero and
> overflow") means IDLE_DELAY (a 21-bit field, REG_GENMASK(20, 0)) multiplied
> by idledly_units_ps (up to 666,664 ps) wraps around U32_MAX whenever
> IDLE_DELAY is >= 6443 ticks.
>
> Similarly, for maxcnt_ps, scaling the unit multiplier from 640 ns to
> 640,000 ps in u32 means IDLE_WAIT_TIME (a 20-bit field, REG_GENMASK(19, 0))
> multiplied by maxcnt_units_ps wraps around U32_MAX whenever IDLE_WAIT_TIME
> is >= 6711 ticks (~4.29 ms out of its ~671 ms range).
>
> When either product wraps, xe_gt_WARN_ON(gt, idledly_hw_ps >= maxcnt_ps)
> can trigger spuriously, and the Wa_14025941587 and Wa_16023105232 checks
> can program a corrupted IDLE_DELAY tick count into RING_IDLEDLY.
>
> Should idledly_units_ps and maxcnt_units_ps be declared as u64 (or the
> operands cast to u64 before multiplying)?

Thanks for catching this. I'll make sure to add the cast to u64 to the
operations in v2.

--
Gustavo Sousa

>
> -- 
> Sashiko AI review · https://sashiko.dev/#/patchset/20261023-wa_16031259911-v1-0-b0453f79c4e1@intel.com?part=3

✗ Xe.CI.FULL: failure for drm/xe: Clean up adjust_idledly() and implement Wa_16031259911

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 59853 bytes --]

== Series Details ==

Series: drm/xe: Clean up adjust_idledly() and implement Wa_16031259911
URL   : https://patchwork.freedesktop.org/series/176761/
State : failure

== Summary ==

CI Bug Log - changes from xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766_FULL -> xe-pw-176761v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-176761v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-176761v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (3 -> 3)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-176761v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_chamelium_hpd@dp-hpd-after-runtime-suspend-d3hot:
    - shard-lnl:          NOTRUN -> [SKIP][1] +1 other test skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-6/igt@kms_chamelium_hpd@dp-hpd-after-runtime-suspend-d3hot.html

  * igt@kms_chamelium_hpd@hdmi-hpd-after-runtime-suspend-d3hot:
    - shard-bmg:          NOTRUN -> [SKIP][2]
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-2/igt@kms_chamelium_hpd@hdmi-hpd-after-runtime-suspend-d3hot.html
    - shard-ptl:          NOTRUN -> [SKIP][3]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-7/igt@kms_chamelium_hpd@hdmi-hpd-after-runtime-suspend-d3hot.html

  * igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier:
    - shard-ptl:          [PASS][4] -> [FAIL][5] +1 other test fail
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-ptl-8/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-2/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier.html

  
Known issues
------------

  Here are the changes found in xe-pw-176761v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-ptl:          NOTRUN -> [SKIP][6] ([Intel XE#3157])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-3/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-ptl:          NOTRUN -> [SKIP][7] ([Intel XE#6925])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-7/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@linear-32bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2327]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-4/igt@kms_big_fb@linear-32bpp-rotate-90.html
    - shard-ptl:          NOTRUN -> [SKIP][9] ([Intel XE#5901]) +2 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-6/igt@kms_big_fb@linear-32bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-90:
    - shard-lnl:          NOTRUN -> [SKIP][10] ([Intel XE#1407]) +3 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-4/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-ptl:          NOTRUN -> [SKIP][11] ([Intel XE#5808]) +6 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][12] ([Intel XE#1124])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#1124]) +1 other test skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_bw@linear-tiling-2-displays-target-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][14] ([Intel XE#367])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-3/igt@kms_bw@linear-tiling-2-displays-target-2160x1440p.html

  * igt@kms_bw@linear-tiling-4-displays-target-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#367])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-7/igt@kms_bw@linear-tiling-4-displays-target-3840x2160p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#2669] / [Intel XE#7389]) +3 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-2/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-a-edp-1.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-c-edp-1:
    - shard-ptl:          NOTRUN -> [SKIP][17] ([Intel XE#5823] / [Intel XE#6918]) +4 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-5/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-c-edp-1.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc:
    - shard-ptl:          NOTRUN -> [SKIP][18] ([Intel XE#5822]) +11 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-3/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#3432])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#2887]) +6 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-5/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][21] ([Intel XE#2887]) +5 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-6/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs.html

  * igt@kms_chamelium_audio@dp-audio:
    - shard-ptl:          NOTRUN -> [SKIP][22] ([Intel XE#2252]) +3 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-3/igt@kms_chamelium_audio@dp-audio.html

  * igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt709:
    - shard-ptl:          NOTRUN -> [SKIP][23] ([Intel XE#8391]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-5/igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt709.html

  * igt@kms_chamelium_color_pipeline@plane-lut1d-ctm3x4:
    - shard-lnl:          NOTRUN -> [SKIP][24] ([Intel XE#7358]) +3 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-4/igt@kms_chamelium_color_pipeline@plane-lut1d-ctm3x4.html

  * igt@kms_chamelium_edid@hdmi-mode-timings:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#373]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-2/igt@kms_chamelium_edid@hdmi-mode-timings.html

  * igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#2252]) +4 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-3/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-ptl:          NOTRUN -> [SKIP][27] ([Intel XE#7642])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-5/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-type-1-suspend-resume:
    - shard-ptl:          NOTRUN -> [SKIP][28] ([Intel XE#6974])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-6/igt@kms_content_protection@dp-mst-type-1-suspend-resume.html
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#6974])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-6/igt@kms_content_protection@dp-mst-type-1-suspend-resume.html

  * igt@kms_content_protection@legacy:
    - shard-bmg:          NOTRUN -> [FAIL][30] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-7/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@legacy@pipe-a-dp-1:
    - shard-bmg:          NOTRUN -> [FAIL][31] ([Intel XE#3304]) +1 other test fail
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-7/igt@kms_content_protection@legacy@pipe-a-dp-1.html

  * igt@kms_cursor_crc@cursor-offscreen-128x42:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#2320]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-10/igt@kms_cursor_crc@cursor-offscreen-128x42.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-lnl:          NOTRUN -> [SKIP][33] ([Intel XE#1424])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-8/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_crc@cursor-sliding-32x32:
    - shard-ptl:          NOTRUN -> [SKIP][34] ([Intel XE#5900]) +3 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-7/igt@kms_cursor_crc@cursor-sliding-32x32.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-ptl:          NOTRUN -> [SKIP][35] ([Intel XE#5846])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-3/igt@kms_cursor_crc@cursor-sliding-512x170.html
    - shard-lnl:          NOTRUN -> [SKIP][36] ([Intel XE#2321] / [Intel XE#7355])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-1/igt@kms_cursor_crc@cursor-sliding-512x170.html
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#2321] / [Intel XE#7355])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-7/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-ptl:          NOTRUN -> [SKIP][38] ([Intel XE#5962]) +1 other test skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-1/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
    - shard-lnl:          NOTRUN -> [SKIP][39] ([Intel XE#309] / [Intel XE#7343]) +2 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-5/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_dirtyfb@psr-dirtyfb-ioctl:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#1508])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-10/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#1340] / [Intel XE#7435])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3.html

  * igt@kms_dp_linktrain_fallback@uhbr-to-hbr-fallback:
    - shard-ptl:          NOTRUN -> [SKIP][42] ([Intel XE#9009])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-3/igt@kms_dp_linktrain_fallback@uhbr-to-hbr-fallback.html
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#9009])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-4/igt@kms_dp_linktrain_fallback@uhbr-to-hbr-fallback.html

  * igt@kms_dsc@dsc-basic-bigjoiner:
    - shard-ptl:          NOTRUN -> [SKIP][44] ([Intel XE#5907]) +2 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-3/igt@kms_dsc@dsc-basic-bigjoiner.html
    - shard-lnl:          NOTRUN -> [SKIP][45] ([Intel XE#8265])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-2/igt@kms_dsc@dsc-basic-bigjoiner.html

  * igt@kms_dsc@dsc-with-bpc-formats-bigjoiner:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#8265])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-4/igt@kms_dsc@dsc-with-bpc-formats-bigjoiner.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#4422] / [Intel XE#7442])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-3/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#8680])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-5/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@display-2x:
    - shard-lnl:          NOTRUN -> [SKIP][49] ([Intel XE#702] / [Intel XE#7344])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-3/igt@kms_feature_discovery@display-2x.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible:
    - shard-ptl:          NOTRUN -> [SKIP][50] ([Intel XE#2316]) +2 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-7/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html

  * igt@kms_flip@2x-flip-vs-rmfb-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][51] ([Intel XE#1421]) +2 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-4/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html

  * igt@kms_flip@flip-vs-blocking-wf-vblank:
    - shard-bmg:          [PASS][52] -> [FAIL][53] ([Intel XE#5408] / [Intel XE#6266]) +1 other test fail
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-bmg-3/igt@kms_flip@flip-vs-blocking-wf-vblank.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-4/igt@kms_flip@flip-vs-blocking-wf-vblank.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling:
    - shard-ptl:          NOTRUN -> [SKIP][54] ([Intel XE#7178]) +3 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-2/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#7178] / [Intel XE#7351])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-6/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-nv12-linear-to-nv12-linear-reflect-x:
    - shard-lnl:          NOTRUN -> [SKIP][56] ([Intel XE#7179])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-3/igt@kms_flip_scaled_crc@flip-nv12-linear-to-nv12-linear-reflect-x.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#2311]) +20 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-plflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][58] ([Intel XE#656] / [Intel XE#7905]) +19 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-5/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary:
    - shard-lnl:          NOTRUN -> [SKIP][59] ([Intel XE#6312] / [Intel XE#651]) +4 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-2/igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-cur-indfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][60] ([Intel XE#6312]) +2 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-8/igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrshdr-rgb565-draw-render:
    - shard-ptl:          NOTRUN -> [SKIP][61] ([Intel XE#6312]) +10 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-1/igt@kms_frontbuffer_tracking@drrshdr-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#4141]) +2 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#7061] / [Intel XE#7356]) +2 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-msflip-blt:
    - shard-ptl:          NOTRUN -> [SKIP][64] ([Intel XE#5800] / [Intel XE#6312]) +6 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-8/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-move:
    - shard-ptl:          NOTRUN -> [SKIP][65] ([Intel XE#7865]) +18 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-2/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][66] ([Intel XE#7865]) +14 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-4/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][67] ([Intel XE#7061]) +3 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-render.html
    - shard-ptl:          NOTRUN -> [SKIP][68] ([Intel XE#7061]) +3 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-4/igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-argb161616f-draw-blt:
    - shard-ptl:          NOTRUN -> [SKIP][69] ([Intel XE#7061] / [Intel XE#7356]) +1 other test skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-7/igt@kms_frontbuffer_tracking@fbcpsr-argb161616f-draw-blt.html
    - shard-lnl:          NOTRUN -> [SKIP][70] ([Intel XE#7061] / [Intel XE#7356])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcpsr-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][71] ([Intel XE#2313]) +16 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-indfb-plflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][72] ([Intel XE#7905]) +22 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-shrfb-msflip-blt:
    - shard-ptl:          NOTRUN -> [SKIP][73] ([Intel XE#5812]) +45 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-4/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@hdr-argb161616f-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][74] ([Intel XE#7061]) +2 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-4/igt@kms_frontbuffer_tracking@hdr-argb161616f-draw-render.html

  * igt@kms_hdmi_audio_bw@audio-bw-hblank80:
    - shard-bmg:          [PASS][75] -> [FAIL][76] ([Intel XE#9313])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-bmg-2/igt@kms_hdmi_audio_bw@audio-bw-hblank80.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-4/igt@kms_hdmi_audio_bw@audio-bw-hblank80.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-ptl:          NOTRUN -> [SKIP][77] ([Intel XE#6901]) +1 other test skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-2/igt@kms_joiner@basic-big-joiner.html
    - shard-lnl:          NOTRUN -> [SKIP][78] ([Intel XE#6901]) +1 other test skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-6/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_plane@pixel-format-4-tiled-modifier@pipe-a-plane-5:
    - shard-bmg:          NOTRUN -> [SKIP][79] ([Intel XE#8303]) +1 other test skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-4/igt@kms_plane@pixel-format-4-tiled-modifier@pipe-a-plane-5.html
    - shard-ptl:          NOTRUN -> [SKIP][80] ([Intel XE#8303]) +1 other test skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-5/igt@kms_plane@pixel-format-4-tiled-modifier@pipe-a-plane-5.html

  * igt@kms_plane@pixel-format-x-tiled-modifier@pipe-b-plane-5:
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#8303]) +1 other test skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-8/igt@kms_plane@pixel-format-x-tiled-modifier@pipe-b-plane-5.html

  * igt@kms_plane@pixel-format-y-tiled-ccs-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][82] ([Intel XE#7283]) +1 other test skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-3/igt@kms_plane@pixel-format-y-tiled-ccs-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-modifier-source-clamping:
    - shard-lnl:          NOTRUN -> [SKIP][83] ([Intel XE#7283]) +2 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-5/igt@kms_plane@pixel-format-y-tiled-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping:
    - shard-ptl:          NOTRUN -> [SKIP][84] ([Intel XE#7283]) +2 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-4/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-ptl:          NOTRUN -> [SKIP][85] ([Intel XE#4596] / [Intel XE#5854]) +1 other test skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-1/igt@kms_plane_multiple@2x-tiling-none.html
    - shard-lnl:          NOTRUN -> [SKIP][86] ([Intel XE#4596] / [Intel XE#5854])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-5/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][87] ([Intel XE#5021] / [Intel XE#7377])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-ptl:          NOTRUN -> [SKIP][88] ([Intel XE#5959])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-1/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a:
    - shard-lnl:          NOTRUN -> [SKIP][89] ([Intel XE#2763] / [Intel XE#6886]) +3 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-5/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][90] ([Intel XE#2938] / [Intel XE#7376] / [Intel XE#7760])
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-8/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-lnl:          [PASS][91] -> [FAIL][92] ([Intel XE#8399]) +1 other test fail
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-lnl-8/igt@kms_pm_dc@dc6-psr.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-2/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][93] ([Intel XE#2499])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-1/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-lnl:          NOTRUN -> [SKIP][94] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-5/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][95] ([Intel XE#1489])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-5/igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area.html
    - shard-ptl:          NOTRUN -> [SKIP][96] ([Intel XE#7304]) +1 other test skip
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-3/igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-sf:
    - shard-lnl:          NOTRUN -> [SKIP][97] ([Intel XE#2893] / [Intel XE#7304])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-2/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr@fbc-pr-no-drrs:
    - shard-bmg:          NOTRUN -> [SKIP][98] ([Intel XE#2234] / [Intel XE#2850]) +6 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-1/igt@kms_psr@fbc-pr-no-drrs.html

  * igt@kms_psr@fbc-psr2-cursor-plane-onoff:
    - shard-lnl:          NOTRUN -> [SKIP][99] ([Intel XE#1406] / [Intel XE#7345])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-5/igt@kms_psr@fbc-psr2-cursor-plane-onoff.html

  * igt@kms_psr@fbc-psr2-cursor-plane-onoff@edp-1:
    - shard-ptl:          NOTRUN -> [SKIP][100] ([Intel XE#1406] / [Intel XE#5835]) +1 other test skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-1/igt@kms_psr@fbc-psr2-cursor-plane-onoff@edp-1.html
    - shard-lnl:          NOTRUN -> [SKIP][101] ([Intel XE#1406] / [Intel XE#4609] / [Intel XE#7345])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-5/igt@kms_psr@fbc-psr2-cursor-plane-onoff@edp-1.html

  * igt@kms_psr@pr-no-drrs:
    - shard-ptl:          NOTRUN -> [SKIP][102] ([Intel XE#1406]) +2 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-1/igt@kms_psr@pr-no-drrs.html
    - shard-lnl:          NOTRUN -> [SKIP][103] ([Intel XE#1406]) +2 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-5/igt@kms_psr@pr-no-drrs.html

  * igt@kms_rotation_crc@bad-pixel-format:
    - shard-lnl:          NOTRUN -> [SKIP][104] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342])
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-2/igt@kms_rotation_crc@bad-pixel-format.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-ptl:          NOTRUN -> [SKIP][105] ([Intel XE#5821]) +1 other test skip
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-2/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-bmg:          NOTRUN -> [SKIP][106] ([Intel XE#3904] / [Intel XE#7342]) +1 other test skip
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_scaling_modes@scaling-mode-center:
    - shard-bmg:          NOTRUN -> [SKIP][107] ([Intel XE#2413]) +1 other test skip
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-2/igt@kms_scaling_modes@scaling-mode-center.html

  * igt@kms_setmode@invalid-clone-exclusive-crtc:
    - shard-bmg:          NOTRUN -> [SKIP][108] ([Intel XE#1435] / [Intel XE#8695])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-10/igt@kms_setmode@invalid-clone-exclusive-crtc.html
    - shard-ptl:          NOTRUN -> [SKIP][109] ([Intel XE#5910])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-8/igt@kms_setmode@invalid-clone-exclusive-crtc.html

  * igt@kms_sharpness_filter@filter-scaler-upscale:
    - shard-bmg:          NOTRUN -> [SKIP][110] ([Intel XE#6503])
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-8/igt@kms_sharpness_filter@filter-scaler-upscale.html

  * igt@xe_compute_preempt@compute-preempt-many-vram-evict:
    - shard-ptl:          NOTRUN -> [SKIP][111] ([Intel XE#5191])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-4/igt@xe_compute_preempt@compute-preempt-many-vram-evict.html

  * igt@xe_evict@evict-cm-threads-small-multi-vm:
    - shard-ptl:          NOTRUN -> [SKIP][112] ([Intel XE#5764]) +2 other tests skip
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-2/igt@xe_evict@evict-cm-threads-small-multi-vm.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-lnl:          NOTRUN -> [SKIP][113] ([Intel XE#6540] / [Intel XE#688]) +4 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-2/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_evict_ccs@evict-overcommit-parallel-nofree-reopen:
    - shard-ptl:          NOTRUN -> [SKIP][114] ([Intel XE#6144])
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-4/igt@xe_evict_ccs@evict-overcommit-parallel-nofree-reopen.html

  * igt@xe_exec_balancer@many-execqueues-virtual-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][115] ([Intel XE#7482]) +7 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-8/igt@xe_exec_balancer@many-execqueues-virtual-userptr-invalidate-race.html

  * igt@xe_exec_balancer@many-virtual-userptr-rebind:
    - shard-ptl:          NOTRUN -> [SKIP][116] ([Intel XE#7482]) +10 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-1/igt@xe_exec_balancer@many-virtual-userptr-rebind.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-bind:
    - shard-bmg:          NOTRUN -> [SKIP][117] ([Intel XE#2322] / [Intel XE#7372]) +3 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-10/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-bind.html

  * igt@xe_exec_basic@multigpu-no-exec-basic-defer-mmap:
    - shard-ptl:          NOTRUN -> [SKIP][118] ([Intel XE#5575] / [Intel XE#7484]) +6 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-4/igt@xe_exec_basic@multigpu-no-exec-basic-defer-mmap.html
    - shard-lnl:          NOTRUN -> [SKIP][119] ([Intel XE#1392]) +3 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-5/igt@xe_exec_basic@multigpu-no-exec-basic-defer-mmap.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-rebind-imm:
    - shard-ptl:          NOTRUN -> [SKIP][120] ([Intel XE#8374]) +5 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-1/igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-rebind-imm.html
    - shard-lnl:          NOTRUN -> [SKIP][121] ([Intel XE#8374]) +3 other tests skip
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-1/igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-rebind-imm.html

  * igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate-race-imm:
    - shard-bmg:          NOTRUN -> [SKIP][122] ([Intel XE#8374]) +3 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-1/igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate-race-imm.html

  * igt@xe_exec_multi_queue@few-execs-basic:
    - shard-lnl:          NOTRUN -> [SKIP][123] ([Intel XE#8364]) +15 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-5/igt@xe_exec_multi_queue@few-execs-basic.html

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-priority:
    - shard-ptl:          NOTRUN -> [SKIP][124] ([Intel XE#8364]) +16 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-2/igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-priority.html

  * igt@xe_exec_multi_queue@two-queues-priority:
    - shard-bmg:          NOTRUN -> [SKIP][125] ([Intel XE#8364]) +10 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-5/igt@xe_exec_multi_queue@two-queues-priority.html

  * igt@xe_exec_reset@cm-multi-queue-gt-reset:
    - shard-ptl:          NOTRUN -> [SKIP][126] ([Intel XE#8369])
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-3/igt@xe_exec_reset@cm-multi-queue-gt-reset.html
    - shard-bmg:          NOTRUN -> [SKIP][127] ([Intel XE#8369])
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-5/igt@xe_exec_reset@cm-multi-queue-gt-reset.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-wt-multi-vma:
    - shard-lnl:          NOTRUN -> [SKIP][128] ([Intel XE#6196])
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-3/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-wt-multi-vma.html

  * igt@xe_exec_system_allocator@threads-many-stride-mmap-huge-nomemset:
    - shard-lnl:          [PASS][129] -> [FAIL][130] ([Intel XE#8058] / [Intel XE#9570])
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-lnl-2/igt@xe_exec_system_allocator@threads-many-stride-mmap-huge-nomemset.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-2/igt@xe_exec_system_allocator@threads-many-stride-mmap-huge-nomemset.html

  * igt@xe_exec_threads@threads-multi-queue-cm-basic:
    - shard-lnl:          NOTRUN -> [SKIP][131] ([Intel XE#8378]) +1 other test skip
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-6/igt@xe_exec_threads@threads-multi-queue-cm-basic.html
    - shard-bmg:          NOTRUN -> [SKIP][132] ([Intel XE#8378]) +2 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-8/igt@xe_exec_threads@threads-multi-queue-cm-basic.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-basic:
    - shard-ptl:          NOTRUN -> [SKIP][133] ([Intel XE#8378]) +5 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-8/igt@xe_exec_threads@threads-multi-queue-mixed-basic.html

  * igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create:
    - shard-bmg:          [PASS][134] -> [ABORT][135] ([Intel XE#9463])
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-bmg-6/igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-9/igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create.html

  * igt@xe_gt_freq@freq_suspend:
    - shard-ptl:          NOTRUN -> [SKIP][136] ([Intel XE#7070])
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-2/igt@xe_gt_freq@freq_suspend.html

  * igt@xe_multigpu_svm@mgpu-atomic-op-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][137] ([Intel XE#6964]) +1 other test skip
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-1/igt@xe_multigpu_svm@mgpu-atomic-op-prefetch.html
    - shard-ptl:          NOTRUN -> [SKIP][138] ([Intel XE#6964])
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-7/igt@xe_multigpu_svm@mgpu-atomic-op-prefetch.html
    - shard-lnl:          NOTRUN -> [SKIP][139] ([Intel XE#6964])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-1/igt@xe_multigpu_svm@mgpu-atomic-op-prefetch.html

  * igt@xe_pat@pat-index-xelp:
    - shard-ptl:          NOTRUN -> [SKIP][140] ([Intel XE#5771] / [Intel XE#7590])
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-2/igt@xe_pat@pat-index-xelp.html
    - shard-lnl:          NOTRUN -> [SKIP][141] ([Intel XE#7590] / [Intel XE#977])
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-4/igt@xe_pat@pat-index-xelp.html
    - shard-bmg:          NOTRUN -> [SKIP][142] ([Intel XE#2245] / [Intel XE#7590])
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-1/igt@xe_pat@pat-index-xelp.html

  * igt@xe_pat@pat-index-xelpg:
    - shard-ptl:          NOTRUN -> [SKIP][143] ([Intel XE#5780] / [Intel XE#7590])
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-1/igt@xe_pat@pat-index-xelpg.html
    - shard-lnl:          NOTRUN -> [SKIP][144] ([Intel XE#7590] / [Intel XE#979])
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-5/igt@xe_pat@pat-index-xelpg.html

  * igt@xe_pm@s4-basic:
    - shard-ptl:          [PASS][145] -> [ABORT][146] ([Intel XE#9362])
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-ptl-5/igt@xe_pm@s4-basic.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-8/igt@xe_pm@s4-basic.html

  * igt@xe_pm@s4-vm-bind-unbind-all:
    - shard-lnl:          [PASS][147] -> [ABORT][148] ([Intel XE#9362])
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-lnl-4/igt@xe_pm@s4-vm-bind-unbind-all.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-2/igt@xe_pm@s4-vm-bind-unbind-all.html

  * igt@xe_pm_residency@cpg-basic:
    - shard-ptl:          NOTRUN -> [SKIP][149] ([Intel XE#6867]) +1 other test skip
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-4/igt@xe_pm_residency@cpg-basic.html
    - shard-lnl:          NOTRUN -> [SKIP][150] ([Intel XE#584] / [Intel XE#7369]) +1 other test skip
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-8/igt@xe_pm_residency@cpg-basic.html

  * igt@xe_query@multigpu-query-topology-l3-bank-mask:
    - shard-lnl:          NOTRUN -> [SKIP][151] ([Intel XE#944]) +1 other test skip
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-5/igt@xe_query@multigpu-query-topology-l3-bank-mask.html
    - shard-ptl:          NOTRUN -> [SKIP][152] ([Intel XE#6019])
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-7/igt@xe_query@multigpu-query-topology-l3-bank-mask.html

  * igt@xe_ras@gpu-health:
    - shard-bmg:          NOTRUN -> [SKIP][153] ([Intel XE#9588])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-1/igt@xe_ras@gpu-health.html
    - shard-ptl:          NOTRUN -> [SKIP][154] ([Intel XE#9588])
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-4/igt@xe_ras@gpu-health.html

  * igt@xe_sriov_flr@flr-basic:
    - shard-lnl:          NOTRUN -> [SKIP][155] ([Intel XE#7569])
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-4/igt@xe_sriov_flr@flr-basic.html

  * igt@xe_sriov_flr@flr-twice:
    - shard-bmg:          [PASS][156] -> [FAIL][157] ([Intel XE#6569])
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-bmg-5/igt@xe_sriov_flr@flr-twice.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-1/igt@xe_sriov_flr@flr-twice.html

  * igt@xe_vm@out-of-memory:
    - shard-ptl:          NOTRUN -> [SKIP][158] ([Intel XE#5745] / [Intel XE#7892])
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-7/igt@xe_vm@out-of-memory.html

  
#### Possible fixes ####

  * igt@intel_hwmon@hwmon-write:
    - shard-bmg:          [FAIL][159] ([Intel XE#8583]) -> [PASS][160]
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-bmg-6/igt@intel_hwmon@hwmon-write.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-4/igt@intel_hwmon@hwmon-write.html

  * igt@kms_bw@linear-tiling-1-displays-target-2160x1440p:
    - shard-bmg:          [SKIP][161] ([Intel XE#367]) -> [PASS][162]
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-bmg-8/igt@kms_bw@linear-tiling-1-displays-target-2160x1440p.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-7/igt@kms_bw@linear-tiling-1-displays-target-2160x1440p.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][163] ([Intel XE#301]) -> [PASS][164] +1 other test pass
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_hdmi_audio_bw@audio-bw-hblank160:
    - shard-bmg:          [FAIL][165] ([Intel XE#9313]) -> [PASS][166]
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-bmg-10/igt@kms_hdmi_audio_bw@audio-bw-hblank160.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-5/igt@kms_hdmi_audio_bw@audio-bw-hblank160.html

  * igt@kms_setmode@basic-no-cpu-idle@pipe-a-edp-1:
    - shard-lnl:          [FAIL][167] ([Intel XE#8618]) -> [PASS][168] +1 other test pass
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-lnl-5/igt@kms_setmode@basic-no-cpu-idle@pipe-a-edp-1.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-6/igt@kms_setmode@basic-no-cpu-idle@pipe-a-edp-1.html

  * igt@kms_vrr@flipline@pipe-a-edp-1:
    - shard-ptl:          [FAIL][169] ([Intel XE#4227] / [Intel XE#7397]) -> [PASS][170] +3 other tests pass
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-ptl-8/igt@kms_vrr@flipline@pipe-a-edp-1.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-7/igt@kms_vrr@flipline@pipe-a-edp-1.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][171] ([Intel XE#6321] / [Intel XE#8355]) -> [PASS][172]
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-bmg-2/igt@xe_evict@evict-mixed-many-threads-small.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-7/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_pm@s3-mocs:
    - shard-bmg:          [ABORT][173] ([Intel XE#9362]) -> [PASS][174]
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-bmg-10/igt@xe_pm@s3-mocs.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-1/igt@xe_pm@s3-mocs.html

  * igt@xe_pm@s4-vm-bind-unbind-all:
    - shard-ptl:          [ABORT][175] ([Intel XE#9362]) -> [PASS][176]
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-ptl-4/igt@xe_pm@s4-vm-bind-unbind-all.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-ptl-3/igt@xe_pm@s4-vm-bind-unbind-all.html

  * igt@xe_pm@s4-vm-bind-userptr:
    - shard-lnl:          [ABORT][177] ([Intel XE#9362]) -> [PASS][178] +2 other tests pass
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-lnl-2/igt@xe_pm@s4-vm-bind-userptr.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-lnl-1/igt@xe_pm@s4-vm-bind-userptr.html

  * igt@xe_sriov_flr@flr-each-isolation:
    - shard-bmg:          [FAIL][179] ([Intel XE#6569]) -> [PASS][180]
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-bmg-9/igt@xe_sriov_flr@flr-each-isolation.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-7/igt@xe_sriov_flr@flr-each-isolation.html

  
#### Warnings ####

  * igt@kms_content_protection@atomic-dpms-hdcp14:
    - shard-bmg:          [FAIL][181] ([Intel XE#3304] / [Intel XE#7374]) -> [SKIP][182] ([Intel XE#7642])
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-bmg-5/igt@kms_content_protection@atomic-dpms-hdcp14.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-3/igt@kms_content_protection@atomic-dpms-hdcp14.html

  * igt@kms_hdmi_audio_bw@suspend-disk-audio-recovery:
    - shard-bmg:          [FAIL][183] ([Intel XE#9319] / [Intel XE#9346]) -> [FAIL][184] ([Intel XE#9346])
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-bmg-2/igt@kms_hdmi_audio_bw@suspend-disk-audio-recovery.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-7/igt@kms_hdmi_audio_bw@suspend-disk-audio-recovery.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][185] ([Intel XE#3544]) -> [SKIP][186] ([Intel XE#3374] / [Intel XE#3544])
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-bmg-1/igt@kms_hdr@brightness-with-hdr.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-6/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][187] ([Intel XE#2426] / [Intel XE#5848]) -> [FAIL][188] ([Intel XE#1729] / [Intel XE#7424])
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-bmg-9/igt@kms_tiled_display@basic-test-pattern.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][189] ([Intel XE#2509] / [Intel XE#7437]) -> [SKIP][190] ([Intel XE#2426] / [Intel XE#5848])
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/shard-bmg-9/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2245]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2245
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2499
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3157]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3157
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#5191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5191
  [Intel XE#5408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5408
  [Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
  [Intel XE#5745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5745
  [Intel XE#5764]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5764
  [Intel XE#5771]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5771
  [Intel XE#5780]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5780
  [Intel XE#5800]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5800
  [Intel XE#5808]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5808
  [Intel XE#5812]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5812
  [Intel XE#5821]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5821
  [Intel XE#5822]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5822
  [Intel XE#5823]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5823
  [Intel XE#5835]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5835
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#5846]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5846
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#5854]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5854
  [Intel XE#5900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5900
  [Intel XE#5901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5901
  [Intel XE#5907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5907
  [Intel XE#5910]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5910
  [Intel XE#5959]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5959
  [Intel XE#5962]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5962
  [Intel XE#6019]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6019
  [Intel XE#6144]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6144
  [Intel XE#6196]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6196
  [Intel XE#6266]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6266
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6569
  [Intel XE#6867]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6867
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
  [Intel XE#6918]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6918
  [Intel XE#6925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6925
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#702]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/702
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7070]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7070
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7344]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7344
  [Intel XE#7345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7345
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7369
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
  [Intel XE#7377]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7377
  [Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
  [Intel XE#7389]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7389
  [Intel XE#7397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7397
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7435
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7442
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7484]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7484
  [Intel XE#7569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7569
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7892]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7892
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#8058]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8058
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8303]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8303
  [Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8391
  [Intel XE#8399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8399
  [Intel XE#8583]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8583
  [Intel XE#8618]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8618
  [Intel XE#8680]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8680
  [Intel XE#8695]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8695
  [Intel XE#9009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9009
  [Intel XE#9313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9313
  [Intel XE#9319]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9319
  [Intel XE#9346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9346
  [Intel XE#9362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9362
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#9463]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9463
  [Intel XE#9570]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9570
  [Intel XE#9588]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9588
  [Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977
  [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979


Build changes
-------------

  * IGT: IGT_9161 -> IGT_9162
  * Linux: xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766 -> xe-pw-176761v1

  IGT_9161: 9161
  IGT_9162: 9162
  xe-6006-b255dd13059988fddde9ea187d1dd1017c9a5766: b255dd13059988fddde9ea187d1dd1017c9a5766
  xe-pw-176761v1: 176761v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176761v1/index.html

[-- Attachment #2: Type: text/html, Size: 67870 bytes --]

Re: [PATCH 01/10] drm/xe: Bail from adjust_idledly() if in VF mode

[Matt Atwood]

On Fri, Oct 23, 2026 at 06:09:29PM -0300, Gustavo Sousa wrote:
> Both Wa_14025941587 and Wa_16023105232 apply adjustments to
> RING_IDLEDLY and take different approaches to avoid SRIOV VF mode.
> 
> Let's converge them into a consistent approach.  Since
> adjust_idledly() should avoid SRIOV VF irrespective of what
> workarounds are enabled, choose to add an early return in that
> function instead of having each related workaround add
> FUNC(xe_rtp_match_not_sriov_vf) to their rules.
> 
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_hw_engine.c  | 6 ++++--
>  drivers/gpu/drm/xe/xe_wa_oob.rules | 4 ++--
>  2 files changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 55ee0c892c1e..50e8c5103bdc 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -611,8 +611,10 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>  	bool wa_applied = false;
>  	bool clamped_below_maxcnt = false;
>  
> -	if ((!IS_SRIOV_VF(gt_to_xe(gt)) && XE_GT_WA(gt, 16023105232)) ||
> -	    XE_GT_WA(gt, 14025941587)) {
> +	if (IS_SRIOV_VF(gt_to_xe(gt)))
> +		return;
> +
> +	if (XE_GT_WA(gt, 16023105232) || XE_GT_WA(gt, 14025941587)) {
>  		u32 mincnt_idledly_ns = 5000;
>  
>  		/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
> index f35181fc4e49..6a1d5250ba1b 100644
> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> @@ -73,6 +73,6 @@
>  16029897822	MEDIA_VERSION(3500)
>  		GRAPHICS_VERSION(3510)
>  14027054324	GRAPHICS_VERSION(3511)
> -14025941587	GRAPHICS_VERSION_RANGE(2001, 3511), FUNC(xe_rtp_match_not_sriov_vf)
> -		MEDIA_VERSION_RANGE(1301, 3503), FUNC(xe_rtp_match_not_sriov_vf)
> +14025941587	GRAPHICS_VERSION_RANGE(2001, 3511)
> +		MEDIA_VERSION_RANGE(1301, 3503)
>  16030224309	GRAPHICS_VERSION(3510)
> 
> -- 
> 2.56.0
> 

Re: [PATCH 02/10] drm/xe: Sync Wa_16023105232 in xe_was to match OOB rule

[Matt Atwood]

On Fri, Oct 23, 2026 at 06:09:30PM -0300, Gustavo Sousa wrote:
> Wa_16023105232 was extended in xe_wa_oob.rules to match extra IP
> releases while the respective entry in xe_was[] was overlooked.
> Update the latter to be in sync with the former.
> 
> Also add comments in the code so that we don't forget to update both
> places if new IP versions are added.
> 
> Fixes: c96e0df4e9f5 ("drm/xe/xe3: Add support for media IP version 30.02")
> Fixes: 4fde66699f1c ("drm/xe/xe3: Add support for graphics IP versions 30.04 & 30.05")
> Cc: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_wa.c         | 5 +++--
>  drivers/gpu/drm/xe/xe_wa_oob.rules | 1 +
>  2 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index c94fe7753f9a..bbe1696a57bc 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -581,8 +581,9 @@ static const struct xe_rtp_table_sr engine_was = XE_RTP_TABLE_SR(
>  	  XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE))
>  	},
>  	{ XE_RTP_NAME("16023105232"),
> -	  XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3000), OR,
> -		       GRAPHICS_VERSION_RANGE(2001, 3001)),
> +	  /* IP versions need to be in sync with the respective entry in xe_wa_oob.rules. */
> +	  XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3002), OR,
> +		       GRAPHICS_VERSION_RANGE(2001, 3005)),
>  	  XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE,
>  			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
>  	},
> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
> index 6a1d5250ba1b..9be392bce969 100644
> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> @@ -44,6 +44,7 @@
>  18013179988	GRAPHICS_VERSION(1255)
>  		GRAPHICS_VERSION_RANGE(1270, 1274)
>  1508761755	GRAPHICS_VERSION(1255)
> +# IP versions need to be in sync with the respective entry in xe_wa.c.
>  16023105232	GRAPHICS_VERSION_RANGE(2001, 3005)
>  		MEDIA_VERSION_RANGE(1301, 3002)
>  16026508708	GRAPHICS_VERSION_RANGE(1200, 3005)
> 
> -- 
> 2.56.0
> 

Re: [PATCH 04/10] drm/xe: Factor out {min,max}_idledly_ps in adjust_idledly()

[Matt Atwood]

On Fri, Oct 23, 2026 at 09:23:04PM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] drm/xe: 32-bit multiplication overflow in adjust_idledly()
> --
> 
> commit 032b173104de210ca0228dd31e057951f3cde20d
> Author: Gustavo Sousa <gustavo.sousa@intel.com>
> 
> drm/xe: Factor out {min,max}_idledly_ps in adjust_idledly()
> 
> This commit reorganizes adjust_idledly() so that workaround-specific logic
> computes min_idledly_ps and max_idledly_ps before applying and rounding
> those limits to the RING_IDLEDLY register field.
> 
> > diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> > index dcc8a6d53c5d0..2d2a80cc2da35 100644
> > --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> > +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> > @@ -585,99 +585,81 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
> >  	xe_reg_whitelist_process_engine(hwe);
> >  }
> >  
> > -static u32 idledly_floor_ticks(u64 idledly_ps, u32 idledly_units_ps)
> > -{
> > -	return DIV_ROUND_DOWN_ULL(idledly_ps, idledly_units_ps);
> > -}
> > -
> >  static void adjust_idledly(struct xe_hw_engine *hwe)
> >  {
> >  	struct xe_gt *gt = hwe->gt;
> > -	u32 idledly_reg_val, maxcnt_reg_val;
> > +	u32 idledly_reg_val;
> > +	u32 idledly;
> >  	u32 idledly_units_ps = 8 * gt->info.timestamp_base;
> > -	u32 maxcnt_units_ps = 640000;
> >  	u64 idledly_ps, idledly_hw_ps;
> > -	u64 maxcnt_ps;
> > +	u64 min_idledly_ps = 0;
> > +	u64 max_idledly_ps = -1;
> >  	bool inhibit_switch = false;
> >  	bool wa_applied = false;
> > -	bool clamped_below_maxcnt = false;
> >  
> >  	if (IS_SRIOV_VF(gt_to_xe(gt)))
> >  		return;
> >  
> >  	if (XE_GT_WA(gt, 16023105232) || XE_GT_WA(gt, 14025941587)) {
> > -		u32 mincnt_idledly_ps = 5000000;
> > -
> >  		/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
> >  		if (!idledly_units_ps)
> >  			return;
> >  
> >  		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
> >  		inhibit_switch = idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED;
> > -		idledly_ps = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val) * idledly_units_ps;
> > +		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
> > +		idledly_ps = idledly * idledly_units_ps;
> >  		idledly_hw_ps = idledly_ps;
> >  
> > -		maxcnt_reg_val = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
> > -		maxcnt_ps = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt_reg_val) * maxcnt_units_ps;
> > -
> > -		/*
> > -		 * Wa_14025941587 is applied before Wa_16023105232, which takes
> > -		 * priority if the two ever conflict (not expected in practice).
> > -		 */
> > -		if (XE_GT_WA(gt, 14025941587) &&
> > -		    idledly_ps < mincnt_idledly_ps) {
> > -			idledly_ps = mincnt_idledly_ps;
> > -			wa_applied = true;
> > -		}
> > +		if (XE_GT_WA(gt, 14025941587))
> > +			min_idledly_ps = max(min_idledly_ps, 5000000);
> >  
> >  		if (XE_GT_WA(gt, 16023105232)) {
> > +			u32 maxcnt_units_ps = 640000;
> > +			u32 maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
> > +
> > +			max_idledly_ps = min_t(u64,
> > +					       max_idledly_ps,
> > +					       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
> > +
> >  			/* Clear the inhibit switch without disturbing a valid delay. */
> >  			if (inhibit_switch) {
> >  				idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
> >  				wa_applied = true;
> >  			}
> > +		}
> >  
> > -			/* Warn only on the value read from hardware. */
> > -			xe_gt_WARN_ON(gt, idledly_hw_ps >= maxcnt_ps);
> > +		/*
> > +		 * min_idledly_ps is applied before max_idledly_ps, which takes
> > +		 * priority if the two ever conflict (not expected in practice).
> > +		 */
> > +		if (idledly_ps < min_idledly_ps) {
> > +			idledly = DIV_ROUND_UP_ULL(min_idledly_ps, idledly_units_ps);
> > +			idledly_ps = idledly * idledly_units_ps;
> > +			wa_applied = true;
> > +		}
> >  
> > -			if (idledly_ps >= maxcnt_ps) {
> > -				/* maxcnt may be 0 if IDLE_WAIT_TIME is unprogrammed. */
> > -				idledly_ps = maxcnt_ps ? maxcnt_ps - 1 : 0;
> > -				clamped_below_maxcnt = true;
> > -				wa_applied = true;
> > +		if (idledly_ps >= max_idledly_ps) {
> > +			if (max_idledly_ps) {
> > +				idledly = DIV_ROUND_DOWN_ULL(max_idledly_ps - 1, idledly_units_ps);
> > +				idledly_ps = idledly * idledly_units_ps;
> 
> [Severity: Medium]
> Can these tick-to-picosecond multiplications in adjust_idledly() in
> drivers/gpu/drm/xe/xe_hw_engine.c overflow 32 bits before being widened to
> u64?
> 
> When hw_engine_init() calls adjust_idledly() on non-VF platforms where
> Wa_16023105232 or Wa_14025941587 is active, idledly, idledly_units_ps (up to
> 8 * 83333 = 666,664 ps), maxcnt_units_ps (640,000 ps), and the return value
> of REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) are all u32.
> 
> In the three assignments:
> 
> 	idledly_ps = idledly * idledly_units_ps;
> 
> both operands are u32. Since IDLE_DELAY is a 21-bit field (REG_GENMASK(20, 0),
> up to 2,097,151 ticks), the product can reach ~1.398e12 ps and wraps modulo
> 2^32 for idledly >= 6443 ticks before assignment to u64 idledly_ps.
> 
> Similarly, in:
> 
> 	max_idledly_ps = min_t(u64,
> 			       max_idledly_ps,
> 			       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
> 
> REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps is evaluated in 32-bit
> unsigned arithmetic before min_t(u64, ...) casts the result to u64. Because
> IDLE_WAIT_TIME is a 20-bit field (REG_GENMASK(19, 0), up to 1,048,575 ticks),
> the product can reach ~6.71e11 ps and wraps 32 bits for IDLE_WAIT_TIME >= 6711
> ticks, which can misprogram RING_IDLEDLY or trigger false
> xe_gt_WARN_ON(gt, idledly_hw_ps >= max_idledly_ps) warnings.
> 
> Commit d864065ea25e ("drm/xe: harden adjust_idledly() against divide-by-zero
> and overflow") previously added explicit (u64) casts to prevent 32-bit
> truncation when converting ticks to time units. Should idledly_units_ps and
> maxcnt_units_ps (or the multiplication operands) be promoted to u64 here as
> well?
Similar to previous patch the bot is correct here, please adjust in v2
> 
> -- 
> Sashiko AI review · https://sashiko.dev/#/patchset/20261023-wa_16031259911-v1-0-b0453f79c4e1@intel.com?part=4

Re: [PATCH 05/10] drm/xe: Bail from adjust_idledly() if no applicable workaround

[Matt Atwood]

On Fri, Oct 23, 2026 at 06:09:33PM -0300, Gustavo Sousa wrote:
> Re-organize adjust_idledly() so that we return and avoid touching the
> hardware if no applicable workaround was found.
> 
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_hw_engine.c | 32 +++++++++++++++++++-------------
>  1 file changed, 19 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 0c9b510e7cac..9f0fd10afd4e 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -605,7 +605,7 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>  	u64 idledly_ps, idledly_hw_ps;
>  	u64 min_idledly_ps = 0;
>  	u64 max_idledly_ps = -1;
> -	bool inhibit_switch = false;
> +	bool clear_inhibit_switch = false;
>  	bool wa_applied = false;
>  
>  	if (IS_SRIOV_VF(gt_to_xe(gt)))
> @@ -616,12 +616,6 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>  		if (!idledly_units_ps)
>  			return;
>  
> -		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
> -		inhibit_switch = idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED;
> -		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
> -		idledly_ps = idledly * idledly_units_ps;
> -		idledly_hw_ps = idledly_ps;
> -
>  		if (XE_GT_WA(gt, 14025941587))
>  			min_idledly_ps = max(min_idledly_ps, 5000000);
>  
> @@ -633,13 +627,24 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>  					       max_idledly_ps,
>  					       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
>  
> -			/* Clear the inhibit switch without disturbing a valid delay. */
> -			if (inhibit_switch) {
> -				idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
> -				wa_applied = true;
> -			}
> +			clear_inhibit_switch = true;
>  		}
>  
> +		/* No applicable workaround found. */
> +		if (min_idledly_ps == 0 && max_idledly_ps == -1 && !clear_inhibit_switch)
> +			return;
> +
> +		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
> +
> +		if (clear_inhibit_switch && idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED) {
> +			idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
> +			wa_applied = true;
> +		}
> +
> +		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
> +		idledly_ps = idledly * idledly_units_ps;
> +		idledly_hw_ps = idledly_ps;
> +
>  		/*
>  		 * min_idledly_ps is applied before max_idledly_ps, which takes
>  		 * priority if the two ever conflict (not expected in practice).
> @@ -671,7 +676,8 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>  
>  			xe_gt_dbg(gt, "idledly %s: set %llups min=%llups max=%llups inh=%u ts=%ups\n",
>  				  hwe->name, idledly_ps, min_idledly_ps, max_idledly_ps,
> -				  !!inhibit_switch, gt->info.timestamp_base);
> +				  !!(idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED),
> +				  gt->info.timestamp_base);
>  			xe_mmio_write32(&gt->mmio,
>  					RING_IDLEDLY(hwe->mmio_base),
>  					idledly_reg_val);
> 
> -- 
> 2.56.0
> 

Re: [PATCH 06/10] drm/xe: Drop early and redundant workaround checks in adjust_idledly()

[Matt Atwood]

On Fri, Oct 23, 2026 at 09:22:02PM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] drm/xe: 32-bit multiplication overflow in adjust_idledly()
> --
> 
> commit 1632f9f2c26646be902e4438963fff43c54e34fd
> Author: Gustavo Sousa <gustavo.sousa@intel.com>
> 
> drm/xe: Drop early and redundant workaround checks in adjust_idledly()
> 
> This commit removes the outer workaround check in adjust_idledly() and
> unindents the body now that each workaround check is scoped to its own
> conditional block and the function returns early when no workaround
> applies.
> 
> > diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> > index e201fa96ee867..00af7344067d3 100644
> > --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> > +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> > @@ -600,77 +600,75 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
> >  	if (IS_SRIOV_VF(gt_to_xe(gt)))
> >  		return;
> >  
> > -	if (XE_GT_WA(gt, 16023105232) || XE_GT_WA(gt, 14025941587)) {
> > -		/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
> > -		if (!idledly_units_ps)
> > -			return;
> > +	/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
> > +	if (!idledly_units_ps)
> > +		return;
> >  
> > -		if (XE_GT_WA(gt, 14025941587))
> > -			min_idledly_ps = max(min_idledly_ps, 5000000);
> > +	if (XE_GT_WA(gt, 14025941587))
> > +		min_idledly_ps = max(min_idledly_ps, 5000000);
> >  
> > -		if (XE_GT_WA(gt, 16023105232)) {
> > -			u32 maxcnt_units_ps = 640000;
> > -			u32 maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
> > +	if (XE_GT_WA(gt, 16023105232)) {
> > +		u32 maxcnt_units_ps = 640000;
> > +		u32 maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
> >  
> > -			max_idledly_ps = min_t(u64,
> > -					       max_idledly_ps,
> > -					       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
> > +		max_idledly_ps = min_t(u64,
> > +				       max_idledly_ps,
> > +				       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
> >  
> > -			clear_inhibit_switch = true;
> > -		}
> > +		clear_inhibit_switch = true;
> > +	}
> >  
> > -		/* No applicable workaround found. */
> > -		if (min_idledly_ps == 0 && max_idledly_ps == -1 && !clear_inhibit_switch)
> > -			return;
> > +	/* No applicable workaround found. */
> > +	if (min_idledly_ps == 0 && max_idledly_ps == -1 && !clear_inhibit_switch)
> > +		return;
> >  
> > -		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
> > +	idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
> >  
> > -		if (clear_inhibit_switch && idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED) {
> > -			idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
> > -			wa_applied = true;
> > -		}
> > +	if (clear_inhibit_switch && idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED) {
> > +		idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
> > +		wa_applied = true;
> > +	}
> > +
> > +	idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
> > +	idledly_ps = idledly * idledly_units_ps;
> > +	idledly_hw_ps = idledly_ps;
> >  
> > -		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
> > +	/*
> > +	 * min_idledly_ps is applied before max_idledly_ps, which takes
> > +	 * priority if the two ever conflict (not expected in practice).
> > +	 */
> > +	if (idledly_ps < min_idledly_ps) {
> > +		idledly = DIV_ROUND_UP_ULL(min_idledly_ps, idledly_units_ps);
> >  		idledly_ps = idledly * idledly_units_ps;
> > -		idledly_hw_ps = idledly_ps;
> > +		wa_applied = true;
> > +	}
> >  
> > -		/*
> > -		 * min_idledly_ps is applied before max_idledly_ps, which takes
> > -		 * priority if the two ever conflict (not expected in practice).
> > -		 */
> > -		if (idledly_ps < min_idledly_ps) {
> > -			idledly = DIV_ROUND_UP_ULL(min_idledly_ps, idledly_units_ps);
> > +	if (idledly_ps >= max_idledly_ps) {
> > +		if (max_idledly_ps) {
> > +			idledly = DIV_ROUND_DOWN_ULL(max_idledly_ps - 1, idledly_units_ps);
> >  			idledly_ps = idledly * idledly_units_ps;
> 
> [Severity: Medium]
> Can the picosecond multiplications in adjust_idledly() overflow 32 bits?
> 
> In the Wa_16023105232 check:
> 
> 	max_idledly_ps = min_t(u64,
> 			       max_idledly_ps,
> 			       REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) * maxcnt_units_ps);
> 
> both REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt) and maxcnt_units_ps (640000)
> have type u32. The multiplication is evaluated in 32-bit unsigned
> arithmetic before min_t(u64, ...) widens the result to u64. Since
> IDLE_WAIT_TIME is REG_GENMASK(19, 0), any register value of 6711 ticks or
> greater (~4.295 ms out of the ~671 ms range) exceeds U32_MAX when
> multiplied by 640000 and wraps around.
> 
> Similarly, idledly (extracted from the 21-bit IDLE_DELAY field) and
> idledly_units_ps (8 * gt->info.timestamp_base) are both u32:
> 
> 	idledly_ps = idledly * idledly_units_ps;
> 
> At all three assignments of idledly_ps in adjust_idledly(), the product is
> computed in 32-bit arithmetic before being assigned to the u64 idledly_ps
> variable, which overflows whenever the delay exceeds ~4.295 ms.
> 
> When reached during GT initialization via:
> 
>   xe_gt_init()
>     -> gt_init_with_all_forcewake()
>       -> xe_hw_engines_init()
>         -> hw_engine_init()
>           -> adjust_idledly()
> 
> this truncation can trigger a spurious xe_gt_WARN_ON(gt, idledly_hw_ps >=
> max_idledly_ps) warning and program an improperly clamped IDLE_DELAY value
> into RING_IDLEDLY.
> 
> Should maxcnt_units_ps and idledly_units_ps be declared as u64 (or the
> multiplications use mul_u32_u32() / a u64 cast) so the products are
> evaluated in 64-bit arithmetic?
I agree with the bot, similar to others in series move from u32 to u64
> 
> -- 
> Sashiko AI review · https://sashiko.dev/#/patchset/20261023-wa_16031259911-v1-0-b0453f79c4e1@intel.com?part=6

Re: [PATCH 07/10] drm/xe: Drop comment about MAXCNT when calling adjust_idledly()

[Matt Atwood]

On Fri, Oct 23, 2026 at 06:09:35PM -0300, Gustavo Sousa wrote:
> The adjust_idledly() function does more than what the comment on the
> call site says.  Furthermore, that comment seems unnecessary; if
> anything, some documentation at the function definition would be
> better, but even that doesn't seem terribly necessary.  Let's just
> drop the comment.
> 
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_hw_engine.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index ffd6ef9f96f4..18c8f88739d5 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -719,7 +719,6 @@ static int hw_engine_init(struct xe_gt *gt, struct xe_hw_engine *hwe,
>  			xe_hw_engine_enable_ring(hwe);
>  	}
>  
> -	/* Ensure IDLEDLY is lower than MAXCNT */
I don't care for just the deletion here, either add a function doc for adjust
idledly, or expand the comment to something like "entry point for workarounds
and functionaly to adjust idledly".

MattA
>  	adjust_idledly(hwe);
>  
>  	return devm_add_action_or_reset(xe->drm.dev, hw_engine_fini, hwe);
> 
> -- 
> 2.56.0
> 

Re: [PATCH 08/10] drm/xe/guc: Increment regset size for Wa_1607983814 inside hwe loop

[Matt Atwood]

On Fri, Oct 23, 2026 at 06:09:36PM -0300, Gustavo Sousa wrote:
> The regset size increment for Wa_1607983814 is correct with today's
> hardware, because the maximum number RCS per GT is one.  That said, it
> is arguably more accurate to make that calculation inside the
> for_each_hw_engine() loop, where we can mimic the same conditions used
> by guc_mmio_regset_write().
> 
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_guc_ads.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index 43a2951a66d6..a67d3405b10f 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -220,14 +220,15 @@ static size_t calculate_regset_size(struct xe_gt *gt)
>  	enum xe_hw_engine_id id;
>  	unsigned int count = 0;
>  
> -	for_each_hw_engine(hwe, gt, id)
> +	for_each_hw_engine(hwe, gt, id) {
>  		xa_for_each(&hwe->reg_sr.xa, sr_idx, sr_entry)
>  			count++;
>  
> -	count += ADS_REGSET_EXTRA_MAX * XE_NUM_HW_ENGINES;
> +		if (XE_GT_WA(gt, 1607983814) && hwe->class == XE_ENGINE_CLASS_RENDER)
> +			count += LNCFCMOCS_REG_COUNT;
> +	}
>  
> -	if (XE_GT_WA(gt, 1607983814))
> -		count += LNCFCMOCS_REG_COUNT;
> +	count += ADS_REGSET_EXTRA_MAX * XE_NUM_HW_ENGINES;
>  
>  	return count * sizeof(struct guc_mmio_reg);
>  }
> 
> -- 
> 2.56.0
> 

Re: [PATCH 09/10] drm/xe/guc: Increment regset size for RING_IDLEDLY workarounds

[Matt Atwood]

On Fri, Oct 23, 2026 at 06:09:37PM -0300, Gustavo Sousa wrote:
> We need to keep calculate_regset_size() in sync with
> guc_mmio_regset_write(). They became out of sync when RING_IDLEDLY was
> added.
> 
> This likely went unnoticed because ADS_REGSET_EXTRA_MAX - being
> greater than the current size of extra_regs - inadvertently provided
> some extra room in the regset, which ended up being used for
> RING_IDLEDLY.
> 
> However, we should not rely on that. We should make
> ADS_REGSET_EXTRA_MAX strictly about extra_regs, and explicitly account
> for the RING_IDLEDLY register.
> 
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_guc_ads.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index a67d3405b10f..2e738d205738 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -226,6 +226,9 @@ static size_t calculate_regset_size(struct xe_gt *gt)
>  
>  		if (XE_GT_WA(gt, 1607983814) && hwe->class == XE_ENGINE_CLASS_RENDER)
>  			count += LNCFCMOCS_REG_COUNT;
> +
> +		if (XE_GT_WA(hwe->gt, 16023105232) || XE_GT_WA(hwe->gt, 14025941587))
> +			count++; /* RING_IDLEDLY */
>  	}
>  
>  	count += ADS_REGSET_EXTRA_MAX * XE_NUM_HW_ENGINES;
> 
> -- 
> 2.56.0
> 

Re: [PATCH 10/10] drm/xe: Implement Wa_16031259911

[Matt Atwood]

On Fri, Oct 23, 2026 at 06:09:38PM -0300, Gustavo Sousa wrote:
> Implement Wa_16031259911, which applies to graphics version 35.10 and
> 35.11.  The workaround definition instructs us to set the minimum idle
> delay value to 2 times the memory read delay, and tells that using 1
> unit of the IDLE_DELAY field covers that minimum.
> 
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_guc_ads.c    | 6 ++++--
>  drivers/gpu/drm/xe/xe_hw_engine.c  | 3 +++
>  drivers/gpu/drm/xe/xe_wa_oob.rules | 1 +
>  3 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index 2e738d205738..7f830122ae16 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -227,7 +227,8 @@ static size_t calculate_regset_size(struct xe_gt *gt)
>  		if (XE_GT_WA(gt, 1607983814) && hwe->class == XE_ENGINE_CLASS_RENDER)
>  			count += LNCFCMOCS_REG_COUNT;
>  
> -		if (XE_GT_WA(hwe->gt, 16023105232) || XE_GT_WA(hwe->gt, 14025941587))
> +		if (XE_GT_WA(hwe->gt, 16023105232) || XE_GT_WA(hwe->gt, 14025941587) ||
> +		    (XE_GT_WA(hwe->gt, 16031259911) && xe_gt_supports_multi_queue(hwe->gt, hwe->class)))
>  			count++; /* RING_IDLEDLY */
>  	}
>  
> @@ -875,7 +876,8 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
>  		}
>  	}
>  
> -	if (XE_GT_WA(hwe->gt, 16023105232) || XE_GT_WA(hwe->gt, 14025941587))
> +	if (XE_GT_WA(hwe->gt, 16023105232) || XE_GT_WA(hwe->gt, 14025941587) ||
> +	    (XE_GT_WA(hwe->gt, 16031259911) && xe_gt_supports_multi_queue(hwe->gt, hwe->class)))
>  		guc_mmio_regset_write_one(ads, regset_map,
>  					  RING_IDLEDLY(hwe->mmio_base),
>  					  count++);
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 18c8f88739d5..96741d3050c5 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -618,6 +618,9 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>  	if (XE_GT_WA(gt, 14025941587))
>  		min_idledly_ps = max(min_idledly_ps, 5000000);
>  
> +	if (XE_GT_WA(gt, 16031259911) && xe_gt_supports_multi_queue(gt, hwe->class))
> +		min_idledly_ps = max(min_idledly_ps, idledly_units_ps);
> +
>  	if (XE_GT_WA(gt, 16023105232)) {
>  		u32 maxcnt_units_ps = 640000;
>  		u32 maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
> index 9be392bce969..a28552c09019 100644
> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> @@ -77,3 +77,4 @@
>  14025941587	GRAPHICS_VERSION_RANGE(2001, 3511)
>  		MEDIA_VERSION_RANGE(1301, 3503)
>  16030224309	GRAPHICS_VERSION(3510)
> +16031259911	GRAPHICS_VERSION_RANGE(3510, 3511)
> 
> -- 
> 2.56.0
>