[PATCH v4 0/7] drm/i915/dp: Add support for the DP symbol based timing generator

[PATCH v4 0/7] drm/i915/dp: Add support for the DP symbol based timing generator

[Arun R Murthy]

Xe3p adds a DP link layer (LL) symbol based timing generator, as an
alternative to the pixel clock based one. It generates the transcoder
timings in LL symbol cycles instead of pixels, which makes the per-line
symbol insertion for 8b/10b MST and 128b/132b SST/MST compliant with
the DP 2.1 hblank symbol cycle count. This reduces the line-to-line
hblank jitter that some sinks can't handle, and the Min Hblank
mechanism can't be used together with it.

This series computes the LL symbol HACT/HTOTAL/CHUNK_SIZE and the 128
bit Data M/N for the symbol based timing generator, programs and enables
it, and drops the Link M/N ratio limit, which only applies to the pixel
based timing generator. If the symbol based timing generator can't be
used (MSO/eDP splitter, timings out of range, Data M/N above 1.0), the
pixel based one is kept.

Patch overview:
 - Patch 1 factors out the DSC slice count and link bpp lookup, to be
   shared with the Min Hblank computation.
 - Patch 2 adds the symbol based timing generator registers.
 - Patch 3 adds the symbol based timing generator state to the crtc
   state, with its state dump and state checker comparison.
 - Patch 4 adds HAS_DP_SYMBOL_TG().
 - Patch 5 computes the timing generator parameters.
 - Patch 6 programs and enables the timing generator, including the
   state readout.
 - Patch 7 lifts the Link M/N ratio limit when the symbol based timing
   generator is used.

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: chaitanya.kumar.borah@intel.com
Cc: uma.shankar@intel.com
Cc: suraj.kandpal@intel.com
To: intel-gfx@lists.freedesktop.org
To: intel-xe@lists.freedesktop.org

Bspec: 68922
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
Changes in v4:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v3: https://lore.kernel.org/r/20261029-vlk-64036-dp-symbol-tg-v3-0-69022424ef17@intel.com

Changes in v3:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v2: https://lore.kernel.org/r/20261028-vlk-64036-dp-symbol-tg-v2-0-43849c325d32@intel.com

Changes in v2:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v1: https://lore.kernel.org/r/20261027-vlk-64036-dp-symbol-tg-v1-0-c46f4ebf67ed@intel.com

---
Arun R Murthy (7):
      drm/i915/dp: Factor out the DSC slice count and link bpp lookup
      drm/i915/display: Add the DP link layer symbol timing generator registers
      drm/i915/display: Add the DP symbol timing generator crtc state
      drm/i915/display: Add HAS_DP_SYMBOL_TG()
      drm/i915/dp: Compute the DP symbol based timing generator parameters
      drm/i915/display: Program and enable the DP symbol based timing generator
      drm/i915/dp: Don't limit the Link M/N ratio with the symbol timing generator

 .../gpu/drm/i915/display/intel_crtc_state_dump.c   |  11 +
 drivers/gpu/drm/i915/display/intel_ddi.c           |   2 +
 drivers/gpu/drm/i915/display/intel_display.c       | 112 +++++++++-
 drivers/gpu/drm/i915/display/intel_display.h       |   1 +
 .../gpu/drm/i915/display/intel_display_device.h    |   1 +
 drivers/gpu/drm/i915/display/intel_display_regs.h  |  38 ++++
 drivers/gpu/drm/i915/display/intel_display_types.h |  13 ++
 drivers/gpu/drm/i915/display/intel_dp.c            | 239 +++++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_dp.h            |   3 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c        |  10 +-
 10 files changed, 405 insertions(+), 25 deletions(-)
---
base-commit: d56ff005f0d16ec136ee31fe3238eb447fefdc1a
change-id: 20261027-vlk-64036-dp-symbol-tg-d72c4222856e

Best regards,
-- 
Arun R Murthy <arun.r.murthy@intel.com>

[PATCH v4 1/7] drm/i915/dp: Factor out the DSC slice count and link bpp lookup

[Arun R Murthy]

Move the DSC slice count and link bpp determination out of
intel_dp_compute_min_hblank() into a helper, so that it can be shared
with the upcoming DP symbol based timing generator computation.
No functional change.

v3: change intel_dp_get_sclice_and_link_bpp -> intel_dp_compute_ (Suraj)

Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 51 ++++++++++++++++++++++-----------
 1 file changed, 34 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index bf5e87a72108eaf274f24bc997f2e8e2cc8320a0..db7c8fcc8683aae1a2bc7050ef7c87ed5155c8dc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3628,6 +3628,35 @@ intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,
 	}
 }
 
+static int intel_dp_compute_dsc_slices_and_link_bpp(const struct intel_crtc_state *crtc_state,
+						    struct intel_connector *connector,
+						    int *dsc_slices, int *link_bpp_x16)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	const struct drm_display_mode *adjusted_mode =
+					&crtc_state->hw.adjusted_mode;
+
+	*dsc_slices = 0;
+
+	if (crtc_state->dsc.compression_enable) {
+		*dsc_slices = intel_dp_dsc_get_slice_count(connector,
+							   adjusted_mode->crtc_clock,
+							   adjusted_mode->crtc_hdisplay,
+							   intel_crtc_num_joined_pipes(crtc_state));
+		if (!*dsc_slices) {
+			drm_dbg(display->drm, "failed to calculate dsc slice count\n");
+			return -EINVAL;
+		}
+
+		*link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16;
+	} else {
+		*link_bpp_x16 = intel_dp_output_format_link_bpp_x16(crtc_state->output_format,
+								    crtc_state->pipe_bpp);
+	}
+
+	return 0;
+}
+
 int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
 				const struct drm_connector_state *conn_state)
 {
@@ -3642,12 +3671,12 @@ int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
 	 */
 	int min_sym_cycles = intel_dp_is_uhbr(crtc_state) ? 3 : 5;
 	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
-	int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);
 	int min_hblank;
 	int max_lane_count = 4;
 	int hactive_sym_cycles, htotal_sym_cycles;
 	int dsc_slices = 0;
 	int link_bpp_x16;
+	int ret;
 
 	if (DISPLAY_VER(display) < 30)
 		return 0;
@@ -3656,22 +3685,10 @@ int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
 	if (!is_mst && !intel_dp_is_uhbr(crtc_state))
 		return 0;
 
-	if (crtc_state->dsc.compression_enable) {
-		dsc_slices = intel_dp_dsc_get_slice_count(connector,
-							  adjusted_mode->crtc_clock,
-							  adjusted_mode->crtc_hdisplay,
-							  num_joined_pipes);
-		if (!dsc_slices) {
-			drm_dbg(display->drm, "failed to calculate dsc slice count\n");
-			return -EINVAL;
-		}
-	}
-
-	if (crtc_state->dsc.compression_enable)
-		link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16;
-	else
-		link_bpp_x16 = intel_dp_output_format_link_bpp_x16(crtc_state->output_format,
-								   crtc_state->pipe_bpp);
+	ret = intel_dp_compute_dsc_slices_and_link_bpp(crtc_state, connector,
+						       &dsc_slices, &link_bpp_x16);
+	if (ret)
+		return ret;
 
 	/* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */
 	hactive_sym_cycles = drm_dp_link_symbol_cycles(max_lane_count,

-- 
2.25.1

[PATCH v4 2/7] drm/i915/display: Add the DP link layer symbol timing generator registers

[Arun R Murthy]

Add the definitions of the registers of the DP link layer (LL) symbol
based timing generator.

v3: change MMIO -> MMIO_TRANS2 (Suraj)

Bspec: 68849, 68922, 69961
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_regs.h | 38 +++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index bbdbc27629d7104c1f80baad44e710872214d42b..1a7badeb327977916c85ce88327ec496623d787b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -879,6 +879,7 @@
 #define   TRANSCONF_DSI_PLL_LOCKED		REG_BIT(29) /* vlv & pipe A only */
 #define   TRANSCONF_FRAME_START_DELAY_MASK	REG_GENMASK(28, 27) /* pre-hsw */
 #define   TRANSCONF_FRAME_START_DELAY(x)		REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
+#define   TRANSCONF_DP_SYMBOL_TG_ENABLE		REG_BIT(28) /* xe3p+ */
 #define   TRANSCONF_PIPE_LOCKED			REG_BIT(25)
 #define   TRANSCONF_FORCE_BORDER			REG_BIT(25)
 #define   TRANSCONF_GAMMA_MODE_MASK_I9XX		REG_BIT(24) /* gmch */
@@ -930,6 +931,7 @@
 #define   TRANSCONF_DITHER_TYPE_TEMP		REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3)
 #define   TRANSCONF_PIXEL_COUNT_SCALING_MASK	REG_GENMASK(1, 0)
 #define   TRANSCONF_PIXEL_COUNT_SCALING_X4	1
+#define   TRANSCONF_PIXEL_COUNT_SCALING_X1	3 /* xe3p+ */
 
 #define _PIPEASTAT		0x70024
 #define PIPESTAT(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
@@ -2332,6 +2334,42 @@
 #define _DP_MIN_HBLANK_CTL_B			0x610ac
 #define DP_MIN_HBLANK_CTL(trans)		_MMIO_TRANS(trans, _DP_MIN_HBLANK_CTL_A, _DP_MIN_HBLANK_CTL_B)
 
+/* DP link layer (LL) symbol based timing generator, display version 35+ */
+#define _TRANS_LLSYM_HACT_A			0x600dc
+#define TRANS_LLSYM_HACT(display, trans) \
+	_MMIO_TRANS2(display, trans, _TRANS_LLSYM_HACT_A)
+#define   TRANS_LLSYM_HACT_MASK			REG_GENMASK(14, 0)
+#define   TRANS_LLSYM_HACT_VAL(x)		REG_FIELD_PREP(TRANS_LLSYM_HACT_MASK, (x))
+
+#define _TRANS_LLSYM_HTOTAL_A			0x600e0
+#define TRANS_LLSYM_HTOTAL(display, trans) \
+	_MMIO_TRANS2(display, trans, _TRANS_LLSYM_HTOTAL_A)
+#define   TRANS_LLSYM_HTOTAL_MASK		REG_GENMASK(14, 0)
+#define   TRANS_LLSYM_HTOTAL_VAL(x)		REG_FIELD_PREP(TRANS_LLSYM_HTOTAL_MASK, (x))
+
+#define _TRANS_LLSYM_CHUNK_SIZE_A		0x600e4
+#define TRANS_LLSYM_CHUNK_SIZE(display, trans) \
+	_MMIO_TRANS2(display, trans, _TRANS_LLSYM_CHUNK_SIZE_A)
+#define   TRANS_LLSYM_CHUNK_SIZE_MASK		REG_GENMASK(11, 0)
+#define   TRANS_LLSYM_CHUNK_SIZE_VAL(x)		REG_FIELD_PREP(TRANS_LLSYM_CHUNK_SIZE_MASK, (x))
+
+/* Data M/N value DW0/DW1 at the base offset, DW2/DW3 in the _EXT register */
+#define _DP_LLSYM_DATAM_A			0x60024
+#define DP_LLSYM_DATAM(display, trans, dw) \
+	_MMIO_TRANS2(display, trans, _DP_LLSYM_DATAM_A + (dw) * 4)
+
+#define _DP_LLSYM_DATAN_A			0x60038
+#define DP_LLSYM_DATAN(display, trans, dw) \
+	_MMIO_TRANS2(display, trans, _DP_LLSYM_DATAN_A + (dw) * 4)
+
+#define _DP_LLSYM_DATAM_EXT_A			0x60470
+#define DP_LLSYM_DATAM_EXT(display, trans, dw) \
+	_MMIO_TRANS2(display, trans, _DP_LLSYM_DATAM_EXT_A + (dw) * 4)
+
+#define _DP_LLSYM_DATAN_EXT_A			0x60478
+#define DP_LLSYM_DATAN_EXT(display, trans, dw) \
+	_MMIO_TRANS2(display, trans, _DP_LLSYM_DATAN_EXT_A + (dw) * 4)
+
 /* SNB eDP training params */
 /* SNB A-stepping */
 #define  EDP_LINK_TRAIN_400MV_0DB_SNB_A		(0x38 << 22)

-- 
2.25.1

[PATCH v4 3/7] drm/i915/display: Add the DP symbol timing generator crtc state

[Arun R Murthy]

Add the DP link layer (LL) symbol based timing generator parameters to
the crtc state. Dump them in the crtc state dump and compare them in
the pipe config checker.

Bspec: 68922
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 11 +++++++++++
 drivers/gpu/drm/i915/display/intel_display.c         | 11 +++++++++++
 drivers/gpu/drm/i915/display/intel_display_types.h   | 13 +++++++++++++
 3 files changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index c51b21222dc6e7c0e6621b903fa0c04cb7508b60..2e10c9a5bba63b026d1ce02e4e1580fb5aeecb02 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -262,6 +262,17 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 			   pipe_config->dip.pps_sdp_tl,
 			   pipe_config->dip.vsc_sdp_tl,
 			   pipe_config->dip.vsc_ext_sdp_tl);
+
+		drm_printf(&p,
+			   "dp symbol tg: %s, hactive: %d, htotal: %d, chunk size: %d, data m: 0x%016llx%016llx, data n: 0x%016llx%016llx\n",
+			   str_enabled_disabled(pipe_config->dp_symbol_tg.enable),
+			   pipe_config->dp_symbol_tg.hactive,
+			   pipe_config->dp_symbol_tg.htotal,
+			   pipe_config->dp_symbol_tg.chunk_size,
+			   pipe_config->dp_symbol_tg.data_m[1],
+			   pipe_config->dp_symbol_tg.data_m[0],
+			   pipe_config->dp_symbol_tg.data_n[1],
+			   pipe_config->dp_symbol_tg.data_n[0]);
 	}
 
 	drm_printf(&p, "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index afe70e9ce34739b67e4d87754f9c361ff77f37a6..7caf5bee8718729667376b487b0584b47891f05a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5515,6 +5515,17 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
 	PIPE_CONF_CHECK_I(min_hblank);
 
+	PIPE_CONF_CHECK_BOOL(dp_symbol_tg.enable);
+	if (pipe_config->dp_symbol_tg.enable) {
+		PIPE_CONF_CHECK_I(dp_symbol_tg.hactive);
+		PIPE_CONF_CHECK_I(dp_symbol_tg.htotal);
+		PIPE_CONF_CHECK_I(dp_symbol_tg.chunk_size);
+		PIPE_CONF_CHECK_LLI(dp_symbol_tg.data_m[0]);
+		PIPE_CONF_CHECK_LLI(dp_symbol_tg.data_m[1]);
+		PIPE_CONF_CHECK_LLI(dp_symbol_tg.data_n[0]);
+		PIPE_CONF_CHECK_LLI(dp_symbol_tg.data_n[1]);
+	}
+
 	if (HAS_DOUBLE_BUFFERED_M_N(display)) {
 		if (!fastset || !pipe_config->update_m_n)
 			PIPE_CONF_CHECK_M_N(dp_m_n);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d0748837ce97ce6291b36adeb0014686f7d699f9..73fc6125a84a07a002cb7202d807833c75da130c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1196,6 +1196,19 @@ struct intel_crtc_state {
 	int max_pipe_bpp;	/* in 1 bpp units */
 	int pipe_bpp;		/* in 1 bpp units */
 	int min_hblank;
+
+	/* DP link layer (LL) symbol based timing generator, 8b/10b MST and 128b/132b SST/MST */
+	struct intel_dp_symbol_tg {
+		bool enable;
+		/* in LL symbol cycles, as opposed to the zero based register values */
+		u16 hactive;
+		u16 htotal;
+		u16 chunk_size;
+		/* 128 bit Data M/N as {low 64 bits, high 64 bits} */
+		u64 data_m[2];
+		u64 data_n[2];
+	} dp_symbol_tg;
+
 	struct intel_link_m_n dp_m_n;
 
 	/* m2_n2 for eDP downclock */

-- 
2.25.1

[PATCH v4 4/7] drm/i915/display: Add HAS_DP_SYMBOL_TG()

[Arun R Murthy]

Add a macro for the display versions with the DP link layer (LL) symbol
based timing generator.

Bspec: 68922
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 7121e7cd95124f3df88fa39f4307db4a209feea1..9c4cafd15c19c39bc0403a05c3b2da58adce1aee 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -169,6 +169,7 @@ struct intel_display_platforms {
 #define HAS_DOUBLE_WIDE(__display)	(DISPLAY_VER(__display) < 4)
 #define HAS_DP20(__display)		((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
 #define HAS_DPT(__display)		(DISPLAY_VER(__display) >= 13)
+#define HAS_DP_SYMBOL_TG(__display)	(DISPLAY_VER(__display) >= 35)
 #define HAS_DP_MST(__display)		(DISPLAY_INFO(__display)->has_dp_mst)
 #define HAS_DSB(__display)		(DISPLAY_INFO(__display)->has_dsb)
 #define HAS_DSC(__display)		(DISPLAY_RUNTIME_INFO(__display)->has_dsc)

-- 
2.25.1

[PATCH v4 5/7] drm/i915/dp: Compute the DP symbol based timing generator parameters

[Arun R Murthy]

Xe3p has a DP link layer (LL) symbol based timing generator, which
makes the per-line symbol insertion for 8b/10b MST and 128b/132b
SST/MST compliant with the DP 2.1 hblank symbol cycle count, reducing
the line-to-line hblank jitter that some sinks can't handle.

The Data M/N registers are 128 bits wide, so the Data M/N is computed as
128 bit values, without reducing them apart from the GCDs of the pixel
clock/link rate and of the SSC efficiency, to keep the full precision.

The timing generator is not used (yet) with the MSO/eDP splitter, and if
the values don't fit the hardware the pixel based timing generator is
kept. The Min Hblank mechanism must not be used together with the symbol
timing generator, so clear min_hblank when it is used.

v3: Move crtc parameters, checker and dump to new patch (Suraj)
v4: dpcd caps bases ssc capability => intel_panel_use_ssc (Suraj)
    Use gcd() from linux/gcd.h

Bspec: 68922
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c     | 171 ++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h     |   3 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c |   6 +
 3 files changed, 180 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index db7c8fcc8683aae1a2bc7050ef7c87ed5155c8dc..788c16df9801131294c73420c2c0d4d3ec848310 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -26,6 +26,7 @@
  */
 
 #include <linux/export.h>
+#include <linux/gcd.h>
 #include <linux/i2c.h>
 #include <linux/iopoll.h>
 #include <linux/log2.h>
@@ -1269,6 +1270,12 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
 	return true;
 }
 
+/* The symbol based timing generator is used for 8b/10b MST and 128b/132b SST/MST */
+static bool intel_dp_has_symbol_tg(struct intel_display *display, bool is_mst, bool is_uhbr)
+{
+	return HAS_DP_SYMBOL_TG(display) && (is_mst || is_uhbr);
+}
+
 static int
 intel_dp_get_max_m_n_ratio(struct intel_display *display)
 {
@@ -3734,6 +3741,165 @@ int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
 	return 0;
 }
 
+/* Number of symbols the transcoder link layer processes in a symbol cycle */
+#define LL_SYMBOLS_PER_CYCLE	4
+
+/* 64 x 64 -> 128 bit multiplication, result as {lo, hi} */
+static void intel_dp_mul_u64_u64(u64 a, u64 b, u64 res[2])
+{
+	res[0] = a * b;
+	res[1] = mul_u64_u64_shr(a, b, 64);
+}
+
+/* Compare two {lo, hi} 128 bit values */
+static int intel_dp_cmp_u128(const u64 a[2], const u64 b[2])
+{
+	if (a[1] != b[1])
+		return a[1] > b[1] ? 1 : -1;
+
+	if (a[0] != b[0])
+		return a[0] > b[0] ? 1 : -1;
+
+	return 0;
+}
+
+/* Compute the DP link layer (LL) symbol based timing generator parameters */
+int intel_dp_compute_symbol_tg(struct intel_dp *intel_dp,
+			       struct intel_crtc_state *crtc_state,
+			       const struct drm_connector_state *conn_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	const struct drm_display_mode *adjusted_mode =
+					&crtc_state->hw.adjusted_mode;
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
+	struct intel_dp_symbol_tg *tg = &crtc_state->dp_symbol_tg;
+	bool is_uhbr = intel_dp_is_uhbr(crtc_state);
+	int symbol_size = is_uhbr ? 32 : 8;
+	int hactive_cycles, hblank_cycles, chunk_cycles = 0;
+	int hblank_pixels;
+	int dsc_slices, link_bpp_x16;
+	u32 ch_num, ch_den, ssc_num, ssc_den, spread_x1000, link_rate_mbps;
+	u32 rate_gcd, ssc_gcd;
+	u64 data_m[2], data_n[2];
+	int ret;
+
+	memset(tg, 0, sizeof(*tg));
+
+	/* The symbol based timing generator is used for 8b/10b MST and 128b/132b SST/MST */
+	if (!intel_dp_has_symbol_tg(display,
+				    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST),
+				    is_uhbr))
+		return 0;
+
+	/* TODO: Support the symbol based timing generator with MSO/eDP splitter */
+	if (crtc_state->splitter.enable)
+		return 0;
+
+	ret = intel_dp_compute_dsc_slices_and_link_bpp(crtc_state, connector,
+						       &dsc_slices, &link_bpp_x16);
+	if (ret)
+		return ret;
+
+	if (crtc_state->dsc.compression_enable) {
+		int slice_width = DIV_ROUND_UP(adjusted_mode->hdisplay, dsc_slices);
+		int chunk_bytes = DIV_ROUND_UP(slice_width * link_bpp_x16, 16 * 8);
+
+		chunk_cycles = DIV_ROUND_UP(chunk_bytes * 8,
+					    LL_SYMBOLS_PER_CYCLE * symbol_size);
+		hactive_cycles = dsc_slices * (chunk_cycles + 1);
+	} else {
+		int hact_width = adjusted_mode->hdisplay;
+		int pix_bpp_x16 = link_bpp_x16;
+
+		/* YUV 4:2:0 without DSC: half the Hactive at twice the bpp */
+		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+			hact_width /= 2;
+			pix_bpp_x16 *= 2;
+		}
+
+		hactive_cycles = DIV_ROUND_UP(DIV_ROUND_UP(hact_width, LL_SYMBOLS_PER_CYCLE) *
+					      pix_bpp_x16, 16 * symbol_size);
+	}
+
+	hblank_pixels = adjusted_mode->htotal - adjusted_mode->hdisplay;
+	hblank_cycles = DIV_ROUND_UP(DIV_ROUND_UP(hblank_pixels, LL_SYMBOLS_PER_CYCLE) *
+				     link_bpp_x16, 16 * symbol_size);
+
+	/* DP 2.1: the minimum Hblank is 5 LL symbol cycles for 8b/10b, 3 for 128b/132b */
+	hblank_cycles = max(hblank_cycles, is_uhbr ? 3 : 5);
+
+	if (hactive_cycles + hblank_cycles > TRANS_LLSYM_HTOTAL_MASK + 1 ||
+	    chunk_cycles > TRANS_LLSYM_CHUNK_SIZE_MASK) {
+		drm_dbg_kms(display->drm,
+			    "LL symbol timings out of range (hactive %d, hblank %d, chunk %d), using pixel TG\n",
+			    hactive_cycles, hblank_cycles, chunk_cycles);
+		return 0;
+	}
+
+	if (is_uhbr) {
+		ch_num = 1568768;
+		ch_den = 1622115;
+	} else if (crtc_state->fec_enable) {
+		ch_num = 51200;
+		ch_den = 65537;
+	} else {
+		ch_num = 8;
+		ch_den = 10;
+	}
+
+	/*
+	 * spread_x1000 is the spread in % multiplied by 1000, so 500 means 0.5%.
+	 * ssc_den * spread_x1000 / (200 * 1000) is ssc_den * (Spread_Amount / 200).
+	 *
+	 * With 0.5% spread: 100000 * 500 / 200000 = 250, so ssc_num = 99750.
+	 * The efficiency is 99750 / 100000 = 0.9975, which equals 1 - 0.5 / 200.
+	 * With no SSC the spread is 0, so ssc_num = ssc_den and the efficiency
+	 * is 1.
+	 *
+	 * SSC is used only if both the panel/VBT policy and the sink allow it,
+	 * same as for the PHY PLL programming.
+	 */
+	ssc_den = 100000;
+	spread_x1000 = intel_panel_use_ssc(display) &&
+		       intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5 ? 500 : 0;
+	ssc_num = ssc_den - DIV_ROUND_CLOSEST(ssc_den * spread_x1000, 200 * 1000);
+
+	/* The link rate in Mbps, port_clock is in 10 kbps units */
+	link_rate_mbps = crtc_state->port_clock / 100;
+
+	rate_gcd = gcd(adjusted_mode->crtc_clock, link_rate_mbps);
+	ssc_gcd = gcd(ssc_num, ssc_den);
+
+	intel_dp_mul_u64_u64((u64)(adjusted_mode->crtc_clock / rate_gcd) *
+			     LL_SYMBOLS_PER_CYCLE * symbol_size * ch_den,
+			     (u64)(hactive_cycles + hblank_cycles) * (ssc_den / ssc_gcd),
+			     data_m);
+	intel_dp_mul_u64_u64((u64)(link_rate_mbps / rate_gcd) * crtc_state->lane_count *
+			     adjusted_mode->htotal * 1000,
+			     (u64)ch_num * (ssc_num / ssc_gcd),
+			     data_n);
+
+	if (intel_dp_cmp_u128(data_m, data_n) > 0) {
+		drm_dbg_kms(display->drm,
+			    "LL symbol data M/N ratio exceeds 1.0, using pixel TG\n");
+		return 0;
+	}
+
+	tg->enable = true;
+	tg->hactive = hactive_cycles;
+	tg->htotal = hactive_cycles + hblank_cycles;
+	tg->chunk_size = chunk_cycles;
+	tg->data_m[0] = data_m[0];
+	tg->data_m[1] = data_m[1];
+	tg->data_n[0] = data_n[0];
+	tg->data_n[1] = data_n[1];
+
+	/* The Min Hblank mechanism must not be used with the symbol TG */
+	crtc_state->min_hblank = 0;
+
+	return 0;
+}
+
 int
 intel_dp_compute_config(struct intel_atomic_state *state,
 			struct intel_encoder *encoder,
@@ -3834,6 +4000,11 @@ intel_dp_compute_config(struct intel_atomic_state *state,
 	if (ret)
 		return ret;
 
+	/* Clears min_hblank if the symbol based timing generator gets enabled */
+	ret = intel_dp_compute_symbol_tg(intel_dp, pipe_config, conn_state);
+	if (ret)
+		return ret;
+
 	/* FIXME: abstract this better */
 	if (pipe_config->splitter.enable)
 		pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 1f4a3aff9abebdb2bf8cd17a77231e5af66f47ac..352c656299e3b2d81e0612a71da6247d02b5aa17 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -215,6 +215,9 @@ int intel_dp_dsc_min_src_input_bpc(void);
 int intel_dp_dsc_min_src_compressed_bpp(void);
 int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
 				const struct drm_connector_state *conn_state);
+int intel_dp_compute_symbol_tg(struct intel_dp *intel_dp,
+			       struct intel_crtc_state *crtc_state,
+			       const struct drm_connector_state *conn_state);
 
 int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector);
 void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 1e6190689e6b2616ed850d61c5bfbf60a62c5422..81ac454603603df42db477ddb26cfb2f620dcfea 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -732,6 +732,12 @@ static int mst_stream_compute_link_for_joined_pipes(struct intel_encoder *encode
 	if (ret)
 		return ret;
 
+	/* Clears min_hblank if the symbol based timing generator gets enabled */
+	ret = intel_dp_compute_symbol_tg(connector->mst.dp,
+					 pipe_config, conn_state);
+	if (ret)
+		return ret;
+
 	return 0;
 }
 

-- 
2.25.1

[PATCH v4 6/7] drm/i915/display: Program and enable the DP symbol based timing generator

[Arun R Murthy]

Program the 128 bit LL symbol Data M/N before the LINK_N write which
arms the double buffered update, the LL symbol HACT/HTOTAL/CHUNK_SIZE
along with the other transcoder timings, and enable the timing
generator via TRANSCONF.DP_Symbol_TG_Enable before the transcoder is
enabled.

v3: Remove redundant HAS_DP_SYMBOL_TG (Jani)
    Use intel_de_read64_2x32()

Bspec: 68849, 68922, 69961
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c     |   2 +
 drivers/gpu/drm/i915/display/intel_display.c | 101 ++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_display.h |   1 +
 3 files changed, 101 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a46ab5d3d70fc75c6975f46e14d1b0c24dc1ba5e..c814e0740aa064f56d844e304c0a93d1047475c6 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4083,6 +4083,7 @@ static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder,
 			REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl);
 
 	intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n);
+	intel_cpu_transcoder_get_llsym_m_n(crtc_state);
 	intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2);
 
 	crtc_state->enhanced_framing =
@@ -4119,6 +4120,7 @@ static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder,
 			REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl);
 
 	intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n);
+	intel_cpu_transcoder_get_llsym_m_n(crtc_state);
 
 	if (DISPLAY_VER(display) >= 11)
 		crtc_state->fec_enable =
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7caf5bee8718729667376b487b0584b47891f05a..71a2f96b5e8f8474fd9ef24ac1c1ac89bcdeff0a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -521,9 +521,14 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
 		return;
 	}
 
-	/* Wa_1409098942:adlp+ */
-	if (DISPLAY_VER(display) >= 13 &&
-	    new_crtc_state->dsc.compression_enable) {
+	/* The early pixel count is in symbols with the DP symbol TG, no scaling */
+	if (new_crtc_state->dp_symbol_tg.enable) {
+		val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
+		val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK,
+				      TRANSCONF_PIXEL_COUNT_SCALING_X1);
+	} else if (DISPLAY_VER(display) >= 13 &&
+		   new_crtc_state->dsc.compression_enable) {
+		/* Wa_1409098942:adlp+ */
 		val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
 		val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK,
 				      TRANSCONF_PIXEL_COUNT_SCALING_X4);
@@ -588,6 +593,14 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
 
 	if ((val & TRANSCONF_ENABLE) == 0)
 		intel_wait_for_pipe_off(old_crtc_state);
+
+	/* Disable the DP symbol based timing generator */
+	if (old_crtc_state->dp_symbol_tg.enable) {
+		intel_de_rmw(display, TRANSCONF(display, cpu_transcoder),
+			     TRANSCONF_DP_SYMBOL_TG_ENABLE, 0);
+		intel_de_write(display, TRANS_LLSYM_HACT(display, cpu_transcoder), 0);
+		intel_de_write(display, TRANS_LLSYM_HTOTAL(display, cpu_transcoder), 0);
+	}
 }
 
 u32 intel_plane_fb_max_stride(struct intel_display *display,
@@ -1683,6 +1696,52 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
 		     HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));
 }
 
+static void intel_cpu_transcoder_set_llsym_m_n(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder transcoder = crtc_state->cpu_transcoder;
+	const struct intel_dp_symbol_tg *tg = &crtc_state->dp_symbol_tg;
+
+	if (!tg->enable)
+		return;
+
+	/*
+	 * These are double buffered, updated by the LINK_N write in
+	 * intel_set_m_n(), so must be written before that.
+	 */
+	intel_de_write(display, DP_LLSYM_DATAM(display, transcoder, 0),
+		       lower_32_bits(tg->data_m[0]));
+	intel_de_write(display, DP_LLSYM_DATAM(display, transcoder, 1),
+		       upper_32_bits(tg->data_m[0]));
+	intel_de_write(display, DP_LLSYM_DATAM_EXT(display, transcoder, 0),
+		       lower_32_bits(tg->data_m[1]));
+	intel_de_write(display, DP_LLSYM_DATAM_EXT(display, transcoder, 1),
+		       upper_32_bits(tg->data_m[1]));
+	intel_de_write(display, DP_LLSYM_DATAN(display, transcoder, 0),
+		       lower_32_bits(tg->data_n[0]));
+	intel_de_write(display, DP_LLSYM_DATAN(display, transcoder, 1),
+		       upper_32_bits(tg->data_n[0]));
+	intel_de_write(display, DP_LLSYM_DATAN_EXT(display, transcoder, 0),
+		       lower_32_bits(tg->data_n[1]));
+	intel_de_write(display, DP_LLSYM_DATAN_EXT(display, transcoder, 1),
+		       upper_32_bits(tg->data_n[1]));
+}
+
+void intel_cpu_transcoder_get_llsym_m_n(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder transcoder = crtc_state->cpu_transcoder;
+	struct intel_dp_symbol_tg *tg = &crtc_state->dp_symbol_tg;
+
+	if (!tg->enable)
+		return;
+
+	tg->data_m[0] = intel_de_read64_2x32(display, DP_LLSYM_DATAM(display, transcoder, 0));
+	tg->data_m[1] = intel_de_read64_2x32(display, DP_LLSYM_DATAM_EXT(display, transcoder, 0));
+	tg->data_n[0] = intel_de_read64_2x32(display, DP_LLSYM_DATAN(display, transcoder, 0));
+	tg->data_n[1] = intel_de_read64_2x32(display, DP_LLSYM_DATAN_EXT(display, transcoder, 0));
+}
+
 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -1693,6 +1752,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
 		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
 					       &crtc_state->fdi_m_n);
 	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
+		intel_cpu_transcoder_set_llsym_m_n(crtc_state);
 		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
 					       &crtc_state->dp_m_n);
 		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
@@ -2929,6 +2989,17 @@ void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state,
 		intel_de_write(display, DP_MIN_HBLANK_CTL(transcoder),
 			       crtc_state->min_hblank);
 	}
+
+	if (crtc_state->dp_symbol_tg.enable) {
+		const struct intel_dp_symbol_tg *tg = &crtc_state->dp_symbol_tg;
+
+		intel_de_write(display, TRANS_LLSYM_HACT(display, transcoder),
+			       TRANS_LLSYM_HACT_VAL(tg->hactive - 1));
+		intel_de_write(display, TRANS_LLSYM_HTOTAL(display, transcoder),
+			       TRANS_LLSYM_HTOTAL_VAL(tg->htotal - 1));
+		intel_de_write(display, TRANS_LLSYM_CHUNK_SIZE(display, transcoder),
+			       TRANS_LLSYM_CHUNK_SIZE_VAL(tg->chunk_size));
+	}
 }
 
 void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state,
@@ -3095,6 +3166,26 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
 	if (DISPLAY_VER(display) >= 30)
 		pipe_config->min_hblank = intel_de_read(display,
 							DP_MIN_HBLANK_CTL(cpu_transcoder));
+
+	if (HAS_DP_SYMBOL_TG(display)) {
+		tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
+
+		if (tmp & TRANSCONF_DP_SYMBOL_TG_ENABLE) {
+			struct intel_dp_symbol_tg *tg = &pipe_config->dp_symbol_tg;
+			u32 hact, htotal, chunk_size;
+
+			hact = intel_de_read(display, TRANS_LLSYM_HACT(display, cpu_transcoder));
+			htotal = intel_de_read(display,
+					       TRANS_LLSYM_HTOTAL(display, cpu_transcoder));
+			chunk_size = intel_de_read(display,
+						   TRANS_LLSYM_CHUNK_SIZE(display, cpu_transcoder));
+
+			tg->enable = true;
+			tg->hactive = REG_FIELD_GET(TRANS_LLSYM_HACT_MASK, hact) + 1;
+			tg->htotal = REG_FIELD_GET(TRANS_LLSYM_HTOTAL_MASK, htotal) + 1;
+			tg->chunk_size = REG_FIELD_GET(TRANS_LLSYM_CHUNK_SIZE_MASK, chunk_size);
+		}
+	}
 }
 
 static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
@@ -3419,6 +3510,10 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
 	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
 		val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW;
 
+	/* Must be set before the transcoder is enabled, so only on modeset */
+	if (crtc_state->dp_symbol_tg.enable)
+		val |= TRANSCONF_DP_SYMBOL_TG_ENABLE;
+
 	intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
 	intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index d53b7b4a80e75f8cb3a76d923d05648ffe505e2d..fa9ae8799a1999d9dd6a1f4e4d56983b6536ba26 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -446,6 +446,7 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
 				    enum transcoder cpu_transcoder,
 				    struct intel_link_m_n *m_n);
 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
+void intel_cpu_transcoder_get_llsym_m_n(struct intel_crtc_state *crtc_state);
 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);
 int intel_max_uncompressed_dotclock(struct intel_display *display);
 enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);

-- 
2.25.1

[PATCH v4 7/7] drm/i915/dp: Don't limit the Link M/N ratio with the symbol timing generator

[Arun R Murthy]

The limit on the Link M/N ratio only applies to the pixel based timing
generator, there is no such restriction when the symbol based timing
generator is used.

Bspec: 68922
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c     | 17 +++++++++++++----
 drivers/gpu/drm/i915/display/intel_dp_mst.c |  4 +++-
 2 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 788c16df9801131294c73420c2c0d4d3ec848310..a8fa0809079e8b3f6fb574cfb73fb6bb8b019cc3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1277,8 +1277,12 @@ static bool intel_dp_has_symbol_tg(struct intel_display *display, bool is_mst, b
 }
 
 static int
-intel_dp_get_max_m_n_ratio(struct intel_display *display)
+intel_dp_get_max_m_n_ratio(struct intel_display *display, bool is_mst, int link_rate)
 {
+	/* No Link M/N ratio limit with the symbol based timing generator */
+	if (intel_dp_has_symbol_tg(display, is_mst, drm_dp_is_uhbr_rate(link_rate)))
+		return INT_MAX;
+
 	if (DISPLAY_VER(display) >= 35)
 		return 22;
 
@@ -1308,7 +1312,9 @@ bool intel_dp_can_support_m_n(struct intel_display *display,
 			      const struct intel_crtc_state *crtc_state,
 			      int pixel_clock, int link_rate)
 {
-	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
+	bool is_mst = crtc_state &&
+		      intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
+	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display, is_mst, link_rate);
 	enum transcoder cpu_transcoder = TRANSCODER_A;
 	u32 link_m, link_n;
 	int m_n_ratio;
@@ -1331,7 +1337,10 @@ void intel_dp_check_m_n_ratio(const struct intel_crtc_state *crtc_state,
 			      struct intel_link_m_n *m_n)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
+	int max_m_n_ratio =
+		intel_dp_get_max_m_n_ratio(display,
+					   intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST),
+					   crtc_state->port_clock);
 	int m_n_ratio;
 
 	m_n->bypass_m_n_ratio_limit = false;
@@ -2815,7 +2824,7 @@ intel_dp_compute_m_n_ratio_limits(struct intel_dp *intel_dp,
 		drm_dbg_kms(display->drm,
 			    "[CONNECTOR:%d:%s] No link config with a Link M/N ratio <= %d\n",
 			    connector->base.base.id, connector->base.name,
-			    intel_dp_get_max_m_n_ratio(display));
+			    intel_dp_get_max_m_n_ratio(display, false, 0));
 
 		return false;
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 81ac454603603df42db477ddb26cfb2f620dcfea..fe9cdf771f481fc8a8b8f3f29e4a24aa53a53f94 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1570,7 +1570,9 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 					   min_link_bpp_x16,
 					   bw_overhead_flags);
 
-	if (!intel_dp_can_support_m_n(display, NULL, mode->clock, max_link_clock)) {
+	/* MST always uses the symbol based timing generator, which has no Link M/N ratio limit */
+	if (!HAS_DP_SYMBOL_TG(display) &&
+	    !intel_dp_can_support_m_n(display, NULL, mode->clock, max_link_clock)) {
 		*status = MODE_CLOCK_HIGH;
 		return 0;
 	}

-- 
2.25.1

✓ CI.KUnit: success for drm/i915/dp: Add support for the DP symbol based timing generator (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Add support for the DP symbol based timing generator (rev3)
URL   : https://patchwork.freedesktop.org/series/177001/
State : success

== Summary ==

+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[10:11:18] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:11:23] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:11:44] Starting KUnit Kernel (1/1)...
[10:11:44] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:11:44] ================= gpu_buddy (14 subtests) ==================
[10:11:44] [PASSED] gpu_test_buddy_alloc_limit
[10:11:44] [PASSED] gpu_test_buddy_alloc_optimistic
[10:11:44] [PASSED] gpu_test_buddy_alloc_pessimistic
[10:11:44] [PASSED] gpu_test_buddy_alloc_pathological
[10:11:44] [PASSED] gpu_test_buddy_alloc_contiguous
[10:11:44] [PASSED] gpu_test_buddy_alloc_clear
[10:11:44] [PASSED] gpu_test_buddy_alloc_range
[10:11:44] [PASSED] gpu_test_buddy_alloc_range_bias
[10:11:45] [PASSED] gpu_test_buddy_fragmentation_performance
[10:11:45] [PASSED] gpu_test_buddy_dirty_tracker_performance
[10:11:45] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[10:11:45] [PASSED] gpu_test_buddy_offset_aligned_allocation
[10:11:45] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[10:11:45] [PASSED] gpu_test_buddy_addr_to_block
[10:11:45] ==================== [PASSED] gpu_buddy ====================
[10:11:45] ============================================================
[10:11:45] Testing complete. Ran 14 tests: passed: 14
[10:11:45] Elapsed time: 27.307s total, 5.075s configuring, 20.365s building, 1.827s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[10:11:46] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:11:48] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:12:26] Starting KUnit Kernel (1/1)...
[10:12:26] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:12:26] ================== guc_buf (11 subtests) ===================
[10:12:26] [PASSED] test_smallest
[10:12:26] [PASSED] test_largest
[10:12:26] [PASSED] test_granular
[10:12:26] [PASSED] test_unique
[10:12:26] [PASSED] test_overlap
[10:12:26] [PASSED] test_reusable
[10:12:26] [PASSED] test_too_big
[10:12:26] [PASSED] test_flush
[10:12:26] [PASSED] test_lookup
[10:12:26] [PASSED] test_data
[10:12:26] [PASSED] test_class
[10:12:26] ===================== [PASSED] guc_buf =====================
[10:12:26] =================== guc_dbm (7 subtests) ===================
[10:12:26] [PASSED] test_empty
[10:12:26] [PASSED] test_default
[10:12:26] ======================== test_size  ========================
[10:12:26] [PASSED] 4
[10:12:26] [PASSED] 8
[10:12:26] [PASSED] 32
[10:12:26] [PASSED] 256
[10:12:26] ==================== [PASSED] test_size ====================
[10:12:26] ======================= test_reuse  ========================
[10:12:26] [PASSED] 4
[10:12:26] [PASSED] 8
[10:12:26] [PASSED] 32
[10:12:26] [PASSED] 256
[10:12:26] =================== [PASSED] test_reuse ====================
[10:12:26] =================== test_range_overlap  ====================
[10:12:26] [PASSED] 4
[10:12:26] [PASSED] 8
[10:12:26] [PASSED] 32
[10:12:26] [PASSED] 256
[10:12:26] =============== [PASSED] test_range_overlap ================
[10:12:26] =================== test_range_compact  ====================
[10:12:26] [PASSED] 4
[10:12:26] [PASSED] 8
[10:12:26] [PASSED] 32
[10:12:26] [PASSED] 256
[10:12:26] =============== [PASSED] test_range_compact ================
[10:12:26] ==================== test_range_spare  =====================
[10:12:26] [PASSED] 4
[10:12:26] [PASSED] 8
[10:12:26] [PASSED] 32
[10:12:26] [PASSED] 256
[10:12:26] ================ [PASSED] test_range_spare =================
[10:12:26] ===================== [PASSED] guc_dbm =====================
[10:12:26] ================== guc_idm (22 subtests) ===================
[10:12:26] [PASSED] bad_init
[10:12:26] [PASSED] no_init
[10:12:26] [PASSED] init_fini
[10:12:26] [PASSED] check_init_small
[10:12:26] [PASSED] check_init_shared
[10:12:26] [PASSED] check_used
[10:12:26] [PASSED] check_quota
[10:12:26] [PASSED] check_all
[10:12:26] [PASSED] check_limits
[10:12:26] [PASSED] check_overlap
[10:12:26] [PASSED] check_overlap_alloc
[10:12:26] [PASSED] check_overlap_release
[10:12:26] [PASSED] check_overlap_partial_init
[10:12:26] [PASSED] check_overlap_partial_shared_range_blocking
[10:12:26] [PASSED] check_used_usable
[10:12:26] [PASSED] check_used_shareable
[10:12:26] [PASSED] check_used_mixed
[10:12:26] [PASSED] check_release_usable_range
[10:12:26] [PASSED] check_release_shareable_range
[10:12:26] [PASSED] check_split_boundaries
[10:12:26] [PASSED] check_shareable_spare
[10:12:26] [PASSED] check_shareable_spare_fragmented_tail
[10:12:26] ===================== [PASSED] guc_idm =====================
[10:12:26] ============== guc_klv_helpers (13 subtests) ===============
[10:12:26] [PASSED] test_count
[10:12:26] [PASSED] test_encode_u32
[10:12:26] [PASSED] test_encode_u64
[10:12:26] [PASSED] test_encode_string
[10:12:26] [PASSED] test_encode_object_raw
[10:12:26] [PASSED] test_encode_object_klv
[10:12:26] [PASSED] test_encode_object_nested
[10:12:26] [PASSED] test_encode_object_basic
[10:12:26] ===================== test_decode_u16  =====================
[10:12:26] [PASSED] empty
[10:12:26] [PASSED] valid
[10:12:26] [PASSED] max
[10:12:26] [PASSED] big
[10:12:26] [PASSED] long
[10:12:26] ================= [PASSED] test_decode_u16 =================
[10:12:26] ===================== test_decode_u32  =====================
[10:12:26] [PASSED] empty
[10:12:26] [PASSED] valid
[10:12:26] [PASSED] max
[10:12:26] [PASSED] long
[10:12:26] ================= [PASSED] test_decode_u32 =================
[10:12:26] ===================== test_decode_u64  =====================
[10:12:26] [PASSED] empty
[10:12:26] [PASSED] short
[10:12:26] [PASSED] valid
[10:12:26] [PASSED] max
[10:12:26] [PASSED] long
[10:12:26] ================= [PASSED] test_decode_u64 =================
[10:12:26] ===================== test_decode_str  =====================
[10:12:26] [PASSED] empty
[10:12:26] [PASSED] one
[10:12:26] [PASSED] one_trash
[10:12:26] [PASSED] two
[10:12:26] [PASSED] two_trash
[10:12:26] [PASSED] three
[10:12:26] [PASSED] dword
[10:12:26] [PASSED] four
[10:12:26] [PASSED] five
[10:12:26] [PASSED] six
[10:12:26] [PASSED] seven
[10:12:26] [PASSED] qword
[10:12:26] ================= [PASSED] test_decode_str =================
[10:12:26] [PASSED] test_print
[10:12:26] ================= [PASSED] guc_klv_helpers =================
[10:12:26] =================== xe_log (4 subtests) ====================
[10:12:26] [PASSED] demo_cper
[10:12:26] [PASSED] demo_dmesg
[10:12:26] ======================= test_dmesg  ========================
[10:12:26] [PASSED] test_fatal
[10:12:27] [PASSED] test_fatal_tile
[10:12:27] [PASSED] test_fatal_gt
[10:12:27] [PASSED] test_fatal_comp
[10:12:27] [PASSED] test_fatal_comp_tile
[10:12:27] [PASSED] test_fatal_comp_gt
[10:12:27] [PASSED] test_fatal_all
[10:12:27] [PASSED] test_recoverable
[10:12:27] [PASSED] test_recoverable_tile
[10:12:27] [PASSED] test_recoverable_gt
[10:12:27] [PASSED] test_recoverable_comp
[10:12:27] [PASSED] test_recoverable_comp_tile
[10:12:27] [PASSED] test_recoverable_comp_gt
[10:12:27] [PASSED] test_recoverable_all
[10:12:27] [PASSED] test_info
[10:12:27] [PASSED] test_info_tile
[10:12:27] [PASSED] test_info_gt
[10:12:27] [PASSED] test_info_err
[10:12:27] [PASSED] test_info_comp
[10:12:27] [PASSED] test_info_comp_tile
[10:12:27] [PASSED] test_info_comp_gt
[10:12:27] [PASSED] test_info_all
[10:12:27] [PASSED] test_hw_fatal
[10:12:27] [PASSED] test_hw_recoverable
[10:12:27] [PASSED] test_hw_corrected
[10:12:27] [PASSED] test_hw_informational
[10:12:27] =================== [PASSED] test_dmesg ====================
[10:12:27] ====================== test_invalid  =======================
[10:12:27] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[10:12:27] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[10:12:27] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[10:12:27] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[10:12:27] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[10:12:27] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[10:12:27] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[10:12:27] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[10:12:27] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[10:12:27] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[10:12:27] ================== [SKIPPED] test_invalid ==================
[10:12:27] ===================== [PASSED] xe_log ======================
[10:12:27] ================== no_relay (3 subtests) ===================
[10:12:27] [PASSED] xe_drops_guc2pf_if_not_ready
[10:12:27] [PASSED] xe_drops_guc2vf_if_not_ready
[10:12:27] [PASSED] xe_rejects_send_if_not_ready
[10:12:27] ==================== [PASSED] no_relay =====================
[10:12:27] ================== pf_relay (14 subtests) ==================
[10:12:27] [PASSED] pf_rejects_guc2pf_too_short
[10:12:27] [PASSED] pf_rejects_guc2pf_too_long
[10:12:27] [PASSED] pf_rejects_guc2pf_no_payload
[10:12:27] [PASSED] pf_fails_no_payload
[10:12:27] [PASSED] pf_fails_bad_origin
[10:12:27] [PASSED] pf_fails_bad_type
[10:12:27] [PASSED] pf_txn_reports_error
[10:12:27] [PASSED] pf_txn_sends_pf2guc
[10:12:27] [PASSED] pf_sends_pf2guc
[10:12:27] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[10:12:27] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[10:12:27] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[10:12:27] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[10:12:27] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[10:12:27] ==================== [PASSED] pf_relay =====================
[10:12:27] ================== vf_relay (3 subtests) ===================
[10:12:27] [PASSED] vf_rejects_guc2vf_too_short
[10:12:27] [PASSED] vf_rejects_guc2vf_too_long
[10:12:27] [PASSED] vf_rejects_guc2vf_no_payload
[10:12:27] ==================== [PASSED] vf_relay =====================
[10:12:27] ================ pf_gt_config (9 subtests) =================
[10:12:27] [PASSED] fair_contexts_1vf
[10:12:27] [PASSED] fair_doorbells_1vf
[10:12:27] [PASSED] fair_ggtt_1vf
[10:12:27] ====================== fair_vram_1vf  ======================
[10:12:27] [PASSED] 3.50 GiB
[10:12:27] [PASSED] 11.5 GiB
[10:12:27] [PASSED] 15.5 GiB
[10:12:27] [PASSED] 31.5 GiB
[10:12:27] [PASSED] 63.5 GiB
[10:12:27] [PASSED] 1.91 GiB
[10:12:27] ================== [PASSED] fair_vram_1vf ==================
[10:12:27] ================ fair_vram_1vf_admin_only  =================
[10:12:27] [PASSED] 3.50 GiB
[10:12:27] [PASSED] 11.5 GiB
[10:12:27] [PASSED] 15.5 GiB
[10:12:27] [PASSED] 31.5 GiB
[10:12:27] [PASSED] 63.5 GiB
[10:12:27] [PASSED] 1.91 GiB
[10:12:27] ============ [PASSED] fair_vram_1vf_admin_only =============
[10:12:27] ====================== fair_contexts  ======================
[10:12:27] [PASSED] 1 VF
[10:12:27] [PASSED] 2 VFs
[10:12:27] [PASSED] 3 VFs
[10:12:27] [PASSED] 4 VFs
[10:12:27] [PASSED] 5 VFs
[10:12:27] [PASSED] 6 VFs
[10:12:27] [PASSED] 7 VFs
[10:12:27] [PASSED] 8 VFs
[10:12:27] [PASSED] 9 VFs
[10:12:27] [PASSED] 10 VFs
[10:12:27] [PASSED] 11 VFs
[10:12:27] [PASSED] 12 VFs
[10:12:27] [PASSED] 13 VFs
[10:12:27] [PASSED] 14 VFs
[10:12:27] [PASSED] 15 VFs
[10:12:27] [PASSED] 16 VFs
[10:12:27] [PASSED] 17 VFs
[10:12:27] [PASSED] 18 VFs
[10:12:27] [PASSED] 19 VFs
[10:12:27] [PASSED] 20 VFs
[10:12:27] [PASSED] 21 VFs
[10:12:27] [PASSED] 22 VFs
[10:12:27] [PASSED] 23 VFs
[10:12:27] [PASSED] 24 VFs
[10:12:27] [PASSED] 25 VFs
[10:12:27] [PASSED] 26 VFs
[10:12:27] [PASSED] 27 VFs
[10:12:27] [PASSED] 28 VFs
[10:12:27] [PASSED] 29 VFs
[10:12:27] [PASSED] 30 VFs
[10:12:27] [PASSED] 31 VFs
[10:12:27] [PASSED] 32 VFs
[10:12:27] [PASSED] 33 VFs
[10:12:27] [PASSED] 34 VFs
[10:12:27] [PASSED] 35 VFs
[10:12:27] [PASSED] 36 VFs
[10:12:27] [PASSED] 37 VFs
[10:12:27] [PASSED] 38 VFs
[10:12:27] [PASSED] 39 VFs
[10:12:27] [PASSED] 40 VFs
[10:12:27] [PASSED] 41 VFs
[10:12:27] [PASSED] 42 VFs
[10:12:27] [PASSED] 43 VFs
[10:12:27] [PASSED] 44 VFs
[10:12:27] [PASSED] 45 VFs
[10:12:27] [PASSED] 46 VFs
[10:12:27] [PASSED] 47 VFs
[10:12:27] [PASSED] 48 VFs
[10:12:27] [PASSED] 49 VFs
[10:12:27] [PASSED] 50 VFs
[10:12:27] [PASSED] 51 VFs
[10:12:27] [PASSED] 52 VFs
[10:12:27] [PASSED] 53 VFs
[10:12:27] [PASSED] 54 VFs
[10:12:27] [PASSED] 55 VFs
[10:12:27] [PASSED] 56 VFs
[10:12:27] [PASSED] 57 VFs
[10:12:27] [PASSED] 58 VFs
[10:12:27] [PASSED] 59 VFs
[10:12:27] [PASSED] 60 VFs
[10:12:27] [PASSED] 61 VFs
[10:12:27] [PASSED] 62 VFs
[10:12:27] [PASSED] 63 VFs
[10:12:27] ================== [PASSED] fair_contexts ==================
[10:12:27] ===================== fair_doorbells  ======================
[10:12:27] [PASSED] 1 VF
[10:12:27] [PASSED] 2 VFs
[10:12:27] [PASSED] 3 VFs
[10:12:27] [PASSED] 4 VFs
[10:12:27] [PASSED] 5 VFs
[10:12:27] [PASSED] 6 VFs
[10:12:27] [PASSED] 7 VFs
[10:12:27] [PASSED] 8 VFs
[10:12:27] [PASSED] 9 VFs
[10:12:27] [PASSED] 10 VFs
[10:12:27] [PASSED] 11 VFs
[10:12:27] [PASSED] 12 VFs
[10:12:27] [PASSED] 13 VFs
[10:12:27] [PASSED] 14 VFs
[10:12:27] [PASSED] 15 VFs
[10:12:27] [PASSED] 16 VFs
[10:12:27] [PASSED] 17 VFs
[10:12:27] [PASSED] 18 VFs
[10:12:27] [PASSED] 19 VFs
[10:12:27] [PASSED] 20 VFs
[10:12:27] [PASSED] 21 VFs
[10:12:27] [PASSED] 22 VFs
[10:12:27] [PASSED] 23 VFs
[10:12:27] [PASSED] 24 VFs
[10:12:27] [PASSED] 25 VFs
[10:12:27] [PASSED] 26 VFs
[10:12:27] [PASSED] 27 VFs
[10:12:27] [PASSED] 28 VFs
[10:12:27] [PASSED] 29 VFs
[10:12:27] [PASSED] 30 VFs
[10:12:27] [PASSED] 31 VFs
[10:12:27] [PASSED] 32 VFs
[10:12:27] [PASSED] 33 VFs
[10:12:27] [PASSED] 34 VFs
[10:12:27] [PASSED] 35 VFs
[10:12:27] [PASSED] 36 VFs
[10:12:27] [PASSED] 37 VFs
[10:12:27] [PASSED] 38 VFs
[10:12:27] [PASSED] 39 VFs
[10:12:27] [PASSED] 40 VFs
[10:12:27] [PASSED] 41 VFs
[10:12:27] [PASSED] 42 VFs
[10:12:27] [PASSED] 43 VFs
[10:12:27] [PASSED] 44 VFs
[10:12:27] [PASSED] 45 VFs
[10:12:27] [PASSED] 46 VFs
[10:12:27] [PASSED] 47 VFs
[10:12:27] [PASSED] 48 VFs
[10:12:27] [PASSED] 49 VFs
[10:12:27] [PASSED] 50 VFs
[10:12:27] [PASSED] 51 VFs
[10:12:27] [PASSED] 52 VFs
[10:12:27] [PASSED] 53 VFs
[10:12:27] [PASSED] 54 VFs
[10:12:27] [PASSED] 55 VFs
[10:12:27] [PASSED] 56 VFs
[10:12:27] [PASSED] 57 VFs
[10:12:27] [PASSED] 58 VFs
[10:12:27] [PASSED] 59 VFs
[10:12:27] [PASSED] 60 VFs
[10:12:27] [PASSED] 61 VFs
[10:12:27] [PASSED] 62 VFs
[10:12:27] [PASSED] 63 VFs
[10:12:27] ================= [PASSED] fair_doorbells ==================
[10:12:27] ======================== fair_ggtt  ========================
[10:12:27] [PASSED] 1 VF
[10:12:27] [PASSED] 2 VFs
[10:12:27] [PASSED] 3 VFs
[10:12:27] [PASSED] 4 VFs
[10:12:27] [PASSED] 5 VFs
[10:12:27] [PASSED] 6 VFs
[10:12:27] [PASSED] 7 VFs
[10:12:27] [PASSED] 8 VFs
[10:12:27] [PASSED] 9 VFs
[10:12:27] [PASSED] 10 VFs
[10:12:27] [PASSED] 11 VFs
[10:12:27] [PASSED] 12 VFs
[10:12:27] [PASSED] 13 VFs
[10:12:27] [PASSED] 14 VFs
[10:12:27] [PASSED] 15 VFs
[10:12:27] [PASSED] 16 VFs
[10:12:27] [PASSED] 17 VFs
[10:12:27] [PASSED] 18 VFs
[10:12:27] [PASSED] 19 VFs
[10:12:27] [PASSED] 20 VFs
[10:12:27] [PASSED] 21 VFs
[10:12:27] [PASSED] 22 VFs
[10:12:27] [PASSED] 23 VFs
[10:12:27] [PASSED] 24 VFs
[10:12:27] [PASSED] 25 VFs
[10:12:27] [PASSED] 26 VFs
[10:12:27] [PASSED] 27 VFs
[10:12:27] [PASSED] 28 VFs
[10:12:27] [PASSED] 29 VFs
[10:12:27] [PASSED] 30 VFs
[10:12:27] [PASSED] 31 VFs
[10:12:27] [PASSED] 32 VFs
[10:12:27] [PASSED] 33 VFs
[10:12:27] [PASSED] 34 VFs
[10:12:27] [PASSED] 35 VFs
[10:12:27] [PASSED] 36 VFs
[10:12:27] [PASSED] 37 VFs
[10:12:27] [PASSED] 38 VFs
[10:12:27] [PASSED] 39 VFs
[10:12:27] [PASSED] 40 VFs
[10:12:27] [PASSED] 41 VFs
[10:12:27] [PASSED] 42 VFs
[10:12:27] [PASSED] 43 VFs
[10:12:27] [PASSED] 44 VFs
[10:12:27] [PASSED] 45 VFs
[10:12:27] [PASSED] 46 VFs
[10:12:27] [PASSED] 47 VFs
[10:12:27] [PASSED] 48 VFs
[10:12:27] [PASSED] 49 VFs
[10:12:27] [PASSED] 50 VFs
[10:12:27] [PASSED] 51 VFs
[10:12:27] [PASSED] 52 VFs
[10:12:27] [PASSED] 53 VFs
[10:12:27] [PASSED] 54 VFs
[10:12:27] [PASSED] 55 VFs
[10:12:27] [PASSED] 56 VFs
[10:12:27] [PASSED] 57 VFs
[10:12:27] [PASSED] 58 VFs
[10:12:27] [PASSED] 59 VFs
[10:12:27] [PASSED] 60 VFs
[10:12:27] [PASSED] 61 VFs
[10:12:27] [PASSED] 62 VFs
[10:12:27] [PASSED] 63 VFs
[10:12:27] ==================== [PASSED] fair_ggtt ====================
[10:12:27] ======================== fair_vram  ========================
[10:12:27] [PASSED] 1 VF
[10:12:27] [PASSED] 2 VFs
[10:12:27] [PASSED] 3 VFs
[10:12:27] [PASSED] 4 VFs
[10:12:27] [PASSED] 5 VFs
[10:12:27] [PASSED] 6 VFs
[10:12:27] [PASSED] 7 VFs
[10:12:27] [PASSED] 8 VFs
[10:12:27] [PASSED] 9 VFs
[10:12:27] [PASSED] 10 VFs
[10:12:27] [PASSED] 11 VFs
[10:12:27] [PASSED] 12 VFs
[10:12:27] [PASSED] 13 VFs
[10:12:27] [PASSED] 14 VFs
[10:12:27] [PASSED] 15 VFs
[10:12:27] [PASSED] 16 VFs
[10:12:27] [PASSED] 17 VFs
[10:12:27] [PASSED] 18 VFs
[10:12:27] [PASSED] 19 VFs
[10:12:27] [PASSED] 20 VFs
[10:12:27] [PASSED] 21 VFs
[10:12:27] [PASSED] 22 VFs
[10:12:27] [PASSED] 23 VFs
[10:12:27] [PASSED] 24 VFs
[10:12:27] [PASSED] 25 VFs
[10:12:27] [PASSED] 26 VFs
[10:12:27] [PASSED] 27 VFs
[10:12:27] [PASSED] 28 VFs
[10:12:27] [PASSED] 29 VFs
[10:12:27] [PASSED] 30 VFs
[10:12:27] [PASSED] 31 VFs
[10:12:27] [PASSED] 32 VFs
[10:12:27] [PASSED] 33 VFs
[10:12:27] [PASSED] 34 VFs
[10:12:27] [PASSED] 35 VFs
[10:12:27] [PASSED] 36 VFs
[10:12:27] [PASSED] 37 VFs
[10:12:27] [PASSED] 38 VFs
[10:12:27] [PASSED] 39 VFs
[10:12:27] [PASSED] 40 VFs
[10:12:27] [PASSED] 41 VFs
[10:12:27] [PASSED] 42 VFs
[10:12:27] [PASSED] 43 VFs
[10:12:27] [PASSED] 44 VFs
[10:12:27] [PASSED] 45 VFs
[10:12:27] [PASSED] 46 VFs
[10:12:27] [PASSED] 47 VFs
[10:12:27] [PASSED] 48 VFs
[10:12:27] [PASSED] 49 VFs
[10:12:27] [PASSED] 50 VFs
[10:12:27] [PASSED] 51 VFs
[10:12:27] [PASSED] 52 VFs
[10:12:27] [PASSED] 53 VFs
[10:12:27] [PASSED] 54 VFs
[10:12:27] [PASSED] 55 VFs
[10:12:27] [PASSED] 56 VFs
[10:12:27] [PASSED] 57 VFs
[10:12:27] [PASSED] 58 VFs
[10:12:27] [PASSED] 59 VFs
[10:12:27] [PASSED] 60 VFs
[10:12:27] [PASSED] 61 VFs
[10:12:27] [PASSED] 62 VFs
[10:12:27] [PASSED] 63 VFs
[10:12:27] ==================== [PASSED] fair_vram ====================
[10:12:27] ================== [PASSED] pf_gt_config ===================
[10:12:27] ===================== lmtt (1 subtest) =====================
[10:12:27] ======================== test_ops  =========================
[10:12:27] [PASSED] 2-level
[10:12:27] [PASSED] multi-level
[10:12:27] ==================== [PASSED] test_ops =====================
[10:12:27] ====================== [PASSED] lmtt =======================
[10:12:27] ================= sriov_packet (1 subtest) =================
[10:12:27] [PASSED] test_descriptor_init
[10:12:27] ================== [PASSED] sriov_packet ===================
[10:12:27] ================= pf_service (11 subtests) =================
[10:12:27] [PASSED] pf_negotiate_any
[10:12:27] [PASSED] pf_negotiate_base_match
[10:12:27] [PASSED] pf_negotiate_base_newer
[10:12:27] [PASSED] pf_negotiate_base_next
[10:12:27] [SKIPPED] pf_negotiate_base_older (no older minor)
[10:12:27] [PASSED] pf_negotiate_base_prev
[10:12:27] [PASSED] pf_negotiate_latest_match
[10:12:27] [PASSED] pf_negotiate_latest_newer
[10:12:27] [PASSED] pf_negotiate_latest_next
[10:12:27] [SKIPPED] pf_negotiate_latest_older (no older minor)
[10:12:27] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[10:12:27] =================== [PASSED] pf_service ====================
[10:12:27] ================= xe_guc_g2g (2 subtests) ==================
[10:12:27] ============== xe_live_guc_g2g_kunit_default  ==============
[10:12:27] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[10:12:27] ============== xe_live_guc_g2g_kunit_allmem  ===============
[10:12:27] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[10:12:27] =================== [SKIPPED] xe_guc_g2g ===================
[10:12:27] =================== xe_mocs (2 subtests) ===================
[10:12:27] ================ xe_live_mocs_kernel_kunit  ================
[10:12:27] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[10:12:27] ================ xe_live_mocs_reset_kunit  =================
[10:12:27] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[10:12:27] ==================== [SKIPPED] xe_mocs =====================
[10:12:27] ================= xe_migrate (3 subtests) ==================
[10:12:27] ================= xe_migrate_sanity_kunit  =================
[10:12:27] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[10:12:27] ================== xe_validate_ccs_kunit  ==================
[10:12:27] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[10:12:27] ============= xe_migrate_access_memory_kunit  ==============
[10:12:27] ========= [SKIPPED] xe_migrate_access_memory_kunit =========
[10:12:27] =================== [SKIPPED] xe_migrate ===================
[10:12:27] ================== xe_dma_buf (1 subtest) ==================
[10:12:27] ==================== xe_dma_buf_kunit  =====================
[10:12:27] ================ [SKIPPED] xe_dma_buf_kunit ================
[10:12:27] =================== [SKIPPED] xe_dma_buf ===================
[10:12:27] ================= xe_bo_shrink (1 subtest) =================
[10:12:27] =================== xe_bo_shrink_kunit  ====================
[10:12:27] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[10:12:27] ================== [SKIPPED] xe_bo_shrink ==================
[10:12:27] ==================== xe_bo (2 subtests) ====================
[10:12:27] ================== xe_ccs_migrate_kunit  ===================
[10:12:27] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[10:12:27] ==================== xe_bo_evict_kunit  ====================
[10:12:27] =============== [SKIPPED] xe_bo_evict_kunit ================
[10:12:27] ===================== [SKIPPED] xe_bo ======================
[10:12:27] =================== xe_any (9 subtests) ====================
[10:12:27] [PASSED] test_to_xe
[10:12:27] [PASSED] test_to_dev
[10:12:27] [PASSED] test_to_pdev
[10:12:27] [PASSED] test_to_drm
[10:12:27] [PASSED] test_if_pdev
[10:12:27] [PASSED] test_if_xe
[10:12:27] [PASSED] test_if_tile
[10:12:27] [PASSED] test_if_gt
[10:12:27] [PASSED] test_to_id
[10:12:27] ===================== [PASSED] xe_any ======================
[10:12:27] ==================== args (13 subtests) ====================
[10:12:27] [PASSED] count_args_test
[10:12:27] [PASSED] call_args_example
[10:12:27] [PASSED] call_args_test
[10:12:27] [PASSED] drop_first_arg_example
[10:12:27] [PASSED] drop_first_arg_test
[10:12:27] [PASSED] first_arg_example
[10:12:27] [PASSED] first_arg_test
[10:12:27] [PASSED] last_arg_example
[10:12:27] [PASSED] last_arg_test
[10:12:27] [PASSED] pick_arg_example
[10:12:27] [PASSED] if_args_example
[10:12:27] [PASSED] if_args_test
[10:12:27] [PASSED] sep_comma_example
[10:12:27] ====================== [PASSED] args =======================
[10:12:27] =================== xe_pci (3 subtests) ====================
[10:12:27] ==================== check_graphics_ip  ====================
[10:12:27] [PASSED] 12.00 Xe_LP
[10:12:27] [PASSED] 12.10 Xe_LP+
[10:12:27] [PASSED] 12.55 Xe_HPG
[10:12:27] [PASSED] 12.60 Xe_HPC
[10:12:27] [PASSED] 12.70 Xe_LPG
[10:12:27] [PASSED] 12.71 Xe_LPG
[10:12:27] [PASSED] 12.74 Xe_LPG+
[10:12:27] [PASSED] 20.01 Xe2_HPG
[10:12:27] [PASSED] 20.02 Xe2_HPG
[10:12:27] [PASSED] 20.04 Xe2_LPG
[10:12:27] [PASSED] 30.00 Xe3_LPG
[10:12:27] [PASSED] 30.01 Xe3_LPG
[10:12:27] [PASSED] 30.03 Xe3_LPG
[10:12:27] [PASSED] 30.04 Xe3_LPG
[10:12:27] [PASSED] 30.05 Xe3_LPG
[10:12:27] [PASSED] 35.10 Xe3p_LPG
[10:12:27] [PASSED] 35.11 Xe3p_XPC
[10:12:27] ================ [PASSED] check_graphics_ip ================
[10:12:27] ===================== check_media_ip  ======================
[10:12:27] [PASSED] 12.00 Xe_M
[10:12:27] [PASSED] 12.55 Xe_HPM
[10:12:27] [PASSED] 13.00 Xe_LPM+
[10:12:27] [PASSED] 13.01 Xe2_HPM
[10:12:27] [PASSED] 20.00 Xe2_LPM
[10:12:27] [PASSED] 30.00 Xe3_LPM
[10:12:27] [PASSED] 30.02 Xe3_LPM
[10:12:27] [PASSED] 35.00 Xe3p_LPM
[10:12:27] [PASSED] 35.03 Xe3p_HPM
[10:12:27] ================= [PASSED] check_media_ip ==================
[10:12:27] =================== check_platform_desc  ===================
[10:12:27] [PASSED] 0x9A60 (TIGERLAKE)
[10:12:27] [PASSED] 0x9A68 (TIGERLAKE)
[10:12:27] [PASSED] 0x9A70 (TIGERLAKE)
[10:12:27] [PASSED] 0x9A40 (TIGERLAKE)
[10:12:27] [PASSED] 0x9A49 (TIGERLAKE)
[10:12:27] [PASSED] 0x9A59 (TIGERLAKE)
[10:12:27] [PASSED] 0x9A78 (TIGERLAKE)
[10:12:27] [PASSED] 0x9AC0 (TIGERLAKE)
[10:12:27] [PASSED] 0x9AC9 (TIGERLAKE)
[10:12:27] [PASSED] 0x9AD9 (TIGERLAKE)
[10:12:27] [PASSED] 0x9AF8 (TIGERLAKE)
[10:12:27] [PASSED] 0x4C80 (ROCKETLAKE)
[10:12:27] [PASSED] 0x4C8A (ROCKETLAKE)
[10:12:27] [PASSED] 0x4C8B (ROCKETLAKE)
[10:12:27] [PASSED] 0x4C8C (ROCKETLAKE)
[10:12:27] [PASSED] 0x4C90 (ROCKETLAKE)
[10:12:27] [PASSED] 0x4C9A (ROCKETLAKE)
[10:12:27] [PASSED] 0x4680 (ALDERLAKE_S)
[10:12:27] [PASSED] 0x4682 (ALDERLAKE_S)
[10:12:27] [PASSED] 0x4688 (ALDERLAKE_S)
[10:12:27] [PASSED] 0x468A (ALDERLAKE_S)
[10:12:27] [PASSED] 0x468B (ALDERLAKE_S)
[10:12:27] [PASSED] 0x4690 (ALDERLAKE_S)
[10:12:27] [PASSED] 0x4692 (ALDERLAKE_S)
[10:12:27] [PASSED] 0x4693 (ALDERLAKE_S)
[10:12:27] [PASSED] 0x46A0 (ALDERLAKE_P)
[10:12:27] [PASSED] 0x46A1 (ALDERLAKE_P)
[10:12:27] [PASSED] 0x46A2 (ALDERLAKE_P)
[10:12:27] [PASSED] 0x46A3 (ALDERLAKE_P)
[10:12:27] [PASSED] 0x46A6 (ALDERLAKE_P)
[10:12:27] [PASSED] 0x46A8 (ALDERLAKE_P)
[10:12:27] [PASSED] 0x46AA (ALDERLAKE_P)
[10:12:27] [PASSED] 0x462A (ALDERLAKE_P)
[10:12:27] [PASSED] 0x4626 (ALDERLAKE_P)
[10:12:27] [PASSED] 0x4628 (ALDERLAKE_P)
[10:12:27] [PASSED] 0x46B0 (ALDERLAKE_P)
[10:12:27] [PASSED] 0x46B1 (ALDERLAKE_P)
[10:12:27] [PASSED] 0x46B2 (ALDERLAKE_P)
[10:12:27] [PASSED] 0x46B3 (ALDERLAKE_P)
[10:12:27] [PASSED] 0x46C0 (ALDERLAKE_P)
[10:12:27] [PASSED] 0x46C1 (ALDERLAKE_P)
[10:12:27] [PASSED] 0x46C2 (ALDERLAKE_P)
[10:12:27] [PASSED] 0x46C3 (ALDERLAKE_P)
[10:12:27] [PASSED] 0x46D0 (ALDERLAKE_N)
[10:12:27] [PASSED] 0x46D1 (ALDERLAKE_N)
[10:12:27] [PASSED] 0x46D2 (ALDERLAKE_N)
[10:12:27] [PASSED] 0x46D3 (ALDERLAKE_N)
[10:12:27] [PASSED] 0x46D4 (ALDERLAKE_N)
[10:12:27] [PASSED] 0xA721 (ALDERLAKE_P)
[10:12:27] [PASSED] 0xA7A1 (ALDERLAKE_P)
[10:12:27] [PASSED] 0xA7A9 (ALDERLAKE_P)
[10:12:27] [PASSED] 0xA7AC (ALDERLAKE_P)
[10:12:27] [PASSED] 0xA7AD (ALDERLAKE_P)
[10:12:27] [PASSED] 0xA720 (ALDERLAKE_P)
[10:12:27] [PASSED] 0xA7A0 (ALDERLAKE_P)
[10:12:27] [PASSED] 0xA7A8 (ALDERLAKE_P)
[10:12:27] [PASSED] 0xA7AA (ALDERLAKE_P)
[10:12:27] [PASSED] 0xA7AB (ALDERLAKE_P)
[10:12:27] [PASSED] 0xA780 (ALDERLAKE_S)
[10:12:27] [PASSED] 0xA781 (ALDERLAKE_S)
[10:12:27] [PASSED] 0xA782 (ALDERLAKE_S)
[10:12:27] [PASSED] 0xA783 (ALDERLAKE_S)
[10:12:27] [PASSED] 0xA788 (ALDERLAKE_S)
[10:12:27] [PASSED] 0xA789 (ALDERLAKE_S)
[10:12:27] [PASSED] 0xA78A (ALDERLAKE_S)
[10:12:27] [PASSED] 0xA78B (ALDERLAKE_S)
[10:12:27] [PASSED] 0x4905 (DG1)
[10:12:27] [PASSED] 0x4906 (DG1)
[10:12:27] [PASSED] 0x4907 (DG1)
[10:12:27] [PASSED] 0x4908 (DG1)
[10:12:27] [PASSED] 0x4909 (DG1)
[10:12:27] [PASSED] 0x56C0 (DG2)
[10:12:27] [PASSED] 0x56C2 (DG2)
[10:12:27] [PASSED] 0x56C1 (DG2)
[10:12:27] [PASSED] 0x7D51 (METEORLAKE)
[10:12:27] [PASSED] 0x7DD1 (METEORLAKE)
[10:12:27] [PASSED] 0x7D41 (METEORLAKE)
[10:12:27] [PASSED] 0x7D67 (METEORLAKE)
[10:12:27] [PASSED] 0xB640 (METEORLAKE)
[10:12:27] [PASSED] 0x56A0 (DG2)
[10:12:27] [PASSED] 0x56A1 (DG2)
[10:12:27] [PASSED] 0x56A2 (DG2)
[10:12:27] [PASSED] 0x56BE (DG2)
[10:12:27] [PASSED] 0x56BF (DG2)
[10:12:27] [PASSED] 0x5690 (DG2)
[10:12:27] [PASSED] 0x5691 (DG2)
[10:12:27] [PASSED] 0x5692 (DG2)
[10:12:27] [PASSED] 0x56A5 (DG2)
[10:12:27] [PASSED] 0x56A6 (DG2)
[10:12:27] [PASSED] 0x56B0 (DG2)
[10:12:27] [PASSED] 0x56B1 (DG2)
[10:12:27] [PASSED] 0x56BA (DG2)
[10:12:27] [PASSED] 0x56BB (DG2)
[10:12:27] [PASSED] 0x56BC (DG2)
[10:12:27] [PASSED] 0x56BD (DG2)
[10:12:27] [PASSED] 0x5693 (DG2)
[10:12:27] [PASSED] 0x5694 (DG2)
[10:12:27] [PASSED] 0x5695 (DG2)
[10:12:27] [PASSED] 0x56A3 (DG2)
[10:12:27] [PASSED] 0x56A4 (DG2)
[10:12:27] [PASSED] 0x56B2 (DG2)
[10:12:27] [PASSED] 0x56B3 (DG2)
[10:12:27] [PASSED] 0x5696 (DG2)
[10:12:27] [PASSED] 0x5697 (DG2)
[10:12:27] [PASSED] 0xB69 (PVC)
[10:12:27] [PASSED] 0xB6E (PVC)
[10:12:27] [PASSED] 0xBD4 (PVC)
[10:12:27] [PASSED] 0xBD5 (PVC)
[10:12:27] [PASSED] 0xBD6 (PVC)
[10:12:27] [PASSED] 0xBD7 (PVC)
[10:12:27] [PASSED] 0xBD8 (PVC)
[10:12:27] [PASSED] 0xBD9 (PVC)
[10:12:27] [PASSED] 0xBDA (PVC)
[10:12:27] [PASSED] 0xBDB (PVC)
[10:12:27] [PASSED] 0xBE0 (PVC)
[10:12:27] [PASSED] 0xBE1 (PVC)
[10:12:27] [PASSED] 0xBE5 (PVC)
[10:12:27] [PASSED] 0x7D40 (METEORLAKE)
[10:12:27] [PASSED] 0x7D45 (METEORLAKE)
[10:12:27] [PASSED] 0x7D55 (METEORLAKE)
[10:12:27] [PASSED] 0x7D60 (METEORLAKE)
[10:12:27] [PASSED] 0x7DD5 (METEORLAKE)
[10:12:27] [PASSED] 0x6420 (LUNARLAKE)
[10:12:27] [PASSED] 0x64A0 (LUNARLAKE)
[10:12:27] [PASSED] 0x64B0 (LUNARLAKE)
[10:12:27] [PASSED] 0xE202 (BATTLEMAGE)
[10:12:27] [PASSED] 0xE209 (BATTLEMAGE)
[10:12:27] [PASSED] 0xE20B (BATTLEMAGE)
[10:12:27] [PASSED] 0xE20C (BATTLEMAGE)
[10:12:27] [PASSED] 0xE20D (BATTLEMAGE)
[10:12:27] [PASSED] 0xE210 (BATTLEMAGE)
[10:12:27] [PASSED] 0xE211 (BATTLEMAGE)
[10:12:27] [PASSED] 0xE212 (BATTLEMAGE)
[10:12:27] [PASSED] 0xE216 (BATTLEMAGE)
[10:12:27] [PASSED] 0xE220 (BATTLEMAGE)
[10:12:27] [PASSED] 0xE221 (BATTLEMAGE)
[10:12:27] [PASSED] 0xE222 (BATTLEMAGE)
[10:12:27] [PASSED] 0xE223 (BATTLEMAGE)
[10:12:27] [PASSED] 0xB080 (PANTHERLAKE)
[10:12:27] [PASSED] 0xB081 (PANTHERLAKE)
[10:12:27] [PASSED] 0xB082 (PANTHERLAKE)
[10:12:27] [PASSED] 0xB083 (PANTHERLAKE)
[10:12:27] [PASSED] 0xB084 (PANTHERLAKE)
[10:12:27] [PASSED] 0xB085 (PANTHERLAKE)
[10:12:27] [PASSED] 0xB086 (PANTHERLAKE)
[10:12:27] [PASSED] 0xB087 (PANTHERLAKE)
[10:12:27] [PASSED] 0xB08F (PANTHERLAKE)
[10:12:27] [PASSED] 0xB090 (PANTHERLAKE)
[10:12:27] [PASSED] 0xB0A0 (PANTHERLAKE)
[10:12:27] [PASSED] 0xB0A1 (PANTHERLAKE)
[10:12:27] [PASSED] 0xB0B0 (PANTHERLAKE)
[10:12:27] [PASSED] 0xFD80 (PANTHERLAKE)
[10:12:27] [PASSED] 0xFD81 (PANTHERLAKE)
[10:12:27] [PASSED] 0xD740 (NOVALAKE_S)
[10:12:27] [PASSED] 0xD741 (NOVALAKE_S)
[10:12:27] [PASSED] 0xD742 (NOVALAKE_S)
[10:12:27] [PASSED] 0xD743 (NOVALAKE_S)
[10:12:27] [PASSED] 0xD745 (NOVALAKE_S)
[10:12:27] [PASSED] 0xD74A (NOVALAKE_S)
[10:12:27] [PASSED] 0xD74B (NOVALAKE_S)
[10:12:27] [PASSED] 0x674C (CRESCENTISLAND)
[10:12:27] [PASSED] 0x674D (CRESCENTISLAND)
[10:12:27] [PASSED] 0x674E (CRESCENTISLAND)
[10:12:27] [PASSED] 0x674F (CRESCENTISLAND)
[10:12:27] [PASSED] 0x6750 (CRESCENTISLAND)
[10:12:27] [PASSED] 0x6751 (CRESCENTISLAND)
[10:12:27] [PASSED] 0x6752 (CRESCENTISLAND)
[10:12:27] [PASSED] 0xD750 (NOVALAKE_P)
[10:12:27] [PASSED] 0xD751 (NOVALAKE_P)
[10:12:27] [PASSED] 0xD752 (NOVALAKE_P)
[10:12:27] [PASSED] 0xD753 (NOVALAKE_P)
[10:12:27] [PASSED] 0xD754 (NOVALAKE_P)
[10:12:27] [PASSED] 0xD755 (NOVALAKE_P)
[10:12:27] [PASSED] 0xD756 (NOVALAKE_P)
[10:12:27] [PASSED] 0xD757 (NOVALAKE_P)
[10:12:27] [PASSED] 0xD75F (NOVALAKE_P)
[10:12:27] =============== [PASSED] check_platform_desc ===============
[10:12:27] ===================== [PASSED] xe_pci ======================
[10:12:27] ============= xe_rtp_tables_test (5 subtests) ==============
[10:12:27] ================== xe_rtp_table_gt_test  ===================
[10:12:27] [PASSED] gt_was/14011060649
[10:12:27] [PASSED] gt_was/14011059788
[10:12:27] [PASSED] gt_was/14015795083
[10:12:27] [PASSED] gt_was/16021867713
[10:12:27] [PASSED] gt_was/14019449301
[10:12:27] [PASSED] gt_was/16028005424
[10:12:27] [PASSED] gt_was/14026578760
[10:12:27] [PASSED] gt_was/1409420604
[10:12:27] [PASSED] gt_was/1408615072
[10:12:27] [PASSED] gt_was/22010523718
[10:12:27] [PASSED] gt_was/14011006942
[10:12:27] [PASSED] gt_was/14014830051
[10:12:27] [PASSED] gt_was/18018781329
[10:12:27] [PASSED] gt_was/1509235366
[10:12:27] [PASSED] gt_was/18018781329
[10:12:27] [PASSED] gt_was/16016694945
[10:12:27] [PASSED] gt_was/14018575942
[10:12:27] [PASSED] gt_was/22016670082
[10:12:27] [PASSED] gt_was/22016670082
[10:12:27] [PASSED] gt_was/14017421178
[10:12:27] [PASSED] gt_was/16025250150
[10:12:27] [PASSED] gt_was/14021871409
[10:12:27] [PASSED] gt_was/16021865536
[10:12:27] [PASSED] gt_was/14021486841
[10:12:27] [PASSED] gt_was/14025160223
[10:12:27] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[10:12:27] [PASSED] gt_was/14025635424
[10:12:27] [PASSED] gt_was/16028005424
[10:12:27] ============== [PASSED] xe_rtp_table_gt_test ===============
[10:12:27] ================== xe_rtp_table_gt_test  ===================
[10:12:27] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[10:12:27] [PASSED] gt_tunings/Tuning: 32B Access Enable
[10:12:27] [PASSED] gt_tunings/Tuning: L3 cache
[10:12:27] [PASSED] gt_tunings/Tuning: L3 cache - media
[10:12:27] [PASSED] gt_tunings/Tuning: Compression Overfetch
[10:12:27] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[10:12:27] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[10:12:27] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[10:12:27] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[10:12:27] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[10:12:27] [PASSED] gt_tunings/Tuning: Stateless compression control
[10:12:27] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[10:12:27] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[10:12:27] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[10:12:27] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[10:12:27] [PASSED] gt_tunings/Tuning: Force All Non-Compressible Memory Reads to be 256B Overfetches
[10:12:27] ============== [PASSED] xe_rtp_table_gt_test ===============
[10:12:27] ================== xe_rtp_table_oob_test  ==================
[10:12:27] [PASSED] oob_was/1607983814
[10:12:27] [PASSED] oob_was/16010904313
[10:12:27] [PASSED] oob_was/18022495364
[10:12:27] [PASSED] oob_was/22012773006
[10:12:27] [PASSED] oob_was/14014475959
[10:12:27] [PASSED] oob_was/22011391025
[10:12:27] [PASSED] oob_was/22012727170
[10:12:27] [PASSED] oob_was/22012727685
[10:12:27] [PASSED] oob_was/22016596838
[10:12:27] [PASSED] oob_was/18020744125
[10:12:27] [PASSED] oob_was/1409600907
[10:12:27] [PASSED] oob_was/22014953428
[10:12:27] [PASSED] oob_was/16017236439
[10:12:27] [PASSED] oob_was/14019821291
[10:12:27] [PASSED] oob_was/14015076503
[10:12:27] [PASSED] oob_was/22016122933
[10:12:27] [PASSED] oob_was/14018913170
[10:12:27] [PASSED] oob_was/14018094691
[10:12:27] [PASSED] oob_was/18024947630
[10:12:27] [PASSED] oob_was/16022287689
[10:12:27] [PASSED] oob_was/13011645652
[10:12:27] [PASSED] oob_was/14022293748
[10:12:27] [PASSED] oob_was/22019794406
[10:12:27] [PASSED] oob_was/22019338487
[10:12:27] [PASSED] oob_was/16023588340
[10:12:27] [PASSED] oob_was/14019789679
[10:12:27] [PASSED] oob_was/14022866841
[10:12:27] [PASSED] oob_was/16021333562
[10:12:27] [PASSED] oob_was/14016712196
[10:12:27] [PASSED] oob_was/14015568240
[10:12:27] [PASSED] oob_was/18013179988
[10:12:27] [PASSED] oob_was/1508761755
[10:12:27] [PASSED] oob_was/16023105232
[10:12:27] [PASSED] oob_was/16026508708
[10:12:27] [PASSED] oob_was/14020001231
[10:12:27] [PASSED] oob_was/16023683509
[10:12:27] [PASSED] oob_was/14025515070
[10:12:27] [PASSED] oob_was/15015404425_disable
[10:12:27] [PASSED] oob_was/16026007364
[10:12:27] [PASSED] oob_was/14020316580
[10:12:27] [PASSED] oob_was/14025883347
[10:12:27] [PASSED] oob_was/16029380221
[10:12:27] [PASSED] oob_was/22022079272
[10:12:27] [PASSED] oob_was/16029897822
[10:12:27] [PASSED] oob_was/14026539277
[10:12:27] [PASSED] oob_was/14027054324
[10:12:27] [PASSED] oob_was/14025941587
[10:12:27] [PASSED] oob_was/16030224309
[10:12:27] [PASSED] oob_was/14028709524
[10:12:27] ============== [PASSED] xe_rtp_table_oob_test ==============
[10:12:27] ================ xe_rtp_table_dev_oob_test  ================
[10:12:27] [PASSED] device_oob_was/22010954014
[10:12:27] [PASSED] device_oob_was/15015404425
[10:12:27] [PASSED] device_oob_was/22019338487_display
[10:12:27] [PASSED] device_oob_was/14022085890
[10:12:27] [PASSED] device_oob_was/14026633728
[10:12:27] [PASSED] device_oob_was/14026746987
[10:12:27] [PASSED] device_oob_was/14026779378
[10:12:27] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[10:12:27] ========== xe_rtp_table_missing_upper_bound_test  ==========
[10:12:27] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[10:12:27] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[10:12:27] [PASSED] register_whitelist/1806527549
[10:12:27] [PASSED] register_whitelist/allow_read_ctx_timestamp
[10:12:27] [PASSED] register_whitelist/allow_read_queue_timestamp
[10:12:27] [PASSED] register_whitelist/16014440446
[10:12:27] [PASSED] register_whitelist/16017236439
[10:12:27] [PASSED] register_whitelist/16020183090
[10:12:27] [PASSED] register_whitelist/14024997852
[10:12:27] [PASSED] register_whitelist/14024997852
[10:12:27] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[10:12:27] =============== [PASSED] xe_rtp_tables_test ================
[10:12:27] =================== xe_rtp (3 subtests) ====================
[10:12:27] =================== xe_rtp_rules_tests  ====================
[10:12:27] [PASSED] no
[10:12:27] [PASSED] yes
[10:12:27] [PASSED] no-and-no
[10:12:27] [PASSED] no-and-yes
[10:12:27] [PASSED] yes-and-no
[10:12:27] [PASSED] yes-and-yes
[10:12:27] [PASSED] no-or-no
[10:12:27] [PASSED] no-or-yes
[10:12:27] [PASSED] yes-or-no
[10:12:27] [PASSED] yes-or-yes
[10:12:27] [PASSED] no-yes-or-yes-no
[10:12:27] [PASSED] no-yes-or-yes-yes
[10:12:27] [PASSED] yes-yes-or-no-yes
[10:12:27] [PASSED] yes-yes-or-yes-yes
[10:12:27] [PASSED] no-no-or-yes-or-no
[10:12:27] [PASSED] or
[10:12:27] [PASSED] or-yes
[10:12:27] [PASSED] or-no
[10:12:27] [PASSED] yes-or
[10:12:27] [PASSED] no-or
[10:12:27] [PASSED] no-or-or-yes
[10:12:27] [PASSED] yes-or-or-no
[10:12:27] [PASSED] no-or-or-no
[10:12:27] [PASSED] missing-context-engine-class
[10:12:27] [PASSED] missing-context-engine-class-or-yes
[10:12:27] [PASSED] missing-context-engine-class-or-or-yes
[10:12:27] =============== [PASSED] xe_rtp_rules_tests ================
[10:12:27] =============== xe_rtp_process_to_sr_tests  ================
[10:12:27] [PASSED] coalesce-same-reg
[10:12:27] [PASSED] coalesce-same-reg-literal-and-func
[10:12:27] [PASSED] no-match-no-add
[10:12:27] [PASSED] two-regs-two-entries
[10:12:27] [PASSED] clr-one-set-other
[10:12:27] [PASSED] set-field
[10:12:27] [PASSED] conflict-duplicate
[10:12:27] [PASSED] conflict-not-disjoint
[10:12:27] [PASSED] conflict-not-disjoint-literal-and-func
[10:12:27] [PASSED] conflict-reg-type
[10:12:27] [PASSED] bad-mcr-reg-forced-to-regular
[10:12:27] [PASSED] bad-regular-reg-forced-to-mcr
[10:12:27] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[10:12:27] ================== xe_rtp_process_tests  ===================
[10:12:27] [PASSED] active1
[10:12:27] [PASSED] active2
[10:12:27] [PASSED] active-inactive
[10:12:27] [PASSED] inactive-active
[10:12:27] [PASSED] inactive-active-inactive
[10:12:27] [PASSED] inactive-inactive-inactive
[10:12:27] ============== [PASSED] xe_rtp_process_tests ===============
[10:12:27] ===================== [PASSED] xe_rtp ======================
[10:12:27] ==================== xe_wa (1 subtest) =====================
[10:12:27] ======================== xe_wa_gt  =========================
[10:12:27] [PASSED] TIGERLAKE B0
[10:12:27] [PASSED] DG1 A0
[10:12:27] [PASSED] DG1 B0
[10:12:27] [PASSED] ALDERLAKE_S A0
[10:12:27] [PASSED] ALDERLAKE_S B0
[10:12:27] [PASSED] ALDERLAKE_S C0
[10:12:27] [PASSED] ALDERLAKE_S D0
[10:12:27] [PASSED] ALDERLAKE_P A0
[10:12:27] [PASSED] ALDERLAKE_P B0
[10:12:27] [PASSED] ALDERLAKE_P C0
[10:12:27] [PASSED] ALDERLAKE_S RPLS D0
[10:12:27] [PASSED] ALDERLAKE_P RPLU E0
[10:12:27] [PASSED] DG2 G10 C0
[10:12:27] [PASSED] DG2 G11 B1
[10:12:27] [PASSED] DG2 G12 A1
[10:12:27] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:12:27] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:12:27] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[10:12:27] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[10:12:27] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[10:12:27] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[10:12:27] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[10:12:27] ==================== [PASSED] xe_wa_gt =====================
[10:12:27] ====================== [PASSED] xe_wa ======================
[10:12:27] ============================================================
[10:12:27] Testing complete. Ran 840 tests: passed: 811, skipped: 29
[10:12:27] Elapsed time: 41.435s total, 2.439s configuring, 38.229s building, 0.737s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[10:12:27] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:12:30] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:12:55] Starting KUnit Kernel (1/1)...
[10:12:55] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:12:55] ============ drm_test_pick_cmdline (2 subtests) ============
[10:12:55] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[10:12:55] =============== drm_test_pick_cmdline_named  ===============
[10:12:55] [PASSED] NTSC
[10:12:55] [PASSED] NTSC-J
[10:12:55] [PASSED] PAL
[10:12:55] [PASSED] PAL-M
[10:12:55] =========== [PASSED] drm_test_pick_cmdline_named ===========
[10:12:55] ============== [PASSED] drm_test_pick_cmdline ==============
[10:12:55] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[10:12:55] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[10:12:55] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[10:12:55] =========== drm_validate_clone_mode (2 subtests) ===========
[10:12:55] ============== drm_test_check_in_clone_mode  ===============
[10:12:55] [PASSED] in_clone_mode
[10:12:55] [PASSED] not_in_clone_mode
[10:12:55] ========== [PASSED] drm_test_check_in_clone_mode ===========
[10:12:55] =============== drm_test_check_valid_clones  ===============
[10:12:55] [PASSED] not_in_clone_mode
[10:12:55] [PASSED] valid_clone
[10:12:55] [PASSED] invalid_clone
[10:12:55] =========== [PASSED] drm_test_check_valid_clones ===========
[10:12:55] ============= [PASSED] drm_validate_clone_mode =============
[10:12:55] ============= drm_validate_modeset (1 subtest) =============
[10:12:55] [PASSED] drm_test_check_connector_changed_modeset
[10:12:55] ============== [PASSED] drm_validate_modeset ===============
[10:12:55] ====== drm_test_bridge_get_current_state (1 subtest) =======
[10:12:55] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[10:12:55] ======== [PASSED] drm_test_bridge_get_current_state ========
[10:12:55] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[10:12:55] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[10:12:55] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[10:12:55] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[10:12:55] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[10:12:55] ============== drm_bridge_alloc (2 subtests) ===============
[10:12:55] [PASSED] drm_test_drm_bridge_alloc_basic
[10:12:55] [PASSED] drm_test_drm_bridge_alloc_get_put
[10:12:55] ================ [PASSED] drm_bridge_alloc =================
[10:12:55] ============= drm_bridge_bus_fmt (5 subtests) ==============
[10:12:55] [PASSED] drm_test_bridge_rgb_yuv_rgb
[10:12:55] [PASSED] drm_test_bridge_must_convert_to_yuv444
[10:12:55] [PASSED] drm_test_bridge_hdmi_auto_rgb
[10:12:55] [PASSED] drm_test_bridge_auto_first
[10:12:55] [PASSED] drm_test_bridge_rgb_yuv_no_path
[10:12:55] =============== [PASSED] drm_bridge_bus_fmt ================
[10:12:55] ============= drm_cmdline_parser (40 subtests) =============
[10:12:55] [PASSED] drm_test_cmdline_force_d_only
[10:12:55] [PASSED] drm_test_cmdline_force_D_only_dvi
[10:12:55] [PASSED] drm_test_cmdline_force_D_only_hdmi
[10:12:55] [PASSED] drm_test_cmdline_force_D_only_not_digital
[10:12:55] [PASSED] drm_test_cmdline_force_e_only
[10:12:55] [PASSED] drm_test_cmdline_res
[10:12:55] [PASSED] drm_test_cmdline_res_vesa
[10:12:55] [PASSED] drm_test_cmdline_res_vesa_rblank
[10:12:55] [PASSED] drm_test_cmdline_res_rblank
[10:12:55] [PASSED] drm_test_cmdline_res_bpp
[10:12:55] [PASSED] drm_test_cmdline_res_refresh
[10:12:55] [PASSED] drm_test_cmdline_res_bpp_refresh
[10:12:55] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[10:12:55] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[10:12:55] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[10:12:55] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[10:12:55] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[10:12:55] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[10:12:55] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[10:12:55] [PASSED] drm_test_cmdline_res_margins_force_on
[10:12:55] [PASSED] drm_test_cmdline_res_vesa_margins
[10:12:55] [PASSED] drm_test_cmdline_name
[10:12:55] [PASSED] drm_test_cmdline_name_bpp
[10:12:55] [PASSED] drm_test_cmdline_name_option
[10:12:55] [PASSED] drm_test_cmdline_name_bpp_option
[10:12:55] [PASSED] drm_test_cmdline_rotate_0
[10:12:55] [PASSED] drm_test_cmdline_rotate_90
[10:12:55] [PASSED] drm_test_cmdline_rotate_180
[10:12:55] [PASSED] drm_test_cmdline_rotate_270
[10:12:55] [PASSED] drm_test_cmdline_hmirror
[10:12:55] [PASSED] drm_test_cmdline_vmirror
[10:12:55] [PASSED] drm_test_cmdline_margin_options
[10:12:55] [PASSED] drm_test_cmdline_multiple_options
[10:12:55] [PASSED] drm_test_cmdline_bpp_extra_and_option
[10:12:55] [PASSED] drm_test_cmdline_extra_and_option
[10:12:55] [PASSED] drm_test_cmdline_freestanding_options
[10:12:55] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[10:12:55] [PASSED] drm_test_cmdline_panel_orientation
[10:12:55] ================ drm_test_cmdline_invalid  =================
[10:12:55] [PASSED] margin_only
[10:12:55] [PASSED] interlace_only
[10:12:55] [PASSED] res_missing_x
[10:12:55] [PASSED] res_missing_y
[10:12:55] [PASSED] res_bad_y
[10:12:55] [PASSED] res_missing_y_bpp
[10:12:55] [PASSED] res_bad_bpp
[10:12:55] [PASSED] res_bad_refresh
[10:12:55] [PASSED] res_bpp_refresh_force_on_off
[10:12:55] [PASSED] res_invalid_mode
[10:12:55] [PASSED] res_bpp_wrong_place_mode
[10:12:55] [PASSED] name_bpp_refresh
[10:12:55] [PASSED] name_refresh
[10:12:55] [PASSED] name_refresh_wrong_mode
[10:12:55] [PASSED] name_refresh_invalid_mode
[10:12:55] [PASSED] rotate_multiple
[10:12:55] [PASSED] rotate_invalid_val
[10:12:55] [PASSED] rotate_truncated
[10:12:55] [PASSED] invalid_option
[10:12:55] [PASSED] invalid_tv_option
[10:12:55] [PASSED] truncated_tv_option
[10:12:55] ============ [PASSED] drm_test_cmdline_invalid =============
[10:12:55] =============== drm_test_cmdline_tv_options  ===============
[10:12:55] [PASSED] NTSC
[10:12:55] [PASSED] NTSC_443
[10:12:55] [PASSED] NTSC_J
[10:12:55] [PASSED] PAL
[10:12:55] [PASSED] PAL_M
[10:12:55] [PASSED] PAL_N
[10:12:55] [PASSED] SECAM
[10:12:55] [PASSED] MONO_525
[10:12:55] [PASSED] MONO_625
[10:12:55] =========== [PASSED] drm_test_cmdline_tv_options ===========
[10:12:55] =============== [PASSED] drm_cmdline_parser ================
[10:12:55] ========== drmm_connector_hdmi_init (20 subtests) ==========
[10:12:55] [PASSED] drm_test_connector_hdmi_init_valid
[10:12:55] [PASSED] drm_test_connector_hdmi_init_bpc_8
[10:12:55] [PASSED] drm_test_connector_hdmi_init_bpc_10
[10:12:55] [PASSED] drm_test_connector_hdmi_init_bpc_12
[10:12:55] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[10:12:55] [PASSED] drm_test_connector_hdmi_init_bpc_null
[10:12:55] [PASSED] drm_test_connector_hdmi_init_formats_empty
[10:12:55] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[10:12:55] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[10:12:55] [PASSED] supported_formats=0x9 yuv420_allowed=1
[10:12:55] [PASSED] supported_formats=0x9 yuv420_allowed=0
[10:12:55] [PASSED] supported_formats=0x5 yuv420_allowed=1
[10:12:55] [PASSED] supported_formats=0x5 yuv420_allowed=0
[10:12:55] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[10:12:55] [PASSED] drm_test_connector_hdmi_init_null_ddc
[10:12:55] [PASSED] drm_test_connector_hdmi_init_null_product
[10:12:55] [PASSED] drm_test_connector_hdmi_init_null_vendor
[10:12:55] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[10:12:55] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[10:12:55] [PASSED] drm_test_connector_hdmi_init_product_valid
[10:12:55] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[10:12:55] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[10:12:55] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[10:12:55] ========= drm_test_connector_hdmi_init_type_valid  =========
[10:12:55] [PASSED] HDMI-A
[10:12:55] [PASSED] HDMI-B
[10:12:55] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[10:12:55] ======== drm_test_connector_hdmi_init_type_invalid  ========
[10:12:55] [PASSED] Unknown
[10:12:55] [PASSED] VGA
[10:12:55] [PASSED] DVI-I
[10:12:55] [PASSED] DVI-D
[10:12:55] [PASSED] DVI-A
[10:12:55] [PASSED] Composite
[10:12:55] [PASSED] SVIDEO
[10:12:55] [PASSED] LVDS
[10:12:55] [PASSED] Component
[10:12:55] [PASSED] DIN
[10:12:55] [PASSED] DP
[10:12:55] [PASSED] TV
[10:12:55] [PASSED] eDP
[10:12:55] [PASSED] Virtual
[10:12:55] [PASSED] DSI
[10:12:55] [PASSED] DPI
[10:12:55] [PASSED] Writeback
[10:12:55] [PASSED] SPI
[10:12:55] [PASSED] USB
[10:12:55] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[10:12:55] ============ [PASSED] drmm_connector_hdmi_init =============
[10:12:55] ============= drmm_connector_init (3 subtests) =============
[10:12:55] [PASSED] drm_test_drmm_connector_init
[10:12:55] [PASSED] drm_test_drmm_connector_init_null_ddc
[10:12:55] ========= drm_test_drmm_connector_init_type_valid  =========
[10:12:55] [PASSED] Unknown
[10:12:55] [PASSED] VGA
[10:12:55] [PASSED] DVI-I
[10:12:55] [PASSED] DVI-D
[10:12:55] [PASSED] DVI-A
[10:12:55] [PASSED] Composite
[10:12:55] [PASSED] SVIDEO
[10:12:55] [PASSED] LVDS
[10:12:55] [PASSED] Component
[10:12:55] [PASSED] DIN
[10:12:55] [PASSED] DP
[10:12:55] [PASSED] HDMI-A
[10:12:55] [PASSED] HDMI-B
[10:12:55] [PASSED] TV
[10:12:55] [PASSED] eDP
[10:12:55] [PASSED] Virtual
[10:12:55] [PASSED] DSI
[10:12:55] [PASSED] DPI
[10:12:55] [PASSED] Writeback
[10:12:55] [PASSED] SPI
[10:12:55] [PASSED] USB
[10:12:55] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[10:12:55] =============== [PASSED] drmm_connector_init ===============
[10:12:55] ========= drm_connector_dynamic_init (6 subtests) ==========
[10:12:55] [PASSED] drm_test_drm_connector_dynamic_init
[10:12:55] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[10:12:55] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[10:12:55] [PASSED] drm_test_drm_connector_dynamic_init_properties
[10:12:55] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[10:12:55] [PASSED] Unknown
[10:12:55] [PASSED] VGA
[10:12:55] [PASSED] DVI-I
[10:12:55] [PASSED] DVI-D
[10:12:55] [PASSED] DVI-A
[10:12:55] [PASSED] Composite
[10:12:55] [PASSED] SVIDEO
[10:12:55] [PASSED] LVDS
[10:12:55] [PASSED] Component
[10:12:55] [PASSED] DIN
[10:12:55] [PASSED] DP
[10:12:55] [PASSED] HDMI-A
[10:12:55] [PASSED] HDMI-B
[10:12:55] [PASSED] TV
[10:12:55] [PASSED] eDP
[10:12:55] [PASSED] Virtual
[10:12:55] [PASSED] DSI
[10:12:55] [PASSED] DPI
[10:12:55] [PASSED] Writeback
[10:12:55] [PASSED] SPI
[10:12:55] [PASSED] USB
[10:12:55] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[10:12:55] ======== drm_test_drm_connector_dynamic_init_name  =========
[10:12:55] [PASSED] Unknown
[10:12:55] [PASSED] VGA
[10:12:55] [PASSED] DVI-I
[10:12:55] [PASSED] DVI-D
[10:12:55] [PASSED] DVI-A
[10:12:55] [PASSED] Composite
[10:12:55] [PASSED] SVIDEO
[10:12:55] [PASSED] LVDS
[10:12:55] [PASSED] Component
[10:12:55] [PASSED] DIN
[10:12:55] [PASSED] DP
[10:12:55] [PASSED] HDMI-A
[10:12:55] [PASSED] HDMI-B
[10:12:55] [PASSED] TV
[10:12:55] [PASSED] eDP
[10:12:55] [PASSED] Virtual
[10:12:55] [PASSED] DSI
[10:12:55] [PASSED] DPI
[10:12:55] [PASSED] Writeback
[10:12:55] [PASSED] SPI
[10:12:55] [PASSED] USB
[10:12:55] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[10:12:55] =========== [PASSED] drm_connector_dynamic_init ============
[10:12:55] ==== drm_connector_dynamic_register_early (4 subtests) =====
[10:12:55] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[10:12:55] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[10:12:55] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[10:12:55] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[10:12:55] ====== [PASSED] drm_connector_dynamic_register_early =======
[10:12:55] ======= drm_connector_dynamic_register (7 subtests) ========
[10:12:55] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[10:12:55] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[10:12:55] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[10:12:55] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[10:12:55] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[10:12:55] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[10:12:55] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[10:12:55] ========= [PASSED] drm_connector_dynamic_register ==========
[10:12:55] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[10:12:55] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[10:12:55] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[10:12:55] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[10:12:55] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[10:12:55] ========== drm_test_get_tv_mode_from_name_valid  ===========
[10:12:55] [PASSED] NTSC
[10:12:55] [PASSED] NTSC-443
[10:12:55] [PASSED] NTSC-J
[10:12:55] [PASSED] PAL
[10:12:55] [PASSED] PAL-M
[10:12:55] [PASSED] PAL-N
[10:12:55] [PASSED] SECAM
[10:12:55] [PASSED] Mono
[10:12:55] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[10:12:55] [PASSED] drm_test_get_tv_mode_from_name_truncated
[10:12:55] ============ [PASSED] drm_get_tv_mode_from_name ============
[10:12:55] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[10:12:55] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[10:12:55] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[10:12:55] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[10:12:55] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[10:12:55] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[10:12:55] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[10:12:55] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[10:12:55] [PASSED] VIC 96
[10:12:55] [PASSED] VIC 97
[10:12:55] [PASSED] VIC 101
[10:12:55] [PASSED] VIC 102
[10:12:55] [PASSED] VIC 106
[10:12:55] [PASSED] VIC 107
[10:12:55] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[10:12:55] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[10:12:55] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[10:12:55] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[10:12:55] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[10:12:55] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[10:12:55] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[10:12:55] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[10:12:55] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[10:12:55] [PASSED] Automatic
[10:12:55] [PASSED] Full
[10:12:55] [PASSED] Limited 16:235
[10:12:55] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[10:12:55] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[10:12:55] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[10:12:55] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[10:12:55] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[10:12:55] [PASSED] RGB
[10:12:55] [PASSED] YUV 4:2:0
[10:12:55] [PASSED] YUV 4:2:2
[10:12:55] [PASSED] YUV 4:4:4
[10:12:55] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[10:12:55] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[10:12:55] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[10:12:55] ============= drm_damage_helper (21 subtests) ==============
[10:12:55] [PASSED] drm_test_damage_iter_no_damage
[10:12:55] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[10:12:55] [PASSED] drm_test_damage_iter_no_damage_src_moved
[10:12:55] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[10:12:55] [PASSED] drm_test_damage_iter_no_damage_not_visible
[10:12:55] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[10:12:55] [PASSED] drm_test_damage_iter_no_damage_no_fb
[10:12:55] [PASSED] drm_test_damage_iter_simple_damage
[10:12:55] [PASSED] drm_test_damage_iter_single_damage
[10:12:55] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[10:12:55] [PASSED] drm_test_damage_iter_single_damage_outside_src
[10:12:55] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[10:12:55] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[10:12:55] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[10:12:55] [PASSED] drm_test_damage_iter_single_damage_src_moved
[10:12:55] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[10:12:55] [PASSED] drm_test_damage_iter_damage
[10:12:55] [PASSED] drm_test_damage_iter_damage_one_intersect
[10:12:55] [PASSED] drm_test_damage_iter_damage_one_outside
[10:12:55] [PASSED] drm_test_damage_iter_damage_src_moved
[10:12:55] [PASSED] drm_test_damage_iter_damage_not_visible
[10:12:55] ================ [PASSED] drm_damage_helper ================
[10:12:55] ============== drm_dp_mst_helper (3 subtests) ==============
[10:12:55] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[10:12:55] [PASSED] Clock 154000 BPP 30 DSC disabled
[10:12:55] [PASSED] Clock 234000 BPP 30 DSC disabled
[10:12:55] [PASSED] Clock 297000 BPP 24 DSC disabled
[10:12:55] [PASSED] Clock 332880 BPP 24 DSC enabled
[10:12:55] [PASSED] Clock 324540 BPP 24 DSC enabled
[10:12:55] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[10:12:55] ============== drm_test_dp_mst_calc_pbn_div  ===============
[10:12:55] [PASSED] Link rate 2000000 lane count 4
[10:12:55] [PASSED] Link rate 2000000 lane count 2
[10:12:55] [PASSED] Link rate 2000000 lane count 1
[10:12:55] [PASSED] Link rate 1350000 lane count 4
[10:12:55] [PASSED] Link rate 1350000 lane count 2
[10:12:55] [PASSED] Link rate 1350000 lane count 1
[10:12:55] [PASSED] Link rate 1000000 lane count 4
[10:12:55] [PASSED] Link rate 1000000 lane count 2
[10:12:55] [PASSED] Link rate 1000000 lane count 1
[10:12:55] [PASSED] Link rate 810000 lane count 4
[10:12:55] [PASSED] Link rate 810000 lane count 2
[10:12:55] [PASSED] Link rate 810000 lane count 1
[10:12:55] [PASSED] Link rate 540000 lane count 4
[10:12:55] [PASSED] Link rate 540000 lane count 2
[10:12:55] [PASSED] Link rate 540000 lane count 1
[10:12:55] [PASSED] Link rate 270000 lane count 4
[10:12:55] [PASSED] Link rate 270000 lane count 2
[10:12:55] [PASSED] Link rate 270000 lane count 1
[10:12:55] [PASSED] Link rate 162000 lane count 4
[10:12:55] [PASSED] Link rate 162000 lane count 2
[10:12:55] [PASSED] Link rate 162000 lane count 1
[10:12:55] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[10:12:55] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[10:12:55] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[10:12:55] [PASSED] DP_POWER_UP_PHY with port number
[10:12:55] [PASSED] DP_POWER_DOWN_PHY with port number
[10:12:55] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[10:12:55] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[10:12:55] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[10:12:55] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[10:12:55] [PASSED] DP_QUERY_PAYLOAD with port number
[10:12:55] [PASSED] DP_QUERY_PAYLOAD with VCPI
[10:12:55] [PASSED] DP_REMOTE_DPCD_READ with port number
[10:12:55] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[10:12:55] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[10:12:55] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[10:12:55] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[10:12:55] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[10:12:55] [PASSED] DP_REMOTE_I2C_READ with port number
[10:12:55] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[10:12:55] [PASSED] DP_REMOTE_I2C_READ with transactions array
[10:12:55] [PASSED] DP_REMOTE_I2C_WRITE with port number
[10:12:55] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[10:12:55] [PASSED] DP_REMOTE_I2C_WRITE with data array
[10:12:55] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[10:12:55] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[10:12:55] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[10:12:55] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[10:12:55] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[10:12:55] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[10:12:55] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[10:12:55] ================ [PASSED] drm_dp_mst_helper ================
[10:12:55] ================== drm_exec (7 subtests) ===================
[10:12:55] [PASSED] sanitycheck
[10:12:55] [PASSED] test_lock
[10:12:55] [PASSED] test_lock_unlock
[10:12:55] [PASSED] test_duplicates
[10:12:55] [PASSED] test_prepare
[10:12:55] [PASSED] test_prepare_array
[10:12:55] [PASSED] test_multiple_loops
[10:12:55] ==================== [PASSED] drm_exec =====================
[10:12:55] =========== drm_format_helper_test (17 subtests) ===========
[10:12:55] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[10:12:55] [PASSED] single_pixel_source_buffer
[10:12:55] [PASSED] single_pixel_clip_rectangle
[10:12:55] [PASSED] well_known_colors
[10:12:55] [PASSED] destination_pitch
[10:12:55] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[10:12:55] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[10:12:55] [PASSED] single_pixel_source_buffer
[10:12:55] [PASSED] single_pixel_clip_rectangle
[10:12:55] [PASSED] well_known_colors
[10:12:55] [PASSED] destination_pitch
[10:12:55] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[10:12:55] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[10:12:55] [PASSED] single_pixel_source_buffer
[10:12:55] [PASSED] single_pixel_clip_rectangle
[10:12:55] [PASSED] well_known_colors
[10:12:55] [PASSED] destination_pitch
[10:12:55] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[10:12:55] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[10:12:55] [PASSED] single_pixel_source_buffer
[10:12:55] [PASSED] single_pixel_clip_rectangle
[10:12:55] [PASSED] well_known_colors
[10:12:55] [PASSED] destination_pitch
[10:12:55] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[10:12:55] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[10:12:55] [PASSED] single_pixel_source_buffer
[10:12:55] [PASSED] single_pixel_clip_rectangle
[10:12:55] [PASSED] well_known_colors
[10:12:55] [PASSED] destination_pitch
[10:12:55] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[10:12:55] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[10:12:55] [PASSED] single_pixel_source_buffer
[10:12:55] [PASSED] single_pixel_clip_rectangle
[10:12:55] [PASSED] well_known_colors
[10:12:55] [PASSED] destination_pitch
[10:12:55] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[10:12:55] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[10:12:55] [PASSED] single_pixel_source_buffer
[10:12:55] [PASSED] single_pixel_clip_rectangle
[10:12:55] [PASSED] well_known_colors
[10:12:55] [PASSED] destination_pitch
[10:12:55] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[10:12:55] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[10:12:55] [PASSED] single_pixel_source_buffer
[10:12:55] [PASSED] single_pixel_clip_rectangle
[10:12:55] [PASSED] well_known_colors
[10:12:55] [PASSED] destination_pitch
[10:12:55] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[10:12:55] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[10:12:55] [PASSED] single_pixel_source_buffer
[10:12:55] [PASSED] single_pixel_clip_rectangle
[10:12:55] [PASSED] well_known_colors
[10:12:55] [PASSED] destination_pitch
[10:12:55] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[10:12:55] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[10:12:55] [PASSED] single_pixel_source_buffer
[10:12:55] [PASSED] single_pixel_clip_rectangle
[10:12:55] [PASSED] well_known_colors
[10:12:55] [PASSED] destination_pitch
[10:12:55] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[10:12:55] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[10:12:55] [PASSED] single_pixel_source_buffer
[10:12:55] [PASSED] single_pixel_clip_rectangle
[10:12:55] [PASSED] well_known_colors
[10:12:55] [PASSED] destination_pitch
[10:12:55] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[10:12:55] ============== drm_test_fb_xrgb8888_to_mono  ===============
[10:12:55] [PASSED] single_pixel_source_buffer
[10:12:55] [PASSED] single_pixel_clip_rectangle
[10:12:55] [PASSED] well_known_colors
[10:12:55] [PASSED] destination_pitch
[10:12:55] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[10:12:55] ==================== drm_test_fb_swab  =====================
[10:12:55] [PASSED] single_pixel_source_buffer
[10:12:55] [PASSED] single_pixel_clip_rectangle
[10:12:55] [PASSED] well_known_colors
[10:12:55] [PASSED] destination_pitch
[10:12:55] ================ [PASSED] drm_test_fb_swab =================
[10:12:55] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[10:12:55] [PASSED] single_pixel_source_buffer
[10:12:55] [PASSED] single_pixel_clip_rectangle
[10:12:55] [PASSED] well_known_colors
[10:12:55] [PASSED] destination_pitch
[10:12:55] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[10:12:55] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[10:12:55] [PASSED] single_pixel_source_buffer
[10:12:55] [PASSED] single_pixel_clip_rectangle
[10:12:55] [PASSED] well_known_colors
[10:12:55] [PASSED] destination_pitch
[10:12:55] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[10:12:55] ================= drm_test_fb_clip_offset  =================
[10:12:55] [PASSED] pass through
[10:12:55] [PASSED] horizontal offset
[10:12:55] [PASSED] vertical offset
[10:12:55] [PASSED] horizontal and vertical offset
[10:12:55] [PASSED] horizontal offset (custom pitch)
[10:12:55] [PASSED] vertical offset (custom pitch)
[10:12:55] [PASSED] horizontal and vertical offset (custom pitch)
[10:12:55] ============= [PASSED] drm_test_fb_clip_offset =============
[10:12:55] =================== drm_test_fb_memcpy  ====================
[10:12:55] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[10:12:55] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[10:12:55] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[10:12:55] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[10:12:55] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[10:12:55] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[10:12:55] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[10:12:55] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[10:12:55] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[10:12:55] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[10:12:55] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[10:12:55] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[10:12:55] =============== [PASSED] drm_test_fb_memcpy ================
[10:12:55] ============= [PASSED] drm_format_helper_test ==============
[10:12:55] ================= drm_format (18 subtests) =================
[10:12:55] [PASSED] drm_test_format_block_width_invalid
[10:12:55] [PASSED] drm_test_format_block_width_one_plane
[10:12:55] [PASSED] drm_test_format_block_width_two_plane
[10:12:55] [PASSED] drm_test_format_block_width_three_plane
[10:12:55] [PASSED] drm_test_format_block_width_tiled
[10:12:55] [PASSED] drm_test_format_block_height_invalid
[10:12:55] [PASSED] drm_test_format_block_height_one_plane
[10:12:55] [PASSED] drm_test_format_block_height_two_plane
[10:12:55] [PASSED] drm_test_format_block_height_three_plane
[10:12:55] [PASSED] drm_test_format_block_height_tiled
[10:12:55] [PASSED] drm_test_format_min_pitch_invalid
[10:12:55] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[10:12:55] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[10:12:55] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[10:12:55] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[10:12:55] [PASSED] drm_test_format_min_pitch_two_plane
[10:12:55] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[10:12:55] [PASSED] drm_test_format_min_pitch_tiled
[10:12:55] =================== [PASSED] drm_format ====================
[10:12:55] ============== drm_framebuffer (10 subtests) ===============
[10:12:55] ========== drm_test_framebuffer_check_src_coords  ==========
[10:12:55] [PASSED] Success: source fits into fb
[10:12:55] [PASSED] Fail: overflowing fb with x-axis coordinate
[10:12:55] [PASSED] Fail: overflowing fb with y-axis coordinate
[10:12:55] [PASSED] Fail: overflowing fb with source width
[10:12:55] [PASSED] Fail: overflowing fb with source height
[10:12:55] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[10:12:55] [PASSED] drm_test_framebuffer_cleanup
[10:12:55] =============== drm_test_framebuffer_create  ===============
[10:12:55] [PASSED] ABGR8888 normal sizes
[10:12:55] [PASSED] ABGR8888 max sizes
[10:12:55] [PASSED] ABGR8888 pitch greater than min required
[10:12:55] [PASSED] ABGR8888 pitch less than min required
[10:12:55] [PASSED] ABGR8888 Invalid width
[10:12:55] [PASSED] ABGR8888 Invalid buffer handle
[10:12:55] [PASSED] No pixel format
[10:12:55] [PASSED] ABGR8888 Width 0
[10:12:55] [PASSED] ABGR8888 Height 0
[10:12:55] [PASSED] ABGR8888 Out of bound height * pitch combination
[10:12:55] [PASSED] ABGR8888 Large buffer offset
[10:12:55] [PASSED] ABGR8888 Buffer offset for inexistent plane
[10:12:55] [PASSED] ABGR8888 Invalid flag
[10:12:55] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[10:12:55] [PASSED] ABGR8888 Valid buffer modifier
[10:12:55] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[10:12:55] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[10:12:55] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[10:12:55] [PASSED] NV12 Normal sizes
[10:12:55] [PASSED] NV12 Max sizes
[10:12:55] [PASSED] NV12 Invalid pitch
[10:12:55] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[10:12:55] [PASSED] NV12 different  modifier per-plane
[10:12:55] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[10:12:55] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[10:12:55] [PASSED] NV12 Modifier for inexistent plane
[10:12:55] [PASSED] NV12 Handle for inexistent plane
[10:12:55] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[10:12:55] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[10:12:55] [PASSED] YVU420 Normal sizes
[10:12:55] [PASSED] YVU420 Max sizes
[10:12:55] [PASSED] YVU420 Invalid pitch
[10:12:55] [PASSED] YVU420 Different pitches
[10:12:55] [PASSED] YVU420 Different buffer offsets/pitches
[10:12:55] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[10:12:55] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[10:12:55] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[10:12:55] [PASSED] YVU420 Valid modifier
[10:12:55] [PASSED] YVU420 Different modifiers per plane
[10:12:55] [PASSED] YVU420 Modifier for inexistent plane
[10:12:55] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[10:12:55] [PASSED] X0L2 Normal sizes
[10:12:55] [PASSED] X0L2 Max sizes
[10:12:55] [PASSED] X0L2 Invalid pitch
[10:12:55] [PASSED] X0L2 Pitch greater than minimum required
[10:12:55] [PASSED] X0L2 Handle for inexistent plane
[10:12:55] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[10:12:55] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[10:12:55] [PASSED] X0L2 Valid modifier
[10:12:55] [PASSED] X0L2 Modifier for inexistent plane
[10:12:55] =========== [PASSED] drm_test_framebuffer_create ===========
[10:12:55] [PASSED] drm_test_framebuffer_free
[10:12:55] [PASSED] drm_test_framebuffer_init
[10:12:55] [PASSED] drm_test_framebuffer_init_bad_format
[10:12:55] [PASSED] drm_test_framebuffer_init_dev_mismatch
[10:12:55] [PASSED] drm_test_framebuffer_lookup
[10:12:55] [PASSED] drm_test_framebuffer_lookup_inexistent
[10:12:55] [PASSED] drm_test_framebuffer_modifiers_not_supported
[10:12:55] ================= [PASSED] drm_framebuffer =================
[10:12:55] ================ drm_gem_shmem (8 subtests) ================
[10:12:55] [PASSED] drm_gem_shmem_test_obj_create
[10:12:55] [PASSED] drm_gem_shmem_test_obj_create_private
[10:12:55] [PASSED] drm_gem_shmem_test_pin_pages
[10:12:55] [PASSED] drm_gem_shmem_test_vmap
[10:12:55] [PASSED] drm_gem_shmem_test_get_sg_table
[10:12:55] [PASSED] drm_gem_shmem_test_get_pages_sgt
[10:12:55] [PASSED] drm_gem_shmem_test_madvise
[10:12:55] [PASSED] drm_gem_shmem_test_purge
[10:12:55] ================== [PASSED] drm_gem_shmem ==================
[10:12:55] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[10:12:55] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[10:12:55] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[10:12:55] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[10:12:55] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[10:12:55] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[10:12:55] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[10:12:55] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[10:12:55] [PASSED] Automatic
[10:12:55] [PASSED] Full
[10:12:55] [PASSED] Limited 16:235
[10:12:55] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[10:12:55] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[10:12:55] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[10:12:55] [PASSED] drm_test_check_disable_connector
[10:12:55] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[10:12:55] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[10:12:55] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[10:12:55] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[10:12:55] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[10:12:55] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[10:12:55] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[10:12:55] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[10:12:55] [PASSED] drm_test_check_output_bpc_dvi
[10:12:55] [PASSED] drm_test_check_output_bpc_format_vic_1
[10:12:55] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[10:12:55] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[10:12:55] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[10:12:55] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[10:12:55] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[10:12:55] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[10:12:55] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[10:12:55] ============ drm_test_check_hdmi_color_format  =============
[10:12:55] [PASSED] AUTO -> RGB
[10:12:55] [PASSED] YCBCR422 -> YUV422
[10:12:55] [PASSED] YCBCR420 -> YUV420
[10:12:55] [PASSED] YCBCR444 -> YUV444
[10:12:55] [PASSED] RGB -> RGB
[10:12:55] ======== [PASSED] drm_test_check_hdmi_color_format =========
[10:12:55] ======== drm_test_check_hdmi_color_format_420_only  ========
[10:12:55] [PASSED] RGB should fail
[10:12:55] [PASSED] YUV444 should fail
[10:12:55] [PASSED] YUV422 should fail
[10:12:55] [PASSED] YUV420 should work
[10:12:55] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[10:12:55] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[10:12:55] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[10:12:55] [PASSED] drm_test_check_broadcast_rgb_value
[10:12:55] [PASSED] drm_test_check_bpc_8_value
[10:12:55] [PASSED] drm_test_check_bpc_10_value
[10:12:55] [PASSED] drm_test_check_bpc_12_value
[10:12:55] [PASSED] drm_test_check_format_value
[10:12:55] [PASSED] drm_test_check_tmds_char_value
[10:12:55] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[10:12:55] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[10:12:55] [PASSED] drm_test_check_mode_valid
[10:12:55] [PASSED] drm_test_check_mode_valid_reject
[10:12:55] [PASSED] drm_test_check_mode_valid_reject_rate
[10:12:55] [PASSED] drm_test_check_mode_valid_reject_max_clock
[10:12:55] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[10:12:55] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[10:12:55] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[10:12:55] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[10:12:55] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[10:12:55] [PASSED] drm_test_check_infoframes
[10:12:55] [PASSED] drm_test_check_reject_avi_infoframe
[10:12:55] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[10:12:55] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[10:12:55] [PASSED] drm_test_check_reject_audio_infoframe
[10:12:55] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[10:12:55] ================= drm_managed (2 subtests) =================
[10:12:55] [PASSED] drm_test_managed_release_action
[10:12:55] [PASSED] drm_test_managed_run_action
[10:12:55] =================== [PASSED] drm_managed ===================
[10:12:55] =================== drm_mm (6 subtests) ====================
[10:12:55] [PASSED] drm_test_mm_init
[10:12:55] [PASSED] drm_test_mm_debug
[10:12:55] [PASSED] drm_test_mm_align32
[10:12:55] [PASSED] drm_test_mm_align64
[10:12:55] [PASSED] drm_test_mm_lowest
[10:12:55] [PASSED] drm_test_mm_highest
[10:12:55] ===================== [PASSED] drm_mm ======================
[10:12:55] ============= drm_modes_analog_tv (5 subtests) =============
[10:12:55] [PASSED] drm_test_modes_analog_tv_mono_576i
[10:12:55] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[10:12:55] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[10:12:55] [PASSED] drm_test_modes_analog_tv_pal_576i
[10:12:55] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[10:12:55] =============== [PASSED] drm_modes_analog_tv ===============
[10:12:55] ============== drm_panic_helper (3 subtests) ===============
[10:12:55] ============= drm_test_panic_screen_user_map  ==============
[10:12:55] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[10:12:55] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[10:12:55] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[10:12:55] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[10:12:55] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[10:12:55] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[10:12:55] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[10:12:55] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[10:12:55] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[10:12:55] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[10:12:55] ========= [PASSED] drm_test_panic_screen_user_map ==========
[10:12:55] ============= drm_test_panic_screen_user_page  =============
[10:12:55] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[10:12:55] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[10:12:55] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[10:12:55] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[10:12:55] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[10:12:55] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[10:12:55] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[10:12:55] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[10:12:55] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[10:12:55] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[10:12:55] ========= [PASSED] drm_test_panic_screen_user_page =========
[10:12:55] ========== drm_test_panic_screen_user_set_pixel  ===========
[10:12:55] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[10:12:55] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[10:12:55] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[10:12:55] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[10:12:55] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[10:12:55] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[10:12:55] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[10:12:55] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[10:12:55] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[10:12:55] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[10:12:55] ====== [PASSED] drm_test_panic_screen_user_set_pixel =======
[10:12:55] ================ [PASSED] drm_panic_helper =================
[10:12:55] ============== drm_plane_helper (2 subtests) ===============
[10:12:55] =============== drm_test_check_plane_state  ================
[10:12:55] [PASSED] clipping_simple
[10:12:55] [PASSED] clipping_rotate_reflect
[10:12:55] [PASSED] positioning_simple
[10:12:55] [PASSED] upscaling
[10:12:55] [PASSED] downscaling
[10:12:55] [PASSED] rounding1
[10:12:55] [PASSED] rounding2
[10:12:55] [PASSED] rounding3
[10:12:55] [PASSED] rounding4
[10:12:55] =========== [PASSED] drm_test_check_plane_state ============
[10:12:55] =========== drm_test_check_invalid_plane_state  ============
[10:12:55] [PASSED] positioning_invalid
[10:12:55] [PASSED] upscaling_invalid
[10:12:55] [PASSED] downscaling_invalid
[10:12:55] ======= [PASSED] drm_test_check_invalid_plane_state ========
[10:12:55] ================ [PASSED] drm_plane_helper =================
[10:12:55] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[10:12:55] ====== drm_test_connector_helper_tv_get_modes_check  =======
[10:12:55] [PASSED] None
[10:12:55] [PASSED] PAL
[10:12:55] [PASSED] NTSC
[10:12:55] [PASSED] Both, NTSC Default
[10:12:55] [PASSED] Both, PAL Default
[10:12:55] [PASSED] Both, NTSC Default, with PAL on command-line
[10:12:55] [PASSED] Both, PAL Default, with NTSC on command-line
[10:12:55] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[10:12:55] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[10:12:55] ================== drm_rect (9 subtests) ===================
[10:12:55] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[10:12:55] [PASSED] drm_test_rect_clip_scaled_not_clipped
[10:12:55] [PASSED] drm_test_rect_clip_scaled_clipped
[10:12:55] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[10:12:55] ================= drm_test_rect_intersect  =================
[10:12:55] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[10:12:55] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[10:12:55] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[10:12:55] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[10:12:55] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[10:12:55] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[10:12:55] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[10:12:55] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[10:12:55] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[10:12:55] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[10:12:55] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[10:12:55] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[10:12:55] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[10:12:55] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[10:12:55] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[10:12:55] ============= [PASSED] drm_test_rect_intersect =============
[10:12:55] ================ drm_test_rect_calc_hscale  ================
[10:12:55] [PASSED] normal use
[10:12:55] [PASSED] out of max range
[10:12:55] [PASSED] out of min range
[10:12:55] [PASSED] zero dst
[10:12:55] [PASSED] negative src
[10:12:55] [PASSED] negative dst
[10:12:55] ============ [PASSED] drm_test_rect_calc_hscale ============
[10:12:55] ================ drm_test_rect_calc_vscale  ================
[10:12:55] [PASSED] normal use
[10:12:55] [PASSED] out of max range
[10:12:55] [PASSED] out of min range
[10:12:55] [PASSED] zero dst
[10:12:55] [PASSED] negative src
[10:12:55] [PASSED] negative dst
[10:12:55] ============ [PASSED] drm_test_rect_calc_vscale ============
[10:12:55] ================== drm_test_rect_rotate  ===================
[10:12:55] [PASSED] reflect-x
[10:12:55] [PASSED] reflect-y
[10:12:55] [PASSED] rotate-0
[10:12:55] [PASSED] rotate-90
[10:12:55] [PASSED] rotate-180
[10:12:55] [PASSED] rotate-270
[10:12:55] ============== [PASSED] drm_test_rect_rotate ===============
[10:12:55] ================ drm_test_rect_rotate_inv  =================
[10:12:55] [PASSED] reflect-x
[10:12:55] [PASSED] reflect-y
[10:12:55] [PASSED] rotate-0
[10:12:55] [PASSED] rotate-90
[10:12:55] [PASSED] rotate-180
[10:12:55] [PASSED] rotate-270
[10:12:55] ============ [PASSED] drm_test_rect_rotate_inv =============
[10:12:55] ==================== [PASSED] drm_rect =====================
[10:12:55] ============ drm_sysfb_modeset_test (1 subtest) ============
[10:12:55] ============ drm_test_sysfb_build_fourcc_list  =============
[10:12:55] [PASSED] no native formats
[10:12:55] [PASSED] XRGB8888 as native format
[10:12:55] [PASSED] remove duplicates
[10:12:55] [PASSED] convert alpha formats
[10:12:55] [PASSED] random formats
[10:12:55] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[10:12:55] ============= [PASSED] drm_sysfb_modeset_test ==============
[10:12:55] ================== drm_fixp (2 subtests) ===================
[10:12:55] [PASSED] drm_test_int2fixp
[10:12:55] [PASSED] drm_test_sm2fixp
[10:12:55] ==================== [PASSED] drm_fixp =====================
[10:12:55] ============================================================
[10:12:55] Testing complete. Ran 667 tests: passed: 667
[10:12:55] Elapsed time: 27.893s total, 2.481s configuring, 24.997s building, 0.408s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[10:12:55] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:12:58] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:13:08] Starting KUnit Kernel (1/1)...
[10:13:08] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:13:08] ================= ttm_device (5 subtests) ==================
[10:13:08] [PASSED] ttm_device_init_basic
[10:13:08] [PASSED] ttm_device_init_multiple
[10:13:08] [PASSED] ttm_device_fini_basic
[10:13:08] [PASSED] ttm_device_init_no_vma_man
[10:13:08] ================== ttm_device_init_pools  ==================
[10:13:08] [PASSED] No DMA allocations, no DMA32 required
[10:13:08] [PASSED] DMA allocations, DMA32 required
[10:13:08] [PASSED] No DMA allocations, DMA32 required
[10:13:08] [PASSED] DMA allocations, no DMA32 required
[10:13:08] ============== [PASSED] ttm_device_init_pools ==============
[10:13:08] =================== [PASSED] ttm_device ====================
[10:13:08] ================== ttm_pool (8 subtests) ===================
[10:13:08] ================== ttm_pool_alloc_basic  ===================
[10:13:08] [PASSED] One page
[10:13:08] [PASSED] More than one page
[10:13:08] [PASSED] Above the allocation limit
[10:13:08] [PASSED] One page, with coherent DMA mappings enabled
[10:13:08] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:13:08] ============== [PASSED] ttm_pool_alloc_basic ===============
[10:13:08] ============== ttm_pool_alloc_basic_dma_addr  ==============
[10:13:08] [PASSED] One page
[10:13:08] [PASSED] More than one page
[10:13:08] [PASSED] Above the allocation limit
[10:13:08] [PASSED] One page, with coherent DMA mappings enabled
[10:13:08] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:13:08] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[10:13:08] [PASSED] ttm_pool_alloc_order_caching_match
[10:13:08] [PASSED] ttm_pool_alloc_caching_mismatch
[10:13:08] [PASSED] ttm_pool_alloc_order_mismatch
[10:13:08] [PASSED] ttm_pool_free_dma_alloc
[10:13:08] [PASSED] ttm_pool_free_no_dma_alloc
[10:13:08] [PASSED] ttm_pool_fini_basic
[10:13:08] ==================== [PASSED] ttm_pool =====================
[10:13:08] ================ ttm_resource (8 subtests) =================
[10:13:08] ================= ttm_resource_init_basic  =================
[10:13:08] [PASSED] Init resource in TTM_PL_SYSTEM
[10:13:08] [PASSED] Init resource in TTM_PL_VRAM
[10:13:08] [PASSED] Init resource in a private placement
[10:13:08] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[10:13:08] ============= [PASSED] ttm_resource_init_basic =============
[10:13:08] [PASSED] ttm_resource_init_pinned
[10:13:08] [PASSED] ttm_resource_fini_basic
[10:13:08] [PASSED] ttm_resource_manager_init_basic
[10:13:08] [PASSED] ttm_resource_manager_usage_basic
[10:13:08] [PASSED] ttm_resource_manager_set_used_basic
[10:13:08] [PASSED] ttm_sys_man_alloc_basic
[10:13:08] [PASSED] ttm_sys_man_free_basic
[10:13:08] ================== [PASSED] ttm_resource ===================
[10:13:08] =================== ttm_tt (15 subtests) ===================
[10:13:08] ==================== ttm_tt_init_basic  ====================
[10:13:08] [PASSED] Page-aligned size
[10:13:08] [PASSED] Extra pages requested
[10:13:08] ================ [PASSED] ttm_tt_init_basic ================
[10:13:08] [PASSED] ttm_tt_init_misaligned
[10:13:08] [PASSED] ttm_tt_fini_basic
[10:13:08] [PASSED] ttm_tt_fini_sg
[10:13:08] [PASSED] ttm_tt_fini_shmem
[10:13:08] [PASSED] ttm_tt_create_basic
[10:13:08] [PASSED] ttm_tt_create_invalid_bo_type
[10:13:08] [PASSED] ttm_tt_create_ttm_exists
[10:13:08] [PASSED] ttm_tt_create_failed
[10:13:08] [PASSED] ttm_tt_destroy_basic
[10:13:08] [PASSED] ttm_tt_populate_null_ttm
[10:13:08] [PASSED] ttm_tt_populate_populated_ttm
[10:13:08] [PASSED] ttm_tt_unpopulate_basic
[10:13:08] [PASSED] ttm_tt_unpopulate_empty_ttm
[10:13:08] [PASSED] ttm_tt_swapin_basic
[10:13:08] ===================== [PASSED] ttm_tt ======================
[10:13:08] =================== ttm_bo (14 subtests) ===================
[10:13:08] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[10:13:08] [PASSED] Cannot be interrupted and sleeps
[10:13:08] [PASSED] Cannot be interrupted, locks straight away
[10:13:08] [PASSED] Can be interrupted, sleeps
[10:13:08] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[10:13:08] [PASSED] ttm_bo_reserve_locked_no_sleep
[10:13:08] [PASSED] ttm_bo_reserve_no_wait_ticket
[10:13:08] [PASSED] ttm_bo_reserve_double_resv
[10:13:08] [PASSED] ttm_bo_reserve_interrupted
[10:13:08] [PASSED] ttm_bo_reserve_deadlock
[10:13:08] [PASSED] ttm_bo_unreserve_basic
[10:13:08] [PASSED] ttm_bo_unreserve_pinned
[10:13:08] [PASSED] ttm_bo_unreserve_bulk
[10:13:08] [PASSED] ttm_bo_fini_basic
[10:13:08] [PASSED] ttm_bo_fini_shared_resv
[10:13:08] [PASSED] ttm_bo_pin_basic
[10:13:08] [PASSED] ttm_bo_pin_unpin_resource
[10:13:08] [PASSED] ttm_bo_multiple_pin_one_unpin
[10:13:08] ===================== [PASSED] ttm_bo ======================
[10:13:08] ============== ttm_bo_validate (22 subtests) ===============
[10:13:08] ============== ttm_bo_init_reserved_sys_man  ===============
[10:13:08] [PASSED] Buffer object for userspace
[10:13:08] [PASSED] Kernel buffer object
[10:13:08] [PASSED] Shared buffer object
[10:13:08] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[10:13:08] ============== ttm_bo_init_reserved_mock_man  ==============
[10:13:08] [PASSED] Buffer object for userspace
[10:13:08] [PASSED] Kernel buffer object
[10:13:08] [PASSED] Shared buffer object
[10:13:08] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[10:13:08] [PASSED] ttm_bo_init_reserved_resv
[10:13:08] ================== ttm_bo_validate_basic  ==================
[10:13:08] [PASSED] Buffer object for userspace
[10:13:08] [PASSED] Kernel buffer object
[10:13:08] [PASSED] Shared buffer object
[10:13:08] ============== [PASSED] ttm_bo_validate_basic ==============
[10:13:08] [PASSED] ttm_bo_validate_invalid_placement
[10:13:08] ============= ttm_bo_validate_same_placement  ==============
[10:13:08] [PASSED] System manager
[10:13:08] [PASSED] VRAM manager
[10:13:08] ========= [PASSED] ttm_bo_validate_same_placement ==========
[10:13:08] [PASSED] ttm_bo_validate_failed_alloc
[10:13:08] [PASSED] ttm_bo_validate_pinned
[10:13:08] [PASSED] ttm_bo_validate_busy_placement
[10:13:08] ================ ttm_bo_validate_multihop  =================
[10:13:08] [PASSED] Buffer object for userspace
[10:13:08] [PASSED] Kernel buffer object
[10:13:08] [PASSED] Shared buffer object
[10:13:08] ============ [PASSED] ttm_bo_validate_multihop =============
[10:13:08] ========== ttm_bo_validate_no_placement_signaled  ==========
[10:13:08] [PASSED] Buffer object in system domain, no page vector
[10:13:08] [PASSED] Buffer object in system domain with an existing page vector
[10:13:08] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[10:13:08] ======== ttm_bo_validate_no_placement_not_signaled  ========
[10:13:08] [PASSED] Buffer object for userspace
[10:13:08] [PASSED] Kernel buffer object
[10:13:08] [PASSED] Shared buffer object
[10:13:08] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[10:13:08] [PASSED] ttm_bo_validate_move_fence_signaled
[10:13:08] ========= ttm_bo_validate_move_fence_not_signaled  =========
[10:13:08] [PASSED] Waits for GPU
[10:13:08] [PASSED] Tries to lock straight away
[10:13:08] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[10:13:08] [PASSED] ttm_bo_validate_swapout
[10:13:08] [PASSED] ttm_bo_validate_happy_evict
[10:13:08] [PASSED] ttm_bo_validate_all_pinned_evict
[10:13:08] [PASSED] ttm_bo_validate_allowed_only_evict
[10:13:08] [PASSED] ttm_bo_validate_deleted_evict
[10:13:08] [PASSED] ttm_bo_validate_busy_domain_evict
[10:13:08] [PASSED] ttm_bo_validate_evict_gutting
[10:13:08] [PASSED] ttm_bo_validate_recrusive_evict
[10:13:08] ================= [PASSED] ttm_bo_validate =================
[10:13:08] ============================================================
[10:13:08] Testing complete. Ran 102 tests: passed: 102
[10:13:08] Elapsed time: 12.896s total, 2.535s configuring, 10.146s building, 0.178s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[10:13:08] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:13:11] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:13:19] Starting KUnit Kernel (1/1)...
[10:13:19] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:13:20] =============== dma-buf-fence (12 subtests) ================
[10:13:20] [PASSED] test_sanitycheck
[10:13:20] [PASSED] test_signaling
[10:13:20] [PASSED] test_add_callback
[10:13:20] [PASSED] test_late_add_callback
[10:13:20] [PASSED] test_rm_callback
[10:13:20] [PASSED] test_late_rm_callback
[10:13:20] [PASSED] test_status
[10:13:20] [PASSED] test_error
[10:13:20] [PASSED] test_wait
[10:13:20] [PASSED] test_wait_timeout
[10:13:20] [PASSED] test_stub
[10:13:20] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[10:13:20] ================== [PASSED] dma-buf-fence ==================
[10:13:20] ============ dma-buf-fence-chain (11 subtests) =============
[10:13:20] [PASSED] test_sanitycheck
[10:13:20] [PASSED] test_find_seqno
[10:13:20] [PASSED] test_find_signaled
[10:13:20] [PASSED] test_find_out_of_order
[10:13:25] [PASSED] test_find_gap
[10:13:25] [PASSED] test_find_race
[10:13:25] [PASSED] test_signal_forward
[10:13:25] [PASSED] test_signal_backward
[10:13:25] [PASSED] test_wait_forward
[10:13:25] [PASSED] test_wait_backward
[10:13:25] [PASSED] test_wait_random
[10:13:25] =============== [PASSED] dma-buf-fence-chain ===============
[10:13:25] ============ dma-buf-fence-unwrap (11 subtests) ============
[10:13:25] [PASSED] test_sanitycheck
[10:13:25] [PASSED] test_unwrap_array
[10:13:25] [PASSED] test_unwrap_chain
[10:13:25] [PASSED] test_unwrap_chain_array
[10:13:25] [PASSED] test_unwrap_merge
[10:13:25] [PASSED] test_unwrap_merge_duplicate
[10:13:25] [PASSED] test_unwrap_merge_seqno
[10:13:25] [PASSED] test_unwrap_merge_order
[10:13:25] [PASSED] test_unwrap_merge_complex
[10:13:25] [PASSED] test_unwrap_merge_complex_seqno
[10:13:25] [PASSED] test_dedup_empty
[10:13:25] ============== [PASSED] dma-buf-fence-unwrap ===============
[10:13:25] ================ dma-buf-resv (5 subtests) =================
[10:13:25] [PASSED] test_sanitycheck
[10:13:25] ===================== test_signaling  ======================
[10:13:25] [PASSED] kernel
[10:13:25] [PASSED] write
[10:13:25] [PASSED] read
[10:13:25] [PASSED] bookkeep
[10:13:25] ================= [PASSED] test_signaling ==================
[10:13:25] ====================== test_for_each  ======================
[10:13:25] [PASSED] kernel
[10:13:25] [PASSED] write
[10:13:25] [PASSED] read
[10:13:25] [PASSED] bookkeep
[10:13:25] ================== [PASSED] test_for_each ==================
[10:13:25] ================= test_for_each_unlocked  ==================
[10:13:25] [PASSED] kernel
[10:13:25] [PASSED] write
[10:13:25] [PASSED] read
[10:13:25] [PASSED] bookkeep
[10:13:25] ============= [PASSED] test_for_each_unlocked ==============
[10:13:25] ===================== test_get_fences  =====================
[10:13:25] [PASSED] kernel
[10:13:25] [PASSED] write
[10:13:25] [PASSED] read
[10:13:25] [PASSED] bookkeep
[10:13:25] ================= [PASSED] test_get_fences =================
[10:13:25] ================== [PASSED] dma-buf-resv ===================
[10:13:25] ============================================================
[10:13:25] Testing complete. Ran 51 tests: passed: 50, skipped: 1
[10:13:25] Elapsed time: 16.647s total, 2.513s configuring, 8.812s building, 5.282s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

Re: [PATCH v4 6/7] drm/i915/display: Program and enable the DP symbol based timing generator

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/display: invalid CMTG MMIO write in intel_set_transcoder_timings()
--

commit d5e98872efc6064e978436ee34bbcfdf86c29006
Author: Arun R Murthy <arun.r.murthy@intel.com>

drm/i915/display: Program and enable the DP symbol based timing generator

This commit programs and enables the DP link layer symbol based timing
generator, including the 128-bit Data M/N registers, HACT/HTOTAL/CHUNK_SIZE
timing registers, and TRANSCONF configuration and state readout.

> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 15117b715e1d5..d450b34b8035a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c

[ ... ]

> @@ -2936,6 +2996,17 @@ void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state,
>  		intel_de_write(display, DP_MIN_HBLANK_CTL(transcoder),
>  			       crtc_state->min_hblank);
>  	}
> +
> +	if (crtc_state->dp_symbol_tg.enable) {
> +		const struct intel_dp_symbol_tg *tg = &crtc_state->dp_symbol_tg;
> +
> +		intel_de_write(display, TRANS_LLSYM_HACT(display, transcoder),
> +			       TRANS_LLSYM_HACT_VAL(tg->hactive - 1));
> +		intel_de_write(display, TRANS_LLSYM_HTOTAL(display, transcoder),
> +			       TRANS_LLSYM_HTOTAL_VAL(tg->htotal - 1));
> +		intel_de_write(display, TRANS_LLSYM_CHUNK_SIZE(display, transcoder),
> +			       TRANS_LLSYM_CHUNK_SIZE_VAL(tg->chunk_size));
> +	}
>  }

[Severity: Medium]
Can this write to non-existent CMTG MMIO registers when
intel_set_transcoder_timings() is called for TRANSCODER_CMTG0 or
TRANSCODER_CMTG1?

During modeset and DC state restore on display version 35,
hsw_configure_cpu_transcoder() and intel_cmtg_restore() call
intel_cmtg_set_timings() -> intel_set_transcoder_timings(crtc_state,
cmtg_transcoder) when cpu_transcoder is TRANSCODER_A or TRANSCODER_B on an
eDP output:

drivers/gpu/drm/i915/display/intel_cmtg.c:intel_cmtg_set_timings() {
	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
	...
	if (type == LRR)
		intel_set_transcoder_timings_lrr(crtc_state, cmtg_transcoder);
	else
		intel_set_transcoder_timings(crtc_state, cmtg_transcoder);
}

When an eDP panel operates at a 128b/132b UHBR link rate without MSO
splitter, intel_dp_compute_symbol_tg() sets crtc_state->dp_symbol_tg.enable
to true.

Just above this block in intel_set_transcoder_timings(), the
DP_MIN_HBLANK_CTL write checks that transcoder is not a CMTG transcoder:

	if (DISPLAY_VER(display) >= 30 &&
	    transcoder != TRANSCODER_CMTG0 &&
	    transcoder != TRANSCODER_CMTG1) {
		intel_de_write(display, DP_MIN_HBLANK_CTL(transcoder),
			       crtc_state->min_hblank);
	}

Without a similar check on transcoder here, _MMIO_TRANS2() translates
TRANS_LLSYM_HACT, TRANS_LLSYM_HTOTAL, and TRANS_LLSYM_CHUNK_SIZE using the
CMTG base offset and writes to unclaimed register offsets 0x6f0dc..0x6f0e4
(or 0x6f1dc..0x6f1e4).

Should this block also check transcoder != TRANSCODER_CMTG0 &&
transcoder != TRANSCODER_CMTG1 before writing the TRANS_LLSYM_* registers?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261103-vlk-64036-dp-symbol-tg-v4-0-6cf8a588b54c@intel.com?part=6

✓ Xe.CI.BAT: success for drm/i915/dp: Add support for the DP symbol based timing generator (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 895 bytes --]

== Series Details ==

Series: drm/i915/dp: Add support for the DP symbol based timing generator (rev3)
URL   : https://patchwork.freedesktop.org/series/177001/
State : success

== Summary ==

CI Bug Log - changes from xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5_BAT -> xe-pw-177001v3_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (15 -> 15)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5 -> xe-pw-177001v3

  IGT_9175: 9175
  xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5: 279235273fc6c0a33df863b4a1cc52ec1e73aba5
  xe-pw-177001v3: 177001v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/index.html

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✗ Xe.CI.FULL: failure for drm/i915/dp: Add support for the DP symbol based timing generator (rev3)

[Patchwork]

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== Series Details ==

Series: drm/i915/dp: Add support for the DP symbol based timing generator (rev3)
URL   : https://patchwork.freedesktop.org/series/177001/
State : failure

== Summary ==

CI Bug Log - changes from xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5_FULL -> xe-pw-177001v3_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-177001v3_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-177001v3_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (3 -> 3)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-177001v3_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_plane@plane-panning-bottom-right-suspend:
    - shard-ptl:          [PASS][1] -> [INCOMPLETE][2] +1 other test incomplete
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5/shard-ptl-5/igt@kms_plane@plane-panning-bottom-right-suspend.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-3/igt@kms_plane@plane-panning-bottom-right-suspend.html

  * igt@xe_pxp@pxp-stale-bo-exec-post-rpm:
    - shard-lnl:          [PASS][3] -> [SKIP][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5/shard-lnl-3/igt@xe_pxp@pxp-stale-bo-exec-post-rpm.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-3/igt@xe_pxp@pxp-stale-bo-exec-post-rpm.html

  
#### Warnings ####

  * igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier-source-clamping:
    - shard-bmg:          [SKIP][5] ([Intel XE#7283]) -> [ABORT][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5/shard-bmg-9/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier-source-clamping.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-3/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier-source-clamping.html

  
Known issues
------------

  Here are the changes found in xe-pw-177001v3_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@intel_hwmon@hwmon-write:
    - shard-ptl:          NOTRUN -> [SKIP][7] ([Intel XE#7225])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-2/igt@intel_hwmon@hwmon-write.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2327])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-8/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#1407])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
    - shard-ptl:          NOTRUN -> [SKIP][10] ([Intel XE#5808]) +2 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
    - shard-lnl:          NOTRUN -> [SKIP][11] ([Intel XE#1124]) +2 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-7/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#610] / [Intel XE#7387])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-5/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#1124]) +3 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-8/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-target-3840x2160p:
    - shard-ptl:          NOTRUN -> [SKIP][14] ([Intel XE#7679])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@kms_bw@connected-linear-tiling-2-displays-target-3840x2160p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-c-edp-1:
    - shard-ptl:          NOTRUN -> [SKIP][15] ([Intel XE#5823] / [Intel XE#6918]) +4 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-c-edp-1.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#2887]) +1 other test skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-b-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2652]) +3 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-2/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-b-dp-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][18] ([Intel XE#3432])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-7/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs:
    - shard-ptl:          NOTRUN -> [SKIP][19] ([Intel XE#5822]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#2887]) +8 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-8/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt2020:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#7358])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-5/igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt2020.html

  * igt@kms_chamelium_color_pipeline@plane-lut1d-pre-ctm3x4:
    - shard-ptl:          NOTRUN -> [SKIP][22] ([Intel XE#8391])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@kms_chamelium_color_pipeline@plane-lut1d-pre-ctm3x4.html

  * igt@kms_chamelium_edid@dp-edid-change-during-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][23] ([Intel XE#373]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - shard-ptl:          NOTRUN -> [SKIP][24] ([Intel XE#2252]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-2/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_chamelium_hpd@dp-hpd-after-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#2252]) +4 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html

  * igt@kms_color_pipeline@plane-lut1d-lut1d@pipe-b-plane-4:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#6969]) +23 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@kms_color_pipeline@plane-lut1d-lut1d@pipe-b-plane-4.html

  * igt@kms_content_protection@atomic-hdcp14:
    - shard-ptl:          NOTRUN -> [SKIP][27] ([Intel XE#7642])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@kms_content_protection@atomic-hdcp14.html

  * igt@kms_content_protection@dp-mst-type-1-suspend-resume:
    - shard-lnl:          NOTRUN -> [SKIP][28] ([Intel XE#6974])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@kms_content_protection@dp-mst-type-1-suspend-resume.html
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#6974])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@kms_content_protection@dp-mst-type-1-suspend-resume.html

  * igt@kms_content_protection@legacy-hdcp14:
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#7642])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-7/igt@kms_content_protection@legacy-hdcp14.html

  * igt@kms_cursor_crc@cursor-offscreen-256x85:
    - shard-ptl:          NOTRUN -> [SKIP][31] ([Intel XE#5900])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@kms_cursor_crc@cursor-offscreen-256x85.html

  * igt@kms_cursor_crc@cursor-onscreen-max-size:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#1424])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-7/igt@kms_cursor_crc@cursor-onscreen-max-size.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-lnl:          NOTRUN -> [SKIP][33] ([Intel XE#2321] / [Intel XE#7355])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-7/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#2321] / [Intel XE#7355])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-5/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html

  * igt@kms_cursor_crc@cursor-rapid-movement-64x21:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#2320])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-8/igt@kms_cursor_crc@cursor-rapid-movement-64x21.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-lnl:          NOTRUN -> [SKIP][36] ([Intel XE#309] / [Intel XE#7343]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
    - shard-lnl:          NOTRUN -> [SKIP][37] ([Intel XE#309] / [Intel XE#7343] / [Intel XE#7935])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#1508])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-8/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dp_link_training@non-uhbr-mst-tbtalt-train:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#9528])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@kms_dp_link_training@non-uhbr-mst-tbtalt-train.html
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#9528])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@kms_dp_link_training@non-uhbr-mst-tbtalt-train.html

  * igt@kms_dp_link_training@non-uhbr-sst-direct-train:
    - shard-ptl:          NOTRUN -> [SKIP][41] ([Intel XE#9534])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-2/igt@kms_dp_link_training@non-uhbr-sst-direct-train.html

  * igt@kms_dp_link_training@non-uhbr-sst-tbtalt-train:
    - shard-ptl:          NOTRUN -> [SKIP][42] ([Intel XE#9539])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-2/igt@kms_dp_link_training@non-uhbr-sst-tbtalt-train.html

  * igt@kms_dp_link_training@uhbr-mst-direct-train:
    - shard-ptl:          NOTRUN -> [SKIP][43] ([Intel XE#9527])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@kms_dp_link_training@uhbr-mst-direct-train.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#4331] / [Intel XE#7227])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-7/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#8265])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#4422] / [Intel XE#7442])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-5/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#2375])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_feature_discovery@psr2:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#2374] / [Intel XE#6128])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-8/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible:
    - shard-ptl:          NOTRUN -> [SKIP][49] ([Intel XE#2316])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-2/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html

  * igt@kms_flip@2x-flip-vs-panning-vs-hang:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#1421]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@kms_flip@2x-flip-vs-panning-vs-hang.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          [PASS][51] -> [FAIL][52] ([Intel XE#301])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][53] ([Intel XE#7178] / [Intel XE#7351]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling.html
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#7178] / [Intel XE#7351])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-ptl:          NOTRUN -> [SKIP][55] ([Intel XE#5800] / [Intel XE#6312])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-2/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#2311]) +19 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@drrshdr-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][57] ([Intel XE#7905]) +9 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@kms_frontbuffer_tracking@drrshdr-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrshdr-abgr161616f-draw-render:
    - shard-ptl:          NOTRUN -> [SKIP][58] ([Intel XE#7061]) +1 other test skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@kms_frontbuffer_tracking@drrshdr-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-render:
    - shard-ptl:          NOTRUN -> [SKIP][59] ([Intel XE#5812]) +27 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][60] ([Intel XE#4141]) +3 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][61] ([Intel XE#7061] / [Intel XE#7356]) +2 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-indfb-scaledprimary:
    - shard-lnl:          NOTRUN -> [SKIP][62] ([Intel XE#6312] / [Intel XE#651])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcdrrs-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-cur-indfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][63] ([Intel XE#6312]) +2 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-7/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-shrfb-msflip-blt:
    - shard-ptl:          NOTRUN -> [SKIP][64] ([Intel XE#6312]) +2 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][65] ([Intel XE#7061] / [Intel XE#7356]) +2 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@hdr-1p-primscrn-indfb-pgflip-blt:
    - shard-ptl:          NOTRUN -> [SKIP][66] ([Intel XE#7865]) +7 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-2/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][67] ([Intel XE#7865]) +4 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][68] ([Intel XE#2313]) +24 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#656] / [Intel XE#7905]) +5 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psrhdr-abgr161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#7061]) +1 other test skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@kms_frontbuffer_tracking@psrhdr-abgr161616f-draw-blt.html
    - shard-lnl:          NOTRUN -> [SKIP][71] ([Intel XE#7061])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@kms_frontbuffer_tracking@psrhdr-abgr161616f-draw-blt.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          NOTRUN -> [SKIP][72] ([Intel XE#3544])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_joiner@basic-force-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][73] ([Intel XE#6911] / [Intel XE#7466])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-5/igt@kms_joiner@basic-force-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-ptl:          NOTRUN -> [SKIP][74] ([Intel XE#6900])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#4090] / [Intel XE#7443])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-bmg:          NOTRUN -> [SKIP][76] ([Intel XE#2486])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier:
    - shard-ptl:          NOTRUN -> [SKIP][77] ([Intel XE#7283]) +2 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][78] ([Intel XE#7283]) +2 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-5/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier.html

  * igt@kms_plane@pixel-format-4-tiled-modifier@pipe-a-plane-5:
    - shard-bmg:          NOTRUN -> [SKIP][79] ([Intel XE#8303]) +1 other test skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-8/igt@kms_plane@pixel-format-4-tiled-modifier@pipe-a-plane-5.html

  * igt@kms_plane@pixel-format-yf-tiled-modifier:
    - shard-lnl:          NOTRUN -> [SKIP][80] ([Intel XE#7283])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-7/igt@kms_plane@pixel-format-yf-tiled-modifier.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-ptl:          NOTRUN -> [SKIP][81] ([Intel XE#5020])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20@pipe-b:
    - shard-lnl:          NOTRUN -> [SKIP][82] ([Intel XE#2763] / [Intel XE#6886]) +7 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20@pipe-b.html

  * igt@kms_pm_dc@dc3co-framedrop-check:
    - shard-ptl:          NOTRUN -> [SKIP][83] ([Intel XE#8395] / [Intel XE#8396]) +1 other test skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@kms_pm_dc@dc3co-framedrop-check.html

  * igt@kms_pm_dc@dc3co-framedrop-check@psr2-xrgb8888:
    - shard-ptl:          NOTRUN -> [SKIP][84] ([Intel XE#8396]) +1 other test skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@kms_pm_dc@dc3co-framedrop-check@psr2-xrgb8888.html

  * igt@kms_pm_dc@dc5-dpms:
    - shard-lnl:          NOTRUN -> [FAIL][85] ([Intel XE#8399])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@kms_pm_dc@dc5-dpms.html

  * igt@kms_pm_dc@dc5-pageflip-negative:
    - shard-bmg:          NOTRUN -> [SKIP][86] ([Intel XE#6927] / [Intel XE#8854])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-8/igt@kms_pm_dc@dc5-pageflip-negative.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-bmg:          NOTRUN -> [SKIP][87] ([Intel XE#7794])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-5/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-lnl:          NOTRUN -> [SKIP][88] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area:
    - shard-ptl:          NOTRUN -> [SKIP][89] ([Intel XE#5858] / [Intel XE#7304]) +1 other test skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-2/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-a-edp-1:
    - shard-ptl:          NOTRUN -> [SKIP][90] ([Intel XE#5858])
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-2/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-a-edp-1.html

  * igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][91] ([Intel XE#1489]) +2 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr@fbc-pr-dpms:
    - shard-ptl:          NOTRUN -> [SKIP][92] ([Intel XE#1406])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@kms_psr@fbc-pr-dpms.html

  * igt@kms_psr@fbc-psr2-basic:
    - shard-bmg:          NOTRUN -> [SKIP][93] ([Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-8/igt@kms_psr@fbc-psr2-basic.html

  * igt@kms_psr@fbc-psr2-sprite-plane-onoff:
    - shard-lnl:          NOTRUN -> [SKIP][94] ([Intel XE#1406] / [Intel XE#7345])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-7/igt@kms_psr@fbc-psr2-sprite-plane-onoff.html

  * igt@kms_psr@fbc-psr2-sprite-plane-onoff@edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][95] ([Intel XE#1406] / [Intel XE#4609] / [Intel XE#7345])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-7/igt@kms_psr@fbc-psr2-sprite-plane-onoff@edp-1.html

  * igt@kms_psr@pr-dpms:
    - shard-lnl:          NOTRUN -> [SKIP][96] ([Intel XE#1406])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-7/igt@kms_psr@pr-dpms.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-bmg:          NOTRUN -> [SKIP][97] ([Intel XE#7795])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-bmg:          NOTRUN -> [SKIP][98] ([Intel XE#3904] / [Intel XE#7342])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
    - shard-lnl:          NOTRUN -> [SKIP][99] ([Intel XE#3904] / [Intel XE#7342])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_scaling_modes@scaling-mode-full:
    - shard-bmg:          NOTRUN -> [SKIP][100] ([Intel XE#2413])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-8/igt@kms_scaling_modes@scaling-mode-full.html

  * igt@kms_setmode@invalid-clone-exclusive-crtc:
    - shard-ptl:          NOTRUN -> [SKIP][101] ([Intel XE#5910])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@kms_setmode@invalid-clone-exclusive-crtc.html

  * igt@kms_sharpness_filter@invalid-filter-with-plane:
    - shard-bmg:          NOTRUN -> [SKIP][102] ([Intel XE#6503])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@kms_sharpness_filter@invalid-filter-with-plane.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-ptl:          NOTRUN -> [SKIP][103] ([Intel XE#5848])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-2/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_vblank@ts-continuation-dpms-suspend:
    - shard-bmg:          [PASS][104] -> [DMESG-WARN][105] ([Intel XE#9365] / [Intel XE#9465])
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5/shard-bmg-5/igt@kms_vblank@ts-continuation-dpms-suspend.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-5/igt@kms_vblank@ts-continuation-dpms-suspend.html

  * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-d-dp-2:
    - shard-bmg:          [PASS][106] -> [DMESG-WARN][107] ([Intel XE#9365])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5/shard-bmg-5/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-d-dp-2.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-5/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-d-dp-2.html

  * igt@kms_vrr@cmrr-desktop-mode:
    - shard-lnl:          NOTRUN -> [SKIP][108] ([Intel XE#9271]) +1 other test skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-7/igt@kms_vrr@cmrr-desktop-mode.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-ptl:          [PASS][109] -> [FAIL][110] ([Intel XE#4227] / [Intel XE#7397])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5/shard-ptl-4/igt@kms_vrr@flip-basic-fastset.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@kms_vrr@flip-basic-fastset.html

  * igt@kms_vrr@flip-basic-fastset@pipe-a-edp-1:
    - shard-ptl:          [PASS][111] -> [FAIL][112] ([Intel XE#6293] / [Intel XE#7397])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5/shard-ptl-4/igt@kms_vrr@flip-basic-fastset@pipe-a-edp-1.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@kms_vrr@flip-basic-fastset@pipe-a-edp-1.html

  * igt@kms_vrr@lobf:
    - shard-ptl:          NOTRUN -> [SKIP][113] ([Intel XE#5950] / [Intel XE#9277])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-2/igt@kms_vrr@lobf.html

  * igt@kms_vrr@lobf@pipe-a-edp-1:
    - shard-ptl:          NOTRUN -> [SKIP][114] ([Intel XE#7638] / [Intel XE#9277])
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-2/igt@kms_vrr@lobf@pipe-a-edp-1.html

  * igt@sriov_basic@pf-unbind-with-vfs-enabled-numvfs-all:
    - shard-bmg:          NOTRUN -> [ABORT][115] ([Intel XE#8868])
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@sriov_basic@pf-unbind-with-vfs-enabled-numvfs-all.html
    - shard-lnl:          NOTRUN -> [SKIP][116] ([Intel XE#8866])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@sriov_basic@pf-unbind-with-vfs-enabled-numvfs-all.html

  * igt@xe_evict@evict-beng-cm-threads-large-multi-vm:
    - shard-ptl:          NOTRUN -> [SKIP][117] ([Intel XE#5764]) +2 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@xe_evict@evict-beng-cm-threads-large-multi-vm.html

  * igt@xe_evict@evict-beng-mixed-many-threads-large:
    - shard-lnl:          NOTRUN -> [SKIP][118] ([Intel XE#6540] / [Intel XE#688]) +2 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-7/igt@xe_evict@evict-beng-mixed-many-threads-large.html

  * igt@xe_exec_balancer@many-execqueues-cm-parallel-userptr-invalidate:
    - shard-ptl:          NOTRUN -> [SKIP][119] ([Intel XE#7482]) +3 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@xe_exec_balancer@many-execqueues-cm-parallel-userptr-invalidate.html

  * igt@xe_exec_balancer@once-cm-parallel-userptr-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][120] ([Intel XE#7482]) +4 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@xe_exec_balancer@once-cm-parallel-userptr-rebind.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][121] ([Intel XE#2322] / [Intel XE#7372])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][122] ([Intel XE#1392])
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate:
    - shard-ptl:          NOTRUN -> [SKIP][123] ([Intel XE#5575] / [Intel XE#7484]) +1 other test skip
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-rebind-imm:
    - shard-ptl:          NOTRUN -> [SKIP][124] ([Intel XE#8374]) +2 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-rebind-imm.html

  * igt@xe_exec_fault_mode@twice-multi-queue:
    - shard-bmg:          NOTRUN -> [SKIP][125] ([Intel XE#8374]) +3 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@xe_exec_fault_mode@twice-multi-queue.html
    - shard-lnl:          NOTRUN -> [SKIP][126] ([Intel XE#8374]) +4 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@xe_exec_fault_mode@twice-multi-queue.html

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-userptr:
    - shard-ptl:          NOTRUN -> [SKIP][127] ([Intel XE#8364]) +8 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@xe_exec_multi_queue@max-queues-preempt-mode-userptr.html

  * igt@xe_exec_multi_queue@one-queue-close-fd-smem:
    - shard-lnl:          NOTRUN -> [SKIP][128] ([Intel XE#8364]) +7 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-7/igt@xe_exec_multi_queue@one-queue-close-fd-smem.html

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-close-fd-smem:
    - shard-bmg:          NOTRUN -> [SKIP][129] ([Intel XE#8364]) +13 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@xe_exec_multi_queue@one-queue-preempt-mode-close-fd-smem.html

  * igt@xe_exec_reset@cm-multi-queue-close-fd:
    - shard-lnl:          NOTRUN -> [SKIP][130] ([Intel XE#8369])
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@xe_exec_reset@cm-multi-queue-close-fd.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-comp-single-vma:
    - shard-ptl:          NOTRUN -> [SKIP][131] ([Intel XE#6196])
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-comp-single-vma.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][132] ([Intel XE#8378]) +1 other test skip
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@xe_exec_threads@threads-multi-queue-mixed-userptr-invalidate-race.html
    - shard-lnl:          NOTRUN -> [SKIP][133] ([Intel XE#8378]) +1 other test skip
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@xe_exec_threads@threads-multi-queue-mixed-userptr-invalidate-race.html

  * igt@xe_exec_threads@threads-multi-queue-shared-vm-basic:
    - shard-ptl:          NOTRUN -> [SKIP][134] ([Intel XE#8378]) +3 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-2/igt@xe_exec_threads@threads-multi-queue-shared-vm-basic.html

  * igt@xe_media_fill@media-fill:
    - shard-bmg:          NOTRUN -> [SKIP][135] ([Intel XE#2459] / [Intel XE#2596] / [Intel XE#7321] / [Intel XE#7453])
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-5/igt@xe_media_fill@media-fill.html

  * igt@xe_pat@xa-app-transient-media-off:
    - shard-bmg:          NOTRUN -> [SKIP][136] ([Intel XE#7590])
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@xe_pat@xa-app-transient-media-off.html

  * igt@xe_pm@d3cold-basic-exec:
    - shard-lnl:          NOTRUN -> [SKIP][137] ([Intel XE#2284] / [Intel XE#366] / [Intel XE#7370])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-7/igt@xe_pm@d3cold-basic-exec.html

  * igt@xe_pm@s3-mocs:
    - shard-ptl:          NOTRUN -> [SKIP][138] ([Intel XE#6867])
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-2/igt@xe_pm@s3-mocs.html

  * igt@xe_pm@vram-d3cold-threshold:
    - shard-bmg:          NOTRUN -> [SKIP][139] ([Intel XE#579] / [Intel XE#7329] / [Intel XE#7517])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@xe_pm@vram-d3cold-threshold.html

  * igt@xe_pm_residency@gt-c6-freeze@gt1:
    - shard-bmg:          [PASS][140] -> [FAIL][141] ([Intel XE#9254]) +1 other test fail
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5/shard-bmg-6/igt@xe_pm_residency@gt-c6-freeze@gt1.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-10/igt@xe_pm_residency@gt-c6-freeze@gt1.html

  * igt@xe_pxp@pxp-termination-key-update-post-termination-irq:
    - shard-bmg:          NOTRUN -> [SKIP][142] ([Intel XE#4733] / [Intel XE#7417])
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-8/igt@xe_pxp@pxp-termination-key-update-post-termination-irq.html

  * igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz:
    - shard-ptl:          NOTRUN -> [SKIP][143] ([Intel XE#6019])
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz.html

  * igt@xe_query@multigpu-query-uc-fw-version-guc:
    - shard-bmg:          NOTRUN -> [SKIP][144] ([Intel XE#944])
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-5/igt@xe_query@multigpu-query-uc-fw-version-guc.html

  * igt@xe_vm@out-of-memory:
    - shard-ptl:          NOTRUN -> [SKIP][145] ([Intel XE#5745] / [Intel XE#7892])
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@xe_vm@out-of-memory.html

  
#### Possible fixes ####

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-lnl:          [FAIL][146] ([Intel XE#8098] / [Intel XE#9690]) -> [PASS][147] +1 other test pass
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5/shard-lnl-7/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-lnl:          [FAIL][148] ([Intel XE#1231]) -> [PASS][149]
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5/shard-lnl-3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [INCOMPLETE][150] ([Intel XE#7084] / [Intel XE#8150]) -> [PASS][151] +1 other test pass
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5/shard-bmg-10/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-9/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_flip@wf_vblank-ts-check-interruptible@a-edp1:
    - shard-ptl:          [INCOMPLETE][152] -> [PASS][153] +1 other test pass
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5/shard-ptl-2/igt@kms_flip@wf_vblank-ts-check-interruptible@a-edp1.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-2/igt@kms_flip@wf_vblank-ts-check-interruptible@a-edp1.html

  * igt@kms_vrr@flip-dpms@pipe-a-edp-1:
    - shard-ptl:          [FAIL][154] ([Intel XE#4227] / [Intel XE#7397]) -> [PASS][155] +3 other tests pass
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5/shard-ptl-1/igt@kms_vrr@flip-dpms@pipe-a-edp-1.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-1/igt@kms_vrr@flip-dpms@pipe-a-edp-1.html

  * igt@xe_exec_fault_mode@atomic-many:
    - shard-bmg:          [FAIL][156] ([Intel XE#8578]) -> [PASS][157]
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5/shard-bmg-5/igt@xe_exec_fault_mode@atomic-many.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-10/igt@xe_exec_fault_mode@atomic-many.html

  * igt@xe_pm@s4-vm-bind-unbind-all:
    - shard-lnl:          [ABORT][158] ([Intel XE#9362]) -> [PASS][159] +1 other test pass
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5/shard-lnl-3/igt@xe_pm@s4-vm-bind-unbind-all.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-lnl-8/igt@xe_pm@s4-vm-bind-unbind-all.html

  * igt@xe_pm@s4-vm-bind-userptr:
    - shard-ptl:          [ABORT][160] ([Intel XE#9362]) -> [PASS][161]
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5/shard-ptl-6/igt@xe_pm@s4-vm-bind-userptr.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-ptl-7/igt@xe_pm@s4-vm-bind-userptr.html

  
#### Warnings ####

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][162] ([Intel XE#2426] / [Intel XE#5848]) -> [FAIL][163] ([Intel XE#1729] / [Intel XE#7424])
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5/shard-bmg-6/igt@kms_tiled_display@basic-test-pattern.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][164] ([Intel XE#2426] / [Intel XE#5848]) -> [SKIP][165] ([Intel XE#2509] / [Intel XE#7437])
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5/shard-bmg-9/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1231]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1231
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2374
  [Intel XE#2375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2375
  [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2459
  [Intel XE#2486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2486
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2596
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4090]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4090
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
  [Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
  [Intel XE#5745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5745
  [Intel XE#5764]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5764
  [Intel XE#579]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/579
  [Intel XE#5800]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5800
  [Intel XE#5808]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5808
  [Intel XE#5812]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5812
  [Intel XE#5822]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5822
  [Intel XE#5823]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5823
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#5858]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5858
  [Intel XE#5900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5900
  [Intel XE#5910]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5910
  [Intel XE#5950]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5950
  [Intel XE#6019]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6019
  [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
  [Intel XE#6128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6128
  [Intel XE#6196]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6196
  [Intel XE#6293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6293
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6867]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6867
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6900
  [Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
  [Intel XE#6918]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6918
  [Intel XE#6927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6927
  [Intel XE#6969]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6969
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7225]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7225
  [Intel XE#7227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7227
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7321
  [Intel XE#7329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7329
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7345
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
  [Intel XE#7387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7387
  [Intel XE#7397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7397
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7442
  [Intel XE#7443]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7443
  [Intel XE#7453]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7453
  [Intel XE#7466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7466
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7484]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7484
  [Intel XE#7517]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7517
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7638]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7638
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#7794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7794
  [Intel XE#7795]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7795
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7892]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7892
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#7935]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7935
  [Intel XE#8098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8098
  [Intel XE#8150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8150
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8303]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8303
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8391
  [Intel XE#8395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8395
  [Intel XE#8396]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8396
  [Intel XE#8399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8399
  [Intel XE#8578]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8578
  [Intel XE#8854]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8854
  [Intel XE#8866]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8866
  [Intel XE#8868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8868
  [Intel XE#9254]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9254
  [Intel XE#9271]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9271
  [Intel XE#9277]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9277
  [Intel XE#9362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9362
  [Intel XE#9365]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9365
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#9465]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9465
  [Intel XE#9527]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9527
  [Intel XE#9528]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9528
  [Intel XE#9534]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9534
  [Intel XE#9539]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9539
  [Intel XE#9690]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9690


Build changes
-------------

  * Linux: xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5 -> xe-pw-177001v3

  IGT_9175: 9175
  xe-6051-279235273fc6c0a33df863b4a1cc52ec1e73aba5: 279235273fc6c0a33df863b4a1cc52ec1e73aba5
  xe-pw-177001v3: 177001v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177001v3/index.html

[-- Attachment #2: Type: text/html, Size: 61755 bytes --]

RE: [PATCH v4 7/7] drm/i915/dp: Don't limit the Link M/N ratio with the symbol timing generator

[Kandpal, Suraj]

> Subject: [PATCH v4 7/7] drm/i915/dp: Don't limit the Link M/N ratio with the
> symbol timing generator
> 
> The limit on the Link M/N ratio only applies to the pixel based timing
> generator, there is no such restriction when the symbol based timing
> generator is used.
> 
> Bspec: 68922
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c     | 17 +++++++++++++----
>  drivers/gpu/drm/i915/display/intel_dp_mst.c |  4 +++-
>  2 files changed, 16 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index
> 788c16df9801131294c73420c2c0d4d3ec848310..a8fa0809079e8b3f6fb574cfb
> 73fb6bb8b019cc3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1277,8 +1277,12 @@ static bool intel_dp_has_symbol_tg(struct
> intel_display *display, bool is_mst, b  }
> 
>  static int
> -intel_dp_get_max_m_n_ratio(struct intel_display *display)
> +intel_dp_get_max_m_n_ratio(struct intel_display *display, bool is_mst,
> +int link_rate)
>  {
> +	/* No Link M/N ratio limit with the symbol based timing generator */
> +	if (intel_dp_has_symbol_tg(display, is_mst,
> drm_dp_is_uhbr_rate(link_rate)))
> +		return INT_MAX;
> +
>  	if (DISPLAY_VER(display) >= 35)
>  		return 22;
> 
> @@ -1308,7 +1312,9 @@ bool intel_dp_can_support_m_n(struct
> intel_display *display,
>  			      const struct intel_crtc_state *crtc_state,
>  			      int pixel_clock, int link_rate)  {
> -	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
> +	bool is_mst = crtc_state &&
> +		      intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
> +	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display, is_mst,
> +link_rate);
>  	enum transcoder cpu_transcoder = TRANSCODER_A;
>  	u32 link_m, link_n;
>  	int m_n_ratio;
> @@ -1331,7 +1337,10 @@ void intel_dp_check_m_n_ratio(const struct
> intel_crtc_state *crtc_state,
>  			      struct intel_link_m_n *m_n)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
> -	int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display);
> +	int max_m_n_ratio =
> +		intel_dp_get_max_m_n_ratio(display,
> +					   intel_crtc_has_type(crtc_state,
> INTEL_OUTPUT_DP_MST),
> +					   crtc_state->port_clock);
>  	int m_n_ratio;
> 
>  	m_n->bypass_m_n_ratio_limit = false;
> @@ -2815,7 +2824,7 @@ intel_dp_compute_m_n_ratio_limits(struct
> intel_dp *intel_dp,
>  		drm_dbg_kms(display->drm,
>  			    "[CONNECTOR:%d:%s] No link config with a Link
> M/N ratio <= %d\n",
>  			    connector->base.base.id, connector->base.name,
> -			    intel_dp_get_max_m_n_ratio(display));
> +			    intel_dp_get_max_m_n_ratio(display, false, 0));

Just use crtc_state->port_clock instead of 0.

With that fixed LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> 
>  		return false;
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index
> 81ac454603603df42db477ddb26cfb2f620dcfea..fe9cdf771f481fc8a8b8f3f29e4
> a24aa53a53f94 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -1570,7 +1570,9 @@ mst_connector_mode_valid_ctx(struct
> drm_connector *_connector,
>  					   min_link_bpp_x16,
>  					   bw_overhead_flags);
> 
> -	if (!intel_dp_can_support_m_n(display, NULL, mode->clock,
> max_link_clock)) {
> +	/* MST always uses the symbol based timing generator, which has no
> Link M/N ratio limit */
> +	if (!HAS_DP_SYMBOL_TG(display) &&
> +	    !intel_dp_can_support_m_n(display, NULL, mode->clock,
> +max_link_clock)) {
>  		*status = MODE_CLOCK_HIGH;
>  		return 0;
>  	}
> 
> --
> 2.25.1

[PATCH v4 6/7] drm/i915/display: Program and enable the DP symbol based timing generator

[Arun R Murthy]

Program the 128 bit LL symbol Data M/N before the LINK_N write which
arms the double buffered update, the LL symbol HACT/HTOTAL/CHUNK_SIZE
along with the other transcoder timings, and enable the timing
generator via TRANSCONF.DP_Symbol_TG_Enable before the transcoder is
enabled.

v3: Remove redundant HAS_DP_SYMBOL_TG (Jani)
    Use intel_de_read64_2x32()

Bspec: 68849, 68922, 69961
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c     |   2 +
 drivers/gpu/drm/i915/display/intel_display.c | 103 ++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_display.h |   1 +
 3 files changed, 103 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a46ab5d3d70fc75c6975f46e14d1b0c24dc1ba5e..c814e0740aa064f56d844e304c0a93d1047475c6 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4083,6 +4083,7 @@ static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder,
 			REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl);
 
 	intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n);
+	intel_cpu_transcoder_get_llsym_m_n(crtc_state);
 	intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2);
 
 	crtc_state->enhanced_framing =
@@ -4119,6 +4120,7 @@ static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder,
 			REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl);
 
 	intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n);
+	intel_cpu_transcoder_get_llsym_m_n(crtc_state);
 
 	if (DISPLAY_VER(display) >= 11)
 		crtc_state->fec_enable =
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7caf5bee8718729667376b487b0584b47891f05a..1af1d589ec6410bbca3e3dcd3fe155da12ce7034 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -521,9 +521,14 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
 		return;
 	}
 
-	/* Wa_1409098942:adlp+ */
-	if (DISPLAY_VER(display) >= 13 &&
-	    new_crtc_state->dsc.compression_enable) {
+	/* The early pixel count is in symbols with the DP symbol TG, no scaling */
+	if (new_crtc_state->dp_symbol_tg.enable) {
+		val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
+		val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK,
+				      TRANSCONF_PIXEL_COUNT_SCALING_X1);
+	} else if (DISPLAY_VER(display) >= 13 &&
+		   new_crtc_state->dsc.compression_enable) {
+		/* Wa_1409098942:adlp+ */
 		val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
 		val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK,
 				      TRANSCONF_PIXEL_COUNT_SCALING_X4);
@@ -588,6 +593,14 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
 
 	if ((val & TRANSCONF_ENABLE) == 0)
 		intel_wait_for_pipe_off(old_crtc_state);
+
+	/* Disable the DP symbol based timing generator */
+	if (old_crtc_state->dp_symbol_tg.enable) {
+		intel_de_rmw(display, TRANSCONF(display, cpu_transcoder),
+			     TRANSCONF_DP_SYMBOL_TG_ENABLE, 0);
+		intel_de_write(display, TRANS_LLSYM_HACT(display, cpu_transcoder), 0);
+		intel_de_write(display, TRANS_LLSYM_HTOTAL(display, cpu_transcoder), 0);
+	}
 }
 
 u32 intel_plane_fb_max_stride(struct intel_display *display,
@@ -1683,6 +1696,52 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
 		     HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));
 }
 
+static void intel_cpu_transcoder_set_llsym_m_n(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder transcoder = crtc_state->cpu_transcoder;
+	const struct intel_dp_symbol_tg *tg = &crtc_state->dp_symbol_tg;
+
+	if (!tg->enable)
+		return;
+
+	/*
+	 * These are double buffered, updated by the LINK_N write in
+	 * intel_set_m_n(), so must be written before that.
+	 */
+	intel_de_write(display, DP_LLSYM_DATAM(display, transcoder, 0),
+		       lower_32_bits(tg->data_m[0]));
+	intel_de_write(display, DP_LLSYM_DATAM(display, transcoder, 1),
+		       upper_32_bits(tg->data_m[0]));
+	intel_de_write(display, DP_LLSYM_DATAM_EXT(display, transcoder, 0),
+		       lower_32_bits(tg->data_m[1]));
+	intel_de_write(display, DP_LLSYM_DATAM_EXT(display, transcoder, 1),
+		       upper_32_bits(tg->data_m[1]));
+	intel_de_write(display, DP_LLSYM_DATAN(display, transcoder, 0),
+		       lower_32_bits(tg->data_n[0]));
+	intel_de_write(display, DP_LLSYM_DATAN(display, transcoder, 1),
+		       upper_32_bits(tg->data_n[0]));
+	intel_de_write(display, DP_LLSYM_DATAN_EXT(display, transcoder, 0),
+		       lower_32_bits(tg->data_n[1]));
+	intel_de_write(display, DP_LLSYM_DATAN_EXT(display, transcoder, 1),
+		       upper_32_bits(tg->data_n[1]));
+}
+
+void intel_cpu_transcoder_get_llsym_m_n(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder transcoder = crtc_state->cpu_transcoder;
+	struct intel_dp_symbol_tg *tg = &crtc_state->dp_symbol_tg;
+
+	if (!tg->enable)
+		return;
+
+	tg->data_m[0] = intel_de_read64_2x32(display, DP_LLSYM_DATAM(display, transcoder, 0));
+	tg->data_m[1] = intel_de_read64_2x32(display, DP_LLSYM_DATAM_EXT(display, transcoder, 0));
+	tg->data_n[0] = intel_de_read64_2x32(display, DP_LLSYM_DATAN(display, transcoder, 0));
+	tg->data_n[1] = intel_de_read64_2x32(display, DP_LLSYM_DATAN_EXT(display, transcoder, 0));
+}
+
 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -1693,6 +1752,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
 		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
 					       &crtc_state->fdi_m_n);
 	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
+		intel_cpu_transcoder_set_llsym_m_n(crtc_state);
 		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
 					       &crtc_state->dp_m_n);
 		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
@@ -2929,6 +2989,19 @@ void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state,
 		intel_de_write(display, DP_MIN_HBLANK_CTL(transcoder),
 			       crtc_state->min_hblank);
 	}
+
+	if (crtc_state->dp_symbol_tg.enable &&
+	    transcoder != TRANSCODER_CMTG0 &&
+	    transcoder != TRANSCODER_CMTG1) {
+		const struct intel_dp_symbol_tg *tg = &crtc_state->dp_symbol_tg;
+
+		intel_de_write(display, TRANS_LLSYM_HACT(display, transcoder),
+			       TRANS_LLSYM_HACT_VAL(tg->hactive - 1));
+		intel_de_write(display, TRANS_LLSYM_HTOTAL(display, transcoder),
+			       TRANS_LLSYM_HTOTAL_VAL(tg->htotal - 1));
+		intel_de_write(display, TRANS_LLSYM_CHUNK_SIZE(display, transcoder),
+			       TRANS_LLSYM_CHUNK_SIZE_VAL(tg->chunk_size));
+	}
 }
 
 void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state,
@@ -3095,6 +3168,26 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
 	if (DISPLAY_VER(display) >= 30)
 		pipe_config->min_hblank = intel_de_read(display,
 							DP_MIN_HBLANK_CTL(cpu_transcoder));
+
+	if (HAS_DP_SYMBOL_TG(display)) {
+		tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
+
+		if (tmp & TRANSCONF_DP_SYMBOL_TG_ENABLE) {
+			struct intel_dp_symbol_tg *tg = &pipe_config->dp_symbol_tg;
+			u32 hact, htotal, chunk_size;
+
+			hact = intel_de_read(display, TRANS_LLSYM_HACT(display, cpu_transcoder));
+			htotal = intel_de_read(display,
+					       TRANS_LLSYM_HTOTAL(display, cpu_transcoder));
+			chunk_size = intel_de_read(display,
+						   TRANS_LLSYM_CHUNK_SIZE(display, cpu_transcoder));
+
+			tg->enable = true;
+			tg->hactive = REG_FIELD_GET(TRANS_LLSYM_HACT_MASK, hact) + 1;
+			tg->htotal = REG_FIELD_GET(TRANS_LLSYM_HTOTAL_MASK, htotal) + 1;
+			tg->chunk_size = REG_FIELD_GET(TRANS_LLSYM_CHUNK_SIZE_MASK, chunk_size);
+		}
+	}
 }
 
 static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
@@ -3419,6 +3512,10 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
 	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
 		val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW;
 
+	/* Must be set before the transcoder is enabled, so only on modeset */
+	if (crtc_state->dp_symbol_tg.enable)
+		val |= TRANSCONF_DP_SYMBOL_TG_ENABLE;
+
 	intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
 	intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index d53b7b4a80e75f8cb3a76d923d05648ffe505e2d..fa9ae8799a1999d9dd6a1f4e4d56983b6536ba26 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -446,6 +446,7 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
 				    enum transcoder cpu_transcoder,
 				    struct intel_link_m_n *m_n);
 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
+void intel_cpu_transcoder_get_llsym_m_n(struct intel_crtc_state *crtc_state);
 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);
 int intel_max_uncompressed_dotclock(struct intel_display *display);
 enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);

-- 
2.25.1