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* [RFC PATCH 0/3] drm/xe: Use MI_SEMAPHORE_WAIT_64 (Wa_16029281913)
@ 2026-11-03 12:37 tilak.tirumalesh.tangudu
  2026-11-03 12:37 ` [RFC PATCH 1/3] drm/xe: Add has_sem64 bit for MI_SEMAPHORE_WAIT_64 support tilak.tirumalesh.tangudu
                   ` (7 more replies)
  0 siblings, 8 replies; 11+ messages in thread
From: tilak.tirumalesh.tangudu @ 2026-11-03 12:37 UTC (permalink / raw)
  To: tilak.tirumalesh.tangudu, satyanarayana.k.v.p, intel-xe

From: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>

Wa_16029281913: MI_SEMAPHORE_WAIT has an issue on some Xe3p platforms.
The recommendation is to use the 64-bit MI_SEMAPHORE_WAIT_64 instruction
instead wherever the GT supports it.

Patch 1 adds the MI_SEMAPHORE_WAIT_64 instruction definition and a
has_sem64 bit to the graphics/media IP descriptors, resolved into
gt->info.has_sem64 at probe time. Every Xe3p platform supports it
except Graphics version 35.10 and Media version 35.00, which only gain
support at stepping B0, and the stepping exception is applied when
resolving the final value, so no caller needs to special-case it.

Patches 2 and 3 switch emit_fake_watchdog() and emit_ulls_postamble()
over to MI_SEMAPHORE_WAIT_64 on platforms that support it, falling back
to the existing 32-bit MI_SEMAPHORE_WAIT otherwise. ULLS_JOB_SIZE_DW is
bumped from 48 to 50 since the 64-bit postamble is 2 dwords wider and
the fixed-size ULLS job slot has no headroom to spare in the worst case
(SRIOV VF).

This series has not been validated on affected hardware.
Posting as RFC to get the approach reviewed while
this is tested. Will repost as a regular PATCH once
validated

Tangudu Tilak Tirumalesh (3):
  drm/xe: Add has_sem64 bit for MI_SEMAPHORE_WAIT_64 support
  drm/xe: Use MI_SEMAPHORE_WAIT_64 for fake watchdog where supported
  drm/xe: Use MI_SEMAPHORE_WAIT_64 in ULLS postamble where supported

 .../gpu/drm/xe/instructions/xe_mi_commands.h  |  6 ++
 drivers/gpu/drm/xe/xe_gt_types.h              |  2 +
 drivers/gpu/drm/xe/xe_pci.c                   | 20 ++++++-
 drivers/gpu/drm/xe/xe_pci_types.h             |  2 +
 drivers/gpu/drm/xe/xe_ring_ops.c              | 58 ++++++++++++++-----
 drivers/gpu/drm/xe/xe_ring_ops_types.h        |  5 +-
 6 files changed, 76 insertions(+), 17 deletions(-)

-- 
2.46.0


^ permalink raw reply	[flat|nested] 11+ messages in thread
* [RFC PATCH 0/3] drm/xe: Use MI_SEMAPHORE_WAIT_64 (Wa_16029281913)
@ 2026-11-02 10:00 tilak.tirumalesh.tangudu
  2026-11-02 10:00 ` [RFC PATCH 1/3] drm/xe: Add has_sem64 bit for MI_SEMAPHORE_WAIT_64 support tilak.tirumalesh.tangudu
  0 siblings, 1 reply; 11+ messages in thread
From: tilak.tirumalesh.tangudu @ 2026-11-02 10:00 UTC (permalink / raw)
  To: tilak.tirumalesh.tangudu, satyanarayana.k.v.p, intel-xe

From: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>

Wa_16029281913: MI_SEMAPHORE_WAIT has an issue on some Xe3p platforms.
The recommendation is to use the 64-bit MI_SEMAPHORE_WAIT_64 instruction
instead wherever the GT supports it.

Patch 1 adds the MI_SEMAPHORE_WAIT_64 instruction definition and a
has_sem64 bit to the graphics/media IP descriptors, resolved into
gt->info.has_sem64 at probe time. Every Xe3p platform supports it
except Graphics version 35.10 and Media version 35.00, which only gain
support at stepping B0; that exception is applied when resolving the
final value, so no caller needs to special-case it.

Patches 2 and 3 switch emit_fake_watchdog() and emit_ulls_postamble()
over to MI_SEMAPHORE_WAIT_64 on platforms that support it, falling back
to the existing 32-bit MI_SEMAPHORE_WAIT otherwise. ULLS_JOB_SIZE_DW is
bumped from 48 to 50 since the 64-bit postamble is 2 dwords wider and
the fixed-size ULLS job slot has no headroom to spare in the worst case
(SRIOV VF).

This series has not been validated on affected hardware.
Posting as RFC to get the approach reviewed while this is tested. Will 
repost as a regular PATCH once validated.


Tangudu Tilak Tirumalesh (3):
  drm/xe: Add has_sem64 bit for MI_SEMAPHORE_WAIT_64 support
  drm/xe: Use MI_SEMAPHORE_WAIT_64 for fake watchdog where supported
  drm/xe: Use MI_SEMAPHORE_WAIT_64 in ULLS postamble where supported

 .../gpu/drm/xe/instructions/xe_mi_commands.h  |  5 ++
 drivers/gpu/drm/xe/xe_gt_types.h              |  2 +
 drivers/gpu/drm/xe/xe_pci.c                   | 21 ++++++-
 drivers/gpu/drm/xe/xe_pci_types.h             |  2 +
 drivers/gpu/drm/xe/xe_ring_ops.c              | 55 ++++++++++++++-----
 drivers/gpu/drm/xe/xe_ring_ops_types.h        |  5 +-
 6 files changed, 73 insertions(+), 17 deletions(-)

-- 
2.46.0


^ permalink raw reply	[flat|nested] 11+ messages in thread

end of thread, other threads:[~2026-11-04  0:34 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-11-03 12:37 [RFC PATCH 0/3] drm/xe: Use MI_SEMAPHORE_WAIT_64 (Wa_16029281913) tilak.tirumalesh.tangudu
2026-11-03 12:37 ` [RFC PATCH 1/3] drm/xe: Add has_sem64 bit for MI_SEMAPHORE_WAIT_64 support tilak.tirumalesh.tangudu
2026-11-03 12:55   ` sashiko-bot
2026-11-03 12:37 ` [RFC PATCH 2/3] drm/xe: Use MI_SEMAPHORE_WAIT_64 for fake watchdog where supported tilak.tirumalesh.tangudu
2026-11-03 12:37 ` [RFC PATCH 3/3] drm/xe: Use MI_SEMAPHORE_WAIT_64 in ULLS postamble " tilak.tirumalesh.tangudu
2026-11-03 13:20 ` ✗ CI.checkpatch: warning for drm/xe: Use MI_SEMAPHORE_WAIT_64 (Wa_16029281913) (rev2) Patchwork
2026-11-03 13:22 ` ✓ CI.KUnit: success " Patchwork
2026-11-03 13:56 ` ✓ Xe.CI.BAT: " Patchwork
2026-11-03 23:05 ` [RFC PATCH 0/3] drm/xe: Use MI_SEMAPHORE_WAIT_64 (Wa_16029281913) Summers, Stuart
2026-11-04  0:34 ` ✗ Xe.CI.FULL: failure for drm/xe: Use MI_SEMAPHORE_WAIT_64 (Wa_16029281913) (rev2) Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2026-11-02 10:00 [RFC PATCH 0/3] drm/xe: Use MI_SEMAPHORE_WAIT_64 (Wa_16029281913) tilak.tirumalesh.tangudu
2026-11-02 10:00 ` [RFC PATCH 1/3] drm/xe: Add has_sem64 bit for MI_SEMAPHORE_WAIT_64 support tilak.tirumalesh.tangudu

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