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* [PATCH] drm/xe/xe3p: Bump offset for PPHWSP software scratch area
@ 2026-11-06 19:32 Gustavo Sousa
  2026-11-06 19:43 ` sashiko-bot
                   ` (5 more replies)
  0 siblings, 6 replies; 7+ messages in thread
From: Gustavo Sousa @ 2026-11-06 19:32 UTC (permalink / raw)
  To: intel-xe; +Cc: Gustavo Sousa

The Xe3p_LPG version 35.10 B0-step adds a new feature that allows
64-bit token for semaphore wait/signal commands.  With that, the
PPHWSP layout was modified to store extra information associated with
the new feature on a region that was previously considered part of the
scratch area of the PPHWSP.  Previously the sw scratch area started at
dword #34, and now that base has been pushed to dword #36.

It appears the value for LRC_PPHWSP_FLUSH_INVAL_SCRATCH_ADDR was meant
to point at the beginning of the sw scratch space, but, because the
hex 0x34 was used in the calculation instead of decimal 34, value is
actually pointing a little further.  As such, we accidentally
"future-proofed" our driver with respect to the layout changes
discussed earlier.

Now let's make this future-proofing intentional and use a buffer area
a bit bigger to allow future hardware extensions not to impact the
driver code for some time.  Use dword 128 as the base for the area
that is going to be used by the driver as scratch space.

Bspec: 60424
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_lrc.h | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h
index f2e829e62168..77949593562c 100644
--- a/drivers/gpu/drm/xe/xe_lrc.h
+++ b/drivers/gpu/drm/xe/xe_lrc.h
@@ -51,8 +51,23 @@ struct xe_lrc_snapshot {
 	u32 ctx_job_timestamp;
 };
 
-#define LRC_PPHWSP_FLUSH_INVAL_SCRATCH_ADDR (0x34 * 4)
-#define LRC_PPHWSP_PXP_INVAL_SCRATCH_ADDR (0x40 * 4)
+/*
+ * The PPHWSP software scratch area starts at different locations
+ * depending on the IP:
+ *
+ *  - Before graphics version 35.10 B0-step: dword #34.
+ *  - Starting with graphics version 35.10 B0: dword #36.
+ *
+ * For our driver usage, we use a custom base that fits all supported
+ * IPs and adds some extra buffer in case future hardware updates end
+ * up reserving extra dwords and further pushing the base of the
+ * scratch area.
+ */
+#define LRC_PPHWSP_SCRATCH_BASE			(128 * 4)
+#define LRC_PPHWSP_SCRATCH_DW(idx)		(LRC_PPHWSP_SCRATCH_BASE + (idx) * 4)
+
+#define LRC_PPHWSP_FLUSH_INVAL_SCRATCH_ADDR	LRC_PPHWSP_SCRATCH_DW(0)
+#define LRC_PPHWSP_PXP_INVAL_SCRATCH_ADDR	LRC_PPHWSP_SCRATCH_DW(12)
 
 #define LRC_WA_BB_SIZE SZ_4K
 

---
base-commit: e96f23b42352b7b9fea6bf92bceed052533fb98e
change-id: 20261106-xe3p-bump-pphwsp-scratch-bce9931eae4d

Best regards,
--  
Gustavo Sousa <gustavo.sousa@intel.com>


^ permalink raw reply related	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2026-11-09 22:28 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-11-06 19:32 [PATCH] drm/xe/xe3p: Bump offset for PPHWSP software scratch area Gustavo Sousa
2026-11-06 19:43 ` sashiko-bot
2026-11-06 19:45 ` ✓ CI.KUnit: success for " Patchwork
2026-11-06 20:16 ` [PATCH] " Umesh Nerlige Ramappa
2026-11-06 20:22 ` ✓ Xe.CI.BAT: success for " Patchwork
2026-11-08  0:34 ` ✓ Xe.CI.FULL: " Patchwork
2026-11-09 22:28 ` [PATCH] " Matt Roper

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