From: Breno Leitao <leitao@debian.org>
To: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
dave.hansen@linux.intel.com, leit@meta.com,
cascardo@canonical.com, hpa@zytor.com, jpoimboe@kernel.org,
peterz@infradead.org, x86@kernel.org, kexec@lists.infradead.org
Subject: Re: [PATCH] x86/bugs: Explicitly clear speculative MSR bits
Date: Tue, 22 Nov 2022 07:55:36 -0800 [thread overview]
Message-ID: <Y3zw+LK5C2esYU8o@gmail.com> (raw)
In-Reply-To: <20221121222031.uo2n7fv7ojusxvr4@desk>
On Mon, Nov 21, 2022 at 02:20:31PM -0800, Pawan Gupta wrote:
> On Sun, Nov 20, 2022 at 12:02:55PM +0000, Breno Leitao wrote:
...
> > diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
> > index 3e3230cccaa7..970b277d02a6 100644
> > --- a/arch/x86/kernel/cpu/bugs.c
> > +++ b/arch/x86/kernel/cpu/bugs.c
> > @@ -137,8 +137,16 @@ void __init check_bugs(void)
> > * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
> > * init code as it is not enumerated and depends on the family.
> > */
> > - if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
> > + if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
> > rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
> > + /*
> > + * Previously running software may have some controls turned ON.
> > + * Clear them and let kernel decide which controls to use.
> > + */
> > + x86_spec_ctrl_base &= ~SPEC_CTRL_MASK;
> > + wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
> > + }
> > +
>
> Nit, extra newline.
Thanks. If no other comment about the diff come until tomorrow, I will
send a v2 without this extra line.
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prev parent reply other threads:[~2022-11-22 17:00 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-18 18:21 [RFC PATCH] x86/bugs: Explicitly clear IBRS MSR bit Breno Leitao
2022-11-18 19:46 ` Pawan Gupta
2022-11-20 12:02 ` [PATCH] x86/bugs: Explicitly clear speculative MSR bits Breno Leitao
2022-11-21 22:20 ` Pawan Gupta
2022-11-22 15:55 ` Breno Leitao [this message]
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