* [PATCH RFC 0/3] arm64: disable/enable d-cache support for
@ 2015-05-04 13:02 Pratyush Anand
2015-05-04 13:02 ` [PATCH RFC 1/3] arm64: Add enable/disable d-cache support for purgatory Pratyush Anand
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: Pratyush Anand @ 2015-05-04 13:02 UTC (permalink / raw)
To: geoff; +Cc: Pratyush Anand, takahiro.akashi, kexec
These patches add support for enable/disable d cache support. It reduces
time for sha verification from more than 2 min to 3-4 sec on my
platform.
There are some of the observation which I am unable to explain.
* It takes around 18 sec when I boot a kexec kernel and around 3-4 sec
* when I boot a crash kernel. In case of kexec kernel start of 1st
* segment is at 0000004000280000 and, end of last segment is at
* 00000040029c0000. In case of crash kernel start of 1st segment is at
* 00000041b9080000 and, end of last segment is at 00000041f9000000.
Pratyush Anand (3):
arm64: Add enable/disable d-cache support for purgatory
arm64: Pass RAM boundary to purgatory
arm64: Enable/disable D-cache before/after sha verification
kexec/arch/arm64/include/types.h | 16 +++
kexec/arch/arm64/kexec-arm64.c | 16 ++-
purgatory/arch/arm64/Makefile | 1 +
purgatory/arch/arm64/cache.S | 222 +++++++++++++++++++++++++++++++++
purgatory/arch/arm64/cache.h | 42 +++++++
purgatory/arch/arm64/entry.S | 10 ++
purgatory/arch/arm64/purgatory-arm64.c | 12 ++
7 files changed, 318 insertions(+), 1 deletion(-)
create mode 100644 kexec/arch/arm64/include/types.h
create mode 100644 purgatory/arch/arm64/cache.S
create mode 100644 purgatory/arch/arm64/cache.h
--
2.1.0
_______________________________________________
kexec mailing list
kexec@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/kexec
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH RFC 1/3] arm64: Add enable/disable d-cache support for purgatory 2015-05-04 13:02 [PATCH RFC 0/3] arm64: disable/enable d-cache support for Pratyush Anand @ 2015-05-04 13:02 ` Pratyush Anand 2015-05-04 13:02 ` [PATCH RFC 2/3] arm64: Pass RAM boundary to purgatory Pratyush Anand ` (3 subsequent siblings) 4 siblings, 0 replies; 11+ messages in thread From: Pratyush Anand @ 2015-05-04 13:02 UTC (permalink / raw) To: geoff; +Cc: Pratyush Anand, takahiro.akashi, kexec This patch adds support to enable/disable d-cache, which can be used for faster purgatory sha256 verification. Signed-off-by: Pratyush Anand <panand@redhat.com> --- purgatory/arch/arm64/Makefile | 1 + purgatory/arch/arm64/cache.S | 222 ++++++++++++++++++++++++++++++++++++++++++ purgatory/arch/arm64/cache.h | 42 ++++++++ 3 files changed, 265 insertions(+) create mode 100644 purgatory/arch/arm64/cache.S create mode 100644 purgatory/arch/arm64/cache.h diff --git a/purgatory/arch/arm64/Makefile b/purgatory/arch/arm64/Makefile index 5d35161fc5f4..04fef16476fb 100644 --- a/purgatory/arch/arm64/Makefile +++ b/purgatory/arch/arm64/Makefile @@ -12,6 +12,7 @@ arm64_PURGATORY_EXTRA_CFLAGS = \ arm64_PURGATORY_SRCS += \ purgatory/arch/arm64/entry.S \ + purgatory/arch/arm64/cache.S \ purgatory/arch/arm64/purgatory-arm64.c dist += \ diff --git a/purgatory/arch/arm64/cache.S b/purgatory/arch/arm64/cache.S new file mode 100644 index 000000000000..6bbdeacdab47 --- /dev/null +++ b/purgatory/arch/arm64/cache.S @@ -0,0 +1,222 @@ +/* + * Cache maintenance + * Some of the routine has been copied from Linux Kernel, therefore + * copying the license as well. + * + * Copyright (C) 2001 Deep Blue Solutions Ltd. + * Copyright (C) 2012 ARM Ltd. + * Copyright (C) 2015 Pratyush Anand <panand@redhat.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "cache.h" + +/* + * dcache_line_size - get the minimum D-cache line size from the CTR register. + */ + .macro dcache_line_size, reg, tmp + mrs \tmp, ctr_el0 // read CTR + ubfm \tmp, \tmp, #16, #19 // cache line size encoding + mov \reg, #4 // bytes per word + lsl \reg, \reg, \tmp // actual cache line size + .endm + +/* + * __inval_cache_range(start, end) + * - start - start address of region + * - end - end address of region + */ +__inval_cache_range: + dcache_line_size x2, x3 + sub x3, x2, #1 + tst x1, x3 // end cache line aligned? + bic x1, x1, x3 + b.eq 1f + dc civac, x1 // clean & invalidate D / U line +1: tst x0, x3 // start cache line aligned? + bic x0, x0, x3 + b.eq 2f + dc civac, x0 // clean & invalidate D / U line + b 3f +2: dc ivac, x0 // invalidate D / U line +3: add x0, x0, x2 + cmp x0, x1 + b.lo 2b + dsb sy + ret +/* + * __flush_dcache_range(start, end) + * - start - start address of region + * - end - end address of region + * + */ +__flush_dcache_range: + dcache_line_size x2, x3 + sub x3, x2, #1 + bic x0, x0, x3 +1: dc civac, x0 // clean & invalidate D line / unified line + add x0, x0, x2 + cmp x0, x1 + b.lo 1b + dsb sy + ret + +/* + * enable_dcache(start, end, page_table) + * - start - start address of ram + * - end - end address of ram + * - page_table - base of page table + */ +.globl enable_dcache +enable_dcache: + stp x6, x7, [sp,#-16]! + stp x16, x17, [sp,#-16]! + stp x18, x19, [sp,#-16]! + + /* save args */ + mov x16, x0 /* first segment start */ + mov x17, x1 /* last segment end */ + mov x18, x2 /* page table */ + mov x19, x30 /* save ret addr */ + + /* + * Invalidate the page tables to avoid potential + * dirty cache lines being evicted. + */ + mov x0, x18 + add x1, x0, #PAGE_TABLE_SIZE + bl __inval_cache_range + + /* + * Clear the page tables. + */ + mov x0, x18 + add x1, x0, #PAGE_TABLE_SIZE +1: stp xzr, xzr, [x0], #16 + stp xzr, xzr, [x0], #16 + stp xzr, xzr, [x0], #16 + stp xzr, xzr, [x0], #16 + cmp x0, x1 + b.lo 1b + + /* + * Create the identity mapping. + */ + ldr x6, =SECTION_SHIFT + ldr x7, =MM_MMUFLAGS + lsr x0, x16, x6 //first index + lsr x1, x17, x6 //last index + +next_sect: + lsl x2, x0, x6 //section + orr x2, x2, x7 + str x2, [x18, x0, lsl #3] + add x0, x0, #1 + cmp x0, x1 + b.ls next_sect + + /* + * Since the page tables have been populated with non-cacheable + * accesses (MMU disabled), invalidate the idmap page + * tables again to remove any speculatively loaded cache lines. + */ + mov x0, x18 + add x1, x0, #PAGE_TABLE_SIZE + bl __inval_cache_range + + mrs x0, CurrentEL + cmp x0, #12 //EL3 + b.eq set_el3 + cmp x0, #8 //EL2 + b.eq set_el2 + cmp x0, #4 //EL1 + b.eq set_el1 + b done_enable + +set_el1: + msr ttbr0_el1, x18 + ldr x0, =TCR_FLAGS + orr x0, x0, #TCR_EL1_IPS_BITS + msr tcr_el1, x0 + ldr x0, =MEMORY_ATTRIBUTES + msr mair_el1, x0 + mrs x0, sctlr_el1 + orr x0, x0, #CR_M + orr x0, x0, #CR_C + msr sctlr_el1, x0 + b done_enable +set_el2: + msr ttbr0_el2, x18 + ldr x0, =TCR_FLAGS + orr x0, x0, #TCR_EL2_IPS_BITS + msr tcr_el2, x0 + ldr x0, =MEMORY_ATTRIBUTES + msr mair_el2, x0 + mrs x0, sctlr_el2 + orr x0, x0, #CR_M + orr x0, x0, #CR_C + msr sctlr_el2, x0 + b done_enable +set_el3: + msr ttbr0_el3, x18 + ldr x0, =TCR_FLAGS + orr x0, x0, #TCR_EL3_IPS_BITS + msr tcr_el3, x0 + ldr x0, =MEMORY_ATTRIBUTES + msr mair_el3, x0 + mrs x0, sctlr_el3 + orr x0, x0, #CR_M + orr x0, x0, #CR_C + msr sctlr_el3, x0 +done_enable: + + mov x30, x19 + ldp x18, x19, [sp],#16 + ldp x16, x17, [sp],#16 + ldp x6, x7, [sp],#16 + + ret + +.globl disable_dcache +disable_dcache: + stp x5, x30, [sp,#-16]! + mrs x5, CurrentEL + cmp x5, #12 //EL3 + b.eq disable_el3 + cmp x5, #8 //EL2 + b.eq disable_el2 + cmp x5, #4 //EL1 + b.eq disable_el1 + b done_disable +disable_el3: + mrs x5, sctlr_el3 + bic x5, x2, #CR_M + bic x5, x2, #CR_C + msr sctlr_el3, x5 + b done_disable +disable_el2: + mrs x5, sctlr_el2 + bic x5, x2, #CR_M + bic x5, x2, #CR_C + msr sctlr_el2, x5 + b done_disable +disable_el1: + mrs x5, sctlr_el1 + bic x5, x2, #CR_M + bic x5, x2, #CR_C + msr sctlr_el1, x5 +done_disable: + bl __flush_dcache_range + ldp x5, x30, [sp],#16 + ret diff --git a/purgatory/arch/arm64/cache.h b/purgatory/arch/arm64/cache.h new file mode 100644 index 000000000000..3ca1d7f9a5ca --- /dev/null +++ b/purgatory/arch/arm64/cache.h @@ -0,0 +1,42 @@ +#ifndef __CACHE_H__ +#define __CACHE_H__ + +#define VA_BITS 42 +#define SECTION_SHIFT 29 +#define PAGE_TABLE_SIZE (1 << (VA_BITS - SECTION_SHIFT + 3)) + +#define TCR_TG0_64K (1 << 14) +#define TCR_SHARED_NON (0 << 12) +#define TCR_ORGN_WBWA (1 << 10) +#define TCR_IRGN_WBWA (1 << 8) +#define TCR_T0SZ(x) ((64 - (x)) << 0) +#define TCR_EL1_IPS_BITS (3 << 32) /* 42 bits physical address */ +#define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */ +#define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */ + +#define TCR_FLAGS (TCR_TG0_64K | TCR_SHARED_NON | TCR_ORGN_WBWA | \ + TCR_IRGN_WBWA | TCR_T0SZ(VA_BITS)) + +#define MT_DEVICE_NGNRNE 0 +#define MT_DEVICE_NGNRE 1 +#define MT_DEVICE_GRE 2 +#define MT_NORMAL_NC 3 +#define MT_NORMAL 4 + +#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE*8)) | \ + (0x04 << (MT_DEVICE_NGNRE*8)) | \ + (0x0c << (MT_DEVICE_GRE*8)) | \ + (0x44 << (MT_NORMAL_NC*8)) | \ + (0xff << (MT_NORMAL*8))) + +#define CR_M (1 << 0) /* MMU enable */ +#define CR_C (1 << 2) /* Dcache enable */ + + +#define PMD_TYPE_SECT (1 << 0) +#define PMD_SECT_AF (1 << 10) +#define PMD_ATTRINDX(t) ((t) << 2) +#define PMD_FLAGS (PMD_TYPE_SECT | PMD_SECT_AF) +#define MM_MMUFLAGS PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS + +#endif -- 2.1.0 _______________________________________________ kexec mailing list kexec@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kexec ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH RFC 2/3] arm64: Pass RAM boundary to purgatory 2015-05-04 13:02 [PATCH RFC 0/3] arm64: disable/enable d-cache support for Pratyush Anand 2015-05-04 13:02 ` [PATCH RFC 1/3] arm64: Add enable/disable d-cache support for purgatory Pratyush Anand @ 2015-05-04 13:02 ` Pratyush Anand 2015-05-04 13:02 ` [PATCH RFC 3/3] arm64: Enable/disable D-cache before/after sha verification Pratyush Anand ` (2 subsequent siblings) 4 siblings, 0 replies; 11+ messages in thread From: Pratyush Anand @ 2015-05-04 13:02 UTC (permalink / raw) To: geoff; +Cc: Pratyush Anand, takahiro.akashi, kexec RAM boundary which includes all the sections is needed for creating identity page mapping and to enable d-cache for those areas. Signed-off-by: Pratyush Anand <panand@redhat.com> --- kexec/arch/arm64/include/types.h | 16 ++++++++++++++++ kexec/arch/arm64/kexec-arm64.c | 16 +++++++++++++++- purgatory/arch/arm64/entry.S | 10 ++++++++++ 3 files changed, 41 insertions(+), 1 deletion(-) create mode 100644 kexec/arch/arm64/include/types.h diff --git a/kexec/arch/arm64/include/types.h b/kexec/arch/arm64/include/types.h new file mode 100644 index 000000000000..08f833a6d585 --- /dev/null +++ b/kexec/arch/arm64/include/types.h @@ -0,0 +1,16 @@ +#ifndef _TYPES_H_ +#define _TYPES_H_ + +#define min(x,y) ({ \ + typeof(x) _x = (x); \ + typeof(y) _y = (y); \ + (void) (&_x == &_y); \ + _x < _y ? _x : _y; }) + +#define max(x,y) ({ \ + typeof(x) _x = (x); \ + typeof(y) _y = (y); \ + (void) (&_x == &_y); \ + _x > _y ? _x : _y; }) + +#endif /* _TYPES_H_ */ diff --git a/kexec/arch/arm64/kexec-arm64.c b/kexec/arch/arm64/kexec-arm64.c index 12c589f8001c..8ce4a61fc9c2 100644 --- a/kexec/arch/arm64/kexec-arm64.c +++ b/kexec/arch/arm64/kexec-arm64.c @@ -28,6 +28,7 @@ #include "fs2dt.h" #include "kexec-syscall.h" #include "arch/options.h" +#include "types.h" /* Global varables the core kexec routines expect. */ @@ -588,9 +589,11 @@ static uint64_t read_sink(const char *command_line) int arm64_load_other_segments(struct kexec_info *info, unsigned long kernel_entry, char *option) { - int result; + int result, i; struct mem_ehdr ehdr; unsigned long dtb_base; + unsigned long arm64_ram_start = -1; + unsigned long arm64_ram_end = 0; unsigned long hole_min, hole_max; char *initrd_buf = NULL; uint64_t purgatory_sink; @@ -720,6 +723,17 @@ int arm64_load_other_segments(struct kexec_info *info, elf_rel_set_symbol(&info->rhdr, "arm64_dtb_addr", &dtb_base, sizeof(dtb_base)); + for (i = 0; i < info->nr_segments; i++) { + arm64_ram_start = min(arm64_ram_start, + (unsigned long)info->segment[i].mem); + arm64_ram_end = max(arm64_ram_end, + ((unsigned long)info->segment[i].mem + + info->segment[i].memsz)); + } + elf_rel_set_symbol(&info->rhdr, "arm64_ram_start", + &arm64_ram_start, sizeof(arm64_ram_start)); + elf_rel_set_symbol(&info->rhdr, "arm64_ram_end", + &arm64_ram_end, sizeof(arm64_ram_end)); } return 0; diff --git a/purgatory/arch/arm64/entry.S b/purgatory/arch/arm64/entry.S index 140e91d87ab1..0713ccdec4ad 100644 --- a/purgatory/arch/arm64/entry.S +++ b/purgatory/arch/arm64/entry.S @@ -52,3 +52,13 @@ size arm64_kernel_entry arm64_dtb_addr: .quad 0 size arm64_dtb_addr + +.globl arm64_ram_start +arm64_ram_start: + .quad 0 +size arm64_ram_start + +.globl arm64_ram_end +arm64_ram_end: + .quad 0 +size arm64_ram_end -- 2.1.0 _______________________________________________ kexec mailing list kexec@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kexec ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH RFC 3/3] arm64: Enable/disable D-cache before/after sha verification 2015-05-04 13:02 [PATCH RFC 0/3] arm64: disable/enable d-cache support for Pratyush Anand 2015-05-04 13:02 ` [PATCH RFC 1/3] arm64: Add enable/disable d-cache support for purgatory Pratyush Anand 2015-05-04 13:02 ` [PATCH RFC 2/3] arm64: Pass RAM boundary to purgatory Pratyush Anand @ 2015-05-04 13:02 ` Pratyush Anand 2015-05-04 14:41 ` [PATCH RFC 0/3] arm64: disable/enable d-cache support for Pratyush Anand 2015-05-06 17:05 ` Geoff Levand 4 siblings, 0 replies; 11+ messages in thread From: Pratyush Anand @ 2015-05-04 13:02 UTC (permalink / raw) To: geoff; +Cc: Pratyush Anand, takahiro.akashi, kexec Enable D cache before SHA verification and disable it before switching to kernel. Since we only map RAM area, therefore currently no printf is allowed between d-cache enable and disable events. Identity mapping for port area with device type memory attributes need to be created for printf to work. Signed-off-by: Pratyush Anand <panand@redhat.com> --- purgatory/arch/arm64/purgatory-arm64.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/purgatory/arch/arm64/purgatory-arm64.c b/purgatory/arch/arm64/purgatory-arm64.c index 3a1c9243bfa2..e045039039b6 100644 --- a/purgatory/arch/arm64/purgatory-arm64.c +++ b/purgatory/arch/arm64/purgatory-arm64.c @@ -2,6 +2,7 @@ * ARM64 purgatory. */ +#include "cache.h" #include <stdint.h> #include <purgatory.h> @@ -10,6 +11,8 @@ extern uint32_t *arm64_sink; extern void (*arm64_kernel_entry)(uint64_t); extern uint64_t arm64_dtb_addr; +extern uint64_t arm64_ram_start; +extern uint64_t arm64_ram_end; static void wait_for_xmit_complete(void) { @@ -44,14 +47,23 @@ void putchar(int ch) } } +uint64_t page_table[PAGE_TABLE_SIZE / sizeof(uint64_t)] __attribute__ ((aligned (PAGE_TABLE_SIZE))) = { }; +extern void enable_dcache(uint64_t , uint64_t , uint64_t *); +extern void disable_dcache(uint64_t , uint64_t); + void setup_arch(void) { printf("purgatory: kernel_entry: %lx\n", (unsigned long)arm64_kernel_entry); printf("purgatory: dtb: %lx\n", arm64_dtb_addr); + printf("purgatory: RAM start: %lx\n", arm64_ram_start); + printf("purgatory: RAM end: %lx\n", arm64_ram_end); + + enable_dcache(arm64_ram_start, arm64_ram_end, page_table); } void post_verification_setup_arch(void) { + disable_dcache(arm64_ram_start, arm64_ram_end); arm64_kernel_entry(arm64_dtb_addr); } -- 2.1.0 _______________________________________________ kexec mailing list kexec@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kexec ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH RFC 0/3] arm64: disable/enable d-cache support for 2015-05-04 13:02 [PATCH RFC 0/3] arm64: disable/enable d-cache support for Pratyush Anand ` (2 preceding siblings ...) 2015-05-04 13:02 ` [PATCH RFC 3/3] arm64: Enable/disable D-cache before/after sha verification Pratyush Anand @ 2015-05-04 14:41 ` Pratyush Anand 2015-05-06 17:05 ` Geoff Levand 4 siblings, 0 replies; 11+ messages in thread From: Pratyush Anand @ 2015-05-04 14:41 UTC (permalink / raw) To: geoff; +Cc: takahiro.akashi, kexec On Monday 04 May 2015 06:32 PM, Pratyush Anand wrote: > These patches add support for enable/disable d cache support. It reduces > time for sha verification from more than 2 min to 3-4 sec on my > platform. > There are some of the observation which I am unable to explain. > * It takes around 18 sec when I boot a kexec kernel and around 3-4 sec > * when I boot a crash kernel. In case of kexec kernel start of 1st > * segment is at 0000004000280000 and, end of last segment is at > * 00000040029c0000. In case of crash kernel start of 1st segment is at > * 00000041b9080000 and, end of last segment is at 00000041f9000000. There is one more observation which is not explainable :( While executing a secondary kernel using kexec -e, if sha256_process() function is aligned at offset 256, it takes 18 sec else it takes double ie 36 sec. # objdump -d purgatory/purgatory.ro | grep sha256_process 0000000000001300 <sha256_process>: -> takes 18 sec If because of some changes in code, this function shifts a bit # objdump -d purgatory/purgatory.ro | grep sha256_process 0000000000001310 <sha256_process>: -> takes 36 sec. So, "__attribute__ ((aligned (256))) void sha256_process( sha256_context *ctx, const uint8_t data[64] )" guarantees constant execution time, but how can this be justified? ~Pratyush _______________________________________________ kexec mailing list kexec@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kexec ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH RFC 0/3] arm64: disable/enable d-cache support for 2015-05-04 13:02 [PATCH RFC 0/3] arm64: disable/enable d-cache support for Pratyush Anand ` (3 preceding siblings ...) 2015-05-04 14:41 ` [PATCH RFC 0/3] arm64: disable/enable d-cache support for Pratyush Anand @ 2015-05-06 17:05 ` Geoff Levand 2015-05-06 17:37 ` Pratyush Anand 4 siblings, 1 reply; 11+ messages in thread From: Geoff Levand @ 2015-05-06 17:05 UTC (permalink / raw) To: Pratyush Anand; +Cc: takahiro.akashi, kexec Hi, I don't really like the idea of doing cache operations in purgatory. For fast reboot we have the --lite option to kexec, which will skip the digest calculations. Your 2 minutes seems like a long time. Is this seen on other platforms? -Geoff On Mon, 2015-05-04 at 18:32 +0530, Pratyush Anand wrote: > These patches add support for enable/disable d cache support. It reduces > time for sha verification from more than 2 min to 3-4 sec on my > platform. > There are some of the observation which I am unable to explain. > * It takes around 18 sec when I boot a kexec kernel and around 3-4 sec > * when I boot a crash kernel. In case of kexec kernel start of 1st > * segment is at 0000004000280000 and, end of last segment is at > * 00000040029c0000. In case of crash kernel start of 1st segment is at > * 00000041b9080000 and, end of last segment is at 00000041f9000000. > > Pratyush Anand (3): > arm64: Add enable/disable d-cache support for purgatory > arm64: Pass RAM boundary to purgatory > arm64: Enable/disable D-cache before/after sha verification > > kexec/arch/arm64/include/types.h | 16 +++ > kexec/arch/arm64/kexec-arm64.c | 16 ++- > purgatory/arch/arm64/Makefile | 1 + > purgatory/arch/arm64/cache.S | 222 +++++++++++++++++++++++++++++++++ > purgatory/arch/arm64/cache.h | 42 +++++++ > purgatory/arch/arm64/entry.S | 10 ++ > purgatory/arch/arm64/purgatory-arm64.c | 12 ++ > 7 files changed, 318 insertions(+), 1 deletion(-) > create mode 100644 kexec/arch/arm64/include/types.h > create mode 100644 purgatory/arch/arm64/cache.S > create mode 100644 purgatory/arch/arm64/cache.h > _______________________________________________ kexec mailing list kexec@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kexec ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH RFC 0/3] arm64: disable/enable d-cache support for 2015-05-06 17:05 ` Geoff Levand @ 2015-05-06 17:37 ` Pratyush Anand 2015-05-07 4:25 ` AKASHI Takahiro 0 siblings, 1 reply; 11+ messages in thread From: Pratyush Anand @ 2015-05-06 17:37 UTC (permalink / raw) To: Geoff Levand; +Cc: takahiro.akashi, kexec Hi Geoff, On Wednesday 06 May 2015 10:35 PM, Geoff Levand wrote: > Your 2 minutes seems like a long time. Is this seen on other platforms? At least it is seen on two different HW platforms I had tested with. I do not know about other. It would be nice if somebody else who is using kexec on HW platform can report their execution time. ~Pratyush _______________________________________________ kexec mailing list kexec@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kexec ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH RFC 0/3] arm64: disable/enable d-cache support for 2015-05-06 17:37 ` Pratyush Anand @ 2015-05-07 4:25 ` AKASHI Takahiro 2015-05-07 4:54 ` Pratyush Anand 0 siblings, 1 reply; 11+ messages in thread From: AKASHI Takahiro @ 2015-05-07 4:25 UTC (permalink / raw) To: Pratyush Anand, Geoff Levand; +Cc: kexec Geoff, Pratyush On 05/07/2015 02:37 AM, Pratyush Anand wrote: > Hi Geoff, > > On Wednesday 06 May 2015 10:35 PM, Geoff Levand wrote: >> Your 2 minutes seems like a long time. Is this seen on other platforms? > > At least it is seen on two different HW platforms I had tested with. I do not know about other. > > It would be nice if somebody else who is using kexec on HW platform can report their execution time. On my HW, it took about 42secs before showing extra boot messages after "I'm in purgatory." -Takahiro AKASHI > ~Pratyush _______________________________________________ kexec mailing list kexec@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kexec ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH RFC 0/3] arm64: disable/enable d-cache support for 2015-05-07 4:25 ` AKASHI Takahiro @ 2015-05-07 4:54 ` Pratyush Anand 2015-05-07 5:08 ` AKASHI Takahiro 2015-05-07 15:32 ` Geoff Levand 0 siblings, 2 replies; 11+ messages in thread From: Pratyush Anand @ 2015-05-07 4:54 UTC (permalink / raw) To: AKASHI Takahiro, Geoff Levand; +Cc: kexec On Thursday 07 May 2015 09:55 AM, AKASHI Takahiro wrote: > Geoff, Pratyush > > On 05/07/2015 02:37 AM, Pratyush Anand wrote: >> Hi Geoff, >> >> On Wednesday 06 May 2015 10:35 PM, Geoff Levand wrote: >>> Your 2 minutes seems like a long time. Is this seen on other platforms? >> >> At least it is seen on two different HW platforms I had tested with. I >> do not know about other. >> >> It would be nice if somebody else who is using kexec on HW platform >> can report their execution time. > > On my HW, it took about 42secs before showing extra boot messages after > "I'm in purgatory." > It would also depend on the size of different segments (mainly kernel and initrd) on which sha256 is calculated. What are the size of binaries in your case? In my case: segment[0].memsz = 0x10e0000 // kernel segment[1].memsz = 0x1910000 // initrd segment[2].memsz = 0x10000 // dtb segment[3].memsz = 0x40000 // purgatory, not included in sha256 segment[4].memsz = 0x10000 // elf core hdr @Geoff: Do you see any specific side effect for enabling D-cache in purgatory, other than the fact that it increases size of purgatory? May be we can keep an user option to select/not select d-cache enabling. _______________________________________________ kexec mailing list kexec@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kexec ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH RFC 0/3] arm64: disable/enable d-cache support for 2015-05-07 4:54 ` Pratyush Anand @ 2015-05-07 5:08 ` AKASHI Takahiro 2015-05-07 15:32 ` Geoff Levand 1 sibling, 0 replies; 11+ messages in thread From: AKASHI Takahiro @ 2015-05-07 5:08 UTC (permalink / raw) To: Pratyush Anand, Geoff Levand; +Cc: kexec On 05/07/2015 01:54 PM, Pratyush Anand wrote: > > > On Thursday 07 May 2015 09:55 AM, AKASHI Takahiro wrote: >> Geoff, Pratyush >> >> On 05/07/2015 02:37 AM, Pratyush Anand wrote: >>> Hi Geoff, >>> >>> On Wednesday 06 May 2015 10:35 PM, Geoff Levand wrote: >>>> Your 2 minutes seems like a long time. Is this seen on other platforms? >>> >>> At least it is seen on two different HW platforms I had tested with. I >>> do not know about other. >>> >>> It would be nice if somebody else who is using kexec on HW platform >>> can report their execution time. >> >> On my HW, it took about 42secs before showing extra boot messages after >> "I'm in purgatory." >> > > It would also depend on the size of different segments (mainly kernel and initrd) on which sha256 is calculated. What > are the size of binaries in your case? segment[0].memsz = 0x877000 // kernel segment[1].memsz = 0x4000 // dtb segment[2].memsz = 0x7000 // purgatory no initrd under normal kexec. > In my case: > > segment[0].memsz = 0x10e0000 // kernel > segment[1].memsz = 0x1910000 // initrd > segment[2].memsz = 0x10000 // dtb > segment[3].memsz = 0x40000 // purgatory, not included in sha256 > segment[4].memsz = 0x10000 // elf core hdr Your numbers have extra "0" :) > @Geoff: Do you see any specific side effect for enabling D-cache in purgatory, other than the fact that it increases > size of purgatory? May be we can keep an user option to select/not select d-cache enabling. The discussions should be Cc'd to linux-arm-kernel (or at least, arm64 maintainers). -Takahiro AKASHI _______________________________________________ kexec mailing list kexec@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kexec ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH RFC 0/3] arm64: disable/enable d-cache support for 2015-05-07 4:54 ` Pratyush Anand 2015-05-07 5:08 ` AKASHI Takahiro @ 2015-05-07 15:32 ` Geoff Levand 1 sibling, 0 replies; 11+ messages in thread From: Geoff Levand @ 2015-05-07 15:32 UTC (permalink / raw) To: Pratyush Anand; +Cc: AKASHI Takahiro, kexec On Thu, 2015-05-07 at 10:24 +0530, Pratyush Anand wrote: > @Geoff: Do you see any specific side effect for enabling D-cache in > purgatory, other than the fact that it increases size of purgatory? May > be we can keep an user option to select/not select d-cache enabling. The checks in purgatory are for kdump, which won't be a regularly used feature. I don't want to add the complexity to save one minute for someone who will likely spend several hours working on a problem that triggered a kdump. -Geoff _______________________________________________ kexec mailing list kexec@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kexec ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2015-05-07 15:32 UTC | newest] Thread overview: 11+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2015-05-04 13:02 [PATCH RFC 0/3] arm64: disable/enable d-cache support for Pratyush Anand 2015-05-04 13:02 ` [PATCH RFC 1/3] arm64: Add enable/disable d-cache support for purgatory Pratyush Anand 2015-05-04 13:02 ` [PATCH RFC 2/3] arm64: Pass RAM boundary to purgatory Pratyush Anand 2015-05-04 13:02 ` [PATCH RFC 3/3] arm64: Enable/disable D-cache before/after sha verification Pratyush Anand 2015-05-04 14:41 ` [PATCH RFC 0/3] arm64: disable/enable d-cache support for Pratyush Anand 2015-05-06 17:05 ` Geoff Levand 2015-05-06 17:37 ` Pratyush Anand 2015-05-07 4:25 ` AKASHI Takahiro 2015-05-07 4:54 ` Pratyush Anand 2015-05-07 5:08 ` AKASHI Takahiro 2015-05-07 15:32 ` Geoff Levand
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox