From: Ram Pai <linuxram@us.ibm.com>
To: kvm-ppc@vger.kernel.org
Subject: [PATCH 03/13] KVM: PPC: Ultravisor: Introduce the MSR_S bit
Date: Tue, 22 Jan 2019 15:59:34 +0000 [thread overview]
Message-ID: <1548172784-27414-4-git-send-email-linuxram@us.ibm.com> (raw)
From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
MSR_S bit enables access to secure memory.
Signed-off-by: Ram Pai <linuxram@us.ibm.com>
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 1c98ef1..3c3588a 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -38,6 +38,7 @@
#define MSR_TM_LG 32 /* Trans Mem Available */
#define MSR_VEC_LG 25 /* Enable AltiVec */
#define MSR_VSX_LG 23 /* Enable VSX */
+#define MSR_S_LG 22 /* Secure VM bit */
#define MSR_POW_LG 18 /* Enable Power Management */
#define MSR_WE_LG 18 /* Wait State Enable */
#define MSR_TGPR_LG 17 /* TLB Update registers in use */
@@ -71,11 +72,13 @@
#define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */
#define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */
#define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */
+#define MSR_S __MASK(MSR_S_LG) /* Secure state */
#else
/* so tests for these bits fail on 32-bit */
#define MSR_SF 0
#define MSR_ISF 0
#define MSR_HV 0
+#define MSR_S 0
#endif
/*
--
1.8.3.1
next reply other threads:[~2019-01-22 15:59 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-22 15:59 Ram Pai [this message]
2019-01-22 23:36 ` [PATCH 03/13] KVM: PPC: Ultravisor: Introduce the MSR_S bit Paul Mackerras
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