* [kvm-ppc-devel] [PATCH 4 of 4] [qemu ppc pci] Emulate the
@ 2008-03-28 2:49 Hollis Blanchard
2008-03-28 9:10 ` Christian Ehrhardt
0 siblings, 1 reply; 2+ messages in thread
From: Hollis Blanchard @ 2008-03-28 2:49 UTC (permalink / raw)
To: kvm-ppc
6 files changed, 491 insertions(+), 1 deletion(-)
qemu/hw/ppc440.c | 27 +++
qemu/hw/ppc440.h | 1
qemu/hw/ppc440_bamboo.c | 15 +
qemu/hw/ppc4xx.h | 41 +++++
qemu/hw/ppc4xx_devs.c | 369 +++++++++++++++++++++++++++++++++++++++++++++++
qemu/pc-bios/bamboo.dts | 39 ++++
# HG changeset patch
# User Hollis Blanchard <hollisb@us.ibm.com>
# Date 1206672309 18000
# Branch merge
# Node ID e0e325f28fdb922e2911a383a96ce7d66c800e72
# Parent 5c61aade5a1cfeecc270f4c0c176709a3a611e87
[qemu ppc pci] Emulate the PCI(-legacy) controller found on some 440 SoCs.
The physical memory map used here is hardcoded to match 440EP, but it could
be abstracted in the future.
Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
diff --git a/qemu/hw/ppc440.c b/qemu/hw/ppc440.c
--- a/qemu/hw/ppc440.c
+++ b/qemu/hw/ppc440.c
@@ -8,17 +8,32 @@
*
*/
+
+#include "hw.h"
+#include "hw/isa.h"
#include "ppc440.h"
+
+#define PPC440EP_PCI_CONFIG 0xeec00000
+#define PPC440EP_PCI_INTACK 0xeed00000
+#define PPC440EP_PCI_SPECIAL 0xeed00000
+#define PPC440EP_PCI_REGS 0xef400000
+#define PPC440EP_PCI_IO 0xe8000000
+#define PPC440EP_PCI_IOLEN 0x10000
+#define PPC440EP_PCI_MEM 0xa0000000
+#define PPC440EP_PCI_MEMLEN 0x20000000
+
void ppc440ep_init(CPUState *env,
target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2],
qemu_irq **picp,
+ ppc4xx_pci_t **pcip,
int do_init)
{
ppc4xx_mmio_t *mmio;
qemu_irq *pic, *irqs;
ram_addr_t offset;
+ ppc4xx_pci_t *pci;
int i;
ppc_dcr_init(env, NULL, NULL);
@@ -44,6 +59,18 @@ void ppc440ep_init(CPUState *env,
for (i = 0; i < 2; i++)
offset += ram_sizes[i];
+ /* PCI */
+ pci = ppc4xx_pci_init(env, pic,
+ PPC440EP_PCI_CONFIG,
+ PPC440EP_PCI_INTACK,
+ PPC440EP_PCI_SPECIAL,
+ PPC440EP_PCI_REGS);
+ if (!pci)
+ printf("couldn't create PCI controller!\n");
+ *pcip = pci;
+
+ isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN);
+
/* serial ports on page 126 of 440EP user manual */
if (serial_hds[0]) {
printf("Initializing first serial port\n");
diff --git a/qemu/hw/ppc440.h b/qemu/hw/ppc440.h
--- a/qemu/hw/ppc440.h
+++ b/qemu/hw/ppc440.h
@@ -24,6 +24,7 @@ void ppc440ep_init(CPUState *env,
target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2],
qemu_irq **picp,
+ ppc4xx_pci_t **pcip,
int do_init);
#endif
diff --git a/qemu/hw/ppc440_bamboo.c b/qemu/hw/ppc440_bamboo.c
--- a/qemu/hw/ppc440_bamboo.c
+++ b/qemu/hw/ppc440_bamboo.c
@@ -9,6 +9,10 @@
*/
#include "config.h"
+#include "qemu-common.h"
+#include "net.h"
+#include "hw.h"
+#include "pci.h"
#include "ppc440.h"
#include "qemu-kvm.h"
#include "device_tree.h"
@@ -26,7 +30,9 @@ void bamboo_init(ram_addr_t ram_size, in
{
char *buf=NULL;
target_phys_addr_t ram_bases[4], ram_sizes[4];
+ NICInfo *nd;
qemu_irq *pic;
+ ppc4xx_pci_t *pci;
CPUState *env;
target_ulong ep=0;
target_ulong la=0;
@@ -77,7 +83,7 @@ void bamboo_init(ram_addr_t ram_size, in
/* call init */
printf("Calling function ppc440_init\n");
- ppc440ep_init(env, ram_bases, ram_sizes, &pic,1);
+ ppc440ep_init(env, ram_bases, ram_sizes, &pic, &pci, 1);
printf("Done calling ppc440_init\n");
/* Register mem */
@@ -171,6 +177,13 @@ void bamboo_init(ram_addr_t ram_size, in
kvm_load_registers(env);
}
+ for (i = 0; i < nb_nics; i++) {
+ nd = &nd_table[i];
+ if (!nd->model)
+ nd->model = "rtl8139";
+ pci_nic_init(pci->bus, nd, -1);
+ }
+
printf("%s: DONE\n", __func__);
}
diff --git a/qemu/hw/ppc4xx.h b/qemu/hw/ppc4xx.h
--- a/qemu/hw/ppc4xx.h
+++ b/qemu/hw/ppc4xx.h
@@ -46,4 +46,45 @@ qemu_irq *ppcuic_init (CPUState *env, qe
qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
uint32_t dcr_base, int has_ssr, int has_vr);
+
+struct pci_master_map {
+ uint32_t la;
+ uint32_t ma;
+ uint32_t pcila;
+ uint32_t pciha;
+};
+
+struct pci_target_map {
+ uint32_t ms;
+ uint32_t la;
+ uint32_t bar;
+};
+
+#define PPC44x_PCI_NR_PMMS 3
+#define PPC44x_PCI_NR_PTMS 2
+
+struct ppc4xx_pci_t {
+ target_phys_addr_t config_space;
+ target_phys_addr_t registers;
+ struct pci_master_map pmm[PPC44x_PCI_NR_PMMS];
+ struct pci_target_map ptm[PPC44x_PCI_NR_PTMS];
+
+ unsigned int pmm_offset_flags;
+ qemu_irq *pic;
+
+ uint32_t pcic0_cfgaddr;
+ PCIBus *bus;
+};
+typedef struct ppc4xx_pci_t ppc4xx_pci_t;
+
+ppc4xx_pci_t *ppc4xx_pci_init(CPUState *env, qemu_irq *pic,
+ target_phys_addr_t config_space,
+ target_phys_addr_t int_ack,
+ target_phys_addr_t special_cycle,
+ target_phys_addr_t registers);
+
+int ppc4xx_pci_config_outbound(ppc4xx_pci_t *pci, unsigned int region,
+ uint32_t plbaddr, uint32_t size_log,
+ uint64_t pcibase);
+
#endif /* !defined(PPC_4XX_H) */
diff --git a/qemu/hw/ppc4xx_devs.c b/qemu/hw/ppc4xx_devs.c
--- a/qemu/hw/ppc4xx_devs.c
+++ b/qemu/hw/ppc4xx_devs.c
@@ -25,6 +25,8 @@
#include "ppc.h"
#include "ppc4xx.h"
#include "sysemu.h"
+#include "pci.h"
+#include "bswap.h"
extern int loglevel;
extern FILE *logfile;
@@ -535,3 +537,370 @@ qemu_irq *ppcuic_init (CPUState *env, qe
return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
}
+
+
+
+
+#define PCIC0_CFGADDR 0x0
+#define PCIC0_CFGDATA 0x4
+
+#define PCIL0_PMM0LA 0x0
+#define PCIL0_PMM0MA 0x4
+#define PCIL0_PMM0PCILA 0x8
+#define PCIL0_PMM0PCIHA 0xc
+#define PCIL0_PMM1LA 0x10
+#define PCIL0_PMM1MA 0x14
+#define PCIL0_PMM1PCILA 0x18
+#define PCIL0_PMM1PCIHA 0x1c
+#define PCIL0_PMM2LA 0x20
+#define PCIL0_PMM2MA 0x24
+#define PCIL0_PMM2PCILA 0x28
+#define PCIL0_PMM2PCIHA 0x2c
+#define PCIL0_PTM1MS 0x30
+#define PCIL0_PTM1LA 0x34
+#define PCIL0_PTM2MS 0x38
+#define PCIL0_PTM2LA 0x3c
+#define PCI_REG_SIZE 0x40
+
+#define PPC44x_PCI_MA_MASK 0xfffff000
+#define PPC44x_PCI_MA_ENABLE 0x1
+
+
+static uint32_t pci4xx_cfgaddr_read4(void *opaque, target_phys_addr_t addr)
+{
+ ppc4xx_pci_t *ppc4xx_pci = opaque;
+ return cpu_to_le32(ppc4xx_pci->pcic0_cfgaddr);
+}
+
+static CPUReadMemoryFunc *pci4xx_cfgaddr_read[] = {
+ &pci4xx_cfgaddr_read4,
+ &pci4xx_cfgaddr_read4,
+ &pci4xx_cfgaddr_read4,
+};
+
+static void pci4xx_cfgaddr_write4(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+ ppc4xx_pci_t *ppc4xx_pci = opaque;
+
+ value = le32_to_cpu(value);
+
+ ppc4xx_pci->pcic0_cfgaddr = value & ~0x3;
+}
+
+static CPUWriteMemoryFunc *pci4xx_cfgaddr_write[] = {
+ &pci4xx_cfgaddr_write4,
+ &pci4xx_cfgaddr_write4,
+ &pci4xx_cfgaddr_write4,
+};
+
+static uint32_t pci4xx_cfgdata_read1(void *opaque, target_phys_addr_t addr)
+{
+ ppc4xx_pci_t *ppc4xx_pci = opaque;
+ int offset = addr & 0x3;
+ uint32_t cfgaddr = ppc4xx_pci->pcic0_cfgaddr;
+ uint32_t value;
+
+ if (!(cfgaddr & (1<<31)))
+ return 0xffffffff;
+
+ value = pci_data_read(ppc4xx_pci->bus, cfgaddr | offset, 1);
+
+ return value;
+}
+
+static uint32_t pci4xx_cfgdata_read2(void *opaque, target_phys_addr_t addr)
+{
+ ppc4xx_pci_t *ppc4xx_pci = opaque;
+ int offset = addr & 0x3;
+ uint32_t cfgaddr = ppc4xx_pci->pcic0_cfgaddr;
+ uint32_t value;
+
+ if (!(cfgaddr & (1<<31)))
+ return 0xffffffff;
+
+ value = pci_data_read(ppc4xx_pci->bus, cfgaddr | offset, 2);
+
+ return cpu_to_le16(value);
+}
+
+static uint32_t pci4xx_cfgdata_read4(void *opaque, target_phys_addr_t addr)
+{
+ ppc4xx_pci_t *ppc4xx_pci = opaque;
+ int offset = addr & 0x3;
+ uint32_t cfgaddr = ppc4xx_pci->pcic0_cfgaddr;
+ uint32_t value;
+
+ if (!(cfgaddr & (1<<31)))
+ return 0xffffffff;
+
+ value = pci_data_read(ppc4xx_pci->bus, cfgaddr | offset, 4);
+
+ return cpu_to_le32(value);
+}
+
+static CPUReadMemoryFunc *pci4xx_cfgdata_read[] = {
+ &pci4xx_cfgdata_read1,
+ &pci4xx_cfgdata_read2,
+ &pci4xx_cfgdata_read4,
+};
+
+static void pci4xx_cfgdata_write1(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+ ppc4xx_pci_t *ppc4xx_pci = opaque;
+ int offset = addr & 0x3;
+
+ pci_data_write(ppc4xx_pci->bus, ppc4xx_pci->pcic0_cfgaddr | offset,
+ value, 1);
+}
+
+static void pci4xx_cfgdata_write2(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+ ppc4xx_pci_t *ppc4xx_pci = opaque;
+ int offset = addr & 0x3;
+
+ value = le16_to_cpu(value);
+
+ pci_data_write(ppc4xx_pci->bus, ppc4xx_pci->pcic0_cfgaddr | offset,
+ value, 2);
+}
+
+static void pci4xx_cfgdata_write4(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+ ppc4xx_pci_t *ppc4xx_pci = opaque;
+ int offset = addr & 0x3;
+
+ value = le32_to_cpu(value);
+
+ pci_data_write(ppc4xx_pci->bus, ppc4xx_pci->pcic0_cfgaddr | offset,
+ value, 4);
+}
+
+static CPUWriteMemoryFunc *pci4xx_cfgdata_write[] = {
+ &pci4xx_cfgdata_write1,
+ &pci4xx_cfgdata_write2,
+ &pci4xx_cfgdata_write4,
+};
+
+static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+ struct ppc4xx_pci_t *pci = opaque;
+ unsigned long offset = addr - pci->registers;
+
+ value = le32_to_cpu(value);
+
+ switch (offset) {
+ case PCIL0_PMM0LA:
+ pci->pmm[0].la = value;
+ break;
+ case PCIL0_PMM1LA:
+ pci->pmm[0].la = value;
+ break;
+ case PCIL0_PMM2LA:
+ pci->pmm[0].la = value;
+ break;
+ default:
+ //printf(" unhandled PCI internal register 0x%lx\n", offset);
+ break;
+ }
+}
+
+static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr)
+{
+ struct ppc4xx_pci_t *pci = opaque;
+ unsigned long offset = addr - pci->registers;
+ uint32_t value;
+
+ switch (offset) {
+ case PCIL0_PMM0LA:
+ value = pci->pmm[0].la;
+ break;
+ case PCIL0_PMM0MA:
+ value = pci->pmm[0].ma;
+ break;
+ case PCIL0_PMM0PCIHA:
+ value = pci->pmm[0].pciha;
+ break;
+ case PCIL0_PMM0PCILA:
+ value = pci->pmm[0].pcila;
+ break;
+
+ case PCIL0_PMM1LA:
+ value = pci->pmm[1].la;
+ break;
+ case PCIL0_PMM1MA:
+ value = pci->pmm[1].ma;
+ break;
+ case PCIL0_PMM1PCIHA:
+ value = pci->pmm[1].pciha;
+ break;
+ case PCIL0_PMM1PCILA:
+ value = pci->pmm[1].pcila;
+ break;
+
+ case PCIL0_PMM2LA:
+ value = pci->pmm[2].la;
+ break;
+ case PCIL0_PMM2MA:
+ value = pci->pmm[2].ma;
+ break;
+ case PCIL0_PMM2PCIHA:
+ value = pci->pmm[2].pciha;
+ break;
+ case PCIL0_PMM2PCILA:
+ value = pci->pmm[2].pcila;
+ break;
+
+ case PCIL0_PTM1MS:
+ value = pci->ptm[0].ms;
+ break;
+ case PCIL0_PTM1LA:
+ value = pci->ptm[0].la;
+ break;
+ case PCIL0_PTM2MS:
+ value = pci->ptm[1].ms;
+ break;
+ case PCIL0_PTM2LA:
+ value = pci->ptm[1].la;
+ break;
+
+ default:
+ //printf(" read from invalid PCI internal register 0x%lx\n", offset);
+ value = 0;
+ }
+
+ value = cpu_to_le32(value);
+
+ return value;
+}
+
+static CPUReadMemoryFunc *pci_reg_read[] = {
+ &pci_reg_read4,
+ &pci_reg_read4,
+ &pci_reg_read4,
+};
+
+static CPUWriteMemoryFunc *pci_reg_write[] = {
+ &pci_reg_write4,
+ &pci_reg_write4,
+ &pci_reg_write4,
+};
+
+static uint32_t pci_int_ack_read4(void *opaque, target_phys_addr_t addr)
+{
+ printf("%s\n", __func__);
+ return 0;
+}
+
+static CPUReadMemoryFunc *pci_int_ack_read[] = {
+ &pci_int_ack_read4,
+ &pci_int_ack_read4,
+ &pci_int_ack_read4,
+};
+
+static void pci_special_write4(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+ printf("%s\n", __func__);
+}
+
+static CPUWriteMemoryFunc *pci_special_write[] = {
+ &pci_special_write4,
+ &pci_special_write4,
+ &pci_special_write4,
+};
+
+static int bamboo_pci_map_irq(PCIDevice *pci_dev, int irq_num)
+{
+ int slot = pci_dev->devfn >> 3;
+
+#if 0
+ /* All pins from each slot are tied to a single board IRQ (2-5) */
+ printf("### %s: devfn %x irq %d -> %d\n", __func__,
+ pci_dev->devfn, irq_num, slot+1);
+#endif
+
+ /* XXX re-examine */
+ return slot + 1;
+}
+
+static void bamboo_pci_set_irq(qemu_irq *pic, int irq_num, int level)
+{
+#if 0
+ printf("### %s: PCI irq %d, UIC irq %d\n", __func__, irq_num, 30 - irq_num);
+#endif
+
+ /* XXX re-examine */
+ qemu_set_irq(pic[30-irq_num], level);
+}
+
+/* XXX Needs some abstracting for boards other than Bamboo. */
+ppc4xx_pci_t *ppc4xx_pci_init(CPUState *env, qemu_irq *pic,
+ target_phys_addr_t config_space,
+ target_phys_addr_t int_ack,
+ target_phys_addr_t special_cycle,
+ target_phys_addr_t registers)
+{
+ ppc4xx_pci_t *pci;
+ PCIDevice *d;
+ int index;
+
+ pci = qemu_mallocz(sizeof(ppc4xx_pci_t));
+ if (!pci)
+ return NULL;
+
+ pci->config_space = config_space;
+ pci->registers = registers;
+ pci->pic = pic;
+
+ pci->bus = pci_register_bus(bamboo_pci_set_irq, bamboo_pci_map_irq,
+ pic, 0, 4);
+ d = pci_register_device(pci->bus, "host bridge", sizeof(PCIDevice),
+ 0, NULL, NULL);
+ d->config[0x00] = 0x14; // vendor_id
+ d->config[0x01] = 0x10;
+ d->config[0x02] = 0x7f; // device_id
+ d->config[0x03] = 0x02;
+ d->config[0x0a] = 0x80; // class_sub = other bridge type
+ d->config[0x0b] = 0x06; // class_base = PCI_bridge
+
+ /* CFGADDR */
+ index = cpu_register_io_memory(0, pci4xx_cfgaddr_read,
+ pci4xx_cfgaddr_write, pci);
+ if (index < 0)
+ goto free;
+ cpu_register_physical_memory(config_space, 4, index);
+
+ /* CFGDATA */
+ index = cpu_register_io_memory(0, pci4xx_cfgdata_read,
+ pci4xx_cfgdata_write, pci);
+ if (index < 0)
+ goto free;
+ cpu_register_physical_memory(config_space + 4, 4, index);
+
+ /* "Special cycle" and interrupt acknowledge */
+ index = cpu_register_io_memory(0, pci_int_ack_read,
+ pci_special_write, pci);
+ if (index < 0)
+ goto free;
+ cpu_register_physical_memory(int_ack, 4, index);
+
+ /* Internal registers */
+ index = cpu_register_io_memory(0, pci_reg_read, pci_reg_write, pci);
+ if (index < 0)
+ goto free;
+ cpu_register_physical_memory(registers, PCI_REG_SIZE, index);
+
+ /* XXX register_savevm() */
+
+ return pci;
+
+free:
+ printf("%s error\n", __func__);
+ qemu_free(pci);
+ return NULL;
+}
diff --git a/qemu/pc-bios/bamboo.dts b/qemu/pc-bios/bamboo.dts
--- a/qemu/pc-bios/bamboo.dts
+++ b/qemu/pc-bios/bamboo.dts
@@ -187,6 +187,45 @@
};
+ PCI0: pci@ec000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb440ep-pci", "ibm,plb-pci";
+ primary;
+ reg = <0 eec00000 8 /* Config space access */
+ 0 eed00000 4 /* IACK */
+ 0 eed00000 4 /* Special cycle */
+ 0 ef400000 40>; /* Internal registers */
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed. Chip supports a second
+ * IO range but we don't use it for now
+ */
+ ranges = <02000000 0 a0000000 0 a0000000 0 20000000
+ 01000000 0 00000000 0 e8000000 0 00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+ /* Bamboo has all 4 IRQ pins tied together per slot */
+ interrupt-map-mask = <f800 0 0 0>;
+ interrupt-map = <
+ /* IDSEL 1 */
+ 0800 0 0 0 &UIC0 1c 8
+
+ /* IDSEL 2 */
+ 1000 0 0 0 &UIC0 1b 8
+
+ /* IDSEL 3 */
+ 1800 0 0 0 &UIC0 1a 8
+
+ /* IDSEL 4 */
+ 2000 0 0 0 &UIC0 19 8
+ >;
+ };
+
};
chosen {
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^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [kvm-ppc-devel] [PATCH 4 of 4] [qemu ppc pci] Emulate the
2008-03-28 2:49 [kvm-ppc-devel] [PATCH 4 of 4] [qemu ppc pci] Emulate the Hollis Blanchard
@ 2008-03-28 9:10 ` Christian Ehrhardt
0 siblings, 0 replies; 2+ messages in thread
From: Christian Ehrhardt @ 2008-03-28 9:10 UTC (permalink / raw)
To: kvm-ppc
Hollis Blanchard wrote:
I always used a bamboo.dts -> dtb out of my kernel tree and used that one along time, so I never saw this issue.
I tried to convert this bamboo.dts file in qemu into a dtb file today and saw that it does not compile (nether with nor without that new patch, the patch only pointed me to that file).
paelzer@HeliosPrime ~/Desktop/KVM/ppc_port/kvm-userspace-vio/qemu/pc-bios $ dtc -I dts -O dtb -o bamboo.dtb2 bamboo.dts
DTC: dts->dtb on file "bamboo.dts"
bamboo.dts:20 syntax error
FATAL ERROR: Couldn't read input tree
Is this correct/expected atm or do we have to fix something here before this goes upstream ?
> diff --git a/qemu/pc-bios/bamboo.dts b/qemu/pc-bios/bamboo.dts
> --- a/qemu/pc-bios/bamboo.dts
> +++ b/qemu/pc-bios/bamboo.dts
> @@ -187,6 +187,45 @@
>
> };
>
> + PCI0: pci@ec000000 {
> + device_type = "pci";
> + #interrupt-cells = <1>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> + compatible = "ibm,plb440ep-pci", "ibm,plb-pci";
> + primary;
> + reg = <0 eec00000 8 /* Config space access */
> + 0 eed00000 4 /* IACK */
> + 0 eed00000 4 /* Special cycle */
> + 0 ef400000 40>; /* Internal registers */
> +
> + /* Outbound ranges, one memory and one IO,
> + * later cannot be changed. Chip supports a second
> + * IO range but we don't use it for now
> + */
> + ranges = <02000000 0 a0000000 0 a0000000 0 20000000
> + 01000000 0 00000000 0 e8000000 0 00010000>;
> +
> + /* Inbound 2GB range starting at 0 */
> + dma-ranges = <42000000 0 0 0 0 0 80000000>;
> +
> + /* Bamboo has all 4 IRQ pins tied together per slot */
> + interrupt-map-mask = <f800 0 0 0>;
> + interrupt-map = <
> + /* IDSEL 1 */
> + 0800 0 0 0 &UIC0 1c 8
> +
> + /* IDSEL 2 */
> + 1000 0 0 0 &UIC0 1b 8
> +
> + /* IDSEL 3 */
> + 1800 0 0 0 &UIC0 1a 8
> +
> + /* IDSEL 4 */
> + 2000 0 0 0 &UIC0 19 8
> + >;
> + };
> +
> };
>
> chosen {
>
> -------------------------------------------------------------------------
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--
Grüsse / regards,
Christian Ehrhardt
IBM Linux Technology Center, Open Virtualization
-------------------------------------------------------------------------
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2008-03-28 2:49 [kvm-ppc-devel] [PATCH 4 of 4] [qemu ppc pci] Emulate the Hollis Blanchard
2008-03-28 9:10 ` Christian Ehrhardt
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