From: cem@kernel.org <cem@kernel.org>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH V4 1/6] riscv: Add a wrapper to call sbi_ecall for base extension
Date: Wed, 13 Mar 2024 22:50:52 +0100 [thread overview]
Message-ID: <20240313215106.325766-2-cem@kernel.org> (raw)
In-Reply-To: <20240313215106.325766-1-cem@kernel.org>
From: Carlos Maiolino <cem@kernel.org>
All SBI extension functions accepts at most one argument, so create a
wrapper around sbi_ecall() to avoid needing to pass in arguments 1 to 5
all the time, also, the wrapper can specify SBI_EXT_BASE directly.
Signed-off-by: Carlos Maiolino <cmaiolino@redhat.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
V4:
- Remove stray blank line
V3:
- Move to the beginning of the series
- Don't mark __base_sbi_ecall() as inline
V2:
- This patch was introduced in V2
riscv/sbi.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/riscv/sbi.c b/riscv/sbi.c
index ffb07a25..76b72a80 100644
--- a/riscv/sbi.c
+++ b/riscv/sbi.c
@@ -14,6 +14,11 @@ static void help(void)
puts("An environ must be provided where expected values are given.\n");
}
+static struct sbiret __base_sbi_ecall(int fid, unsigned long arg0)
+{
+ return sbi_ecall(SBI_EXT_BASE, fid, arg0, 0, 0, 0, 0, 0);
+}
+
int main(int argc, char **argv)
{
struct sbiret ret;
@@ -32,7 +37,7 @@ int main(int argc, char **argv)
}
expected = strtol(getenv("MVENDORID"), NULL, 0);
- ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_MVENDORID, 0, 0, 0, 0, 0, 0);
+ ret = __base_sbi_ecall(SBI_EXT_BASE_GET_MVENDORID, 0);
report(!ret.error, "mvendorid: no error");
report(ret.value == expected, "mvendorid");
--
2.44.0
next prev parent reply other threads:[~2024-03-13 21:50 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-13 21:50 [PATCH V4 0/6] Add riscv tests to cover the base extension specs cem
2024-03-13 21:50 ` cem [this message]
2024-03-13 21:50 ` [PATCH V4 2/6] riscv: Add test to probe SBI Extension cem
2024-03-14 7:09 ` Andrew Jones
2024-03-13 21:50 ` [PATCH V4 3/6] riscv: Factor out environment variable check and report generation cem
2024-03-13 21:50 ` [PATCH 4/6] riscv: Implement test for architecture ID register cem
2024-03-13 21:50 ` [PATCH V4 5/6] riscv: Enable gen_report() to print the wrong value in case of failure cem
2024-03-14 8:45 ` Andrew Jones
2024-03-13 21:50 ` [PATCH V4 6/6] riscv: Test for specific SBI implementation ID cem
2024-03-14 7:13 ` Andrew Jones
2024-03-14 8:46 ` Andrew Jones
2024-03-14 8:59 ` Carlos Maiolino
2024-03-18 17:24 ` [PATCH V4 0/6] Add riscv tests to cover the base extension specs Andrew Jones
2024-03-18 17:27 ` Andrew Jones
2024-03-18 18:39 ` Carlos Maiolino
2024-03-18 19:37 ` Atish Patra
2024-03-19 7:38 ` Andrew Jones
2024-03-20 8:16 ` Carlos Maiolino
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