Re: [PATCH v3 2/5] KVM: nSVM: Disable LBRV in nested control cache when unsupported

[Shivansh Dhiman <shivansh.dhiman@amd.com>]

On 10-07-26 01:18, Yosry Ahmed wrote:
> On Thu, Jul 9, 2026 at 1:32 AM Shivansh Dhiman <shivansh.dhiman@amd.com> wrote:
>>
>> Clear SVM_MISC2_ENABLE_V_LBR in __nested_copy_vmcb_control_to_cache() when
>> the vCPU does not support LBR Virtualization. This lets the cached value be
>> consumed directly instead of re-checking X86_FEATURE_LBRV on every access.
>>
>> Suggested-by: Yosry Ahmed <yosry@kernel.org>
>> Signed-off-by: Shivansh Dhiman <shivansh.dhiman@amd.com>
>> ---
>> Changelog:
>> v3:
>>  * New patch.
>>  * Sanitize V_LBR in the cache and drop the redundant X86_FEATURE_LBRV
>>    checks (Yosry Ahmed).
>>
>> ---
>>  arch/x86/kvm/svm/nested.c | 9 ++++++---
>>  1 file changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c
>> index d3df6b22bfef..84248e6665cf 100644
>> --- a/arch/x86/kvm/svm/nested.c
>> +++ b/arch/x86/kvm/svm/nested.c
>> @@ -534,6 +534,11 @@ void __nested_copy_vmcb_control_to_cache(struct kvm_vcpu *vcpu,
>>         if (!gmet_enabled || !guest_cpu_cap_has(vcpu, X86_FEATURE_GMET))
>>                 to->misc_ctl &= ~SVM_MISC_ENABLE_GMET;
>>
>> +       /* Always clear misc_ctl2 bits that the guest cannot use */
> 
> I think the comment here is unnecessary, the comment above for
> misc_ctl should already make this clear.

[...]

> 
>> +       to->misc_ctl2 = from->misc_ctl2;
>> +       if (!lbrv || !guest_cpu_cap_has(vcpu, X86_FEATURE_LBRV))
> 
> Do we need to check lbrv here? KVM should not set X86_FEATURE_LBRV if
> lbrv=0 anyway, right?

Makes sense on both comments. I'll remove the comment and the !lbrv check
in next version.

> 
>> +               to->misc_ctl2 &= ~SVM_MISC2_ENABLE_V_LBR;
>> +
>>         to->iopm_base_pa        = from->iopm_base_pa & PAGE_MASK;
>>         to->msrpm_base_pa       = from->msrpm_base_pa & PAGE_MASK;
>>         to->tsc_offset          = from->tsc_offset;