Re: [PATCH v5 00/17] riscv: hwprobe: Expose RVA23U64 base behavior

[patchwork-bot+linux-riscv@kernel.org]

Hello:

This series was applied to riscv/linux.git (fixes)
by Paul Walmsley <pjw@kernel.org>:

On Wed, 01 Jul 2026 08:52:13 -0400 you wrote:
> This series builds on Andrew Jones's earlier RFC [1]. It lets userspace
> check for RVA23U64 conformance in one call, instead of walking hwprobe +
> prctl across every mandatory extension.
> 
> The series adds a small framework that resolves profile-class bases (IMA
> and RVA23U64) from the kernel's ISA extension bitmap at init time, and
> surfaces the result through both /proc/cpuinfo and hwprobe. Later patches
> can add RVA23S64, and backward RVA22 / RVA20 detection, to
> riscv_set_isa_bases() without changes to the surrounding code.
> 
> [...]

Here is the summary with links:
  - [v5,01/17] dt-bindings: riscv: sort multi-letter Z extensions alphanumerically
    https://git.kernel.org/riscv/c/e0776dde101a
  - [v5,02/17] riscv: hwprobe.rst: Make indentation consistent
    https://git.kernel.org/riscv/c/dbff3646369c
  - [v5,03/17] riscv: hwprobe.rst: Document EXT_ZICFISS and EXT_ZICFILP
    https://git.kernel.org/riscv/c/a914034334c4
  - [v5,04/17] riscv: Standardize extension capitalization
    (no matching commit)
  - [v5,05/17] riscv: Add Zicclsm to cpufeature and hwprobe
    (no matching commit)
  - [v5,06/17] riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to cpufeature and hwprobe
    (no matching commit)
  - [v5,07/17] riscv: Add B to hwcap and hwprobe
    (no matching commit)
  - [v5,08/17] dt-bindings: riscv: Require block-size for Zicbom, Zicbop, and Zicboz
    (no matching commit)
  - [v5,09/17] dt-bindings: riscv: Add Zic64b extension description
    (no matching commit)
  - [v5,10/17] riscv: Add Zic64b to cpufeature and hwprobe
    (no matching commit)
  - [v5,11/17] riscv: dts: spacemit: k3: Add Zic64b ISA extension
    (no matching commit)
  - [v5,12/17] riscv: dts: spacemit: k1: Add Zic64b ISA extension
    (no matching commit)
  - [v5,13/17] riscv: dts: sophgo: sg2044: Add Zic64b ISA extension
    (no matching commit)
  - [v5,14/17] riscv: Add a getter for user PMLEN support
    (no matching commit)
  - [v5,15/17] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection
    (no matching commit)
  - [v5,16/17] riscv: cpu: Output isa bases lines in cpuinfo
    (no matching commit)
  - [v5,17/17] riscv: hwprobe: Introduce rva23u64 base behavior
    (no matching commit)

You are awesome, thank you!
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