From: Arbel Moshe <arbel.moshe@oracle.com>
To: pbonzini@redhat.com, rkrcmar@redhat.com, kvm@vger.kernel.org
Cc: jmattson@google.com, wanpeng.li@hotmail.com,
idan.brown@oracle.com, liran.alon@oracle.com
Subject: [PATCH v2 0/3] KVM: nVMX: Do not expose APICv to L1 if disabled on L0
Date: Wed, 22 Nov 2017 12:23:37 +0200 [thread overview]
Message-ID: <20171122102340.7110-1-arbel.moshe@oracle.com> (raw)
Hi,
This series aims to fix issue of exposing APICv features to L1 when
enable_apicv==false in L0.
The first patch is just a refactoring of existing code. It replaces updating of
VMX APICv related secondary exec controls, in generic secondary exec control
re-computation. This is done to avoid code-duplication which is error-prone.
The second patch makes sure that if APICv is disabled dynamically when Hyper-V
SynIC is enabled, then also make sure to not expose APICv features to L1 in VMX
MSRs.
The third patch fix a bug of exposing some APICv related features to L1 even
though APICv is disabled in L0.
Regards,
-Arbel Moshe
next reply other threads:[~2017-11-22 10:24 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-22 10:23 Arbel Moshe [this message]
2017-11-22 10:23 ` [PATCH v2 1/3] KVM: nVMX: Refresh APICv secondary exec controls by re-calculating all of them Arbel Moshe
2017-11-22 17:17 ` Jim Mattson
2017-11-22 18:08 ` Jim Mattson
2017-11-23 23:51 ` Paolo Bonzini
2017-11-22 10:23 ` [PATCH v2 2/3] KVM: nVMX: Update nested MSRs in case APICv refreshing Arbel Moshe
2017-11-22 18:04 ` Jim Mattson
2017-11-23 23:54 ` Paolo Bonzini
2017-11-22 10:23 ` [PATCH v2 3/3] KVM: nVMX: Fix nested APICv Secondary CPU Controls when apicv disabled Arbel Moshe
2017-11-22 17:56 ` Jim Mattson
2017-11-23 23:57 ` Paolo Bonzini
2017-11-27 17:14 ` Jim Mattson
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