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From: Arbel Moshe <arbel.moshe@oracle.com>
To: pbonzini@redhat.com, rkrcmar@redhat.com, kvm@vger.kernel.org
Cc: jmattson@google.com, wanpeng.li@hotmail.com,
	idan.brown@oracle.com, liran.alon@oracle.com,
	Arbel Moshe <arbel.moshe@oracle.com>,
	Krish Sadhukhan <krish.sadhukhan@oracle.com>
Subject: [PATCH v2 1/3] KVM: nVMX: Refresh APICv secondary exec controls by re-calculating all of them
Date: Wed, 22 Nov 2017 12:23:38 +0200	[thread overview]
Message-ID: <20171122102340.7110-2-arbel.moshe@oracle.com> (raw)
In-Reply-To: <20171122102340.7110-1-arbel.moshe@oracle.com>

Handle apicv secondary exec ctrls correctly, without duplicating
logic.
This commit doesn't change semantics.

Signed-off-by: Arbel Moshe <arbel.moshe@oracle.com>
Reviewed-by: Liran Alon <liran.alon@oracle.com>
Reviewed-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
---
 arch/x86/kvm/vmx.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 7c3522a989d0..84ccd3b2762c 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -5237,20 +5237,18 @@ static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
 	return pin_based_exec_ctrl;
 }
 
+static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx);
+
 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
 {
 	struct vcpu_vmx *vmx = to_vmx(vcpu);
 
 	vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
+
 	if (cpu_has_secondary_exec_ctrls()) {
-		if (kvm_vcpu_apicv_active(vcpu))
-			vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
-				      SECONDARY_EXEC_APIC_REGISTER_VIRT |
-				      SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
-		else
-			vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
-					SECONDARY_EXEC_APIC_REGISTER_VIRT |
-					SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
+		vmx_compute_secondary_exec_control(vmx);
+		vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
+				vmx->secondary_exec_control);
 	}
 
 	if (cpu_has_vmx_msr_bitmap())
-- 
2.14.1

  reply	other threads:[~2017-11-22 10:24 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-22 10:23 [PATCH v2 0/3] KVM: nVMX: Do not expose APICv to L1 if disabled on L0 Arbel Moshe
2017-11-22 10:23 ` Arbel Moshe [this message]
2017-11-22 17:17   ` [PATCH v2 1/3] KVM: nVMX: Refresh APICv secondary exec controls by re-calculating all of them Jim Mattson
2017-11-22 18:08     ` Jim Mattson
2017-11-23 23:51     ` Paolo Bonzini
2017-11-22 10:23 ` [PATCH v2 2/3] KVM: nVMX: Update nested MSRs in case APICv refreshing Arbel Moshe
2017-11-22 18:04   ` Jim Mattson
2017-11-23 23:54     ` Paolo Bonzini
2017-11-22 10:23 ` [PATCH v2 3/3] KVM: nVMX: Fix nested APICv Secondary CPU Controls when apicv disabled Arbel Moshe
2017-11-22 17:56   ` Jim Mattson
2017-11-23 23:57     ` Paolo Bonzini
2017-11-27 17:14       ` Jim Mattson

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