From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: kvm@vger.kernel.org,
"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Huacai Chen" <chenhuacai@kernel.org>
Subject: [PATCH v2 21/24] target/mips: Extract LSA/DLSA translation generators
Date: Tue, 15 Dec 2020 23:57:54 +0100 [thread overview]
Message-ID: <20201215225757.764263-22-f4bug@amsat.org> (raw)
In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org>
Extract gen_lsa() from translate.c and explode it as
gen_LSA() and gen_DLSA().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.h | 6 ++++
target/mips/translate.c | 35 +++-----------------
target/mips/translate_addr_const.c | 52 ++++++++++++++++++++++++++++++
target/mips/meson.build | 1 +
4 files changed, 63 insertions(+), 31 deletions(-)
create mode 100644 target/mips/translate_addr_const.c
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 8d84e0c254d..47129de81d9 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -128,6 +128,12 @@ void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
int get_fp_bit(int cc);
+/*
+ * Address Computation and Large Constant Instructions
+ */
+bool gen_LSA(DisasContext *ctx, int rd, int rt, int rs, int sa);
+bool gen_DLSA(DisasContext *ctx, int rd, int rt, int rs, int sa);
+
extern TCGv cpu_gpr[32], cpu_PC;
extern TCGv_i32 fpu_fcr0, fpu_fcr31;
extern TCGv_i64 fpu_f64[32];
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2ce3dc10dfb..e0439ba92d8 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6616,31 +6616,6 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
tcg_temp_free(t0);
}
-static void gen_lsa(DisasContext *ctx, int opc, int rd, int rs, int rt,
- int imm2)
-{
- TCGv t0;
- TCGv t1;
- if (rd == 0) {
- /* Treat as NOP. */
- return;
- }
- t0 = tcg_temp_new();
- t1 = tcg_temp_new();
- gen_load_gpr(t0, rs);
- gen_load_gpr(t1, rt);
- tcg_gen_shli_tl(t0, t0, imm2 + 1);
- tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
- if (opc == OPC_LSA) {
- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
- }
-
- tcg_temp_free(t1);
- tcg_temp_free(t0);
-
- return;
-}
-
static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs,
int rt, int bits)
{
@@ -16496,8 +16471,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
return;
case LSA:
check_insn(ctx, ISA_MIPS32R6);
- gen_lsa(ctx, OPC_LSA, rd, rs, rt,
- extract32(ctx->opcode, 9, 2));
+ gen_LSA(ctx, rd, rs, rt, extract32(ctx->opcode, 9, 2));
break;
case ALIGN:
check_insn(ctx, ISA_MIPS32R6);
@@ -21460,8 +21434,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
* amount, meaning that the supported shift values are in
* the range 0 to 3 (instead of 1 to 4 in MIPSR6).
*/
- gen_lsa(ctx, OPC_LSA, rd, rs, rt,
- extract32(ctx->opcode, 9, 2) - 1);
+ gen_LSA(ctx, rd, rs, rt, extract32(ctx->opcode, 9, 2) - 1);
break;
case NM_EXTW:
gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5));
@@ -24347,7 +24320,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL(ctx->opcode);
switch (op1) {
case OPC_LSA:
- gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2));
+ gen_LSA(ctx, rd, rs, rt, extract32(ctx->opcode, 6, 2));
break;
case OPC_MULT:
case OPC_MULTU:
@@ -24401,7 +24374,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
#if defined(TARGET_MIPS64)
case OPC_DLSA:
check_mips_64(ctx);
- gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2));
+ gen_DLSA(ctx, rd, rs, rt, extract32(ctx->opcode, 6, 2));
break;
case R6_OPC_DCLO:
case R6_OPC_DCLZ:
diff --git a/target/mips/translate_addr_const.c b/target/mips/translate_addr_const.c
new file mode 100644
index 00000000000..84662933d49
--- /dev/null
+++ b/target/mips/translate_addr_const.c
@@ -0,0 +1,52 @@
+/*
+ * Address Computation and Large Constant Instructions
+ */
+#include "qemu/osdep.h"
+#include "tcg/tcg-op.h"
+#include "translate.h"
+
+bool gen_LSA(DisasContext *ctx, int rd, int rt, int rs, int sa)
+{
+ TCGv t0;
+ TCGv t1;
+
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return true;
+ }
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+ tcg_gen_shli_tl(t0, t0, sa + 1);
+ tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
+ tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
+
+ tcg_temp_free(t1);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+bool gen_DLSA(DisasContext *ctx, int rd, int rt, int rs, int sa)
+{
+ TCGv t0;
+ TCGv t1;
+
+ check_mips_64(ctx);
+
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return true;
+ }
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+ tcg_gen_shli_tl(t0, t0, sa + 1);
+ tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
+ tcg_temp_free(t1);
+ tcg_temp_free(t0);
+
+ return true;
+}
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 5ccc9ddc6b8..dce0ca96527 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -16,6 +16,7 @@
'mod-msa_helper.c',
'tlb_helper.c',
'translate.c',
+ 'translate_addr_const.c',
'mod-msa_translate.c',
))
mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
--
2.26.2
next prev parent reply other threads:[~2020-12-15 23:01 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-15 22:57 [PATCH v2 00/24] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 01/24] target/mips/translate: Extract decode_opc_legacy() from decode_opc() Philippe Mathieu-Daudé
2020-12-15 23:23 ` Richard Henderson
2020-12-15 22:57 ` [PATCH v2 02/24] target/mips/translate: Expose check_mips_64() to 32-bit mode Philippe Mathieu-Daudé
2021-01-06 18:20 ` Philippe Mathieu-Daudé
2021-01-06 18:37 ` Philippe Mathieu-Daudé
2021-01-07 3:56 ` Jiaxun Yang
2020-12-15 22:57 ` [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper Philippe Mathieu-Daudé
2020-12-15 23:27 ` Richard Henderson
2020-12-15 23:48 ` Philippe Mathieu-Daudé
2020-12-16 2:50 ` Jiaxun Yang
2020-12-16 3:14 ` Jiaxun Yang
2020-12-16 10:50 ` Philippe Mathieu-Daudé
2020-12-16 10:59 ` Philippe Mathieu-Daudé
2020-12-16 11:30 ` Jiaxun Yang
2020-12-16 11:36 ` Jiaxun Yang
2021-01-07 9:04 ` Philippe Mathieu-Daudé
2021-01-07 13:17 ` Philippe Mathieu-Daudé
2020-12-16 10:55 ` Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 04/24] target/mips: Introduce ase_msa_available() helper Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 05/24] target/mips: Simplify msa_reset() Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 06/24] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 07/24] target/mips: Simplify MSA TCG logic Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 08/24] target/mips: Remove now unused ASE_MSA definition Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 09/24] target/mips: Alias MSA vector registers on FPU scalar registers Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 10/24] target/mips: Extract msa_translate_init() from mips_tcg_init() Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 11/24] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 12/24] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 13/24] target/mips: Rename msa_helper.c as mod-msa_helper.c Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 14/24] target/mips: Move msa_reset() to mod-msa_helper.c Philippe Mathieu-Daudé
2020-12-15 23:09 ` Richard Henderson
2020-12-15 22:57 ` [PATCH v2 15/24] target/mips: Extract MSA helpers from op_helper.c Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 16/24] target/mips: Extract MSA helper definitions Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 17/24] target/mips: Declare gen_msa/_branch() in 'translate.h' Philippe Mathieu-Daudé
2020-12-15 23:10 ` Richard Henderson
2020-12-15 22:57 ` [PATCH v2 19/24] target/mips: Introduce decode tree bindings for MSA opcodes Philippe Mathieu-Daudé
2020-12-15 23:11 ` Richard Henderson
2020-12-15 22:57 ` [PATCH v2 20/24] target/mips: Use decode_ase_msa() generated from decodetree Philippe Mathieu-Daudé
2020-12-15 23:15 ` Richard Henderson
2020-12-15 22:57 ` Philippe Mathieu-Daudé [this message]
2020-12-15 23:17 ` [PATCH v2 21/24] target/mips: Extract LSA/DLSA translation generators Richard Henderson
2020-12-15 22:57 ` [PATCH v2 22/24] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes Philippe Mathieu-Daudé
2020-12-15 23:19 ` Richard Henderson
2020-12-15 22:57 ` [PATCH v2 23/24] target/mips: Introduce decodetree helpers for Release6 " Philippe Mathieu-Daudé
2020-12-15 23:21 ` Richard Henderson
2020-12-15 22:57 ` [RFC PATCH v2 24/24] target/mips/mod-msa: Pass TCGCond argument to gen_check_zero_element() Philippe Mathieu-Daudé
2020-12-15 23:22 ` Richard Henderson
2021-01-07 18:29 ` [PATCH v2 00/24] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20201215225757.764263-22-f4bug@amsat.org \
--to=f4bug@amsat.org \
--cc=aleksandar.rikalo@syrmia.com \
--cc=aurelien@aurel32.net \
--cc=chenhuacai@kernel.org \
--cc=jiaxun.yang@flygoat.com \
--cc=kvm@vger.kernel.org \
--cc=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox